Reconfigurable Three-Phase SPWM Implementation On De2 Fpga: Ahmed Belkheiri, Said Aoughellanet, Mohammed BELKHEIRI
Reconfigurable Three-Phase SPWM Implementation On De2 Fpga: Ahmed Belkheiri, Said Aoughellanet, Mohammed BELKHEIRI
Streszczenie. W artykule opisano implementację zmodyfikowanej techniki modulacji sinusoidalnej PWM dla trójfazowych zasilaczy AC o
regulowanym napięciu i częstotliwości. W badaniach wykorzystano platformę DE2 z układem FPGA Cyclone II firmy Altera. Wyniki symulacyjne i
eksperymentalne potwierdzają skuteczność działania i redukcję wykorzystania zasobów układu. (Implementacja rekonfigurowalnej, trójfazowej
techniki SPWM na platformie DE2 z FPGA).
U t
(1) M 2U
2 Tc
The intersections of (Va -Vo)w with rising M at t1, such as
U Tc
(2) t1 Va V0 w
2 2U
Determine the points at which K’1 is turned on and
hence the start of the periods where (Va –Vo) equals –U/2.
3U t
M 2U
(3)
2 Tc
The intersections of (Va-Vo)w with falling M at t2, such a
Fig.2 SPWM technique; PWM high pulse and low pulse; output
voltage
3U T
t2 Va V0 w c
(4) 2 2U Specifications
The three phase SPWM unit is designed to generate six
Determine the points at which K1 is turned on and output pulses (two signals per phase) adjusted in both index
hence the start of the periods where Va –Vo equal +U/2. If modulation, carrier modulating sine frequency with 0:5Hz
fc is much greater than fr , voltage Va –Vo remains almost step (highest possible resolution), but with a phase angle
constant during a cycle Tc of carrier wave, the examination 120o_ between pairs, and an appropriate delay time must
of fig. 1.b easily shows that the average value of Va –Vo, in be inserted between each two complementary
this cycle is pulses(PWM_H and PWM_L) to prevent short circuit
problem and power converter breakdown.
1U
(Va V0 ) av
Tc 2
Tc t2 t1 The proposed SPWM architecture
(5) The block diagram of the proposed architecture is
Replacing t1 and t1 by their values, we get shown in Fig. 3. The data inputs are three 8-bit data word,
the first (frequency_ref) refer to the modulating wave
(Va V0 ) av (Va V0 ) w frequency the second (Amplitude_ref) refer to the
(6) modulation index ma, and the last corresponding to the
frequency carrier, so it can be easily interfaced to a FPGA
So if the reference varies sinusoidally, the average value of development DE2 board (IO port pins). The top module
(Va -Vo) varies in the same way. The aim is to approximate shown in fig. 3 is divided into sub-modules:
sinusoidal output voltages by sinusoidally varying their Three identical modules to generate three sine waves
0
average values. The basic idea to produce SPWM shifted between them with 120 , which are used as
switching signals consists to compare between the sine modulating signals, each signal is generated by using an 8
reference signal Vr and the triangular carrier signal Vc, bit free running counter point to the memory that contains a
which is clearly illustrated in Fig.2. If the reference is 256 samples of a the sine wave, that represented as 8 bit
sinusoidal, two parameters characterize the modulation [9]: signed fractional format (-1 to + 1 of amplitude).
The modulation index or regulation factor ma; this is the
ratio of the amplitude of the reference to the peak value
of the carrier wave :
Vr
ma
(7)
Vc
The frequency modulation index mf ; this is the ratio between
the carrier and reference frequencies:
fc
mf
(8)
fr
Since the turn-off time of power devices is usually longer
than its turn-on time, and therefore, an appropriate delay
time named (dead-time) must be inserted between these
two gating signals of the two complementary switches to
avoid the short circuit. The length of this delay time is
usually about 1.5 to 2 times the maximum turn-off time [10]. Fig.3 Block diagram of SPWM Strategy