Data Concentrator Cape For Beaglebone Black: Ti Designs
Data Concentrator Cape For Beaglebone Black: Ti Designs
Data Concentrator Cape For Beaglebone Black: Ti Designs
UART
D89
TRS3386ECPWR
RF SOM2
CC2543EM
5V
TPS61093
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
1 System Description
2 Design Features
3 Block Diagram
UART
D89
TRS3386ECPWR
RF SOM2
CC2543EM
5V
TPS61093
4 Highlighted Products
For more information on each of the devices in Section 4, see the respective product folders at
www.tI.com. See also the links for Product Folders in Design Resources.
Two 23 x 2 connectors are used to interface the DC-cape to the BeagleBone Black board. Figure 1 shows the interface connector. The signals not
used by DC-Cape are shown as X (not connected on the DC-Cape).
P1 P2
1 2 DGND 1 2 DGND
3 4 VDD_3V3EXP 3 4 VDD_3V3EXP
5 6 VDD_5V 5 6 VDD_5V
7 8 SYS_5V 7 8 SYS_5V
6 9 10 9 10
TIMER5 TIMER6 7
6 11 12 6 11 12 2,8
GPIO1_13 GPIO1_12 7 UART4_RXD GPIO1_28
13 14 7 6 13 14
GPIO0_26 UART4_TXD
7 15 16 7 6 15 16 2,8
GPIO1_15 GPIO1_14 GPIO1_16 GPIO1_17
7 17 18 3 17 18
GPIO0_27 GPIO2_1
19 20 2,8 19 20 2,8
I2C2_SCL I2C2_SDA
21 22 3 21 22 3
UART2_TXD UART2_RXD
23 24 23 24 8
UART1_TXD
25 26 GPIO1_29 3 25 26
UART1_RXD 8
27 28 27 28 6
SPI1_CS0
29 30 6,7 SPI1_D0 29 30 6,7
SPI1_D1
31 32 6,7 31 32
SPI1_SCLK
33 34 33 34
35 36 35 36
37 38 37 38
39 40 39 40
41 42 41 42
43 44 43 44
45 46 45 46
NOTE: A single phase zero cross output is shown in Figure 2. In the DC-Cape , there are three zero cross detectors for three phases.
3V3_EVM
R215 270
C102
0.1uF
LINE_AC_C R6 100K R5 100K R4 100K Q2
24 LINE_AC_C
BC817-40LT1G
DGND
4
LINE_AC_N
ISO2
FOD817BSD 3V3_EVM
R213 D7 U41
3
D6 240K BZV55 C103 R214 0 1 6
DL4148-TP 2 In1 In2 5
3 GND VCC 4
.1uF ZERO_PLC_C 26
In0 Y
R216 SN74LVC1G57DBVR
1.5K 5 % DGND C266
24,25,48 LINE_AC_N
0.1uF
DGND
DGND
2
1
LINE_N_F
25,48 LINE_AC_A
P1
JP3
HDR_2_P1_INCH 1
C5
2
2
1
JP20 L16 15uH
1 2 LINE_AC_A_CON 3
.47uF 400v(ECQ-E4474KF 1 L17 600nH
2 1 2 4
3
HEADER 3 5
JP5
HDR_2_P1_INCH 1777574
25 LINE_AC_B
2
1
2
1
JP21 L14 15uH
8 LINE_COMB
1
1 2 LINE_AC_B_CON CURRENT AND VOLTAGE
3 .47uF 400v(ECQ-E4474KF L15 600nH
2 2 1 2
MARKINGS
7 LINE_N_F 3
HEADER 3
4
5 6
WURTH_750510476 25 LINE_AC_C
GND_AC_PWR
JP2
HDR_2_P1_INCH
C2
2
1
JP22 L12 15uH
1 2 LINE_AC_C_CON
SD PART# 103531-0001R .47uF 400v(ECQ-E4474KF 1 L13 600nH
2 1 2
3
HEADER 3
PL_TXRX
PL_TXRX 26
R17
4.7
D10
SM6T7V5CA
C25
2200PF 250V
GND_AC_PWR
GND_AC_PWR
This design supports single-phase and three-phase power-line communication. To use power-line
communication, connect each phase input and neutral to the power-line communication system as shown
in Table 3. The earth ground input is not connected to any components on the board and can be left
unconnected.
CAUTION
CAUTION
Electric shock possible when connecting board to live wire. Board should
be handled with care by a professional. For safety, use of isolated test
equipment with overvoltage and overcurrent protection is highly recommended.
Table 4 shows the characteristics of a PLC transformer 750510476 designed for PLC modems using TI
Analog Front-End PLC. For more details, refer to PLC Transformer for Texas Instruments AFE030 /
AFE031 / AFE032
SOMPLC-F28M35 Features
• Support for ARIB frequency band
• Supports G3 and IEEE-1901.2 PLC industry standards
• Comprehensive two-chip solution with MCU and AFE032-integrated analog front-end
• 34-pin mini header provides flexibility for interfacing to custom board and other TI Designs like the PLC Data Concentrator and TMDSPLCKIT-
V4
Figure 4 shows the SOMPLC-F28M35 interface.
JP23 JP24
HDR_2_P1_INCH HDR_2_P1_INCH
1
2
1
2
P3
GND_AC_PWR
1 1
P1 ON CC MODULES P2
P5 ON SMART GRID BOARD P6 VDD_3V3EXP
+
R30 NO-POP TP3 C6 C7
R31 NO-POP TP-20RD10 0.1UF 10UF
TP4
TP-20RD10
TP5
TP-20RD10 DGND
P5 P6
1 2 1 2
2 R32 0 CC1_P0.4 3 4 CC1_P1.3 3 4 R33 0
GPIO1_12
2 R34 0 CC1_P0.1 5 6 CC1_P1.0 5 6 R35 0
GPIO0_26
2 R36 0 CC1_P0.2 7 8 R37 0 7 8
UART4_TXD
2 R38 0 CC1_P0.3 9 10 CC1_P2.1 R39 0 2 9 10
UART4_RXD GPIO1_16
CC1_P0.0 11 12 CC1_P2.2 R40 0 11 12 DGND
CC1_P1.1 13 14 CC1_P1.4 R41 0 13 14
CC1_P0.6 15 16 CC1_P1.5 R42 0 2 GPIO1_17 GPIO1_17 R43 0 RESET_CC1 15 16
TP6 CC1_P0.7 17 18 CC1_P1.6 R44 0 17 18 CC1_P0.5 R45 0 2
GPIO1_28
TP-20RD10 19 20 CC1_P1.7 R46 0 2 GPIO1_13 R47 0 CC1_P2.0 19 20
TP7
TP-20RD10 HEADER 10X2 HEADER 10X2
TP8
TP-20RD10
TP9 DGND
TP-20RD10
TIMER5 2
TIMER5
SPI1_CS0_A
VDD_3V3EXP
SPI1_SCLK 2,7
SPI1_SCLK
SPI1_D0 2,7
SPI1_D0
SPI1_D1 SPI1_D1 2,7
R48 R49
10K 10K
JP6
1 SPI1_CS0_A
2 SPI1_CS0 2
3 SPI1_CS0_B
CON3
VDD_3V3EXP
VDD_3V3EXP
R68
0 C10
0.1uF
DGND
R69 VDD_3V3EXP U4
NO-POP TRS3386ECPWR
1 19 VDD_3V3EXP
C12 C1+ VCC
0.1uF 2 C13 0.1uF
DGND 3 V+
C1- 6 C14 0.1uF C15
R70 R71 V-
2.2K 2.2K 4 0.1uF
C11 C2+ 18
0.1uF GND DGND
5 12 DGND
C2- VL DGND
UART1_TXD_RS232 7 17 RSA_TXD P9
DIN1 DOUT1
UART1_RTSN 8 16 RSA_RTS 1
2 I2C2_SCL DIN2 DOUT2 6
9 15 RSA_RXD 2 10
DIN3 DOUT3 RSA_RTS 7
RSA_TXD 3
DGND RSA_CTS 8
20 4 11
PWRDOWN 9
5
PWR_PAD
10uF 5 7
EN FB R80
6 1 294K C21
SS GND 0.01uF
C22 C23
DGND DGND DGND R81 C24 10uF 100uF
11
200K 1uF TPS61093DSK DGND
R82
10.2K DGND DGND
DGND
DGND
6 Software Description
6.1 U-Boot
The U-boot on AM335x uses a two-stage approach. The size of the internal RAM in AM335X is 128 KB.
Of the 128 KB, 18 KB at the end is used by the ROM code. Also, 1 KB at the start (0x402f0000 -
0x402f0400) is secure, and cannot be accessed. The reserved RAM places a limit of 109 KB on the size
of the U-Boot binary which the ROM code can transfer to the internal RAM and use as an initial stack
before initialization of DRAM.
Since it is not possible to squeeze in all the functionality that is normally expected from a U-Boot in less
than 110KB (after setting aside some space for stack, heap, and so forth), a two-stage approach has been
adopted. The first stage initializes only the required boot devices (NAND, MMC, I2C, and so forth. The
second full stage installs all other devices (ethernet, timers, clocks, and so forth).
NOTE: In the rest of this document when referring to the binaries, the binary for the first stage is
referred to as SPL and the binary for the second stage is called U-Boot.
6.1.1.1 Prerequisite
Verify that SDK 6.00 is installed on the host computer. GNU toolchain for the ARM processor from Arago
is recommended to build U-Boot. Arago toolchain can be found in the linux-devkit directory of the SDK. If
not already done, add this compiler to the path by executing the following code.
$ export PATH="<SDK install dir>/linux-devkit/sysroots/i686-arago-linux/usr/bin : $PATH"
6.1.1.3 Compile
Below are instructions on how to generate binaries for the memory or peripheral devices. Building into a
separate object directory with the "O=" parameter is strongly recommended.
6.1.1.3.1 UART
Execute the following code.
$ [ -d ./am335x ] && rm -rf ./am335x
$ make O=am335x CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm am335x_evm
6.1.1.3.2 NAND
Execute the following code.
$ [ -d ./am335x ] && rm -rf ./am335x
$ make O=am335x CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm am335x_evm
6.1.1.3.3 SPI
Execute the following code.
$ [ -d ./am335x ] && rm -rf ./am335x
$ make O=am335x CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm am335x_evm_spiboot
6.2 Kernel
This section will cover the basic steps for building the Linux kernel and drive modules.
6.2.1.1 Prerequisite
Verify that SDK 6.00 is installed on the host computer. GNU toolchain for the ARM processor from Arago
is recommended to build the kernel. Arago toolchain can be found in the linux-devkit directory of the SDK.
If not already done, add this compiler to the path by executing the following code.
$ export PATH="<sdk install dir>>/linux-devkit/sysroots/i686-arago-linux/usr/bin/:$PATH"
NOTE: The next step will delete any saved .config file in the kernel tree as well as the generated
object files. If a previous configuration has already been created, save a copy of the
configuration file before proceeding in order to prevent the loss of the configuration file.
6.2.1.5 Compile
Once the kernel has been configured, it must be compiled to generate the bootable kernel image, as well
as any dynamic kernel modules that were selected.
Build the kernel image. The resulting kernel image file will be located in the arch/arm/boot directory called
uImage.
$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- uImage
Build the dynamic modules. This will result in .ko (kernel object) files being placed in the kernel tree.
These .ko files are the dynamic kernel modules.
$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- modules
6.3.1.2 SD Boot
SD Boot boots from the uSD slot. SD Boot can be used to override what is on the eMMC device. SD Boot
can be used to program the eMMC when used in the manufacturing process or for filed updates.
6.3.3.1 Dynamic IP
Run the dhcp command to obtain the IP address from the DHCP server on the network which the EVM is
connected to.
U-Boot# setenv serverip <tftp server in the network>
U-Boot# dhcp
U-Boot# saveenv
7 Test Data
• Hardware set
– Tx: DC board
– 15-V Power Supply
– Used WE transformer
• Software set
1. Prime version 7.9.1.0 software tested at the single phase meter and Prime version 3.5.0.0 tested at
the DC side
2. G3 version 7.0.1.2 software tested at the single phase meter and GE version 4.0.0.1 tested at the
DC side
• EVM at room temperature
– 18-dB EVM achieved
– Uncoded D8PSK received without any errors
110 120
Average Average
100 Quasi-peak 110 Quasi-peak
CENELEC mask (quasi-peak) 100 CENELEC mask (quasi-peak)
90 CENELEC mask (average) CENELEC mask (average)
90
80
Level (dBuV)
Level (dBuV)
80
70
70
60
60
50
50
40 40
30 30
20 20
150 250 350 450 550 650 150 200 250 300 350 400 450 500 550 600 650 700 750
Frequency (Hz) D001
Frequency (Hz) D002
Figure 8. CENELEC Mask (PRIME) External Power Figure 9. CENELEC Mask (PRIME) Onboard Power
Supply Supply
Level (dBuV)
80 80
70 70
60 60
50 50
40 40
30 30
20 20
150 250 350 450 550 650 750 150 250 350 450 550 650 750
Frequency (Hz) D003
Frequency (Hz) D004
Figure 10. CENELEC Mask (G3) External Power Supply Figure 11. CENELEC Mask (G3) Onboard Power Supply
120 1x100
Quasi-peak measurments DBP SK
110 Quasi-peak ARIB mask DQP SK
-1
100 1x10 D8P SK
90
1x10-2
Level (dBuV)
80
BER
70 1x10-3
60
50 1x10-4
40
1x10-5
30
20 1x10-6
0.0097 0.2097 0.4097 0.6097 0.8097 1 0 2 4 6 8 10 12
Frequency (Hz) D005 SNR (dB) D006
Figure 12. Conducted Emission For ARIB (G3) Figure 13. BER Measurements
8 Design Files
8.1 Schematics
To download the Schematics, see the design files at TIDA-00225.
P1 P2
1 2 DGND 1 2 DGND
3 4 VDD_3V3EXP 3 4 VDD_3V3EXP
5 6 VDD_5V 5 6 VDD_5V
7 8 SYS_5V 7 8 SYS_5V
6 9 10 9 10
TIMER5 TIMER6
6 11 12 6 6 11 12 6
GPIO1_13 GPIO1_12 UART4_RXD GPIO1_28
13 14 6 6 13 14
GPIO0_26 UART4_TXD
15 16 6 15 16 6
GPIO1_15 GPIO1_14 GPIO1_16 GPIO1_17
17 18 3 17 18
GPIO0_27 GPIO2_1
19 20 2,7 19 20 2,7
I2C2_SCL I2C2_SDA
21 22 3 21 22 3
UART2_TXD UART2_RXD
23 24 23 24 7
UART1_TXD
25 26 GPIO1_29 3 25 26 7
UART1_RXD
27 28 27 28 6
SPI1_CS0
29 30 6 SPI1_D0 29 30 6
SPI1_D1
31 32 6 31 32
SPI1_SCLK
33 34 33 34
35 36 35 36
37 38 37 38
39 40 39 40
41 42 41 42
43 44 43 44
45 46 45 46
C210
0.1uF
DS1 DS2 DS3
14
VDD_3V3EXP
DGND LED GRN LED GRN LED GRN
U23A
GPIO1_14 2 3 L138_LED1
SN74LV125APWR
1.5K,5%
1.5K,5%
4.75K,5%
4.75K,5%
4.75K,5%
1
7
Expansion Board EEPROM U24B
R3
R4
R5
R6
R7
DGND
GPIO1_15 5 6 L138_LED2
VDD_3V3EXP
U1 SN74LV125APWR
2,7 6 8
I2C2_SCL
4
5 SCL VCC
2,7 I2C2_SDA SDA
SW1 C1
4 0.1uf,16V
1 VSS DGND
2 A0
3 A1 7 WP U24C
A2 WP R8 10K,1%,NO-POP DGND GPIO0_27 9 8 L138_LED3
SW DIP-2 CAT24C256W
SN74LV125APWR
DGND 256KX8
10
DGND
PLC_3V3
R262
10K JP23 JP24
HDR_2_P1_INCH HDR_2_P1_INCH
PLC_RESET
1
2
1
2
R264
P3
NO-POP
VDD_5V
GND_AC_PWR
R263
NO-POP
R258 R256
150 150
DGND
D12 D13
Green LED Green LED
EVM_15V PLC_15V
R18 0
Q4 D Q5 D
G G VDD_3V3EXP PLC_3V3
S S
DGND DGND
PLC_LED2
R257 R170
100K 100K
DGND DGND
5 LINE_AC_N
JP2
HDR_2_P1_INCH
2
1
LINE_N_F
5 LINE_AC_A
P4
JP3
HDR_2_P1_INCH 1
C2
2
2
1
JP20 L16 15uH
1 2 LINE_AC_A_CON 3
.47uF 400v(ECQ-E4474KF 1 L17 600nH
2 1 2 4
3
HEADER 3 5
JP1
HDR_2_P1_INCH 1777574
5 LINE_AC_B
2
1
2
1
JP21 L14 15uH
8 LINE_COMB
1
1 2 LINE_AC_B_CON CURRENT AND VOLTAGE
3 .47uF 400v(ECQ-E4474KF L15 600nH
2 2 1 2 MARKINGS
7 LINE_N_F 3
HEADER 3
4
5 6
WURTH_750510476 5 LINE_AC_C
GND_AC_PWR
JP5
HDR_2_P1_INCH
C4
2
1
JP22 L12 15uH
1 2 LINE_AC_C_CON
SD PART# 103531-0001R .47uF 400v(ECQ-E4474KF 1 L13 600nH
2 1 2
3
HEADER 3
PL_TXRX 3
PL_TXRX
R20
4.7
D1
SM6T7V5CA
C5
2200PF 250V
TP1 TP2
GND_AC_PWR
DGND
GND_AC_PWR
VDD_3V3EXP
R222 270
C108
0.1uF
4 LINE_AC_A R269 100K R12 100K R267 100K Q3
LINE_AC_A
BC817-40LT1G
DGND
4
LINE_AC_N
ISO3
FOD817BSD VDD_3V3EXP
R217 D9 U39
3
D8 240K BZV55 C109 R218 0 1 6
DL4148-TP 2 In1 In2 5
3 GND VCC 4
.1uF ZERO_PLC_A 3
In0 Y
SN74LVC1G57DBVR
4,5 R223 DGND C264
LINE_AC_N
1.5K 5 % 0.1uF
DGND
DGND
VDD_3V3EXP
R211 270
C100
0.1uF
4 LINE_AC_B R265 100K R2 100K R1 100K Q1
LINE_AC_B
BC817-40LT1G
DGND
4
LINE_AC_N
ISO1
FOD817BSD VDD_3V3EXP
R209 D2 U40
3
D14 240K BZV55 C101 R210 0 1 6
DL4148-TP 2 In1 In2 5
3 GND VCC 4
.1uF ZERO_PLC_B 3
In0 Y
R212 SN74LVC1G57DBVR
4,5 1.5K 5 % DGND C265
LINE_AC_N
0.1uF
DGND
DGND
VDD_3V3EXP
R215 270
C102
0.1uF
4 LINE_AC_C R268 100K R270 100K R266 100K Q2
LINE_AC_C
BC817-40LT1G
DGND
4
LINE_AC_N
ISO2
FOD817BSD VDD_3V3EXP
R213 D7 U41
3
D6 240K BZV55 C103 R214 0 1 6
DL4148-TP 2 In1 In2 5
3 GND VCC 4
.1uF ZERO_PLC_C 3
In0 Y
R216 SN74LVC1G57DBVR
4,5 1.5K 5 % DGND C266
LINE_AC_N
0.1uF
DGND
DGND
NOTE: DIMENSIONS AND LOCATIONS OF THESE CONNECTORS MUST MEET SPECIFICATION FOR INTERFACE MODULES
REFERENCE CC2530EMK USER GUIDE (SWRU208) OR SMART GRID EVM DESIGN FILES
Connector P/N: TFM-110-02-SM-D-A-K-TR (Samtec)
1 1
P1 ON CC MODULES P2
P5 ON SMART GRID BOARD P6 VDD_3V3EXP
+
R30 NO-POP TP3 C6 C7
R31 NO-POP TP-20RD10 0.1UF 10UF
TP4
TP-20RD10
TP5
TP-20RD10 DGND
P5 P6
1 2 1 2
2 R32 0 CC1_P0.4 3 4 CC1_P1.3 3 4 R33 0
GPIO1_12
2 R34 0 CC1_P0.1 5 6 CC1_P1.0 5 6 R35 0
GPIO0_26
2 R36 0 CC1_P0.2 7 8 R37 0 7 8
UART4_TXD
2 R38 0 CC1_P0.3 9 10 CC1_P2.1 R39 0 2 9 10
UART4_RXD GPIO1_16
CC1_P0.0 11 12 CC1_P2.2 R40 0 11 12 DGND
CC1_P1.1 13 14 CC1_P1.4 R41 0 13 14
CC1_P0.6 15 16 CC1_P1.5 R42 0 2 GPIO1_17 GPIO1_17 R43 0 RESET_CC1 15 16
TP6 CC1_P0.7 17 18 CC1_P1.6 R44 0 17 18 CC1_P0.5 R45 0 2
GPIO1_28
TP-20RD10 19 20 CC1_P1.7 R46 0 2 GPIO1_13 R47 0 CC1_P2.0 19 20
TP7
TP-20RD10 HEADER 10X2 HEADER 10X2
TP8
TP-20RD10
TP9 DGND
TP-20RD10
TIMER5 2
TIMER5
SPI1_CS0_A
VDD_3V3EXP
SPI1_SCLK 2
SPI1_SCLK
SPI1_D0 2
SPI1_D0
SPI1_D1 SPI1_D1 2
R48 R49
10K 10K
JP6
1 SPI1_CS0_A
2 SPI1_CS0 2
3 SPI1_CS0_B
CON3
VDD_3V3EXP
VDD_3V3EXP
R68
0 C10
0.1uF
DGND
R69 VDD_3V3EXP U4
NO-POP TRS3386ECPWR
1 19 VDD_3V3EXP
C12 C1+ VCC
0.1uF 2 C13 0.1uF
DGND 3 V+
C1- 6 C14 0.1uF C15
R70 R71 V-
2.2K 2.2K 4 0.1uF
C11 C2+ 18
0.1uF GND DGND
5 12 DGND
C2- VL DGND
UART1_TXD_RS232 7 17 RSA_TXD P9
DIN1 DOUT1
UART1_RTSN 8 16 RSA_RTS 1
2 I2C2_SCL DIN2 DOUT2 6
9 15 RSA_RXD 2 10
DIN3 DOUT3 RSA_RTS 7
RSA_TXD 3
DGND RSA_CTS 8
20 4 11
PWRDOWN 9
5
VDD_3V3EXP
R72 R73
10K 10K
JP7
1 UART1_TXD_RS232
2 UART1_TXD 2
3 UART1_TXD_PLC UART1_TXD_PLC3
CON3
VDD_3V3EXP
R74 R75
10K 10K
JP8
1 UART1_RXD_RS232
2 2
UART1_RXD 3 UART1_RXD_PLC
UART1_RXD_PLC 3
CON3
L1 10uH
PWR_PAD
10uF 5 7
EN FB R80
6 1 294K C21
SS GND 0.01uF
C22 C23
DGND DGND DGND R81 C24 10uF 100uF
11
200K 1uF TPS61093DSK DGND
R82
10.2K DGND DGND
DGND
DGND
2 MTG4
DGND
1 1
MTG5 MTG6
1 1
MTG7 MTG8
1 1
MTG9 MTG10
Figure 21. Layer 1 Primary Side Figure 22. Layer 2 Ground Plane 1
Figure 25. Primary Side Soldermask Figure 26. Primary Side Silkscreen
Figure 27. Secondary Side Soldermask Figure 28. Primary Side Solder Stencil
Figure 29. Secondary Side Silkscreen Figure 30. Secondary Side Solder Stencil
9 References
1. Beagleboard:BeagleBoneBlack (Link: BeagleBone Black)
2. Smart Data Concentrator EVM (TMDSDC3359) Hardware Manual - Key Features (Link:
TMDSDC3359)
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