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Compression Assignment

This document discusses concepts related to scan compression techniques for testing integrated circuits, including definitions of compression, decompression architectures, and masking. It asks questions about determining compression ratios, the impacts of high ratios, and use of clocks and control signals. Additionally, it addresses reasons for increased test patterns with compression, deciding on EDT channel counts, pipeline stages, and differences between basic and Xpress compactors.

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senthilkumar
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178 views

Compression Assignment

This document discusses concepts related to scan compression techniques for testing integrated circuits, including definitions of compression, decompression architectures, and masking. It asks questions about determining compression ratios, the impacts of high ratios, and use of clocks and control signals. Additionally, it addresses reasons for increased test patterns with compression, deciding on EDT channel counts, pipeline stages, and differences between basic and Xpress compactors.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSIGURU DFT TRAINING SCAN INSERTION ASSIGNMENT

COMPRESSION ASSIGNMENT
1. What is compression?
2. Why need compression?
3. Explain compression architecture with decompressor and compactor?
4. Write internal diagram of Decompressor?
5. Define compression ratio? How do you decide compression ratio?
6. What is X-Masking? Why we need X-masking?
7. If keep on increasing compression ratio, what is the impact?
8. Why need decoding logic?
9. Importance of EDT_CLOCK,EDT_UPDATE and EDT_BYPASS
10. Write waveform in terms of edt_clk, scan_clk, edt_update, scan_enable

Part-2
1. What is the reason for increase in pattern count for compressed mode?
2. How to decide EDT channel count?
3. Use of Pipeline Stages Between Pads and Channel Inputs or Outputs?
4. What is the difference between Basic Compactor and Xpress Compactor?

VLSIGuru Confidential 1

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