Exercises for

Active Loads & IC MOS Amplifiers

ECE 102, Fall 2012, F. Najmabadi

 Exercise 1: Compute the voltage gain of the circuit below.

Signal

g m1 (ro1 || ro 2 )
Av =
1 + g m1 (ro1 || ro 2 )

Q1 is a source follower CD Fundamental

and Q2 is its active load Configuration

F. Najmabadi, ECE102, Fall 2012 (2/18)

 Exercise 2: Compute the voltage gain of the circuit below.

Q1 is a CS Amp
Q2/Q3 are the active load

Av = − g m1 (ro1 || RL′ )
RL′ Need to Find R’L

Signal

F. Najmabadi, ECE102, Fall 2012 (3/18)

 ro
R = ro

R = ro (1 +g m R) + R R = ro (1 +g m R) + R
= ro +g m ro R + R
= ro + (1 +g m ro ) R

Resistor in the source circuit (R )

is increased by the factor (1 + gmro)

ro +R ro R Resistor in the drain circuit (R )

= + is reduced by the factor (1 + gmro)
1 + g m ro 1 + g m ro 1 + g m ro
 Finding R’L

RL′
RL′ = ro 2 (1 + g m 2 ro 3 ) + ro 3

RL′ = ro 2 (1 + g m 2 ro 3 ) + ro 3
≈ ro 2 g m 2 ro 3 + ro 3 = ro 3 (1 + g m 2 ro 2 )
≈ g m 2 ro 2 ro 3
Av = − g m1 (ro1 || g m 2 ro 2 ro 3 )

Typically : g m 2 ro 2 ro 3 >> ro1 ⇒ Av ≈ − g m1ro1

 Providing a large active load (e.g., a cascode load) for a CS amplifier

does not increase the gain drastically (only by a factor of two)
F. Najmabadi, ECE102, Fall 2012 (5/18)
 Exercise 3: Compute the Bias point details of transistors in the circuit below
with µnCox = 200 µA/V2, µpCox = 65 µA/V2, (W/L) = 10, Vtp = − 0.6 V, Vtn
= 0.6 V, VAp = − 10 V, VAn = 20 V:
A) Ignore channel-length modulation
B) Include channel-length modulation and set the DC voltage at VG2 = 0.77 V.

λ p = 1 / | VAp | = 0.1 V -1
λn = 1 / VAn = 0.05 V -1

VSG1 = VDD − VG1 = 3 − 2.1 = 0.9 V

VOV 1 = VSG1 − | Vtp |= 0.9 − 0.6 = 0.3 V

F. Najmabadi, ECE102, Fall 2012 (6/18)

 A) Ignore channel-length modulation
µnCox = 200 µA/V2, µpCox = 65 µA/V2, (W/L) = 10, Vtn = 0.6 V

VOV 1 = 0.3 V
W 2
I D1 = 0.5µ p Cox VOV 1 = 0.5 × 65 × 10 −6 × 10 × (0.3) 2
L
I D1 = 29.3 µA

I D 2 = I D1 = 29.3 µA

W 2
I D 2 = 0.5µ n Cox VOV 2 = 0.5 × 200 × 10 −6 × 10 × VOV
2
2
L
VOV 2 = 0.171 V

VGS 2 = VOV 2 + Vtn = 0.171 + 0.6 = 0.771 V

VG 2 = VGS 2 + VS 2 = 0.771 V
F. Najmabadi, ECE102, Fall 2012 (7/18)
 B) Include channel-length modulation and set the DC voltage at VG2 = 0.77 V
µnCox = 200 µA/V2, µpCox = 65 µA/V2, (W/L) = 10,
Vtp = − 0.6 V, Vtn = 0.6 V, λp = 0.1 V-1 , λn = 0.05 V-1

VOV 1 = 0.3 V
VGS 2 = VG 2 = 0.77 V
VOV 2 = 0.17 V
W 2
I D1 = 0.5µ p Cox VOV 1 (1 + λ pVSD1 )
L
W 2
I D2 = 0.5µ n Cox VOV 2 (1 + λnVDS 2 )
L
I D1 = I D 2
W 2 W 2
0.5µ p Cox VOV 1 (1 + λ pVSD1 ) = 0.5µ n Cox VOV 2 (1 + λnVDS 2 )
L L
65 × 10 −6 (0.3) 2 (1 + 0.1VSD1 ) = 200 × 10 −6 (0.17) 2 (1 + 0.05VDS 2 )
1 + 0.1VSD1 = 0.988 + 0.049VDS 2
F. Najmabadi, ECE102, Fall 2012 (8/18)
 1 + 0.1VSD1 = 0.988 + 0.049VDS 2

− VSD1 + 0.49VDS 2 − 0.12 = 0

KVL: VSD1 + VDS 2 = 3

VSD1 = 1.07 V
VDS 2 = 1.93 V

W 2
I D1 = 0.5µ p Cox VOV 1 (1 + λ pVSD1 )
L
= 0.5 × 65 × 10 −6 × 10 × (0.3) 2 (1 + 0.05 × 1.07)
I D1 = (29.3 µA) × (1.035) = 30.3µA
I D 2 = 30.3µA

F. Najmabadi, ECE102, Fall 2012 (9/18)

 Ignore channel-length
Include channel-length modulation
modulation

VOV 1 = 0.3 V 0.3 V 0.3 V 0.3 V Specified

I D1 = I D 2 = 29.3 µA 30.3 µA 31.3 µA 32.3 µA parameters
VGS 2 = VG 2 = 0.771 V 0.770 V 0.780 V 0.800 V
VSD1 = ? 1.07 V 2 V −−
VDS 2 = ? 1.93 V 1V −−
Q2 in triode!

 Ignoring channel-length modulation gives relatively accurate results for ID

and VOV (thus, gm and ro)
o But we cannot find VDS
 In reality (including channel-length modulation), VG2 is also specified.
o We find unique values for VDS
o Precise biasing of VG2 (DC value of vi ) is required.

F. Najmabadi, ECE102, Fall 2012 (10/18)

 Exercise 4: Design the circuit below for a gain of 20 and a power budget of 3 mW.
Assume transistors have the same Vov with µnCox = 100 µA/V2, µpCox = 50
µA/V2, (W/L)3 = 20/0.18, λp = 0.2 V−1, λn = 0.1 V−1, and Vtn = 0.4 V.
Ignore channel-length modulation in biasing calculations.
(Design: Find (W/L) of all transistors, Iref , and VG3 )

 This is a CS amplifier (Q3) with an active load

(Q2) biased with a current mirror (Q1 & Q2)

RL = ro 2
Av = − g m 3 (ro 3 || RL ) = − g m 3 (ro 3 || ro 2 )
Also : I D 3 = I D 2

F. Najmabadi, ECE102, Fall 2012 (11/18)

 2I D3 1 1 1 λ3
g m3 = ro 3 = ro 2 = = ⇒ ro 2 = ro 3
VOV 3 λ3 I D 3 λ 2 I D 2 λ2 I D 3 λ2

ro 3 × ro 2 ro 3 × (λ3 / λ2 )ro 3 (λ3 / λ2 )

ro 3 || ro 2 = = = × ro 3
ro 3 + ro 2 ro 3 + (λ3 / λ2 )ro 3 (λ3 / λ2 ) + 1

Note the only active load

(λ3 / λ2 )
Av = − g m 3 (ro 3 || ro 2 ) = − g m 3 ro 3 × transistor parameter that
(λ3 / λ2 ) + 1 enters the gain formula is λ2

(λ3 / λ2 ) 2I 1 (λ3 / λ2 ) 2 (λ3 / λ2 )

Av = − g m 3 ro 3 × = − D3 × × =− ×
(λ3 / λ2 ) + 1 VOV 3 λ3 I D 3 (λ3 / λ2 ) + 1 λ3VOV 3 (λ3 / λ2 ) + 1
The relevant parameters of
transistor amplifier are λ & VOV

λ3 λ p 2 2
= = 2 → ro 2 = 2ro 3 20 = × ⇒ VOV 3 = 0.33 V
λ2 λn 0.1VOV 3 3
F. Najmabadi, ECE102, Fall 2012 (12/18)
 VOV 1 = VOV 2 = VOV 3 = 0.33 V

VGS 3 = VOV 3 + Vtn = 0.33 + 0.4 = 0.73 V

VG 3 = VGS 3 + VS 3 = 0.73 V

W  2 20
I D3 = 0.5µ n Cox   VOV 3 = 0.5 × 100 × 10 ×
−6
× (0.33) 2
 L 3 0.18

I D 3 = 617 µA I D 2 = I D 3 = 617 µA

W  2 W  2
I D 2 = 0.5µ p Cox   VOV 2 = 0 . 5 µ n ox 
C  VOV 3 = I D 3
 L 2  L 3
W  W 
50 ×   = 100 ×  
 L 2  L 3
W  W  40
  = 2 ×   =
 2
L  L  3 0.18
F. Najmabadi, ECE102, Fall 2012 (13/18)
 I D 3 = 617 µA

I D 2 = I D 3 = 617 µA

W  W  40
  = 2×  =
 L 2  L  3 0.18

Current Mirror:
P = 1.8 ( I D 3 + I ref ) = 3 × 10 -3 W
I D 3 + I ref = 1.11× 10 -3 I ref
=
(W / L)1
I D2 (W / L) 2
I ref = 616 µA
616 × 10 −6 (W / L)1
−6
=
617 × 10 (W / L) 2

W  W  40
  =  =
 L 1  L  2 0.18
F. Najmabadi, ECE102, Fall 2012 (14/18)
 Exercise 5: Design the common gate stage of the circuit below for a gain of 20
and an input impedance of 150 Ω for (W/L)3 = 40/0.18 and ID5 = ID2 = 2 Iref
Assume Q1 and Q2 have the same VOV , µnCox = 100 µA/V2, λp = 0.2 V-1,
and λn = 0.1 V-1.
Ignore channel-length modulation in biasing calculations.
(Design: Find W/L of all transistors and Iref )

F. Najmabadi, ECE102, Fall 2012 (15/18)

 4) Q4 is the reference leg
of Q3-Q4 current mirror 2) Q3 is the active load
for the CG amplifier as
well as for biasing

Signal

1) Q1 is a CG amplifier

3) Q2 provides the current

source which is necessary
in the source circuit for
biasing Q1
6) Qref is the primary
transistor for all current 5) Q5 provides the
steering circuits reference current for the
Q3-Q4 current mirror

F. Najmabadi, ECE102, Fall 2012 (16/18)

 Gain = 20

2 I D1 1 1 1
g m1 = ro1 = ro 3 = =
VOV 1 λ1 I D1 λ3 I D 3 λ3 I D1

λ3
ro1 = ro 3 = 2ro 3
λ1

(λ3 / λ1 ) 2
ro1 || ro 3 = × ro1 = × ro1
(λ3 / λ1 ) + 1 3

2 2 2
Av ≈ g m1 (ro1 || ro 3 ) = × g m1ro1 = ×
3 3 λ1VOV 1

2 2
20 = × ⇒ VOV 1 = 0.33 V
3 0.1VOV 1

F. Najmabadi, ECE102, Fall 2012 (17/18)

 Input Resistance = 150 Ω
Ri = RQ 2 || RCG
RQ 2 = ro 2
ro1 + ro 3 ro1 (1 + ro 3 / ro1 ) 1 + ro 3 / ro1 3
RCG = ≈ = =
1 + g m1ro1 g m1ro1 g m1 g m1
3 RCG
RCG << RQ 2 ⇒ Ri = RQ 2 || RCG ≈ RCG =
g m1 RQ2
Ri
3
150 = ⇒ g m1 = 20 mA/V
g m1
−3
2 I D1 20 × 10
g m1 = = 20 ×10 −3 ⇒ I D1 = = 3 mA
VOV 1 2 × 0.33
W  2 W 
3 × 10 −3
= I D1 = 0.5µ n Cox   VOV 1 = 0.5 × 100 × 10 ×   × (0.33) 2
−6

 L 1  L 1
W  99
  = 551 =
 L 1 0.18
F. Najmabadi, ECE102, Fall 2012 (18/18)
 W  99 W  40
  = &   =
 L 1 0.18  L  3 0.18

I D 3 = I D 2 = I D1 = 3 mA
I D 4 = I D 5 = I D 2 = 3 mA
I ref = 0.5 I D 5 = 1.5 mA

W  W  99
I D 2 = I D1 ⇒   =   =
 L  2  L 1 0.18 Q1 and Q2 have the same Vov

I D 4 (W / L) 4 W  W  40
= ⇒   =  =
I D 3 (W / L) 3  L  4  L  3 0.18
I ref (W / L) ref W  W  50
= ⇒   = 0.5 ×   = Current Mirrors
I D2 (W / L) 2  L  ref  L  2 0.18
I ref (W / L) ref W  W  99
= ⇒   = 2×  =
I D5 (W / L) 5  L 5  L  ref 0.18
F. Najmabadi, ECE102, Fall 2012 (19/18)