What is the difference between VHDL and Verilog?

Fundamentally speaking, not a lot. You can produce robust designs and comprehensive test environments with
both langauges, for both ASIC and FPGA. However, the two langauges approach the task from different directions;
VHDL, intended as a specification langauge, is very exact in its nature and hence very verbose. Verilog, intended as a
simulation langauge, it much closer to C in style, in that it is terse and elegant to write but requires much more care to
avoid nasty bugs. VHDL doesn't let you get away with much; Verilog assumes that whatever you wrote was exactlywhat
you intended to write. If you get a VHDL architecture to compile, it's probably going to approximate to the function you
wanted. For Verilog, successful compilation merely indicates that the syntax rules were met, nothing more. VHDL has
some features that make it good for system-level modelling, whereas Verilog is much better than VHDL at gate-level
simulation.

What is Synthesis?
Synthesis is the stage in the design flow which is concerned with translating your VHDL code into gates - and that's
putting it very simply! First of all, the VHDL must be written in a particular way for the target technology that you are
using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have
synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

How many versions of VHDL are there?

There are four. The original release of the VHDL language occured in 1987 with the adoption of the Language
Reference Manual as an IEEE standard. In 1993, the IEEE-1076 standard was modified and ratified and became known
as VHDL'93. This is now widely supported. In 2000, the VHDL 1076 2000 Edition appeared - this fixed shared variables
by introducing the idea of protected types. Finally, VHDL 1076-2002 appeared. This includes protected mode types, but
also changes ports of mode buffer to make them more usable, along with some other small changes. In practise, VHDL
1076-1993 is the current flavour of VHDL which is widely supported by tool vendors.

What is VHDL?

VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated
Circuit. It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to
describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as
conventional digital circuits.
VHDL is a notation, and is precisely and completely defined by the Language Reference Manual ( LRM ). This sets
VHDL apart from other hardware description languages, which are to some extent defined in an ad hoc way by the
behaviour of tools that use them. VHDL is an international standard, regulated by the IEEE. The definition of the
language is non-proprietary.
VHDL is not an information model, a database schema, a simulator, a toolset or a methodology! However, a
methodology and a toolset are essential for the effective use of VHDL.
Simulation and synthesis are the two main kinds of tools which operate on the VHDL language. The Language
Reference Manual does not define a simulator, but unambiguously defines what each simulator must do with each part
of the language.
VHDL does not constrain the user to one style of description. VHDL allows designs to be described using any
methodology - top down, bottom up or middle out! VHDL can be used to describe hardware at the gate level or in a
more abstract way. Successful high level design requires a language, a tool set and a suitable methodology. VHDL is
the language, you choose the tools, and the methodology... well, I guess that's where Doulos come in to the equation!

What is Verilog?
Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems.
Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test
analysis (testability analysis and fault grading) and for logic synthesis.
Difference between vhdl and verilog
1. Verilog is based on C, while VHDL is based on Pascal and Ada.
2. Unlike Verilog, VHDL is strongly typed.
3. Ulike VHDL, Verilog is case sensitive.
4. Verilog is easier to learn compared to VHDL.
5. Verilog has very simple data types, while VHDL allows users to create
more complex data types.
6. Verilog lacks the library management, like that of VHDL.

Data types
VHDL. A multitude of language or user defined data types can be
used. This may mean dedicated conversion functions are needed
to convert objects from one type to another. The choice of which
data types to use should be considered wisely, especially
enumerated (abstract) data types. This will make models easier to
write, clearer to read and avoid unnecessary conversion functions
that can clutter the code. VHDL may be preferred because it
allows a multitude of language or user defined data types to be
used.
Verilog. Compared to VHDL, Verilog data types are very simple,
easy to use and very much geared towards modeling hardware
structure as opposed to abstract hardware modeling. Unlike
VHDL, all data types used in a Verilog model are defined by the
Verilog language and not by the user. There are net data types,
for example wire, and a register data type called reg. A model
with a signal whose type is one of the net data types has a
corresponding electrical wire in the implied modeled circuit.
Objects, that is signals, of type reg hold their value over
simulation delta cycles and should not be confused with the
modeling of a hardware register. Verilog may be preferred
because of it's simplicity.
Design reusability
VHDL. Procedures and functions may be placed in a package so
that they are avail able to any design-unit that wishes to use
them.
Verilog. There is no concept of packages in Verilog. Functions and
procedures used within a model must be defined in the module.
To make functions and procedures generally accessible from
different module statements the functions and procedures must
be placed in a separate system file and included using the
`include compiler directive.
Easiest to Learn
Starting with zero knowledge of either language, Verilog is
probably the easiest to grasp and understand.

Libraries
VHDL. A library is a store for compiled entities, architectures, packages and

configurations. Useful for managing multiple design projects.

Verilog. There is no concept of a library in Verilog. This is due to it's origins as

an interpretive language.

Operators
The majority of operators are the same between the two

languages. Verilog does have very useful unary reduction

operators that are not in VHDL. A loop statement can be used in

VHDL to perform the same operation as a Verilog unary reduction

operator. VHDL has the mod operator that is not found in Verilog.

Procedures and tasks

VHDL allows concurrent procedure calls; Verilog does not allow

concurrent task calls.

Verboseness
VHDL. Because VHDL is a very strongly typed language models

must be coded precisely with defined and matching data types.

This may be considered an advantage or disadvantage. However,

it does mean models are often more verbose, and the code often

longer, than it's Verilog equivalent.

 Verilog. Signals representing objects of different bits widths may be assigned to
each other. The signal representing the smaller number of bits is automatically
padded out to that of the larger number of bits, and is independent of whether it is
the assigned signal or not. Unused bits will be automatically optimized away
during the synthesis process. This has the advantage of not needing to model quite
so explicitly as in VHDL, but does mean unintended modeling errors will not be
identified by an analyzer.
Difference between c program and vhdl program?

C is a high level language that is compiled into machine language for specific system.
The system implements some sort of state machine that can process the compiled machine
language.

In VHDL you have to design the statemachine itself. Furthermore VHDL is compiled into logic
primitives that could be built by logic gates which itself could be realized with transistors.

C is a programming language.
VHDL is a hardware description language.

Element Test and Maintenance (ASIC test

ETM:
interface)

CLB:Configurable Logic Block (cf. FPGAs)

Design rule checking

Design Rule Checking or Check(s) (DRC) is the area of Electronic Design Automation that
determines whether the physical layout of a particular chip layout satisfies a series of recommended
parameters called Design Rules. Design rule checking is a major step duringPhysical
verification signoff on the design, which also involves LVS (Layout versus schematic) Check, XOR Checks,
ERC (Electrical Rule Check) and Antenna Checks. For advanced processes some fabs also insist upon the
use of more restricted rules to improve yield.
ERC (Electrical rule check)
ERC (Electrical rule check) involves checking a design for all electrical connections that are
considered dangerous. This might include checking for

well and substrate areas for proper contacts and spacings thereby ensuring correct power
and ground connections
unconnected inputs or shorted outputs.
gates connected directly to supplies

ERC checks are based upon assumptions about the normal operating conditions
of the ASIC, so they may give many false warning on ASICs with multiple or negative
supplies. They can also check for structures susceptible to ESD damage

UNIVERSAL GATES

3 universal gates are: NAND, NOR and Fredkin gate.

The basic Fredkin gate is a controlled swap gate that maps three inputs (C, I1, I2) onto
three outputs (C, O1, O2). The C input is mapped directly to the C output. If C = 0, no
swap is performed; I1 maps to O1, and I2 maps to O2. Otherwise, the two outputs are
swapped so that I1 maps to O2, and I2 maps to O1.

why are NAND and NOR gates called universal gates?

All other gates/functions can be implemented by NOR or NAND gates. so they are called
universal gates. In fact, in chips, entire logic maybe built using only NAND (or NOR) gates. eg:
inverter-- nand with inputs shorted. and ------ nand followed by a inverter(using nand). or---------
giving inverted inputs to nand gate. If you delve deep into realms of VLSI you maybe able to
understand the reason .Implementing with NAND is easier when considering power and area of
the chip.
LIBRARIES
VHDL libraries allow you to store commonly used packages and entities that you can use
in your VHDL files. A VHDL package file contains common design elements that you can
use in the VHDL file source files that make up your design. Use the following procedures
to create VHDL libraries and package files and to move package files from one library to
another.

VHDL packages are collections of reusable declarations and descriptions of

VHDL types, subtypes, subprograms, aliases, constants, attributes,
components, etc.
The declaration section of a package contains declaration statement for all
the elements in the package. For several elements (e.g. TYPE definitions),
the declaration is all that is needed. For some elements, however (e.g.
 subprograms), a functional description is also needed. This additional
information is placed in the body section of the package.

Transient response
In Electrical Engineering and Mechanical Engineering, a transient response or natural response is
the response of a system to a change from equilibrium.

In Electrical Engineering a simple example would be the output of a 5 volt DC power supply when
it is turned on: the transient response is from the time the switch is flipped until the output reaches a
steady 5 volts. At this time the power supply reaches its steady-state response of a constant 5 volts.

The transient response is not necessarily tied to "on/off" events but to any event that affects the
equilibrium of the system. If in an RC circuit the resistor or capacitor is replaced with a variable
resistor or variable capacitor (or both) then the transient response is the response to a change in the
resistor or capacitor.
Transient Electric Circuit Analysis
A transient electric circuit analysis analyzes an electric circuit subjected to time-varying
source voltage or currents.

DC circuit analysis
A network, in the context of electronics, is a collection of interconnected components.Network
analysis is the process of finding the voltages across, and the currents through, every component in
the network. There are a number of different techniques for achieving this. However, for the most part,
they assume that the components of the network are all linear.
DC Circuit Analysis
In this chapter, capacitors and inductors will be introduced (without considering the effects of AC
current.) The big thing to understand about Capacitors and Inductors in DC Circuits is that they have a
transient (temporary) response. During the transient period, capacitors build up charge and stop the
flow of current (eventually acting like infinite resistors.) Inductors build up energy in the form of
magnetic fields, and become more conductive. In other words, in the steady-state (long term
behavior), capacitors become open circuits and inductors become short circuits. Thus, for DC
analysis, you can replace a capacitor with an empty space and an inductor with a wire. The only
circuit components that remain are voltage sources, current sources, and resistors.

AC Analysis
The AC analysis is a small signal analysis in the frequency domain. Basically
this type of simulation uses the same algorithms as the DC analysis (section 3.1 on
page ). The AC analysis is a linear modified nodal analysis. Thus no iterative
process is necessary. With the Y-matrix of the components, i.e. now a complex
matrix, and the appropriate extensions it is necessary to solve the equation system
(4.1) similar to the (linear) DC analysis.
 Non-linear components have to be linearized at the DC bias point. That is,
before an AC simulation with non-linear components can be performed, a DC
simulation must be completed successfully.
AC Analysis
AC analysis lets you investigate small signal behavior. You can plot voltage or current and

produce Bode plots, Nyquist diagrams, Nichols charts, Smith charts, polar plots, and noise plots.

Other operators - including real, imaginary, magnitude, phase, and group delay - make analysis

and plotting easy. Micro-Cap provides automatic frequency step control for smooth plots with a

minimum number of calculations, greatly speeding AC analysis

DC Analysis
DC analysis provides for plotting static DC variables. You can use DC analysis for various plots,

including transfer functions, where one source is varied, and device IV curves, where two sources are

varied. Transfer function plots help to determine DC offset, bias, and overall amplifier gain.

Numerous variables can be varied in DC analysis. Among these are voltage and current sources,

temperature, and model parameters. The variables can be swept in a linear or log method, or swept

through a list of values.

Transient Analysis
Transient analysis provides for plotting of any time-domain waveform. Available

variables include digital state, voltage, current, power, energy, charge, resistance,

capacitance, inductance, B field, and H field. A variety of variables and mathematical

functions are available to simplify plots. Here are some examples:

V(Out): Voltage at node Out.

I(L1): Current through inductor L1.

PD(Q1): Power dissipation in Q1.

ES(M1): Energy stored in M1.

HARM(V(A)): Waveform A's harmonics.

RMS(v(1)*exp(-T/6n)): An RMS value.

D(A): The digital state on node A.

HEX(1,2,3,4): Hex value of nodes 1 to 4.