A B C D E

Compal Confidential
Model Name : P3MJ0
1
File Name : LA-7121P 1

BOM P/N:43XXXXXXL01(UMA)
43XXXXXXL02(DIS)

Compal Confidential
2

M/B Schematics Document 2

Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH

Nvidia N12P-GS/GV

2010-11-16
3 3

REV:0.2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 1 of 57
A B C D E
 A B C D E

P3MJ0 block diagram Fan Control

page 46

100MHz PCI-E 2.0x16 5GT/s PER LANE

PEG(DIS) Intel Memory BUS(DDRIII)
1
VRAM * 8 Nvidia N12P-GS(128bit) 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2 1

DDR3 Nvidia N12P-GV(64bit) Sandy Bridge BANK 0, 1, 2, 3 page 11,12

BGA 1.5V DDRIII 1333

64*16 Processor
25W/15W page22~33
EDP DC/QC 35W
128*16 2 lane SV
(reserved)
page 34
rPGA989
page 4~10

FDI x8 DMI x4 USB 2.0 conn WLAN Conn CMOS Camera

for Bluetooth BT
page 37
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz page 39 page 34
standalone
port 1 page 40
page 36 page 35 page 34 2.7GT/s 1GB/s x4 port 8 port 10
3.3V 48MHz port 13
USBx14
HDMI(UMA/Optimus) LVDS(UMA/Optimus)
Intel port 0 port 11
CRT(UMA/Optimus) HD Audio 3.3V 24MHz
2
TMDS(UMA/Optimus) Cougar Point-M MINI Card
2

PCH USB 2.0 conn WWAN

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz HDA Codec sub board page 39
989pin BGA Conexnt 20584
port 4 port 3 port 2 port 1 100MHz SPI sub board
page 13~21 port 12
USB 3.0 controller Card Reader MINI Card LAN(GbE) SATA x 6 SIM card
WLAN (+BT) Atheros AR8151 (GEN1 1.5GT/S ,GEN2 3GT/S) page 39
UPD720200AF1 RTS5209 Power off design
+ Charger page 40 page 39 Atheros AR8152 SPI ROM x1
sub board
page 44 Wireless HDMI 4MB page 14
port 0
SATA HDD
5 in 1 slot RJ45 Conn. page 38
conn x 1 page 40
sub board
page 43
Int. Speaker MIC Jack DMIC SPDIF/HP Jack
3 3
LPC BUS
page 46 sub board module sub board
33MHz

RTC CKT. ENE KB930

page 13 page 41

Power On/Off CKT. Touch Pad Int.KBD CPU XDP

page 43 page 42 page 42 page 5
P3MJ0 Sub-board
DC/DC Interface CKT. USB 2.0 +
page 45
Audio Codec + Jack
BIOS ROM
page 41
4 4
Power Circuit DC/DC LAN
page 48~56

Security Classification Compal Secret Data Compal Electronics, Inc.

LED Sub board conn Power Board Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

page 42 & buttons THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
page 46 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 2 of 57
A B C D E
 A B C D E

Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 +VGA_CORE Core voltage for GPU ON OFF OFF 1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VCCP +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW +3VALW always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW_EC +3VALW always to KBC ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS +3VALW to +3VS power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VS +5VALW to +5VS switched power rail ON OFF OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
BOARD ID Table BTO Option Table
2 +RTCVCC RTC power ON ON ON 2
BTO Item BOM Structure
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Board ID PCB Revision
UMA Only UMA@
0 0.1
Discrete(OPTIMUS) OPT@
1 0.2
VRAM X76@
EC SM Bus1 address EC SM Bus2 address 2 0.3
Connector CONN@
3 1.0
3G 3G@
Device Address Device Address 4
Smart Battery 0001 011X b
Blue Tooth BT@
5
Unpop @
6
N12P-GS GS@
7
N12P-GV GV@
PCH SM Bus address Project ID Table for AD channel
Device Address Vcc 3.3V +/- 5%
Clock Generator (9LVS3199AKLFT, 1101 0010b
Ra/Rc/Re 100K +/- 5%
RTM890N-631-VB-GRT) Board ID Rb / Rd / Rf V AD_PID min V AD_PID typ V AD_PID max
DDR DIMM0 1001 000Xb JM30 0 0 V 0 V 0 V
DDR DIMM2 1001 010Xb JM40 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
JM50 18K +/- 5% 0.436 V 0.503 V 0.538 V
SJM30 33K +/- 5% 0.712 V 0.819 V 0.875 V
3 3
3G & BT Config SJM40 56K +/- 5% 1.036 V 1.185 V 1.264 V
3G SKU: 3G@ SJM50 100K +/- 5% 1.453 V 1.650 V 1.759 V
BT SKU: BT@ NC NC
NC NC
BOM Config USB Port Table
UMA Only: UMA@ /BT@/3G@
3 External Design Common
N12P-GS OPTIMUS: OPT@/GS@/X76@/BT@/3G@ USB 2.0 USB 1.1 Port USB Port
N12P-GV OPTIMUS: OPT@/GV@/X76@/BT@/3G@ schematics pages
0 USB/B (Left Side) sequence
UHCI0 Part count location define
1 USB/B (Left Side)
CPU/PCH/CLK 1~1099
2
UHCI1 DIMM 2000~2099
3
EHCI1 dGPU 1400~1999
4
UHCI2 LVDS/CRT/HDMI/DP 2100~2199
5
Audio 1100~1199
6
UHCI3 LAN 1200~1299
7
Card Reader 1300~1399
8 Mini Card(WLAN)
VRAM BOM Config UHCI4 Other IO
9 Mini Card(WWAN) (HDD/ODD/MINI/
add later 2400~xxxx
10 Camera USB/KBD/BIOS/
4
EHCI2 UHCI5 4
11 Button/LED)
12 SIM Card KBC 2200~2299
UHCI6
13 Blue Tooth POK CKT, DC/DC 2300~2399

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 3 of 57
A B C D E
 5 4 3 2 1

D D
+1.05VS_VCCP

1
R1
24.9_0402_1%

JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
15 DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
15 DMI_CRX_PTX_N1 B25 DMI_RX#[1]
15 DMI_CRX_PTX_N2 A25 DMI_RX#[2]
15 DMI_CRX_PTX_N3 B24 K33 PEG_HRX_GTX_N15
DMI_RX#[3] PEG_RX#[0] PEG_HRX_GTX_N14
PEG_RX#[1] M35
15 DMI_CRX_PTX_P0 B28 L34 PEG_HRX_GTX_N13
DMI_RX[0] PEG_RX#[2] PEG_HRX_GTX_N[0..15] 22
15 DMI_CRX_PTX_P1 B26 J35 PEG_HRX_GTX_N12
DMI_RX[1] PEG_RX#[3] PEG_HRX_GTX_P[0..15] 22

DMI
15 DMI_CRX_PTX_P2 A24 J32 PEG_HRX_GTX_N11
DMI_RX[2] PEG_RX#[4] PEG_HRX_GTX_N10
15 DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34 PEG_HTX_C_GRX_N[0..15] 22
H31 PEG_HRX_GTX_N9
PEG_RX#[6] PEG_HTX_C_GRX_P[0..15] 22
G21 G33 PEG_HRX_GTX_N8
15 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
E22 G30 PEG_HRX_GTX_N7
15 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_HRX_GTX_N6
15 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_HRX_GTX_N5
15 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
E32 PEG_HRX_GTX_N4
PEG_RX#[11] PEG_HRX_GTX_N3
15 DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33
D22 D31 PEG_HRX_GTX_N2
15 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]

PCI EXPRESS* - GRAPHICS

F20 B33 PEG_HRX_GTX_N1
15 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
C21 C32 PEG_HRX_GTX_N0
15 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PEG_HRX_GTX_P15
C PEG_RX[0] PEG_HRX_GTX_P14 C
PEG_RX[1] L35
K34 PEG_HRX_GTX_P13
PEG_RX[2] PEG_HRX_GTX_P12
15 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PEG_HRX_GTX_P11
15 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PEG_HRX_GTX_P10
15 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] PEG_HRX_GTX_P9

Intel(R) FDI
15 FDI_CTX_PRX_N3 F18 FDI0_TX#[3] PEG_RX[6] G31
B21 F33 PEG_HRX_GTX_P8
15 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PEG_HRX_GTX_P7
15 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PEG_HRX_GTX_P6
15 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_HRX_GTX_P5
15 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PEG_HRX_GTX_P4
PEG_RX[11] PEG_HRX_GTX_P3
PEG_RX[12] D34
A22 E31 PEG_HRX_GTX_P2
15 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_HRX_GTX_P1
15 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
E20 B32 PEG_HRX_GTX_P0
15 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
15 FDI_CTX_PRX_P3 G18 FDI0_TX[3]
B20 M29 PEG_HTX_GRX_N15 C1 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N15
15 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PEG_HTX_GRX_N14 C2 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N14
15 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PEG_HTX_GRX_N13 C3 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N13
15 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_HTX_GRX_N12 C4 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N12
15 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PEG_HTX_GRX_N11 C5 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N11
+1.05VS_VCCP PEG_TX#[4] PEG_HTX_GRX_N10 C6 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N10
15 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
15 FDI_FSYNC1 J17 K28 PEG_HTX_GRX_N9 C7 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N9
FDI1_FSYNC PEG_TX#[6] PEG_HTX_GRX_N8 C8 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N8
PEG_TX#[7] J30 1 2
15 FDI_INT H20 J28 PEG_HTX_GRX_N7 C9 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N7
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 C10 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N6
PEG_TX#[9] H29 1 2
1

15 FDI_LSYNC0 J19 G27 PEG_HTX_GRX_N5 C11 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N5

R2 FDI0_LSYNC PEG_TX#[10] PEG_HTX_GRX_N4 C12 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N4
15 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 1 2
24.9_0402_1% F27 PEG_HTX_GRX_N3 C13 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N3
PEG_TX#[12] PEG_HTX_GRX_N2 C14 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N2
PEG_TX#[13] D28 1 2
F26 PEG_HTX_GRX_N1 C15 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N1
2

PEG_TX#[14] PEG_HTX_GRX_N0 C16 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_N0

PEG_TX#[15] E25 1 2
B EDP_COMP B
A18 eDP_COMPIO
A17 M28 PEG_HTX_GRX_P15 C17 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P15
eDP_ICOMPO PEG_TX[0] PEG_HTX_GRX_P14 C18 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P14
34 EDP_HPD# B16 eDP_HPD PEG_TX[1] M33 1 2
M30 PEG_HTX_GRX_P13 C19 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P13
PEG_TX[2] PEG_HTX_GRX_P12 C20 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P12
PEG_TX[3] L31 1 2
34 EDP_AUXP C15 L28 PEG_HTX_GRX_P11 C21 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P11
eDP_AUX PEG_TX[4] PEG_HTX_GRX_P10 C22 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P10
34 EDP_AUXN D15 eDP_AUX# PEG_TX[5] K30 1 2
eDP

K27 PEG_HTX_GRX_P9 C23 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P9

PEG_TX[6] PEG_HTX_GRX_P8 C24 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P8
PEG_TX[7] J29 1 2
C17 J27 PEG_HTX_GRX_P7 C25 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P7
34 EDP_TXP0 eDP_TX[0] PEG_TX[8]
EDP_TXP1 F16 H28 PEG_HTX_GRX_P6 C26 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P6
34 EDP_TXP1 eDP_TX[1] PEG_TX[9]
C16 G28 PEG_HTX_GRX_P5 C27 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P5
eDP_TX[2] PEG_TX[10] PEG_HTX_GRX_P4 C28 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P4
G15 eDP_TX[3] PEG_TX[11] E28 1 2
F28 PEG_HTX_GRX_P3 C29 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P3
PEG_TX[12] PEG_HTX_GRX_P2 C30 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P2
34 EDP_TXN0 C18 eDP_TX#[0] PEG_TX[13] D27 1 2
EDP_TXN1 E16 E26 PEG_HTX_GRX_P1 C31 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P1
34 EDP_TXN1 eDP_TX#[1] PEG_TX[14]
D16 D25 PEG_HTX_GRX_P0 C32 1 2 OPT@ .1U_0402_16V7K PEG_HTX_C_GRX_P0
eDP_TX#[2] PEG_TX[15]
F15 eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0
CONN@
Typ- suggest 220nF. The change in AC capacitor
eDP_COMPIO and ICOMPO signals value from 100nF to 220nF is to enable
should be shorted near balls INETL_RPGA_989P-S compatibility with future platforms having PCIE
and routed with typical Gen3 (8GT/s)
impedance <25 mohms

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 4 of 57
5 4 3 2 1
 5 4 3 2 1

JCPU1B
+1.05VS_VCCP Processor Pullups

R5 2 1 62_0402_5% H_PROCHOT# A28 CLK_CPU_DMI_R R3 1 2 0_0402_5% CLK_CPU_DMI 14

MISC

CLOCKS
BCLK CLK_CPU_DMII#_R R4
17 H_SNB_IVB# C26 PROC_SELECT# BCLK# A27 1 2 0_0402_5% CLK_CPU_DMI# 14

AN34 SKTOCC#
R8 2 1 10K_0402_5% H_CPUPWRGD_R DPLL_REF_CLK A16 CLK_DP_R R362 1 2 1K_0402_5%
A15 CLK_DP#_R R363 1 2 1K_0402_5% +1.05VS_VCCP
DPLL_REF_CLK#
@ C211 2 1 220P_0402_50V7K
T3 PAD H_CATERR# AL33 CATERR#
R9

THERMAL
220pF close to CPU(ESD) 0_0402_5%
D D
1 2 H_PECI_ISO AN33 R8
18,41 H_PECI PECI SM_DRAMRST# H_DRAMRST# 6
CLK_DP_R R6 1 @ 2 0_0402_5% CLK_DP 14

DDR3
MISC
R10 CLK_DP#_R R7 1 @ 2 0_0402_5% CLK_DP# 14
56_0402_5%
41,50 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0
PROCHOT# SM_RCOMP[0] SM_RCOMP1
SM_RCOMP[1] A5
R11 A4 SM_RCOMP2
+3VS 0_0402_5% SM_RCOMP[2]
eDP enable:
Buffered reset to CPU 1 2 H_THEMTRIP#_R AN32
18 H_THRMTRIP# THERMTRIP# TX:mount C2114, C2115,
AUX: mount C2118, C2119
+1.05VS_VCCP
1 HPD: mount R2112, Q2103, R2114
C33
0.1U_0402_16V4Z AP29 XDP_PRDY#_R PAD T86 CFG4: mount R55
PRDY#

1
2 PREQ# AP27 XDP_PREQ#_R PAD T87 CLK: mount R6,R7, unmount R362, R363
R15
75_0402_5% R12 AR26 XDP_TCK_R
TCK

PWR MANAGEMENT
0_0402_5% XDP_TMS_R

JTAG & BPM

TMS AR27
5

U1 R17 1 2 H_PM_SYNC_R AM34 AP30 XDP_TRST#_R

15 H_PM_SYNC
2 43_0402_1% PM_SYNC TRST#
1
P

NC
Y 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# R13
TDI AR28 XDP_TDI_R
17,40,41,44,46 PLT_RST# PLT_RST# 2 0_0402_5% AP26 XDP_TDO_R
A TDO
G

1
SN74LVC1G07DCKR_SC70-5 18 H_CPUPWRGD 1 2 H_CPUPWRGD_R AP33
@ UNCOREPWRGOOD
3

R19 R14
0_0402_5% 130_0402_5% AL35 DBRESET#_R 1 R361 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# 15
PM_SYS_PWRGD_BUF DBR#
2 1 2 PM_DRAM_PWRGD_R V8 SM_DRAMPWROK
AT28 XDP_BPM#0_R PAD T38
BPM#[0] XDP_BPM#1_R PAD T39
BPM#[1] AR29
AR30 XDP_BPM#2_R PAD T40
BUF_CPU_RST# BPM#[2] XDP_BPM#3_R PAD T41
AR33 RESET# BPM#[3] AT30
AP32 XDP_BPM#4_R PAD T42
+3VS +3VALW BPM#[4] XDP_BPM#5_R PAD T43
BPM#[5] AR31
AT31 XDP_BPM#6_R PAD T44
BPM#[6] XDP_BPM#7_R PAD T45
BPM#[7] AR32
+1.5V_CPU_VDDQ
1
C C34 DDR3 Compensation Signals C
0.1U_0402_16V4Z
1

2 R16 Sandy Bridge_rPGA_Rev1p0 SM_RCOMP0 R21 2 1 140_0402_1%

U2 200_0402_5% CONN@
R18 74AHC1G09GW_TSSOP5 SM_RCOMP1 R22 2 1 25.5_0402_1%
5

10K_0402_5%
2

1 2 1
INETL_RPGA_989P-S SM_RCOMP2 R24 2 1 200_0402_1%
P

B PM_SYS_PWRGD_BUF
O 4
15 PM_DRAM_PWRGD 2 A
G

1
3

@ PU/PD for JTAG signals

R20 +1.05VS_VCCP
39_0402_5%
XDP_TMS_R R31 2 @ 1 51_0402_5%
1 2

D XDP_TDI_R R34 2 @ 1 51_0402_5%

45,53 SUSP SUSP 2 Q1
G 2N7002H_SOT23-3 XDP_TDO_R R37 2 @ 1 51_0402_5%
S @
3

XDP_TCK_R R39 2 @ 1 51_0402_5%

XDP_TRST#_R R42 2 @ 1 51_0402_5%

+3VS

XDP_DBRESET# R48 2 1 1K_0402_5%

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 5 of 57
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D

11 DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 11 12 DDR_B_D[0..63] SB_CLK[0] AE2 M_CLK_DDR2 12

SA_CLK#[0] AA6 M_CLK_DDR#0 11 SB_CLK#[0] AD2 M_CLK_DDR#2 12
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA 11 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB 12
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
DDR_A_D4 SA_DQ[3] DDR_B_D4 SB_DQ[3]
D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1 11 A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3 12
D DDR_A_D5 DDR_B_D5 D
C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR#1 11 A8 SB_DQ[5] SB_CLK#[1] AD1 M_CLK_DDR#3 12
DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA 11 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB 12
DDR_A_D7 C3 DDR_B_D7 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 SA_DQ[8] G4 SB_DQ[8]
DDR_A_D9 F8 DDR_B_D9 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 SA_DQ[10] RSVD_TP[1] AB4 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F9 SA_DQ[12] RSVD_TP[3] W9 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D13 F7 DDR_B_D13 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 SA_DQ[14] F2 SB_DQ[14]
DDR_A_D15 G7 DDR_B_D15 G2
DDR_A_D16 SA_DQ[15] DDR_B_D16 SB_DQ[15]
K4 SA_DQ[16] RSVD_TP[4] AB3 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
K1 SA_DQ[18] RSVD_TP[6] W10 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D19 J1 DDR_B_D19 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
DDR_A_D22 SA_DQ[21] DDR_B_D22 SB_DQ[21]
J2 SA_DQ[22] SA_CS#[0] AK3 DDR_CS0_DIMMA# 11 K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# 12
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# 11 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# 12
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 SA_DQ[24] RSVD_TP[7] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
N10 SA_DQ[25] RSVD_TP[8] AH1 N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D26 N8 DDR_B_D26 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDR_B_D29 SB_DQ[28]
M9 SA_DQ[29] SA_ODT[0] AH3 M_ODT0 11 N5 SB_DQ[29] SB_ODT[0] AE4 M_ODT2 12

DDR SYSTEM MEMORY B

DDR_A_D30 DDR_B_D30

DDR SYSTEM MEMORY A

N9 SA_DQ[30] SA_ODT[1] AG3 M_ODT1 11 M2 SB_DQ[30] SB_ODT[1] AD4 M_ODT3 12
DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
DDR_A_D32 SA_DQ[31] RSVD_TP[9] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
AG6 SA_DQ[32] RSVD_TP[10] AH2 AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D33 AG5 DDR_B_D33 AM6
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
DDR_A_D35 AK5 DDR_B_D35 AP3
DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] 11 AN3 SB_DQ[36] DDR_B_DQS#[0..7] 12
C DDR_A_D37 DDR_A_DQS#0 DDR_B_D37 DDR_B_DQS#0 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 SA_DQ[39] SA_DQS#[2] J3 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D40 AJ8 M6 DDR_A_DQS#3 DDR_B_D40 AP5 N3 DDR_B_DQS#3
DDR_A_D41 SA_DQ[40] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AK8 SA_DQ[41] SA_DQS#[4] AL6 AN9 SB_DQ[41] SB_DQS#[4] AN5
DDR_A_D42 AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AK9 SA_DQ[43] SA_DQS#[6] AR12 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 SA_DQ[45] AN8 SB_DQ[45]
DDR_A_D46 AL9 DDR_B_D46 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 SA_DQ[47] AR5 SB_DQ[47]
DDR_A_D48 AP11 DDR_B_D48 AR9
SA_DQ[48] DDR_A_DQS[0..7] 11 SB_DQ[48] DDR_B_DQS[0..7] 12
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D53 AR8 AN6 DDR_B_DQS4
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D55 AH12 AK11 DDR_B_DQS6
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
DDR_A_D59 AK15 DDR_B_D59 AT14
DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
AL14 SA_DQ[60] DDR_A_MA[0..15] 11 AT12 SB_DQ[60] DDR_B_MA[0..15] 12
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[3] W7 SB_MA[3] T6
V3 DDR_A_MA4 T2 DDR_B_MA4
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
SA_MA[5] V2 SB_MA[5] T4
W3 DDR_A_MA6 T3 DDR_B_MA6
SA_MA[6] DDR_A_MA7 SB_MA[6] DDR_B_MA7
11 DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 12 DDR_B_BS0 AA9 SB_BS[0] SB_MA[7] R2
B DDR_A_MA8 DDR_B_MA8 B
11 DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 12 DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
V6 W5 DDR_A_MA9 R6 R3 DDR_B_MA9
11 DDR_A_BS2 SA_BS[2] SA_MA[9] 12 DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
SA_MA[12] DDR_A_MA13 SB_MA[12] DDR_B_MA13
11 DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 12 DDR_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
AD9 V5 DDR_A_MA14 AB8 R5 DDR_B_MA14
11 DDR_A_RAS# SA_RAS# SA_MA[14] 12 DDR_B_RAS# SB_RAS# SB_MA[14]
AF9 V7 DDR_A_MA15 AB9 R4 DDR_B_MA15
11 DDR_A_WE# SA_WE# SA_MA[15] 12 DDR_B_WE# SB_WE# SB_MA[15]

Sandy Bridge_rPGA_Rev1p0 Sandy Bridge_rPGA_Rev1p0

CONN@ CONN@

+1.5V

@ R49
1

0_0402_5%
1 2 R50
1K_0402_5%
2
S

5 H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 R51 2 DDR3_DRAMRST# 11,12

Q2 1K_0402_5%
2

BSS138_NL_SOT23-3
R52
G
2

4.99K_0402_1%
1

A A
R53
0_0402_5%
7,14 DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

Security Classification Compal Secret Data Compal Electronics, Inc.

1 Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

C35
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
0.047U_0402_16V4Z AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 6 of 57

5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

JCPU1E

L7 CFG2
RSVD28
RSVD29 AG7

1
T90 PAD CFG0 AK28 AE7
T46 PAD CFG1 CFG[0] RSVD30
AK29 CFG[1] RSVD31 AK2
T47 PAD CFG2 AL26 W8 R54
T48 PAD CFG3 CFG[2] RSVD32 1K_0402_1%
AL27 CFG[3]
D T49 PAD CFG4 D
AK26

2
T50 PAD CFG5 CFG[4]
AL29 CFG[5] RSVD33 AT26
T51 PAD CFG6 AL30 AM33
T52 PAD CFG7 CFG[6] RSVD34
AM31 CFG[7] RSVD35 AJ27
T53 PAD CFG8 AM32
T54 PAD CFG9 CFG[8]
AM30 CFG[9]
T55 PAD CFG10 AM28
T56 PAD CFG11 CFG[10]
AM26 CFG[11] PEG Static Lane Reversal - CFG2 is for the 16x
T57 PAD CFG12 AN28
T58 PAD CFG13 CFG[12]
AN31 CFG[13] RSVD37 T8
T59 PAD CFG14 AN26 J16 1: Normal Operation; Lane # definition matches
T60 PAD CFG15 CFG[14] RSVD38
AM27 CFG[15] RSVD39 H16 CFG2 socket pin map definition
T61 PAD CFG16 AK31 G16
T62 PAD CFG17 CFG[16] RSVD40
AN29 CFG[17]
0:Lane Reversed
*
AR35 CFG4
T82 PAD VAXG_VAL_SENSE RSVD41
AJ31 VAXG_VAL_SENSE RSVD42 AT34

1
T83 PAD VSSAXG_VAL_SENSE AH31 AT33
T84 PAD VCC_VAL_SENSE VSSAXG_VAL_SENSE RSVD43 @
AJ33 VCC_VAL_SENSE RSVD44 AP35
T85 PAD VSS_VAL_SENSE AH33 AR34 R55
VSS_VAL_SENSE RSVD45 1K_0402_1%

2
AJ26 RSVD5

RESERVED
RSVD46 B34
CPU_RSVD6 B4 A33
CPU_RSVD7 RSVD6 RSVD47
D1 RSVD7 RSVD48 A34
SA_DIMM_VREFDQ RSVD49 B35 Display Port Presence Strap
RSVD50 C35
1

1
C SB_DIMM_VREFDQ C

For Future CPU M3 support, F25 1 : Disabled; No Physical Display Port

Sandey bridge not supportM3,
R63
1K_0402_1%
R64
1K_0402_1%
F24
F23
RSVD8
RSVD9
RSVD10
CFG4 * attached to Embedded Display Port
Check list1.0&CRB say can NC D24 AJ32
2

RSVD11 RSVD51
G25 RSVD12 RSVD52 AK32 0 : Enabled; An external Display Port device is
G24
E23
RSVD13 connected to the Embedded Display Port
RSVD14
D23 RSVD15
C30 AH27 PAD T4
RSVD16 VCC_DIE_SENSE
A31 RSVD17
B30 CFG6
+3VS RSVD18
B29 RSVD19
check +3VS or +3VALW D30 AN35 PAD T5 CFG5
RSVD20 RSVD54 PAD T6
B31 RSVD21 RSVD55 AM35
1

1
A30 RSVD22
R385 C29 @ R61 @ R62
@R62
@ 10K_0402_5% RSVD23 1K_0402_1% 1K_0402_1%
10/2, From JM50, delete,
J20
10/19, From checklist 1.2, add the path
2

2
RSVD24
B18 RSVD25 RSVD56 AT2
follow Module design VCCIO_SEL A19 AT1
VCCIO_SEL RSVD57
RSVD58 AR1
1

VCCIO_SEL For 2012 CPU support R378 J15

@ 10K_0402_5% RSVD27

1/NC : (Default) +1.05VS_VTT B1

*
2

KEY
A19 PCIE Port Bifurcation Straps
0: +1.0VS_VTT
11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
RSVD26 had changed the name to VCCIO_SEL CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B

Sandy Bridge_rPGA_Rev1p0
Need PH +3VALW 10K at +1.05VS_VTT source CONN@ disabled
for 2012 processor +1.05V and +1.0V select 01: Reserved - (Device 1 function 1 disabled ; function
INETL_RPGA_989P-S 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7
R60 1 @ 2 0_0402_5%

1
@ R66
1K_0402_1%
Q3
+V_DDR_M3_REFA

2
1 3 CPU_RSVD6

AP2302GN-HF_SOT23-3
@
2
PEG DEFER TRAINING
DRAMRST_CNTRL_PCH

1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion
R65 1 @ 2 0_0402_5%
A A
0: PEG Wait for BIOS for training
Q13
+V_DDR_M3_REFB
1 3 CPU_RSVD7

AP2302GN-HF_SOT23-3
@
Security Classification Compal Secret Data
2
Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title Compal Electronics, Inc.
DRAMRST_CNTRL_PCH 6,14
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
9/16, SM50 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 7 of 57
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER
SV type CPU
+CPU_CORE
QC 94A
+1.05VS_VCCP
Bottom Socket Cavity DC 53A 8.5A
AG35 VCC1
MB Bottom Socket Cavity
1 1 1 1 1 AG34 AH13 +1.05VS_VCCP 1 1
VCC2 VCCIO1

10U_0805_6.3V6M
C36

10U_0805_6.3V6M
C37

10U_0805_6.3V6M
C38

10U_0805_6.3V6M
C39

10U_0805_6.3V6M
C40

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

330U_D2_2V_Y

330U_D2_2V_Y
AG33 VCC3 VCCIO2 AH10 1 1 1 1 1

C41
AG32 AG10 + + @
VCC4 VCCIO3

C43

C44

C45

C46

C47

C42
AG31 VCC5 VCCIO4 AC10
2 2 2 2 2
AG30 VCC6 VCCIO5 Y10
D 2 2 2 2 2 2 2 2012 compatible D
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
1 1 1 1 1 AF34 VCC12 VCCIO11 J12

10U_0805_6.3V6M
C48

10U_0805_6.3V6M
C49

10U_0805_6.3V6M
C50

10U_0805_6.3V6M
C51

10U_0805_6.3V6M
C52
AF33 VCC13 VCCIO12 J11

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AF32 VCC14 VCCIO13 H14 1 1 1 1 1
AF31 H12 @ @ @ @ @
2 2 2 2 2 VCC15 VCCIO14

C53

C54

C55

C56

C57
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
2 2 2 2 2
AF28 VCC18 VCCIO17 G13

PEG AND DDR

AF27 VCC19 VCCIO18 G12
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
+CPU_CORE
AD33 F11
AD32
VCC23 VCCIO22
E14 MB Top Socket Cavity
Top Socket Cavity AD31
VCC24
VCC25
VCCIO23
VCCIO24 E12
AD30 VCC26 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

330U_D2_2V_Y
1 1 1 1 1 1 1 1 AD29 VCC27 VCCIO25 E11 1 1 1 1
22U_0805_6.3V6M
C59

22U_0805_6.3V6M
C60

22U_0805_6.3V6M
C61

22U_0805_6.3V6M
C62

22U_0805_6.3V6M
C63

22U_0805_6.3V6M
C64

22U_0805_6.3V6M
C65

22U_0805_6.3V6M
C66

C58
AD28 D14 @ @ +
VCC28 VCCIO26

C67

C68

C69

C70
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
2 2 2 2 2 2 2 2 2 2 2 2 2
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
AC29 B12
Top Socket Edge VCC37 VCCIO35

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AC28 VCC38 VCCIO36 A14 1 1 1 1 1
C C
AC27 VCC39 VCCIO37 A13

22U_0805_6.3V6M

C71

C72

C73

C74

C75
1 1 1 1 1 1 1 1 AC26 VCC40 VCCIO38 A12
22U_0805_6.3V6M
C76

22U_0805_6.3V6M
C77

22U_0805_6.3V6M
C78

22U_0805_6.3V6M
C79

22U_0805_6.3V6M
C80

22U_0805_6.3V6M
C81

22U_0805_6.3V6M
C82

C83
AA35 VCC41 VCCIO39 A11
2 2 2 2 2
AA34 VCC42
AA33 VCC43 VCCIO40 J23
2 2 2 2 2 2 2 2
AA32 VCC44
AA31 VCC45
AA30 VCC46
AA29 VCC47
AA28 VCC48
AA27 VCC49
AA26 VCC50

CORE SUPPLY
+CPU_CORE +1.05VS_VCCP +1.05VS_VCCP
Y35 VCC51
Y34
Bottom Socket Edge Y33
VCC52
VCC53

1
Y32 VCC54
Y31 R67 R68
VCC55
330U_D2_2.5VY_R9M
C84

330U_D2_2.5VY_R9M
C85

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1 1 1 1 Y30 130_0402_5% 75_0402_5%

VCC56
Y29 VCC57
C86

C87

+ + + + Y28

2
VCC58
Y27 VCC59
Y26 VCC60
2 2 2 2 9/16 V35

SVID
VCC61 H_CPU_SVIDALRT# R69
V34 VCC62 VIDALERT# AJ29 1 2 43_0402_1% VR_SVID_ALRT# 54
PDDG says 470u*4 V33 AJ30 H_CPU_SVIDCLK R70 1 2 0_0402_5%
VCC63 VIDSCLK VR_SVID_CLK 54
V32 AJ28 H_CPU_SVIDDAT R71 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT 54
V31 VCC65
V30 VCC66
V29 VCC67
V28 VCC68
V27 VCC69 Place the PU
V26
B
U35
VCC70 resistors close to VR B
VCC71
U34 VCC72
U33 VCC73
U32 VCC74
U31 VCC75
U30 VCC76
U29 VCC77
U28 VCC78
U27 VCC79
U26 VCC80 +CPU_CORE
Place the PU
R35
R34
VCC81 resistors close to CPU
VCC82
R33 VCC83

1
R32 VCC84
R31 R72
VCC85 100_0402_1%
R30 VCC86
R29 VCC87

SENSE LINES
R28

2
VCC88
R27 VCC89 VCC_SENSE AJ35 VCCSENSE_R R73 1 2 0_0402_5%
VCCSENSE 54
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R R74 1 2 0_0402_5%
VSSSENSE 54
P35 VCC91
P34 VCC92

1
P33 R75
VCC93 VCCIO_SENSE 100_0402_1%
P32 VCC94 VCCIO_SENSE B10 VCCIO_SENSE 53
P31 A10 VSSIO_SENSE
VCC95 VSSIO_SENSE VSSIO_SENSE 53
P30 VCC96
P29

2
VCC97
P28 VCC98
P27 VCC99
P26 VCC100

A A

Sandy Bridge_rPGA_Rev1p0
CONN@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 8 of 57
5 4 3 2 1
 5 4 3 2 1

D D

DELETE

+VGFX_CORE
EDS1.3
JCPU1G
POWER
QC DC 33A
Top Socket Cavity

SENSE
LINES
AT24 VAXG1 VAXG_SENSE AK35 VCC_AXG_SENSE 54
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE 54 +1.5V_CPU_VDDQ

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 AT21 VAXG3
AT20 VAXG4
AT18 VAXG5

C91

C92

C93

C94
AT17 VAXG6 10/2

1
2 2 2 2
AR24 VAXG7
AR23 +V_SM_VREF should R83
C VAXG8 1K_0402_1% C
AR21 VAXG9
AR20 have 20 mil trace width

VREF
VAXG10
AR18
Top Socket Edge

2
VAXG11
AR17 VAXG12
AP24 AL1 +V_SM_VREF_CNT R84 1 2 0_0402_5% +V_SM_VREF
VAXG13 SM_VREF
AP23 VAXG14
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 AP21 VAXG15 1
AP20 C99
VAXG16

1
AP18 0.1U_0402_16V4Z
VAXG17
C95

C96

C97

C98
AP17 R85
2 2 2 2 VAXG18 2 1K_0402_1%
AN24 VAXG19
AN23 VAXG20
AN21

2
VAXG21
AN20 VAXG22

DDR3 -1.5V RAILS

AN18 +1.5V_CPU_VDDQ +1.5VS
Bottom Socket Cavity AN17
VAXG23
VAXG24 10A JP1 @

GRAPHICS
AM24 VAXG25 VDDQ1 AF7 1 2
AM23 VAXG26 VDDQ2 AF4
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1 1 1 1 AM21 AF1 1 PAD-OPEN 4x4m

VAXG27 VDDQ3

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AM20 VAXG28 VDDQ4 AC7 1 1 1 1 1 1
AM18 AC4 + C104
VAXG29 VDDQ5
C100

C101

C102

C103

C105

C106

C107

C108

C109

C110
AM17 AC1 330U_D2_2V_Y
2 2 2 2 VAXG30 VDDQ6
AL24 VAXG31 VDDQ7 Y7
2 2 2 2 2 2 2
AL23 VAXG32 VDDQ8 Y4
AL21 VAXG33 VDDQ9 Y1
AL20 VAXG34 VDDQ10 U7
AL18 U4
Bottom Socket Edge AL17
VAXG35
VAXG36
VDDQ11
VDDQ12 U1
AK24 VAXG37 VDDQ13 P7
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1 @ 1 @ 1 @ 1 @ AK23 P4
VAXG38 VDDQ14
AK21 VAXG39 VDDQ15 P1
AK20 VAXG40
C111

C112

C113

C114

B B
AK18 VAXG41
2 2 2 2
AK17 VAXG42
AJ24 VAXG43
AJ23 VAXG44
AJ21 VAXG45
AJ20
Bottom Socket Edge AJ18
VAXG46
VAXG47
AJ17 VAXG48
AH24 +VCCSA
6A

SA RAIL
VAXG49
330U_D2_2V_Y

330U_D2_2V_Y

1 1 AH23 9/16, SM50

@ VAXG50 +VCCSA
Vaxg AH21 VAXG51 VCCSA1 M27
+ + AH20 M26
VAXG52 VCCSA2
AH18 VAXG53 VCCSA3 L26
C115

C116

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0603_6.3V6M
‧ Can connect to GND if motherboard only AH17 VAXG54 VCCSA4 J26 1 1 1 1 @ 1 R86 2 100_0402_5% VCCSA_SENSE
2 2
VCCSA5 J25 1
supports external graphics and if GFX VR is not

C117

C118

C119

C120
VCCSA6 J24
H26 + C121
stuffed in a common motherboard design, VCCSA7 2 2 2 2 330U_D2_2V_Y
VCCSA8 H25
‧ VAXG can be left floating in a common
1.8V RAIL

2 R87
motherboard design (Gfx VR keeps VAXG from 1 2 0_0402_5% VSSSA_SENSE 52
floating) if the VR is stuffed +1.8VS R88 +1.8VS_VCCPLL 1.2A
0_0805_5%
1 2 B6 H23 VCCSA_SENSE 52
MISC

VCCPLL1 VCCSA_SENSE
A6 VCCPLL2
330U_D2_2V_Y
C122

10U_0805_6.3V6M
C125

1U_0402_6.3V6K
C123

1U_0402_6.3V6K
C124

1 1 1 A2 VCCPLL3
1
+ C22 H_FC_C22
FC_C22
VCCSA_VID1 C24 VCCSA_VID1 52
2 2

2
2 2

1
R89
A Sandy Bridge_rPGA_Rev1p0 @R90
@ R90 A
10K_0402_5%
CONN@ 1 0_0402_5%

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 9 of 57
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I

D D
AT35 VSS1 VSS81 AJ22
AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24
AT16 VSS8 VSS88 AJ3 T30 VSS166 VSS239 E21
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18
AT10 VSS10 VSS90 AJ1 T28 VSS168 VSS241 E15
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6
AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5
AR13 VSS18 VSS98 AH25 P2 VSS176 VSS249 E4
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2
AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17
AP19 VSS28 VSS108 AF5 N26 VSS186 VSS259 C34
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31
AP13 VSS30 VSS110 AF2 L33 VSS188 VSS261 C28
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 VSS32 VSS112 AE34 L27 VSS190 VSS263 C25
C C
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AP1 VSS34 VSS114 AE32 L8 VSS192 VSS265 C10
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22
AN25 AE29 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13
AN13 VSS41 VSS121 AE9 K35 VSS199 VSS272 B11
AN10 VSS42 VSS122 AD7 K32 VSS200 VSS273 B9
AN7 VSS43 VSS123 AC9 K29 VSS201 VSS274 B8
AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7
AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3
AM22 VSS47 VSS127 AC3 H33 VSS205 VSS278 B2
AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35
AM16 VSS49 VSS129 AB35 H27 VSS207 VSS280 A32
AM13 VSS50 VSS130 AB34 H24 VSS208 VSS281 A29
AM10 VSS51 VSS131 AB33 H21 VSS209 VSS282 A26
AM7 VSS52 VSS132 AB32 H18 VSS210 VSS283 A23
AM4 VSS53 VSS133 AB31 H15 VSS211 VSS284 A20
AM3 VSS54 VSS134 AB30 H13 VSS212 VSS285 A3
AM2 VSS55 VSS135 AB29 H10 VSS213
AM1 VSS56 VSS136 AB28 H9 VSS214
AL34 VSS57 VSS137 AB27 H8 VSS215
AL31 VSS58 VSS138 AB26 H7 VSS216
AL28 VSS59 VSS139 Y9 H6 VSS217
AL25 VSS60 VSS140 Y8 H5 VSS218
AL22 VSS61 VSS141 Y6 H4 VSS219
AL19 VSS62 VSS142 Y5 H3 VSS220
AL16 VSS63 VSS143 Y3 H2 VSS221
AL13 VSS64 VSS144 Y2 H1 VSS222
B B
AL10 VSS65 VSS145 W35 G35 VSS223
AL7 VSS66 VSS146 W34 G32 VSS224
AL4 VSS67 VSS147 W33 G29 VSS225
AL2 VSS68 VSS148 W32 G26 VSS226
AK33 VSS69 VSS149 W31 G23 VSS227
AK30 VSS70 VSS150 W30 G20 VSS228
AK27 VSS71 VSS151 W29 G17 VSS229
AK25 VSS72 VSS152 W28 G11 VSS230
AK22 VSS73 VSS153 W27 F34 VSS231
AK19 VSS74 VSS154 W26 F31 VSS232
AK16 VSS75 VSS155 U9 F29 VSS233
AK13 VSS76 VSS156 U8
AK10 VSS77 VSS157 U6
AK7 VSS78 VSS158 U5
AK4 VSS79 VSS159 U3
AJ25 VSS80 VSS160 U2

Sandy Bridge_rPGA_Rev1p0 Sandy Bridge_rPGA_Rev1p0

CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 10 of 57
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
R2001
+V_DDR_M3_REFA 1K_0402_1%
+1.5V +1.5V
R2016
JDIMM1

2
1 2 +DIMM0_VREF 1 2
VREF_DQ VSS DDR_A_DQS#[0..7] 6
3 4 DDR_A_D4
VSS DQ4

2.2U_0603_6.3V6K

0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
0_0402_5% DQ0 DQ5 DDR_A_DQS[0..7] 6

C2000

C2001
DDR_A_D1 7 8
@ R2002 DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 DDR_A_D[0..63] 6

1
1K_0402_1% DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 14 DDR_A_MA[0..15] 6

2
DDR_A_D2 VSS VSS DDR_A_D6
15 16

2
D DDR_A_D3 DQ2 DQ6 DDR_A_D7 D
17 DQ3 DQ7 18
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24
25 VSS VSS 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,12
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
All VREF traces should 35 DQ11 DQ15 36 Layout Note:
37 38
have 10 mil trace width DDR_A_D16 39
VSS VSS
40 DDR_A_D20 Place near JDIMM1
DDR_A_D17 DQ16 DQ20 DDR_A_D21 +1.5V
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48

1U_0402_6.3V6K
C2002

1U_0402_6.3V6K
C2003

1U_0402_6.3V6K
C2004

1U_0402_6.3V6K
C2005
49 50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52

1
DDR_A_D19 53 54
DQ19 VSS DDR_A_D28
55 VSS DQ28 56
DDR_A_D24 57 58 DDR_A_D29

2
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS DQS3# DDR_A_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72
+1.5V

6 DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_CKE1_DIMMA 6

CKE0 CKE1
75 VDD VDD 76

10U_0603_6.3V6M
C2007

10U_0603_6.3V6M
C2008

10U_0603_6.3V6M
C2009

10U_0603_6.3V6M
C2010

10U_0603_6.3V6M
C2011

10U_0603_6.3V6M
C2012

10U_0603_6.3V6M

330U_D2_2V_Y
C DDR_A_MA15 C
77 NC A15 78

C2006
6 DDR_A_BS2 DDR_A_BS2 79 80 DDR_A_MA14 @
BA2 A14

C2013
81 82 +
DDR_A_MA12 VDD VDD DDR_A_MA11
83 A12/BC# A11 84
DDR_A_MA9 85 86 DDR_A_MA7

2
A9 A7
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD VDD 100
6 M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1 M_CLK_DDR1 6
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
6 M_CLK_DDR#0 103 CK0# CK1# 104 M_CLK_DDR#1 6 +1.5V
105 VDD VDD 106
DDR_A_MA10 107 108 DDR_A_BS1 DDR_A_BS1 6
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
6 DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# 6
111 VDD VDD 112

1
6 DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA# DDR_CS0_DIMMA# 6 R2003
DDR_A_CAS# WE# S0# M_ODT0 1K_0402_1%
6 DDR_A_CAS# 115 CAS# ODT0 116 M_ODT0 6
117 VDD VDD 118
DDR_A_MA13 119 120 M_ODT1 M_ODT1 6
DDR_CS1_DIMMA# A13 ODT1
6 DDR_CS1_DIMMA# 121 122 Layout Note:

2
S1# NC
123 124
125
VDD VDD
126 +VREF_CA Place near JDIMM1.203,204
TEST VREF_CA
127 VSS VSS 128 JM50

2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
C2014

0.1U_0402_16V4Z
C2015
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37 R2004 +0.75VS
133 VSS VSS 134

1
DDR_A_DQS#4 135 136 DDR_A_DM4 1K_0402_1%
DDR_A_DQS4 DQS4# DM4
137 DQS4 VSS 138
139 140 DDR_A_D38

2
B DDR_A_D34 VSS DQ38 DDR_A_D39 B
141 DQ34 DQ39 142

1U_0402_6.3V6K
C2016

1U_0402_6.3V6K
C2017

1U_0402_6.3V6K
C2018

1U_0402_6.3V6K
C2019
DDR_A_D35 143 144
DQ35 VSS DDR_A_D44
145 VSS DQ44 146

1
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_A_DQS#5

2
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
153 DM5 DQS5 154
155 VSS VSS 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_A_DQS#6 169 170 DDR_A_DM6
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_A_D54
DDR_A_D50 VSS DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS DDR_A_D60
179 VSS DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61 DDR_A_DM0
183 DQ57 VSS 184
185 186 DDR_A_DQS#7 DDR_A_DM1
DDR_A_DM7 VSS DQS7# DDR_A_DQS7 DDR_A_DM2
187 DM7 DQS7 188
189 190 DDR_A_DM3
DDR_A_D58 VSS VSS DDR_A_D62 DDR_A_DM4
191 DQ58 DQ62 192
DDR_A_D59 193 194 DDR_A_D63 DDR_A_DM5
DQ59 DQ63 DDR_A_DM6
195 VSS VSS 196
197 198 DDR_A_DM7
SA0 EVENT# D_CK_SDATA
+3VS 199 VDDSPD SDA 200 D_CK_SDATA 12,14
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 12,14
+0.75VS 203 VTT VTT 204 +0.75VS
A A
1
0.1U_0402_16V4Z
C2020

2.2U_0603_6.3V6K
C2021

10K_0402_5%
R2013

10K_0402_5%
R2014

205 206
<Address: 00> GND1 GND2
2

207 BOSS1 BOSS2 208

1

SP07000NZ00
DIMM_A Reserve H:4mm FOX_AS0A621-U4RG-7H
2

CONN@
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 11 of 57
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
+V_DDR_M3_REFB R2015
1K_0402_1% +1.5V +1.5V
R2040
JDIMM2 CONN@
1 2 +DIMM1_VREF 1 2

2
VREF_DQ VSS1 DDR_B_D4
3 VSS2 DQ4 4

2.2U_0603_6.3V6K
C2022

0.1U_0402_16V4Z
C2023
DDR_B_D0 5 6 DDR_B_D5
0_0402_5% DQ0 DQ5

1
DDR_B_D1 7 8
@ DQ1 VSS3 DDR_B_DQS#[0..7] 6
9 10 DDR_B_DQS#0
R2017 DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0
11 12 DDR_B_DQS[0..7] 6

2
1K_0402_1% DM0 DQS0
13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D[0..63] 6

2
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
D D
19 VSS7 VSS8 20 DDR_B_MA[0..15] 6
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
All VREF traces should 29 DQS1 RESET# 30 DDR3_DRAMRST# 6,11
31 VSS11 VSS12 32
have 10 mil trace width DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20 +1.5V
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DQS#2 DM2

1U_0402_6.3V6K
C2024

1U_0402_6.3V6K
C2025

1U_0402_6.3V6K
C2026

1U_0402_6.3V6K
C2027
DDR_B_DQS2 47 48
DQS2 VSS17 DDR_B_D22
49 VSS18 DQ22 50

1
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_B_D28

2
DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 DQ24 DQ29 58
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70 Layout Note:
71 72
VSS25 VSS26 Place near JDIMM2
+1.5V

6 DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB DDR_CKE3_DIMMB 6

CKE0 CKE1
75 VDD1 VDD2 76

10U_0603_6.3V6M
C2029

10U_0603_6.3V6M
C2030

10U_0603_6.3V6M
C2031

10U_0603_6.3V6M
C2032

10U_0603_6.3V6M
C2033

10U_0603_6.3V6M
C2034

10U_0603_6.3V6M

330U_D2_2V_Y
C DDR_B_MA15 @ @ C
77 NC1 A15 78

1
C2035

C2028
6 DDR_B_BS2 DDR_B_BS2 79 80 DDR_B_MA14
BA2 A14

1
81 82 +
DDR_B_MA12 VDD3 VDD4 DDR_B_MA11
83 A12/BC# A11 84
DDR_B_MA9 85 86 DDR_B_MA7

2
A9 A7
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
6 M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3 M_CLK_DDR3 6
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
6 M_CLK_DDR#2 103 CK0# CK1# 104 M_CLK_DDR#3 6 +1.5V
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1 DDR_B_BS1 6
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
6 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 6
111 VDD13 VDD14 112 Layout Note:

1
6 DDR_B_WE# DDR_B_WE# 113 114 DDR_CS2_DIMMB# DDR_CS2_DIMMB# 6
DDR_B_CAS# 115
WE# S0#
116 M_ODT2 R2018 Place near JDIMM2.203,204
6 DDR_B_CAS# CAS# ODT0 M_ODT2 6
117 118 1K_0402_1% +0.75VS
DDR_B_MA13 VDD15 VDD16 M_ODT3
119 A13 ODT1 120 M_ODT3 6
6 DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122

2
S1# NC2
123 VDD17 VDD18 124
125 126 +VREF_CB
NCTEST VREF_CA

1U_0402_6.3V6K
C2036

1U_0402_6.3V6K
C2037

1U_0402_6.3V6K
C2038

1U_0402_6.3V6K
C2039
127 VSS27 VSS28 128 JM50

1
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

1
2.2U_0603_6.3V6K
C2040

0.1U_0402_16V4Z
C2041
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37 R2019
133 134

2
VSS29 VSS30

1
DDR_B_DQS#4 135 136 DDR_B_DM4 1K_0402_1%
DDR_B_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
139 140 DDR_B_D38

2
B DDR_B_D34 VSS32 DQ38 DDR_B_D39 B
141 DQ34 DQ39 142
DDR_B_D35 143 144
DQ35 VSS33 DDR_B_D44
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 DM5 DQS5 154
155 156 DDR_B_DM0
DDR_B_D42 VSS37 VSS38 DDR_B_D46 DDR_B_DM1
157 DQ42 DQ46 158
DDR_B_D43 159 160 DDR_B_D47 DDR_B_DM2
DQ43 DQ47 DDR_B_DM3
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52 DDR_B_DM4
DDR_B_D49 DQ48 DQ52 DDR_B_D53 DDR_B_DM5
165 DQ49 DQ53 166
167 168 DDR_B_DM6
DDR_B_DQS#6 VSS41 VSS42 DDR_B_DM6 DDR_B_DM7
169 DQS#6 DM6 170
DDR_B_DQS6 171 172
DQS6 VSS43 DDR_B_D54
173 VSS44 DQ54 174
DDR_B_D50 175 176 DDR_B_D55
+3VS +3VS DDR_B_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_B_D60
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 DQ56 DQ61 182
DDR_B_D57 183 184
DQ57 VSS47
1

0.1U_0402_16V4Z
C2042

2.2U_0603_6.3V6K
C2043

185 186 DDR_B_DQS#7

VSS48 DQS#7
1

R2028 DDR_B_DM7 187 188 DDR_B_DQS7

10K_0402_5% DM7 DQS7
189 VSS49 VSS50 190
DDR_B_D58 191 192 DDR_B_D62
2

DDR_B_D59 DQ58 DQ62 DDR_B_D63

193 194
2

DQ59 DQ63
195 VSS51 VSS52 196
197 SA0 EVENT# 198
199 200 D_CK_SDATA
VDDSPD SDA D_CK_SDATA 11,14
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 11,14
+0.75VS 203 VTT1 VTT2 204 +0.75VS
A A
1

205 G1 G2 206
R2029
10K_0402_5% FOX_AS0A621-U4SG-7H
SP07000NN00
2

<Address: 01> Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

DIMM_B Standard type H:4mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 12 of 57
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1 CMOS
For re-chareable RTC W=20mils trace width 10mil W=20mils
1 2 PCH_RTCX2
R91 10M_0402_5% +CHGRTC +RTCVCC
+RTCBATT

SHORT PADS
JCMOS1
RTC BAT and 1K ohm D1
+RTCVCC 2
1 are at Power page

1
32.768KHZ_12.5PF_Q13MC14610002
1

4
C126 1
Y1 1U_0603_10V4Z @
OSC

OSC

2
2
18P_0402_50V8J

1 2 PCH_RTCRST# 3
R93 20K_0402_5% 1
1 1 1 2 PCH_SRTCRST# BAS40-04_SOT23-3 C127
C129 R94 20K_0402_5% 1U_0603_10V4Z
NC

NC
1

1
SHORT PADS
JME1
C128 18P_0402_50V8J
C130 Place C127 close to PCH. 2
2

2 2 1U_0603_10V4Z @

2
2

D D

ME +3VS
+RTCVCC

R96 1 2 1M_0402_5% SM_INTRUDER# SERIRQ R97 2 1 10K_0402_5%

R98 1 2 330K_0402_5% PCH_INTVRMEN U3A PCH_SATALED# R99 2 1 10K_0402_5%

PCH_RTCX1 LPC_AD0 PCH_GPIO21 R129 1 10K_0402_5%

INTVRMEN A20 RTCX1 FWH0 / LAD0 C38
A38 LPC_AD1
LPC_AD0 41 2

LPC
FWH1 / LAD1 LPC_AD1 41
H：Integrated VRM enable PCH_RTCX2 C20 B37 LPC_AD2 PCH_GPIO19 R394 2 1 4.7K_0402_5%
* L：Integrated VRM disable
RTCX2 FWH2 / LAD2
FWH3 / LAD3 C37 LPC_AD3
LPC_AD2
LPC_AD3
41
41
PCH_RTCRST# D20 Debug Port DG 1.2 PH 4.7K +3VS need to check
RTCRST# LPC_FRAME#
(INTVRMEN should always be pull high.) FWH4 / LFRAME# D36 LPC_FRAME# 41
PCH_SRTCRST# G22 SRTCRST#
E36

RTC
SM_INTRUDER# LDRQ0#
K22 INTRUDER# LDRQ1# / GPIO23 K36
+3VS
PCH_INTVRMEN C17 V5 SERIRQ
R102 1 @ 2 1K_0402_5% HDA_SPKR INTVRMEN SERIRQ SERIRQ 41
SPI ROM FOR ME ( 4MByte )
HIGH= Enable ( No Reboot ) AM3 +3VS
SATA0RXN SATA_DTX_C_PRX_N0 38
LOW= Disable (Default) HDA_BIT_CLK N34 AM1
* HDA_BCLK SATA0RXP SATA_DTX_C_PRX_P0 38

SATA 6G
AP7 HDD If use SPI programmer, PCH_SPI_WP# R103 1 2 3.3K_0402_5%
SATA0TXN SATA_PTX_DRX_N0 38
HDA_SYNC L34 AP5
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 38 R854 should be open
46 HDA_SPKR
HDA_SPKR T10 SPKR SATA1RXN AM10 (Normal is pop) PCH_SPI_HOLD# R104 1 2 3.3K_0402_5%
SATA1RXP AM8
HDA_RST# K34 AP11
+3VALW_PCH @ R105 HDA_RST# SATA1TXN +3VS R106 +3V_DSW_SPI
1K_0402_5% SATA1TXP AP10
0_0402_5%
Please short PJP35
2 1 HDA_SDOUT 46 HDA_SDIN0 HDA_SDIN0 E34 AD7 1 2
R108 HDA_SDIN0 SATA2RXN
SATA2RXP AD5 C131
0_0402_5% G34 AH5 D6 PCH_SPI_SO 1 2 PCH_SPI_SO_R
HDA_SDIN1 SATA2TXN R107 0_0402_5%
41 HDA_SDO 2 1 SATA2TXP AH4 2 1 1 2
C34 @ U4 CONN@

IHDA
HDA_SDIN2 RB751V-40_SOD323-2
0.1U_0402_16V4Z
C
HDA_SDO A34
SATA3RXN AB8
AB10
8 VCC VSS 4
C

HDA_SDIN3 SATA3RXP PCH_SPI_WP#

ME debug mode,this signal has a weak internal PD SATA3TXN AF3 9/06 SM50 3 W
Low = Disabled (Default) AF1
* High = Enabled [Flash Descriptor Security Overide] HDA_SDOUT A36
SATA3TXP PCH_SPI_HOLD# 7

SATA
HDA_SDO HOLD
SATA4RXN Y7
Y5 PCH_SPI_CS# 1 2 PCH_SPI_CS#_R 1
SATA4RXP R109 0_0402_5% S
C36 HDA_DOCK_EN# / GPIO33 SATA4TXN AD3
AD1 PCH_SPI_CLK 1 2 PCH_SPI_CLK_R 6
SATA4TXP R110 0_0402_5% C
N32 HDA_DOCK_RST# / GPIO13
Y3 PCH_SPI_SI 1 2 PCH_SPI_SI_R 5 2 PCH_SPI_SO_R
+3VALW_PCH R113 SATA5RXN R111 0_0402_5% D Q
SATA5RXP Y1
51_0402_5% AB3 WIESO_G6179-100000
R112 HDA_SYNC PCH_JTAG_TCK SATA5TXN
2 1 1K_0402_5% 2 1 J3 JTAG_TCK SATA5TXP AB1
+1.05VS_VCC_SATA
SP07000OJ00
This signal has a weak internal pull-down PCH_JTAG_TMS H7 Y11 R114

JTAG
PAD T1 JTAG_TMS SATAICOMPO 37.4_0402_1% SPI ROM Socket
PAD PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
On Die PLL VR Select is supplied by T2 JTAG_TDI SATAICOMPI
1.5V when sampled high PCH_JTAG_TDO H1 @ C132 @ R115
* 1.8V when sampled low
PAD T9 JTAG_TDO
SATA3RCOMPO AB12 R116 +1.05VS_SATA3 22P_0402_50V8J 33_0402_5% &U1
Needs to be pulled High for Huron River platfrom
49.9_0402_1% 2 1 1 2PCH_SPI_CLK_R
AB13 SATA3_COMP 1 2
SATA3COMPI
Reserve for EMI please close to UH1
PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
SPI_CLK SATA3RBIAS R117 750_0402_1% 45@ S IC FL 32M W25Q32BVSSIG SOIC 8P SPI ROM
PCH_SPI_CS# Y14 SPI_CS0#
SA00003K800
T1
SPI

R119 SPI_CS1# PCH_SATALED#

SATALED# P3 PCH_SATALED# 42
33_0402_5%
46 HDA_BITCLK_AUDIO 1 2 HDA_BIT_CLK PCH_SPI_SI V4 SPI_MOSI SATA0GP / GPIO21 V14 PCH_GPIO21

PCH_SPI_SO U3 P1 PCH_GPIO19 PAD

SPI_MISO SATA1GP / GPIO19 T7
R125
33_0402_5% COUGARPOINT_FCBGA989~D
B B
46 HDA_RST#_AUDIO 1 2 HDA_RST#
R128
33_0402_5%
46 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_R

SM50 @ 1 2 HDA_BITCLK_AUDIO
C133 22P_0402_50V8J
@ 1 2 HDA_SDOUT_AUDIO
C134 22P_0402_50V8J

Prevent back drive issue.

+3VS
From JM50
2
G

Prevent back drive issue. Q7

BSS138_NL_SOT23-3
+3VS 3 1HDA_SYNC
S

D
2
G

Q4
BSS138_NL_SOT23-3
HDA_SDOUT_R 3 1HDA_SDOUT 46 HDA_SYNC_AUDIO 1 2
S

@ R123
0_0402_5%
1 2

@ R100
0_0402_5% DG1.5, potential leakage concern
A A
10/11 move 33 ohm and 1M ohm to sub board

Security Classification Compal Secret Data

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 13 of 57
5 4 3 2 1
 5 4 3 2 1

U3B +3VALW_PCH

46 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 PCH_SMBCLK R137 1 2 2.2K_0402_5%

PCIE_PRX_DTX_P1 PERN1 LID_SW_OUT#
46 PCIE_PRX_DTX_P1 BJ34 PERP1 SMBALERT# / GPIO11 E12 LID_SW_OUT# 41
PCIE LAN C135 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32 PCH_SMBDATA R138 1 2 2.2K_0402_5%
46 PCIE_PTX_C_DRX_N1 PETN1
C136 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32 H14 PCH_SMBCLK
46 PCIE_PTX_C_DRX_P1 PETP1 SMBCLK PCH_SMBCLK 39
PCH_SML0CLK R139 1 2 2.2K_0402_5%
39 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA
PERN2 SMBDATA PCH_SMBDATA 39
39 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_P2 BF34 PCH_SML0DATA R140 1 2 2.2K_0402_5%
C137 PCIE_PTX_DRX_N2 PERP2
Wireless LAN 39 PCIE_PTX_C_DRX_N2 1 2 0.1U_0402_10V7K BB32 PETN2
C138 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 PCH_SML1CLK R141 1 2 2.2K_0402_5%

SMBUS
39 PCIE_PTX_C_DRX_P2 PETP2
SML0ALERT# / GPIO60 A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 6,7
40 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 BG36 PCH_SML1DATA R142 1 2 2.2K_0402_5%
PCIE_PRX_DTX_P3 PERN3 PCH_SML0CLK
40 PCIE_PRX_DTX_P3 BJ36 PERP3 SML0CLK C8
Card Reader C212 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N3 AV34 PCH_GPIO74 R143 1 2 10K_0402_5%
40 PCIE_PTX_C_DRX_N3 PETN3
C213 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P3 AU34 G12 PCH_SML0DATA check: no need to pull high?
40 PCIE_PTX_C_DRX_P3 PETP3 SML0DATA PCH_GPIO47 R144 1 2 10K_0402_5%
D D
44 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_N4 BF36
PCIE_PRX_DTX_P4 PERN4 LID_SW_OUT# R145 10K_0402_5%
44 PCIE_PRX_DTX_P4 BE36 PERP4 1 2
USB3.0 C214 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_GPIO74
44 PCIE_PTX_C_DRX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
C215 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 BB34 DRAMRST_CNTRL_PCH R146 1 2 1K_0402_5%
44 PCIE_PTX_C_DRX_P4 PETP4
E14 PCH_SML1CLK

PCI-E*
SML1CLK / GPIO58
BG37 PERN5
BH37 M16 PCH_SML1DATA
PERP5 SML1DATA / GPIO75
AY36 PETN5
BB36 PETP5 +3VS
BJ38 PERN6
BG38 R147

Controller
PERP6 Q8A 4.7K_0402_5%
AU36 PETN6 CL_CLK1 M7

2
AV36 2N7002KDWH_SOT363-6 1 2 +3VS
PETP6

Link
BG40 T11 PCH_SMBDATA 6 1 D_CK_SDATA D_CK_SDATA 11,12
PERN7 CL_DATA1
BJ40 PERP7
AY40 PETN7 1 2
BB40 P10 R396 0_0402_5% R148
PETP7 CL_RST1# @ 4.7K_0402_5%

5
BE38 PERN8 1 2 +3VS
BC38 PERP8
AW38 PCH_SMBCLK 3 4 D_CK_SCLK D_CK_SCLK 11,12
PETN8 Q8B
AY38 PETP8 2N7002KDWH_SOT363-6
PEG_A_CLKRQ# / GPIO47 M10 PCH_GPIO47 1 2
Y40 R397 0_0402_5%
CLKOUT_PCIE0N @
Y39 CLKOUT_PCIE0P
AB37

CLOCKS
PCH_GPIO73 CLKOUT_PEG_A_N
J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38
+3VS
R149 2 1 0_0402_5% CLK_MINI1# AB49 AV22 CLK_CPU_DMI#
39 CLK_PCIE_MINI1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5
R150 2 1 0_0402_5% CLK_MINI1 AB47 AU22 CLK_CPU_DMI Pull up at EC side.
39 CLK_PCIE_MINI1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
Wireless LAN Q9A

2
39 MINI1_CLKREQ# M1 2N7002KDWH_SOT363-6
PCIECLKRQ1# / GPIO18 CLK_DP#
CLKOUT_DP_N / CLKOUT_BCLK1_N AM12 CLK_DP# 5
C AM13 CLK_DP PCH_SML1DATA 6 1 EC_SMB_DA2 EC_SMB_DA2 22,41 C
CLKOUT_DP_P / CLKOUT_BCLK1_P CLK_DP 5
R151 2 1 0_0402_5% CLK_USB30# AA48
44 CLK_PCIE_USB30# CLKOUT_PCIE2N
USB3.0 R152 2 1 0_0402_5% CLK_USB30 AA47 1 2
44 CLK_PCIE_USB30 CLKOUT_PCIE2P
BF18 CLK_BUF_CPU_DMI# R398 0_0402_5%
CLKIN_DMI_N

5
44 USB30_CLKREQ# V10 BE18 CLK_BUF_CPU_DMI @
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
PCH_SML1CLK 3 4 EC_SMB_CK2 EC_SMB_CK2 22,41
R153 1 2 0_0402_5% CLK_LAN# Y37 BJ30 CLKIN_DMI2# Q9B
46 CLK_PCIE_LAN# CLKOUT_PCIE3N CLKIN_DMI2_N
PCIE LAN R154 1 2 0_0402_5% CLK_LAN Y36 BG30 CLKIN_DMI2 2N7002KDWH_SOT363-6
46 CLK_PCIE_LAN CLKOUT_PCIE3P CLKIN_DMI2_P
1 2
46 LAN_CLKREQ# A8 R399 0_0402_5%
PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M# @
CLKIN_DOT_96N G24
E24 CLK_BUF_DREF_96M
R333 CLK_CARD# CLKIN_DOT_96P
40 CLK_PCIE_CARD# 1 2 0_0402_5% Y43 CLKOUT_PCIE4N
Card Reader R334 1 2 0_0402_5% CLK_CARD Y45 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
40 CLK_PCIE_CARD CLKOUT_PCIE4P
AK7 CLK_BUF_PCIE_SATA# CLK_BUF_CPU_DMI R156 1 2 10K_0402_5%
R338 PCH_GPIO26 CLKIN_SATA_N / CKSSCD_N CLK_BUF_PCIE_SATA
40 CARD_CLKREQ# 1 2 0_0402_5% L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P AK5
CLKIN_DMI2# R157 1 2 10K_0402_5%
CLKIN_DMI2 R158 1 2 10K_0402_5%
V45 K45 CLK_BUF_ICH_14M
CLKOUT_PCIE5N REFCLK14IN CLK_BUF_DREF_96M# R161 10K_0402_5%
V46 CLKOUT_PCIE5P 1 2
CLK_BUF_DREF_96M R162 1 2 10K_0402_5%
PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK 17
CLK_BUF_PCIE_SATA# R163 1 2 10K_0402_5%
CLK_BUF_PCIE_SATA R164 1 2 10K_0402_5%
R159 1 2 0_0402_5% CLK_VGA# AB42 V47 XTAL25_IN
22 CLK_PEG_VGA# CLKOUT_PEG_B_N XTAL25_IN
R160 1 2 0_0402_5% CLK_VGA AB40 V49 XTAL25_OUT CLK_BUF_ICH_14M R167 1 2 10K_0402_5%
22 CLK_PEG_VGA CLKOUT_PEG_B_P XTAL25_OUT
PEG_CLKREQ#_R E6 R168 +1.05VS_VCCDIFFCLKN
PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
XCLK_RCOMP
V40 CLKOUT_PCIE6N
V42 XTAL25_IN
CLKOUT_PCIE6P
PCH_GPIO45 T13 XTAL25_OUT 1 2
PCIECLKRQ6# / GPIO45 R169 1M_0402_5%
V38 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 K43 CLK_FLEX0 T8 PAD
FLEX CLOCKS

V37 Y2
B CLKOUT_PCIE7P CLK_27M_TCLK_R R170 2 @ B
CLKOUTFLEX1 / GPIO65 F47 1 22_0402_5% CLK_27M_TCLK 22 2 1
PCH_GPIO46 K12 PCIECLKRQ7# / GPIO46
CLKOUTFLEX2 / GPIO66 H47 CLK_48M_USB3_PCH_R R173 2 @ 1 22_0402_5% CLK_48M_USB3_PCH 44 1 25MHZ_20PF_7A25000012 1
PAD T88 CLK_BCLK_ITP# AK14
CLK_BCLK_ITP CLKOUT_BCLK0_N / CLKOUT_PCIE8N
PAD T89 AK13 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67 K49 DGPU_PRSNT# C143 C144
18P_0402_50V8J 18P_0402_50V8J
2 2
COUGARPOINT_FCBGA989~D

@ R175 @ C145
33_0402_5% 22P_0402_50V8J
+3VS CLK_BUF_ICH_14M 2 1 1 2

1
+3VS @ R178 @ C146
R382 33_0402_5% 22P_0402_50V8J
R174 2 1 10K_0402_5% MINI1_CLKREQ# 10K_0402_5% CLK_PCI_LPBACK 2 1 1 2
UMA@
R176 2 1 10K_0402_5% USB30_CLKREQ#
VGA_ON 17,45,55

2
+3VALW_PCH DGPU_PRSNT# Reserve for EMI please close to U60
+3VALW_PCH

2
1

R383
R179 10K_0402_5%
R180 2 1 10K_0402_5% PCH_GPIO73
10K_0402_5%
OPT@ Compal Electronics, Inc.
1
R181 2 1 10K_0402_5% LAN_CLKREQ#
2

Q16
2

R182 1 10K_0402_5% PCH_GPIO26 2N7002H_SOT23-3

G

2
OPT@ R379 Pull high at VGA side
R183 2 1 10K_0402_5% PCH_GPIO44 PEG_CLKREQ#_R 1 3 1 2
GPIO67
PEG_CLKREQ# 22 DGPU_PRSNT#
0_0402_5%
D

S
1

R184 2 1 10K_0402_5% PCH_GPIO45 OPT@

R381 R380
R185 2 1 10K_0402_5% PCH_GPIO46 for safe @ @
OPTIMUS 0
2.2K_0402_5% 2.2K_0402_5%
A
UMA 1 A
2

Security Classification Compal Secret Data

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 14 of 57
5 4 3 2 1
 5 4 3 2 1

D D
+RTCVCC

U3C DSWODVREN R187 2 1 330K_0402_5%

4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 4 R188 2 @ 1 330K_0402_5%

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1
4 DMI_CTX_PRX_N1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_CTX_PRX_N1 4
4 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 4 DSWODVREN - On Die DSW VR Enable
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3
BG20 BH13 H：Enable
4 DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3
FDI_RXN4 BC12 FDI_CTX_PRX_N4
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
4
4
* L：Disable
4 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 FDI_CTX_PRX_N5 4
DMI_CTX_PRX_P1 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N6
4 DMI_CTX_PRX_P1 BC20 DMI1RXP FDI_RXN6 BG10 FDI_CTX_PRX_N6 4
4 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 4
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7
4 DMI_CTX_PRX_P3 BJ20 DMI3RXP
R186 @ BG14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 4
0_0402_5% DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1
4 DMI_CRX_PTX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 4
2 1 DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 +3VALW_PCH
4 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 4
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 4
4 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 WAKE# R193 1 2 10K_0402_5%

DMI
FDI
4 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 4
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 4
+3VS DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6 PCH_GPIO29 R196
4 DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 4 1 2 10K_0402_5%
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 4
4 DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7
DMI_CRX_PTX_P2 AY18
4 DMI_CRX_PTX_P2 DMI2TXP
5

10/11 U7 DMI_CRX_PTX_P3 AU18

4 DMI_CRX_PTX_P3 DMI3TXP +3VS
AW16 FDI_INT
VCC

FDI_INT FDI_INT 4
41 PCH_PWROK 1 R389 1 2 8.2K_0402_5%
IN1 SYS_PWROK +1.05VS_VCCP FDI_FSYNC0
OUT 4 BJ24 DMI_ZCOMP FDI_FSYNC0 AV12 FDI_FSYNC0 4
2
GND

54 VGATE IN2
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 PCH_GPIO32 R198 1 @ 2 10K_0402_5%
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 4
R189 49.9_0402_1%
MC74VHC1G08DFT2G_SC70-5 1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
FDI_LSYNC0 4
3

C R190 750_0402_1% DMI2RBIAS FDI_LSYNC0 EC team suggestion C

4mil width and place BB10 FDI_LSYNC1 South Bridge side must have
FDI_LSYNC1 FDI_LSYNC1 4
within 500mil of the PCH pull-low 10K on this pin(GPIO32)
R191 2 1 10K_0402_5% SYS_PWROK

A18 DSWODVREN
DSWVRMEN

System Power Management

not support Deep S4,S5 DPWROK mux with PWROK
SUSACK#_R C12 E22 PCH_RSMRST#_R check list1.0 P.42
SUSACK# DPWROK R195
0_0402_5%
5 XDP_DBRESET# 1 2 XDP_DBRESET#_R K3 SYS_RESET# WAKE# B9 WAKE# 1 2 PCH_PCIE_WAKE# 39,44,46
R194 0_0402_5%
R197
0_0402_5% SYS_PWROK P12 N3 PCH_GPIO32
SUSACK#_R SUSWARN#_R SYS_PWROK CLKRUN# / GPIO32
2 1
@
PCH_PWROK 1 2 PCH_PWROK_R L22 G8 SUS_STAT# T10 PAD
R199 0_0402_5% PWROK SUS_STAT# / GPIO61
R201 0_0402_5%
L10 N14 SUSCLK 2 1
APWROK SUSCLK / GPIO62 SUSCLK_R 41
T11 PAD
PM_DRAM_PWRGD B13 D10 PM_SLP_S5#
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 41
T12 PAD
41 PCH_RSMRST# 1 2 PCH_RSMRST#_R C21 H4 PM_SLP_S4#
+3VS RSMRST# SLP_S4# PM_SLP_S4# 41
R202 0_0402_5%
T13 PAD
R203 2 1 200_0402_5% PM_DRAM_PWRGD SUSWARN#_R K16 F4 PM_SLP_S3#
SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# 41

B PBTN_OUT#_R SLP_A# T91 PAD Can be left NC when IAMT is not B

41 PBTN_OUT# 1 2 E20 PWRBTN# SLP_A# G10
R205 0_0402_5% support on the platfrom
D3
+3VALW_PCH 1 2 PCH_ACIN H20 G16 T14 PAD not support Deep S4,S5 can NC
41,45,48 ACIN ACPRESENT / GPIO31 SLP_SUS#
PCH EDS1.2 P.74
RB751V-40_SOD323-2 T15 PAD
PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
R206 2 1 10K_0402_5% SUSWARN#_R

R207 2 1 200K_0402_5% PCH_ACIN RI# A10 K14 PCH_GPIO29

RI# SLP_LAN# / GPIO29
R208 2 1 10K_0402_5% PCH_GPIO72
COUGARPOINT_FCBGA989~D
R209 2 1 10K_0402_5% RI#

R210 2 1 10K_0402_5% PCH_RSMRST#_R

No30

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 15 of 57
5 4 3 2 1
 5 4 3 2 1

D D

Pull high at LVDS conn side. U3D

IGPU_BKLT_EN J47 AP43
L_BKLTEN SDVO_TVCLKINN
34 PCH_ENVDD M45 L_VDD_EN SDVO_TVCLKINP AP45

34 DPST_PWM P45 L_BKLTCTL SDVO_STALLN AM42

SDVO_STALLP AM40
34 PCH_LCD_CLK T40 L_DDC_CLK
34 PCH_LCD_DATA K47 L_DDC_DATA SDVO_INTN AP39
SDVO_INTP AP40
CTRL_CLK T45 SDVO_CTRLDATA strap pull high
CTRL_DATA L_CTRL_CLK
P39
2.37K_0402_1% L_CTRL_DATA at level shift page
IGPU_BKLT_EN R215 1 2 0_0402_5% ENBKL R212 2 1 LVDS_IBG AF37 P38 SDVO_SCLK
ENBKL 41 LVD_IBG SDVO_CTRLCLK SDVO_SCLK 36
AF36 M39 SDVO_SDATA
LVD_VBG SDVO_CTRLDATA SDVO_SDATA 36
2

0_0402_5% LVD_VREF AE48

R211 R214 LVD_VREFH
2 1 AE47 LVD_VREFL DDPB_AUXN AT49
100K_0402_5% DDPB_AUXP AT47
DDPB_HPD AT40 PCH_DPB_HPD PCH_DPB_HPD 36
PCH_TXCLK- AK39

LVDS
34 PCH_TXCLK-
1

PCH_TXCLK+ LVDSA_CLK# PCH_DPB_N0

34 PCH_TXCLK+ AK40 LVDSA_CLK DDPB_0N AV42 PCH_DPB_N0 36
C PCH_DPB_P0 C
PCH_TXOUT0- DDPB_0P AV40
PCH_DPB_N1
PCH_DPB_P0 36 HDMI D2
34 PCH_TXOUT0- AN48 LVDSA_DATA#0 DDPB_1N AV45 PCH_DPB_N1 36
PCH_TXOUT1- PCH_DPB_P1

Digital Display Interface

34 PCH_TXOUT1-
PCH_TXOUT2-
AM47 LVDSA_DATA#1 DDPB_1P AV46
PCH_DPB_N2
PCH_DPB_P1 36 HDMI D1
34 PCH_TXOUT2- AK47 LVDSA_DATA#2 DDPB_2N AU48 PCH_DPB_N2 36
AJ48 AU47 PCH_DPB_P2 PCH_DPB_P2 36 HDMI D0
LVDSA_DATA#3 DDPB_2P PCH_DPB_N3
DDPB_3N AV47 PCH_DPB_N3 36
PCH_TXOUT0+ AN47 AV49 PCH_DPB_P3 PCH_DPB_P3 36 HDMI CLK
34 PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P
PCH_TXOUT1+ AM49
34 PCH_TXOUT1+ LVDSA_DATA1
PCH_TXOUT2+ AK49
34 PCH_TXOUT2+ LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42

AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
+3VS AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
R220 1 2 2.2K_0402_5% CTRL_CLK AF47 BA48
LVDSB_DATA2 DDPC_2P
AF43 LVDSB_DATA3 DDPC_3N BB47
R221 1 2 2.2K_0402_5% CTRL_DATA BB49
DDPC_3P

PCH_CRT_B N48 M43

35 PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
PCH_CRT_G P49 M36
35 PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
PCH_CRT_R T49
35 PCH_CRT_R CRT_RED
AT45

CRT
B PCH_CRT_CLK DDPD_AUXN B
35 PCH_CRT_CLK T39 CRT_DDC_CLK DDPD_AUXP AT43
PCH_CRT_DATA M40 BH41
35 PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD
+3VS BB43
PCH_CRT_HSYNC DDPD_0N
35 PCH_CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
R222 1 2 2.2K_0402_5% PCH_CRT_CLK 35 PCH_CRT_VSYNC PCH_CRT_VSYNC M49 BF44
CRT_VSYNC DDPD_1N
DDPD_1P BE44
R223 1 2 2.2K_0402_5% PCH_CRT_DATA BF42
CRT_IREF DDPD_2N
T43 DAC_IREF DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42
1

1
R224 1 2 150_0402_1% PCH_CRT_B
R226 COUGARPOINT_FCBGA989~D
R227 1 2 150_0402_1% PCH_CRT_G R225 0_0402_5%
1K_0402_0.5%
R228 1 2 150_0402_1% PCH_CRT_R
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 16 of 57
5 4 3 2 1
 5 4 3 2 1

U3E
NV_CE#0 AY7
NV_CE#1 AV7
BG26 TP1 NV_CE#2 AU3
footprint should change to RP_0804_8P4R BJ26 BG4
+3VS TP2 NV_CE#3
because RP_8P4R doesn't exist BH25 TP3
BJ16 TP4 NV_DQS0 AT10
R229 BG16 BC8
PCI_PIRQA# TP5 NV_DQS1
8 1 AH38 TP6
7 2 PCI_PIRQD# AH37 AU2
PCI_PIRQC# TP7 NV_DQ0 / NV_IO0
6 3 AK43 TP8 NV_DQ1 / NV_IO1 AT4
D PCI_PIRQB# D
5 4 AK45 TP9 NV_DQ2 / NV_IO2 AT3
C18 TP10 NV_DQ3 / NV_IO3 AT1
8.2K_8P4R_5% N30 AY3
TP11 NV_DQ4 / NV_IO4
H3 TP12 NV_DQ5 / NV_IO5 AT5
R230 AH12 AV3

NVRAM
PCH_GPIO55 TP13 NV_DQ6 / NV_IO6
8 1 AM4 TP14 NV_DQ7 / NV_IO7 AV1
7 2 PCH_GPIO51 AM5 BB1
PCH_GPIO5 TP15 NV_DQ8 / NV_IO8
6 3 Y13 TP16 NV_DQ9 / NV_IO9 BA3
5 4 PCH_GPIO52 K24 BB5
TP17 NV_DQ10 / NV_IO10
L24 TP18 NV_DQ11 / NV_IO11 BB3
8.2K_8P4R_5% AB46 BB7
TP19 NV_DQ12 / NV_IO12
AB45 BE8

RSVD
R231 TP20 NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14 BD4
8 1 PCH_GPIO2 BF6
NV_DQ15 / NV_IO15
7 2 No28
6 3 PCH_GPIO4 B21 AV5
PCH_GPIO3 TP21 NV_ALE DF_TVS
5 4 M20 TP22 NV_CLE AY1
AY16 TP23
8.2K_8P4R_5% BG46 AV10
TP24 NV_RCOMP

NV_RB# AT8
DMI Termination Voltage
BE28 TP25 NV_RE#_WRB0 AY5
R233 1 2 8.2K_0402_5% PCH_GPIO53 BC30 BA2 Set to Vcc when HIGH
TP26 NV_RE#_WRB1
BE32 TP27 DF_TVS
BJ32 TP28 NV_WE#_CK0 AT12 Set to Vss when LOW
10/2 BC28 TP29 NV_WE#_CK1 BF3
BE30 TP30
BF32 +1.8VS
R234 TP31
1 2 8.2K_0402_5% DGPU_HOLD_RST# BG32 TP32 USBP0N C24 USB20_N0
USB20_N0 46
AV26 A24 USB20_P0 USB conn (left)
TP33 USBP0P USB20_P0 46

1
BB26 C25 USB20_N1
C TP34 USBP1N USB20_N1 37 C
R388 1 2 100K_0402_5% PLT_RST# AU28 B25 USB20_P1 USB conn (left) DG1.2
TP35 USBP1P USB20_P1 37 2.2K_0402_5%
AY30 TP36 USBP2N C26
AU26 A26 R235
TP37 USBP2P
AY26 K28

2
TP38 USBP3N DF_TVS
AV28 TP39 USBP3P H28 2 R236 1 H_SNB_IVB# 5
AW30 E28 1K_0402_5%
TP40 USBP4N
USBP4P D28
USBP5N C28 CLOSE TO THE BRANCHING POINT
USBP5P A28
USBP6N C29
USBP6P B29
PCI_PIRQA# K40 N28 PCH HM65 config not support USB port 6 & 7.
PCI_PIRQB# PIRQA# USBP7N
Boot BIOS Strap bit1 BBS1 K38 M28

PCI
PCI_PIRQC# PIRQB# USBP7P USB20_N8
H38 PIRQC# USBP8N L30 USB20_N8 39
Boot BIOS PCI_PIRQD# G38 K30 USB20_P8 Mini Card(WLAN) USB_OC0# R237 1 2 10K_0402_5%
PIRQD# USBP8P USB20_P8 39
G30 USB20_N9 USB_OC1# R238 1 2 10K_0402_5%
Bit11 Bit10 Destination USBP9N USB20_N9 39
R241 DGPU_HOLD_RST# C46 E30 USB20_P9 Mini Card(WWAN) USB_OC2# R239 1 2 10K_0402_5%

USB
REQ1# / GPIO50 USBP9P USB20_P9 39 +3VALW_PCH
0_0402_5% PCH_GPIO52 C44 C30 USB20_N10 USB_OC3# R240 1 2 10K_0402_5%
REQ2# / GPIO52 USBP10N USB20_N10 34
0 1 Reserved 2 1 VGA_ON_R E40 A30 USB20_P10 CMOS Camera (LVDS) USB_OC4# R242 1 2 10K_0402_5%
14,45,55 VGA_ON REQ3# / GPIO54 USBP10P USB20_P10 34
GNT1#/ L32 USB_OC5# R243 1 2 10K_0402_5%
PCH_GPIO51 USBP11N USB_OC6# R244 10K_0402_5%
GPIO51 1 0 PCI D47 GNT1# / GPIO51 USBP11P K32 1 2
PCH_GPIO53 E42 G32 USB20_N12 USB_OC7# R245 1 2 10K_0402_5%
GNT2# / GPIO53 USBP12N USB20_N12 39
1 1 SPI PCH_GPIO55 F46 E32 USB20_P12 Mini Card(SIM reserved)
GNT3# / GPIO55 USBP12P USB20_P12 39
C32 USB20_N13
USBP13N USB20_N13 40
0 0 LPC A32 USB20_P13 Bluetooth
USBP13P USB20_P13 40
PCH_GPIO2 G42
PCH_GPIO3 PIRQE# / GPIO2
PCH_GPIO4
G40 PIRQF# / GPIO3 USBRBIAS
Within 500 mils
C42 PIRQG# / GPIO4 USBRBIAS# C33 1 2
PCH_GPIO5 D44 R246 22.6_0402_1%
PIRQH# / GPIO5
RF Boris Tsai suggests USBRBIAS B33
PAD T16 K10
B PME# B
PLT_RST# C6 A14 USB_OC0# USB_OC0# 46 (For USB Port0)
5,40,41,44,46 PLT_RST# PLTRST# OC0# / GPIO59
CLK_PCI_LPBACK K20 USB_OC1# USB_OC1# 37 (For USB Port1)
OC1# / GPIO40 USB_OC2#
OC2# / GPIO41 B17 OC[0..3] use for EHCI 1
CLK_PCI_LPC R247 2 1 22_0402_5% CLK_PCI0 H49 C16 USB_OC3# OC[4..7] use for EHCI 2
14 CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
2 2 CLK_PCI_LPC R248 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4#
41 CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
PAD T17 CLK_PCI2 J48 A16 USB_OC5#
C216 C217 PAD T18 CLK_PCI3 CLKOUT_PCI2 OC5# / GPIO9 USB_OC6#
K42 CLKOUT_PCI3 OC6# / GPIO10 D14
10P_0402_50V8J 10P_0402_50V8J PAD T19 CLK_PCI4 H40 C14 USB_OC7#
@ 1 1 CLKOUT_PCI4 OC7# / GPIO14
@
No14
COUGARPOINT_FCBGA989~D

No40 R250
0_0402_5% @
No40 2 1
+3VS +3VS

U10
5

OPT@
5

R252 U11
VCC

PLT_RST# 1 100_0402_5%
VCC

IN1 PLT_RST#
OUT 4 1 2 PLTRST_VGA# 22 1 IN1
DGPU_HOLD_RST# 2 R232 1 2 OPT@ 4
GND

IN2 OUT PLT_RST_BUF# 39

0_0402_5% OPT@ 2
GND

IN2
1

MC74VHC1G08DFT2G_SC70-5 R253 R254

3

A 100K_0402_5% MC74VHC1G08DFT2G_SC70-5 100K_0402_5% A

3

OPT@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 17 of 57
5 4 3 2 1
 5 4 3 2 1

+3VS

R264 2 UMA@ 1 10K_0402_5% OPTIMUS_EN#

R393 1 OPT@ 2 10K_0402_5%

+3VS
GPIO28 GPIO38
On-Die PLL Voltage Regulator
This signal has a weak internal pull up OPTIMUS_EN#
PCH_GPIO68 R256 1 2 10K_0402_5%
D H：On-Die voltage regulator enable D
* L：On-Die PLL Voltage Regulator disable * OPTIMUS 0 PCH_GPIO69 R257 1 2 10K_0402_5%
+3VALW_PCH Non-OPTIMUS 1 PCH_GPIO70 R258 1 2 10K_0402_5%

R395 1 @ 2 4.7K_0402_5% PCH_GPIO71 R259 1 2 10K_0402_5%

R260 1 @ 2 1K_0402_5% PCH_GPIO28

Debug Port DG 1.2 PH 4.7K +3VALW_PCH +3VS

Can be configured as wake input to

EC_KBRST# R261 1 2 10K_0402_5%
allow wakes from Deep Sleep.
If not used then use 8.2-kΩ to 10-kΩ
pull-down to GND. U3F check: pull high?
PCH_GPIO0 T7 C40 PCH_GPIO68
R262 PCH_GPIO27 BMBUSY# / GPIO0 TACH4 / GPIO68
1 2 10K_0402_5% No26
No34 PCH_GPIO1 A42 B41 PCH_GPIO69
TACH1 / GPIO1 TACH5 / GPIO69
PCH_GPIO6 H36 C41 PCH_GPIO70 +3VS
TACH2 / GPIO6 TACH6 / GPIO70
41 EC_SCI# EC_SCI# E38 A40 PCH_GPIO71
TACH3 / GPIO7 TACH7 / GPIO71

2
41 EC_SMI# EC_SMI# C10 R263
GPIO8
10K_0402_5%
+3VS PCH_GPIO12 C4
C +3VS LAN_PHY_PWR_CTRL / GPIO12 C

1
+3VALW SMIB G2 P4
44 SMIB GPIO15 A20GATE GATEA20 41

2
R275 1 2 100K_0402_5% WWAN_OFF#
R391 1 @ 2 10K_0402_5% R267 AU16 PCH_PECI_R 1 @ 2

CPU/MISC
PECI H_PECI 5,41
10K_0402_5% PCH_GPIO16 U2 0_0402_5% R265
SATA4GP / GPIO16
2

R277 1 @ 2 200K_0402_5% PCH_GPIO36 RCIN# P5 EC_KBRST#

EC_KBRST# 41
R392 1 2 10K_0402_5% R273

GPIO
1
10K_0402_5% DGPU_PWROK D40 AY11
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 5
OPT@
1

D PCH_GPIO22 PCH_THRMTRIP#_R 1 H_THRMTRIP#

T5 AY10 2 H_THRMTRIP# 5
1

+VRAM_1.5VS Q17 SCLOCK / GPIO22 THRMTRIP# R268 390_0402_5%

2
1 G OPT@ PCH_GPIO24 E8 T14
GPIO36: CRB1.0 PH200K to +3VS, GPIO24 / MEM_LED INIT3_3V#
S INIT3_3V
3

but CHK1.2 says pull down when not used R130 OPT@ PCH_GPIO27 E16 GPIO27
10K_0402_5% 2N7002H_SOT23-3 This signal has weak internal
1 2 2 PCH_GPIO28 P8 GPIO28 PU, can't pull low
NC_1 AH8
1 Q5 39,40 BT_ON# BT_ON# K1
OPT@ 3 STP_PCI# / GPIO34
NC_2 AK11
C218 AP2302GN-HF_SOT23-3 PCH_GPIO35 K4
1U_0402_6.3V6K GPIO35
NC_3 AH10
OPT@ 2 PCH_GPIO36 V8 SATA2GP / GPIO36
+3VS AK10 Intel schematic reviwe recommand.
WWAN_OFF# NC_4
39 WWAN_OFF# M5 SATA3GP / GPIO37
NC_5 P37
OPTIMUS_EN# N2 SLOAD / GPIO38
R255 2 1 10K_0402_5% PCH_GPIO0 PCH_GPIO39 M3 SDATAOUT0 / GPIO39
PCH_GPIO48 V13 BG2 T20 PAD
SDATAOUT1 / GPIO48 VSS_NCTF_15
R270 1 2 10K_0402_5% PCH_GPIO1 WL_OFF# V3 BG48 T21 PAD
B 39 WL_OFF# SATA5GP / GPIO49 VSS_NCTF_16 B
R271 1 2 10K_0402_5% PCH_GPIO6 PCH_GPIO57 D6 BH3 T22 PAD
GPIO57 VSS_NCTF_17
R272 1 2 10K_0402_5% PCH_GPIO16 BH47 T23 PAD
VSS_NCTF_18
No20 PAD T73 A4 BJ4 T63 PAD
VSS_NCTF_1 VSS_NCTF_19
R274 1 2 10K_0402_5% PCH_GPIO22 PAD T74 A44 BJ44 T24 PAD
VSS_NCTF_2 VSS_NCTF_20
PAD T75 A45 BJ45 T25 PAD
VSS_NCTF_3 VSS_NCTF_21

NCTF
R276 1 2 10K_0402_5% PCH_GPIO39 PAD T76 A46 BJ46 T26 PAD
VSS_NCTF_4 VSS_NCTF_22
PAD T77 A5 BJ5 T64 PAD
VSS_NCTF_5 VSS_NCTF_23
PAD T78 A6 BJ6 T65 PAD
VSS_NCTF_6 VSS_NCTF_24
R278 1 2 10K_0402_5% BT_ON# PAD T79 B3 C2 T81 PAD
VSS_NCTF_7 VSS_NCTF_25
R279 1 2 10K_0402_5% PCH_GPIO48 PAD T80 B47 C48 T66 PAD
VSS_NCTF_8 VSS_NCTF_26
R280 1 2 10K_0402_5% WL_OFF# PAD T27 BD1 D1 T67 PAD
VSS_NCTF_9 VSS_NCTF_27
PAD T28 BD49 D49 T68 PAD
+3VALW_PCH VSS_NCTF_10 VSS_NCTF_28
PAD T29 BE1 E1 T69 PAD
R281 PCH_GPIO12 VSS_NCTF_11 VSS_NCTF_29
1 2 10K_0402_5%
PAD T30 BE49 E49 T70 PAD
R282 SMIB VSS_NCTF_12 VSS_NCTF_30
1 2 1K_0402_5%
PAD T31 BF1 F1 T71 PAD
R283 VSS_NCTF_13 VSS_NCTF_31
1 2 10K_0402_5% PCH_GPIO57 CRB1.0 PH10K to +3VALW
GPIO24 Unmultiplexed PAD T32 BF49 F49 T72 PAD
A R284 VSS_NCTF_14 VSS_NCTF_32 A
1 2 10K_0402_5% PCH_GPIO24 NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event. COUGARPOINT_FCBGA989~D

R285 1 2 10K_0402_5% PCH_GPIO35

10/2 JM50 install, SM50 uninstall

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 18 of 57
5 4 3 2 1
 5 4 3 2 1

PCH Power Rail Table

+1.05VS_VCCP +1.05VS_PCH U3G POWER +VCCADAC +3VS S0 Iccmax
L1 Voltage Rail Voltage Current (A)
JP3 @ 1300mA MBK1608221YZF_2P
2 1 +1.05VS_PCH AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23 VCCCORE[2] 1 1 1 V_PROC_IO 1.05 0.001

10U_0805_6.3V6M
C150

1U_0402_6.3V6K
C151

1U_0402_6.3V6K
C152

1U_0402_6.3V6K
C153

0.01U_0402_16V7K
C147

0.1U_0402_10V7K
C148
CRT
PAD-OPEN 4x4m 1 1 1 1 AD21 VCCCORE[3]
AD23 U47 C149
VCCCORE[4] VSSADAC

VCC CORE
AF21 10U_0805_6.3V6M V5REF 5 0.001
VCCCORE[5] 2 2 2
AF23 VCCCORE[6]
D 2 2 2 2 R286 +3VS D
AG21 VCCCORE[7]
AG23 0_0805_5% V5REF_Sus 5 0.001
VCCCORE[8] +VCCA_LVDS
AG24 VCCCORE[9] 1mA VCCALVDS AK36 1 2
AG26 VCCCORE[10]
AG27 VCCCORE[11] VSSALVDS AK37 Vcc3_3 3.3 0.266
AG29 VCCCORE[12]
AJ23

LVDS
VCCCORE[13]
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 VccADAC 3.3 0.001
AJ27 +1.8VS
VCCCORE[15] L2
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38
AJ31 0.1UH_MLF1608DR10KT_10%_1608 VccADPLLA 1.05 0.08
+1.05VS_VCCP +1.05VS_VCCDPLLEXP VCCCORE[17] +VCCTX_LVDS
60mA VCCTX_LVDS[3] AP36 2 1
1 1 1 0.1uH inductor, 200mA

22U_0805_6.3V6M
VCCTX_LVDS[4] AP37 VccADPLLB 1.05 0.08
R289 2 1 0_0603_5% +1.05VS_VCCDPLLEXP AN19 C154 C155
VCCIO[28] 0.01U_0402_16V7K 0.01U_0402_16V7K
2 2 2

C156
VccCore 1.05 1.3
PAD T37 +VCCAPLLEXP BJ22 R290 +3VS
VCCAPLLEXP 0_0805_5%
This pin can be left as no connect in V33 +3VS_VCC3_3_6 1 2 VccDMI 1.05 0.042

HVCMOS
VCC3_3[6]
AN16 VCCIO[15]
On-Die VR enabled mode (default). 1
AN17 VCCIO[16]
VccIO 1.05 2.925
V34 C157
VCC3_3[7]
0.1U_0402_10V7K
2 VccASW 1.05 1.01
AN21 VCCIO[17]
AN26 +VCCAFDI_VRM
VCCIO[18]
VccSPI 3.3 0.02
AN27 2925mA AT16 +VCCAFDI_VRM
VCCIO[19] VCCVRM[3]
+1.05VS_VCCP R291 +1.05VS_VCC_EXP AP21 +VCCP_VCCDMI R292 +1.05VS_VCCP VccDSW 3.3 0.003
C 0_0805_5% VCCIO[20] 0_0805_5% C
1 2 +1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 VccpNAND 1.8 0.19

DMI
+1.05VS_VCCP
10U_0805_6.3V6M
C159

1U_0402_6.3V6K
C160

1U_0402_6.3V6K
C161

1U_0402_6.3V6K
C162

1U_0402_6.3V6K
C163

1 1 1 1 1 AP24 R293

VCCIO
VCCIO[22] 0_0805_5% C158
AP26 20mA AB36 +1.05VS_VCC_DMI_CCI 1 2 1U_0402_6.3V6K VccRTC 3.3 6 uA
VCCIO[23] VCCIO[1] 2
2 2 2 2 2 1
AT24 VCCIO[24]
VccClkDMI C164 VccSus3_3 3.3 0.119
1U_0402_6.3V6K
2
AN33 VCCIO[25] VccDFTERM VccSusHDA 3.3 / 1.5 0.01
AN34 VCCIO[26] VCCPNAND[1] AG16
+3VS R294 +3VS_VCCA3GBG +VCCPNAND R295 +1.8VS
0_0805_5% 0_0805_5% VccVRM 1.8 / 1.5 0.16

NAND / SPI
1 2 +3VS_VCCA3GBG BH29 AG17 1 2
VCC3_3[3] 190mA VCCPNAND[2]
1
C165 VccCLKDMI 1.05 0.02
0.1U_0402_10V7K AJ16 1
VCCPNAND[3] C166
2 +VCCAFDI_VRM 0.1U_0402_10V7K VccSSC 1.05 0.095
AP16 VCCVRM[2]
VCCPNAND[4] AJ17
2
Place C167 Near BG6 pin
+1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VCCFDIPLL +3V_VCCPSPI
+1.05VS_VCCP R297 R298
1
1 2+1.05VS_VCCDPLL_FDI AP17 VCCIO[27]
0_0805_5% VccALVDS 3.3 0.001
FDI

@ C167 0_0805_5% V1 +3V_VCCPSPI 1 2 +3VS

1U_0402_6.3V6K 20mA VCCSPI
2 leakage PAW00 found VccTX_LVDS 1.8 0.06
+VCCP_VCCDMI AU20 VCCDMI[2] 1
C168
B COUGARPOINT_FCBGA989~D 1U_0402_6.3V6K B
2

+VCCAFDI_VRM
+1.5VS

R299 2 1 0_0603_5% +VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE

VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A A

0 ohm for current test: delete when phase B

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 19 of 57
5 4 3 2 1
 5 4 3 2 1

+3VS @ R301
Have internal VRM
0_0805_5% +1.05VS_VCCP@ R302
VCC3_3 = 266mA detal waiting for newest spec
1 2 0_0603_5%
2 1 +VCCACLK VCCDMI = 42mA detal waiting for newest spec
L3
10UH_LB2012T100MR_20% +5VALW R303
1 2 +3VS_VCC_CLKF33 0_0603_5% @
+3VALW_PCH R304 2 1
1 1
POWER +1.05VS_VCCP

10U_0805_10V4Z
C169

1U_0402_6.3V6K
C170
0_0603_5% U3J R305
1 2 +VCCPDSW 0_0603_5% Q12
+3VALW +1.05VS_VCCUSBCORE AO3413L_SOT23-3 +5VALW_PCH
1 AD49 VCCACLK VCCIO[29] N26 2 1
2 2
1
R306 1 @ 2 0_0603_5% C171 P26 3 1

D
0.1U_0402_10V7K VCCIO[30] C172
T16 VCCDSW3_3 3mA
2

0.1U_0402_10V7K
C174

20K_0402_5%
R307
D @ C173 P28 1U_0402_6.3V6K D

G
VCCIO[31]

1
0.1U_0402_10V7K 2
1

2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]

VCCIO[33] T29 45,46 PCH_PWR_EN#

+3VS_VCC_CLKF33 R308 +3VALW_PCH 2
T38

2
VCC3_3[5] 0_0603_5%
T23 +3V_VCCPUSB 2 1
+VCCAPLL_CPY_PCH BH23
119mA VCCSUS3_3[7]
VCCAPLLDMI2 +3VALW_PCH

0.1U_0402_10V7K
C175
T24 1 R310
@ R309 +VCCDPLL_CPY VCCSUS3_3[8] +5VALW_PCH +3VALW_PCH
1 +1.05VS_VCCP 1 2 0_0603_5% AL29 VCCIO[14]
0_0603_5%
C176 V23 +3V_VCCAUBG 2 1

USB
10U_0603_10V6M VCCSUS3_3[9]
1

2
+VCCSUS1 2 C177 D4
AL24 DCPSUS[3] VCCSUS3_3[10] V24
2 0.1U_0402_10V7K R311
1
P24 100_0402_5%
@ C178
@C178 VCCSUS3_3[6] 2 R312 +1.05VS_VCCP RB751V-40_SOD323-2
1U_0402_6.3V6K AA19 0_0603_5%

1
2 VCCASW[1] +1.05VS_VCCAUPLL +PCH_V5REF_SUS
VCCIO[34] T26 2 1
+1.05VS_VCCP R313 AA21 1010mA
VCCASW[2] 1
0_0805_5%
1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C179
VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2

22U_0603_6.3V6M
C180

22U_0603_6.3V6M
C181

Clock and Miscellaneous

AA26 VCCASW[4]
AN23 +VCCA_USBSUS @ C182 1 2 1U_0402_6.3V6K
DCPSUS[4]
AA27 VCCASW[5]
2 2 +3V_VCCPSUS
VCCSUS3_3[1] AN24
AA29 VCCASW[6]
+5VS +3VS
AA31 VCCASW[7]
AC26 P34 +PCH_V5REF_RUN R314 +3VALW_PCH
VCCASW[8] 1mA V5REF

2
C 0_0603_5% D5 C
1 1 1

1U_0402_6.3V6K
C183

1U_0402_6.3V6K
C184

1U_0402_6.3V6K
C185
AC27 2 1 R315
VCCASW[9] +3V_VCCPSUS 100_0402_5%
N20 1

PCI/GPIO/LPC
VCCSUS3_3[2] C186 RB751V-40_SOD323-2
AC29 VCCASW[10]
2 2 2 1U_0402_6.3V6K
N22

1
+1.05VS_VCCP VCCSUS3_3[3] +PCH_V5REF_RUN
AC31 VCCASW[11]
R316 L5 2 R317 +3VS
VCCSUS3_3[4] P20 1
0_0805_5% 10UH_LB2012T100MR_20% AD29 0_0805_5%
+VCCA_DPLL_L +1.05VS_VCCA_A_DPL VCCASW[12] C187
1 2 1 2 VCCSUS3_3[5] P22 2 1
AD31 1 1U_0603_10V6K
VCCASW[13] C188 2
1 2 +1.05VS_VCCA_B_DPL W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
L6 VCCASW[14] VCC3_3[1]
2 +3VS
220U_B2_2.5VM_R35
C189

1U_0402_6.3V6K
C191

220U_B2_2.5VM_R35
C190

1U_0402_6.3V6K
C192

10UH_LB2012T100MR_20% 1 1 W23 W16 R318

VCCASW[15] VCC3_3[8] 0_0603_5%
1 1
+ + W24 T34 +3VS_VCCPPCI 2 1
VCCASW[16] VCC3_3[4]
1
W26 C193
2 2 2 2 VCCASW[17] 0.1U_0402_10V7K
R319 +3VS
W29 VCCASW[18] 0_0603_5% 2
W31 AJ2 +VCC3_3_2 2 1
+1.05VS_VCCP R320 VCCASW[19] VCC3_3[2] +1.05VS_SATA3 R321 +1.05VS_VCCP
1
0_0603_5% W33 0_0805_5%
+VCCDIFFCLK VCCASW[20] C194
2 1 VCCIO[5] AF13 2 1
0.1U_0402_10V7K 1
+VCCRTCEXT 2
1 N16 DCPRTC
C196 1 AH13 C195
1U_0402_6.3V6K C197 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM +1.05VS_SATA3 2
Y49 VCCVRM[4] VCCIO[13] AH14
+1.05VS_VCCP R322 2 +1.05VS_VCCDIFFCLKN
0_0603_5% 2
B +1.05VS_VCCDIFFCLKN B
2 1 VCCIO[6] AF14
1 +1.05VS_VCCA_A_DPL BD47 Place C199 Near AK1 pin

SATA
VCCADPLLA 80mA +VCCSATAPLL
VCCAPLLSATA AK1
C198 +1.05VS_VCCA_B_DPL BF47 +VCCAFDI_VRM
1U_0402_6.3V6K VCCADPLLB 80mA
2 1
AF11 +VCCAFDI_VRM @ C199
+1.05VS_VCCP R323 +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA R324 +1.05VS_VCCP 10U_0603_10V6M
AF17 VCCIO[7]
0_0603_5% AF33 0_0805_5%
+1.05VS_SSCVCC VCCIO[8] +1.05VS_VCC_SATA 2
2 1 AF34 VCCIO[9]
55mA VCCIO[2] AC16 2 1
1 +1.05VS_VCCDIFFCLKN AG34 VCCIO[11]
C200
VccDIFFCLKN VCCIO[3] AC17 1
C201
1U_0402_6.3V6K +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
2 VCCIO[10] 95mA VCCIO[4]
2
+VCCSST
VccSSC +1.05VS_VCCP
V16 DCPSST
+1.05VM_VCCSUS 1

1 C202 +1.05VM_VCCSUS T17 T21 +VCCME_22 R326 2 1 0_0603_5%

C203 0.1U_0402_10V7K DCPSUS[1] VCCASW[22]
V19
MISC

@ 2 DCPSUS[2]
1U_0402_6.3V6K +1.05VS_VCCP R328 V21 +VCCME_23 R327 2 1 0_0603_5%
2 0_0603_5% VCCASW[23]
CPU

1 2 +V_CPU_IO BJ8 V_PROC_IO 1mA +VCCME_21 R329

leakage PAW00 found
VCCASW[21] T19 2 1 0_0603_5%
1 1 1
+RTCVCC +3VALW_PCH
4.7U_0603_6.3V6K
C204

0.1U_0402_10V7K
C205

0.1U_0402_10V7K
C206

RTC

A22 P32 +VCCSUSHDA R330 2 1 0_0603_5%

HDA

2 2 2 VCCRTC 10mA VCCSUSHDA

1U_0402_6.3V6K
C207

0.1U_0402_10V7K
C208

0.1U_0402_10V7K
C209

1 1 1 1
COUGARPOINT_FCBGA989~D C210
A 0.1U_0402_16V4Z A

2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2009/12/01 2010/12/31 Title
Issued Date Deciphered Date SCHEMATIC,MB LA-A7121
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 20 of 57
5 4 3 2 1
 5 4 3 2 1

U3I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
D U3H D
B15 VSS[164] VSS[264] K7
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
AA2 VSS[2] VSS[81] AK4 B31 VSS[168] VSS[268] L26
AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
AA33 VSS[4] VSS[83] AK46 B39 VSS[170] VSS[270] L36
AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF29 VSS[52] VSS[131] AT42 BH15 VSS[218] VSS[318] W27
AF31 VSS[53] VSS[132] AT46 BH17 VSS[219] VSS[319] W48
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF5 VSS[58] VSS[137] AV20 BH33 VSS[224] VSS[324] Y46
AF7 VSS[59] VSS[138] AV24 BH35 VSS[225] VSS[325] Y8
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
B B
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
AH36 VSS[67] VSS[146] AW2 D22 VSS[233] VSS[337] G14
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH42 VSS[70] VSS[149] AW28 D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
COUGARPOINT_FCBGA989~D G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
A A

COUGARPOINT_FCBGA989~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 21 of 57
5 4 3 2 1
 5 4 3 2 1

U1400A

DG: 0.1u*4, 10u*1, bead 30 ohm PEG_HTX_C_GRX_P0 AP17 Part 1 of 7 K1

PEG_HTX_C_GRX_N0 PEX_RX0 GPIO0 HPD_C HPD_C
AN17 PEX_RX0_N GPIO1 K2 1 OPT@ 2
10/11 check ok PEG_HTX_C_GRX_P1 AN19 K3 R1401 100K_0402_5%
PEG_HTX_C_GRX_N1 PEX_RX1 GPIO2
150mA AP19 PEX_RX1_N GPIO3 H3
L1400 OPT@ Layout note: Under GPU PEG_HTX_C_GRX_P2 AR19 H2
+PLLVDD PEG_HTX_C_GRX_N2 PEX_RX2 GPIO4 GPU_VID0
+1.05VS_DGPU 1 2 AR20 PEX_RX2_N GPIO5 H1 GPU_VID0 55
BLM18PG330SN1D_2P PEG_HTX_C_GRX_P3 AP20 H4 GPU_VID1
PEX_RX3 GPIO6 GPU_VID1 55

4700P_0402_25V7K
0.1U_0402_16V4Z

OPT@ C1402
0.1U_0402_16V4Z

OPT@ C1403
0.1U_0402_16V4Z

OPT@ C1404
0.1U_0402_16V4Z

OPT@ C1400
10U_0603_6.3V6M
PEG_HTX_C_GRX_N3 AN20 H5 GPU_VID2 55
PEX_RX3_N GPIO7

OPT@ C1401
1 1 1 1 2 PEG_HTX_C_GRX_P4 AN22 H6 OVERT#_VGA
PEX_RX4 GPIO8

1
C1596
PEG_HTX_C_GRX_N4 AP22 J7 THERM#_VGA
PEG_HTX_C_GRX_P5 PEX_RX4_N GPIO9
AR22 PEX_RX5 GPIO10 K4
PEG_HTX_C_GRX_N5 AR23 K5 R1496 No31

2
2 2 2 2 1 PEG_HTX_C_GRX_P6 PEX_RX5_N GPIO11 +3VSDGPU
10/5 JM50 2 OPT@ 1 0_0402_5% R1404

@
AP23 H7

GPIO
PEG_HTX_C_GRX_N6 PEX_RX6 GPIO12 10K_0402_5%
D AN23 PEX_RX6_N GPIO13 J4 D
PEG_HTX_C_GRX_P7 AN25 J6 2 OPT@ 1
PEG_HTX_C_GRX_N7 PEX_RX7 GPIO14 Q1400
AP25 PEX_RX7_N GPIO15 L1

2
G
PEG_HTX_C_GRX_P8 AR25 L2 OPT@
PEG_HTX_C_GRX_N8 PEX_RX8 GPIO16 R1497
AR26 PEX_RX8_N GPIO17 L4
PEG_HTX_C_GRX_P9 AP26 M4 2 1 NV_PERFORMANCE_R 3 1 NV_PERFORMANCE 41
PEG_HTX_C_GRX_N9 PEX_RX9 GPIO18 @ 0_0402_5%

D
AN26 PEX_RX9_N GPIO19 L7
PEG_HRX_GTX_N[0..15] PEG_HTX_C_GRX_P10 AN28 L5
4 PEG_HRX_GTX_N[0..15] PEX_RX10 GPIO20 Replace GPIO 12 with GPIO 18.
PEG_HTX_C_GRX_N10 AP28 K6 2N7002H_SOT23-3
PEG_HRX_GTX_P[0..15] PEG_HTX_C_GRX_P11 PEX_RX10_N GPIO21 When : B stage platforms
4 PEG_HRX_GTX_P[0..15] AR28 PEX_RX11 GPIO22 L6
PEG_HTX_C_GRX_N11 AR29 M6
PEG_HTX_C_GRX_N[0..15] PEG_HTX_C_GRX_P12 PEX_RX11_N GPIO23
4 PEG_HTX_C_GRX_N[0..15] AP29 PEX_RX12 GPIO24 M7
PEG_HTX_C_GRX_N12 AN29
PEG_HTX_C_GRX_P[0..15] PEG_HTX_C_GRX_P13 PEX_RX12_N
4 PEG_HTX_C_GRX_P[0..15] AN31 PEX_RX13 MIOA_D0_NC N1
PEG_HTX_C_GRX_N13 AP31 P4
PEG_HTX_C_GRX_P14 PEX_RX13_N MIOA_D1_NC +3VSDGPU
AR31 PEX_RX14 MIOA_D2_NC P1
PEG_HTX_C_GRX_N14 AR32 P2
PEG_HTX_C_GRX_P15 PEX_RX14_N MIOA_D3_NC
AR34 PEX_RX15 MIOA_D4_NC P3
PEG_HTX_C_GRX_N15 AP34 T3 VGA_EDID_CLK 1 OPT@ 2
PEX_RX15_N MIOA_D5_NC R1405 2.2K_0402_5%
MIOA_D6_NC T2 GPIO I/O FUNCTION VGA_EDID_DATA
MIOA_D7_NC T1 1 OPT@ 2
PEG_HRX_GTX_P0 C1405 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P0 AL17 U4 R1406 2.2K_0402_5%
PEX_TX0 MIOA_D8_NC

PCI EXPRESS
PEG_HRX_GTX_N0 C1406 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_N0 AM17 U1 GPIO1 IN HPD_C SMB_CLK_GPU 1 OPT@ 2
PEG_HRX_GTX_P1 C1407 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_P1 PEX_TX0_N MIOA_D9_NC R1407 2.2K_0402_5%
2 AM18 PEX_TX1 MIOA_D10_NC U2
PEG_HRX_GTX_N1 C1408 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_N1 AM19 U3 SMB_DATA_GPU 1 OPT@ 2
PEG_HRX_GTX_P2 C1409 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_P2 PEX_TX1_N MIOA_D11_NC R1408 2.2K_0402_5%
PEG_HRX_GTX_N2 C1410 OPT@ 1
2
.1U_0402_16V7K PEG_HRX_C_GTX_N2
AL19 PEX_TX2 MIOA_D12_NC R6 GPIO5 OUT GPU_VID0
2 AK19 T6

DVO
PEG_HRX_GTX_P3 C1411 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_P3 PEX_TX2_N MIOA_D13_NC
2 AL20 PEX_TX3 MIOA_D14_NC N6
PEG_HRX_GTX_N3 C1412 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_N3 AM20 GPIO6 OUT GPU_VID1 THERM#_VGA 1 OPT@ 2
PEG_HRX_GTX_P4 C1413 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_P4 PEX_TX3_N R1410 100K_0402_5%
2 AM21 PEX_TX4 MIOB_D0_NC Y1
PEG_HRX_GTX_N4 C1414 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_N4 AM22 Y2 OVERT#_VGA 1 OPT@ 2
PEG_HRX_GTX_P5 C1415 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_P5 PEX_TX4_N MIOB_D1_NC R1411 10K_0402_5%
PEG_HRX_GTX_N5
2
PEG_HRX_C_GTX_N5
AL22 PEX_TX5 MIOB_D2_NC Y3 GPIO7 OUT GPU_VID2 HDCP_SCL
C1416 OPT@ 1 2 .1U_0402_16V7K AK22 AB3 1 OPT@ 2
PEG_HRX_GTX_P6 C1417 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_P6 PEX_TX5_N MIOB_D3_NC R1412 2.2K_0402_5%
2 AL23 PEX_TX6 MIOB_D4_NC AB2
C PEG_HRX_GTX_N6 C1418 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N6 HDCP_SDA C
2 AM23 PEX_TX6_N MIOB_D5_NC AB1 GPIO8 IN OVERT 1 OPT@ 2
PEG_HRX_GTX_P7 C1419 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P7 AM24 AC4 R1413 2.2K_0402_5%
PEG_HRX_GTX_N7 C1420 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N7 PEX_TX7 MIOB_D6_NC VGA_CRT_DATA
2 AM25 PEX_TX7_N MIOB_D7_NC AC1 1 OPT@ 2
PEG_HRX_GTX_P8 C1421 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P8 AL25 AC2 GPIO9 IN ALERT R1414 2.2K_0402_5%
PEG_HRX_GTX_N8 C1422 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N8 PEX_TX8 MIOB_D8_NC VGA_CRT_CLK
2 AK25 PEX_TX8_N MIOB_D9_NC AC3 1 OPT@ 2
PEG_HRX_GTX_P9 C1423 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P9 AL26 AE3 R1415 2.2K_0402_5%
PEG_HRX_GTX_N9 C1424 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N9 PEX_TX9 MIOBD_10_NC I2CB_SCL
2 AM26 PEX_TX9_N MIOB_D11_NC AE2 GPIO12 IN AC/DC detection 1 OPT@ 2
PEG_HRX_GTX_P10 C1425 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P10 AM27 U6 R1416 2.2K_0402_5%
PEG_HRX_GTX_N10 C1426 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N10 PEX_TX10 MIOB_D12_NC I2CB_SDA
2 AM28 PEX_TX10_N MIOB_D13_NC W6 1 OPT@ 2
PEG_HRX_GTX_P11 C1427 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P11 AL28 Y6 GPIO18 IN Reserve for VPS R1417 2.2K_0402_5%
PEG_HRX_GTX_N11 C1428 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N11 PEX_TX11 MIOB_D14_NC
2 AK28 PEX_TX11_N
PEG_HRX_GTX_P12 C1429 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P12 AK29 N3
PEG_HRX_GTX_N12 C1430 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N12 PEX_TX12 MIOA_HSYNC_NC
2 AL29 PEX_TX12_N MIOA_VSYNC_NC L3
PEG_HRX_GTX_P13 C1431 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P13 AM29
PEG_HRX_GTX_N13 C1432 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N13 PEX_TX13
2 AM30 PEX_TX13_N MIOB_HSYNC_NC W1
PEG_HRX_GTX_P14 C1433 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P14 AM31 W2
PEG_HRX_GTX_N14 C1434 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N14 PEX_TX14 MIOB_VSYNC_NC
2 AM32 PEX_TX14_N
PEG_HRX_GTX_P15 C1435 OPT@ 1 2 .1U_0402_16V7K PEG_HRX_C_GTX_P15 AN32 N2
PEG_HRX_GTX_N15 C1436 OPT@ 1 .1U_0402_16V7K PEG_HRX_C_GTX_N15 PEX_TX15 MIOA_DE_NC
2 AP32 PEX_TX15_N MIOA_CTL3_NC P5
MIOA_VREF_NC N5

MIOB_DE_NC Y5
@R1419
@ R1419 @C1437
@ C1437 14 CLK_PEG_VGA CLK_PEG_VGA AR16 W3
22_0402_5% 10P_0402_50V8J CLK_PEG_VGA# PEX_REFCLK MIOB_CTL3_NC
14 CLK_PEG_VGA# AR17 PEX_REFCLK_N MIOB_VREF_NC AF1
XTALIN 2 1 1 2 PEG_CLKREQ# AR13 PEX_CLKREQ_N
MIOA_CLKIN_NC N4 1 OPT@ 2
1 @ 2 PEX_TSTCLK_OUT AJ17 R4 R1420 10K_0402_5%
Layout note: Reserve for EMI please close to UV1 Layout note: Differential signalR1421 200_0402_1%
PEX_TSTCLK_OUT# PEX_TSTCLK_OUT MIOA_CLKOUT_NC
AJ18 PEX_TSTCLK_OUT_N
MIOB_CLKIN_NC AE1 1 OPT@ 2
V4 R1422 10K_0402_5%
PLTRST_VGA# MIOB_CLKOUT_NC
17 PLTRST_VGA# AM16 PEX_RST_N
1 @ 2 AG21 T4
R1424 10M_0402_5% PEX_TERMP MIOA_CLKOUT_NC_N +3VSDGPU
1 OPT@ 2 MIOB_CLKOUT_NC_N W4 9/20
B R1400 2.49K_0402_1% Diode at PCH B

MIOACAL_PD_VDDQ_NC U5

1
Y1400 OPT@ +PLLVDD 60mA AE9 T5
XTALIN PLLVDD MIOACAL_PU_GND_NC
1 2 XTAL_OUT OPT@
45mA AF9 AA7 R1428
27MHZ_16PF_X5H027000FG1H SP_PLLVDD MIOBCAL_PD_VDDQ_NC 10K_0402_5%
MIOBCAL_PU_GND_NC AA6
1 1 45mA AD9

2
C1438 C1439 VID_PLLVDD
CLK

18P_0402_50V8J OPT@ 2 @ 1 XTALIN B1 PEG_CLKREQ#

14 CLK_27M_TCLK XTAL_IN 14 PEG_CLKREQ#
OPT@ 18P_0402_50V8J R1425 22_0402_5% XTAL_OUT B2 AM15
2 2 XTAL_OUT DACA_RED
DACA_GREEN AM14
2 OPT@ 1 XTALOUT D1 AL14
R1426 2 OPT@ XTALSSIN XTAL_OUTBUFF DACA_BLUE
1 10K_0402_5% D2 XTAL_SSIN
R1427 10K_0402_5% AM13
DACA_HSYNC
DACA_VSYNC AL13

SMB_CLK_GPU E2 AJ12
+3VSDGPU Note: Internal Thermal Sensor SMB_DATA_GPU E1 I2CS_SCL DACA_VDD
I2CS_SDA DACA_VREF AK12 T1405
DACA_RSET AK13 T1406

2
Q1401A VGA_EDID_CLK E3
I2CC_SCL
DACs

2N7002KDWH_SOT363-6 VGA_EDID_DATA E4 AK4 R1516

I2CC_SDA DACB_RED
2

OPT@ AL4 10K_0402_5%

I2CB_SCL DACB_GREEN
G3 I2CB_SCL DACB_BLUE AJ4 OPT@
SMB_CLK_GPU I2CB_SDA
I2C

1 6 EC_SMB_CK2 14,41 G2

1
I2CB_SDA
DACB_HSYNC AM1
VGA_CRT_CLK G1 AM2
VGA_CRT_DATA G4 I2CA_SCL DACB_VSYNC
I2CA_SDA
DACB_VDD AG7
1 R1494 2 check leakage HDCP_SCL F6 AK6
I2CH_SCL DACB_VREF T1408
@ 0_0402_5% HDCP_SDA G6 AH7
I2CH_SDA DACB_RSET T1409

2
R1517
N12P-GS1-A1_BGA_973P GS@ 10K_0402_5%
A 1 OPT@ A

Q1401B
5

2N7002KDWH_SOT363-6
OPT@
SMB_DATA_GPU 4 3 10/11 NV: DACx-VDD 10K to GND, others NC
EC_SMB_DA2 14,41

Security Classification Compal Secret Data Compal Electronics, Inc.

1 R1495 2 Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title
@ 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 22 of 57
5 4 3 2 1
 5 4 3 2 1

U1400D +3VSDGPU

Part 4 of 7

2
AM11 IFPA_TXC NC_0 A2
AM12 A7 R1507
IFPA_TXC_N NC_1
AM8 IFPA_TXD0 NC_2 B7 10K_0402_5%
AL8 IFPA_TXD0_N NC_3 C5 @
AM10 C7 STRAP4

1
IFPA_TXD1 NC_4 STRAP4
AM9 IFPA_TXD1_N NC_5 D5
AK10 IFPA_TXD2 NC_6 D6

2
AL10 D7 STRAP3 No6 No6
IFPA_TXD2_N NC_7 R1508
AK11 IFPA_TXD3 NC_8 E5
AL11 E7 PGOOD 2 R1511 1 10K_0402_5%
D IFPA_TXD3_N NC_9 GV@ D
NC_10 F4 GV@
G5 10K_0402_5%

1
NC_11
AP13 IFPB_TXC NC_12 H32
AN13 IFPB_TXC_N NC_13 J25
AN8 IFPB_TXD4 NC_14 J26
AP8 P6 STRAP_REF2 2 R1512 1
IFPB_TXD4_N NC_15 GV@
AP10 IFPB_TXD5 NC_16 U7
AN10 V6 40.2K_0402_1% +3VSDGPU
IFPB_TXD5_N NC_17
AR11 IFPB_TXD6 NC_18 Y4
AR10 IFPB_TXD6_N NC_19 AA4

2
AN11 IFPB_TXD7 NC_20 AB4
AP11 AB7 R1509
IFPB_TXD7_N NC_21
NC_22 AC5 10K_0402_5%

NC
NC_23 AD6 @
AM7 AF6

1
IFPC_L0 NC_24 STRAP3
AM6 IFPC_L0_N NC_25 AG6
AL5 IFPC_L1 NC_26 AG20

2
AM5 IFPC_L1_N NC_27 AJ5 No6
AM3 AK15 R1510
IFPC_L2 NC_28
AM4 IFPC_L2_N NC_29 AL7 4.99K_0402_1%
AP1 GV@
IFPC_L3
AR2

1
IFPC_L3_N

AR8 IFPD_L0
AR7 IFPD_L0_N
AP7 IFPD_L1
AN7 IFPD_L1_N
AN5 IFPD_L2
AP5

LVDS/TMDS
C C
IFPD_L2_N
AR5 IFPD_L3
AR4 IFPD_L3_N

AH6 IFPE_L0
AH5 IFPE_L0_N
AH4 IFPE_L1
AG4 IFPE_L1_N
AF4 IFPE_L2
AF5 IFPE_L2_N
AE6 IFPE_L3
AE5 IFPE_L3_N

VDD_SENSE_0 D35 VGAVCC_SENSE 55

AL2 IFPF_L0 VDD_SENSE_1 P7
AL3 IFPF_L0_N VDD_SENSE_2 AD20
AJ3 IFPF_L1
AJ2 IFPF_L1_N
AJ1 IFPF_L2
AH1 IFPF_L2_N GND_SENSE_0 AD19
AH2 IFPF_L3 GND_SENSE_1 E35
AH3 IFPF_L3_N GND_SENSE_2 R7
NV suggests directly connect to GND

all NC, can't support 3D and high resolution HDMI AP2 IFPC_AUX_I2CW_SCL
AN3 IFPC_AUX_I2CW_SDA_N TEST
B B
AP4 AP35 TESTMODE R1429 1 OPT@ 2 10K_0402_5%
IFPD_AUX_I2CX_SCL TESTMODE R1409 1 @
AN4 IFPD_AUX_I2CX_SDA_N JTAG_TCK AP14 2 10K_0402_5%
JTAG_TDI AN14 T1402
JTAG_TDO AN16 T1403
AE4 IFPE_AUX_I2CY_SCL JTAG_TMS AR14 T1404
AD4 IFPE_AUX_I2CY_SDA_N JTAG_TRST_N AP16 1 OPT@ 2
R1430 10K_0402_5%

AF3 IFPF_AUX_I2CZ_SCL +3VSDGPU

AF2 IFPF_AUX_I2CZ_SDA_N SERIAL
C3 ROM_CS# 2 1
ROM_CS_N ROM_SI R1431 10K_0402_5%
ROM_SI D3 ROM_SI 33
C4 ROM_SO ROM_SO 33
ROM_SO ROM_SCLK
ROM_SCLK D4 ROM_SCLK 33

GENERAL JM50
A5 R1498 2 OPT@ 1 36K_0402_1% if unuse this pin , pull down 36k
NC/SPDIF_NC
A4 BUFRST_N
MULTI_STRAP_REF0_GND N9 1 OPT@ 2
+3VSDGPU 1 OPT@ 2 AB5 CEC
R1432 40.2K_0402_1%
R1433 10K_0402_5% M9 1 OPT@ 2
STRAP0 MULTI_STRAP_REF1_GND R1434 40.2K_0402_1%
33 STRAP0 W5 STRAP0
33 STRAP1 STRAP1 W7 B5
STRAP2 STRAP1 THERMDP
33 STRAP2 V7 STRAP2 THERMDN B4

A N12P-GS1-A1_BGA_973P GS@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 23 of 57
5 4 3 2 1
 5 4 3 2 1

For PHQAA EVT Phase only N12M-GE Performance Mode N12P-GS Performance Mode N12P-GE Performance Mode
Mode VID1 VID0 +VGA_CORE Mode NVCLK (MHz) MCLK (MHz) +VGA_CORE Mode NVCLK (MHz) MCLK (MHz) +VGA_CORE Mode NVCLK (MHz) MCLK (MHz) +VGA_CORE

P0(Cold) 1 1 0.95 V P0 606 790 1.00 V P0 TBD TBD TBD P0 TBD TBD TBD

P0 0 1 0.950V P8 TBD TBD TBD P8 TBD TBD TBD P8 TBD TBD TBD
D D
P8/P12 0 0 0.825 V P12 TBD TBD TBD P12 TBD TBD TBD P12 TBD TBD TBD

+VGA_CORE +VGA_CORE
U1400G Layout note: Near GPU
AB11 VDD_0 VDD_56 P21
AB13 Part 7 of 7 P23 +VGA_CORE
VDD_1 VDD_57
AB15 VDD_2 VDD_58 P25
AB17 R11 +VGA_CORE
VDD_3 VDD_59
AB19 VDD_4 VDD_60 R12 reserve for power team

10U_0603_6.3V6M

10U_0603_6.3V6M

4.7U_0603_6.3V6K

22U_0805_6.3V6M

47U_0805_4V6
AB21 VDD_5 VDD_61 R13

OPT@ C1446

OPT@ C1447

OPT@ C1448

OPT@ C1449

OPT@ C1450
AB23 VDD_6 VDD_62 R14 2 2 1 1 1

330U_D2_2V_Y
OPT@ C1441

330U_D2_2V_Y
OPT@ C1597
AB25 VDD_7 VDD_63 R15 1 1
C AC11 VDD_8 VDD_64 R16 C
AC12 R17 + +
VDD_9 VDD_65 1 1 2 2 2
AC13 VDD_10 VDD_66 R18
AC14 VDD_11 VDD_67 R19
2 2
AC15 VDD_12 VDD_68 R20
AC16 VDD_13 VDD_69 R21
AC17 VDD_14 VDD_70 R22
AC18 VDD_15 VDD_71 R23
AC19 VDD_16 VDD_72 R24
AC20 VDD_17 VDD_73 R25
AC21 VDD_18 VDD_74 T12
AC22 VDD_19 VDD_75 T14
AC23 VDD_20 VDD_76 T16
POWER

AC24 VDD_21 VDD_77 T18

AC25 VDD_22 VDD_78 T20
AD12 VDD_23 VDD_79 T22
AD14 VDD_24 VDD_80 T24
AD16 VDD_25 VDD_81 V11
AD18 VDD_26 VDD_82 V13 Layout note: Under GPU
AD22 VDD_27 VDD_83 V15
AD24 V17 +VGA_CORE
VDD_28 VDD_84
L11 VDD_29 VDD_85 V19
L12 VDD_30 VDD_86 V21
0.047U_0402_25V7K

0.047U_0402_25V7K

0.047U_0402_25V7K

0.022U_0402_25V7K

0.022U_0402_25V7K

0.022U_0402_25V7K
L13 VDD_31 VDD_87 V23
OPT@ C1451

OPT@ C1452

OPT@ C1453

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K
L14 VDD_32 VDD_88 V25 OPT@ C1454

OPT@ C1455

OPT@ C1456

OPT@ C1457

OPT@ C1458

OPT@ C1459
L15 VDD_33 VDD_89 W11 1 1 1 1 1 1
1

L16 VDD_34 VDD_90 W12

B L17 VDD_35 VDD_91 W13 B
L18 W14
2

VDD_36 VDD_92 2 2 2 2 2 2
L19 VDD_37 VDD_93 W15
L20 VDD_38 VDD_94 W16
L21 VDD_39 VDD_95 W17
L22 VDD_40 VDD_96 W18
L23 VDD_41 VDD_97 W19
L24 VDD_42 VDD_98 W20
L25 VDD_43 VDD_99 W21
M12 VDD_44 VDD_100 W22
M14 W23 +VGA_CORE
VDD_45 VDD_101
M16 VDD_46 VDD_102 W24
M18 VDD_47 VDD_103 W25
0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K
M20 VDD_48 VDD_104 Y12
M22 VDD_49 VDD_105 Y14
OPT@ C1460

OPT@ C1461

OPT@ C1462

OPT@ C1463

OPT@ C1464

OPT@ C1465

OPT@ C1466

OPT@ C1467

OPT@ C1468

OPT@ C1469

OPT@ C1470
M24 VDD_50 VDD_106 Y16 1 1 1 1 1 1 1 1 1

1
P11 VDD_51 VDD_107 Y18
P13 VDD_52 VDD_108 Y20
P15 Y22
2

2
VDD_53 VDD_109 2 2 2 2 2 2 2 2
P17 VDD_54 VDD_110 Y24
P19 VDD_55

N12P-GS1-A1_BGA_973P GS@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 24 of 57
5 4 3 2 1
 5 4 3 2 1

U1400E
Layout note: Under GPU
3.5A Part 5 of 7 2200mA
+VRAM_1.5VS J23
1600mA AG11 +1.05VS_DGPU
FBVDDQ_0 PEX_IOVDDQ_0

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

22U_0805_6.3V6M
J24 FBVDDQ_1 PEX_IOVDDQ_1 AG12

OPT@ C1471

OPT@ C1472

OPT@ C1473

OPT@ C1474

OPT@ C1475

OPT@ C1476

OPT@ C1477

OPT@ C1478

OPT@ C1479

OPT@ C1480

OPT@ C1481
1 1 1 1 J29 FBVDDQ_2 PEX_IOVDDQ_2 AG13 1 1 1 1 1 1 1
AA27 FBVDDQ_3 PEX_IOVDDQ_3 AG15
AA29 FBVDDQ_4 PEX_IOVDDQ_4 AG16
AA31 FBVDDQ_5 PEX_IOVDDQ_5 AG17
2 2 2 2 2 2 2 2 2 2 2
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22
AC27 FBVDDQ_8 PEX_IOVDDQ_8 AG23
AD27 FBVDDQ_9 PEX_IOVDDQ_9 AG24
D AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25 D
Layout note: Under GPU AJ28 AG26 +1.05VS_DGPU
FBVDDQ_11 PEX_IOVDDQ_11

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

22U_0805_6.3V6M
B18 FBVDDQ_12 PEX_IOVDDQ_12 AJ14

OPT@ C1482

OPT@ C1483

OPT@ C1484

OPT@ C1485

OPT@ C1486

OPT@ C1487

OPT@ C1488
+VRAM_1.5VS E21 FBVDDQ_13 PEX_IOVDDQ_13 AJ15 1 1 1 1 1 1 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
G17 FBVDDQ_14 PEX_IOVDDQ_14 AJ19

OPT@ C1490

OPT@ C1491

OPT@ C1492

OPT@ C1493

OPT@ C1494

OPT@ C1495

OPT@ C1496

OPT@ C1489
1 G18 FBVDDQ_15 PEX_IOVDDQ_15 AJ21
1 1 1 1 1 1 1 G22 FBVDDQ_16 PEX_IOVDDQ_16 AJ22
2 2 2 2 2 2 2
G8 FBVDDQ_17 PEX_IOVDDQ_17 AJ24
G9 FBVDDQ_18 PEX_IOVDDQ_18 AJ25
2
H29 FBVDDQ_19 PEX_IOVDDQ_19 AJ27

POWER
2 2 2 2 2 2 2
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
J15 FBVDDQ_21 PEX_IOVDDQ_21 AK20
J16 FBVDDQ_22 PEX_IOVDDQ_22 AK23
J17 FBVDDQ_23 PEX_IOVDDQ_23 AK26
J20 AL16 L1401 OPT@
FBVDDQ_24 PEX_IOVDDQ_24 BLM18PG121SN1D_0603
J21 FBVDDQ_25
J22 FBVDDQ_26 2 1 +1.05VS_DGPU

0.1U_0402_16V4Z

1U_0402_6.3V6K

4.7U_0603_6.3V6K
N27 FBVDDQ_27 600mA

OPT@ C1497

OPT@ C1498

OPT@ C1499
P27 FBVDDQ_28 PEX_IOVDD_0 AK16 1 1 1
R27 FBVDDQ_29 PEX_IOVDD_1 AK17
T27 FBVDDQ_30 PEX_IOVDD_2 AK21
U27 FBVDDQ_31 PEX_IOVDD_3 AK24
2 2 2
U29 FBVDDQ_32 PEX_IOVDD_4 AK27
V27 FBVDDQ_33
V29 FBVDDQ_34 120mA
V34
W27
FBVDDQ_35 120mA AG14 +PEX_PLLVDD
FBVDDQ_36 PEX_PLLVDD
Y27 FBVDDQ_37 +3VSDGPU
120mA under GPU near GPU 0_0603_5%
1 OPT@ 2 +IFPAB_PLLVDD AK9 AG19 R1505 2 OPT@ 1
IFPAB_PLLVDD PEX_SVDD_3V3

1U_0402_6.3V6K
C1603

0.1U_0402_16V4Z
C1501

4.7U_0603_6.3V6K
C1502
C R1435 1 @ 2 10K_0402_5% AJ11 F7 C
R1436 1K_0402_1% IFPAB_RSET PEX_SVDD_3V3_NC +1.05VS_DGPU
1 1 1

1 OPT@ 2 +IFPAB_IOVDD AG9 2 @ 1

IFPA_IOVDD

OPT@

OPT@

OPT@
R1437 10K_0402_5% AG10 J10 R1515
IFPB_IOVDD VDD33_0 2 2 2 0_0603_5%
VDD33_1 J11
VDD33_2 J12 NVIDIA suggest reserve it
1 OPT@ 2 +IFPD_PLLVDD AJ9 J13 120mA
R1438 1 @ IFPC_PLLVDD VDD33_3
2 10K_0402_5% AK7 IFPC_RSET VDD33_4 J9
R1439 1K_0402_1% under GPU near GPU 0_0603_5%
1 OPT@ 2 +IFPD_IOVDD AJ8 R1506 2 OPT@ 1 +3VSDGPU
IFPC_IOVDD

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V6K

4.7U_0603_6.3V6K
R1440 10K_0402_5%

OPT@ C1503

OPT@ C1504

OPT@ C1505

OPT@ C1506

OPT@ C1507
MIOA_VDDQ_NC_0 P9 1 1 1 1 1
+IFPD_PLLVDD AC6 R9
@ IFPD_PLLVDD MIOA_VDDQ_NC_1
1 2 AB6 IFPD_RSET MIOA_VDDQ_NC_2 T9
R1441 1K_0402_1% U9
MIOA_VDDQ_NC_3

1
+IFPD_IOVDD OPT@ 2 2 2 2 2
AK8 IFPD_IOVDD R1513
1 OPT@ 2 +IFPEF_PLLVDD AA9 10K_0402_5%
R1442 10K_0402_5% MIOB_VDDQ_NC_0
AJ6 IFPEF_PLLVDD MIOB_VDDQ_NC_1 AB9
1 @ 2 AL1 W9

2
R1443 1K_0402_1% IFPEF_RSET MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3 Y9
1 OPT@ 2 +IFPE_IOVDD AE7 IFPE_IOVDD

1
R1444 10K_0402_5% AD7 OPT@
IFPF_IOVDD R1514
10K_0402_5%

N12P-GS1-A1_BGA_973P GS@

2
check: power connection?
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 25 of 57
5 4 3 2 1
 5 4 3 2 1

U1400F

B3 Part 6 of 7
GND_0
B6 GND_1 GND_97 V18
B9 GND_2 GND_98 V20
B12 GND_3 GND_99 V22
B15 GND_4 GND_100 V24
B21 GND_5 GND_101 V31
B24 GND_6 GND_102 Y11
B27 GND_7 GND_103 Y13
B30 GND_8 GND_104 Y15
B33 GND_9 GND_105 Y17
D
C2 GND_10 GND_106 Y19 D
C34 GND_11 GND_107 Y21
E6 GND_12 GND_108 Y23
E9 GND_13 GND_109 Y25
E12 GND_14 GND_110 AA2
E15 GND_15 GND_111 AA5
E18 GND_16 GND_112 AA11
E24 GND_17 GND_113 AA12
E27 GND_18 GND_114 AA13
E30 GND_19 GND_115 AA14
F2 GND_20 GND_116 AA15
F31 GND_21 GND_117 AA16
F34 GND_22 GND_118 AA17
F5 GND_23 GND_119 AA18
J2 GND_24 GND_120 AA19
J5 GND_25 GND_121 AA20
J31 GND_26 GND_122 AA21
J34 GND_27 GND_123 AA22
K9 GND_28 GND_124 AA23
L9 GND_29 GND_125 AA24
M2 GND_30 GND_126 AA25
M5 GND_31 GND_127 AA34
M11 GND_32 GND_128 AB12
M13 GND_33 GND_129 AB14
M15 GND_34 GND_130 AB16
M17 GND_35 GND_131 AB18
M19 GND_36 GND_132 AB20
M21 GND_37 GND_133 AB22
M23 GND_38 GND_134 AB24
M25 GND_39 GND_135 AC9
C M31 GND_40 GND_136 AD2 C
M34 GND_41 GND_137 AD5

GND
N11 GND_42 GND_138 AD11
N12 GND_43 GND_139 AD13
N13 GND_44 GND_140 AD15
N14 GND_45 GND_141 AD17
N15 GND_46 GND_142 AD21
N16 GND_47 GND_143 AD23
N17 GND_48 GND_144 AD25
N18 GND_49 GND_145 AD31
N19 GND_50 GND_146 AD34
N20 GND_51 GND_147 AE11
N21 GND_52 GND_148 AE12
N22 GND_53 GND_149 AE13
N23 GND_54 GND_150 AE14
N24 GND_55 GND_151 AE15
N25 GND_56 GND_152 AE16
P12 GND_57 GND_153 AE17
P14 GND_58 GND_154 AE18
P16 GND_59 GND_155 AE19
P18 GND_60 GND_156 AE20
P20 GND_61 GND_157 AE21
P22 GND_62 GND_158 AE22
P24 GND_63 GND_159 AE23
R2 GND_64 GND_160 AE24
R5 GND_65 GND_161 AE25
R31 GND_66 GND_162 AG2
R34 GND_67 GND_163 AG5
T11 GND_68 GND_164 AG31
B
T13 GND_69 GND_165 AG34 B
T15 GND_70 GND_166 AK2
T17 GND_71 GND_167 AK5
T19 GND_72 GND_168 AK14
T21 GND_73 GND_169 AK31
T23 GND_74 GND_170 AK34
T25 GND_75 GND_171 AL6
U11 GND_76 GND_172 AL9
U12 GND_77 GND_173 AL12
U13 GND_78 GND_174 AL15
U14 GND_79 GND_175 AL18
U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
U17 GND_82 GND_178 AL27
U18 GND_83 GND_179 AL30
U19 GND_84 GND_180 AN2
U20 GND_85 GND_181 AN34
U21 GND_86 GND_182 AP3
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
U24 GND_89 GND_185 AP12
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
V5 GND_92 GND_188 AP21
V9 GND_93 GND_189 AP24
V12 GND_94 GND_190 AP27
V14 GND_95 GND_191 AP30
V16 GND_96 GND_192 AP33

A A
N12P-GS1-A1_BGA_973P GS@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 26 of 57
5 4 3 2 1
 5 4 3 2 1

U1400B

Part 2 of 7 CMDA0
MDA[0..63] MDA0 L32
FBA_CMD0 U30
V30
CMDA0 29 GB2-128
D 29,30 MDA[0..63] FBA_D0 FBA_CMD1 D
MDA1 CMDA2
MDA2
N33
L33
FBA_D1 FBA_CMD2 U31
V32 CMDA3
CMDA2 29 Mode E - Mirror Mode Mapping
FBA_D2 FBA_CMD3 CMDA3 29
MDA3 N34 T35 CMDA4
FBA_D3 FBA_CMD4 CMDA4 29,30
MDA4 N35 U33 CMDA5 DATA Bus
FBA_D4 FBA_CMD5 CMDA5 29,30
MDA5 P35 W32 CMDA6
FBA_D5 FBA_CMD6 CMDA6 29,30
MDA6 P33 W33 CMDA7 Address 0..31 32..63
FBA_D6 FBA_CMD7 CMDA7 29,30
MDA7 P34 W31 CMDA8
FBA_D7 FBA_CMD8 CMDA8 29,30
MDA8 K35 W34 CMDA9 CMD3 CKE_L
FBA_D8 FBA_CMD9 CMDA9 29,30
MDA9 K33 U34 CMDA10
FBA_D9 FBA_CMD10 CMDA10 29,30
MDA10 K34 U35 CMDA11 CMD8 A8 A8
FBA_D10 FBA_CMD11 CMDA11 29,30
MDA11 H33 U32 CMDA12
FBA_D11 FBA_CMD12 CMDA12 29,30
MDA12 G34 T34 CMDA13 CMD2 CS0#_L
FBA_D12 FBA_CMD13 CMDA13 29,30
MDA13 G33 T33 CMDA14
FBA_D13 FBA_CMD14 CMDA14 29,30
MDA14 E34 W30 CMDA15 CMD21 A7 A6
FBA_D14 FBA_CMD15 CMDA15 29,30
MDA15 E33 AB30 CMDA16
FBA_D15 FBA_CMD16 CMDA16 30
MDA16 G31 AA30 CMD24 A2 A1
MDA17 FBA_D16 FBA_CMD17 CMDA18
F30 FBA_D17 FBA_CMD18 AB31 CMDA18 30
MDA18 G30 AA32 CMDA19 CMD23 A11 A9
FBA_D18 FBA_CMD19 CMDA19 30
MDA19 G32 AB33 CMDA20
FBA_D19 FBA_CMD20 CMDA20 29,30
MDA20 K30 Y32 CMDA21 CMD26 A5 A4
FBA_D20 FBA_CMD21 CMDA21 29,30
MDA21 K32 Y33 CMDA22
FBA_D21 FBA_CMD22 CMDA22 29,30
MDA22 H30 AB34 CMDA23 CMD7 A0 A12
FBA_D22 FBA_CMD23 CMDA23 29,30
MDA23 K31 AB35 CMDA24
FBA_D23 FBA_CMD24 CMDA24 29,30
MDA24 L31 Y35 CMDA25 CMD15 CAS# CAS#
FBA_D24 FBA_CMD25 CMDA25 29,30
MDA25 L30 W35 CMDA26
CMDA26 29,30

MEMORY INTERFACE
MDA26 FBA_D25 FBA_CMD26 CMDA27
M32 FBA_D26 FBA_CMD27 Y34 CMDA27 29,30 CMD13 BA1 A3
MDA27 N30 Y31 CMDA28
FBA_D27 FBA_CMD28 CMDA28 29,30
MDA28 M30 Y30 CMDA29 CMD4 A9 A11
FBA_D28 FBA_CMD29 CMDA29 29,30
MDA29 P31 W29 CMDA30
FBA_D29 FBA_CMD30 CMDA30 29,30
C MDA30 R32 Y29 CMD18 CS0#_H C
MDA31 FBA_D30 FBA_CMD31
R30 FBA_D31 DQMA[7..0] 29,30
MDA32 AG30 P32 DQMA0 CMD29 BA0 BA0
+1.05VS_DGPU FBA_D32 FBA_DQM0 DQSA#[7..0] 29,30
MDA33 AG32 H34 DQMA1
FBA_D33 FBA_DQM1 DQSA[7..0] 29,30
MDA34 AH31 J30 DQMA2 CMD27 BA2 A15
L1402 OPT@ 100mA MDA35 FBA_D34 FBA_DQM2 DQMA3
AF31 FBA_D35 FBA_DQM3 P30
1 2 +FB_AVDD0 MDA36 AF30 AF32 DQMA4 CMD6 A3 BA1
FBA_D36 FBA_DQM4
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

BLM18PG330SN1D_2P MDA37 AE30 AL32 DQMA5

FBA_D37 FBA_DQM5
OPT@ C1509

OPT@ C1510

OPT@ C1511

OPT@ C1512

OPT@ C1599

2 1 1 1 1 MDA38 AC32 AL34 DQMA6 CMD17 CS1#_H

MDA39 FBA_D38 FBA_DQM6 DQMA7
AD30 FBA_D39 FBA_DQM7 AF35
MDA40 AN33 CMD19 ODT_H
MDA41 FBA_D40 DQSA#0
AL31 FBA_D41 FBA_DQS_RN0 L35
1 2 2 2 2

A
MDA42 AM33 G35 DQSA#1 CMD22 A4 A5
MDA43 FBA_D42 FBA_DQS_RN1 DQSA#2
AL33 FBA_D43 FBA_DQS_RN2 H31
MDA44 AK30 N32 DQSA#3 CMD12 A13 A14
MDA45 FBA_D44 FBA_DQS_RN3 DQSA#4
AK32 FBA_D45 FBA_DQS_RN4 AD32
MDA46 AJ30 AJ31 DQSA#5 CMD28 WE# A10
MDA47 FBA_D46 FBA_DQS_RN5 DQSA#6
AH30 FBA_D47 FBA_DQS_RN6 AJ35
MDA48 AH33 AC34 DQSA#7 CMD10 A1 A2
+1.05VS_DGPU MDA49 FBA_D48 FBA_DQS_RN7
AH35 FBA_D49
MDA50 AH34 L34 DQSA0 CMD25 A10 WE#
L1403 OPT@ 100mA MDA51 FBA_D50 FBA_DQS_WP0 DQSA1
AH32 FBA_D51 FBA_DQS_WP1 H35
1 2 +FB_AVDD1 MDA52 AJ33 J32 DQSA2 CMD9 A12 A0
FBA_D52 FBA_DQS_WP2
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

BLM18PG330SN1D_2P MDA53 AL35 N31 DQSA3

FBA_D53 FBA_DQS_WP3
OPT@ C1514

OPT@ C1515

OPT@ C1516

OPT@ C1517

OPT@ C1600

2 1 1 1 1 MDA54 AM34 AE31 DQSA4 CMD1 CS1#_L

MDA55 FBA_D54 FBA_DQS_WP4 DQSA5
AM35 FBA_D55 FBA_DQS_WP5 AJ32
MDA56 AF33 AJ34 DQSA6 CMD11 RAS# RAS#
MDA57 FBA_D56 FBA_DQS_WP6 DQSA7
AE32 FBA_D57 FBA_DQS_WP7 AC33
1 2 2 2 2 MDA58 AF34 FBA_D58 CMD0 ODT_L
MDA59 AE35 P29
B
MDA60 FBA_D59 FBA_WCK0 B
AE34 FBA_D60 FBA_WCK0_N R29 CMD5 A6 A7
MDA61 AE33 L29
MDA62 FBA_D61 FBA_WCK1
AB32 FBA_D62 FBA_WCK1_N M29 CMD16 CKE_H
MDA63 AC35 AG29
FBA_D63 FBA_WCK2
FBA_WCK2_N AH29 CMD20 RST RST
+FB_AVDD0 AG27 AD29
FB_DLLAVDD_0 FBA_WCK3
AF27 FB_PLLAVDD_0 FBA_WCK3_N AE29 CMD14 A14 A13
+FB_AVDD1 J19 CMD30 A15 BA2
FB_DLLAVDD_1 CLKA0
J18 FB_PLLAVDD_1 FBA_CLK0 T32 CLKA0 29
T31 CLKA0#
FBA_CLK0_N CLKA0# 29
J27 FB_VREF_NC
+VRAM_1.5VS 2 OPT@ 1 T30 AC31 CLKA1
FBA_DEBUG0 FBA_CLK1 CLKA1 30
R1445 2 OPT@ 1 60.4_0402_1% T29 AC30 CLKA1#
FBA_DEBUG1 FBA_CLK1_N CLKA1# 30
R1446 10K_0402_5%

N12P-GS1-A1_BGA_973P GS@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 27 of 57
5 4 3 2 1
 5 4 3 2 1

U1400C

Part 3 of 7 F18 CMDB0

MDB[0..63] FBC_CMD0 CMDB0 31
MDB0 B13 E19
31,32 MDB[0..63] FBC_D0 FBC_CMD1
MDB1 D13 D18 CMDB2
FBC_D1 FBC_CMD2 CMDB2 31
MDB2 A13 C17 CMDB3
FBC_D2 FBC_CMD3 CMDB3 31
MDB3 A14 F19 CMDB4
FBC_D3 FBC_CMD4 CMDB4 31,32
MDB4 C16 C19 CMDB5
FBC_D4 FBC_CMD5 CMDB5 31,32
D MDB5 B16 B17 CMDB6 D
FBC_D5 FBC_CMD6 CMDB6 31,32
MDB6 A17 E20 CMDB7
FBC_D6 FBC_CMD7 CMDB7 31,32
MDB7 D16 B19 CMDB8
MDB8 C13
FBC_D7 FBC_CMD8
D20 CMDB9
CMDB8 31,32 GB2-128
FBC_D8 FBC_CMD9 CMDB9 31,32
MDB9 B11 A19 CMDB10
MDB10 C11
FBC_D9 FBC_CMD10
D19 CMDB11
CMDB10 31,32 Mode E - Mirror Mode Mapping
FBC_D10 FBC_CMD11 CMDB11 31,32
MDB11 A11 C20 CMDB12 DATA Bus
FBC_D11 FBC_CMD12 CMDB12 31,32
MDB12 C10 F20 CMDB13
FBC_D12 FBC_CMD13 CMDB13 31,32
MDB13 C8 B20 CMDB14 Address 0..31 32..63
FBC_D13 FBC_CMD14 CMDB14 31,32
MDB14 B8 G21 CMDB15
FBC_D14 FBC_CMD15 CMDB15 31,32
MDB15 A8 F22 CMDB16 CMD3 CKE_L
FBC_D15 FBC_CMD16 CMDB16 32
MDB16 E8 F24
MDB17 FBC_D16 FBC_CMD17 CMDB18
F8 FBC_D17 FBC_CMD18 F23 CMDB18 32 CMD8 A8 A8
MDB18 F10 C25 CMDB19
FBC_D18 FBC_CMD19 CMDB19 32
MDB19 F9 C23 CMDB20 CMD2 CS0#_L
FBC_D19 FBC_CMD20 CMDB20 31,32
MDB20 F12 F21 CMDB21
FBC_D20 FBC_CMD21 CMDB21 31,32
MDB21 D8 E22 CMDB22 CMD21 A7 A6
FBC_D21 FBC_CMD22 CMDB22 31,32
MDB22 D11 D21 CMDB23
FBC_D22 FBC_CMD23 CMDB23 31,32
MDB23 E11 A23 CMDB24 CMD24 A2 A1
FBC_D23 FBC_CMD24 CMDB24 31,32
MDB24 D12 D22 CMDB25
FBC_D24 FBC_CMD25 CMDB25 31,32
MDB25 E13 B23 CMDB26 CMD23 A11 A9

MEMORY INTERFACE C
FBC_D25 FBC_CMD26 CMDB26 31,32
MDB26 F13 C22 CMDB27
FBC_D26 FBC_CMD27 CMDB27 31,32
MDB27 F14 B22 CMDB28 CMD26 A5 A4
FBC_D27 FBC_CMD28 CMDB28 31,32
MDB28 F15 A22 CMDB29
FBC_D28 FBC_CMD29 CMDB29 31,32
MDB29 E16 A20 CMDB30 CMD7 A0 A12
FBC_D29 FBC_CMD30 CMDB30 31,32
MDB30 F16 G20
MDB31 FBC_D30 FBC_CMD31
F17 FBC_D31 CMD15 CAS# CAS#
C MDB32 D29 A16 DQMB0 C
MDB33 FBC_D32 FBC_DQM0 DQMB1
F27 FBC_D33 FBC_DQM1 D10 CMD13 BA1 A3
MDB34 F28 F11 DQMB2
MDB35 FBC_D34 FBC_DQM2 DQMB3
E28 FBC_D35 FBC_DQM3 D15 DQMB[7..0] 31,32 CMD4 A9 A11
MDB36 D26 D27 DQMB4
FBC_D36 FBC_DQM4 DQSB#[7..0] 31,32
MDB37 F25 D34 DQMB5 CMD18 CS0#_H
FBC_D37 FBC_DQM5 DQSB[7..0] 31,32
MDB38 D24 A34 DQMB6
MDB39 FBC_D38 FBC_DQM6 DQMB7
E25 FBC_D39 FBC_DQM7 D28 CMD29 BA0 BA0
MDB40 E32
MDB41 FBC_D40 DQSB#0
F32 FBC_D41 FBC_DQS_RN0 B14 CMD27 BA2 A15
MDB42 D33 B10 DQSB#1
MDB43 FBC_D42 FBC_DQS_RN1 DQSB#2
E31 FBC_D43 FBC_DQS_RN2 D9 CMD6 A3 BA1
MDB44 C33 E14 DQSB#3
MDB45 FBC_D44 FBC_DQS_RN3 DQSB#4
F29 FBC_D45 FBC_DQS_RN4 F26 CMD17 CS1#_H
MDB46 D30 D31 DQSB#5
MDB47 FBC_D46 FBC_DQS_RN5 DQSB#6
E29 FBC_D47 FBC_DQS_RN6 A31 CMD19 ODT_H
MDB48 B29 A26 DQSB#7
MDB49 FBC_D48 FBC_DQS_RN7
C31 FBC_D49 CMD22 A4 A5
MDB50 C29 C14 DQSB0
MDB51 FBC_D50 FBC_DQS_WP0 DQSB1
B31 FBC_D51 FBC_DQS_WP1 A10 CMD12 A13 A14
MDB52 C32 E10 DQSB2
MDB53 FBC_D52 FBC_DQS_WP2 DQSB3
B32 FBC_D53 FBC_DQS_WP3 D14 CMD28 WE# A10
MDB54 B35 E26 DQSB4
MDB55 FBC_D54 FBC_DQS_WP4 DQSB5
B34 FBC_D55 FBC_DQS_WP5 D32 CMD10 A1 A2
MDB56 A29 A32 DQSB6
MDB57 FBC_D56 FBC_DQS_WP6 DQSB7
B28 FBC_D57 FBC_DQS_WP7 B26 CMD25 A10 WE#
MDB58 A28
MDB59 FBC_D58
B C28 FBC_D59 FBC_WCK0 G14 CMD9 A12 A0 B
MDB60 C26 G15
MDB61 FBC_D60 FBC_WCK0_N
D25 FBC_D61 FBC_WCK1 G11 CMD1 CS1#_L
MDB62 B25 G12
MDB63 FBC_D62 FBC_WCK1_N
A25 FBC_D63 FBC_WCK2 G27 CMD11 RAS# RAS#
FBC_WCK2_N G28
FBC_WCK3 G24 CMD0 ODT_L
+VRAM_1.5VS 1 OPT@ 2 K27 FBCAL_PD_VDDQ FBC_WCK3_N G25
R1447 40.2_0402_1% CMD5 A6 A7
1 OPT@ 2 L27 FBCAL_PU_GND
R1448 40.2_0402_1% E17 CLKB0 CMD16 CKE_H
FBC_CLK0 CLKB0 31
1 OPT@ 2 M27 FBCAL_TERM_GND FBC_CLK0_N D17 CLKB0#
CLKB0# 31
R1449 60.4_0402_1% CMD20 RST RST
+VRAM_1.5VS 2 OPT@ 1 G19 D23 CLKB1
FBC_DEBUG0 FBC_CLK1 CLKB1 32
R1450 2 OPT@ 1 60.4_0402_1% G16 E23 CLKB1# CMD14 A14 A13
FBB_DEBUG1 FBC_CLK1_N CLKB1# 32
R1451 10K_0402_5%
CMD30 A15 BA2
N12P-GS1-A1_BGA_973P GS@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 28 of 57
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits MDA[0..63] 27,30

CMDA[30..0] 27,30

DQMA[7..0] 27,30
U1402 U1403
DQSA[7..0] 27,30
+VRAM_1.5VS +FBA_VREF0 M8 E3 MDA3 +FBA_VREF0 M8 E3 MDA19
VREFCA DQL0 VREFCA DQL0 DQSA#[7..0] 27,30
H1 F7 MDA6 H1 F7 MDA17
VREFDQ DQL1 MDA1 VREFDQ DQL1 MDA18
DQL2 F2 DQL2 F2
1

D CMDA7 N3 F8 MDA4 CMDA7 N3 F8 MDA16 Group2 D

R1452 CMDA10 A0 DQL3 MDA2 CMDA10 A0 DQL3 MDA20
P7 A1 DQL4 H3 Group0 P7 A1 DQL4 H3
1.1K_0402_1% CMDA24 P3 H8 MDA7 CMDA24 P3 H8 MDA22
OPT@ CMDA6 A2 DQL5 MDA0 CMDA6 A2 DQL5 MDA21
Layout: trace width 40mil N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA22 P8 H7 MDA5 CMDA22 P8 H7 MDA23
2

+FBA_VREF0 CMDA26 A4 DQL7 CMDA26 A4 DQL7

P2 A5 P2 A5
CMDA5 R8 CMDA5 R8
A6 A6
1

CMDA21 R2 D7 MDA29 CMDA21 R2 D7 MDA14

R1453
1
C1518 CMDA8 T8
A7 DQU0
C3 MDA26 CMDA8 T8
A7 DQU0
C3 MDA9
GB2-128
1.1K_0402_1% 0.01U_0402_25V7K CMDA4 A8 DQU1 MDA30 CMDA4 A8 DQU1 MDA12
R3 A9 DQU2 C8 R3 A9 DQU2 C8 Mode E - Mirror Mode Mapping
OPT@ OPT@ CMDA25 L7 C2 MDA24 CMDA25 L7 C2 MDA11
2 CMDA23 A10/AP DQU3 MDA27 CMDA23 A10/AP DQU3 MDA13
R7 A7 Group3 R7 A7 Group1 DATA Bus
2

CMDA9 A11 DQU4 MDA25 CMDA9 A11 DQU4 MDA8

N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDA12 T3 B8 MDA31 CMDA12 T3 B8 MDA15 Address 0..31 32..63
CMDA14 A13 DQU6 MDA28 CMDA14 A13 DQU6 MDA10
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDA30 M7 CMDA30 M7 CMD3 CKE_L
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD8 A8 A8
CMDA29 M2 B2 CMDA29 M2 B2
CMDA13 BA0 VDD CMDA13 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD2 CS0#_L
CLKA0 CMDA27 M3 G7 CMDA27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD21 A7 A6
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD24 A2 A1

OPT@ CLKA0 J7 N9 CLKA0 J7 N9
27 CLKA0 CK VDD CK VDD
160_0402_1% CLKA0# K7 R1 CLKA0# K7 R1 CMD23 A11 A9
27 CLKA0# CK VDD CK VDD
R1454 CMDA3 K9 R9 CMDA3 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
C CMD26 A5 A4 C
1

CLKA0# CMDA0 K1 A1 CMDA0 K1 A1 CMD7 A0 A12

CMDA2 ODT/ODT0 VDDQ CMDA2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDA11 J3 C1 CMDA11 J3 C1 CMD15 CAS# CAS#
CMDA15 RAS VDDQ CMDA15 RAS VDDQ CMDA0
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDA28 L3 D2 CMDA28 L3 D2 CMD13 BA1 A3
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
F1 F1 CMDA3 CMD4 A9 A11
DQSA0 VDDQ DQSA2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
DQSA3 C7 H9 DQSA1 C7 H9 CMD18 CS0#_H
DQSU VDDQ DQSU VDDQ

2
R1455 R1456 CMD29 BA0 BA0
DQMA0 E7 A9 DQMA2 E7 A9 10K_0402_5% 10K_0402_5%
DQMA3 DML VSS DQMA1 DML VSS OPT@ OPT@
D3 DMU VSS B3 D3 DMU VSS B3 CMD27 BA2 A15
E1 E1

1
VSS VSS
VSS G8 VSS G8 CMD6 A3 BA1
DQSA#0 G3 J2 DQSA#2 G3 J2
DQSA#3 DQSL VSS DQSA#1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD17 CS1#_H
VSS M1 VSS M1
VSS M9 VSS M9 CMD19 ODT_H
VSS P1 VSS P1
CMDA20 T2 P9 CMDA20 T2 P9 CMD22 A4 A5
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD12 A13 A14
CMD28 WE# A10
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 B
R1457 R1458 L1 B9 R1459 L1 B9 CMD10 A1 A2
10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
OPT@ OPT@ L9 D8 OPT@ L9 D8 CMD25 A10 WE#
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD9 A12 A0
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD1 CS1#_L
VSSQ G9 VSSQ G9
CMD11 RAS# RAS#
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD0 ODT_L
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@ CMD5 A6 A7
CMD16 CKE_H
+VRAM_1.5VS +VRAM_1.5VS
CMD20 RST RST
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
CMD14 A14 A13
OPT@ C1601

OPT@ C1523

OPT@ C1524

OPT@ C1525

OPT@ C1526

OPT@ C1527

OPT@ C1532

OPT@ C1533

OPT@ C1534

OPT@ C1535

OPT@ C1536
1000P_0402_50V7K

4.7U_0603_6.3V6M
OPT@ C1519

4.7U_0603_6.3V6M
OPT@ C1520

4.7U_0603_6.3V6M
OPT@ C1521

4.7U_0603_6.3V6M
OPT@ C1522

4.7U_0603_6.3V6M
OPT@ C1528

4.7U_0603_6.3V6M
OPT@ C1529

4.7U_0603_6.3V6M
OPT@ C1530

4.7U_0603_6.3V6M
OPT@ C1531

1 1 1 1 1 1 1 1 1 1 CMD30 A15 BA2

1

1
2

2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 29 of 57
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits

MDA[0..63] 27,29

CMDA[30..0] 27,29
U1404 U1405
+VRAM_1.5VS
DQMA[7..0] 27,29
+FBA_VREF1 M8 E3 MDA38 +FBA_VREF1 M8 E3 MDA58
VREFCA DQL0 MDA33 VREFCA DQL0 MDA59
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSA[7..0] 27,29
1
F2 MDA39 F2 MDA57
R1460 CMDA9 DQL2 MDA35 CMDA9 DQL2 MDA61
D N3 A0 DQL3 F8 N3 A0 DQL3 F8 DQSA#[7..0] 27,29 D
1.1K_0402_1% CMDA24 P7 H3 MDA36 Group4 CMDA24 P7 H3 MDA60 Group7
OPT@ CMDA10 A1 DQL4 MDA34 CMDA10 A1 DQL4 MDA62
Layout: trace width 40mil P3 A2 DQL5 H8 P3 A2 DQL5 H8
CMDA13 N2 G2 MDA37 CMDA13 N2 G2 MDA56
2

+FBA_VREF1 CMDA26 A3 DQL6 MDA32 CMDA26 A3 DQL6 MDA63

P8 A4 DQL7 H7 P8 A4 DQL7 H7
CMDA22 P2 CMDA22 P2
A5 A5
1

1 CMDA21 R8 CMDA21 R8
R1461 C1537 CMDA5 A6 MDA42 CMDA5 A6 MDA51
R2 A7 DQU0 D7 R2 A7 DQU0 D7 GB2-128
1.1K_0402_1% 0.01U_0402_25V7K CMDA8 T8 C3 MDA45 CMDA8 T8 C3 MDA52
OPT@ OPT@ CMDA23 A8 DQU1 MDA40 CMDA23 A8 DQU1 MDA48
R3 A9 DQU2 C8 R3 A9 DQU2 C8 Mode E - Mirror Mode Mapping
2 CMDA28 MDA46 CMDA28 MDA53
L7 C2 L7 C2
2

CMDA4 A10/AP DQU3 MDA41 CMDA4 A10/AP DQU3 MDA49

R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group6 DATA Bus
CMDA7 N7 A2 MDA47 CMDA7 N7 A2 MDA54
CMDA14 A12 DQU5 MDA43 CMDA14 A12 DQU5 MDA50
T3 A13 DQU6 B8 T3 A13 DQU6 B8 Address 0..31 32..63
CMDA12 T7 A3 MDA44 CMDA12 T7 A3 MDA55
CMDA27 A14 DQU7 CMDA27 A14 DQU7
M7 A15/BA3 +VRAM_1.5VS
M7 A15/BA3 +VRAM_1.5VS
CMD3 CKE_L
CMD8 A8 A8
CMDA29 M2 B2 CMDA29 M2 B2
CMDA6 BA0 VDD CMDA6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD2 CS0#_L
CLKA1 CMDA30 M3 G7 CMDA30 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD21 A7 A6
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD24 A2 A1

R1462 CLKA1 J7 N9 CLKA1 J7 N9
27 CLKA1 CK VDD CK VDD
160_0402_1% CLKA1# K7 R1 CLKA1# K7 R1 CMD23 A11 A9
27 CLKA1# CK VDD CK VDD
OPT@ CMDA16 K9 R9 CMDA16 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
C CMD26 A5 A4 C
1

CLKA1# CMDA19 K1 A1 CMDA19 K1 A1 CMD7 A0 A12

CMDA18 ODT/ODT0 VDDQ CMDA18 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDA11 J3 C1 CMDA11 J3 C1 CMD15 CAS# CAS#
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDA25 L3 D2 CMDA25 L3 D2 CMD13 BA1 A3
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD4 A9 A11
DQSA4 F3 H2 DQSA7 F3 H2
DQSA5 DQSL VDDQ DQSA6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD18 CS0#_H
CMDA19 CMD29 BA0 BA0
DQMA4 E7 A9 DQMA7 E7 A9
DQMA5 DML VSS DQMA6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD27 BA2 A15
E1 E1 CMDA16
VSS VSS
VSS G8 VSS G8 CMD6 A3 BA1
DQSA#4 G3 J2 DQSA#7 G3 J2
DQSA#5 DQSL VSS DQSA#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD17 CS1#_H

2
VSS M1 VSS M1
M9 M9 R1463 R1464 CMD19 ODT_H
VSS VSS 10K_0402_5% 10K_0402_5%
VSS P1 VSS P1
CMDA20 T2 P9 CMDA20 T2 P9 OPT@ OPT@ CMD22 A4 A5
RESET VSS RESET VSS
T1 T1

1
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD12 A13 A14
CMD28 WE# A10
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 B
R1465 L1 B9 R1466 L1 B9 CMD10 A1 A2
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
OPT@ L9 D8 OPT@ L9 D8 CMD25 A10 WE#
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD9 A12 A0
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD1 CS1#_L
VSSQ G9 VSSQ G9
CMD11 RAS# RAS#
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD0 ODT_L
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@ CMD5 A6 A7
+VRAM_1.5VS +VRAM_1.5VS CMD16 CKE_H
CMD20 RST RST
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
OPT@ C1538

OPT@ C1539

OPT@ C1540

OPT@ C1541

OPT@ C1542

OPT@ C1543

OPT@ C1544

OPT@ C1545

OPT@ C1546

CMD14 A14 A13

4.7U_0603_6.3V6M
OPT@ C1547

4.7U_0603_6.3V6M
OPT@ C1548

4.7U_0603_6.3V6M
OPT@ C1549

4.7U_0603_6.3V6M
OPT@ C1550

4.7U_0603_6.3V6M
OPT@ C1551

4.7U_0603_6.3V6M
OPT@ C1552

4.7U_0603_6.3V6M
OPT@ C1553

4.7U_0603_6.3V6M
OPT@ C1554

4.7U_0603_6.3V6M
OPT@ C1555
1 1 1 1 1 1 1 1 1
1

1
CMD30 A15 BA2
2

2
2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 30 of 57
5 4 3 2 1
 5 4 3 2 1

MDB[0..63] 28,32
Memory Partition C - Lower 32 bits CMDB[30..0] 28,32

DQMB[7..0] 28,32

DQSB[7..0] 28,32
+VRAM_1.5VS U1406 U1407
DQSB#[7..0] 28,32
+FBB_VREF0 M8 E3 MDB3 +FBB_VREF0 M8 E3 MDB16
VREFCA DQL0 VREFCA DQL0
1
D H1 F7 MDB5 H1 F7 MDB17 D
R1467 VREFDQ DQL1 MDB2 VREFDQ DQL1 MDB19
DQL2 F2 DQL2 F2
1.1K_0402_1% CMDB7 N3 F8 MDB4 Group0 CMDB7 N3 F8 MDB18
GS@ CMDB10 A0 DQL3 MDB1 CMDB10 A0 DQL3 MDB23
Layout: trace width 40mil P7 A1 DQL4 H3 P7 A1 DQL4 H3 Group2 GB2-128
CMDB24 P3 H8 MDB6 CMDB24 P3 H8 MDB21
2

+FBB_VREF0 CMDB6 A2 DQL5 MDB0 CMDB6 A2 DQL5 MDB22

CMDB22
N2
P8
A3 DQL6 G2
H7 MDB7 CMDB22
N2
P8
A3 DQL6 G2
H7 MDB20
Mode E - Mirror Mode Mapping
A4 DQL7 A4 DQL7
1

1 CMDB26 P2 CMDB26 P2 DATA Bus

R1468 C1556 CMDB5 A5 CMDB5 A5
R8 A6 R8 A6
1.1K_0402_1% 0.01U_0402_25V7K CMDB21 R2 D7 MDB31 CMDB21 R2 D7 MDB13 Address 0..31 32..63
GS@ GS@ CMDB8 A7 DQU0 MDB25 CMDB8 A7 DQU0 MDB9
T8 A8 DQU1 C3 T8 A8 DQU1 C3
2 CMDB4 MDB29 CMDB4 MDB14
R3 C8 R3 C8 CMD3 CKE_L
2

CMDB25 A9 DQU2 MDB24 CMDB25 A9 DQU2 MDB11

L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
CMDB23 R7 A7 MDB28 Group3 CMDB23 R7 A7 MDB12 Group1 CMD8 A8 A8
CMDB9 A11 DQU4 MDB26 CMDB9 A11 DQU4 MDB8
N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDB12 T3 B8 MDB30 CMDB12 T3 B8 MDB15 CMD2 CS0#_L
CMDB14 A13 DQU6 MDB27 CMDB14 A13 DQU6 MDB10
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDB30 M7 CMDB30 M7 CMD21 A7 A6
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD24 A2 A1
CMDB29 M2 B2 CMDB29 M2 B2
CMDB13 BA0 VDD CMDB13 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD23 A11 A9
CLKB0 CMDB27 M3 G7 CMDB27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD26 A5 A4
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD7 A0 A12

R1469 CLKB0 J7 N9 CLKB0 J7 N9
28 CLKB0 CK VDD CK VDD
C 160_0402_1% CLKB0# K7 R1 CLKB0# K7 R1 CMD15 CAS# CAS# C
28 CLKB0# CK VDD CK VDD
GS@ CMDB3 K9 R9 CMDB3 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
CMD13 BA1 A3
1

CLKB0# CMDB0 K1 A1 CMDB0 K1 A1 CMD4 A9 A11

CMDB2 ODT/ODT0 VDDQ CMDB2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDB11 J3 C1 CMDB11 J3 C1 CMD18 CS0#_H
CMDB15 RAS VDDQ CMDB15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDB28 L3 D2 CMDB28 L3 D2 CMD29 BA0 BA0
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD27 BA2 A15
DQSB0 F3 H2 DQSB2 F3 H2 CMDB0
DQSB3 DQSL VDDQ DQSB1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD6 A3 BA1
CMDB3 CMD17 CS1#_H
DQMB0 E7 A9 DQMB2 E7 A9
DQMB3 DML VSS DQMB1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD19 ODT_H
VSS E1 VSS E1

2
VSS G8 VSS G8 CMD22 A4 A5
DQSB#0 G3 J2 DQSB#2 G3 J2
DQSB#3 DQSL VSS DQSB#1 DQSL VSS R1470 R1471
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD12 A13 A14
M1 M1 10K_0402_5% 10K_0402_5%
VSS VSS GS@ GS@
M9 M9 CMD28 WE# A10

1
VSS VSS
VSS P1 VSS P1
CMDB20 T2 P9 CMDB20 T2 P9 CMD10 A1 A2
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD25 A10 WE#
B B
CMD9 A12 A0
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
R1472 R1473 L1 B9 R1474 L1 B9 CMD1 CS1#_L
10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
GS@ GS@ L9 D8 GS@ L9 D8 CMD11 RAS# RAS#
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD0 ODT_L
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD5 A6 A7
VSSQ G9 VSSQ G9
CMD16 CKE_H
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD20 RST RST
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@ CMD14 A14 A13
+VRAM_1.5VS +VRAM_1.5VS CMD30 A15 BA2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
GS@

GS@ C1561

GS@ C1562

GS@ C1563

GS@ C1564

GS@ C1565

GS@ C1566

GS@ C1567

GS@ C1568

GS@ C1569

GS@ C1570

GS@ C1571

GS@ C1572

GS@ C1573

GS@ C1574
1000P_0402_50V7K

4.7U_0603_6.3V6M
GS@ C1557

4.7U_0603_6.3V6M
GS@ C1558

4.7U_0603_6.3V6M
GS@ C1559

4.7U_0603_6.3V6M
GS@ C1560

1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

1
C1602
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 31 of 57
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

MDB[0..63] 28,31

CMDB[30..0] 28,31
U1408 U1409

+VRAM_1.5VS DQMB[7..0] 28,31

+FBB_VREF1 M8 E3 MDB37 +FBB_VREF1 M8 E3 MDB56
VREFCA DQL0 MDB35 VREFCA DQL0 MDB63
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSB[7..0] 28,31
D F2 MDB36 F2 MDB57 D
DQL2 DQL2
1
CMDB9 N3 F8 MDB34 CMDB9 N3 F8 MDB62
A0 DQL3 A0 DQL3 DQSB#[7..0] 28,31
R1475 CMDB24 P7 H3 MDB38 Group4 CMDB24 P7 H3 MDB58 Group7
1.1K_0402_1% CMDB10 A1 DQL4 MDB32 CMDB10 A1 DQL4 MDB60
P3 A2 DQL5 H8 P3 A2 DQL5 H8
GS@ Layout: trace width 40mil CMDB13 N2 G2 MDB39 CMDB13 N2 G2 MDB59
CMDB26 A3 DQL6 MDB33 CMDB26 A3 DQL6 MDB61
P8 H7 P8 H7
2

+FBB_VREF1 CMDB22 A4 DQL7 CMDB22 A4 DQL7

P2 A5 P2 A5
CMDB21 R8 CMDB21 R8
A6 A6
1

CMDB5 MDB41 CMDB5 MDB49

R1476
1
C1575 CMDB8
R2
T8
A7 DQU0 D7
C3 MDB46 CMDB8
R2
T8
A7 DQU0 D7
C3 MDB55
GB2-128
1.1K_0402_1% 0.01U_0402_25V7K CMDB23 A8 DQU1 MDB42 CMDB23 A8 DQU1 MDB48
GS@ GS@ CMDB28
R3
L7
A9 DQU2 C8
C2 MDB47 CMDB28
R3
L7
A9 DQU2 C8
C2 MDB53
Mode E - Mirror Mode Mapping
2 CMDB4 A10/AP DQU3 MDB44 CMDB4 A10/AP DQU3 MDB51
R7 A7 Group5 R7 A7 Group6 DATA Bus
2

CMDB7 A11 DQU4 MDB45 CMDB7 A11 DQU4 MDB52

N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDB14 T3 B8 MDB40 CMDB14 T3 B8 MDB50 Address 0..31 32..63
CMDB12 A13 DQU6 MDB43 CMDB12 A13 DQU6 MDB54
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDB27 M7 CMDB27 M7 CMD3 CKE_L
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD8 A8 A8
CMDB29 M2 B2 CMDB29 M2 B2
CMDB6 BA0 VDD CMDB6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD2 CS0#_L
CMDB30 M3 G7 CMDB30 M3 G7
CLKB1 BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD21 A7 A6
VDD K8 VDD K8
VDD N1 VDD N1 CMD24 A2 A1
2

CLKB1 J7 N9 CLKB1 J7 N9
28 CLKB1 CK VDD CK VDD
R1477 CLKB1# K7 R1 CLKB1# K7 R1 CMD23 A11 A9
28 CLKB1# CK VDD CK VDD
C 160_0402_1% CMDB16 K9 R9 CMDB16 K9 R9 C
CKE/CKE0 VDD CKE/CKE0 VDD
GS@ CMD26 A5 A4
1

CMDB19 K1 A1 CMDB19 K1 A1 CMD7 A0 A12

CLKB1# CMDB18 ODT/ODT0 VDDQ CMDB18 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDB11 J3 C1 CMDB11 J3 C1 CMD15 CAS# CAS#
CMDB15 RAS VDDQ CMDB15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDB25 L3 D2 CMDB25 L3 D2 CMD13 BA1 A3
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD4 A9 A11
DQSB4 F3 H2 DQSB7 F3 H2
DQSB5 DQSL VDDQ DQSB6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD18 CS0#_H
CMD29 BA0 BA0
DQMB4 E7 A9 DQMB7 E7 A9
DQMB5 DML VSS DQMB6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD27 BA2 A15
VSS E1 VSS E1
G8 G8 CMDB19 CMD6 A3 BA1
DQSB#4 VSS DQSB#7 VSS
G3 DQSL VSS J2 G3 DQSL VSS J2
DQSB#5 B7 J8 DQSB#6 B7 J8 CMD17 CS1#_H
DQSU VSS DQSU VSS CMDB16
VSS M1 VSS M1
VSS M9 VSS M9 CMD19 ODT_H
VSS P1 VSS P1

2
CMDB20 T2 P9 CMDB20 T2 P9 CMD22 A4 A5
RESET VSS RESET VSS R1478 R1479
VSS T1 VSS T1
L8 T9 L8 T9 10K_0402_5% 10K_0402_5% CMD12 A13 A14
ZQ/ZQ0 VSS ZQ/ZQ0 VSS GS@ GS@
B CMD28 WE# A10 B

1
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
R1480 L1 B9 R1481 L1 B9 CMD10 A1 A2
+VRAM_1.5VS NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 D8 GS@ L9 D8 CMD25 A10 WE#
GS@ NCZQ1 VSSQ NCZQ1 VSSQ
1 E2 E2
2

2
GS@ VSSQ VSSQ
+ VSSQ E8 VSSQ E8 CMD9 A12 A0
C1576 F9 F9
220U_D2_4VY_R15M VSSQ VSSQ
VSSQ G1 VSSQ G1 CMD1 CS1#_L
VSSQ G9 VSSQ G9
2
CMD11 RAS# RAS#
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD0 ODT_L
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@ CMD5 A6 A7
+VRAM_1.5VS +VRAM_1.5VS
CMD16 CKE_H
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CMD20 RST RST

GS@ C1577

GS@ C1578

GS@ C1579

GS@ C1580

GS@ C1581

GS@ C1582

GS@ C1583

GS@ C1584

GS@ C1585

4.7U_0603_6.3V6M
GS@ C1586

4.7U_0603_6.3V6M
GS@ C1587

4.7U_0603_6.3V6M
GS@ C1588

4.7U_0603_6.3V6M
GS@ C1589

4.7U_0603_6.3V6M
GS@ C1590

4.7U_0603_6.3V6M
GS@ C1591

4.7U_0603_6.3V6M
GS@ C1592

4.7U_0603_6.3V6M
GS@ C1593

4.7U_0603_6.3V6M
GS@ C1594
1 1 1 1 1 1 1 1 1 CMD14 A14 A13
1

1
CMD30 A15 BA2
2

2
2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 32 of 57
5 4 3 2 1
 5 4 3 2 1

GS: Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VSDGPU N12P-GV QS DevID: 0x1050,
1. ROM_SCLK: pull up 5K ohm. ROM_SO +3VS_DGPU XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
2. STRAP2: pull down 5K ohm.
No6 3. ROM_SO: pull up 10K ohm. ROM_SCLK +3VS_DGPU PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLLEN_TERM
No47 4. STRAP3: pull down 5K ohm. ROM_SI +3VS_DGPU RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]

2
5. STRAP4: pull down 10K ohm.
R1482 R1483 R1484 6. STRAP_REF2, need to stuff with 40K ohm 1%. STRAP2 +3VS_DGPU PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
45.3K_0402_1% 34.8K_0402_1% 45.3K_0402_1%
7. PGOOD (pin E7) stuff 10K ohm.
OPT@ @ @ STRAP1 +3VS_DGPU 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
D D

1
STRAP0: as same as N12P-GS with 45K pull up. STRAP0 +3VS_DGPU USER[3] USER[2] USER[1] USER[0]
STRAP0 STRAP1: pull down 35K as N12P-GS
23 STRAP0
23 STRAP1 STRAP1
23 STRAP2 STRAP2
GV: Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
2

2
R1485 R1486 R1487
GB1b-64 ROM_SO +3VS_DGPU FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
45.3K_0402_1% 34.8K_0402_1% 24.9K_0402_1%
@ OPT@ GS@ ROM_SCLK +3VS_DGPU PCI_DEVID[4] SUB_VENDOR PCI_DEVID[5] PEX_PLLEN_TERM
1

1
No47 ROM_SI +3VS_DGPU RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
STRAP2 +3VS_DGPU PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
R1490 R1487 STRAP1 +3VS_DGPU 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
STRAP0 +3VS_DGPU USER[3] USER[2] USER[1] USER[0]

+3VSDGPU
STRAP3 +3VS_DGPU SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
4.99K_0402_1% 4.99K_0402_1% STRAP4 +3VS_DGPU RESERVED RESERVED PCIE_MAX_SPEED DP_PLL_VDD33V
GV@ GV@

No6 No47
2

C C

R1488 R1489
15K_0402_1% 10K_0402_1% GS@
@ GV@ R1490
1

15K_0402_1% Resistor Values Pull-up to +3VS Pull-down to Gnd

N11P-GS strap0 strap1 strap2 ROM_SI ROM_SO ROM_SCLK
Option Component 5K 1000 0000
23 ROM_SI ROM_SI 64MX16 H L L L L H
23 ROM_SO ROM_SO Samsung 45K 35K GV@ 20K 10K 15K 10K 1001 0001
23 ROM_SCLK ROM_SCLK SA000035700 GS@
U1400 L 15K 1010 0010
64MX16 H L L L H
2

Hynix 45K 35K GV@ 15K 10K 15K 20K 1011 0011
R1491 R1492 R1493 SA000032400 GS@
X76 20K_0402_5% 10K_0402_1% 15K_0402_1% 25K 1100 0100
X76@ GS@ @ 128MX16 H L L L L H
N12P-GV-OP-B-A1_BGA973 Samsung 45K 35K 45K 10K 15K 30K 1101 0101
1

GV@ GS@
SA00004JO00 35K 1110 0110
128MX16 H L L L L H
Hynix 45K 35K 35K 10K 15K 45K 1111 0111
SA00003VS10 GS@

GPU DeviceID ROM_SCLK STRAP2

B Hynix (900MHZ) 512MB 0010 PD 15K (SD034150280) N12P-GS 0x0DF4 Pull up 15K Pull down 25K
B

64MX16 H5TQ1G63DFR-11C
SA000041S40 1GB 0010 PD 15K (SD034150280) N12P-GE 0x0DF5 Pull up 15K Pull down 30K

N12P-GV 0x1050 Pull up 5K pull down 5K

Hynix 2G No2 No44
128MX16 H5TQ2G63BFR-12C 2GB 0110 PD 34.8k(SD034348280)
SA00003YO20

Samsung (900MHZ) 512MB 0011 PD 20K (SD034200280) No1

No44
64MX16 K4W1G1646G-BC11
SA00004GS10 1GB 0011 PD 20K (SD034200280)

Samsung 2G
A
128M16 K4W2G1646C-HC12 2GB 0111 PD 45.3K(SD034453280) A
SA000047Q20

XCLK_417 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/23 Deciphered Date 2011/08/25 Title
0 277MHz (Default) SCHEMATIC,MB LA-A7121
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1 Reserved DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 33 of 57
5 4 3 2 1
 5 4 3 2 1

+LCDVDD
LCD POWER CIRCUIT
+3VALW +3VS
W=60mils

1
D D

1
R2100 +INVPWR_B+ L2100 B+
Place closed to JLVDS1

1
300_0603_5% R2101 C2101 +LCDVDD FBMA-L11-201209-221LMA30T_0805
4.7U_0805_10V4Z +3VS W=60mils
10K_0402_5% 2 1

2
L2101

2
FBMA-L11-201209-221LMA30T_0805

2
R2102 2 1

1
D 10K_0402_5% S Q2101 C2102 C2103 C2104
2 2 1 2 AO3413L_SOT23-3

1
Q2100 G G 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z C2105 C2106 SM010014520 3000ma

2
2N7002H_SOT23-3 S D 680P_0402_50V7K 68P_0402_50V8J 220ohm@100mhz DCR
3

1
1
C2100 +LCDVDD

2
4.7U_0603_6.3V6K 0.04
W=60mils

1
D

2
PCH_ENVDD 2 Q2102
16 PCH_ENVDD
G 2N7002H_SOT23-3

1
S C2108
3
1

C2107 0.1U_0402_16V4Z
R2103 4.7U_0805_10V4Z
LCD/LED PANEL Conn.

2
100K_0402_5% +3VS

No33 R2104 1 2 2.2K_0402_5% PCH_LCD_CLK No12 pin 4, 8,9,34 changed, should check with JM40/50
2

R2105 1 2 2.2K_0402_5% PCH_LCD_DATA W=60mils

+INVPWR_B+

1
@ C2109 @ C2110 JLVDS1 CONN@
10P_0402_50V8J 10P_0402_50V8J 1 1
2

2
2
3 3
T2100PAD COLOR_ENG_EN 4
DAC_BRIG 4
41 DAC_BRIG 5 5
DISPOFF# 6
C U2102 +3VS INVTPWM 6 C
7 7
1 R2107 2 1 OE# 46 DMIC_DATA 8 8
100K_0402_5% 5 9
VCC 46 DMIC_CLK 9
EDP_AUX_R 10
R2108 1 10
16 DPST_PWM 2 IN 41 BKOFF# 2 0_0402_5% DISPOFF# EDP_AUX#_R 11 11
12 12
4 INVTPWM R2109 1 2 10K_0402_5% EDP_TX1_R 13
OUT EDP_TX1#_R 13
3 GND 14 14
1

15 15
74AHC1G125GW_SOT353-5 R2110 C2111 2 1 220P_0402_50V7K DAC_BRIG EDP_TX0_R 16
EDP_TX0#_R 16
10K_0402_5% 17 17
C2112 2 1 220P_0402_50V7K INVTPWM 18
PCH_TXCLK+ 18
16 PCH_TXCLK+ 19
2

19
C2113 2 1 220P_0402_50V7K DISPOFF# 16 PCH_TXCLK-
PCH_TXCLK- 20 20
PCH_TXOUT2+ 21
16 PCH_TXOUT2+ 21
PCH_TXOUT2- 22
16 PCH_TXOUT2- 22
23 23
PCH_TXOUT1+ 24
16 PCH_TXOUT1+ 24
PCH_TXOUT1- 25
16 PCH_TXOUT1- 25
26 26
PCH_TXOUT0+ 27
16 PCH_TXOUT0+ 27
PCH_TXOUT0- 28
+3VS 16 PCH_TXOUT0- 28
16 PCH_LCD_DATA PCH_LCD_DATA 29
+LCDVDD PCH_LCD_CLK 29
16 PCH_LCD_CLK 30 30
31 31
W=60mils 32 32
33 33
T2101PAD DCR
eDP +3VS EDP_HPD
34
35
34
35
36 36 G1 41
@ R2112 Near JLVDS1 37 42
+1.05VS_VCCP 1K_0402_5% R2154 1 37 G2
17 USB20_P10 2 0_0402_5% USB20_CMOS_P10 38 38 G3 43
B R2155 1 B
1 2 17 USB20_N10 2 0_0402_5% USB20_CMOS_N10 39 39 G4 44
EDP_TXN0 .1U_0402_16V7K @ 2 1 C2114 EDP_TX0#_R 40 45
4 EDP_TXN0 40 G5

1
4 EDP_HPD# EDP_TXP0 .1U_0402_16V7K @ 2 1 C2115 EDP_TX0_R
4 EDP_TXP0
C2151 C2152 ACES_50398-04071-001
1

D EDP_TXN1 .1U_0402_16V7K @ 2 C2149 EDP_TX1#_R 22P_0402_50V8J

4 EDP_TXN1 1 22P_0402_50V8J

2
Q2103
2N7002H_SOT23-3 G
2 EDP_HPD
4 EDP_TXP1
EDP_TXP1 .1U_0402_16V7K @ 2 1 C2150 EDP_TX1_R @ @
SP010013I00
1

@ S 4 EDP_AUXN EDP_AUXN .1U_0402_16V7K @ 2 1 C2118 EDP_AUX#_R

3

@ 4 EDP_AUXP EDP_AUXP .1U_0402_16V7K @ 2 1 C2119 EDP_AUX_R

R2114 pin define changed, follow JM50
100K_0402_5%
2

D2100
1 V I/O V I/O 6

2 Ground V BUS 5 +3VS

USB20_CMOS_N10 3 4 USB20_CMOS_P10
V I/O V I/O
IP4223CZ6_SO6-6

ESD request

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 34 of 57
5 4 3 2 1
 A B C D E

No36

JM50 ESD team Suggestion

+5VS W=40mils

2
+R_CRT_VCC +CRT_VCC
D2101 F2100
2 1.1A_6V_SMD1812P110TFW=40mils
1 1 2
3
1 D2102 D2103 RB491D-YS_SOT23-3 1

1
PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 C2120
0.1U_0402_16V4Z

2
change P/N: SCS00003H00
CRT Connector
L2102 L2103
BLM18BA470SN1D_2P BLM18BA470SN1D_2P
PCH_CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 JCRT1
16 PCH_CRT_R
L2104 L2105 6
BLM18BA470SN1D_2P BLM18BA470SN1D_2P T92 PAD CRT_P11 11
PCH_CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 1
16 PCH_CRT_G
L2106 L2107 7
BLM18BA470SN1D_2P BLM18BA470SN1D_2P 12
PCH_CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 2
16 PCH_CRT_B
8

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1 13

1
3

1
C2127

C2128

C2129
R2115 R2116 R2117 9

C2121

C2122

C2123

C2124

C2125

C2126
150_0402_1% 150_0402_1% 150_0402_1% 14 G 16
4 17

2
G
10
2

2
15
5

1
C2130
SUYIN_070546FR015S297ZR
100P_0402_50V8J T93 CONN@ DC060003L00

2
SM010012010 300ma 120ohm@100mhz DCR 0.4 PAD CRT_P5
HW3 doesn't use CRT_DET
1 2 CRT_HSYNC_2
2 +CRT_VCC L2108 MBC1608121YZF_0603 DSUB_12 2

C2131 1 2 0.1U_0402_16V4Z R2118 2 1 10K_0402_5% 1 2 CRT_VSYNC_2

1
L2109 MBC1608121YZF_0603

1
5

1
U2101 C2133 C2134 DSUB_15

2
10P_0402_50V8J 10P_0402_50V8J C2132
P

OE#

2
PCH_CRT_HSYNC 2 4 CRT_HSYNC_1 68P_0402_50V8J
16 PCH_CRT_HSYNC A Y

1
G
C2135
74AHCT1G125GW_SOT353-5 68P_0402_50V8J
3

2
+CRT_VCC

C2136 1 2 0.1U_0402_16V4Z

1
U2100

OE#
PCH_CRT_VSYNC 2 4 CRT_VSYNC_1
16 PCH_CRT_VSYNC A Y

G
74AHCT1G125GW_SOT353-5
3
+CRT_VCC

+3VS

1
R2120 R2121
4.7K_0402_5% 4.7K_0402_5%

2
2
G
3 3
Q2104
PCH_CRT_DATA 3 1 2N7002H_SOT23-3 DSUB_12
16 PCH_CRT_DATA

D
2
G
Q2105
16 PCH_CRT_CLK PCH_CRT_CLK 3 1 2N7002H_SOT23-3 DSUB_15

D
PCH DDC PU 2.2K on Page 16

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 35 of 57
A B C D E
 5 4 3 2 1

ESD request
Common mode choke 90ohm on these singals
No36 Compal PN: SM070000K00
Vendor PN: WCM-2012-900T
@ R2129
0_0603_5%
1 2 W=40mils HDMI_CLK+ R2130 1 @ 0_0402_5% HDMI_R_CK+
2
D2105 +HDMI_5V_OUT
D F2101 D
+5VS 2 4 4 3 3
1+HDMI_5V 1 2
3 L2110 WCM-2012-900T_4P

1
RB491D-YS_SOT23-3 1.1A_6V_SMD1812P110TF 1 2
C2137 1 2
0.1U_0402_16V4Z HDMI_CLK- R2131 1 @ 2 0_0402_5% HDMI_R_CK-

2
change P/N: SCS00003H00 +3VS

HDMI_TX0+ R2132 1 @ 2 0_0402_5% HDMI_R_D0+

4 4 3 3

1
R2133 L2111 WCM-2012-900T_4P
1M_0402_5% 1 2
1 2

2
C2138 1 .1U_0402_16V7K HDMI_TX2- HDMI_TX0- R2134 1 @ 0_0402_5% HDMI_R_D0-

G
UMA 16 PCH_DPB_N0 2 2

2
16 PCH_DPB_P0 C2139 2 1 .1U_0402_16V7K HDMI_TX2+
HDMI_HPD 1 3 PCH_DPB_HPD 16
C2140 2 1 .1U_0402_16V7K HDMI_TX1- Q2106 HDMI_TX1+ R2135 1 @ 2 0_0402_5% HDMI_R_D1+

S
C2143
16 PCH_DPB_N1

220P_0402_25V8J
16 PCH_DPB_P1 C2141 2 1 .1U_0402_16V7K HDMI_TX1+ 2N7002H_SOT23-3

1
4 4 3 3
16 PCH_DPB_N2 C2142 2 1 .1U_0402_16V7K HDMI_TX0- R2136
C2144 2 1 .1U_0402_16V7K HDMI_TX0+ 100K_0402_5% L2112 WCM-2012-900T_4P
16 PCH_DPB_P2

2
1 1 2 2
16 PCH_DPB_N3 C2145 2 1 .1U_0402_16V7K HDMI_CLK-

2
16 PCH_DPB_P3 C2146 2 1 .1U_0402_16V7K HDMI_CLK+ HDMI_TX1- R2137 1 @ 2 0_0402_5% HDMI_R_D1-

HDMI_TX2+ R2138 1 @ 2 0_0402_5% HDMI_R_D2+

4 4 3 3
C C
NVIDA Recommand 05/10 WCM-2012-900T_4P
L2113
1 1 2 2
DIS HDMI_TX2- R2139 1 @ 2 0_0402_5% HDMI_R_D2-

HDMI_TX2- R2140 1 2 680_0402_5% HDMI_GND

HDMI_TX2+ R2141 1 2 680_0402_5%
Not reserved
HDMI_TX1- R2142 1 2 680_0402_5%
Not reserved HDMI_TX1+ R2143 1 2 680_0402_5%

HDMI_TX0- R2144 1 2 680_0402_5%

HDMI_TX0+ R2145 1 2 680_0402_5%

HDMI_CLK- R2146 1 2 680_0402_5%

HDMI_CLK+ R2147 1 2 680_0402_5%

UMA 680_0402_5%
+HDMI_5V_OUT DIS 499_0402_1%

1
D
+3VS 2
G
HDMI connector S

3
Q2107
2

2N7002H_SOT23-3
D2106 D2107 JHDMI1 CONN@
RB751V-40_SOD323-2 RB751V-40_SOD323-2 HDMI_HPD 19 HP_DET
+HDMI_5V_OUT 18 +5V
B B
17
2 1

2 1

DDC/CEC_GND
2.2K_0402_5%

2.2K_0402_5%

+3VS HDMI_SDATA 16
HDMI_SCLK SDA
15 SCL
14
R2148

R2149

Reserved
Pull high at VGA side 13 CEC
HDMI_R_CK- 12 CK-
2
G

11 23
1

Q2108 HDMI_R_CK+ CK_shield GND3

1109 RF request 10 22
R2150 HDMI_SCLK_R HDMI_SCLK HDMI_R_D0- CK+ GND2
16 SDVO_SCLK 1 2 0_0402_5% 3 1 2N7002H_SOT23-3 9 D0- GND1 21
S

8 D0_shield GND0 20
2

1
G

HDMI_R_D0+ 7
Q2109 C2147 HDMI_R_D1- D0+
6 D1-
R2151 1 2 0_0402_5% HDMI_SDATA_R 3 1 2N7002H_SOT23-3 HDMI_SDATA 47P_0402_50V8J 5
16 SDVO_SDATA
2

@ HDMI_R_D1+ D1_shield
S

4 D1+
1

HDMI_R_D2- 3
C2148 D2-
2 D2_shield
Place closed to JHDMI1 47P_0402_50V8J HDMI_R_D2+ 1
2

@ D2+

SUYIN_100042GR019M23BZR
DC232001100
+3VS From layout request, change footprint
SUYIN_100042GR019M23BZR_19P-S

R2152 1 2 2.2K_0402_1% SDVO_SCLK

A R2153 1 A
2 2.2K_0402_1% SDVO_SDATA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/08/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 36 of 57
5 4 3 2 1
 5 4 3 2 1

D D

+USB_VCCD
150U_B2_6.3VM_R35M
1 1
C2474
+ C2473
2
2 470P_0402_50V7K

+5VALW +USB_VCCD
U2400
1 8 @ No8
GND VOUT JM50 R2436 +USB_VCCD
2 VIN VOUT 7 1 2 0_0402_5%
3 VIN VOUT 6
EPAD

1 SYSON# 4 5 R2435 1 2 0_0402_5% L2401 WCM-2012-670T_4P JUSB1 CONN@

EN FLG USB_OC1# 17
C2471 USB20_N1 4
17 USB20_N1 4 3 3 USB20_N1_1
1 VCC
2 D-
4.7U_0603_6.3V6K AP2301MPG-13_MSOP8 1 USB20_P1_1 3
9

2 C2472 USB20_P1 D+
17 USB20_P1 1 1 2 2 4 GND
5 VCC GND 9
C 0.1U_0402_16V4Z 6 10 C
2 R2439 1 D- GND
2 0_0402_5% 7 D+ GND 11
@ 8 12
45,46 SYSON# GND GND
TOP_YUB2008-1R0021

DC021011051
use DC021011050 symbol

No15
D2408
6 3 USB20_P1_1

+USB_VCCD 5 2

USB20_N1_1 4 1
B B
CM1293A-04SO_SOT23-6~D

SC300000O00
S DIO(BR) AZC099-04S.R7G SOT23 ESD

ESD request 10/5

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/4 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 37 of 57
5 4 3 2 1
 5 4 3 2 1

D D

should check HDD pin definition

SATA HDD1 Conn.
CL 4.0 mm
JHDD1 CONN@ check: +3VS need or not?
1 1
13 SATA_PTX_DRX_P0 SATA_PTX_DRX_P0 C2460 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
SATA_PTX_DRX_N0 C2461 1 2
13 SATA_PTX_DRX_N0 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3 3
4 4
SATA_DTX_C_PRX_N0 C2462 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N0 5
13 SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 C2463 1 SATA_DTX_PRX_P0 5
13 SATA_DTX_C_PRX_P0 2 0.01U_0402_16V7K 6 6
7 +3VS
7
+3VS 8 8
9 9

1
10 C2464
10
11 11
+5VS R2432 12 0.1U_0402_16V4Z

2
0_0805_5% 12
13 13
1 2 +5VS_HDD1 14 14
15 15
16 16
17 17
18 18
19 +5VS_HDD1
19
20 20
C C
21 G1 100mils
22 G2
23 G3

10U_0805_10V4Z
C2465

1U_0402_6.3V6K
C2466

0.1U_0402_16V4Z
C2467

1000P_0402_50V7K
C2468
24 G4

1
ACES_50406-02071-001

2
SP010016L00

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/08/10 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 38 of 57
5 4 3 2 1
 A B C D E

For Wireless LAN +3VS_WLAN +1.5VS +3VS_WLAN

Mini Card Power Rating
Power Primary Power (mA) Auxiliary Power (mA)

1
C2475 C2476 C2477 C2478 C2479 C2480 Peak Normal Normal
+3VS R2440 +3VS_WLAN 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0_1206_5% 60mil +3VS 1000 750

2
2 1
+3V 330 250 250 (wake enable)
+1.5VS 500 375 5 (Not wake enable)
+3VS_WLAN
No14
@ R2442 +1.5VS +3VS_WLAN
0_0402_5% JWLAN1 CONN@
1 1
15,44,46 PCH_PCIE_WAKE# 1 2 1 1 2 2
(WLAN_BT_DATA) 3
(WLAN_BT_CLK) 3 4 4
5 5 6 6
14 MINI1_CLKREQ# 7 7 8 8
9 9 10 10
14 CLK_PCIE_MINI1# 11 11 12 12
14 CLK_PCIE_MINI1 13 13 14 14
15 15 16 16
17 17 18 18
19 WL_OFF#
19 20 20 PLT_RST_BUF#
WL_OFF# 18
21 21 22 22 PLT_RST_BUF# 17
23 R2443 1 2 0_0603_5%
14 PCIE_PRX_DTX_N2 23 24 24 +3VS
14 PCIE_PRX_DTX_P2 25 25 26 26
27 27 28 28
29 MINI1_SMBCLK R2444 1 @ 2 0_0402_5%
29 30 30 MINI1_SMBDATA R2445 1 @
PCH_SMBCLK 14
14 PCIE_PTX_C_DRX_N2 31 31 32 32 2 0_0402_5% PCH_SMBDATA 14
14 PCIE_PTX_C_DRX_P2 33 33 34 34
35 35 36 36 USB20_N8 17
37 37 38 38 USB20_P8 17
39 39 40 40
41 R2447 1 2 0_0402_5%
41 42 42
43 43 44 44 MINI1_LED# 41
R2448 45
0_0402_5% 45 46 46
47 47 48 48 (9~16mA)

1
41 E51TXD_P80DATA 1 2 E51TXD_P80DATA1_R 49 49 50 50
41 E51RXD_P80CLK 1 2 E51RXD_P80CLK_R 51 51 52 52
R2449
R2635 100K_0402_5%
1

0_0402_5% 53 54
GND1 GND2

2
R2450 FOX_AS0B221-S40N-7H
100K_0402_5%
2 1
SP07000MG00 +3VS_WLAN
2

R2636
1K_0402_5%
4 mm High
+3VS_WWAN
+3VS U2420 3G@
Peak: 3A
2 2
@ WLAN&BT Combo module circuits DMN3030LSS-13_SOP8L-8 120mil
D2432 8 1
41,45,52,53 SUSP# 1 2 BT_CTRL BT BT 7 2

@ C2734
on module on module 1 6 3 1 1

1
10U_0603_6.3V6M
C2735

0.1U_0402_16V4Z
C2736

10U_0603_6.3V6M
C2737

1U_0402_6.3V6K
C2738

150U_B2_6.3VM_R35M
RB751V-40_SOD323-2 5 +
1

D
Enable Disable
BT_ON# 2 Q2436
18,40 BT_ON#

2
G 2N7002H_SOT23-3 2 2 2

3G@

3G@

3G@

3G@
S BT_CTRL H L
3

BT_ON#
L H 20mil
+VSB
20mil R2630 3G@ 20mil
47K_0402_5%
2 1 3VS_WWAN_GATE

1
D C2739

WWAN R2453 1 3G@

L2406
2 0_0402_5%

@
41 EC_SIM_DETECT# EC_SIM_DETECT# 2
G
S
Q2437 0.1U_0603_25V7K
2N7002H_SOT23-3 3G@
3G@ 2

3
USB20_N12 4 3 USB20_N12_R
17 USB20_N12

R2456 1 3G@ 2 0_0402_5% USB20_P12 1 2 USB20_P12_R

17 USB20_P12
L2407 @ OCE2012120YZF_4P
USB20_N9 4 3 USB20_N9_R
17 USB20_N9
1 3G@ 2

3
R2452 0_0402_5%
USB20_P9 1 2 USB20_P9_R
17 USB20_P9
D2409 3G@
OCE2012120YZF_4P UIM_VPP 1 4 UIM_RST

3
1 3G@ 2 D2433 3G@
3
R2454 0_0402_5% PJDLC05C_SOT23-3
2 5 +UIM_PWR

1
UIM_DATA 3 6 UIM_CLK

CM1293A-04SO_SOT23-6~D
check power well
+3VS

+3VS_WWAN +3VS_WWAN +UIM_PWR

1

JWWAN1 CONN@ R2401

1 10K_0402_5% JSIM1 CONN@ 40mil
1 2 2 3G@
3 3 4 4 4 GND VCC 1
5 UIM_VPP UIM_RST
6 6 5 2
2

5 +UIM_PWR UIM_DATA VPP RST UIM_CLK

7 7 8 8 6 I/O CLK 3
9 UIM_DATA UIM_DET_R
9 10 10 UIM_CLK
41 UIM_DET_EC 1 2 7 DET

22P_0402_50V8J

22P_0402_50V8J
11 0_0402_5%
11 12 12

3G@

3G@
13 UIM_RST R2537 USB20_P12_R
13 14 14 8 D+ 1 1

3G@

56P_0402_50V8
R2451 3G@ 2 0_0402_5% UIM_VPP 3G@ USB20_N12_R

.1U_0402_16V7K
0.1U_0402_16V4Z
15 15 16 16 1 9 D-

C2497 3G@

3G@
17 17 18 18 GND 10 1 1 1
M_WXMIT_OFF#
22P_0402_50V8J

19 19 20 20 1 GND 11
2 2
C2494 3G@

C2495

C2740
21 21 22 22

C2496
23 23 24 24 2 2 2

C2741
25 WWAN_DET# 1 R2405 2 3G@ 0_0402_5%
25 26 26 WWAN_DET#_EC 41 2
27 27 28 28
29 29 30 30
31 TAITW_PMPAT7-08GLBS1N14H0
31 32 32
33 33 34 34
35
37
35 36 36
USB20_N9_R
USB20_P9_R SP07000NX00
37 38 38
39 39 40 40
41 WWAN_LED#
41 42 42 WWAN_LED# 41
4 43 43 44 44
4
45 R2625 1 100K_0402_5% +3VALW
45 46 46 2
47 47 48 48
49 49 50 50
51 51 52 52
Place as close as JSIM1
53 GND1 GND2 54

FOX_AS0B221-S40N-7H DET signal, normal Close, connect to GND.
Security Classification Compal Secret Data Compal Electronics, Inc.
SP07000MG00 Issued Date 2008/08/10 2010/12/31 Title
D2429 3G@ Deciphered Date
4 mm High 1 2 M_WXMIT_OFF# SCHEMATIC,MB LA-A7121
18 WWAN_OFF# THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
RB751V-40_SOD323-2 C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 39 of 57
A B C D E
 A B C D E

No 41, for measurement

+ODR_PWR

+3VS +3VS_CARD
Card Reader 1 2
R1313 0_0805_5%

0.1U_0402_10V7K
C1301

10U_0603_6.3V6M
C1302

0.1U_0402_10V7K
C1303

0.1U_0402_10V7K
C1304
@
40 mils 40 mils

1
100K_0402_5%
R1301
1 1 1 1

1 2 2 2 2 1

2
Close to connector
U1300 +3VS_CARD
10 mils
14 PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_p3 1 48 RREF R1300 2 1 6.2K_0603_1%
HSIP RREF
PCIE_PTX_C_DRX_N3 2 47
40 mils 2 1
14 PCIE_PTX_C_DRX_N3 HSIN 3V3_IN C1305 0.1U_0402_10V7K
14 CLK_PCIE_CARD CLK_PCIE_CARD 3 46 CARD_CLKREQ#
REFCLKP CLK_REQ# CARD_CLKREQ# 14

14 CLK_PCIE_CARD# CLK_PCIE_CARD# 4 45 PLT_RST#

REFCLKN PERST# PLT_RST# 5,17,41,44,46
C1300 1 2 4.7U_0603_6.3V6K
20 mils AV12 5 44
AV12 EEDO
PCIE_PRX_DTX_P3 1 2 PCIE_PRX_C_DTX_P3 6 43
14 PCIE_PRX_DTX_P3 HSOP EECS
C1306 0.1U_0402_10V7K
PCIE_PRX_DTX_N3 1 2 PCIE_PRX_C_DTX_N3 7 42
14 PCIE_PRX_DTX_N3 HSON EESK
C1307 0.1U_0402_10V7K
8 GND GPIO/EEDI 41 5IN1_LED# 42
+ODR_PWR
20
1
mils
2 DV12 9 40 MS_INS#
DV12 MS_INS#
2 40 mils C1308 0.1U_0402_10V7K 10 39 SD_CD# 2
+3VS_CARD Card1_3V3 SD_CD#
40 mils 11 38 SP15_SDWP_XDD7
3V3_IN SP15
10U_0603_6.3V6M
C1309

0.1U_0402_10V7K
C1310

1 1 12 37 SP14_MSCLK_XDD6 1 2 SP14_MSCLK_XDD6_R
Card2_3V3 SP14 R1302 0_0402_5% 2
XD_CD# 13 36 SP13_MSD7_XDD5
XD_CD# SP13 C1311
2 2 20 mils DV33_18 14 35 SP12_MSD3_XDD4 5PF_0402_50V8
DV33_18 SP12 1
4.7U_0603_6.3V6K

0.1U_0402_10V7K

@
@ C1312

1 1 15 34 SP11_MSD6_XDD3 vendor suggest

GND SP11
C1313

SP1_SDD7_XDRDY 16
SP1 SP10 33 SP10_MSD2_XDD2 for EMI
BT Conn.
2 2 SP2_SDD6_XDRE# SP9_MSD0_XDD1 +BT_VCC
17 SP2 SP9 32
(Port 13)
SP3_SDD5_XDCE# 18 31 SP8_MSD4_XDD0 JBT1 CONN@
SP3 SP8
8 G2 6 6
SP4_SDD4_XDWE# 19 30 SP7_MSD1_XDWP# 7
SP4 SP7 G1 5 5
SD_D1_R SD_D1 SP6_MSD5_XDALE 4 4 USB20_P13 17
1 2 20 SD_D1 SP6 29 3 3 USB20_N13 17
R1303 0_0402_5% 1 2
C1315 @ SD_D0_R SD_D0 SP5_MSBS_XDCLE C1314 4.7U_0603_6.3V6K 2 2
5PF_0402_50V8
1
R1304
2
0_0402_5%
21 SD_D0 SP5 28 20 mils 1 1
1 2 SD_CLK_R 1 2 SD_CLK 22 27 DV12_S 1 2 ACES_87213-0600G
R1305 33_0402_1% SD_CLK DV12_S C1316 0.1U_0402_10V7K
vendor suggest SD_CMD_R 1 2 SD_CMD 23 26
BT Wire Cable Note:
SD_CMD GND
for EMI SD_D3_R
R1306 0_0402_5%
SD_D3 SD_D2 SD_D2_R
Pin 3, Pin 4 NC
1 2 24 SD_D3 SD_D2 25 1 2
R1307 0_0402_5% R1308 0_0402_5%

3
RTS5209-GR_LQFP48_7X7
SP02000FR00 3

+3VALW +3VS
+ODR_PWR +ODR_PWR
Reserve for EMI please close to JREAD1 No46
JREAD1 CONN@ BT@

1
39 11 C1317 C1318
XD-VCC SD4-VDD 0.1U_0402_16V4Z BT@
MS9-VCC 18
SP8_MSD4_XDD0 31 @ @ 1U_0603_10V4Z

2
XD10-D0

3
SP9_MSD0_XDD1 32 8 SD_CLK_R 1 2 2 1 S
SP10_MSD2_XDD2 XD11-D1 SD5-CLK SD_D0_R BT_ON# 1 BT@ Q1300
33 XD12-D2 SD7-DAT0 4 18,39 BT_ON# 2 2
SP11_MSD6_XDD3 34 3 SD_D1_R R1309 C1319 R1310 10K_0402_5% G BT@
SP12_MSD3_XDD4 XD13-D3 SD8-DAT1 SD_D2_R 33_0402_5% 22P_0402_50V8J D AO3413L_SOT23-3
35 21

1
SP13_MSD7_XDD5 XD14-D4 SD9-DAT2 SD_D3_R
36 XD15-D5 SD1-DAT3 19

2
SP14_MSCLK_XDD6 37 16 SD_CMD_R C1320 W=40mils
SP15_SDWP_XDD7 XD16-D6 SD2-CMD SD_CD# BT@
38 XD17-D7 SD-CD 1 +BT_VCC
2 SP15_SDWP_XDD7 0.1U_0402_16V4Z

1
SD-WP

1
SP4_SDD4_XDWE# 28 BT@ BT@
XD07-WE

1
4.7U_0805_10V4Z
C1321

0.1U_0402_16V4Z
C1322
SP7_MSD1_XDWP# 29 6 Reserve for EMI R1311
SP6_MSD5_XDALE XD08-WP SD6-VSS 300_0603_5%
27 XD06-ALE SD3-VSS 13 please close to JREAD1
XD_CD# 22 BT@

2
SP1_SDD7_XDRDY XD01-CD
23

2
SP2_SDD6_XDRE# XD02-R/B @ @
24 XD03-RE
SP3_SDD5_XDCE# 25 17 SP14_MSCLK_XDD6_R 1 2 1 2
SP5_MSBS_XDCLE XD04-CE MS8-SCLK SP9_MSD0_XDD1
26 XD05-CLE MS4-DATA0 10

1
SP7_MSD1_XDWP# R1312 C1323 D
MS3-DATA1 9
30 12 SP10_MSD2_XDD2 33_0402_5% 22P_0402_50V8J 2 Q1301
XD GND MS5-DATA2 SP12_MSD3_XDD4 G 2N7002H_SOT23-3
40 XD GND MS7-DATA3 15
4 MS_INS# BT@ 4
14 S

3
MS6-INS SP5_MSBS_XDCLE
MS2-BS 7
MS1-VSS 5
41 SD CD/WP GND MS10-VSS 20
42 SD CD/WP GND
TAITW_R013-P17-HM_NR
Security Classification Compal Secret Data Compal Electronics, Inc.
DC021010041 10/5 Issued Date 2008/08/10 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 40 of 57
A B C D E
 5 4 3 2 1

+3VALW_EC
No5
+3VLP EC_PME# R2235 1 2 10K_0402_5%
R2233
0_0805_5% LID_SW# R2202 2 1 100K_0402_5%
1 @ 2

+5VS
R2200 +3VALW_EC L2200
+3VALW 0_0805_5% FBMA-L11-160808-800LMT_0603 TP_CLK R2203 1 2 4.7K_0402_5%
1 2 +3VALW_EC 1 2 +EC_VCCA
TP_DATA R2204 1 2 4.7K_0402_5%

0.1U_0402_16V4Z
C2201

0.1U_0402_16V4Z
C2202

0.1U_0402_16V4Z
C2203

0.1U_0402_16V4Z
C2204

1000P_0402_50V7K
C2205

1000P_0402_50V7K
C2206
1

1
C2207 +3VS
D 0.1U_0402_16V4Z D

ECAGND2
@ C2200 @ R2205 EC_MUTE# R2201 2 @ 1 10K_0402_5%
22P_0402_50V8J 33_0402_5%
2 1 2 1 CLK_PCI_LPC BKOFF# R2206 1 2 10K_0402_5%

111
125
22
33
96

67
U2200

9
+3VALW_EC

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
R2207 2 1 200K_0402_5%
+3VALW_EC R2208 2 1 47K_0402_5% EC_RST#
GATEA20 1 21 3G_LED# D2200
18 GATEA20 GATEA20/GPIO00 PWM0/GPIO0F 3G_LED# 42
C2208 2 1 0.1U_0402_16V4Z EC_KBRST# 2 23 BEEP# 2 1 ACIN 15,45,48
18 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM1/GPIO10 BEEP# 46
SERIRQ 3 PWM Output 26 FAN_PWM
13 SERIRQ SERIRQ# FANPWM0/GPIO12 FAN_PWM 46
LPC_FRAME# 4 27 ACOFF RB751V-40_SOD323-2
13 LPC_FRAME# LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 ACOFF 47
LPC_AD3 5 EC_ACIN C2209 2 1 100P_0402_50V8J
13 LPC_AD3 LPC_AD3/LAD3
LPC_AD2 7 C2210 2 1 100P_0402_50V8J ECAGND
+3VALW_EC 13 LPC_AD2 LPC_AD2/LAD2
LPC_AD1 8 63 BATT_TEMP
13 LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 BATT_TEMP 50
10/1 ENE Recommand LPC_AD0 10 64
13 LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39
LPC & MISC 65 ADP_I
ADP_I/AD2/GPI3A ADP_I 48,50
R2209 1 2 47K_0402_5% KSO1 CLK_PCI_LPC 12 66 AD_BID0
17 CLK_PCI_LPC CLK_PCI_EC/PCICLK AD3/GPI3B
PLT_RST# 13 AD Input 75 AD_PID0
5,17,40,44,46 PLT_RST# PCIRST#/GPIO05 AD4/GPI42
R2210 1 2 47K_0402_5% KSO2 EC_RST# 37 76 @T2202 PAD
EC_SCI# EC_RST#/ECRST# AD5/GPI43
18 EC_SCI#
PWR_SUSP_LED
20 EC_SCI#/GPIO0E power said: IMVP_IMON no need +3VS
42 PWR_SUSP_LED 38 CLKRUN#/GPIO1D
R2212 1 2 10K_0402_5% EC_SMI# 68 DAC_BRIG
DAC_BRIG/DA0/GPO3C DAC_BRIG 34
70 EC_SIM_DETECT#
EN_DFAN1/DA1/GPO3D EC_SIM_DETECT# 39
R2213 1 2 2.2K_0402_5% EC_SMB_DA1 DA Output 71 @ T2203 PAD 1 2
IREF/DA2/GPO3E

5
KSI0 55 72 @ T2204 PAD U2201 C2211 0.1U_0402_16V4Z
KSI1 KSI0/GPIO30 DA3/GPO3F
56

P
R2214 EC_SMB_CK1 KSI2 KSI1/GPIO31 H_PROCHOT#_EC
1 2 2.2K_0402_5% 57 KSI2/GPIO32 2 A Y 4

1
KSI3 EC_MUTE#

NC
58 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 83 EC_MUTE# 46

G
C KSI4 GFX_CORE_PWRGD R2215 C
59 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 84 GFX_CORE_PWRGD 54
@ C2212 @ R2216 KSI5 60 85 WWAN_LED# WWAN_LED# 39 100K_0402_5% SN74LVC1G06DCKR_SC70-5

1
22P_0402_50V8J 33_0402_5% KSI6 KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C H_PROCHOT#_EC
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
2 1 1 2 KSI7 62 87 TP_CLK
TP_CLK 42

2
KSI[0..7] KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA R2217
42,46 KSI[0..7] 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 42
KSO1 40 0_0402_5%
KSO[0..17] KSO2 KSO1/GPIO21 VR_HOT#
Reserve for EMI please close to U44 42,46 KSO[0..17] 41 54 VR_HOT# 2 1 H_PROCHOT# 5,50
KSO3 KSO2/GPIO22
42 KSO3/GPIO23 SDICS#/GPXIOA00 97 @T2210 PAD
KSO4 43 98 65W/90W#
+3VS KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 65W/90W# 50
KSO5 HDA_SDO
KSO6
44 KSO5/GPIO25 Int. K/B ME_EN/SDIMOSI/GPXIOA02 99
LID_SW#
HDA_SDO 13
R2218
45 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 109 LID_SW# 43 Latest design guide suggest change UE4 to 74LVC1G06.
1 2 2.2K_0402_5% EC_SMB_CK2 KSO7 46 KSO7/GPIO27 SPI Device I/F
KSO8 47 KSO8/GPIO28
R2219 1 2 2.2K_0402_5% EC_SMB_DA2 KSO9 48 KSO9/GPIO29 SPIDI/MISO 119 FRD#_R R2220 1 2 0_0402_5% FRD#
KSO10 49 120 FWR#_R R2221 1 2 33_0402_5% FWR#
KSO11 KSO10/GPIO2A SPIDO/MOSI SPI_CLK_R R2222 33_0402_5% SPI_CLK
50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 1 2
R2223 1 2 10K_0402_5% EC_SCI# KSO12 51 128 FSEL#_R R2224 1 2 33_0402_5% FSEL#
KSO13 KSO12/GPIO2C SPICS#
52 KSO13/GPIO2D
KSO14 53
KSO15 KSO14/GPIO2E
54 KSO15/GPIO2F GPIO40 73 UIM_DET_EC 39
KSO16 81 74 EC_PECI R2225 1 2 43_0402_1%
KSO16/GPIO48 H_PECI/GPIO41 H_PECI 5,18
KSO17 82 GPIO 89 USB_CHARGE_CB Colay until C test
KSO17/GPIO49 FSTCHG/GPIO50 USB_CHARGE_CB 43
90 BATT_AMB_LED#
BATT_CHG_LED#/GPIO52 BATT_AMB_LED# 42
91 CAPS_LED#
48,50 EC_SMB_CK1
EC_SMB_CK1 77 EC_SMB_CK1/SCL0/GPIO44
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54 92 BATT_BLUE_LED#
CAPS_LED# 46
BATT_BLUE_LED# 42 +3VALW_EC
SPI ROM 128KB
EC_SMB_DA1 78 93 PWR_LED
48,50 EC_SMB_DA1 EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55 PWR_LED 42
EC_SMB_CK2 79 95 SYSON U2202
14,22 EC_SMB_CK2 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 SYSON 44,45,51 20mils
EC_SMB_DA2 80 121 VR_ON 8 4
14,22 EC_SMB_DA2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 54 VCC VSS
127 EC_ACIN
AC_IN/GPIO59

1
SM Bus C2213 3
0.1U_0402_16V4Z W
PM_SLP_S3# 6 100 PCH_RSMRST# 7
15 PM_SLP_S3# PCH_RSMRST# 15

2
B PM_SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 LID_SW_OUT# HOLD B
15 PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 101 LID_SW_OUT# 14
EC_SMI# 15 102 EC_ON FSEL# 1
18 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXIOA05 EC_ON 43 S
EC_XCLK1 EC_XCLK0 39 WWAN_DET#_EC 16 103 EC_PME#
GPIO0A EC_SWI#/GPXIOA06 EC_PME# 46
MINI1_LED# 17 104 PCH_PWROK SPI_CLK 6
39 MINI1_LED# GPIO0B ICH_PWROK/GPXIOA07 PCH_PWROK 15 C
USB_CHARGE_2A# 18 GPIO 105 BKOFF#
43 USB_CHARGE_2A# GPIO0C BKOFF#/GPXIOA08 BKOFF# 34
1

C2214 C2215 T2211 PAD @ 19 GPO RF_OFF#/GPXIOA09 106 PWR_SAVE_LED# FWR# 5 2 FRD#
SUS_PWR_DN_ACK/GPIO0D PWR_SAVE_LED# 46 D Q
1

USB_CHARGE_100mA 25 107 WLAN_LED#

43 USB_CHARGE_100mA INVT_PWM/PWM2/GPIO11 GPXIOA10 WLAN_LED# 42
15P_0402_50V8J 15P_0402_50V8J FAN_SPEED1 28 108 BATT_RED_LED# MX25L2005M2C-12G SOP 8P
OSC

OSC

BATT_RED_LED# 42
2

46 FAN_SPEED1 PCH_PWR_EN FAN_SPEED1/FANFB0/GPIO14 GPXIOA11

45 PCH_PWR_EN 29 FANFB1/GPIO15
E51TXD_P80DATA 30 SA00002C100 (S IC FL 1MB MX25L1005AMC-12G SOP 8P 3.3V)
39 E51TXD_P80DATA EC_TX/GPIO16
E51RXD_P80CLK 31 110 PM_SLP_S4#
39 E51RXD_P80CLK EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 PM_SLP_S4# 15
ON/OFF ENBKL
NC

NC

43 ON/OFF 32 ON_OFF/GPIO18 ENBKL/GPXIOD02 112 ENBKL 16 No10

T2217 PAD @ 34 114 EAPD
SUSP_LED#/GPIO19 EAPD/GPXIOD03 EAPD 46
NUM_LED# 36 GPI EC_THERM#/GPXIOD04 115 SA_PGOOD SA_PGOOD 52
46 NUM_LED#
2

NUM_LED#/GPIO1A SUSP# @ R2227 @ C2216

SUSP#/GPXIOD05 116 SUSP# 39,45,52,53
X2200 117 PBTN_OUT# 22_0402_5% 100P_0402_50V8J
PBTN_OUT#/GPXIOD06 PBTN_OUT# 15
32.768KHZ_12.5PF_Q13MC14610002 118 NV_PERFORMANCE SPI_CLK 2 1 1 2
EC_PME#/GPXIOD07 NV_PERFORMANCE 22
EC_XCLK1 122
@ EC_XCLK0 XCLK1 +V18R
15 SUSCLK_R 1 2 123 XCLK0 V18R 124
R2228 0_0402_5% Reserve for EMI please close to U2202

1
AGND

C2217
GND
GND
GND
GND
GND

1 @ 2
R2234 100K_0402_5% 4.7U_0805_10V4Z

2
KB930QF-A1_LQFP128_14X14
11
24
35
94
113

69

20mil
L2201 No9
ECAGND 2 1
Board ID Project ID FBMA-L11-160808-800LMT_0603
+3VALW_EC
Analog Board ID definition, +3VALW_EC Analog Board ID definition
Please see page 3.
2

A R2229 A

Ra 100K_0402_5% R2231
Ra 100K_0402_5%
No32
wait for EC define R value
1

AD_BID0
1

AD_PID0
1

8.2K_0402_5%
R2230

0_0402_5%

C2218
Security Classification Compal Secret Data Compal Electronics, Inc.
R2232

Rb 0.1U_0402_16V4Z C2219
Rb 0.1U_0402_16V4Z 2009/12/01 2010/12/31 Title
Issued Date Deciphered Date
2

SCHEMATIC,MB LA-A7121
2

2
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 41 of 57
5 4 3 2 1
 1 2 3 4 5 6 7 8

To TP/B Conn. +5VS

1
No11 C2498
+5VS 0.1U_0402_16V4Z

2
Follow JM50 JTP1 CONN@
1 1
2 2 TP_CLK 41
3 3 TP_DATA 41
KSI[0..7] 4 LEFT_BTN#
KSI[0..7] 41,46 4

1
A RIGHT_BTN# @ @ A
5 5

100P_0402_50V8J
C2500

100P_0402_50V8J
C2501
JKB1 CONN@ KSO[0..17]
(Left) KSO[0..17] 41,46 6 6
7

2
KSO0 KSO16 C2499 1 100P_0402_50V8J GND
1 1 2 8 GND
KSO1 2
KSO2 2 KSO17 C2502 1 100P_0402_50V8J ACES_85201-0605N
3 3 2
KSO3 4 KSO7 C2503 1 2 100P_0402_50V8J
KSO4 4 KSO15 C2504 1 100P_0402_50V8J
5 5 2
KSO5 KSO6 C2505 1 100P_0402_50V8J
KSO6
6
7
6 2
KSO14 C2506 1 2 100P_0402_50V8J
SP01000LB00
KSO7 7 KSO5 C2507 1 100P_0402_50V8J
8 8 2
KSO8 9 KSO13 C2508 1 2 100P_0402_50V8J
KSO9 9 KSO4 C2509 1 100P_0402_50V8J
10 10 2
KSO10 11 KSO12 C2510 1 2 100P_0402_50V8J
KSO11 11 TP_CLK LEFT_BTN#
12 12
KSO12 13 KSO3 C2511 1 2 100P_0402_50V8J
KSO13 13 KSI0 C2512 1 100P_0402_50V8J TP_DATA RIGHT_BTN#
14 14 2
KSO14 15 KSI4 C2513 1 2 100P_0402_50V8J
15

2
KSO15 16 KSO11 C2514 1 2 100P_0402_50V8J
KSO16 16 KSO2 C2515 1 100P_0402_50V8J D2410 D2411
17 17 2
KSO17 18 KSO10 C2516 1 2 100P_0402_50V8J PJSOT05C_SOT23-3 PJSOT05C_SOT23-3
KSI0 18 KSO1 C2517 1 100P_0402_50V8J
19 19 2
KSI1 20 KSI1 C2518 1 2 100P_0402_50V8J
KSI2 20
21

1
KSI3 21 KSO0 C2519 1 100P_0402_50V8J
22 22 2
KSI4 23 KSI2 C2520 1 2 100P_0402_50V8J ESD request
KSI5 23 KSI5 C2521 1 100P_0402_50V8J
24 24 2
KSI6 25 27 KSO9 C2522 1 2 100P_0402_50V8J
KSI7 25 G1 KSI6 C2523 1 100P_0402_50V8J
26 26 G2 28 2
KSI3 C2524 1 2 100P_0402_50V8J
KSI7 C2525 1 2 100P_0402_50V8J
ACES_85201-26051 KSO8 C2526 1 2 100P_0402_50V8J
B SW2400 SW2401 B
(Right) LEFT_BTN# RIGHT_BTN#
10/04 Check footprint ok 3 1 3 1

SP01000GE00 4 2 4 2

5
6

5
6
EVQPLHA15_4P EVQPLHA15_4P

Should Check LED, not the correct P/N

LED
3G/Wireless LED Battery Reserved PWR_SUSP_LED#
Top View LED with Blue/Amber/Red Color

6
+3VS Q2432A
R2459 LED1 41 PWR_SUSP_LED 2 2N7002KDWH_SOT363-6
2.2K_0402_5% pin1,2 LED1 short wave length, BLU

2
1 2 2 1 3G_LED# +3VALW
3G_LED# 41 pin3,4 LED2 long wave length, AMB

1
R2460 B R2541 LED3 R2546
3.9K_0402_5% 2.2K_0402_5% 100K_0402_5%
1 2 4 3 WLAN_LED# 1 2 2 1 BATT_BLUE_LED# BATT_BLUE_LED# 41
C A WLAN_LED# 41 B C
R2542

1
3.9K_0402_5%
HT-297UD5-CB5_AMBER-BLUE 1 2 4 3 BATT_AMB_LED# BATT_AMB_LED# 41
A

HT-297UD5-CB5_AMBER-BLUE PWR_LED#

3
R2543 LED4
3.9K_0402_5% Q2432B
1 2 2 1 BATT_RED_LED# BATT_RED_LED# 41 41 PWR_LED 5 2N7002KDWH_SOT363-6
R

4
HT-191USD5_RED R2547
100K_0402_5%
Power

1
46 PWR_LED#

+3VALW R2462 LED2

HDD +3VS +3VS

2.2K_0402_5%
10/2
2
1 2 2 1 PWR_LED#
R2463 B @
3.9K_0402_5% +3VS R2403
5

1 2 4 3 PWR_SUSP_LED# U2401 10K_0402_5%

A LED5
VCC

IN1 1 5IN1_LED# 40
HT-297UD5-CB5_AMBER-BLUE 1 2 2 1MEDIA_LED#4 OUT
R2540 100_0402_1% B 2
GND

IN2 PCH_SATALED# 13

1 HT-191NB5_BLUE
D C2402 MC74VHC1G08DFT2G_SC70-5 D
3

0.1U_0402_16V4Z
@
2

Power/SUS Battery 3G/WLAN BlueTooth ACIN

LED Status
ON SUS Full Charge 3G WLAN Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/08/10 Deciphered Date 2010/12/31 Title
NEW70/80/90 Blue Amber Blue Amber Blue Amber SCHEMATIC,MB LA-A7121
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 42 of 57
1 2 3 4 5 6 7 8
 A B C D E

No16
D2402 +USB3_VCCA
U2DP1 6 1 U2DN1
USB Host Charger +USB3_VCCA 5
I/O4

REF2 REF1
I/O1
2

150U_B2_6.3VM_R35M

10U_0805_6.3V6M
1
R2536 4 3
I/O3 I/O2

C2597
10K_0402_5% U2414 +

C2595
41 USB_CHARGE_CB 1 2 8 1 PJUSB208H_SOT23-6
U2DN1_L CB CEN SW_U2DN1_L
44 U2DN1_L 7 2

1
U2DP1_L TDM DM SW_U2DP1_L Oper Drain, Low Active, need PU
44 U2DP1_L 6 TDP DP 3
5 VCC GND 4
+USB3_VCCA R2626 1 2 0_0402_5% 9
GND
1
1 R2627 1 @ 1
VL 2 0_0402_5% C2609 MAX14566EETA+_TDFN-EP8_2X2
0.1U_0402_16V4Z
L2404
2 SW_U2DN1_L U2DN1
3 4

SW_U2DP1_L
3 4

U2DP1
USB3.0 Connector
2 2 1 1
CB=0 Auto detection charger identification active U37 EN# active at S0, S5(AC) and S5(DC)
WCM-2012-670T_4P
CB=1 Connect DP/DM to TDP/TDM EN# USB_CHARGE_2A# PPON1
S0 ACTIVE LOW LOW +USB3_VCCA
S5(AC) ACTIVE LOW LOW
S5(DC) OFF HIGH LOW L2402 No18
U3TXDN1_L 2 1U3TXDN1
44 U3TXDN1_L
JUSB3
1 VBUS
U3TXDP1_L 3 4U3TXDP1 U2DN1 2
44 U3TXDP1_L D-
U2DP1 3 For customer request
+USB3_VCCA OCE2012120YZF_4P D+
4 GND
+5VALW U3RXDN1 5 GND_Frame 1 2
Stuff diodes to gate backflow from EC or PPON1. L2403 U3RXDP1 SSRX- R2522 0_0603_5%
6 SSRX+ GND 10
C2601 U2411 W=60mils U3RXDN1_L 2 1U3RXDN1 7 11 1 2
44 U3RXDN1_L GND GND
No4 .1U_0402_16V7K 1 8 U3TXDN1 8 12 R2524 0_0603_5%
GND VOUT R2514 U3TXDP1 SSTX- GND
1 2 2 VIN VOUT 7 9 SSTX+ GND 13 1 2
D2435 3 6 10K_0402_5% U3RXDP1_L 3 4U3RXDP1 C2602
VIN VOUT 44 U3RXDP1_L

EPAD
41 USB_CHARGE_2A# 2 1 R2530 1 2 4 5 1 2 OCTEK_USB-09EAEB .1U_0402_16V7K
EN FLG OCI1B 44
10K_0402_5% OCE2012120YZF_4P
1SS355_SOD323-2 10/5
1

AP2301MPG-13_MSOP8 DC233008O00

9
R2640 D2416
No36 10K_0402_5% U3RXDN1 1 1 109 U3RXDN1

2 U3RXDP1 U3RXDP1 2
AC Mode (Adapter In) 2 2 98
2

Signal Name S0 S3 S5 U3TXDN1 4 4 77 U3TXDN1

USB_CHARGE_CB 1 0 0
+USB3_VCCA USB_CHARGE_2A# 0 0 0 U3TXDP1 5 5 66 U3TXDP1
No43 VL 3 3
C2731 U2419 DC Mode (Battery >30%)
1U_0603_10V4Z 1 Signal Name S0 S3 S5 8
VOUT
2 1 5 VIN USB_CHARGE_CB 1 0 0
@ 2 YSCLAMP0524P_SLP2510P8-10-9
GND USB_CHARGE_2A# 0 0 0
41 USB_CHARGE_100MA R2618 1 2 4 3
10K_0402_5% ON OC
DC Mode (Battery <30%)
@ TPS22945DCKR_SC70-5 Signal Name S0 S3 S5
@
USB_CHARGE_CB 1 0 0
TPS22945 : SA000031000 USB_CHARGE_2A# 0 1 1

USB_CHARGE_CB Switch Control Bit, 0:Autio Detection, 1:Pass-through

USB_CHARGE_2A# Enable 2A USB Power Switch (Low active)

3 3

Power Button No17

Lid Switch
+3VALW +3VALW_EC

(Hall Effect Switch)

2

+3VALW
R2466 R2467
100K_0402_5% 100K_0402_5%
@
1

1
D2434
2 R2402 47K_0402_5%
ON/OFF 41
ON/OFFBTN# 1
46 ON/OFFBTN#
3 51ON# U2402
51ON# 47
D2401

2
BAV70W_SOT323-3 2 3 1 2 LID_SW#

GND
VDD VOUT LID_SW# 41
RB751V-40_SOD323-2
2 APX9131AAI-TRG_SOT23-3 1

1
1

D C2401 C2400
EC_ON 2 Q2404
41 EC_ON
G 2N7002H_SOT23-3 0.1U_0402_16V4Z 10P_0402_50V8J
2

S 1 2
3

R2470

10K_0402_5%
Anpec p/n:SA00003B900
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/08/10 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 43 of 57
A B C D E
 5 4 3 2 1

+3V_USB3 +1.05VR
+1.5V to +1.05V Transfer Close to U2410.D7 Close to U2410.P13
+5VALW +1.5V +5VALW +1.05V_USB3

C2572

C2573

C2574

C2575

C2576

C2577

C2578

C2579

C2580

C2581

C2582

C2583

C2584

C2585

C2586
U2408
+3VA_USB3 +3VA_USB3
1U_0603_10V6K

10U_0603_6.3V6M
+1.5V
C2570

C2571
6 VCNTL
1

1 5 VIN VOUT 3

1
9 VIN VOUT 4
+5VALW

.1U_0402_16V7K
C2587

0.01U_0402_16V7K
C2588

8P_0402_50V8D

.1U_0402_16V7K
C2590

0.01U_0402_16V7K
C2591

8P_0402_50V8D
@ @
2

1
C2589

C2592
SYSON 8

2
EN

10U_0603_6.3V6M
2 1 7 2 1 R2511 2

GND
POK FB

C2593

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

.1U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
R2510 5.1K_0402_1% 10K_0402_1%

2
1

1
Vout=0.8(1+10K/32.4K) APL5930KAI-TRG_SO8 R2512

1
32.4K_0402_1%
1.042 ~ 1.0469 ~ 1.0519V

2
Spec: 0.9975 ~ 1.05 ~ 1.1025

2
D D

7K for customer request, can use other kind

R2513 of capacitor, like Y5V.
0_0805_5%
+3VALW to +3V Transfer +3V_USB3
+1.05V_USB3 1 2 +1.05VR +3VA_USB3
+3V_USB3 +3VA_USB3
L2405
+3VALW U2409 +3V_USB3 BLM18AG601SN1D_2P
U2410 1 2
3 1

D10

H11
E11
E12

K11
K12

P13
F13
F14
VIN VOUT

L10

L13
L14

1
G3
G4

N4
N5
N6

C4
C5
C6
C7
D5

C8
C9
D8
D9

H3
H4

D7
SYSON C2594

P3

E3
E4
F3

L9

L5

L8
41,45,51 SYSON 4 VIN/CE VOUT 5
10U_0805_6.3V6M
2

VDD33
VDD33
VDD33

VDD33
VDD33
VDD33

VDD33
VDD33

VDD33
VDD33

VDD33
VDD33
VDD33
VDD33

VDD10
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10

VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

U3AVDO33

U2AVDD10

2
GND
RT9701-PB_SOT23-5

14 CLK_PCIE_USB30 B2 PECLKP
14 CLK_PCIE_USB30# B1 PECLKN
U3TXDP2 B6 Exchange port2 and port1 for vendor's suggestion,
C2598 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P4 D2
14 PCIE_PRX_DTX_P4 C2599 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_N4 D1
PETXP
A6 port2 may affect test issue.
14 PCIE_PRX_DTX_N4 PETXN U3TXDN2
U2DM2 N8
14 PCIE_PTX_C_DRX_P4 F2 PERXP
14 PCIE_PTX_C_DRX_N4 F1 PERXN U2DP2 P8
U3RXDP2 B8

A8 +3V_USB3
U3RXDN2
R2515 1 2 0_0402_5% H2
5,17,40,41,46 PLT_RST# PERSTB
15,39,46 PCH_PCIE_WAKE#
R2516 1 2 0_0402_5% K1 PEWAKEB OCI2B G14 OCI2B R2517 1 2 10K_0402_5%
CLKREQ_USB3 K2 Can be attach to EC, either. H13 OCI1B R2518 1 2 10K_0402_5%
R2519 1 PECREQB OCI1B
No3 +3V_USB3 2 10K_0402_1%
No21 @ R2520 1 2 100_0402_1% J2 AUXDET OCI1B 43
No29 +3V_USB3 R2521 1 2 10K_0402_5% J1 H14
SMI 0_0402_5% R2637 1 SMI_R PSEL PPON2
2 H1 SMI PCI Express/ExpressCard select signal PPON1 J14 No4
SMIB (P4) unused pin SMI# 0_0402_5% R2638 1 @ 2 SMIB_R P4
C 0_0402_5% R2639 1 @ 2
SMIB 1:others C
connected to GND. R2523 1 2 10K_0402_5% P5 0:Express Card or Mini card C2596 .1U_0402_16V7K
+3V_USB3 PONRSTB
D2417 B10 U3TX_C_DP11 2 U3TXDP1_L
U3TXDP1 U3TXDP1_L 43
1 2
SPI_CLK_USB M2 A10 U3TX_C_DN11 2 U3TXDN1_L
SPISCK U3TXDN1 U3TXDN1_L 43
1U_0603_10V6K

1SS355_SOD323-2 SPI_CS_USB# N2 N10 U2DN1_L C2600 .1U_0402_16V7K

+3V_USB3 SPISCB U2DM1 U2DN1_L 43
C2603

No36 USB_SO_SPI_SI N1 SPISI

1

USB_SI_SPI_SO M1 P10 U2DP1_L

SPISO U2DP1 U2DP1_L 43
B12 U3RXDP1_L
U3RXDP1 U3RXDP1_L 43
2

+3VS R2525 A12 U3RXDN1_L

U3RXDN1 U3RXDN1_L 43
10K_0402_5%
K13 GND
2
G

Q2427 K14 R2526

1

SSM3K7002FU_SC70-3 GND 1.6K_0402_1%

J13 GND
3 1 CLKREQ_USB3 As short as possible P12 1 2
14 USB30_CLKREQ# RREF
S

GND N12
C14 GND
GND N11 No23
No29
GND D6
R2538 USB3_XT1 N14
USB3_XT2 XT1
14 CLK_48M_USB3_PCH 2 1 M14 XT2

3
0_0402_5%
@
Q2419B
P6 SMI 5
CSEL

4
P14 2N7002KDWH_SOT363-6
GND
A1 GND GND P11
2

A2 GND GND P9
R2532

R2533

A3 GND GND P7
+3V_USB3
0_0402_5%

0_0402_5%

@ A4 P2
+3V_USB3 GND GND +3V_USB3
A5 GND GND P1
A7 N13
1

GND GND

2
+3V_USB3 +3V_USB3 A9 N9
GND GND R2643
A11 GND GND N7
2

B B
A13 N3 10K_0402_5%
GND GND @
A14 GND GND M13
2

2
10K_0402_5%
R2529

C2604 R2527 @ R2528 B3 M12

1
.1U_0402_16V7K 10K_0402_5% 47K_0402_5% +3V_USB3 GND GND
B4 GND GND M11
B5 M10 SMI# 1 6 SMIB 18
2

GND GND
B7 GND GND M9
U2412 B9 M8
1

SPI_CS_USB# GND GND Q2419A

8 VCC CS# 1 B11 GND GND M7
7 2 USB_SI_SPI_SO B13 M6 2N7002KDWH_SOT363-6
SPI_CLK_USB NC SO GND GND
6 SCLK WP# 3 B14 GND GND M5
USB_SO_SPI_SI 5 4 C1 M4
SI GND GND GND
C2 GND GND M3
MX25L5121EMC-20G_SO8 C3 L12
GND GND
C10 GND GND L11
C11 GND GND L7
GND L6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

USB3_XT1
USB3_XT2
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

UPD720200AF1-DAP-A_FBGA176
1

R2535
100_0402_5%
2

Y2400 Place as close as PCB footprint change: UPD720200F1-XXX-A_FBGA_176P-NH

1 2 possibile to
24MHZ_12PF_X5H024000DC1H U2410.N14 and U2410.M14 From JM50: P/N change to SA000048H10
1

C2607 C2608 10/29 From JM40: P/N change to SA000048H00

12P_0402_50V8J 12P_0402_50V8J
2

A A

Pin compare table for support USB remote wakeup or not

AUXDET(Pin J2) CSEL(Pin P6) CLK

Support USB pull high Tied to GND Must use 24MHz crystal: mount
Security Classification Compal Secret Data Compal Electronics, Inc.
remote 10k to Y1,R19,C40,C41 Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title
wakeup VDD33
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
Not support USB Tied to GND pull high Can use either 48MHz or 24MHz When AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
remote wakeup to use 48MHz clock: mount R22,R25 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
VDD33 Date: Tuesday, December 14, 2010 Sheet 44 of 57
5 4 3 2 1
 A B C D E

+5VALW
MOS needed!
+5VALW TO +5VS +3VALW TO +3VALW(PCH AUX Power)

2
+5VALW
+5VALW U2404 R2479
SI4178DY-T1-GE3_SO8 +5VS 100K_0402_5%
Short J5 for PCH VCCSUS3.3

2
8 1 R2480

1
7 2 +3VALW J2400 @ 100K_0402_5%

2
6 3 1 2 +3VALW_PCH SUSP
1 2 5,53 SUSP

1
10U_0805_10V4Z
C2538

1U_0603_10V4Z
C2539
5 R2481

1
1

1
10U_0805_10V4Z
C2540

10U_0805_10V4Z
C2541
470_0603_5% JUMP_43X79 SYSON#
37,46 SYSON#
U2405 40mil

2
SI4178DY-T1-GE3_SO8
2

6
3
8 1

6
No45 7 2 2N7002KDWH_SOT363-6

2
Q2407A 6 3 2
2N7002KDWH_SOT363-6 39,41,52,53 SUSP#

1
1 Q2406A 1

10U_0805_10V4Z
C2542

1U_0603_10V4Z
C2543
20mil 10mil 5 SYSON 5
41,44,51 SYSON

1
2 1 5VS_GATE 2 SUSP C2544 R2482 Q2406B
+VSB

1
1
R2485 470_0603_5% R2483

4
100K_0402_5% 10U_0805_10V4Z R2484 10K_0402_5%

6 1
3

1
C2545 2N7002KDWH_SOT363-6 100K_0402_5%
0.1U_0603_25V7K

2
Q2407B Q2408A

2
SUSP 5 20mil 10mil
2 PCH_PWR_EN# +5VALW
+VSB R2486 2 1 200K_0402_5% 3V_GATE
4

2N7002KDWH_SOT363-6

1
3

2
2N7002KDWH_SOT363-6

1
R2487
Q2408B C2546 100K_0402_5%
PCH_PWR_EN# 5 0.1U_0603_25V7K

1
4
2N7002KDWH_SOT363-6 PCH_PWR_EN#
20,46 PCH_PWR_EN#
+3VALW TO +3VS

1
D

41 PCH_PWR_EN 2 Q2409
+3VALW U2406 +3VS G 2N7002H_SOT23-3

1
SI4178DY-T1-GE3_SO8 S

3
8 1 R2488
7 2 100K_0402_5%

2
10U_0805_10V4Z
C2547

10U_0805_10V4Z
C2548

6 3

2
1

1
10U_0805_10V4Z
C2549

1U_0603_10V4Z
C2550
5 R2489
470_0603_5%
2

6 1
No45 10/5, follow JM50
R2490 10mil Q2410A
20mil 200K_0402_5%
2 1 3VS_GATE 2 SUSP +1.5V to +1.5VSDGPU for GPU
2
+VSB
+1.05VS_VCCP to +1.05VSDGPU for GPU +1.5V +VRAM_1.5VS
2
1
3

C2551 2N7002KDWH_SOT363-6 No39 Q2418

0.1U_0603_25V7K +1.05VS_VCCP AO4430L_SO8
Q2410B +1.05VS_DGPU 8 1
2

SUSP 5 Q2415 7 2

2
AO4430L_SO8 4A 6 3 OPT@ OPT@

10U_0805_10V4Z
C2567
8 1 5 R2504
4

1U_0603_10V4Z
C2566
2N7002KDWH_SOT363-6 7 2 OPT@ 470_0603_5%

2
1

2
OPT@ 6 3 OPT@ C2568 OPT@ OPT@

4
1
10U_0805_10V4Z
C2732
C2565 5 OPT@ R2498 10U_0805_10V4Z

1
1U_0603_10V4Z
C2563
10U_0805_10V4Z 470_0603_5%
+1.5V to +1.5VS

2
1211 EMI ADD 0.1U close PJ5 OPT@ OPT@

6
1
+1.5V +1.5VS
U2407 20mil 10mil

6
AO4430L_SO8 2 1 1.5VSDGPU_GATE 2 VGA_ON#
+VSB
8 1 20mil OPT@ R2497 10mil R2505
7 2 510K_0402_5% OPT@ 510K_0402_5% OPT@

1
1

1
10U_0805_10V4Z
C2555

10U_0805_10V4Z
C2556

0.1U_0402_16V4Z
C2557

0.1U_0402_16V4Z
C2558

10U_0805_10V4Z
C2553

1U_0603_10V4Z
C2554

510K_0402_5%
6 3 +VSB 2 1 1.05VSDGPU_GATE 2 VGA_ON# C2569 Q2423A

R2509
5 R2494 OPT@ 2N7002KDWH_SOT363-6
1

470_0603_5% OPT@ @ 0.1U_0603_25V7K

2

2
3

1
510K_0402_5%
@ C2733 Q2416A VGA_ON# 5
4

R2493
OPT@ 2N7002KDWH_SOT363-6 OPT@
2

2
0.1U_0603_25V7K Q2423B

4
VGA_ON# 5 2N7002KDWH_SOT363-6
6

No45 OPT@

2
Q2413A Q2416B

4
20mil 10mil 2N7002KDWH_SOT363-6
+VSB 2 1 1.5VS_GATE 2 SUSP

1
R2496 D
750K_0402_5% ACIN 2 Q2426
1
1

@ C2562 2N7002KDWH_SOT363-6 G 2N7002H_SOT23-3

3

1
D
510K_0402_5%
R2499

0.1U_0603_25V7K S @

3
ACIN 2 Q2434
2

Q2413B G 2N7002H_SOT23-3
SUSP 5 S @ +5VALW
2

3
3 3
4

2
2N7002KDWH_SOT363-6 OPT@
R2620
1

D 100K_0402_5%
15,41,48 ACIN ACIN 2 Q2417 2009/08/17 add VGA_ON#
G 2N7002H_SOT23-3

1
S @ VGA_ON#
3

1
+3VS D
2 Q2433
14,17,55 VGA_ON
G 2N7002H_SOT23-3

1
@ +3VSDGPU S OPT@

3
R2621 R2619
0_0805_5%

1
OPT@ 1 2 22K_0402_5%
C2552 OPT@

2
10U_0805_10V4Z 2
OPT@ Q2412
AO3413L_SOT23-3
+3VALW
100mil(1.5A)
3 1

D
1

2
OPT@ OPT@

1
R2624 OPT@ R2622

2
100K_0402_5% C2559 470_0603_5% +VGA_CORE

3VSdelay_gate
10U_0805_10V4Z
2

2
+0.75VS OPT@

2
+1.05VS_VCCP +1.8VS +1.5V 1 2
R2495 OPT@ R2507
1

6
1K_0402_5% 470_0805_5%
2

R2500 OPT@
22_0603_5% R2501 R2502 @ R2503 OPT@ Q2414A

1
3

470_0603_5% 470_0603_5% 470_0603_5% OPT@ C2561 2N7002KDWH_SOT363-6 23VSdelay_gate

R2623 OPT@ 0.1U_0603_25V7K
2

1K_0402_5% Q2414B
1 1

1 1

1 1

1
VGA_ON 2N7002KDWH_SOT363-6 D
4 1 2 5 4
1

D D D D VGA_ON# Q2425
2
1

2 SUSP 2 SUSP 2 SUSP 2 SYSON# G 2N7002H_SOT23-3

4

G 2N7002H_SOT23-3 G 2N7002H_SOT23-3 G 2N7002H_SOT23-3 G 2N7002H_SOT23-3 OPT@ S OPT@

3
S Q59 S Q60 S Q61 S Q62 C2560
3

@ 0.1U_0603_25V7K

2009/08/14
CP_S3PowerReduction
WhitePaper_Rev0.9
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/08/10 Deciphered Date 2010/12/31 Title
0.75VS speed up discharge
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 45 of 57
A B C D E
 A B C D E

+5VS
ZZZ1
C2403 L2408
For USB 20 small board

1
1 2 1 2 DMIC_CLK No36
@ BLM18PG300SN1D_2P D2427
1000P_0402_50V7K FAN1 Conn 1SS355_SOD323-2
USB2.0+Audio codec + Jack conn @
PCB-MB
@
@ D2428

2
C2404 L2409 +5VS R2476 BAS16_SOT23-3
+5VS No12 1 2 1 2 DMIC_DATA 0_0603_5% 1 2
JUSBF1 CONN@ @ BLM18PG300SN1D_2P 1 2 +VCC_FAN1
+3VS 1 1 1000P_0402_50V7K

2
2 2 @ C2723
3 3 C2722 10U_0805_10V4Z
41 BEEP# 4 4 10U_0805_10V4Z 1 2

1
5 5 No37 ESD request FM1 FM2 FM3 FM4
13 HDA_SPKR
6 6 No44 1 1 1 1 C2724
41 EC_MUTE#
7 7 1000P_0402_50V7K
1 13 HDA_RST#_AUDIO +3VS 1
8 8 1 2
13 HDA_SDIN0
13 HDA_SDOUT_AUDIO 9 9
13 HDA_SYNC_AUDIO 10 10

1
13 HDA_BITCLK_AUDIO 11 11
SPKL+ 12 12 R2477
SPKL-
SPKR+
13 13 Int. Speaker Conn. 10K_0402_5% No13
14 14 40mil
SPKR- 15 15 JFAN1 CONN@

2
16 16 1 Left Side +VCC_FAN1 1 1
+5VALW 17 17 1 C1137 @
41 FAN_SPEED1 2 2
18 18 1000P_0402_50V7K C1130 FAN_PWM 3
47P_0402_50V8J JSPK1 41 FAN_PWM 3
19 19 CONN@ 4
37,45 SYSON# 4

1
SPKL+ R1122 1 2 SPK_L+
17 USB_OC0# 20 20 2 0_0805_5% 1 1 C2725
SPKL- R1124 1 2 SPK_L-
17 USB20_N0 21 21 2 0_0805_5% 1 2 2 1000P_0402_50V7K 5 GND1
17 USB20_P0 22 22 1 6

2
C1134 @ GND2
23 23 20mil
24 24 1000P_0402_50V7K C1133 3 E&T_3806-F04N-02R
41 EAPD G1

3
2 47P_0402_50V8J4
25 25 G2
D1103 2
34 DMIC_DATA
26 26 SP02000H900
27 27 ACES_88266-02001
34 DMIC_CLK PJDLC05C_SOT23-3
28 28
29 GND1 D1103 & D1104 please close to SP020008Y00
30 GND2 JSPK1 & JSPK2 ,respectively
ACES_85201-2805
SP01000GO00 1 Right Side

1
1 @
C1131
C1138 47P_0402_50V8J JSPK2 CONN@ 2P8 * 11
SPKR+ R1130 1 1000P_0402_50V7K 2 SPK_R+
2 0_0805_5% 1 1
SPKR- R1131 1 2 SPK_R-
2 0_0805_5% 1 2 2
1 H2400 H2401 H2402 H2403 H2404 H2405 H2406 H2407 H2408 H2409 H2410
For LAN small board

3
20mil C1141 @
1000P_0402_50V7K C1132 3
2 47P_0402_50V8J4 G1

LAN conn D1104 2 G2 @ @ @ @ @ @ @ @ @ @ @

1
ACES_88266-02001
2 PJDLC05C_SOT23-3 2
No42 +3VALW +3V_LAN SP020008Y00
R2406
2 @ 1

1
0_1206_5% Capacitors C1130-C1133 are only needed if
speaker connector is physically far from audio
3 1 codec. When in doubt, it's always a good No22
S

idea to have population option. Place them

Q2439 close to speaker connector. H2411 H2412 H2413 H2414 H2418 H2420 H2424 H2425
G

AO3413L_SOT23-3
2

20,45 PCH_PWR_EN# 3P3 * 4 @ @ @ @ @ @ @ @

1
H2417
JLAN1 CONN@ H2415 H2416
1 H2422 H2423
+3VS 1 2 2 CLK_PCIE_LAN 14
3 3 4 4 CLK_PCIE_LAN# 14
5 @
6 6 LAN_CLKREQ# 14

1
5 @ @
14 PCIE_PRX_DTX_P1 7 8 8 NUM_LED# 41
1

7 @ @
14 PCIE_PRX_DTX_N1 9 10 10 CAPS_LED# 41

1
9
14 PCIE_PTX_C_DRX_P1 11 11 12 12 PWR_SAVE_LED# 41
14 PCIE_PTX_C_DRX_N1 13 13 14 14 KSO0 41,42
15,39,44 PCH_PCIE_WAKE# 15 15 16 16 KSI1 41,42
41 EC_PME# 17 17 18 18
5,17,40,41,44 PLT_RST# 19 19 20 20
21 GND GND 22

ACES_87242-2001-09

BUTTON Open Door shut down key

SP02000OH00 No19
Normally door closed --> BI low --> battery power on
Battery Indicator BTN No27 Open door --> BI high --> battery power off
No35
SW2402 No38
MPTCFG-T-Q-T-R_2P No7
KSO0
3 3
R2641
3

0_0402_5% JSW1 CONN@

KSI1 PWR SAVE BTN# 50 BI 1 @ 2 BI_R 1 1
KSO0 1 2 KSI2 KSI2 41,42 2 2

R2642
0_0402_5% 3
5

BI_RESET G1
1 2 4 G2
ACES_88266-02001
SN100001D10
ESD request 10/5 SP020008Y00
D2413
ON/OFFBTN# 2
PWR board 1
KSO0
PWR_LED# 3 KSI1 PWR SAVE button Reset key (shut down)
+3VALW press: low pulse --> shut down --> need user to press power button to turn on
PJSOT24CH_SOT23-3 KSI2 Battery ID BTN#

JPWR1 CONN@ +RTCVCC

1 R2628
1 1K_0402_5%
2 2 PWR_LED# 42 check: PWR_SAVE# and BAT_STAT use keyboard matrix
3 ON/OFFBTN# 43 1 2 BI
3
4 4

5 D2430 R2644 SW2404

GND

3
6 3 0_0402_5% S Q2435
GND 49,50 MAINPWON
1 1 @ 2 1 3 BI_GATE 2 AO3413L_SOT23-3
ACES_88514-0401 2 G
49 3V5V EN D
2 4

1
1
4 BAV70W_SOT323-3 EVQPLHA15_4P 4

6
5
1
D R2629
SP01000R400 BI_GATE 2 Q2438 10K_0402_5% BI_RESET
G 2N7002H_SOT23-3
S

2
check: SN111002700
PWR indicator is the same as PWR_LED?

Security Classification Compal Secret Data

Issued Date 2007/1/15 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 46 of 57
A B C D E
 5 4 3 2 1

ACES_50305-00441-001 PL1
SMB3025500YA_2P
VIN PJ1 @ PJ2
1 1 1 2 +3VALWP 2 2 1 1 +3VALW +0.75VSP 2 2 1 1 +0.75VS
2 2
3 JUMP_43X118 @ JUMP_43X118
3
4 4
GND 5

1
6 PC3
GND PC1 PC2 100P_0402_50V8J PC4
PJP1 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K

2
PJ3 PJ4
+5VALWP 2 1 +5VALW +VCCSAP 2 1 +VCCSA
D 2 1 2 1 D
PJ25 @ JUMP_43X118 @ JUMP_43X118
@ JUMP_43X39
1 1 2 2
2

PD9 @ VIN PJ5 PJ6 +VGA_CORE

PJSOT24CH_SOT23-3 +1.8VSP 2 1 +1.8VS +VGA_COREP 2 1
2 1 2 1

2
PD1 @ JUMP_43X118 @ JUMP_43X118
LL4148_LL34-2 PJ7
1

2 2 1 1

1
PD2 PJ8 @ JUMP_43X118
LL4148_LL34-2 2 1
2 1
BATT+ 2 1

1
@ JUMP_43X118
PR1 PR2 PJ10
68_1206_5% 68_1206_5% PJ9 +1.5V @JUMP_43X39
PQ1 VS +1.5VP 2 1 1 1
TP0610K-T1-E3_SOT23-3 2 1 +VSBP 2 2 +VSB

2
@ JUMP_43X118
0.22U_0603_25V7K

N1 3 1
1

PR3 1 PC6 PJ11

PC5

C 100K_0402_5% 0.1U_0603_25V7K C
2 2 1 1
2

PR4 @ JUMP_43X118
2

22K_0402_5% +1.05VS_VCCPP PJ13 +1.05VS_VCCP

43 51ON# 1 2 2 2 1 1
@ JUMP_43X118

Pre_chg PQ2
PR5 VIN PR6 LL4148_LL34-2 TP0610K-T1-E3_SOT23-3
0_0402_5% 1K_1206_5% PD3 B+
+CHGRTC 1 2 1 2 2 1 3 1
+3VLP

100K_0402_5%
@ @ @

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
PR7 100K_0402_5%

1
1K_1206_5%
PR8

PR9
1

1
1 2
- +

PC114
PC80

PC81
PBJ1 PR11 PR12
560_0603_5% 560_0603_5% PR10

2
2 1 1 2 1 2 +RTCBATT 1K_1206_5%
2

2
1 2
2

B PR13 B

1
ML1220T13RE 1K_1206_5%
@ 1 2 PR14
12 100K_0402_5%
1

0_0402_5% PQ4
PR15 PD20 PDTC115EU_SOT323-3
41 ACOFF 2 1 2
1 2 2
+5VALW 3

BAS40CW_SOT323-3
PQ3
3

PDTC115EU_SOT323-3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 47 of 55
5 4 3 2 1
 A B C D

for reverse input protection

1
PQ5 D
2
G SI1304BDL-T1-E3_SC70-3
S

3
PR16 PR17
1 2 1 2

1 1M_0402_5% 3M_0402_5% 1

VIN P1 P2 B+ CHG_B+
AO4466L_SO8 AO4466L_SO8 0.56UH_1127AS-R56N_3.3A_30% AO4466L_SO8
PQ6 PQ7 PL16 PQ8
8 1 1 8 1 4 PR18 1 2 8 1

2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
7 2 2 7 @ 7 2

10U_0805_25V6K

0.1U_0402_25V6
6 3 @ 3 6 2 3 0.02_2512_1% 6 3
2200P_0402_50V7K

PC119
0.1U_0402_25V6

10U_0805_25V6K
0_0402_5%
5 5 5 @

0.01U_0402_50V7K
PC10

PC11

PC13
PC109
1

0_0402_5%
PR19

PC12
1

1
VIN

PC7

PR20
4

PC14
2

1
PC8

2
1

1 2
2

2
0.1U_0402_25V6
PC9 PD5
2

0.1U_0402_25V6 BAS40CW_SOT323-3

1
BQ24725_BATDRV 1 2

PC15
0.047U_0402_25V7K PR21

1
4.12K_0603_1%

4.12K_0603_1%
4.12K_0603_1%
PC16
1

1 2
PR22

PR23

5
10_1206_1%

10_0603_5%
PR25
1
VIN

PR24
0.1U_0603_25V7K
2

2
1

PQ9

BQ24725_ACN
2 2

1
PR26 SIS412DN-T1-GE3_POWERPAK8-5

PC17

BQ24725_ACP

BQ24725_BST 2
@ 3.3_1210_5% DH_CHG 4

2
PC18 PD6

BQ24725_LX
2
1 2 RB751V-40_SOD323-2 BATT+
1 2

DH_CHG
PL2
1U_0603_25V6K PC19 4.7U_LF919AS-4R7M-P3_5.2A_20% PR28

3
2
1
1 2 0.01_1206_1%
PR27 BQ24725_LX 1 2 CHG 1 4
@ 3.3_1210_5% 1U_0603_25V6K

4.7_1206_5%
20

19

18

17

16

SIS412DN-T1-GE3_POWERPAK8-5
2 3
2

CSOP1
PU1

2200P_0402_50V7K

0.01U_0402_50V7K
CSON1
1
PHASE

HIDRV

BTST
VCC

REGN

PR29

10U_0805_25V6K

10U_0805_25V6K
1

21

0.1U_0402_25V6

0.1U_0402_25V6
PC20 PAD

PC24

PC26
PC21

PC22
1

1
PQ10
@ 2.2U_0805_25V6K 1 15 DL_CHG 4 @
2

ACN LODRV

PC23

PC25
2

2
2 14

680P_0402_50V7K
2.2U_0603_16V6K
ACP GND PR66

3
2
1

2
1
BQ24725RGRR_VQFN20_3P5X3P5 10_0603_5%

PC27
BQ24725_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP

1
PR67

PC28

2
6.8_0603_5%
BQ24725_ACDRV 4 12 SRN1 2 CSON1 @

2
ACDRV SRN
PR30
+3VALW 1 2 5 11 BQ24725_BATDRV
ACOK ACDET BATDRV
10K_0402_1%
IOUT
3 3

SDA

SCL

ILIM
PR31 Pre_chg +3VALW
6

10
1 2
15,41,45 ACIN PR32
1

10K_0402_1% 1 2

0.01U_0402_25V7K
PD7

100K_0402_1%
PR33 RB751V-40_SOD323-2 316K_0402_1%

1
VIN

PC29
PR34

1
2

1 2

2
154K_0402_1%

255K_0402_1%
1

PR35

Vin Dectector
Min. Typ Max.
2

H-->L 17.23V
0.1U_0402_25V6

66.5K_0402_1%

L--> H 17.63V EC_SMB_CK1 41,50

1

PC30

PR36

ILIM and external DPM

2

EC_SMB_DA1 41,50
3.97A PC31
2

4 2 1 ADP_I 41,50 to EC 4

100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 48 of 55
A B C D
 5 4 3 2 1

2VREF_8205

1U_0603_10V6K
D D

1
PC32

2
PR37 PR38
13K_0402_1% 30K_0402_1%
1 2 1 2

PR39 PR40
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
HCB4532KF-800T90_1812 1 2 1 2
PL3
B+ 1 2 Typ: 175mA +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.1U_0603_25V7K
PR41 PR42
110K_0402_1% 154K_0402_1%
PC33

PC40
4.7U_0805_10V6K
1 2 1 2
1

1
PC34

PC35

PC36

PC37

PC38

PC39
5

5
PU2
2

2
PC41
PQ11 PQ12

ENTRIP2

REF
FB2

FB1

ENTRIP1
TONSEL
1
C C
25 P PAD

2
4 4
7 VO2 VO1 24
SPOK 50
8 23 PR44 PC43
SIS412DN-T1-GE3_POWERPAK8-5 PR43 VREG3 PGOOD 0_0603_5% 0.1U_0603_25V7K SIS412DN-T1-GE3_POWERPAK8-5
1
2
3

3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
PL4 0_0603_5% BOOT2 BOOT1 PL5
4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A PC42 UG_3V 10
VFB=2.0V 21 UG_5V 4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A
0.1U_0603_25V7K UGATE2 UGATE1
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

1
4.7_1206_5%

4.7_1206_5%
SI7716ADN-T1-GE3_POWERPAK8-5 LG_3V 12 19 LG_5V
LGATE2 LGATE1

5
@ PR45

@ PR46
PQ13

SKIPSEL
PR47 @

VREG5
46 3V5V EN 0_0402_5%

GND

VIN
RT8205EGQW_WQFN24_4X4

NC
EN
1 2 1 1
2

2
4
PC44 + 4 PC46 +

13

14

15

16

17

18
1

1
680P_0402_50V7K

680P_0402_50V7K
PR48
PD8
@ PC45

@ PC47
330U_D2E_6.3VM_R25M 499K_0402_1% 150U_D2E_6.3VM_R18
2 2
1 2 1 2
2

1
2
3

2
B+

3
2
1
RLZ5.1B_LL34
1
100K_0402_1%

1U_0603_10V6K
VL

1
PC48

1
PR49

PC49
4.7U_0805_10V6K
B Typ: 175mA PQ14 B

2
SI7716ADN-T1-GE3_POWERPAK8-5
2

2
ENTRIP1 ENTRIP2 RT8205_B+

1
6

D D

0.1U_0603_25V7K
PQ15A 2 5
DMN66D0LDW-7_SOT363-6 G G PQ15B 2VREF_8205

2
PC50
DMN66D0LDW-7_SOT363-6
S S TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
1

(2)SMPS2=375KHZ(+3VALWP)

PR51
100K_0402_1%
VL 2 1

+3.3VALWP +5VALWP
46,50 MAINPWON PR50 Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
0_0402_5% f=375KHz, L=4.7UH f=300KHz, L=4.7UH,Rentrip=154k ohm
1

2 1
PQ16 Rdson=15~18m ohm Rdson=15~18m ohm
PD4 1M_0402_1% PDTC115EU_SOT323-3 1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
LL4148_LL34-2 PR53
2 1 1 2 2
Vlimit=10*10^-6*110Kohm/10=0.11V Vlimit=10*10^-6*154Kohm/10=0.15V
VIN Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
402K_0402_1%

4.7U_0603_6.3V6K

A Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT- Iocp=8.44~11.57A (8.44>8.4 -> OK) A

1

PR52
1
PR54

PC51

316K_0402_1%
3

2 1
VS
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 49 of 55
5 4 3 2 1
 5 4 3 2 1

D ACES_50299-01001-001 D

10 10
9 9
8 8
7 EC_SMDA
7 EC_SMCA
6 6
5 TH
5 BI+
4 4

2
3 3
PR55
2 2
1 100_0402_1%
PH1 under CPU botten side :
1

2
PJP2 PR56
CPU thermal protection at 92 degree C

1
100_0402_1%
<40,41> EC_SMB_DA1 41,48
VL
Recovery at 72 degree C
VMB

1
1
PL6
SMB3025500YA_2P
<40,41> EC_SMB_CK1 41,48
1 2 BATT+ PR57

1
1K_0402_5%

2
PR60 PC52 PR58 PR59
1

6.49K_0402_1% 0.1U_0603_25V7K VL 10K_0402_1% 21K_0402_1%

2
PC53 PC54 2 1
0.01U_0402_25V7K +3VALWP
1000P_0402_50V7K
2

2
2
PU3
@ PR61 1 8
VCC TMSNS1

1
100K_0402_1%
PR62 2 7 2 1
1K_0402_1% GND RHYST1

1
3 6 PR63
~OT1 TMSNS2
C 46,49 MAINPWON 9.53K_0402_1% C

2
4 ~OT2 RHYST2 5 2 1
BATT_TEMP 41 @ PR64
G718TM1U_SOT23-8
47K_0402_1%

46 BI

1
PH2 PH1
@ 100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC

2
PQ19
TP0610K-T1-E3_SOT23-3

3 1
0.22U_0603_25V7K

B+ +VSBP
100K_0402_1%
1
PR65

PC55
1

PC56
0.1U_0603_25V7K 65W@ PR74
2

5.62K_0402_1%
2

PR68
VL 22K_0402_1%
1 2
2

+3VALWP
PR69 PR70

B
100K_0402_1% 0_0402_5% ADP_I 41,48 B

1
PR71 1 2 @
1

1K_0402_5% D PR72
1 2 2 PQ20 7.15K_0402_1%
49 SPOK
1U_0402_6.3V6K

1
G 2N7002W-T/R7_SOT323-3
S +3VS @ PC57
PC58

2
1

1
0.1U_0603_25V7K

2
PR73 PR74 90W@

1
10K_0402_1% 8.87K_0402_1% D
2

2 65W/90W# 41

1
@ PR75 G

2
0_0402_5% PR76 S

3
1 2 100K_0402_1% PU4 @
5,41 H_PROCHOT# 1 VCC TMSNS1 8 PQ21
2N7002W-T/R7_SOT323-3

2
2 GND RHYST1 7 1 2
1

@ D
PQ22 2 3 6 PR77 90W@
2N7002W-T/R7_SOT323-3 G OT1 TMSNS2 16.2K_0402_1%
S 4 5
3

OT2 RHYST2

1
G718TM1U_SOT23-8 PR78
65W@ PR77 10K_0402_1%
28.7K_0402_1%

2
For 65W adapter==>action 70W , Recovery 54W
For 90W adapter==>action 97W , Recovery 75W
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 50 of 55
5 4 3 2 1
 A B C D

PL17
1.5_8209_B+ 1 2
B+

5
6
7
8

2200P_0402_50V7K

0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PQ23 FBMA-L11-322513-151LMA50T_1210

1
PC59

PC60

PC61

PC62
PR81
267K_0402_1% 4

2
PR82 1 2
0_0402_5%
1 2
41,44,45 SYSON AO4406AL_SO8

3
2
1
1 1

2
47K_0402_5%
PR83 PC63 PL7

@ PR84
0_0603_5% 0.1U_0603_25V7K 1UH_FDUE1040D-1R0M-P3_21.3A_20%

15

14
+1.5VP

1
@ PU5 BST_1.5V 1 2BST_1.5V-1 1 2 1 2
PC64

BOOT
NC
EN/DEM
.1U_0402_16V7K

2
2 13 DH_1.5V
TON UGATE

1
3 12 LX_1.5V 1
VOUT PHASE

5
6
7
8
@ PR85
@PR85
VFB=0.75V PQ24 4.7_1206_5% + PC65
4 VDD CS 11 +5VALW 330U_D2E_2.5VM
5 10

2
FB VDDP 2
6 9 DL_1.5V 4
PGOOD LGATE

PGND
PR86

GND

1
15K_0402_1%
100_0603_5% @ PC67
@PC67

1
PR87
1 2 680P_0402_50V7K
+5VALW RT8209MGQW_WQFN14_3P5X3P5 PC66

3
2
1

2
4.7U_0805_10V6K AO4456_SO8

2
1

2
PC68
4.7U_0603_6.3V6K

2
<Vo=1.5V> VFB=0.75V PR88
V=0.75*(1+10K/10K)=1.5V 1 2
Fsw=298KHz
10K_0402_1%

1
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
2 Ipeak=19.53A, Imax=23.44A, Iocp=13.67A PR89 2

Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.63A 10K_0402_1%

=>1/2Delta I=2.315A
choose Rcs=15K 2
Iocpmax=((15K*11uA)/0.0045)+2.315A=35.65A
Iocpmin=((15K*9uA)/(0.0056*1.3))+2.315A=23.06A
Iocp=23.06A~35.65A

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 51 of 55
A B C D
 5 4 3 2 1

1.8VSP
Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A
Vout=0.6*(1+(20K/10K))=1.8V

PU6 PL8

4
PJ17 2.2UH 20% FDSD0630-H-2R2M=P3 8.3A
2 1 10 2 LX_1.8V 1 2
+5VALW

PG
2 1 PVIN LX +1.8VSP

68P_0402_50V8J
@ JUMP_43X118 9 3
PVIN LX

1
4.7_1206_5%
1

1
PC70
PC69 8 SVIN

PR90
22U_0805_6.3VAM PR91
6 FB_1.8V 20K_0402_1%

2
D
EN_1.8V FB D

22U_0805_6.3VAM

22U_0805_6.3VAM
5

2
EN

1
NC

NC
TP

PC71

PC72
FB=0.6Volt

11

2
1 2
39,41,45,53 SUSP#

1
1

680P_0603_50V7K
PR92 100K_0402_5%

0.1U_0402_10V7K
2

PC73

PC74
SY8033BDBC_DFN10_3X3 PR93

1
PR94 10K_0402_1%

2
1M_0402_5%

2
2
1
+3VS

10K_0402_5%
PR103
1
0_0402_5%
PR105
2 1 SA_PGOOD 41
C C

PU7 4 PL9
PJ18 2.2UH 20% FDSD0630-H-2R2M=P3 8.3A
2 1 10 2 LX_VCCSAP 1 2
+5VALW
PG

2 1 PVIN LX +VCCSAP

68P_0402_50V8J
@ JUMP_43X118 9 3
PVIN LX

2
4.7_1206_5%

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
1

1
PC75
PC76 PR101

22U_0805_6.3VAM
8 SVIN

1
PR97

PC78

PC82

PC83
22U_0805_6.3VAM 0_0402_5%

PC84
6 FB_VCCSAP
2

2
EN_VCCSAP FB
5

2
EN PR102
NC

NC
TP

1 2 VSSSA_SENSE 9
FB=0.6Volt 0_0402_5%
11

1 2 @
53 VCCPPWRGOOD PR100 PR107
@

680P_0603_50V7K
PR99 100K_0402_5%
0.1U_0402_10V7K

1 2 1 2 VCCSA_SENSE 9
2

PC79

PC77
SY8033BDBC_DFN10_3X3
1

PR104
2
1M_0402_5% 3.4K_0402_1% 10_0402_5%
2
1

+3VS

1
PR108

1
20K_0402_1% PR109
10K_0402_5%

2
PR95
10K_0402_1% PR111

2
1
2 D 10K_0402_5%
2 2 1
G

1
B B
S PQ28

1
PQ27 PMBT2222A_SOT23-3

1
2N7002W-T/R7_SOT323-3 @ PC85 PR112 @
4700P_0402_25V7K 100K_0402_5% 2 2 1

1
VCCSA_VID1 9

2
PR113 100K_0402_5% @ PR114

3
10K_0402_5%

2
VID[0] VID[1] VCCSA Vout Require on 2011/ 2012 Required
0 0 0.9 V Yes/Yes
0 1 0.8 V Yes/Yes
1 1 0.75V No/Yes
1 1 0.65V No/Yes
A A

Note:Use VCCSA_SEL to switch High & Low Level for VID[1]

(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 52 of 55
5 4 3 2 1
 5 4 3 2 1

PU8

+1.5V 1 VIN VCNTL 6 +3VALW

2 GND NC 5

1
PC87

1
PC86 3 7 1U_0603_10V6K
4.7U_0805_6.3V6K PR115 VREF NC

2
1K_0402_1% 4 8
VOUT NC
D 9 D

2
TP
G2992F1U_SO8

.1U_0402_16V7K
PR116
+0.75VSP

1
24.9K_0402_1% D PQ30

PC88
5,45 SUSP 1 2 2 2N7002W-T/R7_SOT323-3

1
G D PR117 PC90

2
1
S 2 SUSP 1K_0402_1% 10U_0603_6.3V6M

3
PC89 G

2
1U_0402_6.3V6K PQ29 S

3
2N7002W-T/R7_SOT323-3

PL18
1.05VS_51117_B+ 1 2 B+

2200P_0402_50V7K

0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
FBMA-L11-322513-151LMA50T_1210

5
6
7
8
C C

1
PC91

PC92

PC93

PC94
PR118 PQ31
267K_0402_1% AO4406AL_SO8
1 2

2
39,41,45,52 SUSP# PR119
680K_0402_5% @ 47K_0402_5% 4
1 2 PR120
1

PR121 PC96

15

14
1

1
PQ45 PU9 0_0603_5% 0.1U_0603_25V7K PL10

3
2
1
2N7002W-T/R7_SOT323-3 PC95 BST_1.05VS_VCCP 1 2 1 2 1UH_FDUE1040D-1R0M-P3_21.3A_20%

EN/DEM

BOOT
NC
+1.05VS_VCCPP
1

D 0.1U_0603_50V7K 2 1
2

SUSP 2 2 13 DH_1.05VS_VCCP
2

G TON UGATE

1
S 3 12 LX_1.05VS_VCCP
3

VOUT PHASE

5
6
7
8
@ PR122
4 11 4.7_1206_5% 1
VDD CS
VFB=0.75V + PC97
5 10 +5VALW

1 2
FB VDDP

2
330U_D2E_2.5VM
PR124 6 9 DL_1.05VS_VCCP 4
PGOOD LGATE

PGND
100_0603_5% @ PC98 PR123 2 PR145
GND

1 2 680P_0402_50V7K 0_0402_5% 0_0402_5%

+5VALW

2
PQ32 2 1 VSSIO_SENSE 8

1
1

1
15K_0402_1%
RT8209MGQW_WQFN14_3P5X3P5 AO4456_SO8
7

3
2
1
1

PR125
PC99
PC100 4.7U_0805_10V6K

2
4.7U_0603_6.3V6K
2

2
B B

PR126
4.02K_0402_1%
1 2
PR128
1

10_0402_5%
52 VCCPPWRGOOD PR129 2 1 VCCIO_SENSE 8
PR127 1 2 +3VALW
10K_0402_1%
10K_0402_1%
2

PR130 @
10K_0402_1%

<Vo=1.05V> VFB=0.75V
1

V=0.75*(1+4.02K/10K)=1.052V
Fsw=298KHz
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=12.866A, Imax=9A, Iocp=15.439A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=3.33A
A =>1/2Delta I=1.665A A

choose Rcs=15K
Iocpmax=((15K*11uA)/0.0045)+1.665A=37.62A
Iocpmin=((15K*9uA)/(0.0056*1.3))+1.665A=23.02A
Iocp=23.02A~37.62A Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 53 of 55
5 4 3 2 1
 5 4 3 2 1

GFX_B+

GFX@ PC101

GFX@ PC102

GFX@ PC103
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
1

1
@ 1K_0402_1%

CSD17308Q3_SON8-5
PR153
PC105 PR140 2 1 +VGFX_CORE

GFX@ PQ33
GFX@ 39P_0402_50V7K GFX@ 2.55K_0402_1% @ PC107

2
2 1 2 1 330P_0402_50V7K GFX@ PR134
1 2 10_0402_1% UGATEG 1 2 4
VCC_AXG_SENSE 9

2
PR135
@ 330P_0402_50V7K GFX@ 422_0402_1% PR221
2 1 2 1 2 1 2 1 2 1 VSS_AXG_SENSE 9
0_0603_5% GFX@ PL12
+VGFX_CORE

3
2
1
2

1
GFX@ PC112 GFX@ PR139 GFX@ 330P_0402_50V7K GFX@ PC110 0.36UH_PCMC104T-R36MN1R17_30A_20%
PC116

294K_0402_1%
150P_0402_50V8J 475K_0402_1% PC104 0.01U_0402_50V7K 2 1 PHASEG 4 1

PR136
GFX@ PC108 1
1

680P_0603_50V7K 4.7_1206_5%
D GFX@ PR143 0.22U_0603_10V7K 3 2 D

5
+

@ PR138
10_0402_1% BOOTG 2 1 2 1 PC111
2

1
TPCA8057-H_PPAK56-8-5
2 1 GFX@ 330U_X_2VM_R6M
GFX@ PR137 GFX@ PR141 GFX@ PR142
GFX@ PC106 0_0603_5% 3.65K_0402_1% 1_0402_5% 2

2
UGATEG

PHASEG
1000P_0402_50V7K

LGATEG
BOOTG

GFX@ PQ34
LGATEG

NTCG
2 1 4

ISNG
ISPG

2
@ PC113
GFX@ PR144 GFX@ PH4
+5VS

1
GFX@ 8.06K_0402_1% 7.5K_0402_1% 10K_0402_1%_ERTJ0EG103FA
PR132 +1.05VS_VCCP +3VS 1 2 1 2
GFX@ PC115

41

40

39

38

37

36

35

34

33

32

31

3
2
1

2
.1U_0402_16V7K

2
PU10 1 2 1 2

COMPG

FBG

RTNG

ISUMPG

ISUMNG

NTCG

BOOTG

UGATEG

PHASEG

LGATEG
PAD

1
PR217 GFX@ PR147
GFX@ 1.91K_0402_1% PR218 11K_0402_1%

2
@ PC144
@PC144 0_0603_5% 1 2

2
.1U_0402_16V7K PR148 30 BOOT2

1
BOOT2
2

PR149 130_0402_1% 1 GFX@ PC117

2
54.9_0402_1% VWG UGATE2 .1U_0402_16V7K
UGATE2 29
2 1 2
1

1
PGOODG PHASE2
28
1

PHASE2

1
+3VS 41 GFX_CORE_PWRGD 3 PC118

ISPG
8 VR_SVID_DAT SDA
2

1.91K_0402_1%

27 LGATE2 PC164 GFX@ 0.047U_0402_16V4Z PR151

PR159 SVID_ALERT# LGATE2 1U_0603_10V6K GFX@ 953_0402_1%
4

2
8 VR_SVID_ALRT# ALERT#
2

@ 499_0402_1% 26
SVID_SCLK VCCP
5

2
8 VR_SVID_CLK SCLK
PR156

25 2 1 2 1 ISNG
+5VS
1

PR155 ISL95835HRTZ-T_TQFN40_5X5 PWM3

41 VR_ON 1 2 6 VR_ON
24 LGATE1 PR160 PR152 @ 0_0402_5% Connect to +5V can disable
1

0_0402_5% LGATE1 0_0402_5%

15 VGATE 7 PGOOD
23 PHASE1 GFX portion
PHASE1
41 VR_HOT# 8 VR_HOT#
22 UGATE1
UGATE1
1
47P_0402_50V8J

NTC 9 NTC
PC122

21 BOOT1
BOOT1

ISEN3/ FB2
C C
10
2

VW CPU_B+
470KB_0402_5%_ERTJ0EV474J

ISUMN

ISUMP
1

COMP

ISEN2

ISEN1
27.4K_0402_1%

VDD
RTN
GFX_B+
2

VIN
PR161

FB

1
PH5

PR162

11

12

13

14

15

16

17

18

19

20

2
2.2_0603_5%
2

PJ21

2
1

ISEN2

ISEN1
JUMP_43X39

2
NTCG @

1comp

FB

1
PC130 10P_0402_50V8J
+5VS
2

1
3.83K_0402_1%

1
PR158

1000P_0402_50V7K

0.22U_0603_25V7K

ISEN3
GFX@ 27.4K_0402_1%

PC123

2
2
FBMA-L11-322513-151LMA50T_1210
GFX@ 470KB_0402_5%_ERTJ0EV474J

2
2

PR164 PL11
1
1

1
PR133

PC129

PR163 1_0603_5% CPU_B+ 1 2 B+

1
8.06K_0402_1%

5
PH3

68U_25V_M_R0.44
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1
2

PC124

PC125

PC126
CSD17308Q3_SON8-5
1

0.22U_0402_6.3V6K2
+

PC127
1U_0603_10V6K
comp
2

0.22U_0402_6.3V6K2

1
PQ35
PC131
680P_0402_50V7K
1

PC133
20.5K_0402_1%
2

2
PC137

PC136
GFX@ 3.83K_0402_1%

47P_0402_50V8J

UGATE2 1 2 4

2
1

1
PR172

1 2
PR131

PR226
267K_0402_1%

2
PR175

PC134

0_0603_5% PL13
1

3
2
1
0.36UH_PCMC104T-R36MN1R17_30A_20%
2

PHASE2 4 1
330P_0402_50V7K PR165 +CPU_CORE
2

680P_0603_50V7K 4.7_1206_5%
0_0603_5% 3 2
PC135 PR173

@ PR166
TPCA8057-H_PPAK56-8-5
BOOT2 2 1 2 1
VSUM-

@ 2K_0402_1% 1000P_0402_50V7K 887_0402_1% VSUM+

2
-
p
h
:h
PP
RR
1
7
2
=
2
0
.6
5
KK
VV
b
o
o
t
=
0=
V.
,
I
c
cI
mc
a
x
=
5
4=
A5

B PR177 PC132 B
0.22U_0603_10V7K
2
-
p
:
1
7
2
=
1
9

b
o
o
t
1
1
V
,
c
m
a
x
4
A

1 2 1 2 1 2 1 2

2
1

PQ36
LGATE2 4
FB

1.47K_0402_1%

PC141 PR167 PR169

0.022U_0402_16V7K
1

11K_0402_1%
470P_0402_50V8J @ 2.61K_0402_1% 3.65K_0402_1%
0.22U_0402_10V6K
1 2
1

1
PC139

@ PC140
VSUM+ 1 2
1

1
PR180 PC145

PR178

PC138

PR174
PR176
2

3
2
1
10K_0402_1%

2
3.32K_0402_1% ISEN2 1 PR168 2 PR171
2

2
1

1
100_0402_1%

PR170
2

2 PH6
10K_0402_1%_ERTJ0EG103FA VSUM- 1 2 2 1 ISEN1

CPU_B+
2

2 VSUM- 1_0402_5% 10K_0402_1%

5
@

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

PC147

PC148

PC149
PC146

CSD17308Q3_SON8-5
.1U_0402_16V7K

1
PQ37
2
0.01U_0402_50V7K
330P_0402_50V7K

UGATE1 1 2 4

2
1

1
PC142

PC143

PR227
2-ph: PR178=1.47K for ~70A OCP 0_0603_5% PL14
2

3
2
1
2

2
10_0402_1%

0.36UH_PCMC104T-R36MN1R17_30A_20%
PR179

PR181 PHASE1 4 1
10_0402_1% PR182 +CPU_CORE

680P_0603_50V7K 4.7_1206_5%
@ 0_0603_5% 3 2

@ PR183
TPCA8057-H_PPAK56-8-5
BOOT1 2 1 2 1
1

1
8

PQ38
VSSSENSE

+CPU_CORE PC150 PR185

VCCSENSE

0.22U_0603_10V7K 3.65K_0402_1%

2
LGATE1 4 VSUM+ 1 2

1
A A

@ PC151
10K_0402_1%
ISEN1 1 PR184 2
3 PR187
2
1

2
1_0402_5% 10K_0402_1%
VSUM- 1 PR186 2 2 1ISEN2

+CPU_CORE +GFX_CORE
Iocp=70A, IccMAX=53A Iocp=40A, IccMAX=24A Security Classification Compal Secret Data Compal Electronics, Inc.
Load line=1.9mohm Load line=3.9mohm Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title
DCR=1.1mohm DCR=1.1mohm
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
4019BI A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 54 of 55
5 4 3 2 1
 5 4 3 2 1

PJ20
B+ 2 1 B+_CORE
2 1
@ JUMP_43X118
+3VS

1
VGA@ PC152 VGA@ PC153

1
10U_1206_25V6M 10U_1206_25V6M
@ PR188

2
10K_0402_5%

5
D D

CSD17308Q3_SON8-5
2

VGA@ PQ39
VGA_PWROK
4

VGA@ PR189 VGA@ PC154

PU11 VGA@ 0_0603_5% 0.1U_0603_25V7K
VGA@ PR190 1 10 BST_VCORE 1 2 1 2

3
2
1
75K_0402_1% PGOOD VBST 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1 2 2 9 DH_VCORE VGA@ PL15
TRIP DRVH
+3VS 3 8 SW_VCORE 3 2
EN SW +VGA_COREP
4 VFB V5IN 7 +5VALW 4 1

1 2 5 6 DL_VCORE
RF DRVL
2

DL_VCORE
ESR=10mohm

2
@ PR192 VGA@ PR191 11
TP

1
10K_0402_5% 200K_0402_1% VGA@
RT8237_SON10_3X3 PC155 PQ40 PQ41 VGA@ PR193

TPCA8057-H_PPAK56-8-5

TPCA8057-H_PPAK56-8-5
1

1
VGA@ PR194 VFB=0.7V 1U_0603_6.3V6M 4.7_1206_5% 1
1

10K_0402_1% VGA@ PR195 VGA@ PC157

VGA_ON 1 2 0_0402_5% + 330U_D2E_2.5VM

1 2
17,45 VGA_ON Switch freq. (RF pin setting) 4 4

2
1

47K ==>450KHz 2

VGA@
VGA@ PC158 VGA@ PR196
VGA@ PC159 680P_0603_50V7K 10_0402_5%
100K ==>390KHz

2
VGA@
C .1U_0402_16V7K 2 1 C
2

3
2
1

3
2
1
200K ==>350KHz (Currently setting)
GS@ PR198
470K ==>300KHz

2
1.82K_0402_1%
GCORE_SEN
GV@ PR198 VGAVCC_SENSE 23
2.15K_0402_1%

1
GS@ PR201
6.49K_0402_1%
+3VSDGPU

2
1
GV@ PR201

2
8.66K_0402_1%
TPCA8057-H Rds=2.6m/3.2m ohm VGA@ PC160 VGA@ PR200 VGA@ PR202
2200P_0402_25V7K 10K_0402_1% 10K_0402_5%

1
2
VGA@ PR203

1
6
D 10K_0402_5%
2 1 2
G

2
DMN66D0LDW-7_SOT363-6
1

1
GS@ PR205 VGA@ PQ42A S

1
Vtrip range ==> 0.2V ~ 3V @ PR219 8.25K_0402_1% GV@ PR205 VGA@ PC161 @ PR206
16.2K_0402_1% +3VSDGPU 10K_0402_1% +3VSDGPU 4700P_0402_25V7K 10K_0402_5%

2
VFB=0.7V

1
2

2
V=0.7*(1+Rtop/Rbottom)

2
Fsw=350KHz VGA@ PR216 VGA@ PR207
B 10K_0402_5% 10K_0402_5% B

Cout ESR=12m ohm Rdson(max)=3.2 mohm Rdson(typ)=2.6 mohm. VGA@ PR222 VGA@ PR208
6

6
D 10K_0402_5% D 10K_0402_5%
1

1
Ipeak=41.02A, Imax=28.714A, Iocp=43A 2 1 2 2 1 2 +3VSDGPU
Delta I=((19-0.9)*(0.9/19))/(L*Fsw)=6.8A VGA@ PQ44A G VGA@ PQ43A G
1

1
=>1/2Delta I=3.4A DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6

2
S VGA@ PC163 S VGA@ PC162
1

1
choose Rcs=75K 4700P_0402_25V7K 4700P_0402_25V7K PR210 VGA@
2

2
10K_0402_5%
Iocpmax=((75K*11uA)/0.0013)+3.4A=75.52A @ PR220 +3VSDGPU @ PR209
2

2
Iocpmin=((75K*9uA)/(0.0016*1.35))+3.4A=48.42A 10K_0402_5% 10K_0402_5%

1
VGA@ PR211
Iocp=48.42A~75.52A

3
D 10K_0402_5%

2
5 2 1
GPU_VID1 22

1
G
@ PR223
10K_0402_5%
VGA@ PQ42B S @ PR212
VGA@ PR225

4
DMN66D0LDW-7_SOT363-6 10K_0402_5%
3

D 10K_0402_5% +3VSDGPU

2
52 1
VGA@ PQ44B G GPU_VID2 22

2
DMN66D0LDW-7_SOT363-6
GPU_VID1 GPU_VID0 S VGA@ PR224 @ PR213
4

NVIDIA/N12P-GS NVIDIA/N12P-GV1
10K_0402_5% VGA@ PR214 10K_0402_5%

3
D 10K_0402_5%
5 2 1
GPU_VID0 22
2

1
VGA@ PQ43B G
P0(Cold) 0 1 1.0V 1.025V VGA@ PR215
AP DMN66D0LDW-7_SOT363-6
S 10K_0402_5%

4
A A
P0(Hot) 1 0 0.975V 1.0V

2
P8/P12 1 1 0.825V 0.85V
AP
ES ---- ---- ---- 0.925V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title
SCHEMATIC,MB LA-A7121

4
0
1
9
B
I
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 14, 2010 Sheet 55 of 55
5 4 3 2 1
 5 4 3 2 1

A pahse 10/22
No1: P43, From JM50, change D2435 from SCS00000Z00 to SC600000B00
09/23 No17: From conn list, P40,update JREAD1 to DC021010041, update JUSB3 to DC231003030 No2, P33, delete 10/21 No 4 (add J2 for GND_LVDS for GND noise solution)
No01: P45, chnge Q2407 and Q2408, change DC interface part number, No18: P37, From ESD Jeremy, change USB ESD to SC300000O00 No3: P46, from ME request, add SPVS320200 for open door shut down function
change Q2407,2408,2410,2413,2414,2416,2423,2424 to SB00000EO10 No19: P46, From ESD Jeremy,add PWR board conn ESD SCA00000E10 No4: P46, change S1@ to install, S2@ to @
No5: P15, install R197 back
No02: P15, change PCH_GPIO32 to CLKRUN# and pull down 10/6 No6: P3, modify BOM config
No03: P18, delete Optimus_EN# and change to GPIO38 No1: P13, change BIOS conn SP07000F500
No2: P43, From ESD Jeremy, install D2416, D2402 10/24
09/24 No3: P5, From ME, change JXDP1 to SP01000N300 No1: update schematics part and footprint: L2406, L2407, D2432, Q2436, D2427, C1130~C1133
No04: P05,P16,P17,18, delete JXDP2 and relative intersheet symbols. No4: P46, delete JUSBFPC1 No2: P46, change U2407 to AO4430L_SO8 for more power eating
No05: P46, add 3P3 * 6 No5: P3, From EC Donate, update PID table
No06: D2100 swap from layout No6: From ME conn list, change JHDMI1: DC232001100; JLAN1: SP02000OH00 10/25
No07: delete DCR and COLOR_ENG_EN function No7: Update symbol: SW2400,SW2401, C1405~1436, C1457, C1458, C1300, C1314, C1451~1453, R229~R231, R2619, Q2429 No1: P41, P42, change netname from BATT_GRN_LED# to BATT_BLUE_LED#
No08: add LID_SW function and revise FAN circuits to following JM50 and NELA0 power circuits JMSJM_20101006.dsn combined: power circuits JM30_20101025.dsn combined
No09: add 3G@ for WWAN 1.Swap some component between NTC and NTCG. No2: P05, delete XDP and related circuits
No10: add R385 for reserved VCCIO_SEL pull high No3: P39, swap L2406, L2407
No11: change CPU 60pin XDP to 26pin, revise relative circuits 2.Delete PC128 No4: P46, change P/N only: SW2405 SN400000Z00 (ALPS P/N: SPVS410100)
3.Add +0.75VSP on power IC side. power circuits JM30_20101025A.dsn combined
09/27 4.PQ41 on VGA low side. No5: From JM40, P13, change SPI ROM (&U1) to SA00003K800
power circuits combined
No12: change WWAN circuits (EC_SIM_DETECT, UIM_DET, WWAN_DET#) 5.Change PQ25 to SIS412DN.
6.Change PQ26 to SI7716. 10/27
No1: From JM40, update P/N: PCH SA00004EE10
D
09/28 7.Swap PH1 and PH2. power circuits JM30_20101027.dsn combined ( for VID) D
No13: P39, add pull high +3VS at UIM_DET 8.Delete PD4.
No14: P22, reserve SM bus 0 ohm 7.Add PL16 for EMI.
power circuits combined 10/29
No15: P07, From JM50, change VCCIO_SEL PU from +3VALW to +3VS, should check No1: From JM40, P44, change USB3.0 number to SA000048H00
No16: P19, From JM50, delete R300 (+1.8VS path to +VCCAFDI_CRM)
No17: P35, Only UMA path, delete 0 ohm at the path
No18: P97, From JM50, change D2416 symbol and add D2402, change R2536 symbol 10/7
No19: P43, From JM50, delete power delay circuits (DGPU_PWR_EN to VGA_ON, SUSP# to VS_ON)
No20: P46, change Power board conn 4 pin SP01000R400 No1: Update footprint: R229, R230, R231 -- RP_0804_8P4R
No21: P42, From JM50, HDD LED sources from PCH and CR No2: Update symbol: R51, R214, Q2406, Q2414, Q2416, Q2423, Q16, U2402, U2401
power circuits LA-7121P_R01_20100928A.dsn combined
No22: P41, Power/ Jackie: delete IMVP_IMON, no need 10/8
No23: P41, move PLT_RST# pull low from R2226 to R388 No1: P18, from checklist and CG5, pull down PCH_GPIO36 and 37
No24: P3, add part location define No2: P7,From JM50, delete R and add T82~85 on VAXG_VAL_SENSE ...
No25: P18 and P35, From JM50, delete CRT_DET# (don't use this pin) and change CRT_DET to PCH_GPIO0 No3: P11,12, From JM50, delete R2039, R2041 M3 function
No26: P17 and P37, From JM50, change OC pin from USB_OC1# to USB_OC0# No4: P22, From JM50, add GPU_VID2
No27: P13, From JM50, change R107 to 0 ohm No5: P23, change part reference, R755~R760 change to R1507~1512
No28: P42, reserve C2402 No6: P25, From JM50,delete C1597, C1598 and add R1513, R1514 to GND
No29: P42, change JKB1 to SP01000R500, JTP1 to SP010014M00 No7: P23, From JM50, install R1431
No30: P97, change JUSB3 to DC233007O00 No8: P25, From NVIDIA, reserve one 0 ohm R1515 to connect to +1.05VSDGPU
No31: P39, modify UIM_DET function, reserve WWAN_OFF# path
09/29 10/11
No32: P17 and 39, change WWAN from USB port 11 to port 9, and update page 3 table No1: P46, change JUSBFFC1 pin definition: add 1 +5VS and delete 1 GND
No33: P14, change name : PEG_CLKREQ_R# to PEG_CLKREQ#_R No2: P15, From JM50, R186.2 connect to PCH_PWROK
No34: P05, delete SM bus to XDP No3: P14, for Layout request, shrink C180, C181 to 0603
No35: delete No31 No4: P13, from Lance, move R122 and R25 to audio sub board
No36: P13, add R25 at HDA_SYNC_R for potential leakage concern, (DG1.5) power circuits JM30_20101011C.dsn combined:
power circuits JMSJM_20100929.dsn combined Change item-->Back the pull-up power to +3VSDGPU for GPUVID, add GPU_VID2
No37: P42, From JM50, delete Q2431, no need to reserve it
No38: P42, from JM50, modify BATT LED circuits (need to confirm P/N); No5: P25, change R1515 connection to +1.05VS_DGPU
combine PWR_LED# and PWR_SUSP_LED# and change source from +3VS to +3VALW No6: P15, delete D2
No7: P22, delete C1440, add R1516, R1517
No39: P42, from JM50 GPIO table, No8: P22, From NV DG:
pin 16: USB30_LED# and rename USB3_LED# to USB30_LED# for related circuits for PLL, delete C1595, for NVVDD, delete C1442(330u), C1443~C1445, for PEX_PLLVDD, delete C1500, for FBx_PLLAVDD, delete C1508, C1513
pin 19: NC, and delete SUSWARN# from PCH. No9: P15, install R196
pin 21: 3G_LED# No10: P22, From NVCARE, GPIO12 pull high(R1404), and NV_PERFORMANCE(D1400) use diode to prevent leakage,
pin 25: NC delete R1409, R1402, R1403, T1400, change C1~C32 X7R
pin 70: EC_SIM_DETECT No11: P23, From NVCARE, add reserved 10K pull down on JTAG_TCK
pin 73: PWR_SAVE_LED#, and add this signal to LAN connector No12: P43, delete USB_100MA_OC# (wait the symbol ok)
No13: P39, change P39 +UIM_PWR_C to +UIM_PWR
pin 86: H_PROCHOT#_EC
pin 89: PWRSHARE_OE#
pin 97: NC 10/12
No1, From JM50, P17, P18, Change WWAN_OFF# from GPIO51 to GPIO37; Change WL_OFF# from GPIO55 to GPIO49
pin 103: EC_PME# No2, From JM40, P42, change TP switch: SN111002700, P46, change reset key:SN100003A00
C pin 106: CPU1.5V_S3_GATE No3, From JM40, P46, change JPWR1 pin definition C
No4, From JM40, P41, change ESD solution connection from SPI_CLK_R to SPI_CLK
pin 108: SA_PGOOD No5, From JM40, P39, add R2625 pull high for WWAN_LED#
pin 118: NC No6, From JM40, P18, change back PCH_GPIO38 to OPTIMUS_EN# and modify PU/PD
No7, P17,P18, check PCH power, delete L4, R296, L7, R325 and change C176, C199 from 0805 to 0603
No8, From ME, P42, BAT LED should be Top view, change LED2406 and LED2408 circuits
No9, From JM40, P41, reserve a path +3VLP to EC
No10, From RF, add C216, C217 for PCI CLK
No11, for BOM upload, change JUSBFFC1 to JUSBFC1, LED24xx to LED1,2,3,4,5; add ZZZ1
09/29 No12, for BOM upload,
No40: P02, modify block diagram change C1137, C1134, C1138, C1141 to SE074102K80,
No41: P04, P34, reserve eDP 2 lane
No42: P42, reverse KB conn pin define (pin1 different from the old one) change JP1 and JP3 "@",
No43: P44 and P97, change USB3.0 and Codec change Q59~Q62, Q1301, Q2100, Q2102~Q2109, Q2404, Q2409, Q2417, Q2426, Q2433, Q2434 from SB570020120to SB000008J10,
No44: P46, change power conn name to JPWR1 change JXDP1, JSPK1 and JSPK2 "CONN@",
No45: P39, correct name: +3V_WWAN to +3VS_WWAN;
delete PCIE IF; update C2726, C1309, C1400, C1509, C1514, C1446, C1447, C1480, C1487, R1483, R1486, R170, R173,
add 4 x 0 ohm for WWAN_DET# and UIM_DET R393, R1455, R1456, R1463, R1464, R1470, R1471, R1478, R1479, D2102, D2103, Q16
No46: P41, change EC pin define (from EC Donate), add AD_PID0 change T* to "@"
No47: P09, From JM50, delete +1.5V_CPU_VDDQ and delete JP2 from +1.5V

09/30 10/13
No1: P41, EC pin define change No1, From JM40, P39, change D2409 part for BOM
pin 106: PWR_SAVE_LED# (USB30_LED# delete y customer) No2, for BOM upload,
pin 118: NC change R1300 to SD00000BN80 (0603), change C2489, C2493, C2496, C2494, C2495, C2487, C2491, C2488, C2492, C2497, C2485
No3, From JM40, P43, modify USB30 charger function
No2: P17, P37, delete JUSB1 (will on daughter board), delete R2434 (already PU at PCH) No4, From JM40, P46, change SW2403 to SN400000I00
No3: P14, From JM50, add PCH_GPIO44 back; delete R95 No5, From Diode common, 2N7002 (SB000008J10), 2 in1 2N7002 (SB00000EO10), BSS138 (SB501380020)
No4: P14, P44, for USB30 clock, install R173, R2538, uninstall R2535, Y2400, C2607, C2608
No5: P14, From JM50, due to no PCH XDP, delete JTAG_TMS, TDO, TDI, add TP No6, for BOM upload, update C1321, C2101, C2107, C2217, C2475, C2477
No6: P15, From JM50, change CLKRUN# to PCH_GPIO32, Add pull high 8.2K No7, for Layout request, update H2424 footprint, delete H2414
No7: P18, From JM50, add T63 to T80 No8, follow nvidia, delete R1499~R1504, change C1~C32 to 0.1uF X7R
No8: P20, From JM50, uninstall R303, install Q12, C174, R307
No9: P41, From JM50, Change PWRSHARE_OE# to USB_CHARGE_CB, Change PWRSHARE# to USB_CHARGE_EN# 10/14
No10: P46, install R2584 for phase A test No1, P27, add GND connection: +FB_AVDD0, +FB_AVDD1
No11: P44, delete USB30_LED# circuits No2, P13, change R126 connection to HDA_SDOUT to HDA_SDOUT_R
No12: P43, From JM50, move USB3 conn and related power switch to P43 power circuits JM30_20101014.dsn combined:
No13: P36, From ESD Jeremy, change HDMI ESD L2110~L2113 to SM070000K00 and install them; No3, P46, From Layout request, delete H2421 H2419 (netlist 1B)
No14: P37, P96, From ESD Jeremy, change USB ESD L2110~L2113 to SM070000K00 and install them; No4, P36, From Layout request, swap L2110~L2113, (netlist 1C)
No5, P46, From Layout request, change H2423, H2422 footprint, (netlist 1D)
power circuits JM30_20101014A.dsn combined:
10/2
No1: P7, From JM50, delete CPU AN35, AM35 signal
No2: P9, From JM50, delete Q15 and change R83,R85 to 1k 10/15
No3: P13, From JM50, delete GPIO13, GPIO33 and test point No1, P37, add JUSB2 (standard type USB for study)
No4: P13, From JM50, delete GPIO21 pull low and board ID function No2, P46, From Lance, change reset key to SN111002700
No5: P17, From JM50, delete R2475, change DGPU_PWR_EN to VGA_ON, DGPU_PWR_EN# to VGA_ON# No3, From JM50, update connector list, change JBT1 to 6pin : SP02000FR00
B
No6: P17, From JM50, delete R331 (DGPU_HOLD_RST# pull high) No4, From layout request, H2423 , H2422 , H2420 , H2418 change to H_3P3, change JHDMI1 to SUYIN_100042GR019M23BZR_19P-S B
No7: P18, From JM50, install R285 No5, From JM50, change reset and D-door shut down solution
No8: P18, From JM50, delete R384 PWR_SAVE# No6, From JM50, change BAT ID BTN from KSI0 to KSI2
No9: P22, delete not neccessary part R1423 No7, P39, change EC_SIM_DETECT to EC_SIM_DETECT# due to low active
No10: P38, From JM50, reserved HDD +3VS No8, P18, P39, delete UIM_DET_PCH and WWAN_DET#_PCH path
No11: P41, From JM50, temporarily follow the name: active high: PWR_SUSP_LED, PWR_LED, wait for EC definition No9, P39, change +3VS to +3VS_WWAN circuits
No12: P42, From JM50, same as No11, add MOS to reverse the 2 signals
No13: P42, From JM50, change PWR_STAT key to KB matrix, and change LAN connector pin define (PWR_SAVE# --> KSI1, KSO0)
No14: modify LAN board conn, now use 24 pin, will study 20 pin ok or not 10/18
No15: revise P91~99 small board power circuits JM30_20101018.dsn combined:
No16: P42, From JM50, swap BATT_AMB_LED# with BATT_GRN_LED#, change HDD LED and R, change Wireless LED part and to +3VS No1, P44, From JM40, add R2631~R2634
No17: P46, From JM50, change PWRBTN_LED# to PWR_LED# No2, P41, From JM40, change +3VLAW to +3VALW_EC for 2 power sources
No18: P22, From JM50, add NV_PERFORMANCE to GPIO12, GPIO18 No3, P38, From JM40, change JHDD1 pin define
No19: P7,P11,P12, install M1@ and change M3@ to @ No4, P34, rename R478, R479, to R2154, R2155; change C492, C493 to C2151, C2152
No20: P43, From JM50, U2414.5 change power source to +USB3_VCCA, Delete R2619 No5, P39, From JM50, add WLAN1 components for BT: R2635, R2636, D2432, Q2436
No6, P43, P44, From JM50, change USB3 conn from port 2 to port 1
10/4 Bryant Hou No7, P13, From JM50, add PCH_GPIO19 pull high R394
No8, P18, From JM50, add PCH_GPIO28 pull high R395
Update JP4=>JUSBFPC1 No9, P44, From JM50, change U2412 to SA000046000
C1576 390U=>220U No10, P39, From JM50, change WWAN circuits
No11, (sourcer Amy requests, from Bryant mail 10/18 09:41PM)
USB3.0 & HDMI Conn Footprint change D2434 to SC600000B00,
U2419 footprint(need you chk) change D3, D4, D5, D6, D1400, D2106, D2107, D2200, D2401, D2429 to SCS00000Z00,
Combine new pw circuit change C1~C32, C1405~C1436, C1457, C1458 to SE076104K80
Add original JUSB1 circuit
Del JUSB2 circuit
add Speaker 10/19
No1, P5, change JXDP1.13 from VGATE to SYS_PWROK
No2, P37, delete JUSB2
No3, P41, add R2234, T2217, T2218
10/5 No4, From JM50, P44, change 11 cap from 0.1u to 0.01uF (C2572~C2576, C2578~C2583)
No1: P46, add USBFFC1 back and modify pin(add SPKR signal) No5, P46, reverse JFAN1 pin definition
No2: P46, modify JLAN1, delete 1 +3VALW, add 1 GND No6, P14, P7, add CLK_CPU_ITP / CLK_CPU_ITP# path
No3: P37, delete R2434 (double pull high) No7, P37, add JUSB2 back (colay )
No4: P43, From JM50, update U2414 symbol
No5: P13, From JM50, add Q4 and R100 for Audio Issue 10/20
No6: P43, Layout request, L2402, L2403, L2404 swap N-P No1, From ME, P13, change U4 from SP07000F500 to SP07000OJ00
No7: P22~P30, From JM50, based on JM50 circuits and JM30 part reference, No2, P33, From JM40, change VGA strap definition
(but delete VGA_HDMI_DET and HDMI output, IFPC power circuits, change PEG names) No3, P14, P7, delete 10/19 No6, reserve test point
power circuits JM30_20101020.dsn combined:
No4, P37, From layout request, L2401 swap
No8: P45, From JM50, Due to the change of GPU pages, DC interface changes too No5, P24, add 1 more 330uF for power study
No6, P34, reseve JLVDS1 pin7,8 for COLOR_ENG_EN and DCR
No9: page 34~46 change to page 31 to 43 No7, From JM40, P29, P30, change OPT@ to GS@
power page from P44 to P52 No8, From JM40, P22 to P33, modify some parts to GS@ and GV@
No9, From JM40, P14, P44, for USB3 wake up function, uninstall R173, R2538, install R2535, C2607, C2608, Y2400
EE modify list : p99 power circuits JM30_20101021.dsn combined:
No10, From JM40, P15, install R197
A
No10: page12, From connector list, No11, From JM40, P44, Change USB3.0 power name +3V to +3V_USB3, Change USB3.0 power name +1.05V to +1.05V_USB3 A
change JDIMM2 to SP07000NN00, No12, From JM40, P37, P43, ,use ABO common part, change U2400 and U2411 to AP2301MPG-13_MSOP8 (Follow HW3 Standard Part)
change JLVDS1 to SP010013I00,
change JCRT1 to DC060003L00 10/21
change JKB1 to SP01000GE00 power circuits JM30_20101021.dsn combined (power revises)
No1, P22, From JM50, delete D1400 and add Q1400
power circuits JM30_20101021.dsn combined (revise +VGFX_CORE jumps)
No2, From JM40,
No11: delete No7 and No8, change back original dGPU, add C1595~C1603, add R1498~R1506 P33, add U2102 circuits for INVTPWM ESD
P44, add R2637, R2638, R2639, (Follow Vendor suggestion), change power name +3VA to +3VA_USB3
, modify some R, C values P43, add D2435, D2436, R2640, (Stuff diodes to gate backflow from EC or PPON1)
No12: From power, P46, change reset button connection to 3V5V EN P39, change U2420.8 from +3VALW to +3VS
No13: for JM30/40/50/power common name: change +3VS_DGPU to +3VSDGPU
No3, P39, change D2431 to 2N7002
No14: P37, From JM50, change R2435 from 10K to 0 ohm No4, P33, add J2 for GND_LVDS for GND noise solution Security Classification Compal Secret Data Compal Electronics, Inc.
No15: P43, From JM50, Delete U36.1 net USB_Charge_EN# No5, P39, rename +3VS_GATE to +3VS_WWAN_GATE, and add BT_ON# intersheet
No16: P41, From JM50, Add EC GPIO No6, from DRC check, delete some redundant nets Issued Date 2008/08/10 Deciphered Date 2010/12/31 Title
Pin 118-->NV_PERFORMANCE No7, P53, power changes +VGFX_CORE SCHEMATIC,MB LA-A7121
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Pin 25-->USB_Charge_100mA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D A
Pin 18-->USB_Charge_2A# DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 56 of 57
5 4 3 2 1
 5 4 3 2 1

11/10 A phase SMT MEMO and Rework instruction

11/3
No1: P33, change X76@ R1491 samsung 64*16 PD 20K (from 25K)

11/5 SMT MEMO

No2: P33, change VRAM P/N: from SA00003MQ60 to SA000047Q20, from SA00003VS10 to SA00003YO00
No3: P44, uninstall R2637, R2639, install R2638 for BIOS setting from high active to low active
11/6 rework instruction
No4: P43,44, delete PPON1 signal and change D2435
11/8 rework instruction
No5: P41, add 10K pull high R2235 for EC_PME#
11/10 rework instruction
No6: follow nvidia Johnson Yeh, for N12P-GV strap pin:
below strap setting would need to be changed for N12P-GV-ES
1. ROM_SCLK: pull up 15K ohm.
2. ROM_SO: pull up 10K ohm.
D 3. STRAP2: pull up 45K ohm. D
4. STRAP3: pull down 5K ohm.
5. STRAP4: pull down 10K ohm.
6. STRAP_REF2, need to stuff with 40K ohm 1%.
7. PGOOD (pin E7) stuff 10K ohm.

11/11
No7: From DFB request, P46, change SW2402 to SN100001D10 (P5LM0 design)
No8: From JM40, change JUSB1 to TopYang DC021011051
11/12
No9: P41, delete colay EC BIOS ROM U2203
No10: P41, P46, Follow JM40 design, add EAPD signal for MUTE function in EC common code
No11: P37, change reserved JUSB2 P/N
power circuits JM30_2010-11-12A-FOR DCIN CONNECTOR.dsn combined
11/15
No12: P46; P34, change JUSBF1 P/N to SP01000GO00 (28 pin), and add DMIC_CLK, DMIC_DATA;
change JLVDS1 pin definition, but later should confirm with JM40/50
No13: P46, change JFAN1 P/N to SP02000H900 and swap pin definition
No8: JUSB1 footprint change because not sync up with ME
11/16
No14, P39,, change JWLAN1 pin definition: delete pin 17,19, 8, 10, 12, 14, 16;
P17, and delete R249 for no-use PCI CLK to WLAN
No8: change JUSB1 to TopYang DC021011051 and use DC021011050 footprint
No15, P37, delete JUSB2
No16, P43, change C2595 to SGA00002N80
11/19
No17, P43, add ON/OFF pull high R2467 to +3VALW_EC and unmount R2466
No18, From connector list v28, P43, JUSB3 to DC233008O00
No19, P46, (1) delete Open door shut down key (move to sub board), add 1 connector for this function;
(2) change reset key function, delete unmounted components
No20, P18, For VGA sequence logic, add circuits to DGPU_PWROK, and from pull high to pull low
11/24
No21, P44, To avoid leakage, delete R2638 0 ohm and add D2418
No22, P46, add H2414 7P0
11/25
No23, P44, To avoid SMIB leakage, Follow JM40 to do this circuit
No24, P14, reserve SMBUS 0 ohm: R396, R397, R398, R399
C C
11/26
No25, P43, revise USB3.0 function table
power circuits JM30_20101125.dsn combined
11/29
No26, P18, modify No20, delete VGA_PWROK path and add PMOS
No27, P46, modify P19, add back unpop parts, and reserve 0 ohm test resistor for open door function, use S1@ and S2@ to distinguish them
No28, P17, delete VGA_ON pull high
No29, P44, Modify No23, add pull low, change 2N7002
No30, P15, Follow JM40, change R210 to PCH_RSMRST#_R instead of PCH_RSMRST#
No31, P22, Follow JM40, change R1404 PU location from R1496.2 to Q1400.3
power circuits JM30_20101129.dsn combined
No32, P41, change Board ID:R2230 8.2K
No33, P34, From JM50, for LVDS rise sequence, change R2102 from 1K to 10K, change C2100 from 0.047u to 4.7U
11/30
No34, P18, modify VGA sequence - using 2 NMOS
No35, P46, modify reset and shut down function - delete S1@ and S2@ optional
12/1
No36, Follow JM40 2nd source,
D2101, D2105 change to SCS00003H00
D2417, D2427, D2435 change to SC100001K00
C186, C1459, C1473, C1474, C1477, C1478, C1484, C1485, C1498, C1506, C1510, C1515, C1538, C1539,
C1540, C1541, C1566, C1567, C1568, C1569, C1577, C1578, C1579, C1580, C1603, C2466 change to SE000000K80
No37, P34, 46, add EMI solution for DMIC_CLK, DMIC_DATA
power circuits JM30_20101201.dsn combined
No38, P46, From JM40, modify reset button
No39, P45, From JM40, change Q2415 to SB000007O10
No40, From JM40, due to common parts "AND", change U10, U11 to SA00000OH00
No41, add +3VS_CARD 0 ohm for power consumption measurement
new power circuits JM30_20101201.dsn combined again
12/3
No42, P46, Follow JM40add 3V_LAN MOS to separate 3VALW

date Func. No. Page

12/8 BOM change No43 Change SB000008J10 to SB00000J200
description No44 P33 VRAM hynix 128*16 --> SA00003YO20
VRAM samsung 64*16 --> value 0011
design change No45 P46 For DC power consumption and pwer sequence, change R2485 to 100K, R2490 to 200K, R2496 to 750K
BOM change No46 P17 change C1317 from @ to BT@
B
12/9 design change No47 P33 N12P-GV QS DevID: 0x1050, B
1. ROM_SCLK: pull up 5K ohm.
2. STRAP2: pull down 5K ohm.
3. ROM_SO: pull up 10K ohm.
4. STRAP3: pull down 5K ohm.
5. STRAP4: pull down 10K ohm.
6. STRAP_REF2, need to stuff with 40K ohm 1%.
7. PGOOD (pin E7) stuff 10K ohm.

STRAP0: as same as N12P-GS with 45K pull up.

STRAP1: pull down 35K as N12P-GS

should change later

P17 for VGA_ON pull high deleted, need to arrange RP instead R

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/08/10 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-A7121
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BI
Date: Tuesday, December 14, 2010 Sheet 57 of 57
5 4 3 2 1
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