Fa17-Eee-008 - Asssignment 2

ASSIGNMENT #2
Q. No. 1: Derive following equation of pMOS device resistance and show how voltage is
applied between source and drain terminals, hole mobility and gate capacitance contribute
to the resistance.
𝑅𝑝=1/𝛽(𝑉𝐺 − |𝑉𝑇𝑝|)
Solution:
For the channel creation the threshold voltage must be less than the gate voltage in Mosfets, so in
the case of Pmos device we use “− |𝑉𝑇𝑝|” because to allow a flow of current in order to create a
channel so,
Qc = CG*(VG - |𝑉𝑇𝑝|)
Whereas CG = Cox*AG
Also AG = W*L
So
CG = Cox*W*L
Hence,
Qc = (Cox*W*L)*(VG - |𝑉𝑇𝑝|)
Then current with respect of transient time (The time required to move for a hole from on p
region to another p region) will be
I = Qc/Tt
As Tt = L/v so,
I = Qc/(L/v)
By putting equation of Qc in above I then we get,
I = (Cox*W*v)*(VG - |𝑉𝑇𝑝|)
“v” in above equation is known as the velocity of a particle so,
v = up*E
Where up = mobility of a hole and E is known as electric field who is obtained by the voltage
applied over length so,
E=V/L
Hence by putting values of E and “v” in the I we get,
I = [Cox* up *(W/L)*V]*(VG - |𝑉𝑇𝑝|)
As we know that BP = Cox* up *(W/L)

So,
I = [BP *V]*(VG - |𝑉𝑇𝑝|)
As by ohm’s law
Rp = V/I
Hence,
Rp= 1/[BP* (VG - |𝑉𝑇𝑝|)]
This type of a tapered nature of the channel causes the current between S and D to grow less than
linear with VDS. When the voltage drop between the two capacitor plates at the drain side is such
that no more free electrons are available there then the channel is pinched off which means in a
constant state. This happens when VG – VD = Vth.
Q. No. 2: Show complete steps of CMOS process flow to design an inverter. Explain in
detail each step what processes are involved.
Solution:
Following steps must be taken in record to design an inverter:
Substrate
Start the process with selecting a substrate i.e p substrate.
N diffusion
Basically whenever the n diffusion is created then it means you have created Pmos
SIO2 Layer
When you apply this layer you then tell that where is the N region and P region or to distinguish
between these regions then other regions or areas are then isolated. This process is also known as
oxidation which is a process done by using high-purity oxygen and hydrogen, which are exposed
in an oxidation furnace approximately at 1000 degree centigrade.
Thin oxide Layer
After this we grow so to make sure that we cannot place any material above Sio2 layer.
Polysilicon layer
It is implanted above thin oxide layer when it is done then you cannot do any implantation below
it then.
N implant and P implant
When you do N implant the n region is created and same with P implant.
2nd Polysilicon layer
Whenever it is need it can be created after p implant, in case of inverter it is not needed.
Contact
Contacts are made to connect Nmos or Pmos to metal to make them terminals as for input or
output purpose.
Metal Deposit Layer
It is created after contact.
Formation of the N-well
By using ion implantation or diffusion process N-well is formed.
Removal of SiO2
Using the hydrofluoric acid, the remaining SiO2 is removed
Removing the layer barring a small area for the Gates
Except the two small regions required for forming the Gates of NMOS and PMOS, the
remaining layer is stripped off.
Oxidation process
Again, an oxidation layer is formed on this layer with two small regions for the formation of the
gate terminals of NMOS and PMOS.
Masking and N-diffusion
By using the masking process small gaps are made for the purpose of N-diffusion.
P-diffusion
Similar to the above N-diffusion process, the P-diffusion regions are diffused to form the
terminals of the PMOS.
Metallization
Aluminum is sputtered on the whole wafer.
Terminals
The terminals of the PMOS and NMOS are made from respective gaps.
Q. No. 3: Design a Full Adder layout using cell concept and using minimum space.
Solution: N.p ---->

Q. No. 4: What will be the expression for 𝐼𝐷𝑆𝑛= 𝑉𝑠𝑎𝑡.
Solution:
The condition should be VDSn=Vsat
As we know that the
IDn= un*Cox *(W/L) *[(VSGn - Vtn)VDSn- VDSn2 ]
But the given condition in question is that VDSn=Vsat
Hence,
IDn= un*Cox *(W/L) *[(VSGn - Vtn)*Vsat- Vsat2 ]
While we know that we Vsat= VGS - Vtn
So the IDn becomes,
IDn= un*Cox *(W/L) *[(VSGn - Vtn)*( VGS - Vtn)- (VGS - Vtn)2 ]
Hence,
IDn= un*Cox *(W/L) *[(VGS - Vtn)2 - (VGS - Vtn)2 ]
So,
IDn= 0
As Pinch off voltage is the drain to source voltage after which the drain to source current
becomes almost constant so we can that voltage maybe in pinch off state.
Q5. Revise lecture “Elements of Physical Design – Part 2 and summary of all the topics
covered in this lecture”.
In this lecture we have learnt about the elements of physical design from which following are
mentioned below with detail:
LAYOUT EDITOR
 NMOS and PMOS are formed where poly cuts down the N and P region respectively into
two segments.
 There are no electrical path conducting layers until it is created by using contact cut.
 Distinguish the different layers
 Provide functionality to create different layers
CELL CONCEPTS
 The building blocks in physical design are called cells.

 Cell based designs are straightforward to visualize because they are organized properly.
 Ports are basically inputs and output terminals.
 For placement of power lines 𝐷𝑚1−𝑚1 is the edge to edge distance btw input voltage
terminal VDD and ground terminal VSS.
 Pitch = 𝐷𝑚1−𝑚1 + 1.
 Edge to edge distance is very important in drawing the layout of a circuit.
 The transistors can be placed either horizontally or vertically after completion of the
placement of power lines.
 Mosfets width are limited to 𝐷𝑚1−𝑚1 (edge to edge distance btw VDD and VSS)
 They can also be placed horizontally or vertically.
 For horizontal case the 𝐷𝑚1−𝑚1 will be larger while X1 required will be smaller.
 When cells are combined they form a complex unit.
 Shape of cell affects how they fit together while every cell is a tile.
 An alternate approach uses alternate VDD and VSS power lines and alternate logic cells
are inverted so there is no space reserved for routing that’s why we need to used Metal2
or higher which offers high packing density.
 For port placement we have to make sure the input and output ports are placed in an ideal
location so to ensure smooth and convenient wiring.
 When designing a cell , what needs to be ensured is that cells can be wired together in a
complex arrangement which means that proper port placement is required.
 Mosfets are specified with respect to W/L ratio. 𝐴𝐺=𝐿×𝑊 and 𝐶𝐺=𝐶𝑜𝑥𝑊𝐿
 Channel resistance which impedes current flow is inversely proportional to width
 Mobility ratio 𝑟=𝜇𝑛𝜇𝑝=𝑅𝑝𝑅𝑛, where 𝑟>1between 2 and 3
 In order to design symmetric CMOS , 𝐶𝐺𝑝=𝑟𝐶𝐺𝑛
 Unit transistor is used to minimum size MOSFET.
 The design rules :
 minimum width of poly and minimum width of Active mask
 We will get 𝑊𝐿𝑚𝑖𝑛=𝑤𝑎𝑤𝑝 and 𝐶𝐺=𝐶𝑜𝑥𝑤𝑎𝑤𝑝

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ASSIGNMENT #2

By putting equation of Qc in above I then we get,

“v” in above equation is known as the velocity of a particle so,

I = [Cox* up *(W/L)*V]*(VG - |𝑉𝑇𝑝|)

As we know that BP = Cox* up *(W/L)

Rp= 1/[BP* (VG - |𝑉𝑇𝑝|)]

Following steps must be taken in record to design an inverter:

Start the process with selecting a substrate i.e p substrate.

Thin oxide Layer

N implant and P implant

2nd Polysilicon layer

Metal Deposit Layer

It is created after contact.

Formation of the N-well

By using ion implantation or diffusion process N-well is formed.

Using the hydrofluoric acid, the remaining SiO2 is removed

Removing the layer barring a small area for the Gates

Masking and N-diffusion

Aluminum is sputtered on the whole wafer.

Solution: N.p ---->

 The building blocks in physical design are called cells.

 We will get 𝑊𝐿𝑚𝑖𝑛=𝑤𝑎𝑤𝑝 and 𝐶𝐺=𝐶𝑜𝑥𝑤𝑎𝑤𝑝

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I = [Cox* up (W/L)V]*(VG - |𝑉𝑇𝑝|)