DEPARTMENT OF PHYSICS

NAME HLABANO INNOCENT

PRAC PARTNER SIZIBA THOMAS

PROGRAM HETTW 2.1

REGISTRATION NUMBER R181204

DATE OF EXPERIMENT 06/10/19

DATE OF SUBMISSION 13/10/19

TITTLE: EXPERIMENT E4:-SEQUNTIAL LOGIC DESIGN

Practical E4: Sequential Logic Design

1. Objectives And Objectives

a) To learn how basic sequential logic circuits work

b) To study the behaviour and applications of flip flops and basic sequential circuits including shift
registers and counters

Introduction And Theory

Logic circuits for digital systems are either combinational or sequential. The output of combinational
circuits depends only on the current inputs. In contrast, the output of a sequential circuit depends not
only on the current value of the input but also upon the internal state of the circuit that is on the
condition of earlier inputs. The basic building blocks (memory elements) of a sequential circuit are
the flip-flops (FFs). The flip flops change their output state depending upon inputs at certain interval
of time synchronized with some clock pulse applied to it. The McGraw-Hill Companies ,(2011)

A memory stores data – usually one bit per element. A snapshot of the memory is called the state. A
one bit memory is often called a bistable, - it has two stable internal states. The latch (flip-flop) is a
basic bi-stable memory element widely used in sequential logic circuits.  Usually there are two
outputs: Q and its complementary value, Q .  They are called state variables.  State variables which
change only between logic 1 and logic 0 are called binary state variables. 
In the practical, sequential logic circuits were introduced through the construction of a RS latch
(using NAND and NOR gates), which will help you to attain an understanding about how memory is
developed in logic circuits. Stability in the RS latch was obtained by implementing a series of gate
controls, all of which led to the development of the JK flip flop. Commercially available JK flip flops
were used to construct shift registers and counters.
(Digi-Key ELECTRONICS 2018) The SR flip – flop is one of the fundamental parts of the
sequential circuit logic. It is a memory device and a binary data of 1 – bit can be stored in
it.The SR flip – flop, as mensioned before has two stable states in which it can store data in
the form of either binary zero or binary one. Like all flip - flops, an SR flip - flop is also an
edge sensitive device.

SR flip – flop is one of the most vital components in digital logic and it is also the most basic
sequential circuit that is possible. The S and R in SR flip - flop means ‘SET’ and ‘RESET’
respectively. Hence it is also called Set -Reset flip - flop. The symbolic representation of the
SR Flip Flop is shown below.

SET S Q Output

RESET R Q’ Inverted Output

 Clock

The SR flip - flop works during the transition of clock pulse either from low -to - high or
from high - to - low (depending on the design) that is it can be either positive edge triggered-
leading edge or negative edge triggered-trailing edge .For a positive edge triggered SR flip
-flop, suppose, if S input is at high level (logic 1) and R input is at low level (logic 0) during
a low -to - high transition on clock pulse, then the SR flip - flop is said to be in SET state and
the output of the SR flip - flop is SET to1. For the same clock situation, if the R input is at
high level (logic 1) and S input is at low level (logic 0), then the SR flip -flop is said to be in
the RESET state and the output of the SR flip - flop is RESET to 0.

Flip Flop Output

State Q Q’

SET 1 0

RESET 0 1

Unclocked or simple SR flip – flops are same as SR Latches. The two types of unclocked SR
flip – flops are discussed below

2.Equipment and Devices used:

• Electronics project board
• Sequential Logic Tutor
• sn74LS00 Quad 2-input NAND gate
• sn74LS02 Quad 2-input NOR gate
• sn74LS76 Dual JK Master-slave flip flop
• 74LS11 - Triple 3-input AND gate
• LEDs and limiting resistors

4. Procedure And Experimental Results

4.1 S-R Latch

The S-R latch is the fundamental element in sequential logic design. When using static gates
as building blocks, it is the most fundamental simple SR latch, where S and R stand for set
and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit
is present on the output marked Q. While the S and R inputs are both low, feedback maintains
the Q and Q’ outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed
high while R (Reset) is held low, then the Q output is forced high, and stays high when S
returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced
low, and stays low when R returns to low. The McGraw-Hill Companies ,(2011)
 The circuits for the S-R latches were constructed shown in Fig.1 and Fig. 2 using the 7402
TTL and 7400 TTL packages. Their operations were verified using switches and LEDs,
carefully and their function tables were as presented below. 

Fig. 1. S-R latch with NOR gates. Fig. 2. S-R latch with NAND gates. Fig. 3: Symbol of S-R latch

The unclocked S-R flip-flop using NAND Gate -SR flip flop can be designed by cross
coupling of two NAND gates. It is an active low input SR flip -flop. The circuit of SR flip –
flop using NAND gates is shown in figure below ;

S’ Q

R’ Q’

Operation principle ;
a) When both the SET and RESET inputs are high, then the output remains in previous
state - it holds the previous data.
b) When SET input is HIGH and RESET input is LOW, then the flip flop will be in
RESET state. Because the low input of NAND gate with R input drives the other
NAND gate with 1, as its output is 1. So both the inputs of the NAND gate with S
input are 1. This will cause the output of the flip - flop to settle in RESET state.
c) When SET input is LOW and RESET input is HIGH, then the flip flop will be in SET
state. Because the low input of NAND gate with S input drives the other NAND gate
with 1, as its output is 1. So both the inputs of the NAND gate with R input are 1.
This will cause the output of the flip -flop to settle in SET state. (Odnulade E 2018)
d) When both the SET and RESET inputs are low, then the flip flop will be in an
undefined state. Because the low inputs of S and R, violates the rule of flip -flop that
the outputs should compliment to each other. So the flip flop is in an undefined state
(or forbidden state).

The table below summarizes above explained working of SR Flip Flop designed with the
NAND gates
 S’ R’ Q State

1 1 Previous State No change

1 0 0 Reset

0 1 1 Set

0 0 ? Forbidden

The unclocked S R flip-flop using NOR gate -SR flip flop can also be designed by cross
coupling of two NOR gates. It is an active high input SR flip – flop. The circuit of SR flip –
flop using NOR gates is shown in below figure.

S Q

R Q’

(ELECTRONIC TUTORIALS) The operation :

a) When both the SET and RESET inputs are low, then the output remains in previous
state that is. it holds the previous data
b) When SET input is low and RESET input is high, then the flip flop will be in RESET
state. Because the high input of NOR gate with R input drives the other NOR gate
with 0, as its output is 0. So both the inputs of the NOR gate with S input are 0. This
will cause the output of the flip - flop to settle in RESET state.
c) When SET input is high and RESET input is low, then the flip flop will be in SET
state. Because the low input of NOR gate with S input drives the other NOR gate with
1, as its output is 1. So both the inputs of the NOR gate with R input are 1. This will
cause the output of the flip flop to settle in SET state.
d) When both the SET and RESET inputs are high, then the flip flop will be in an
undefined state. Because the high inputs of S and R, violates the rule of flip flop that
the outputs should complement to each other. So the flip flop is in undefined state (or
forbidden state).
 The table below summarizes above explained working of SR Flip Flop designed with
the NOR gates.

S R Q State

0 0 Previous State No Change

0 1 0 Reset

1 0 1 Set

1 1 ? Forbidden

Even though simple SR flip - flops and simple SR latches are same, both the terms are used
in their respective contexts. The problem with simple SR flip - flops is that they are level
sensitive to the control signal which makes them transparent devices. In order to avoid this,
Gated or Clocked SR flip - flops are introduced (whenever the term SR flip – flop is used, it
usually refers to clocked SR flip – flop). Clock signal makes the device edge sensitive (and
hence no transparency).

SR NAND latch Output Waveforms

S’
R’

Q’

The R = S = 0 combination is called a restricted combination or a forbidden state because, as

both NAND gates then output 1s, it breaks the logical equation Q = not Q. The combination
is also inappropriate in circuits where both inputs may go high simultaneously (i.e. a
transition from restricted to keep). The output would lock at either 1 or 0 depending on the
propagation time relations between the gates (a race condition). In certain implementations, it
could also lead to longer ringings (damped oscillations) before the output settles, and thereby
result in undetermined values .

4.2 Clocked (Enabled) S-R Flip-Flop:

As shown in Fig. 3, a clocked S-R flip-flop has an additional clock input so that the S and R inputs are
active only when the clock is high.  When the clock goes low, the state of flip-flop is latched and
cannot change until the clock goes high again.  Therefore, the clocked S-R flip-flop is also called
“enabled” S-R flip-flop.

The circuits for the “enabled” S-R latches were constructed as shown in Fig.4 using the 7400 TTL
package. Switches and LEDs were used carefully to verify its operation and function table was
written as Table 1. 

Table 1

Inputs Outputs State

CLK S R Q
X 0 0 No change Previous State
Pulse 0 1 0 Reset
Pulse 1 0 1 Set
Pulse 1 1 - ------- Forbidden
 Fig. 4
The basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic
circuits but it suffers from two basic switching problems.
 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
 2. if Set or Reset change state while the enable (EN) input is high the correct
latching action may not occur
Then to overcome these two fundamental design problems with the SR flip-flop design,
the JK flip Flop was developed.

4.3 Flip flops

When both inputs to the S-R flip-flop in Fig. 1 were changed from logic 1 to logic 0 at the same time,
its outputs were unpredictable due to the race condition.  In logic circuit design, that condition was
avoided by making sure that 1's were not applied to both inputs simultaneously. That situation was
solved by modifying the S-R flip flop as shown in Fig. 5 and Fig. 6.

Fig. 5: JK FF with NOR gates. Fig. 6: JK FF with NAND gates. Fig. 7: Symbol of JK FF

The JK flip flop is a widely used Master-slave device that features in the design of many
sequential circuits. It is versatile in that it may be easily used as a toggle flipflop ( T-type) or
a D flipflop (D-type).

a) The circuits of Fig. 5 and Fig. 6 were connected the behaviour of the JK flipflops were
carefully verified. The characteristic tables were written as presented below.
JK Flip Flop with NOR Gates for fig 5

Clock J K Q Q’
pulse 0 0 Latch Latch
pulse 0 1 0 1
pulse 1 0 1 0
pulse 1 1 Toggle Toggle
X 0 0 Latch Latch
X 0 1 Latch Latch
X 1 0 Latch Latch
X 1 1 Latch Latch

JK Flip Flop with NOR Gates(without clock)

The Truth Table for the JK Function for Fig 6

same as Clock Input Output Description

for the
SR Latch

Clk J K Q Q

X 0 0 1 0

Memory
no change

X 0 0 0 1

‾↓ ̲ 0 1 1 0

Reset Q » 0

X 0 1 0 1

‾↓ ̲ 1 0 0 1 Set Q » 1
 X 1 0 1 0

‾↓ ̲ 1 1 0 1

toggle
Toggle
action

‾↓ ̲ 1 1 1 0

b) The behaviour of the JK flipflop (in the 7476 TTL package) were carefully verified and its
characteristic table was drawn (Function table 2) . The clock edge to which it responded as well
as the asynchronous operation of the preset and clear inputs were noted carefully. Toggle
switches were used for the inputs and LEDs on the outputs

Function Table 2

Inputs Outputs

PRE CLR ClK J K Q Q’

L H X X X H L

H L X X X L H

L L X X X H+ H+

H H Pulse L L Qo Qo’

H H Pulse H L H L

H H Pulse L H L H

H H Pulse H H Toggle Toggle

c) An inverter was connected between the J and K inputs and verified that the operation was that of
a D flip flop as shown by its characteristic table (Table 3).
The D-type Flip-flop

D Flip Flop Characteristic Table (define the behavior of flip-flops)

Table 3

D Q Q+ Operation

0 0 0 Reset

0 1 0 Reset

1 0 1 Set

1 1 1 Set

For the operation of the D flip flops which makes them so desirable for shift registers,
Whenever there is a change on the clock of a D flip flop (either rising or falling edge,
depending on the specifications of the flip flop). The data at the output “Q” becomes the
same data as the one at the input “D”. The Output “Q” of the flip flop will stay at that value
until the next clock cycle, where it will then change again to the value (High or low, 1 or 0) at
the input.

 
d) The J and K inputs were connected together and verifed that it operated as a T flip flop as
proved by its characteristic table.

Q’

T Flip flop characteristic table

Table 4
Input Outputs

T Qn Qn+1

0 0 0

0 1 1

1 0 1
 1 1 o

4.4 Shift Registers

The Shift Register is another type of sequential logic circuit that can be used for the storage
or the transfer of binary data. It is an n-bit register with provision for shifting its stored data
by one position at each clock pulse. The logical configuration of a shift register consists of a
chain of flip-flops connected in cascade, with the output of one flip-flop connected to the
input of the next flip-flop.  All flip-flops receive a common clock pulse which causes the shift
from one stage to the next. This sequential device loads the data present on its inputs and then
moves or “shifts” it to its output once every clock cycle, hence the name Shift Register. A
shift register basically consists of several single bit “D-Type Data Latches”, one for each data
bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so
that the output from one data latch becomes the input of the next latch and so on. Data bits
may be fed in or out of a shift register serially, that is one after the other from either the left
or the right direction, or all together at the same time in a parallel configuration (see Fig. 8).
Shift registers are classified according to three basic considerations: their method of data
handling (serial-in serial-out, serial-in parallel-out, and parallel-in serial-out), their direction
of data movement (shift right, shift left, and bidirectional), and their bit length.

Fig. 8

Types of Shift Registers

Shift registers are categorized into types majorly by their mode of operation, either serial or
parallel.
There are six (6) basic types of shift registers which are listed below although some of them
can be further divided based on direction of data flow either shift right or shift left.
1. Serial in – Serial out Shift Register (SISO)

According to Odnulade E  ( 2018)

2. Serial In – Parallel out shift Register (SIPO)

3. Parallel in – Parallel out Shift Register (PIPO)
4. Parallel in – Serial out Shift Register (PISO) 
5. Bidirectional Shift Registers
6. Counters

D Flip flop Truth Table

Odnulade (2018) Flip-flops can be connected in series to form shift registers in many ways. A
simple left-to-right shift register can be constructed from JK flip-flops configured as D flip-
flops as shown in Fig. 9. Note that an inverter was required only for the left-most flip-flop;

thereafter the Q output was available instead. The preset inputs were tied to logic HI. A
low frequency clock input provided by the function generator was used for the experiment so
that you can observe the register output patterns Q3Q2Q1Q0 on LEDs. Toggle switches were
used to provide the clear input as well as the serial input. Note was taken about the fact that

the JK flip-flop in the editor did not contain the output Q , but it could be obtained by

inverting Q (attached an inverter to Q and used the output of the inverter as Q ).

Fig. 9: 4-bit shift register

Two 7476 dual JK flip-flops (or the Sequential Logic Tutor) were used to connect a serial-in,
parallel-out shift register as shown in Fig. 9.  L1–L4  were connected to four LEDs, SW1
and  SW 2  to switches, and CLK to a pulser. Initially,   SW 2 was used to logic
1.  Switch  SW 2 was at logic 1 cleared all flip-flops.  Then SW1was set to logic 1
and  SW 2 to logic 0.  The pulser button was pushed several times to allow more logic 1 to
be shifted into the shift register.  SW1was changed to logic 0 and repeated the experiment
again.

4.5 Counters
A counter is a sequential logic circuit that goes through a prescribed sequence of states upon
the application of input pulses.  The prescribed sequence can be a binary sequence or any
other sequence.  A counter that goes through 2N (N is the number of flip-flops in the series)
states is called a binary counter.  The modulus of a counter is the number of different states it
is allowed to have.  Counter modulus is normally 2N unless controlled by a feedback circuit
which limits the number of possible states (an example being the decimal counter).  Counters
are very widely used in almost all computers and other digital electronic systems.  There are
two major categories of counters: asynchronous counters and synchronous counters.
 
Asynchronous Counters
Counters arranged so that the output of one flip-flop generates the clock input of the next
higher stage are generally called asynchronous counters (or ripple counter).  In other words,
in asynchronous counters, the CLK inputs of all flip-flops (except the first one) are triggered
not by the incoming pulses but rather by the transition that occurs in other flip-
flops.  Therefore, the change of state of a particular flip-flop is dependent upon the present
state of other flip-flops.  Fig. 10 shows a count-up ripple counter.  When a transition from,
say, 0111 to 1000 occurs, the one-to-zero transition of the low-order three bits ripples from
bit to bit.  Since each flip-flop has a non-zero propagation delay, ripple counters are relatively
slow.  Therefore, an upper limit on the number of flip-flops in the flip-flop chain ought to be
imposed.

Fig. 10: 4-bit ripple counter.

 
Basic Data Movement Through A Shift Register

Clock Pulse
QA QB QC QD
No

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

 Synchronous Counters
Synchronous counters eliminate the cumulative flip-flop delay seen in ripple counter.  Each
flip-flop is clocked by the same clock signal.  Each gate selectively controls when each more
significant bit flip-flop is to change state (t oggle) on the next clock transition.  Such control
(enable) can be realized by setting, for example, the J and K inputs of a J-K flip-flop.   Because of this
control, the addition of a common clock will synchronize data transfer and all flip-flops will change
state simultaneously.  The important feature of a synchronous counter is that the transitions of the
individual flip-flops are synchronized to a master clock signal.
J-K flip-flops are normally used in the synchronous counters due to the enabling (controlling) feature
of the J and K inputs.  There are two basic schemes for generating the J and K inputs.  One of them is
illustrated in the four-bit binary counter shown in Fig. 11.  Notice that the information to the J-K
inputs is formed in a parallel fashion.  The counter is accordingly termed as synchronous parallel
counter.  In the parallel scheme the number of inputs to each AND gate increases linearly with the
number of stages.  For this added expense one gets the fastest possible synchronous counting circuit.
 Fig. 11: 4-bit synchronous parallel counter.

 
If the J-K input information is formed from the output of the AND gate in the previous stage,
one has a synchronous serial counter.  Although the serial scheme is slower than the parallel
scheme, the number of inputs to the AND gate per stage is constant in the serial case (two
inputs per stage).

The count-up ripple counter was connected as shown in Fig. 10 using two 74LS76 chips Data
switch  SW 1 was set from logic 0 to logic 1 (cleared all flip-flops).   CLK was then
connected to a pulse generator (J-K flip-flops in 74LS76 were negative edge triggered) and
started counting by pushing the pulser button.   The process was Continue and the output of
each transition in a truth table was recorded.  It counted correctly as shown by the timing
diagram .
 We converted the count-up ripple counter to a count-down ripple counter by connecting the
clock of the flip-flops to   Q   instead of Q (the LEDs were still connected to Q).  
Modification were made and the try out the Ripple counter Timing Diagram was as
presented below.

Asynchronous Ripple counter Timing Diagram

Clk Pulse Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
Repeat

The 4-bit synchronous parallel counter was connected as shown in Fig. 11.  The same
procedures were repeated in the ripple counter experiment.
 
Conclusion
In accordance with Morris L. and John R. (1971). In the practical, the introduction and the
construction of RS latches (using NAND and NOR gates), helped the student to attain an
understanding about how memory was developed in logic circuits. Commercially available
JK flip flops were used to construct shift registers and counters. In the asynchronous binary
counter practical, it was discovered that the output of one counter stage was connected directly
to the clock input of the next counter stage and so on along the chain.
The result of that was the fact that the asynchronous counter suffers from what is known as
“Propagation Delay” in which the timing signal was delayed a fraction through each flip-flop.
However, with the synchronous counter, the external clock signal was connected to the clock
input of each individual flip-flop within the counter so that all of the flip-flops are clocked
together simultaneously (in parallel) at the same time giving a fixed time relationship. In
other words, changes in the output occurred in “synchronisation” with the clock signal.
The result of the synchronisation was that all the individual output bits were changing state at
exactly the same time in response to the common clock signal with no ripple effect and
therefore, no propagation delay (Odnulade E 2018) .

Applications of Shift registers

Shift registers are used in a lot of applications some of which are;

1. Parallel to serial conversion- where they are used to reduce the number of wires, or lines
needed for communication between two devices, since serial communication generally
require just two wires compared to parallel which depends on the number of bits being sent.
2. Input and output microcontrollers- In modern day electronics, microcontrollers IO pins are
referred to as real estates and one needs as much as possible for certain application like
turning on 100 leds or reading 100 reed switches with something like an Arduino or the
Atmeg328p microcontroller. For example, a serial to parallel shift register can be used to
control 8 LEDs, using just three of the microcontrollers IO pins.

3. They are used in state registers which are used in sequential devices- Like a finite memory
machine, the next state of the device is always determined by shifting and inserting a new
data into the previous position.
4. One other main application is found in Time delays- Shift registers are used for time delay
in devices, with the time being adjusted by the clock, or increased by cascading shift registers
or reduced by taking the output from a lower significant bit.
The time delay is usually calculated using the formula;
t = N * (1 / fc)                                                                    
 N is the number of flip flop stage at which the output is taken, Fc is the frequency of the
clock signal and t which is the value being determined is the amount of time for which the
output will be delayed.
When selecting a shift register for a particular task because of the wide range and type its
important to select one that matches your particular need, considering things like, the mode of
operation, the bit size (number of flip flops), right or left or bidirectional etc.
 
Some of the most popular shift registers are;
a) 74HC 194 4-bit bidirectional universal shift register
b) 74HC 198 8-bit bidirectional universal shift register
c) 74HC595 Serial-In-Parallel-Out shift register
d) 74HC165 Parallel-In-Serial-Out shift register
e) IC 74291 4-bit universal shift register, binary up/down counter, synchronous.
f) IC 74395 4-bit universal shift register with three-state outputs.
g) IC 74498 8-bit bidirectional shift register with parallel inputs and three-state outputs.
h) IC 74671 4-bit bidirectional shift register.

References;
Digi-Key ELECTRONICS 2018

Floyd, Thomas L. (2010). Electric Circuit Fundamentals. Prentice Hall, Boston. ISBN:
9780135105856

Halkais, Christos, C. and Millman, Jacob (1985). Integrated electronics: Analog and digital
circuits and systems. McGraw-Hill, Tokyo

https://www.electronics-tutorials.ws/counter/count_3.htm ELECRONIC TUTORIALS

Odnulade Emmanuel Jan 15, 2018 Shift Registers : Introduction , Types and Applications

The McGraw-Hill Companies ,(2011) .Digital Principles and Applications, Special Indian
Edition 2011

Robert L. Morris and John R. Miller (1971). TTL Integrated Circuits. Prepared by the Texas
Instruments Incorporated .

Schuler, C A. (1985). Electronics: Principles and Applications. 2 nd Ed. McGraw-Hill Book

Co., ISBN: 9780071315531
 
Appendix A

7400 Quad 2-input Logic NAND Gate 7402 Quad 2-input Logic NOR Gate

7476 Dual JK Master Slave Flip flop with Preset and clear 74LS11 - Triple 3-input AND gate
 Applications

SR flip – flops are very simple but are not widely used in practical circuits because of their
illegal state where both S and R are high (S = R = 1). But they are used in switching circuits
as they provide simple switching function (between Set and Reset). One such application is a
Switch de – bounce circuit. The SR flip – flops are used to eliminate mechanical bounce of
switches in digital circuits.

Synchronous Counter Summary

Then to summarise some of the main points about Synchronous Counters:
 Synchronous Counters can be made from Toggle or D-type flip-flops.
 Synchronous counters are easier to design than asynchronous counters.
 They are called synchronous counters because the clock input of the flip-flops
are all clocked together at the same time with the same clock signal.
 Due to this common clock pulse all output states switch or change simultaneously.
 With all clock inputs wired together there is no inherent propagation delay.
 Synchronous counters are sometimes called parallel counters as the clock is fed in
parallel to all flip-flops.
 The inherent memory circuit keeps track of the counters present state.
 The count sequence is controlled using logic gates.
 Overall faster operation may be achieved compared to Asynchronous counters.