1.5°C Smbus Temperature Sensor in Miniature Sot-23: Product Features
1.5°C Smbus Temperature Sensor in Miniature Sot-23: Product Features
1.5°C Smbus Temperature Sensor in Miniature Sot-23: Product Features
1.5°C SMBus
Temperature Sensor in
Miniature SOT-23
EMC1001
Digital Mux
THERM
Datasheet
Order Number(s):
EMC1001-AFZQ-TR for 6 pin, SOT 23 Lead-Free RoHS compliant package
(tape and reel)
EMC1001-1-AFZQ-TR for 6 pin, SOT 23 Lead-Free RoHS compliant package
(alternate addresses, tape and reel)
See Table 1.2, "SMBus Address Configuration Information," on page 3
Reel size is 8,000 pieces.
Datasheet
ADDR/THERM 1 6 SMDATA
GND 2 5 ALERT/THERM2
VDD 3 4 SMCLK
ADDR/THERM 1 Logic output that can be used to turn on/off a fan or throttle a CPU clock
in the event of an over-temperature condition. This is an open-drain
output. This pin is sampled following power up and the value of the pull
up resistor determines the SMBus slave address per Table 1.2.Total
capacitance on this pin must not exceed 100 pF, and the pull-up resistor
must be connected to the same supply voltage as VDD
GND 2 Ground.
ALERT/THERM2 5 Logic output used as interrupt, SMBus alert or as a second THERM output.
This is an open-drain output.
EMC1001 7.5kΩ ±5% Note 1.1, Note 1.2 1001 000b 6-Lead SOT-23
12kΩ ±5% Note 1.2 1001 001b 6-Lead SOT-23
20kΩ ±5% Note 1.2 0111 000b 6-Lead SOT-23
33kΩ ±5% Note 1.2 0111 001b 6-Lead SOT-23
EMC1001-1 7.5kΩ ±5% Note 1.1, Note 1.2 1001 010b 6-Lead SOT-23
12kΩ ±5% Note 1.2 1001 011b 6-Lead SOT-23
20kΩ ±5% Note 1.2 0111 010b 6-Lead SOT-23
33kΩ ±5% Note 1.2 0111 011b 6-Lead SOT-23
Note 1.1 This value must be greater than 1kΩ ±5% and less than or equal to 7.5kΩ ±5%.
Note 1.2 The pull-up resistor must be connected to VDD (pin 1), and the total capacitance on this
pin must be less than 100pF.
Datasheet
Note: Stresses above those listed could cause damage to the device. This is a stress rating only
and functional operation of the device at any other condition above those indicated in the
operation sections of this specification is not implied. When powering this device from
laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be
exceeded or device failure can result. Some power supplies exhibit voltage spikes on their
outputs when the AC power is switched on or off. In addition, voltage transients on the AC
power line may appear on the DC output. If this possibility exists, it is suggested that a clamp
circuit be used.
Datasheet
VDD=3.0V to 3.6V, TA= -25°C to +125°C, Typical values at TA = 27°C unless otherwise noted
DC Power
Temperature Measurement
±1 ±3 °C -25°C≤TA≤125°C
Resolution 0.25 °C
Conversion Time 26 ms
Voltage Tolerance
Hysteresis 500 mV
Input Capacitance 5 pF
SMBus Timing
Spike Suppression 50 ns
Datasheet
VDD=3.0V to 3.6V, TA= -25°C to +125°C, Typical values at TA = 27°C unless otherwise noted
Note 2.1 300nS rise time max is required for 400kHz bus operation. For lower clock frequencies,
the maximum rise time is (0.1/FSMB)+50nS
Datasheet
A host controller, such as an SMSC I/O controller, communicates with the EMC1001 via the two wire
serial interface named SMBus. The SMBus interface is used to read and write registers in the
EMC1001, which is a slave-only device. A detailed timing diagram is shown in Figure 3.1.
T LO W T H IG H
T H D :STA T SU :S TO
TR TF
SM CLK
T H D :S TA T H D :D A T T S U :D AT T SU :S TA
SM DA TA
TBUF
1 7 1 1 8 1 8 1 1
1 7 1 1 8 1 1 7 1 1 8 1 1
Bits: 1 7 1 1 8 1 1
Datasheet
Bits: 1 7 1 1 8 1 1
ALERT
RESPONSE EMC1001 SLAVE
FIELD: START ADDRESS RD ACK ADDRESS NACK STOP
Bits: 1 7 1 1 8 1 1
Datasheet
The EMC1001 is an SMBus temperature that monitors a single temperature zone. Thermal
management is performed in cooperation with a host device. The host reads the temperature data from
the EMC1001 and takes appropriate action such as controlling fan speed or processor clock frequency.
The EMC1001 has programmable temperature limit registers that define a safe operating window. After
the host has configured the temperature limits, the EMC1001 can operate as a free-running
independent watchdog to warn the host of temperature hot spots without requiring the host to poll the
device. The ADDR/THERM output can be used to control a fan without host intervention.
EMC1001 Host
SMCLK
SMDATA SMBus
Internal Interface
Diode ALERT/THERM2
ADDR/THERM Fan
Driver
where:
k = Boltzmann’s constant
ηkT ⎛I ⎞
ΔVBE = VBE _ HIGH − VBE _ LOW = ln⎜⎜ HIGH ⎟⎟ T = absolute temperature in Kelvin
q ⎝ I LOW ⎠ q = electron charge
η = diode ideality factor
Datasheet
VDD
The advantages of this architecture over Nyquist rate FLASH or SAR converters are superb linearity
and inherent noise immunity. The linearity can be directly attributed to the delta-sigma ADC single-bit
comparator while the noise immunity is achieved by the ~20ms integration time which translates to
50Hz input noise bandwidth.
VALID RANGE
–40°C TO 125°C
TEMPERATURE TWO’S COMPLEMENT
-0.25°C 1111 1111 11 Note 4.1
0.0°C 0000 0000 00
+0.25°C 0000 0000 01
+0.50°C 0000 0000 10
+0.75°C 0000 0000 11
+1°C 0000 0001 00
Note 4.1 Temperature measurement returns 1100 0000 00 for all temperatures ≤ -64.00°C
Note 4.2 Temperature measurement returns 0111 1111 11 for all temperatures ≥ +127.75°C
The eight most significant bits are stored in the Temperature Value High Byte register and the two least
significant bits stored in the Temperature Value Low Byte register as outlined in Table 4.2. The six LSB
positions of the Temperature Value Low Byte register always read zero. In Table 4.2, the upper case
Datasheet
“B” shows the bit position of a 16-bit word created by concatenating the High Byte and Low Byte, and
the lower case “b” shows the bit position in the 10-bit value.
As described in the SMBus specification, an SMBus slave may inform the SMBus master that it wants
to talk by asserting the SMBALERT# signal. One or more ALERT outputs can be hardwired together
as a wired-or bus to a common input.
The ALERT/THERM2 pin resets when the EMC1001 responds to an alert response address (ARA=0001
100) sent by the host, and if the out of limit condition no longer exists, but it does not reset if the error
condition remains. The ALERT/THERM2 pin can be masked so that it will not assert in the event of an
out of limit temperature measurement, except when it is configured as a second THERM pin.
Logic
Temp
Level
Temperature High Limit
SMBus ARA
Temperature Low Limit
Logic High
ALERT/THERM2
Time
The ALERT/THERM2 pin can be configured as a second THERM pin that asserts when the temperature
measurement exceeds the Temperature High Limit value. In this mode, the output will not de-assert
until the temerature drops below the Temperature High Limit minus the THERM Hysteresis value.
When the ADDR/THERM pin is asserted, it will not de-assert until the temperature drops below the
THERM limit minus the THERM hysteresis value.
Datasheet
Logic
Temp
THERM
Level
Hysteresis
THERM Limit
Logic High
THERM
Time
REGISTER
ADDRESS
(HEX) R/W REGISTER NAME POWER-ON DEFAULT
00 R Temperature Value High Byte 0000 0000
01 R Status undefined
02 R Temperature Value Low Byte 0000 0000
03 R/W Configuration 0000 0000
04 R/W Conversion Rate 0000 0100
05 R/W Temperature High Limit High Byte 0101 0101 (85°C)
06 R/W Temperature High Limit Low Byte 0000 0000
07 R/W Temperature Low Limit High Byte 0000 0000 (0°C)
08 R/W Temperature Low Limit Low Byte 0000 0000
0F W One-Shot N/A
20 R/W THERM Limit 0101 0101 (85°C)
21 R/W THERM Hysteresis 0000 1010 (10°C)
22 R/W SMBus Timeout Enable 0000 0001
FD R Product ID Register 0000 0000 (EMC1001)
0000 0001 (EMC1001-1)
FE R Manufacture ID 0101 1101
FF R Revision Number 0000 0011 Note 4.3
Datasheet
Note 4.3 Revision number may change. Please obtain the latest version of this document from the
SMSC web site.
At device power-up, the default values are stored in all registers. A power-on-reset is initiated when
power is first applied to the part and the VDD supply exceeds the POR threshold. Reads of undefined
registers will return 00h and writes to undefined registers will be ignored.
The EMC1001 uses an interlock mechanism that locks the low byte value when the high byte register
is read. This prevents updates to the low byte register between high byte and low byte reads. This
interlock mechanism requires that the high byte register always be read prior to reading the low byte
register.
STATUS REGISTER
4 Reserved
3 Reserved
2 Reserved
1 Reserved
Bit 7 indicates that the ADC is busy converting a value. Bits 6 and 5 indicate that the temperature
measurement is above or below the limits respectively. Bit 0 indicates that the measured temperature
has exceeded the THERM limit. When bit 0 goes high the ADDR/THERM output will be asserted.
Each bit is cleared individually when the status register is read, provided that the error condition for
that bit no longer exists. The ALERT/THERM2 output is latched and will not be reset until the host has
responded with an alert response address (ARA=0001 100). The ALERT/THERM2 output will not reset
if the status register has not been cleared.
Datasheet
CONFIGURATION REGISTER
4–0 Reserved 0
Bit 7 is used to mask the ALERT/THERM2 signal. When this bit is set to 0, any out of limit condition
will assert ALERT/THERM2. This bit is ignored if the ALERT/THERM2 pin is configured as THERM2 signal
by bit 5.
Bit 6 initiates ADC conversions. When this bit is low, the ADC will convert temperatures in a
continuous mode. When this bit is high, the ADC will be in standby mode, thus reducing supply
current significantly though the SMBus will still be active. If bit 6 is 1 and the one-shot register is
written to, the ADC will execute a temperature measurement and then return to standby mode.
Bit 5 sets the ALERT/THERM2 pin to act as either an SMBALERT# signal or as the THERM2 signal. If
bit 5 is set to 1 the ALERT/THERM2 pin acts as the THERM2 signal and bit 7 is ignored.
CONVERSION RATE
VALUE CONVERSIONS/SECOND TYPICAL QUIESCENT CURRENT (μA)
00h 0.0625 36
01h 0.125 37
02h 0.25 38
03h 0.5 40
04h 1 44
05h 2 54
06h 4 71
07h 8 109
08h 16 182
09h 32 326
0Ah to FFh Reserved
Datasheet
The temperature low limit (TL) is a 10-bit value that is set by the Temperature Low Limit High Byte
register and the Temperature Low Limit Low Byte register as shown in Table 4.2 on page 11.
The limits are compared to the temperature measurement results (TINT) and have been exceeded if
(TINT ≤ TL or TINT > TH). If either limit is exceeded then the appropriate bit is set high in the status
register and the ALERT/THERM2 output will respond as described in Section 4.3 on page 11.
The THERM limit (TTH) is a single byte value set by the THERM Limit register. Exceeding the THERM
limit asserts the ADDR / THERM signal as described in Section 4.4 on page 11. When the
ALERT/THERM2 pin is configured as THERM2, then exceeding the high limit asserts this pin.
Datasheet
3 E1 E
1 2 3
INDEX AREA
(D/2 x E1/2) e 5X b 2 4 c 4
5
TOP VIEW END VIEW
DATASHEET
H
16
C
A2 A GAUGE PLANE
0.25
NOTES:
SEATING PLANE 1. "N" IS THE TOTAL NUMBER OF LEADS .
A1 2. TRUE POSITION SPREAD TOLERANCE IS ± 0.10mm AT MAXIMUM MATERIAL CONDITION.
L 0
3. PACKAGE BODY DIMENSION "D" DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR
ccc C GATE BURRS. MAXIMUM MOLD FLASH, PROTRUSIONS OR GATE BURRS IS 0.25 mm PER
L1
END. DIMENSION "E1" DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
MAXIMUM INTERLEAD FLASH OR PROTRUSION IS 0.25 mm PER SIDE. "D1" & "E1"
SIDE VIEW DETAIL "A" (SCALE: 2/1) DIMENSIONS ARE DETERMINED AT DATUM PLANE "H".
4. DIMENSIONS "b" & "c" APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 TO
0.15 mm FROM THE LEAD TIP.
5. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
INDEX AREA INDICATED (SEE TOP VIEW).
6. FIVE LEAD PACKAGE IS A VERSION OF 6 LEAD PACKAGE, WHERE LEAD #5 HAS BEEN
REMOVED FROM 6 LEAD PACKAGE.
Figure 5.1 EMC1001, 6 Pin SOT Package Outline; 1.6mm Body Width, 0.95mm Pitch