AT25SF321: Features
AT25SF321: Features
AT25SF321: Features
Features
Single 2.5V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual and Quad Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Blocks via WP Pin
3 Protected Programmable Security Register Pages
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
0.7ms Typical Page Program (256 Bytes) Time
70ms Typical 4-Kbyte Block Erase Time
300ms Typical 32-Kbyte Block Erase Time
600ms Typical 64-Kbyte Block Erase Time
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
2µA Deep Power-Down Current (Typical)
10µA Standby current (Typical)
4mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil and 208-mil)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
Die in Wafer Form
DS-25SF321–047F–8/2017
Description
The Adesto® AT25SF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM
for execution. The flexible erase architecture of the AT25SF321 is ideal for data storage as well, eliminating the need for
additional data storage devices.
The erase block sizes of the AT25SF321 have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because
certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and
unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments to be added while still maintaining
the same overall device density.
The device also contains three pages of Security Register that can be used for purposes such as unique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register
pages can be individually locked.
Asserted
Symbol Name and Function State Type
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down
mode), and the SO pin will be in a high-impedance state. When the device is deselected,
data will not be accepted on the SI pin.
CS Low Input
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI pin
SCK - Input
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data
input including command and address sequences. Data on the SI pin is always latched in on
the rising edge of SCK.
With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin
(I/O0) in conjunction with other pins to allow two or four bits of data on (I/O3-0) to be clocked
SI (I/O0) in on every falling edge of SCK - Input/Output
To maintain consistency with the SPI nomenclature, the SI (I/O0) pin will be referenced as
the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it
will be referenced as I/O0
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
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Table 1-1. Pin Descriptions (Continued)
Asserted
Symbol Name and Function State Type
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in
conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on every
falling edge of SCK
SO (I/O1) - Input/Output
To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as
the SO pin unless specifically addressing the Dual-I/O modes in which case it will be
referenced as I/O1
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
WRITE PROTECT: The WP pin controls the hardware locking feature of the device.
With the Quad-Input Byte/Page Program command, the WP pin becomes an input pin (I/O2)
and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every rising
edge of SCK. With the Quad-Output Read commands, the WP Pin becomes an output pin
(I/O2) in conjunction with other pins to allow four bits of data on (I/O33-0) to be clocked in on
WP
every falling edge of SCK.
(I/O2) - Input/Output
To maintain consistency with the SPI nomenclature, the WP (I/O2) pin will be referenced as
the WP pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O2
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to VCC whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold Function” on page 34 for additional details on the Hold operation.
HOLD With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin
(I/O3) (I/O3) and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every
- Input/Output
rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin becomes an
output pin (I/O3) in conjunction with other pins to allow four bits of data on (I/O33-0) to be
clocked in on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the HOLD (I/O3) pin will be referenced
as the HOLD pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O3
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to VCC
whenever possible.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
VCC Operations at invalid VCC voltages may produce spurious results and should not be - Power
attempted.
GROUND: The ground reference for the power supply. GND should be connected to the
GND - Power
system ground.
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Figure 1-1. 8-SOIC (Top View) Figure 1-2. 8-UDFN (Top View)
CS 1 8 VCC
CS 1 8 VCC
SO 2 7 HOLD
SO 2 7 HOLD
WP 3 6 SCK
WP 3 6 SCK
GND 4 5 SI
GND 4 5 SI
2. Block Diagram
Figure 2-1. Block Diagram
SRAM
Data Buffer
SCK
Interface
Control
SI (I/O0) And
Logic Y-Decoder Y-Gating
SO (I/O1)
Address Latch
Flash
Memory
WP (I/O2) X-Decoder Array
HOLD (I/O3)
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
3. Memory Array
To provide the greatest flexibility, the memory array of the AT25SF321 can be erased in four levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
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Figure 3-1. Memory Architecture Diagram
Block Erase Detail Page Program Detail
•••
•••
4KB 3E6FFFh – 3E6000h
4KB 3E5FFFh – 3E5000h
4KB 3E4FFFh – 3E4000h 256 Bytes 0017FFh – 001700h
32KB
4KB 3E3FFFh – 3E3000h 256 Bytes 0016FFh – 001600h
4KB 3E2FFFh – 3E2000h 256 Bytes 0015FFh – 001500h
4KB 3E1FFFh – 3E1000h 256 Bytes 0014FFh – 001400h
4KB 3E0FFFh – 3E0000h 256 Bytes 0013FFh – 001300h
256 Bytes 0013FFh – 001300h
•••
•••
•••
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4. Device Operation
The AT25SF321 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI
Master. The SPI Master communicates with the AT25SF321 via the SPI bus which is comprised of four signal lines: Chip
Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25SF321
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
SCK
SI MSB LSB
SO MSB LSB
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Table 5-1. Command Listing
Read Commands
1111 1111
Continuous Read Mode Reset - Dual FFFFh Up to 104 MHz 0 0 0 6.6
1111 1111
Continuous Read Mode Reset - Quad FFh 1111 1111 Up to 104 MHz 0 0 0 6.6
Block Erase (32 Kbytes) 52h 0101 0010 Up to 104 MHz 3 0 0 7.2
Byte/Page Program (1 to 256 Bytes) 02h 0000 0010 Up to 104 MHz 3 0 1+ 7.1
Protection Commands
Security Commands
Erase Security Register Page 44h 0100 0100 Up to 104 MHz 3 0 0 9.1
Program Security Register Page 42h 0100 0010 Up to 104 MHz 3 0 1+ 9.2
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Table 5-1. Command Listing
Miscellaneous Commands
Resume from Deep Power-Down ABh 1010 1011 Up to 104 MHz 0 0 0 11.4
6. Read Commands
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Figure 6-2. Read Array - 0Bh Opcode
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CS
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
OUTPUT OUTPUT
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6,6,2 0 0 1 1 1 0 1 1 A A A A A A A A A X X X X X X X X D6 D4 D2 D0 D6 D4 D2 D0 D6 D4
MSB MSB MSB
HI
GH-
IMPEDANCE
SO D7 D5 D3 D1 D7 D5 D3 D1 D7 D5
MSB MSB MSB
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6.3 Dual-I/O Read Array (BBh)
The Dual-I/O Read Array command is similar to the Dual-Output Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address
with two bits of address on each clock and two bits of data on every clock cycle.
The Dual-I/O Read Array command can be used at any clock frequency, up to the maximum specified by fRDDO. To
perform the Dual-I/O Read Array operation, the CS pin must first be asserted and then the opcode BBh must be clocked
into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location
of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also be
clocked into the device.
After the three address bytes and the mode byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is always output
on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same
data byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO
and SI pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.
When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the SO and SI pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-4. Dual I/O Read Array (Initial command or previous M5, M4≠1,0)
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 19 20 21 22 23 24 25 26 27
SCK
Address Bits Address Bits
Opcode A23-A16 A15-A8 A7-A0 M7-M0 Byte 1 Byte 2
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Figure 6-5. Dual-I/O Read Array (Previous command set M5, M4 = 1,0)
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SCK
Address Bits Address Bits
A23-A16 A15-A8 A7-A0 M7-M0 Byte 1 Byte 2
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Figure 6-6. Quad-Output Read Array
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
Opcode Address Bits A23-A0 Don't Care OUT OUT OUT OUT OUT
I/O0 0 1 1 0 1 0 1 1 A A A A A A A A A X X X X X X X X D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
06% 06% 06%
(SI)
High-impedance
I/O1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
(SO)
High-impedance
I/O2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
(WP)
High-impedance
I/O3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
MSB MSB MSB MSB MSB
(HOLD)
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Figure 6-7. Quad-I/O Read Array (Initial command or previous M5, M4 ≠ 1,0)
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Figure 6-8. Quad I/O Read Array with Continuous Read Mode (Previous Command Set M5-4 =1,0)
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
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The "Continuous Read Mode" bits M7-0 are set by the Dual/Quad I/O Read Array commands. M5-4 are used to control
whether the 8-bit SPI instruction code (BBh or EBh) is needed or not for the next instruction. When M5-4 = (1,0), the next
instruction will be treated the same as the current Dual/Quad I/O Read Array command without needing the 8-bit
instruction code. When M5-4 do not equal (1,0), the device returns to normal SPI instruction mode, in which all
instructions can be accepted. M7-6 and M3-0 are reserved bits for future use; either 0 or 1 values can be used.
See Figure 6-9, the Continuous Read Mode Reset instruction (FFh or FFFFh) can be used to set M4 = 1, thus the device
will release the Continuous Read Mode and return to normal SPI operation.
To reset Continuous Read Mode during Quad I/O operation, only eight clocks are needed to shift in instruction FFh. To
reset Continuous Read Mode during Dual I/O operation, sixteen clocks are needed to shift in instruction FFFFh.
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that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page.
For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then
the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be
programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will not be
programmed and will remain in the erased state (FFh). In addition, if more than 256 bytes of data are sent to the device,
then only the last 256 bytes sent will be latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes
sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not
be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and
should take place in a time of tPP or tBP if only programming a single byte.
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is
deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device
will abort the operation and no data will be programmed into the memory array. In addition, if the memory is in the
protected state (see “Non-Volatile Protection” on page 21), then the Byte/Page Program command will not be executed,
and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will
be reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete
byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or because the memory location to be
programmed is protected.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster
throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to determine if the
data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status
Register will be reset back to the logical “0” state.
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AT25SF321 15
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7.2 Block Erase (20h, 52h, or D8h)
A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three
different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used
for a 32-Kbyte erase, or D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write
Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1”
state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the
4- or 32- or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored.
When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-
timed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the
device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values can be either a
logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored by the device. For a 64-Kbyte erase, address
bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must
be deasserted on an byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase
operation will be performed.
If the memory is in the protected state, then the Block Erase command will not be executed, and the device will return to
the idle state once the CS pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete
address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the
region to be erased is protected.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to
determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status
Register will be reset back to the logical “0” state.
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AT25SF321 16
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the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase
the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on an byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if the memory
array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle
state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state
if the CS pin is deasserted on uneven byte boundaries or if the memory is in the protected state.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tCHPE time to
determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status
Register will be reset back to the logical “0” state.
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AT25SF321 17
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internal address counter increments and crosses into the suspended area, the device will then start outputting undefined
data until the internal address counter crosses to an unsuspended area.
A program operation is not allowed to a block that has been erase suspended. If a program operation is attempted to an
erase suspended block, then the program operation will abort and the WEL bit in the Status Register will be reset back to
a logical "0" state. Likewise, an erase operation is not allowed to a block that included the page that has been program
suspended. If attempted, the erase operation will abort and the WEL bit in the Status Register will be reset to a logical "0"
state.
If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a Write
Status Register operation, then the device will simply ignore the opcode and no operation will be performed. The state of
the WEL bit in the Status Register will not be affected.
Table 7-1. Operations Allowed and Not Allowed During a Program/Erase Suspend Command
Read Commands
Read Array (03h, 0Bh, 3Bh, BBh, 6Bh, EBh) Allowed (1) Allowed(1)
Continuous Read Reset (FFh) Allowed(1) Allowed(1)
Program and Erase Commands
Block Erase (20h, 52h, D8h) Not Allowed Not Allowed
Chip Erase (C7h, 60h) Not Allowed Not Allowed
Byte/Page Program (02h) Not Allowed Allowed(1)
Program/Erase Suspend (75h) Not Allowed Not Allowed
Program/Erase Resume (7Ah) Allowed Allowed
Protection Commands
Write Enable (06h) Allowed Allowed
Write Disable (04h) Allowed Allowed
Security Commands
Erase Security Register Page (44h) Not Allowed Not Allowed
Program Security Register Page (42h) Not Allowed Not Allowed
Read Security Register Page (48h) Allowed Allowed
Status Register Commands
Read Status Register (05h, 35h) Allowed Allowed
Write Status Register (01h) Not Allowed Not Allowed
Volatile Write Enable Status Register (50h) Not Allowed Not Allowed
Miscellaneous Commands
Read Manufacturer and Device ID (9Fh) Allowed Allowed
Read ID (90h) Allowed Allowed
Deep Power-Down (B9h) Not Allowed Not Allowed
(2)
Resume from Deep Power-Down (ABh) Allowed Allowed(2)
1. Allowed for all 64K-byte blocks other than the one currently suspended.
2. Allowed for reading Device ID.
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Figure 7-5. Program/Erase Suspend
CS
0 1 2 3 4 5 6 7
SCK
OPCODE
SI 0 1 1 1 0 1 0 1
MSB
HI
GH-
IMPEDANCE
SO
0 1 2 3 4 5 6 7
SCK
OPCODE
SI 0 1 1 1 1 0 1 0
MSB
HI
GH-
IMPEDANCE
SO
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8. Protection Commands and Features
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8.3 Non-Volatile Protection
The device can be software protected against erroneous or malicious program or erase operations by utilizing the Non-
Volatile Protection feature of the device. Non-Volatile Protection can be enabled or disabled by using the Write Status
Register command to change the value of the Protection (CMP, SEC, TB, BP2, BP1, BP0) bits in the Status Register.
The following table outlines the states of the Protection bits and the associated protection area
.
Table 8-1. Memory Array with CMP=0
X X 0 0 0 None None
X X 1 1 1 000000h-3FFFFFh ALL
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Table 8-2. Memory Array Protection with CMP=1
X X 0 0 0 000000h-3FFFFFh All
X X 1 1 1 NONE NONE
As a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the Protection can be
locked from updates by using the WP pin (see “Protected States and the Write Protect Pin” on page 22 for more details).
AT25SF321 22
DS-25SF321–047F–8/2017
9. Security Register Commands
The device contains three extra pages called Security Registers that can be used for purposes such as unique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The Security Registers are
independent of the main Flash memory.
Each page of the Security Register can be erased and programmed independently. Each page can also be
independently locked to prevent further changes.
Table 9-1. Security Register Addresses for Erase Security Register Page Command
&6
0 1 2 3 4 5 6 7
6&.
OPCODE %,7$''5(66
6, $ $ $ $ $
MSB
AT25SF321 23
DS-25SF321–047F–8/2017
9.2 Program Security Registers (42h)
The Program Security Registers command utilizes the internal 256-byte buffer for processing. Therefore, the contents of
the buffer will be altered from its previous state when this command is issued.
The Security Registers can be programmed in a similar fashion to the Program Array operation up to the maximum clock
frequency specified by fCLK. Before a Program Security Registers command can be started, the Write Enable command
must have been previously issued to the device (see “Write Enable (06h)” on page 20) to set the Write Enable Latch
(WEL) bit of the Status Register to a logical “1” state. To program the Security Registers, the CS pin must first be
asserted and the opcode of 42h must be clocked into the device. After the opcode has been clocked in, the three address
bytes must be clocked in to specify the starting address location of the first byte to program within the Security Register.
Table 9-2. Security Register Addresses for Program Security Registers Command
0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39
6&.
OPCODE ADDRESS BI
TS A23-
A0 DATAI
NBYTE1 DATAI
NBYTEn
6, 0 0 1 A A A A A A D D D D D D D D D D D D D D D D
MSB MSB MSB MSB
HI
GH-
IMPEDANCE
62
AT25SF321 24
DS-25SF321–047F–8/2017
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
Table 9-3. Security Register Addresses for Read Security Registers Command
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36
6&.
OPCODE ADDRESS BI
TS A23-
A0 DON'
TCARE
6, 0 1 A A A A A A A A A X X X X X X X X X
MSB MSB MSB
DATABYTE1
HI
GH-
IMPEDANCE
62 D D D D D D D D D D
MSB MSB
AT25SF321 25
DS-25SF321–047F–8/2017
Table 10-1. Status Register Format - Byte 1
7 SRP0 Status Register Protection bit-0 R/W See Table 10-3 on Status Register Protection
6 SEC Block Protection R/W See Table 8-1 and 8-2 on Non-Volatile Protection
5 TB Top or Bottom Protection R/W See Table 8-1 and 8-2 on Non-Volatile Protection
4 BP2 Block Protection bit-2 R/W See Table 8-1 and 8-2 on Non-Volatile Protection
3 BP1 Block Protection bit-1 R/W See Table 8-1 and 8-2 on Non-Volatile Protection
2 BP0 Block Protection bit-0 R/W See Table 8-1 and 8-2 on Non-Volatile Protection
0 Device is not Write Enabled (default)
1 WEL Write Enable Latch Status R
1 Device is Write Enabled
0 Device is ready
0 RDY/BSY Ready/Busy Status R
1 Device is busy with an internal operation
Notes: 1. Only bits 7 through 2 of the Status Register can be modified when using the Write Status Register command.
2. R/W = Readable and writable
R = Readable only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SCK
23&2'(
SI 0 0 0 0 0 1 0 1
MSB
67$7865(*,67(5 67$7865(*,67(5 67$7865(*,67(5
BYTE 1 BYTE 1 BYTE 1
HI
GH-
IMPEDANCE
SO D D D D D D D D D D D D D D D D D D D D D D D D
MSB MSB MSB
AT25SF321 26
DS-25SF321–047F–8/2017
Table 10-2. Status Register Format – Byte 2
0 SRP1 Status Register Protect bit-1 R/W See table on Status Register Protection
Notes: 1. Only bits 6 through 3, 1, and 0 of the Status Register can be modified when using the Write Status Register command
2. R/W = Readable and writable
R = Readable only.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SCK
23&2'(
SI 0 0 0 1 0 1
MSB
67$7865(*,67(5 67$7865(*,67(5 67$7865(*,67(5
BYTE 2 BYTE 2 BYTE 2
HI
GH-
IMPEDANCE
SO D D D D D D D D D D D D D D D D D D D D D D D D
MSB MSB MSB
0 1 0 Hardware Protected WP=0, the Status Register is locked and cannot be written.
Power Supply Lock- Status Register is protected and cannot be written to again
1 0 X
Down (1) until the next Power-Down, Power-Up cycle.
1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to the (0, 0) state.
AT25SF321 27
DS-25SF321–047F–8/2017
The CMP bit complements the effect of the other bits.
The SEC bit selects between large and small block size protection.
The TB bit selects between top of the array or bottom of the array protection.
The BP2, BP1, and BP0 bits determine how much of the array is protected.
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an incomplete or
unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset
when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Program Security Register,
Erase Security Register, or Write Status Register command must have been clocked into the device.
10.1.6 QE Bit
The QE bit is used to determine if the device is in the Quad Enabled mode. If the QE bit is in the logical “1” state, then the
HOLD and WP pins functions as input/output pins similar to the SI and SO. If the QE bit is in the logical “0” state, then the
HOLD pin functions as an input only and the WP pin functions as an input only.
AT25SF321 28
DS-25SF321–047F–8/2017
The complete one byte or two bytes of data must be clocked into the device before the CS pin is deasserted, and the CS
pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,
the state of the Status Register bits will not change, memory protection status will not change, and the WEL bit in the
Status Register will be reset back to the logical “0” state
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI 0 0 0 0 0 0 0 1 D D D D D D D D D D D D D D D D
MSB MSB
High-Impedance
SO
AT25SF321 29
DS-25SF321–047F–8/2017
Figure 10-4. Write Enable for Volatile Status Register
&6
0 1 2 3 4 5 6 7
6&.
OPCODE
6,
MSB
HI
GH-
IMPEDANCE
62
1 Manufacturer ID 1Fh
AT25SF321 30
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Table 11-3. Manufacturer and Device ID Details
Hex
Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Details
Sub Code Product Version Code Sub Code: 000 (Standard series)
Device ID (Part 2) 01h
Product Version: 00001
0 0 0 0 0 0 0 1
CS
0 6 7 8 14 15 16 22 23 24 30 31 32
SCK
OPCODE
SI 9Fh
HIGH-IMPEDANCE
SO 1Fh 87h 01h
Note: Each transition shown for SI and SO represents one byte (8 bits)
AT25SF321 31
DS-25SF321–047F–8/2017
Figure 11-2. Read ID (Legacy Command)
&6
0 1 2 3 4 5 6 7 29 30 31 32 33 34 35 36 37 38 39
6&.
OPCODE '800<%<7(6
6, 1 0 0 X X X X X
MSB
'(9,&(,'
HI
GH-
IMPEDANCE
62 D D D D D D D D
MSB
&6
W('3'
6&.
23&2'(
6,
06%
+,*+,03('$1&(
62
$FWLYH&XUUHQW
,&&
6WDQGE\0RGH&XUUHQW
'HHS3RZHU'RZQ0RGH&XUUHQW
AT25SF321 32
DS-25SF321–047F–8/2017
11.4 Resume from Deep Power-Down (ABh)
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down
command must be issued. The Resume from Deep Power-Down command is the only command that the device will
recognize while in the Deep Power-Down mode.
To resume from the Deep Power-Down mode, the CS pin must first be asserted and the opcode of ABh must be clocked
into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is
deasserted, the device will exit the Deep Power-Down mode within the maximum time of tRDPD and return to the standby
mode. After the device has returned to the standby mode, normal command operations such as Read Array can be
resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an byte
boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode.
&6
t
RDPD
0 1 2 3 4 5 6 7
6&.
OPCODE
6, 1 0 1 0 1 0 1 1
MSB
HI
GH-
IMPEDANCE
62
Act
iveCur
rent
,&&
St
andbyModeCur
rent
DeepPower
-DownModeCur
rent
AT25SF321 33
DS-25SF321–047F–8/2017
Figure 11-5. Resume from Deep Power-Down and Read Device ID
&6
0 1 2 3 4 5 6 7 29 30 31 32 33 34 35 36 37 38 39
6&.
OPCODE '800<%<7(6
W5'32
6, 1 0 1 0 1 0 1 1 X X X X X
MSB
'(9,&(,'
HI
GH-
IMPEDANCE
62 D D D D D D D D
MSB
Act
i
veCur
rent
,&&
'HHS3RZHU'RZQ0RGH&XUUHQW 6WDQGE\0RGH&XUUHQW
AT25SF321 34
DS-25SF321–047F–8/2017
Figure 11-6. Hold Mode
CS
SCK
HOLD
AT25SF321 35
DS-25SF321–047F–8/2017
12. Electrical Specifications
12.1 Absolute Maximum Ratings*
Temperature under Bias. . . . . . . . . . . . . -55°C to +125°C *Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C the device. This is a stress rating only and functional
operation of the device at these or any other
conditions beyond those indicated in the operational
All Input Voltages (including NC Pins)
sections of this specification is not implied. Exposure
with Respect to Ground . . . . . . . . . . . . . . -0.6V to +4.1V
to absolute maximum rating conditions for extended
periods may affect device reliability.
All Output Voltages
with Respect to Ground . . . . . . . . . . -0.6V to VCC + 0.5V
12.3 DC Characteristics
2.5V to 3.6V
Active Current,
ICC4(1) CS = VCC 10 16 mA
Program Operation
Active Current,
ICC5(1) CS = VCC 10 16 mA
Erase Operation
AT25SF321 36
DS-25SF321–047F–8/2017
2.5V to 3.6V
1. Typical values measured at 3.0V @ 25°C for the 2.5V to 3.6V range
fCLK Maximum Clock Frequency for All Operations 104 104 MHz
(excluding opcodes below)
fRDLF Maximum Clock Frequency for 03h Opcode 50 50 MHz
tCLKR(1) Clock Rise Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns
tCLKF(1) Clock Fall Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns
AT25SF321 37
DS-25SF321–047F–8/2017
12.5 AC Characteristics - All Other Parameters
2.5V to 3.6V 2.7V to 3.6V
Symbol Parameter Min Typ Max Min Typ Max Units
tPP (1) Page Program Time (256 Bytes) 0.7 5 0.7 3.0 ms
AT25SF321 38
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12.6 Program and Erase Characteristics
2.5 to 3.6V 2.7V to 3.6V
AT25SF321 39
DS-25SF321–047F–8/2017
12.8 Input Test Waveforms and Measurement Levels
AC 0.9VCC AC
DRIVING VCC/2 MEASUREMENT
LEVELS 0.1VCC LEVEL
Device
Under
Test
30pF
13. AC Waveforms
Figure 13-1. Serial Input Timing
W&6+
&6
W&6/6 W&6/+ W&6++
W&/.+ W&/./ W&6+6
6&.
W'6 W'+
+,*+,03('$1&(
62
&6
W&/.+ W&/./ W',6
6&.
6,
W2+
W9 W9
62
AT25SF321 40
DS-25SF321–047F–8/2017
Figure 13-3. WP Timing for Write Status Register Command When BPL = 1
CS
t WPS t WPH
WP
SCK
SI 0 0 0 X MSB
MSB OF LSB OF MSB OF
WRITE STATUS REGISTER WRITE STATUS REGISTER NEXT OPCODE
OPCODE DATA BYTE
HIGH-IMPEDANCE
SO
CS
SCK
tHHH tHLS
tHLH tHHS
HOLD
SI
HIGH-IMPEDANCE
SO
CS
SCK
tHHH tHLS
tHLH tHHS
HOLD
SI
tHLQZ tHHQX
SO
AT25SF321 41
DS-25SF321–047F–8/2017
14. Ordering Information
AT 2 5 S F 3 2 1 – SSHD – B
Device Grade
H = Green, NiPdAu lead finish,
Device Density Industrial temperature range
(–40°C to +85°C)
32 = 32-megabit
Package Option
Interface M = 8-pad, 5 x 6 x 0.6 mm UDFN
1 = Serial SS = 8-lead, 0.150" wide SOIC
S = 8-lead, 0.208" wide SOIC
DWF = Die in Wafer Form
Max. Freq.
Ordering Code (1) Package Operating Voltage (MHz) Operation Range
AT25SF321-SSHD-B
8S1
AT25SF321-SSHD-T
AT25SF321-SHD-B Industrial
8S2 2.5V to 3.6V 85MHz
AT25SF321-SHD-T (-40°C to +85°C)
AT25SF321-MHD-T 8MA1
(2)
AT25SF321-DWF DWF
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8MA1 8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN)
AT25SF321 42
DS-25SF321–047F–8/2017
15. Packaging Information
E E1
N L
Ø
TOP VIEW
END VIEW
e b
A COMMON DIMENSIONS
(Unit of Measure = mm)
5/19/10
AT25SF321 43
DS-25SF321–047F–8/2017
15.2 8S2 – 8-lead, .208” EIAJ SOIC
E E1
L
N
TOP VIEW θ
END VIEW
e b COMMON DIMENSIONS
A (Unit of Measure = mm)
4/15/08
® TITLE GPC DRAWING NO. REV.
8S2, 8-lead, 0.208” Body, Plastic Small
Package Drawing Contact: Outline Package (EIAJ) STN 8S2 F
contact@adestotech.com
AT25SF321 44
DS-25SF321–047F–8/2017
15.3 8MA1 – UDFN
E
C
Pin 1 ID
D SIDE VIEW
TOP VIEW
A1
A
K E2
0.45 Option A
8 1 Pin #1
Pin #1 Notch Chamfer COMMON DIMENSIONS
(0.20 R) (C 0.35)
(Unit of Measure = mm)
(Option B)
7 2 SYMBOL MIN NOM MAX NOT E
A 0.45 0.55 0.60
D2 e
A1 0.00 0.02 0.05
6 3
b 0.35 0.40 0.48
C 0.152 REF
5 4 D 4.90 5.00 5.10
D2 3.80 4.00 4.20
b
E 5.90 6.00 6.10
BOTTOM VIEW
L E2 3.20 3.40 3.60
e 1.27
L 0.50 0.60 0.75
y 0.00 – 0.08
K 0.20 – –
4/15/08
TITLE GPC DRAWING NO. REV.
® Package Drawing Contact: 8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally
contact@adestotech.com Enhanced Plastic Ultra Thin Dual Flat No Lead YFG 8MA1 D
Package (UDFN)
AT25SF321 45
DS-25SF321–047F–8/2017
16. Revision History
Revision Level – Release Date History
AT25SF321 46
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Corporate Office
California | USA
Adesto Headquarters
3600 Peterson Way
Santa Clara, CA 95054
Phone: (+1) 408.400.0578
Email: contact@adestotech.com
Adesto®, the Adesto logo, CBRAM®, and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective
owners.
Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms
and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications
detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the
Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.