EC25C32 32kbits SPI Serial EEPROM: General Description
EC25C32 32kbits SPI Serial EEPROM: General Description
General Description
The EC25C32 is an industrial standard electrically In order to refrain the state machine from entering into a
erasable programmable read only memory Wrong state during power-up sequence or a power
(EEPROM) Product that utilizes standard Serial toggle off-on condition, a power on reset circuit is
Peripheral Interface (SPI) for communications. implemented. During power-up, the device does not
The EC25C32 contains a memory array of 32K respond to any instructions until the supply voltage
bits (4,096x 8), which is organized in 32 bytes per (VCC)has reached an acceptable stable level above the
page. reset threshold voltage. Once VCC passes the power on
This EEPROM operates in a wide voltage range reset threshold, the device is reset and enters into
from 1.7V to 5.5V,which fits most application. Standby mode. This should also avoid any inadvertent
The device provides low-power operations and Write operations during power-up stage. During power-
low standby current. The product is offered in down process, the device will enter into standby mode,
Lead-free, RoHS, halogen free or Green package. once VCC drops below the power on reset threshold
The available package types are 8-pin SOP, voltage. In addition, the device will be in standby mode
TSSOP and UDFN. after receiving the Stop command, provided that no
The functionalities of the EC25C32 are optimized internal write operation is in progress. Nevertheless,
for most applications, such as consumer it is illegal to send a command unless the VCC is within its
electronics,wireless,telecommunication, industrial, operating level.
medical ,instrumentation, commercial and others,
where low-power and low-voltage are vital. This
product has a compatible SPI interface: Chip-
Select ( CS ), Serial Data In (SI), Serial Data Out
(SO) and Serial Clock (SCK) for high-speed
communication. Furthermore, a Hold feature
via HOLD pin allows the device entering into
a suspended state whenever necessary and
resuming the communication without re-initializing
the serial sequence. A Status Register
facilitates a flexible write protection mechanism
and device Status monitoring.
Features
EC25C XXN XX X X
R:Tape & Reel
Pin Configuration
(SOP-8/TSSOP-8) (DFN-8)
Pin Definition
Pin No. Pin Name I/O Definition
1 CS I Chip Select
2 SO O Serial Data Output
3 WP I Write Protect Input
4 GND - Ground
5 SI I Serial Data Input
6 SCK I Serial Clock
7 HOLD I Hold function
8 VCC - Supply Voltage
Pin Descriptions
Chip Select ( )
The CS pin is used to enable or disable the device. Upon power-up, CS must follow the supply voltage. When
the device is ready for instruction input, this signal requires a High-to-Low transition. Once CS is stable at Low,
the device is enabled. Then the master and slave can communicate among each other through SCK, SI, and
SO pins. Upon completion of transmission, CS must be driven to High in order to stop the operation or start
the internal write operation. And the device will enter into standby mode, unless an internal write operation is in
progress. During this mode, SO becomes high impedance.
Serial Clock (SCK)
Under the SPI modes (0,0) and (1,1),this clock signal provides synchronization between the master and
EC25C32.Typically,Op-Codes,addresses and data are latched from SI at the rising edge of SCK, while data
from SO are clocked out at the falling edge of SCK.
Serial Data Input (SI)
Data Input pin.
Serial Data Output(SO)
Data output pin.
Write Protect ( )
This active Low input signal is utilized to initiate Hardware Write Protection mode. This mode prevents the
Block Protection bits and the WPEN bit in the Status Register from being modified. To activate the Hardware
Write Protection, WP must be Low simultaneously when WPEN is set to 1.
Hold ( )
This feature is used to suspend the device in the middle of a serial sequence and temporarily ignore further
communication on the bus (SI,SO,SCK).The HOLD signal transitions must occur only when SCK is Low and be
held stable during SCK transitions. Connecting HOLD to High disables this feature. Figure.8 shows Hold timing.
Device Operation
Status Register
The Status Register accessible by the user consists of 8-bits data for write protection control and write status.
It Hardware Write Protection is enabled or WEN is set to 0. If neither is true, it can be modified by a valid
instruction.
Op-Code Instructions
The operations of the EC25C32 are controlled by a set of instruction Op-Codes (Table3) that are clocked-in
serially via SI pin. To initiate an instruction, the chip select(CS) must be Low. Subsequently, each Low-to-High
transition of the clock (SCK) will latch a stable level from SI. After the 8-bit Op-Code, it may continue to latch-in
an address and/or data output, data are latched out at the falling edge of SCK. All communications start with
MSB first. Upon the transmission of the last bit but prior to any following Low-to-High transition on SCK, CS
must be brought to High in order to end the transaction and start the operation. The device will enter into
Standby Mode after the operation is completed. data from SI accordingly, or to output data from SO. During
data output, data are latched out at the falling edge of SCK. All communications start with MSB first. Upon
the transmission of the last bit but prior to any following Low-to-High transition on SCK, CS must be brought
to High in order to end the transaction and start the operation. The device will enter into Standby Mode after the
operation is completed.
READ 0000 X011 Read Data from Array A15-A0 - D7-D0, ...
WRITE 0000 X010 Write Data to Array A15-A0 D7-D0, ... -
Notes:
[1] X = Don’t care bit. However, it is recommended to be “0”.
[2]Some address bits may be don’t care (Table 5).
[3] It is strongly recommended that an appropriate format of Op-Code must be entered. Otherwise, it maycause
unexpected phenomenon to be occurred. Nevertheless, it is illegal to input invalid any Op-Code.
Write Enable
When VCC is initially applied ,the device powers up with both status register and entire array in a write-
disabled state. Upon completion of Write Disable(WRDI),Write Status Register(WRSR) or Write Data to Array
(WRITE), the device resets the WEN bit in the Status Register to 0. Prior to any data modification, a Write
Enable (WREN) instruction is necessary to set WEN to 1 (Figure.2).
Write Disable
The device can be completely protected from modification by resetting WEN to 0 through the Write Disable
(WRDI) instruction (Figure.3).
Read Data
This instruction includes an Op-Code and 16-bit address, then results the selected data to be shifted out from
SO. Following the first data byte, additional sequential data can be output. If the data byte of the last
address is initially output, then address will rollover to the first address in the array, and the output could loop
indefinitely. At any time, a rising CS signal ceases the operation (Figure.6).
Write Data
The WRITE instruction contains an Op-Code, a 16-bit address and the first data byte. Additional data bytes
may be supplied sequentially after the first byte. Each WRITE instruction can affect up to 32 bytes of data in a
page. Each page has a starting address XXXXXXXX XXX00000 and an ending address XXXXXXXX XXX11111.
After the last byte of data in a page is input, the address rolls over to the beginning of the same page. If more
than 32 bytes of data is input during a single instruction, then only the last 32 bytes will be retained, but the
initial data will be overwritten. The contents of the array defined by Block Protection cannot be modified as long
as that block configuration is selected. The contents of the array outside the Block Protection can only be
modified if Write Enable (WEN) is set to 1. Therefore, it may be necessary that a WREN instruction is initiated
prior to WRITE. Once Write operation is completed, WEN is reset for complete chip write protection (Figure.7)
Besides, Hardware Write Protection has no affect on the memory array.
Diagrams
Electrical Characteristics
Absolute Maximum Ratings
Symbol Parameter Value Unit
VS Supply Voltage -0.5 to + 6.5 V
VP Voltage on Any Pin –0.5 to VCC + 0.5 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
IOUT Output Current 5 mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other condition outside those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Operating Range
Capacitance
[1,2]
Symbol Parameter Conditions Max. Unit
Input / Output
CI/O VI/O = 0V 8 pF
Capacitance
Note: (1) Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
(2) Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
AC Electrical Characteristic
1.7VVCC<2.5V 2.5VVCC<4.5V 4.5VVCC5.5V
Symbol Parameter[1] Unit
Min. Max. Min. Max. Min. Max.
FSCK SCK Clock Frequency 0 5 0 10 0 20 MHz
TRI Input Rise Time — 1 — 1 — 1 μs
TFI Input Fall Time — 1 — 1 — 1 μs
TWH SCK High Time 80 — 40 — 20 — ns
TWL SCK Low Time 80 — 40 — 20 — ns
TCS CS High Time 100 — 50 — 25 — ns
TCSS CS Setup Time 100 — 50 — 25 — ns
TCSH CS Hold Time 100 — 50 — 25 — ns
TSU Data In Setup Time 20 — 10 — 5 — ns
TH Data In Hold Time 20 — 10 — 5 — ns
THD HOLD Setup Time 20 — 10 — 5 — ns
TCD HOLD Hold Time 20 — 10 — 5 — ns
[2]
TV Output Valid 0 80 0 40 0 20 ns
THO Output Hold Time 0 — 0 — 0 — ns
TLZ HOLDto Output Low Z 0 80 0 40 0 25 ns
THZ HOLDto Output High Z — 80 — 40 — 40 ns
TDIS Output Disable Time — 80 — 40 — 40 ns
TWC Write Cycle Time — 5 — 5 — 5 ms
Notes: [1] The parameters are characterized but not 100% tested.
[2] CL = 30pF (typical)
Package Information
SOP -8
Note:
1. Controlling Dimension:MM
2. Dimension D and E1 do not include
Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MS-012
5. Drawing is not to scale
TSSOP -8
Note:
1. Controlling Dimension:MM
2. Dimension D and E do not include Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MO-153 AA
5. Drawing is not to scale
6. Package may have exposed tie bar
DFN-8
Note:
1. Controlling Dimension:MM
2. Drawing is not to scale