Professional Documents
Culture Documents
25Q16BSIG
25Q16BSIG
FEATURES
◆ 16M-bit Serial Flash ◆ Program/Erase Speed
-2048K-byte -Page Program time: 0.7ms typical
-256 bytes per programmable page -Sector Erase time: 100ms typical
-Block Erase time: 0.3/0.4/0.8s typical
◆ Standard, Dual, Quad SPI -Chip Erase time: 16s typical
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# ◆ Flexible Architecture
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 -Sector of 4K-byte
-Block of 32/64/128K-byte
◆ High Speed Clock Frequency
-120MHz for fast read with 30PF load ◆ Low Power Consumption
-Dual I/O Data transfer up to 180Mbits/s -20mA maximum active current
-Quad I/O Data transfer up to 360Mbits/s -5uA maximum power down current
(1)
◆ Software/Hardware Write Protection ◆ Advanced security Features
-Write protect all/portion of memory via software -16-Bit Customer ID
-Enable/Disable protection with WP# Pin -Security Architecture
-Top or Bottom, Sector or Block selection
◆ Single Power Supply Voltage
◆ Minimum 100,000 Program/Erase Cycles -Full voltage range:2.7~3.6V
Note: 1.Please contact Gigadevice for details.
GENERAL DESCRIPTION
The GD25Q16 (16M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of
360Mbits/s.
CONNECTION DIAGRAM
CS# 1 8 VCC
SO 2 7 HOLD#
Top View
WP# 3 6 SCLK
VSS 4 5 SI
8–LEAD SOP/DIP
1
Uniform Sector
Dual and Quad Serial Flash GD25Q16
PIN DESCRIPTION
Pin Name I/O Description
CS# I Chip Select Input
SO (IO1) I/O Data Output (Data Input Output 1)
WP# (IO2) I/O Write Protect Input (Data Input Output 2)
VSS Ground
SI (IO0) I/O Data Input (Data Input Output 0)
SCLK I Serial Clock Input
HOLD# (IO3) I/O Hold Input (Data Input Output 3)
VCC Power Supply
BLOCK DIAGRAM
Status
Write Protect Logic
Register
and Row Decode
Flash
High Voltage
HOLD#(IO3) Memory
Generators
SPI
SCLK Command &
Control Logic Page Address
Latch/Counter
CS#
2
Uniform Sector
Dual and Quad Serial Flash GD25Q16
MEMORY ORGANIZATION
Each device has Each block has Each sector has Each page has
2M 128/64/32K 4K 256 bytes
8K 512/256/128 16 - pages
512 32/16/8 - - sectors
16/32/64 - - - blocks
3
Uniform Sector
Dual and Quad Serial Flash GD25Q16
DEVICE OPERATION
SPI Mode
Standard SPI
The GD25Q16 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q16 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH
and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the
standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25Q16 supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad
I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at
four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O
pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad
Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD HOLD
4
Uniform Sector
Dual and Quad Serial Flash GD25Q16
Data Protection
The GD25Q16 provide the following data protection methods:
◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE)
-Block Erase (BE)
-Chip Erase (CE)
◆ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
◆ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Table1. GD25Q16 Protected area size
Status Register Content Memory Content
5
Uniform Sector
Dual and Quad Serial Flash GD25Q16
Status Register
S15-S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Reserved QE SRP1 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, BP0) bits are 0.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0 #WP Status Register Description
The Status Register can be written to after a Write Enable
0 0 X Software Protected
command, WEL=1.(Default)
WP#=0, the Status Register locked and can not be written to.
0 1 0 Hardware Protected
6
Uniform Sector
Dual and Quad Serial Flash GD25Q16
COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most
significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the
command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from
Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can
be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the
command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen
and WEL will not be reset.
Table2. Commands
Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes
Write Enable 06H
Write Disable 04H
Read Status Register 05H (S7-S0) (continuous)
Read Status Register-1 35H (S15-S8) (continuous)
Write Status Register 01H (S7-S0) (S15-S8)
Read Data 03H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) (continuous)
Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
(1)
Dual Output 3BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Fast Read
(2) (1)
Dual I/O BBH A23-A8 A7-A0 (D7-D0) (continuous)
(2)
Fast Read M7-M0
(3)
Quad Output 6BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Fast Read
(5) (3)
Quad I/O EBH A23-A0 dummy (D7-D0) (continuous)
(4)
Fast Read M7-M0
(6) (3)
Quad I/O Word E7H A23-A0 dummy (D7-D0) (continuous)
(7) (4)
Fast Read M7-M0
Continuous Read Reset FFH
Page Program 02 H A23-A16 A15-A8 A7-A0 D7-D0 Next byte
Sector Erase 20H A23-A16 A15-A8 A7-A0
Block Erase(32K) 52H A23-A16 A15-A8 A7-A0
Block Erase(64K) D8H A23-A16 A15-A8 A7-A0
Block Erase(128K) D2H A23-A16 A15-A8 A7-A0
Chip Erase C7/60 H
Program/Erase 75H
Suspend
Program/Erase Resume 7AH
Deep Power-Down B9H
Release From Deep ABH dummy dummy dummy (ID7-ID0) (continuous)
Power-Down, And
Read Device ID
Release From Deep ABH
Power-Down
7
Uniform Sector
Dual and Quad Serial Flash GD25Q16
Manufacturer/
90H dummy dummy 00H (M7-M0) (ID7-ID0) (continuous)
Device ID
High Performance Mode A3H dummy dummy dummy
Read Identification 9FH (M7-M0) (ID15-ID8) (ID7-ID0) (continuous)
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
Table of ID Definitions:
Operation Code M7-M0 ID15-ID8 ID7-ID0
9FH C8 40 15
90H C8 14
ABH 14
8
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
06H
High-Z
SO
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
04H
High-Z
SO
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
Command
SI
05H or 35H
S7~S0 or S15~S8 out S7~S0 or S15~S8 out
SO High-Z
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB
9
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
10
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK
SO High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI 7 6 5 4 3 2 1 0
Data Out1 Data Out2
SO 7 6 5 4 3 2 1 0 7 6 5
MSB MSB
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK
SO High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI 6 4 2 0 6 4 2 0 6
Data Out1 Data Out2
SO 7 5 3 1 7 5 3 1 7
MSB MSB
11
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI(IO0) 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4
12
Uniform Sector
Dual and Quad Serial Flash GD25Q16
Figure10. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0) BBH 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
A23-16 A15-8 A7-0 M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1 Byte2 Byte3 Byte4
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
A23-16 A15-8 A7-0 M7-0
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1 Byte2 Byte3 Byte4
13
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0) EBH 4 0 4 0 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2
14
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0) E7H 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
Figure15. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
15
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
2075
2076
2078
2072
2074
2077
2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
16
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
17
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
18
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
60H or C7H
19
Uniform Sector
Dual and Quad Serial Flash GD25Q16
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it
requires a delay of tDP before the supply current is reduced to I CC2 and the Deep Power-Down Mode is entered. Any Deep
Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure22. Deep Power-Down Sequence Diagram
CS#
0 1 2 3 4 5 6 7 tDP
SCLK
Release From Deep Power-Down Or High Performance Mode And Read Device ID (RDI) (ABH)
The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can be
used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic
identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the
CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure23. Release from Power-Down
will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other
command are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. The Device ID value for the GD25Q16
is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is
completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, and shown in Figure23, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other
command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or
Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure23. Release Power-Down Or High Performance Mode Sequence Diagram
CS#
0 1 2 3 4 5 6 7 t RES1
SCLK
Command
SI
ABH
20
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38
SCLK
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Manufacturer ID Device ID
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
21
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
SI 9FH
Manufacturer ID
SO 7 6 5 4 3 2 1 0
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
22
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
Command 3 Dummy Bytes t HPM
SI A3H 23 22 2 1 0
MSB
SO
High Performance Mode
SI(IO0) FFH
23
Uniform Sector
Dual and Quad Serial Flash GD25Q16
CS#
0 1 2 3 4 5 6 7 tSUS
SCLK
Command
SI
75H
High-Z
SO
Accept read command
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
7AH
SO Resume Erase/Program
24
Uniform Sector
Dual and Quad Serial Flash GD25Q16
POWER-ON TIMING
Vcc(max)
Program, Erase and Write command are ignored
Chip Selection is not allowed
Vcc(min)
tVSL Read command Device is fully
Reset is allowed accessible
State
VWI
tPUW
Time
150℃ 10 Years
Minimum Pattern Data Retention Time
125℃ 20 Years
Erase/Program Endurance -40 to 85℃ 100K Cycles
LATCH UP CHARACTERISTICS
Parameter Min Max
25
Uniform Sector
Dual and Quad Serial Flash GD25Q16
4.0V
20ns
0V 3.6V
20ns
-0.5V
26
Uniform Sector
Dual and Quad Serial Flash GD25Q16
DC CHARACTERISTIC
(T= -40℃~85℃, VCC=2.7~3.6V)
Symbol Parameter Test Condition Min. Typ Max. Unit.
ILI Input Leakage Current ±2 μA
ILO Output Leakage Current ±2 μA
ICC1 Standby Current CS#=VCC, 1 5 μA
VIN=VCC or VSS
ICC2 Deep Power-Down Current CS#=VCC, 1 5 μA
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 90MHz, 15 20 mA
Q=Open(*1,*2,*4 I/O)
ICC3 Operating Current (Read)
CLK=0.1VCC / 0.9VCC
at 80MHz, 13 18 mA
Q=Open(*1,*2,*4 I/O)
ICC4 Operating Current (PP) CS#=VCC 10 mA
ICC5 Operating Current(WRSR) CS#=VCC 10 mA
ICC6 Operating Current (SE) CS#=VCC 10 mA
ICC7 Operating Current (BE) CS#=VCC 10 mA
I CC8 High Performance Current 600 800 uA
VIL Input Low Voltage -0.5 0.2VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL =1.6mA 0.4 V
VOH Output High Voltage IOH =-100μA VCC-0.2 V
27
Uniform Sector
Dual and Quad Serial Flash GD25Q16
AC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.7~3.6V, CL=30pf)
Symbol Parameter Min. Typ. Max. Unit.
Serial Clock Frequency For: FAST_READ(0BH),
fC DC. 120 MHz
Dual Output(3BH)
Serial Clock Frequency For: Dual I/O(BBH),
fC1 Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O DC. 90 MHz
With High Performance Mode)
Serial Clock Frequency For: Dual I/O(BBH),
fC2 Quad I/O(EBH) (Dual I/O & Quad I/O Without High DC. 50 MHz
Performance Mode)
fR Serial Clock Frequency For: Read(03H) DC. 90 MHz
tCLH Serial Clock High Time 3.5 ns
tCLL Serial Clock Low Time 3.5 ns
tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns
tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns
tSLCH CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL CS# High Time(read/write) 20 ns
tSHQZ Output Disable Time 16 ns
tCLQX Output Hold Time 0 ns
tDVCH Data In Setup Time 2 ns
tCHDX Data In Hold Time 2 ns
tHLCH Hold# Low Setup Time (relative to Clock) 5 ns
tHHCH Hold# High Setup Time (relative to Clock) 5 ns
tCHHL Hold# High Hold Time (relative to Clock) 5 ns
tCHHH Hold# Low Hold Time (relative to Clock) 5 ns
tHLQZ Hold# Low To High-Z Output 6 ns
tHHQX Hold# Low To Low-Z Output 6 ns
tCLQV Clock Low To Output Valid 6 ns
tWHSL Write Protect Setup Time Before CS# Low 20 ns
tSHWL Write Protect Hold Time After CS# High 100 ns
tDP CS# High To Deep Power-Down Mode 0.1 μs
CS# High To Standby Mode Without Electronic Signature
tRES1 0.1 μs
Read
CS# High To Standby Mode With Electronic Signature
tRES2 0.1 μs
Read
tHPM CS# High To High Performance mode 0.2 us
28
Uniform Sector
Dual and Quad Serial Flash GD25Q16
tSHSL
CS#
SI MSB LSB
SO High-Z
CS#
tCH tSHQZ
SCLK
tCLQV tCLQV tCL
tCLQX tCLQX tQLQH
SO LSB
tQHQL
SI
Least significant address bit (LIB) in
CS#
tCHHH
tHLQZ tHHQX
SO
HOLD#
29
Uniform Sector
Dual and Quad Serial Flash GD25Q16
ORDERING INFORMATION
GD XX X XX X X X X
Packing Type
T:Tube
Y:Tray
R:Tape & Reel
Green Code
P:Pb Free Only Green Package
G:Pb Free & Halogen Free Green Package
Temperature Range
C:Commercial(0℃ to +70℃)
I:Industrial(-40℃ to +85℃)
Package Type
T:SOP8 150mil
S:SOP8 208mil
P:DIP8
W: WSON (6*5mm)
Density
80:8Mb
16:16Mb
32:32Mb
64:64Mb
Series
Q:3V, 4KB Uniform Sector, Quad I/O
LQ:1.8V,4KB Uniform Sector
Product Family
25:Serial Flash
NOTE:
1. Standard bulk shipment is in Tube. Any alternation of packing method (for Tape, Reel and Tray etc.), please
advise in advance.
30
Uniform Sector
Dual and Quad Serial Flash GD25Q16
PACKAGE INFORMATION
Package SOP8L 208MIL
8 5 θ
E1 E
L1
L
1 4
C
D
A2 A
b A1
S e
Dimensions
Symbol
A A1 A2 b C D E E1 e L L1 S θ
Unit
Min 0.05 1.70 0.36 0.19 5.13 7.70 5.18 0.50 1.21 0.62 0
mm Nom 0.15 1.80 0.41 0.20 5.23 7.90 5.28 1.27 0.65 1.31 0.74 5
Max 2.16 0.25 1.91 0.51 0.25 5.33 8.10 5.38 0.80 1.41 0.88 8
Min 0.002 0.067 0.014 0.007 0.202 0.303 0.204 0.020 0.048 0.024 0
Inch Nom 0.006 0.071 0.016 0.008 0.206 0.311 0.208 0.050 0.026 0.052 0.029 5
Max 0.085 0.010 0.075 0.020 0.010 0.210 0.319 0.212 0.031 0.056 0.035 8
31
Uniform Sector
Dual and Quad Serial Flash GD25Q16
8 5 θ
E1 E
L1
L
1 4
C
D
A2 A
b A1
S e
Dimensions
Symbol
A A1 A2 b C D E E1 e L L1 S θ
Unit
Min 0.10 1.35 0.36 0.15 4.77 5.80 3.80 0.46 0.85 0.41 0
mm Nom 0.15 1.45 0.41 0.20 4.90 5.99 3.90 1.27 0.66 1.05 0.54 5
Max 1.75 0.20 1.55 0.51 0.25 5.03 6.20 4.00 0.86 1.25 0.67 8
Min 0.004 0.053 0.014 0.006 0.188 0.228 0.150 0.018 0.033 0.016 0
Inch Nom 0.006 0.057 0.016 0.008 0.193 0.236 0.154 0.050 0.026 0.041 0.021 5
Max 0.069 0.008 0.061 0.020 0.010 0.198 0.244 0.158 0.034 0.049 0.026 8
32
Uniform Sector
Dual and Quad Serial Flash GD25Q16
Package DIP8L
8 5
E1
1 4
D
E
A2 A
C
L A1
b eB
S e
b1
Dimensions
Symbol
A A1 A2 b b1 C D E E1 e eB SL S
Unit
Min 0.38 3.18 1.14 0.36 0.20 9.02 7.62 6.22 7.87 2.92 0.76
mm Nom 3.30 1.52 0.46 0.25 9.27 7.87 6.35 2.54 8.89 3.30 1.14
Max 5.33 3.43 1.78 0.56 0.36 10.16 8.13 6.48 9.53 3.81 1.52
Min 0.015 0.125 0.045 0.014 0.008 0.355 0.300 0.245 0.310 0.115 0.030
Inch Nom 0.130 0.060 0.018 0.010 0.365 0.310 0.250 0.10 0.350 0.130 0.045
Max 0.21 0.135 0.070 0.022 0.014 0.400 0.320 0.255 0.375 0.150 0.060
33
Uniform Sector
Dual and Quad Serial Flash GD25Q16
REVISION HISTORY
Version No Description Date
1.0 Initial Release Sep.10,2009
1.1 Add Packing Type(Tray, Reel & Tape), Add 150Mil Package Feb.04,2010
1.2 Add tHPM Parameter May.14,2010
1.3 Update Datasheet Aug.04,2010
34