EN25F80 8 Megabit Serial Flash Memory With 4kbytes Uniform Sector
EN25F80 8 Megabit Serial Flash Memory With 4kbytes Uniform Sector
EN25F80 8 Megabit Serial Flash Memory With 4kbytes Uniform Sector
EN25F80
8 Megabit Serial Flash Memory with 4Kbytes Uniform Sector
FEATURES
• Software and Hardware Write Protection:
• Single power supply operation
- Write Protect all or portion of memory via
- Full voltage range: 2.7-3.6 volt
software
• 8 Mbit Serial Flash - Enable/Disable protection with WP# pin
- 8 M-bit/1024 K-byte/4096 pages
• High performance program/erase speed
- 256 bytes per programmable page
- Page program time: 1.5ms typical
• High performance - Sector erase time: 150ms typical
- 100MHz clock rate - Block erase time 800ms typical
- Chip erase time: 10 Seconds typical
• Low power consumption
- 5 mA typical active current • Lockable 256 byte OTP security sector
- 1 μA typical power down current
• Minimum 100K endurance cycle
• Uniform Sector Architecture:
• Package Options
- 256 sectors of 4-Kbyte
- 8 pins SOP 200mil body width
- 16 blocks of 64-Kbyte
- 8 contact VDFN
- Any sector or block can be
- 8 pins PDIP
erased individually
- All Pb-free packages are RoHS compliant
• Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25F80 is a 8M-bit (1024K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25F80 is designed to allow either single Sector at a time or full chip erase operation. The
EN25F80 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
Figure.1 CONNECTION DIAGRAMS
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EN25F80
SIGNAL DESCRIPTION
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will
be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same
SPI signals.
Vss Ground
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EN25F80
MEMORY ORGANIZATION
The memory is organized as:
z 1,048,576 bytes
z Uniform Sector Architecture
16 blocks of 64-Kbyte
256 sectors of 4-Kbyte
z 4096 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 2. Uniform Block Sector Architecture
Block Sector Address range
255 0FF000h 0FFFFFh
….
….
….
15
240 0F0000h 0F0FFFh
239 0EF000h 0EFFFFh
….
….
….
14
224 0E0000h 0E0FFFh
223 0DF000h 0DFFFFh
….
….
….
13
208 0D0000h 0D0FFFh
207 0CF000h 0CFFFFh
….
….
….
12
192 0C0000h 0C0FFFh
191 0BF000h 0BFFFFh
….
….
….
11
176 0B0000h 0B0FFFh
175 0AF000h 0AFFFFh
….
….
….
10
160 0A0000h 0A0FFFh
159 09F000h 09FFFFh
….
….
….
9
144 090000h 090FFFh
143 08F000h 08FFFFh
….
….
….
8
128 080000h 080FFFh
127 07F000h 07FFFFh
….
….
….
7
112 070000h 070FFFh
111 06F000h 06FFFFh
….
….
….
6
96 060000h 060FFFh
95 05F000h 05FFFFh
….
….
….
5
80 050000h 050FFFh
79 04F000h 04FFFFh
….
….
….
4
64 040000h 040FFFh
63 03F000h 03FFFFh
….
….
….
3
48 030000h 030FFFh
47 02F000h 02FFFFh
….
….
….
2
32 020000h 020FFFh
31 01F000h 01FFFFh
….
….
….
1
16 010000h 010FFFh
15 00F000h 00FFFFh
….
….
….
4 004000h 004FFFh
0 3 003000h 003FFFh
2 002000h 002FFFh
1 001000h 001FFFh
0 000000h 000FFFh
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EN25F80
OPERATING FEATURES
SPI Modes
The EN25F80 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus
operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus
master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal
is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DI pin is
sampled on the rising edge of the CLK. Data output on the DO pin is clocked out on the falling edge
of CLK.
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the
internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on
the same page of memory.
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EN25F80
All other instructions are ignored while the device is in the Deep Power-down mode. This can be
used as an extra software protection mechanism, when the device is not in active use, to protect the
device from inadvertent Write, Program or Erase instructions.
Status Register. The Status Register contains a number of status and control bits that can be read
or set (as appropriate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size
of the area to be software protected against Program and Erase instructions.
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit is operated in conjunction with the
Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal
allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the
Status Register (SRP, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as
normal sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can
only be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to
1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern the
EN25F80 provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a
number of clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction
completion
z The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions
are ignored except one particular instruction (the Release from Deep Power-down instruction).
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EN25F80
TABLE 3. Protected Area Sizes Sector Organization
Hold Function
The Hold (HOLD) signal is used to pause any serial communications with the device without reset-
ting the clocking sequence. However, taking this signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold
condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial
Clock (CLK) being Low (as shown in Figure 4.).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides
with Serial Clock (CLK) being Low.
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts af-
ter Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock
(CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in
Figure 4.).
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)
and Serial Clock (CLK) are Don’t Care.
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of
the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the
moment of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is necessary to
drive Hold (HOLD) High, and then to drive Chip Select (CS#) Low. This prevents the device from
going back to the Hold condition.
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EN25F80
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first.
Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#)
is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant
bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence
has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device
ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip
Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the
number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For
Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be
reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power
Down (RES ) minimum number of bytes specified has to be given, without which, the
command will be ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least
1 data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must,
any less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle
continues unaffected.
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EN25F80
read Device ID
Release from Deep
Power-down
Manufacturer/ 90h
Device ID
dummy dummy 00h(5) (M7-M0) (ID7-ID0)
Read Identification 9Fh (M7-M0) (ID15-ID8) (ID7-ID0)
Enter OTP mode 3Ah
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from
the device on the DO pin.
2. The Status Register contents will repeat continuously until CS# terminate the instruction.
3. All sectors may use any address within the sector.
4. The Device ID will repeat continuously until CS# terminate the instruction.
5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.
ABh 13h
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EN25F80
S7 S6 S5 S4 S3 S2 S1 S0
Write In Progress
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EN25F80
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no
such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size
of the area to be software protected against Program and Erase instructions. These bits are written
with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1,
BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against
Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect (BP2,
BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) instruction is executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0.
Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will
read 0 for these bit locations. It is recommended to mask out the reserved bit when testing the
Status Register. Doing this will ensure compatibility with future devices.
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit is operated in conjunction with the
Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#)
signal allow the device to be put in the Hardware Protected mode (when the Status Register Protect
(SRP) bit is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the
Status Register (SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR)
instruction is no longer accepted for execution.
In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as
normal sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can
only be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to
1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
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EN25F80
fined in Table 3.. The Write Status Register (WRSR) instruction also allows the user to set or reset
the Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status
Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the
Hardware Protected Mode (HPM) is entered.
NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip
Select (CS#) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any
effects on the cycle that is in progress.
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EN25F80
Read Data Bytes at Higher Speed (FAST_READ) (0Bh)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the
memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted
out, at a maximum frequency FR, during the falling edge of Serial Clock (CLK).
The instruction sequence is shown in Figure 10. The first byte addressed can be at any location.
The address is automatically incremented to the next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip
Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
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EN25F80
least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 11. If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed
correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly pro-
grammed at the requested addresses without having any effects on the other bytes of the same
page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is
tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2,
BP1, BP0) bits (see Table 3) is not executed.
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EN25F80
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP2,
BP1, BP0) bits (see Table 3) is not executed.
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EN25F80
Chip Erase (CE) (C7h/60h)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the
instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 14. Chip Select (CS#) must be driven High after the
eighth bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose
duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The
Chip Erase (CE) instruction is ignored if one, or more, sectors are protected.
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EN25F80
When used only to release the device from the power-down state, the instruction is issued by driving
the CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 16.
After the time duration of tRES1 (See AC Characteristics) the device will resume normal operation
and other instructions will be accepted. The CS# pin must remain high during the tRES1 time
duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated
by driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The
Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in Figure 17. The Device ID value for the EN25F80 are listed in Table 5. The Device ID can
be read continuously. The instruction is completed by driving CS# high.
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device
was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is
immediate. If the device was previously in the Deep Power-down mode, though, the transition to the
Standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least
tRES2 (max), as specified in Table 10. Once in the Stand-by Power mode, the device waits to be
selected, so that it can receive, decode and execute instructions.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release from
Deep Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device
ID of the device, and can be applied even if the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program
or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
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EN25F80
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EN25F80
WRSR command will ignore the input data and program LOCK_BIT to 1.
User must clear the protect bits before enter OTP mode.
OTP sector can only be program and erase when LOCK_BIT equal ‘0’ and BP [2:0] = ‘000’. In OTP
mode, user can read other sectors, but program/erase other sectors only allowed when OTP_LOCK
equal ‘0’.
User can use WRDI (04H) command to exit OTP mode.
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EN25F80
Power-up Timing
Note:
1.The parameters are characterized only.
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EN25F80
Table 8. DC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)
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EN25F80
Table 10.100MHz AC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol Alt Parameter Min Typ Max Unit
Serial Clock Frequency for:
FR fC FAST_READ, PP, SE, BE, DP, RES, WREN, D.C. 100 MHz
WRDI, WRSR
fR Serial Clock Frequency for READ, RDSR, RDID D.C. 66 MHz
tCLH 1 Serial Clock High Time 4 ns
tCLL1 Serial Clock Low Time 4 ns
tCLCH2 Serial Clock Rise Time (Slew Rate) 0.1 V / ns
tCHCL 2 Serial Clock Fall Time (Slew Rate) 0.1 V / ns
tSLCH tCSS CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL tCSH CS# High Time 100 ns
tSHQZ 2 tDIS Output Disable Time 6 ns
tCLQX tHO Output Hold Time 0 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tHLCH HOLD# Low Setup Time ( relative to CLK ) 5 ns
tHHCH HOLD# High Setup Time ( relative to CLK ) 5 ns
tCHHH HOLD# Low Hold Time ( relative to CLK ) 5 ns
tCHHL HOLD# High Hold Time ( relative to CLK ) 5 ns
tHLQZ 2 tHZ HOLD# Low to High-Z Output 6 ns
tHHQZ 2 tLZ HOLD# High to Low-Z Output 6 ns
tCLQV tV Output Valid from CLK 8 ns
tWHSL3 Write Protect Setup Time before CS# Low 20 ns
tSHWL3 Write Protect Hold Time after CS# High 100 ns
tDP 2
CS# High to Deep Power-down Mode 3 µs
This Data Sheet may be revised by subsequent versions 23 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
Table 11. 75MHz AC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol Alt Parameter Min Typ Max Unit
Serial Clock Frequency for:
FR fC FAST_READ, PP, SE, BE, DP, RES, WREN, D.C. 75 MHz
WRDI, WRSR
fR Serial Clock Frequency for READ, RDSR, RDID D.C. 66 MHz
tCLH 1 Serial Clock High Time 6 ns
tCLL1 Serial Clock Low Time 6 ns
tCLCH2 Serial Clock Rise Time (Slew Rate) 0.1 V / ns
tCHCL 2 Serial Clock Fall Time (Slew Rate) 0.1 V / ns
tSLCH tCSS CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL tCSH CS# High Time 100 ns
tSHQZ 2 tDIS Output Disable Time 6 ns
tCLQX tHO Output Hold Time 0 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tHLCH HOLD# Low Setup Time ( relative to CLK ) 5 ns
tHHCH HOLD# High Setup Time ( relative to CLK ) 5 ns
tCHHH HOLD# Low Hold Time ( relative to CLK ) 5 ns
tCHHL HOLD# High Hold Time ( relative to CLK ) 5 ns
tHLQZ 2 tHZ HOLD# Low to High-Z Output 6 ns
tHHQZ 2 tLZ HOLD# High to Low-Z Output 6 ns
tCLQV tV Output Valid from CLK 6 ns
tWHSL3 Write Protect Setup Time before CS# Low 20 ns
tSHWL3 Write Protect Hold Time after CS# High 100 ns
tDP 2
CS# High to Deep Power-down Mode 3 µs
This Data Sheet may be revised by subsequent versions 24 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
This Data Sheet may be revised by subsequent versions 25 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
ABSOLUTE MAXIMUM RATINGS
Stresses above the values so mentioned above may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions
up to or above these values. Exposure of the device to the maximum rating values for extended
periods of time may adversely affect the device reliability.
Notes:
1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for
periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O
pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure
below.
Vcc
+1.5V
This Data Sheet may be revised by subsequent versions 26 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
Table 12. DATA RETENTION and ENDURANCE
Input voltage with respect to Vss on all I/O Pins -1.0 V Vcc + 1.0 V
This Data Sheet may be revised by subsequent versions 27 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
PACKAGE MECHANICAL
This Data Sheet may be revised by subsequent versions 28 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
Figure 27. VDFN8 ( 5x6mm )
DIMENSION IN MM
SYMBOL
MIN. NOR MAX
A 0.76 0.80 0.84
A1 0.00 0.02 0.04
A2 --- 0.20 ---
D 5.90 6.00 6.10
E 4.90 5.00 5.10
D2 4.18 4.23 4.28
E2 3.95 4.00 4.05
e --- 1.27 ---
b 0.35 0.40 0.45
L 0.55 0.60 0.65
Note : 1. Coplanarity: 0.1 mm
This Data Sheet may be revised by subsequent versions 29 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
Figure 28. PDIP8
DIMENSION IN INCH
SYMBOL
MIN. NOR MAX
A --- --- 0.210
A1 0.015 --- ---
A2 0.125 0.130 0.135
D 0.355 0.365 0.400
E 0.300 0.310 0.320
E1 0.245 0.250 0.255
L 0.115 0.130 0.150
eB 0.310 0.350 0.375
Θ0 0 7 15
This Data Sheet may be revised by subsequent versions 30 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
ORDERING INFORMATION
EN25F80 - 75 H C P
PACKAGING CONTENT
(Blank) = Conventional
P = RoHS compliant
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
PACKAGE
H = 8-pin 200mil SOP
V = 8-pin VDFN
Q = 8-pin PDIP
SPEED
100 = 100 Mhz
75 = 75 Mhz
This Data Sheet may be revised by subsequent versions 31 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23
EN25F80
Revisions List
This Data Sheet may be revised by subsequent versions 32 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2007/11/23