512 Kbit SPI Serial Flash: Features

512 Kbit SPI Serial Flash
A Microchip Technology Company SST25VF512
Data Sheet
SST serial flash family features a four-wire, SPI-compatible interface that allows
for a low pin-count package occupying less board space and ultimately lowering
total system costs. SST25VF512 SPI serial flash memory is manufactured with
SST's proprietary, high-performance CMOS SuperFlash technology. The split-
gate cell design and thick-oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
Features
• Single 2.7-3.6V Read and Write Operations • End-of-Write Detection
– Software Status
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3 • Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
• 20 MHz Max Clock Frequency without deselecting the device
• Superior Reliability • Write Protection (WP#)
– Endurance: 100,000 Cycles (typical) – Enables/Disables the Lock-Down function of the status
– Greater than 100 years Data Retention register
• Low Power Consumption: • Software Write Protection
– Active Read Current: 7 mA (typical) – Write protection through Block-Protection bits in status
– Standby Current: 8 µA (typical) register
• Flexible Erase Capability • Packages Available
– Uniform 4 KByte sectors – 8-lead SOIC (4.9mm x 6mm)
– Uniform 32 KByte overlay blocks – 8-contact WSON
• Fast Erase and Byte-Program: • All non-Pb (lead-free) devices are RoHS compliant
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
©2011 Silicon Storage Technology, Inc. www.microchip.com DS25076A 10/11
Downloaded from: http://www.datasheetcatalog.com/

Data Sheet
Product Description
SST’s serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count
package occupying less board space and ultimately lowering total system costs. SST25VF512 SPI
serial flash memory is manufactured with SST’s proprietary, high-performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
The SST25VF512 device significantly improves performance, while lowering power consumption. The
total energy consumed is a function of the applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or Program operation is less than alternative
flash memory technologies. The SST25VF512 device operates with a single 2.7-3.6V power supply.
The SST25VF512 device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 1
for the pin assignments.
©2011 Silicon Storage Technology, Inc. DS25076A 10/11

2
Data Sheet
Block Diagram
SuperFlash
X - Decoder Memory
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
Control Logic and
Data Latches
Serial Interface
1192 B1.5
CE# SCK SI SO WP# HOLD#

3
Data Sheet
Pin Description
CE# 1 8 VDD CE# 1 8 VDD
SO 2 7 HOLD# SO 2 7 HOLD#
Top View
Top View
WP# 3 6 SCK WP# 3 6 SCK
VSS 4 5 SI VSS 4 5 SI
1192 08-soic P1.4 1192 08-wson P1a.6
8-lead SOIC 8-contact WSON
Figure 1: Pin Assignments
Table 1: Pin Description

Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI Serial Data To transfer commands, addresses, or data serially into the device.
Input Inputs are latched on the rising edge of the serial clock.
SO Serial Data To transfer data serially out of the device.
Output Data is shifted out on the falling edge of the serial clock.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the
device.
VDD Power Sup- To provide power supply (2.7-3.6V).
ply
VSS Ground
T1.7 25076

4
Data Sheet
Memory Organization
The SST25VF512 SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay
blocks.
Device Operation
The SST25VF512 is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF512 supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3 MODE 3
SCK MODE 0 MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DON T CARE
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB 1192 F34.6
Figure 2: SPI Protocol

5
Data Sheet
Hold Operation
HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode
when the SCK next reaches the active low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be driven active low. See Figure 17 for Hold timing.
SCK
HOLD#
Active Hold Active Hold Active
1192 F44.0
Figure 3: Hold Condition Waveform
Write Protection
The SST25VF512 provides software Write protection. The Write Protect pin (WP#) enables or disables
the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the sta-
tus register provide Write protection to the memory array and the status register. See Table 3 for Block-
Protection description.
Write Protect Pin (WP#)

The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is disabled.
Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction

WP# BPL Execute WRSR Instruction
L 1 Not Allowed
L 0 Allowed
H X Allowed
T2.0 25076

6
Data Sheet
Status Register
The software status register provides status on whether the flash memory array is available for any
Read or Write operation, whether the device is Write enabled, and the state of the memory Write pro-
tection. During an internal Erase or Program operation, the status register may be read only to deter-
mine the completion of an operation in progress. Table 4 describes the function of each bit in the
software status register.
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for
the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is
ready for the next valid operation.
Write Enable Latch (WEL)

The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the
Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset),
it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)
commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming reached its highest memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
Block Protection (BP1, BP0)

The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 3, to be
software protected against any memory Write (Program or Erase) operations. The Write-Status-Regis-
ter (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are both 0. After
power-up, BP1 and BP0 are set to 1.

7
Data Sheet
Block Protection Lock-Down (BPL)
WP# pin driven low (VIL), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it
prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high (VIH),
the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Table 3: Software Status Register Block Protection1

Status
Register Bit Protected
Protection Level BP1 BP0 Memory Area
0 0 0 None
1 0 1 0C000H-0FFFFH
(1/4 Memory Array)2
2 1 0 08000H-0FFFFH
(1/2 Memory Array)
3 1 1 00000H-0FFFFH
(Full Memory Array)
T3.5 25076
1. Default at power-up for BP1 and BP0 is ‘11’.
2. Protection Level 1 (1/4 Memory Array) applies to Byte-Program, Sector-Erase, and Chip-Erase operations.
It does not apply to Block-Erase operations.
Table 4: Software Status Register

Bit Name Function Default at Power-up Read/Write
0 BUSY 1 = Internal Write operation is in progress 0 R
0 = No internal Write operation is in progress
1 WEL 1 = Device is memory Write enabled 0 R
0 = Device is not memory Write enabled
2 BP0 Indicate current level of block write protection (See Table 3) 1 R/W
3 BP1 Indicate current level of block write protection (See Table 3) 1 R/W
4:5 RES Reserved for future use 0 N/A
6 AAI Auto Address Increment Programming status 0 R
1 = AAI programming mode
0 = Byte-Program mode
7 BPL 1 = BP1, BP0 are read-only bits 0 R/W
0 = BP1, BP0 are read/writable
T4.0 25076
Auto Address Increment (AAI)

The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI
programming mode or Byte-Program mode. The default at power up is Byte-Program mode.

8
Data Sheet
Instructions
Instructions are used to Read, Write (Erase and Program), and configure the SST25VF512. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or
Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list
of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of
CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must
be driven low before an instruction is entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high
transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction
in progress and return the device to the standby mode. Instruction commands (Op Code), addresses,
and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions1

Bus Cycle2 1 2 3 4 5
Cycle Type/Operation3,4 SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT
Read 03H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X DOUT
Sector-Erase5,6 20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z - -
Block-Erase5,7 52H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z - -
Chip-Erase6 60H Hi-Z - - - - - - - -
Byte-Program6 02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN Hi-Z
Auto Address Increment AFH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN Hi-Z
(AAI) Program6,8
Read-Status-Register 05H Hi-Z X DOUT - Note9 - Note9 - Note9
(RDSR)
Enable-Write-Status-Reg- 50H Hi-Z - - - - - - - -
ister (EWSR)10
Write-Status-Register 01H Hi-Z Data Hi-Z - - -. - - -
(WRSR)10
Write-Enable (WREN) 06H Hi-Z - - - - - - - -
Write-Disable (WRDI) 04H Hi-Z - - - - - - - -
Read-ID 90H or Hi-Z 00H Hi-Z 00H Hi-Z ID Hi-Z X DOUT12
ABH Addr11
T5.18 25076
1. AMS = Most Significant Address
AMS = A15 for SST25VF512
Address bits above the most significant bit of each density can be VIL or VIH
2. One bus cycle is eight clock periods.
3. Operation: SIN = Serial In, SOUT = Serial Out
4. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable
(WREN) instruction must be executed.
7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.

9
Data Sheet
11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufac-
turer’s and Device ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 48H for SST25VF512
Read
The Read instruction outputs the data starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a low to high transition on CE#. The
internal address pointer will automatically increment until the highest memory address is reached.
Once the highest memory address is reached, the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for 4 Mbit density, once the data from address loca-
tion 7FFFFH had been read, the next output will be from address location 00000H.
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-
A0]. CE# must remain active low for the duration of the Read cycle. See Figure 4 for the Read
sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70
SCK MODE 0
SI 03 ADD. ADD. ADD.

MSB MSB
N N+1 N+2 N+3 N+4
HIGH IMPEDANCE
SO DOUT DOUT DOUT DOUT DOUT
MSB
1192 F10.11
Figure 4: Read Sequence

10
Data Sheet
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait TBP for the completion of
the internal self-timed Byte-Program operation. See Figure 5 for the Byte-Program sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39
SCK MODE 0
SI 02 ADD. ADD. ADD. DIN

MSB MSB MSB LSB
SO HIGH IMPEDANCE
1192 F08.11
Figure 5: Byte-Program Sequence

11
Data Sheet
Auto Address Increment (AAI) Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the
next sequential address location. This feature decreases total programming time when the entire mem-
ory array is to be programmed. An AAI program instruction pointing to a protected memory area will be
ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program
instruction.
Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI program
instruction is initiated by executing an 8-bit command, AFH, followed by address bits [A23-A0]. Follow-
ing the addresses, the data is input sequentially from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the AAI program instruction is executed. The user must poll the BUSY bit in the software
status register or wait TBP for the completion of each internal self-timed Byte-Program cycle. Once the
device completes programming byte, the next sequential address may be program, enter the 8-bit
command, AFH, followed by the data to be programmed. When the last desired byte had been pro-
grammed, execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. After execution of the
WRDI command, the user must poll the Status register to ensure the device completes programming.
See Figure 6 for AAI programming sequence.
There is no wrap mode during AAI programming; once the highest unprotected memory address is
reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0).
TBP TBP
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 33 34 35 36 37 38 39 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
SCK MODE 0
SI AF A[23:16] A[15:8] A[7:0] Data Byte 1 AF Data Byte 2
TBP
CE#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
SI AF Last Data Byte 04 05

Write Disable (WRDI) Read Status Register (RDSR)
Instruction to terminate Instruction to verify end of
AAI Operation AAI Operation
SO DOUT
1192 F39.10
Figure 6: Auto Address Increment (AAI) Program Sequence

12
Data Sheet
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-
Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any
command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, fol-
lowed by address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to
determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait
TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 7 for the Sector-Erase
sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0

MSB MSB
SO HIGH IMPEDANCE
1192 F06.12
Figure 7: Sector-Erase Sequence

13
Data Sheet
Block-Erase
The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-
Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any com-
mand sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed
by address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most significant address) are used to deter-
mine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the
instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the com-
pletion of the internal self-timed Block-Erase cycle. See Figure 8 for the Block-Erase sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0

MSB MSB
SO HIGH IMPEDANCE
1192 F28.11
Figure 8: Block-Erase Sequence
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE
for the completion of the internal self-timed Chip-Erase cycle. See Figure 9 for the Chip-Erase
sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 60
MSB
SO HIGH IMPEDANCE
1192 F07.12
Figure 9: Chip-Erase Sequence

14
Data Sheet
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register
may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in
progress, the Busy bit may be checked before sending any new commands to assure that the new
commands are properly received by the device. CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing
clock cycles until it is terminated by a low to high transition of the CE#. See Figure 10 for the RDSR
instruction sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK MODE 0
SI 05
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB Status
Register Out
1192 F37.7
Figure 10:Read-Status-Register (RDSR) Sequence
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit to 1 allowing Write operations to
occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE#
must be driven high before the WREN instruction is executed.
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 06
MSB
SO HIGH IMPEDANCE
1192 F35.6
Figure 11:Write Enable (WREN) Sequence

15
Data Sheet
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any
new Write operations from occurring. CE# must be driven high before the WRDI instruction is exe-
cuted.
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 04
MSB
SO HIGH IMPEDANCE
1192 F36.6
Figure 12:Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)
instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction
does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Regis-
ter (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.

16
Data Sheet
Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register
(EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-
Status-Register instruction must be executed immediately after the execution of the Enable-Write-Sta-
tus-Register instruction (very next instruction bus cycle). This two-step instruction sequence of the
EWSR instruction followed by the WRSR instruction works like SDP (software data protection) com-
mand structure which prevents any accidental alteration of the status register values. The Write-Sta-
tus-Register instruction will be ignored when WP# is low and BPL bit is set to “1”. When the WP# is
low, the BPL bit can only be set from “0” to “1” to lock-down the status register, but cannot be reset
from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0,
and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP# pin is
driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction,
the BP0, BP1, and BPL bit in the status register can all be altered by the WRSR instruction. In this
case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as
altering the BP0 and BP1 bit at the same time. See Table 2 for a summary description of WP# and BPL
functions. CE# must be driven low before the command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. See Figure 13 for EWSR and WRSR instruc-
tion sequences.
CE#
MODE 3 0 1 2 3 4 5 6 7 MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK MODE 0 MODE 0
STATUS
REGISTER IN
SI 50 01 7 6 5 4 3 2 1 0
MSB MSB MSB
SO HIGH IMPEDANCE
1192 F38.9
Figure 13:Enable-Write-Status-Register (EWSR) and Write-Status-Register (WRSR)

Sequence

17
Data Sheet
Read-ID
The Read-ID instruction identifies the device as SST25VF512 and manufacturer as SST. The device
information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-
A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the
device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and
device ID output data toggles between address 00000H and 00001H until terminated by a low to high
transition on CE#.
Table 6: Product Identification

Address Data
Manufacturer’s ID 00000H BFH
Device ID
SST25VF512 00001H 48H
T6.5 25076
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63
SCK MODE 0
SI 90 or AB 00 00 ADD1
MSB MSB
HIGH
HIGH IMPEDANCE IMPEDANCE
SO BF Device ID BF Device ID
MSB
Note: The manufacturer s and device ID output stream is continuous until terminated by a low to high transition on CE#.
1. 00H will output the manfacturer s ID first and 01H will output device ID first before toggling between the two.
1192 F19.15
Figure 14:Read-ID Sequence

18
Data Sheet
Electrical Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-
ditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
Table 7: Operating Range

Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
T7.1 25076
Table 8: AC Conditions of Test1

Input Rise/Fall Time Output Load
5ns CL = 30 pF
T8.1 25076
1. See Figures 19 and 20
Table 9: DC Operating Characteristics VDD = 2.7-3.6V

Limits
Symbol Parameter Min Max Units Test Conditions
IDDR Read Current 10 mA CE#=0.1 VDD/0.9 VDD@20 MHz, SO=open
IDDW Program and Erase Current 30 mA CE#=VDD
ISB Standby Current 15 µA CE#=VDD, VIN=VDD or VSS
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 0.7 VDD V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T9.9 25076

19
Data Sheet
Table 10:Recommended System Power-up Timings
Symbol Parameter Minimum Units
TPU-READ1 VDD Min to Read Operation 10 µs
TPU-WRITE 1 VDD Min to Write Operation 10 µs
T10.0 25076
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 11:Capacitance (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum
COUT1 Output Pin Capacitance VOUT = 0V 12 pF
CIN 1 Input Capacitance VIN = 0V 6 pF
T11.0 25076
parameter.
Table 12:Reliability Characteristics
Symbol Parameter Minimum Specification Units Test Method
NEND1 Endurance 10,000 Cycles JEDEC Standard A117
TDR1 Data Retention 100 Years JEDEC Standard A103
ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78
T12.1 25076
parameter.

20
Data Sheet
Table 13:AC Operating Characteristics VDD = 2.7-3.6V
Limits
Symbol Parameter Min Max Units
FCLK Serial Clock Frequency 20 MHz
TSCKH Serial Clock High Time 20 ns
TSCKL Serial Clock Low Time 20 ns
TSCKR Serial Clock Rise Time 5 ns
TSCKF Serial Clock Fall Time 5 ns
TCES1 CE# Active Setup Time 20 ns
TCEH1 CE# Active Hold Time 20 ns
TCHS1 CE# Not Active Setup Time 10 ns
TCHH1 CE# Not Active Hold Time 10 ns
TCPH CE# High Time 100 ns
TCHZ CE# High to High-Z Output 20 ns
TCLZ SCK Low to Low-Z Output 0 ns
TDS Data In Setup Time 5 ns
TDH Data In Hold Time 5 ns
THLS HOLD# Low Setup Time 10 ns
THHS HOLD# High Setup Time 10 ns
THLH HOLD# Low Hold Time 15 ns
THHH HOLD# High Hold Time 10 ns
THZ HOLD# Low to High-Z Output 20 ns
TLZ HOLD# High to Low-Z Output 20 ns
TOH Output Hold from SCK Change 0 ns
TV Output Valid from SCK 20 ns
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 100 ms
TBP Byte-Program 20 µs
T13.15 25076
1. Relative to SCK.

21
Data Sheet
TCPH
CE#
TCHH TCES TSCKF TCHS

TCEH
SCK
TDS TDH TSCKR
SI MSB LSB
SO HIGH-Z HIGH-Z
1192 F41.7
Figure 15:Serial Input Timing Diagram
CE#
TSCKL
TSCKH
SCK
TOH
TCLZ TCHZ
SO MSB LSB
TV
SI
1192 F42.6
Figure 16:Serial Output Timing Diagram
CE#
THHH THLS THHS
SCK
THLH
THZ TLZ
SO
SI
HOLD#
1192 F43.1
Figure 17:Hold Timing Diagram

22
Data Sheet
VDD
VDD Max
Chip selection is not allowed.
All commands are rejected by the device.
VDD Min
TPU-READ
Device fully accessible
TPU-WRITE
Time
1192 F45.0
Figure 18:Power-up Timing Diagram

23
Data Sheet
VIHT
VHT VHT
INPUT REFERENCE POINTS OUTPUT
VLT VLT
VILT
1192 F02.1
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measure-
times (10%  90%) are <5 ns.

ment reference points for inputs and outputs are VHT (0.7VDD) and VLT (0.3VDD). Input rise and fall
Note: VHT - VHIGH Test

VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 19:AC Input/Output Reference Waveforms
TO TESTER
TO DUT
CL
1192 F03.0
Figure 20:A Test Load Example

24
Data Sheet
Product Ordering Information
SST 25 VF 512 - 20 - 4C - SAE

XX XX XXX - XX - XX - XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
A = 8 leads or contacts
Package Type
S = SOIC
Q = WSON
Temperature Range
C = Commercial = 0°C to +70°C
Minimum Endurance
4 = 10,000 cycles
Operating Frequency
20 = 20 MHz
Device Density
512 = 512 Kbit
Voltage
V = 2.7-3.6V
Product Series
25 = Serial Peripheral Interface flash
memory
1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST25VF512

SST25VF512-20-4C-SAE SST25VF512-20-4C-QAE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combi-
nations.

25
Data Sheet
Packaging Diagrams
Pin #1
Identifier
TOP VIEW SIDE VIEW
7°
4 places
0.51
5.0 0.33
4.8
1.27 BSC
END VIEW
45° 7°
0.25 4 places
0.10
4.00
3.80
1.75
6.20 1.35 0.25 0°
5.80 0.19
8°
1.27
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, 0.40
08-soic-5x6-SA-8
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. 1mm
Figure 21: 8-lead Small Outline Integrated Circuit (SOIC) 150 mil body width (4.9mm x 6mm)
SST Package Code: SA

26
Data Sheet
TOP VIEW SIDE VIEW BOTTOM VIEW

Pin #1
0.2
Pin #1
Corner
1.27 BSC
5.00 ± 0.10 4.0

0.076 0.48
0.35
3.4
0.70
0.05 Max 0.50
6.00 ± 0.10
0.80
0.70
CROSS SECTION
Note: 1. All linear dimensions are in millimeters (max/min).
2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions. 0.80
3. The external paddle is electrically connected to the 0.70
die back-side and possibly to certain VSS leads. 1mm
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the VSS of the unit. 8-wson-5x6-QA-9.0
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.
Figure 22:8-contact Very-very-thin Small Outline No-lead (WSON)

SST Package Code: QA

27
Data Sheet
Table 14:Revision History
Revision Description Date
00 • Initial release May 2001
01 • Remove Cycles 6 & 7 for Read and Write operations. Jan 2002
• Swapped Ready#/Busy logic. (1 = busy, 0 = not busy)
• Change WP# description
• Added SPI protocol timing diagram.
• Updated all timing diagrams
• Remove all Reset# pin description.
• Add HOLD# description.
• Updated Transient Voltage parameter.
• Add Auto Address Increment (AAI) feature and description.
• Global layout changes.
• Updated all Instruction descriptions.
02 • Removed 15H and 1DH commands for Read ID Apr 2002
03 • Moved the 2 Mbit and 4 Mbit parts to data sheet S71231 Apr 2003
• Moved the 1 Mbit part to data sheet S71233
• Changed AC timing parameter TCES and TCEH timings to 20 ns
• AC timing point corrected in Figure 19
• Added RDSR instruction in Figure 6
• Added System Power-up Timing
• Re-aligned CE# with CLK in Mode 3 for all figures
• Corrected block address range to AMS-A15 in “Block-Erase” on
page 14
04 • Removed Industrial temperature parts Aug 2003
• Updated Figures 2, 4 - 14: Aligned SI waveform with rising edge of
clock
05 • 2004 Data Book Dec 2003
06 • Added footnote 2 to Table 3 on page 8 (PSN: C0250001) Apr 2004
07 • Added RoHS compliance information on page 1 and in the “Product Jan 2005
Ordering Information” on page 25
• Updated the surface mount lead temperature from 240°C to 260°C
and the time from 3 seconds to 10 seconds on page 19.
08 • Revised the Absolute Max. Stress Ratings for Surface Mount Solder Nov 2005
Reflow Temp.
09 • Updated QA package drawing to version 9. Jan 2006
• Removed leaded parts.
A • Applied new document format Oct 2011
• Released document under letter revision system
• Updated Spec number S71192 to DS25076

28
Data Sheet
ISBN:978-1-61341-677-8
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-
nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office locations and information, please see www.microchip.com.
Silicon Storage Technology, Inc.

A Microchip Technology Company
www.microchip.com

29
This datasheet has been downloaded from:
www.DatasheetCatalog.com
Datasheets for electronic components.

512 Kbit SPI Serial Flash: Features

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512 Kbit SPI Serial Flash: Features

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512 Kbit SPI Serial Flash

A Microchip Technology Company SST25VF512

©2011 Silicon Storage Technology, Inc. www.microchip.com DS25076A 10/11

Downloaded from: http://www.datasheetcatalog.com/

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

CE# SCK SI SO WP# HOLD#

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

CE# 1 8 VDD CE# 1 8 VDD

1192 08-soic P1.4 1192 08-wson P1a.6

8-lead SOIC 8-contact WSON

Figure 1: Pin Assignments

Table 1: Pin Description

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Figure 2: SPI Protocol

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Active Hold Active Hold Active

Figure 3: Hold Condition Waveform

Write Protect Pin (WP#)

Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Write Enable Latch (WEL)

Block Protection (BP1, BP0)

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Table 3: Software Status Register Block Protection1

Table 4: Software Status Register

Auto Address Increment (AAI)

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Table 5: Device Operation Instructions1

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

SI 03 ADD. ADD. ADD.

Figure 4: Read Sequence

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

SI 02 ADD. ADD. ADD. DIN

Figure 5: Byte-Program Sequence

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

SI AF A[23:16] A[15:8] A[7:0] Data Byte 1 AF Data Byte 2

SI AF Last Data Byte 04 05

Figure 6: Auto Address Increment (AAI) Program Sequence

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

SI 20 ADD. ADD. ADD.

Figure 7: Sector-Erase Sequence

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

SI 52 ADD. ADD. ADD.

Figure 8: Block-Erase Sequence

Figure 9: Chip-Erase Sequence

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Figure 10:Read-Status-Register (RDSR) Sequence

Figure 11:Write Enable (WREN) Sequence

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Figure 12:Write Disable (WRDI) Sequence

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Figure 13:Enable-Write-Status-Register (EWSR) and Write-Status-Register (WRSR)

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Table 6: Product Identification

Figure 14:Read-ID Sequence

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Table 7: Operating Range

Table 8: AC Conditions of Test1

Table 9: DC Operating Characteristics VDD = 2.7-3.6V

©2011 Silicon Storage Technology, Inc. DS25076A 10/11

Table 11:Capacitance (TA = 25°C, f=1 Mhz, other pins open)

©2011 Silicon Storage Technology, Inc. DS25076A 10/11