512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8)
Many-Time Programmable Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories Data Sheet
FEATURES:
• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 • Fast Byte-Program Operation:
• 2.7-3.6V Read Operation – Byte-Program Time: 10 µs (typical)
• Superior Reliability – Chip Program Time:
0.6 seconds (typical) for SST37VF512
– Endurance: At least 1000 Cycles 1.2 seconds (typical) for SST37VF010
– Greater than 100 years Data Retention
2.4 seconds (typical) for SST37VF020
• Low Power Consumption: 4.8 seconds (typical) for SST37VF040
– Active Current: 10 mA (typical) • Electrical Erase Using Programmer
– Standby Current: 2 µA (typical)
– Does not require UV source
• Fast Read Access Time: – Chip-Erase Time: 100 ms (typical)
– 70 ns • CMOS I/O Compatibility
– 90 ns • JEDEC Standard Byte-wide Flash
• Latched Address and Data EEPROM Pinouts
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP
PRODUCT DESCRIPTION
The SST37VF512/010/020/040 devices are 64K x8 / 128K To meet surface mount and conventional through hole
x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable requirements, the SST37VF512/010/020/040 are offered in
(MTP), low cost flash, manufactured with SST’s proprietary, 32-lead PLCC, 32-lead TSOP, and 32-pin PDIP packages.
high performance CMOS SuperFlash technology. The See Figures 1, 2, and 3 for pinouts.
split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with Device Operation
alternate approaches. The SST37VF512/010/020/040 can
be electrically erased and programmed at least 1000 times The SST37VF512/010/020/040 devices are nonvolatile
using an external programmer, e.g., to change the contents memory solutions that can be used instead of standard
of devices in inventory. The SST37VF512/010/020/040 flash devices if in-system programmability is not required. It
have to be erased prior to programming. These devices is functionally (Read) and pin compatible with industry
conform to JEDEC standard pinouts for byte-wide flash standard flash products.The device supports electrical
memories. Erase operation via an external programmer.
Featuring high performance Byte-Program, the

Read
SST37VF512/010/020/040 provide a typical Byte-Pro-
gram time of 10 µs. Designed, manufactured, and tested The Read operation of the SST37VF512/010/020/040 is
for a wide spectrum of applications, these devices are controlled by CE# and OE#. Both CE# and OE# have to be
offered with an endurance of at least 1000 cycles. Data low for the system to obtain data from the outputs. Once
retention is rated at greater than 100 years. the address is stable, the address access time is equal to
the delay from CE# to output (TCE). Data is available at the
The SST37VF512/010/020/040 are suited for applications output after a delay of TOE from the falling edge of OE#,
that require infrequent writes and low power nonvolatile assuming the CE# pin has been low and the addresses
storage. These devices will improve flexibility, efficiency, have been stable for at least TCE-TOE. When the CE# pin is
and performance while matching the low cost in nonvolatile high, the chip is deselected and a standby current of only
applications that currently use UV-EPROMs, OTPs, and 10 µA (typical) is consumed. OE# is the output control and
mask ROMs. is used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is VIH. Refer
to Figure 4 for the timing diagram.
©2002 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
S71151-02-000 2/02 397 Many-Time Programmable and MTP are trademarks of Silicon Storage Technology, Inc.
1 These specifications are subject to change without notice.
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash
Data Sheet
Byte-Program Operation Product Identification Mode

The SST37VF512/010/020/040 are programmed by using The Product Identification mode identifies the devices as
an external programmer. The programming mode is acti- SST37VF512, SST37VF010, SST37VF020, and
vated by asserting 11.4-12.6V on OE# pin and VIL on CE# SST37VF040 and manufacturer as SST. This mode may
pin. The device is programmed using a single pulse (WE# be accessed by the hardware method. To activate this
pin low) of 10 µs per byte. Using the MTP programming mode, the programming equipment must force VH (11.4-
algorithm, the Byte-Program process continues byte-by- 12.6V) on address A9. Two identifier bytes may then be
byte until the entire chip has been programmed. Refer to sequenced from the device outputs by toggling address
Figure 10 for the flowchart and Figure 6 for the timing dia- line A0. For details, see Table 3 for hardware operation.
gram.
TABLE 1: PRODUCT IDENTIFICATION
Chip-Erase Operation Address Data
The only way to change a data from a “0” to “1” is by Manufacturer’s ID 0000H BFH
electrical erase that changes every bit in the device to Device ID
“1”. The SST37VF512/010/020/040 use an electrical SST37VF512 0001H C4H
Chip-Erase operation. The entire chip can be erased
SST37VF010 0001H C5H
in 100 ms (WE# pin low). In order to activate erase
mode, the 11.4-12.6V is applied to OE# and A9 pins SST37VF020 0001H C6H
while CE# is low. All other address and data pins are SST37VF040 0001H C2H
“don’t care”. The falling edge of WE# will start the T1.2 397
Chip-Erase operation. Once the chip has been erased,

all bytes must be verified for FFH. Refer to Figure 9 for Design Considerations
the flowchart and Figure 5 for the timing diagram. The SST37VF512/010/020/040 should have a 0.1 µF
ceramic high frequency, low inductance capacitor con-
nected between VDD and GND. This capacitor should be
placed as close to the package terminals as possible.
OE# and A9 must remain stable at VH for the entire dura-
tion of an Erase operation. OE# must remain stable at VH
for the entire duration of the Program operation.
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
X-Decoder
Memory
Memory Address Address Buffer

Y-Decoder
CE#
OE# I/O Buffers
Control Logic
A9
WE#
DQ7 - DQ0
397 ILL B1.1
©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

2
Data Sheet
SST37VF512 SST37VF010 SST37VF020 SST37VF040
WE#
VDD
A12
A15
A16
A18
A17
WE#
VDD
A12
A15
A16
A17
NC
WE#
VDD
A12
A15
A16
NC
NC
WE#
VDD
A12
A15
NC
NC
NC
SST37VF040 SST37VF020 SST37VF010 SST37VF512 SST37VF512 SST37VF010 SST37VF020 SST37VF040
4 3 2 1 32 31 30
A7 A7 A7 A7 5 29 A14 A14 A14 A14
A6 A6 A6 A6 6 28 A13 A13 A13 A13
A5 A5 A5 A5 7 27 A8 A8 A8 A8
A4 A4 A4 A4 8 26 A9 A9 A9 A9
32-lead PLCC
A3 A3 A3 A3 9 25 A11 A11 A11 A11
10
Top View 24
A2 A2 A2 A2 OE# OE# OE# OE#
A1 A1 A1 A1 11 23 A10 A10 A10 A10
A0 A0 A0 A0 12 22 CE# CE# CE# CE#
DQ0 DQ0 DQ0 DQ0 13 21 DQ7 DQ7 DQ7 DQ7
14 15 16 17 18 19 20
SST37VF040 SST37VF020 SST37VF010 SST37VF512
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
397 ILL F02a.3

DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

A11 A11 A11 A11 1 32 OE# OE# OE# OE#
A9 A9 A9 A9 2 31 A10 A10 A10 A10
A8 A8 A8 A8 3 30 CE# CE# CE# CE#
A13 A13 A13 A13 4 29 DQ7 DQ7 DQ7 DQ7
A14 A14 A14 A14 5 28 DQ6 DQ6 DQ6 DQ6
A17 A17 NC NC 6 Standard Pinout 27 DQ5 DQ5 DQ5 DQ5
WE# WE# WE# WE# 7 26 DQ4 DQ4 DQ4 DQ4
VDD VDD VDD VDD 8 Top View 25 DQ3 DQ3 DQ3 DQ3
A18 NC NC NC 9 24 VSS VSS VSS VSS
A16 A16 A16 NC 10 23 DQ2 DQ2 DQ2 DQ2
A15 A15 A15 A15 11 22 DQ1 DQ1 DQ1 DQ1
A12 A12 A12 A12 12 21 DQ0 DQ0 DQ0 DQ0
A7 A7 A7 A7 13 20 A0 A0 A0 A0
A6 A6 A6 A6 14 19 A1 A1 A1 A1
A5 A5 A5 A5 15 18 A2 A2 A2 A2
A4 A4 A4 A4 16 17 A3 A3 A3 A3
397 ILL F01.0
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

3
Data Sheet
A18 NC NC NC 1 32 VDD VDD VDD VDD

A16 A16 A16 NC 2 31 WE# WE# WE# WE#
A15 A15 A15 A15 3 30 NC NC A17 A17
A12 A12 A12 A12 4 29 A14 A14 A14 A14
A7 A7 A7 A7 5 28 A13 A13 A13 A13
A6 A6 A6 A6 6 32-pin 27 A8 A8 A8 A8
A5 A5 A5 A5 7 PDIP 26 A9 A9 A9 A9
A4 A4 A4 A4 8 Top View 25 A11 A11 A11 A11
A3 A3 A3 A3 9 24 OE# OE# OE# OE#
A2 A2 A2 A2 10 23 A10 A10 A10 A10
A1 A1 A1 A1 11 22 CE# CE# CE# CE#
A0 A0 A0 A0 12 21 DQ7 DQ7 DQ7 DQ7
VSS VSS VSS VSS 16 17 DQ3 DQ3 DQ3 DQ3
397 ILL F02b.1
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions
AMS1-A0 Address Inputs To provide memory addresses.
DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Program cycles.
The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
WE# Write Enable To program or erase (WE# = VIL pulse during Program or Erase)
OE# Output Enable To gate the data output buffers during Read operation when low
VDD Power Supply To provide 3.0V supply (2.7-3.6V)
VSS Ground
NC No Connection Unconnected pins.
T2.1 397
1. AMS = Most significant address
AMS = A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040

4
Data Sheet
TABLE 3: OPERATION MODES SELECTION
Mode CE# WE# A9 OE# DQ Address
Read VIL VIH AIN VIL DOUT AIN
Output Disable VIL X X VIH High Z AIN
Standby VIH X X X High Z X
Chip-Erase VIL VIL VH VH High Z X
Byte-Program VIL VIL AIN VH DIN AIN
Program/Erase Inhibit X VIH X X High Z X
X X X VIL or VIH High Z/ DOUT X
Product Identification VIL VIH VH VIL Manufacturer’s ID (BFH) AMS2 - A1=VIL, A0=VIL
Device ID1 AMS2 - A1=VIL, A0=VIH
T3.2 397
1. Device ID = C4H for SST37VF512, C5H for SST37VF020, C6H for SST37VF020, and C2H for SST37VF040
2. AMS = Most significant address
AMS = A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040
Note: X = VIL or VIH (or VH in case of OE# and A9)
VH = 11.4-12.6V
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE AC CONDITIONS OF TEST

Range Ambient Temp VDD Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Commercial 0°C to +70°C 2.7-3.6V Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF
See Figures 7 and 8

5
Data Sheet
TABLE 4: READ MODE DC OPERATING CHARACTERISTICS VDD=2.7-3.6V (Ta = 0°C to +70°C (Commercial))
Limits
Symbol Parameter Min Max Units Test Conditions
IDD VDD Read Current Address input=VIL/VIH, at f=1/TRC Min
VDD=VDD Max
12 mA CE#=OE#=VIL, all I/Os open
ISB Standby VDD Current 15 µA CE#=VIHC, VDD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 0.7 VDD V VDD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.3 V IOH=-100 µA, VDD=VDD Min
IH Supervoltage Current for A9 200 µA CE#=OE#=VIL, A9=VH Max
T4.4 397
TABLE 5: PROGRAM/ERASE DC OPERATING CHARACTERISTICS VDD=2.7-3.6V (Ta = 25°C±5°C)
Limits
Symbol Parameter Min Max Units Test Conditions
IDD VDD Erase or Program Current 20 mA CE#=VIL, OE#=VH, VDD=VDD Max, WE#=VIL
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VH Supervoltage for A9 and OE# 11.4 12.6 V
IH Supervoltage Current for A9 and OE# 200 µA OE#=VH Max, A9=VH Max, VDD=VDD Max,
CE# = VIL
T5.1 397
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units
TPU-READ 1 Power-up to Read Operation 100 µs
TPU-WRITE1 Power-up to Write Operation 100 µs
T6.1 397
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum

CI/O 1 I/O Pin Capacitance VI/O = 0V 12 pF
CIN1 Input Capacitance VIN = 0V 6 pF
T7.0 397
TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method
NEND1 Endurance 10,000 Cycles JEDEC Standard A117
TDR1 Data Retention 100 Years JEDEC Standard A103
ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78
T8.3 397

6
Data Sheet
AC CHARACTERISTICS
TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V (Ta = 0°C to +70°C (Commercial))
SST37VF512-70 SST37VF512-90
SST37VF010-70 SST37VF010-90
SST37VF020-70 SST37VF020-90
SST37VF040-70 SST37VF040-90
Symbol Parameter Min Max Min Max Units
TRC Read Cycle Time 70 90 ns
TCE Chip Enable Access Time 70 90 ns
TAA Address Access Time 70 90 ns
TOE Output Enable Access Time 35 45 ns
TCLZ1 CE# Low to Active Output 0 0 ns
TOLZ1 OE# Low to Active Output 0 0 ns
TCHZ1 CE# High to High-Z Output 30 30 ns
TOHZ1 OE# High to High-Z Output 30 30 ns
TOH1 Output Hold from Address Change 0 0 ns
T9.2 397
TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD = 2.7-3.6V (Ta = 25°C±5°C)
Symbol Parameter Min Max Units
TBP Byte-Program Time 12 20 µs
TCES CE# Setup Time 1 ns
TCEH CE# Hold Time 1 ns
TAS Address Setup Time 1 ns
TAH Address Hold Time 1 ns
TDS Data Setup Time 1 ns
TDH Data Hold Time 1 ns
TPRT OE# Rise Time for Program and Erase 1 ns
TVPS OE# Setup Time for Program and Erase 1 ns
TVPH OE# Hold Time for Program and Erase 1 ns
TPW WE# Program Pulse Width 10 15 ns
TEW WE# Erase Pulse Width 100 500 ns
TVR OE#/A9 Recovery Time for Erase 1 ns
TART A9 Rise Time to 12V during Erase 1 ns
TA9S A9 Setup Time during Erase 1 ms
TA9H A9 Hold Time during Erase 1 ms
T10.0 397

7
Data Sheet
TRC TAA
ADDRESS
TCE
CE#
TOE
OE#
VIH TOLZ TOHZ

WE#
TCHZ
TOH
HIGH-Z TCLZ HIGH-Z
DQ7-0
DATA VALID DATA VALID
397 ILL F03.0
FIGURE 4: READ CYCLE TIMING DIAGRAM
ADDRESS
(EXCEPT A9)
CE# TCEH
DQ7-0
VH
TVPS
VDD TVPH
OE#
VSS TPRT
VH TVR
TA9S
A9
VIH
VIL TART
TA9H
TEW
WE#
TCES
397 ILL F04.0
FIGURE 5: CHIP-ERASE TIMING DIAGRAM

8
Data Sheet
TPC
ADDRESS ADDRESS VALID
TAH
TAS
CE# TCEH
TDS
TDH
DQ7-0 DATA VALID

HIGH-Z
VH
TVPS
VDD TPRT
TPW
OE#
VSS TVPH
WE#
TCES 397 ILL F05.0
FIGURE 6: BYTE-PROGRAM TIMING DIAGRAM

9
Data Sheet
VIHT
INPUT VIT REFERENCE POINTS VOT OUTPUT
VILT
397 ILL F06.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 V) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test

VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 7: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
CL
397 ILL F07.1
FIGURE 8: A TEST LOAD EXAMPLE

10
Data Sheet
Start
A9 = VH, OE# = VH
CE# = VIL
Erase 100ms pulse

(WE# = VIL)
WE# = VIH
OE#/A9 = VIL or VIH
Wait TVR Recovery Time
Read Device
No
Compare all
bytes to FF
Yes
Device Passed Device Failed
397 ILL F08.0
FIGURE 9: CHIP-ERASE ALGORITHM

11
Data Sheet
Start
Erase*
OE# = VH
Address = First Location;

Load Data
CE# = VIL
Program 10µs pulse

(WE# = VIL)
Increment Address Last Address? OE# = VIL

No Yes
Wait TVR
Read Device
No
Compare all bytes
to original data
Yes
Device Passed Device Failed
397 ILL F09.1
*See Figure 9
FIGURE 10: BYTE-PROGRAM ALGORITHM

12
Data Sheet
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2

SST37VFxxx - XXX - XX - XX
Package Modifier
H = 32 pins or leads
Package Type
N = PLCC
P = PDIP
W = TSOP (type 1, die up, 8mm x 14mm)
Operating Temperature
C = Commercial = 0° to +70°C
Minimum Endurance
3 = 1,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Device Density
040 = 4 Mbit
020 = 2 Mbit
010 = 1 Mbit
512 = 512 Kbit
Voltage
V = 2.7-3.6V
Valid combinations for SST37VF512

SST37VF512-70-3C-NH SST37VF512-70-3C-WH
SST37VF512-90-3C-NH SST37VF512-90-3C-WH SST37VF512-90-3C-PH



Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

13
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW SIDE VIEW BOTTOM VIEW

.495
.485 .112
Optional .453 .106
Pin #1 .447
Identifier .048 .020 R. .029 x 30˚ .040 R.
.042 2 1 32 MAX. .023 .030
.042 .021
.048 .013
.595 .553 .032 .400 .530
.585 .547 .026 BSC .490
.050
BSC
.015 Min.
.095
.050 .075
BSC .032
.140 .026
.125
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
32-plcc-NH-3
4. Coplanarity: 4 mils.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH

14
Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10 0.27
7.90 0.17
12.50 0.15
12.30 0.05
DETAIL
1.20
max.
0.70
0.50 14.20
13.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min). 1mm 32-tsop-WH-7
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

15
Data Sheet
32
CL
Pin #1 Identifier 1
.625
.600
.550
1.655 .530
.075 7˚
.065 1.645 4 PLCS.
Base
.200
Plane
.170
Seating
Plane
.050
0˚
.015
.012 15˚
.150 .008
.022 .100 BSC .120
.080 .065 .600 BSC
.070 .045 .016
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3
32-PIN PLASTIC DUAL IN-LINE PINS (PDIP)

SST PACKAGE CODE: PH
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com

16

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash

Uploaded by

Copyright:

Available Formats

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash

Uploaded by

Copyright:

Available Formats

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8)

Many-Time Programmable Flash

Featuring high performance Byte-Program, the

Byte-Program Operation Product Identification Mode

Chip-Erase operation. Once the chip has been erased,

FUNCTIONAL BLOCK DIAGRAM

Memory Address Address Buffer

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

SST37VF512 SST37VF010 SST37VF020 SST37VF040

397 ILL F02a.3

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

SST37VF040 SST37VF020 SST37VF010 SST37VF512 SST37VF512 SST37VF010 SST37VF020 SST37VF040

397 ILL F01.0

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

SST37VF040 SST37VF020 SST37VF010 SST37VF512 SST37VF512 SST37VF010 SST37VF020 SST37VF040

A18 NC NC NC 1 32 VDD VDD VDD VDD

397 ILL F02b.1

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP

TABLE 2: PIN DESCRIPTION

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

OPERATING RANGE AC CONDITIONS OF TEST

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

TABLE 5: PROGRAM/ERASE DC OPERATING CHARACTERISTICS VDD=2.7-3.6V (Ta = 25°C±5°C)

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

TABLE 8: RELIABILITY CHARACTERISTICS

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

VIH TOLZ TOHZ

397 ILL F03.0

FIGURE 4: READ CYCLE TIMING DIAGRAM

FIGURE 5: CHIP-ERASE TIMING DIAGRAM

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

ADDRESS ADDRESS VALID

DQ7-0 DATA VALID

FIGURE 6: BYTE-PROGRAM TIMING DIAGRAM

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

INPUT VIT REFERENCE POINTS VOT OUTPUT

397 ILL F06.1

Note: VIT - VINPUT Test

FIGURE 7: AC INPUT/OUTPUT REFERENCE WAVEFORMS

397 ILL F07.1

FIGURE 8: A TEST LOAD EXAMPLE

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

Erase 100ms pulse

OE#/A9 = VIL or VIH

Wait TVR Recovery Time

Device Passed Device Failed

397 ILL F08.0

FIGURE 9: CHIP-ERASE ALGORITHM

©2002 Silicon Storage Technology, Inc. S71151-02-000 2/02 397

Address = First Location;

Program 10µs pulse

Increment Address Last Address? OE# = VIL

Device Passed Device Failed

397 ILL F09.1