39 SF 040
39 SF 040
39 SF 040
SST39SF040
Preliminary Specifications
FEATURES:
• Organized as 512K X8 • Fast Erase and Byte-Program:
• Single 5.0V Read and Write Operations – Sector-Erase Time: 18 ms typical 1
– Chip-Erase Time: 70 ms typical
• Superior Reliability – Byte-Program Time: 14 µs typical
– Endurance: 100,000 Cycles (typical) – Chip Rewrite Time: 8 seconds typical 2
– Greater than 100 years Data Retention • Automatic Write Timing
• Low Power Consumption: – Internal VPP Generation
– Active Current: 10 mA (typical) • End-of-Write Detection 3
– Standby Current: 30 µA (typical)
– Toggle Bit
• Sector-Erase Capability – Data# Polling
– Uniform 4 KByte sectors • TTL I/O Compatibility 4
• Fast Read Access Time:
• JEDEC Standard
– 45, 55 and 70 ns
• Latched Address and Data
– Flash EEPROM Pinouts and command sets 5
• Packages Available
– 32-Pin PDIP
– 32-Pin PLCC 6
– 32-Pin TSOP (8mm x 14mm)
7
PRODUCT DESCRIPTION
gies. The total energy consumed is a function of the
The SST39SF040 is a 512K x8 CMOS Multi-Purpose applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses 8
Flash (MPF) manufactured with SST’s proprietary, high
less current to program and has a shorter erase time, the
performance CMOS SuperFlash technology. The split-
total energy consumed during any Erase or Program
gate cell design and thick oxide tunneling injector attain
better reliability and manufacturability compared with
operation is less than alternative flash technologies. The 9
SST39SF040 device also improves flexibility while lower-
alternate approaches. The SST39SF040 device writes
ing the cost for program, data, and configuration storage
(Program or Erase) with a 5.0V power supply. The
SST39SF040 device conforms to JEDEC standard
applications. 10
pinouts for x8 memories. The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Featuring high performance Byte-Program, the
Program cycles that have occurred. Therefore the sys-
11
SST39SF040 device provides a maximum Byte-Program
time of 20 µsec. The entire memory can be erased and tem software or hardware does not have to be modified
or de-rated as is necessary with alternative flash tech-
programmed byte-by-byte typically in 8 seconds, when
nologies, whose Erase and Program times increase with 12
using interface features such as Toggle Bit or Data#
Polling to indicate the completion of Program operation. accumulated Erase/Program cycles.
To protect against inadvertent write, the SST39SF040 To meet high density, surface mount requirements, the 13
device has on-chip hardware and Software Data Protec- SST39SF040 device is offered in 32-pin TSOP and 32-pin
tion schemes. Designed, manufactured, and tested for a PLCC packages. A 600 mil, 32-pin PDIP is also available.
wide spectrum of applications, the SST39SF040 device See Figures 1, 2 and 3 for pinouts. 14
is offered with a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years. Device Operation
The SST39SF040 device is suited for applications that Commands are used to initiate the memory operation 15
functions of the device. Commands are written to the
require convenient and economical updating of program,
device using standard microprocessor write sequences.
configuration, or data memory. For all system applica-
A command is written by asserting WE# low while
tions, the SST39SF040 device significantly improves
keeping CE# low. The address bus is latched on the falling
16
performance and reliability, while lowering power con-
edge of WE# or CE#, whichever occurs last. The data bus
sumption. The SST39SF040 inherently uses less energy
is latched on the rising edge of WE# or CE#, whichever
during erase and program than alternative flash technolo-
occurs first.
© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.
398-03 3/00 1 These specifications are subject to change without notice.
4 Megabit Multi-Purpose Flash
SST39SF040
Preliminary Specifications
Read Chip-Erase Operation
The Read operation of the SST39SF040 device is con- The SST39SF040 device provides a Chip-Erase opera-
trolled by CE# and OE#, both have to be low for the tion, which allows the user to erase the entire memory
system to obtain data from the outputs. CE# is used for array to the “1’s” state. This is useful when the entire
device selection. When CE# is high, the chip is dese- device must be quickly erased.
lected and only standby power is consumed. OE# is the
The Chip-Erase operation is initiated by executing a six-
output control and is used to gate data from the output
byte Software Data Protection command sequence with
pins. The data bus is in high impedance state when either
Chip-Erase command (10H) with address 5555H in the
CE# or OE# is high. Refer to the Read cycle timing
last byte sequence. The internal Erase operation begins
diagram for further details (Figure 4).
with the rising edge of the sixth WE# or CE#, whichever
occurs first. During the internal Erase operation, the only
Byte-Program Operation
valid read is Toggle Bit or Data# Polling. See Table 4 for
The SST39SF040 device is programmed on a byte-by-
the command sequence, Figure 10 for timing diagram,
byte basis. The Program operation consists of three
and Figure 18 for the flowchart. Any commands written
steps. The first step is the three-byte-load sequence for
during the Chip-Erase operation will be ignored.
Software Data Protection. The second step is to load
byte address and byte data. During the Byte-Program
Write Operation Status Detection
operation, the addresses are latched on the falling edge
The SST39SF040 device provides two software means to
of either CE# or WE#, whichever occurs last. The data is
detect the completion of a Write (Program or Erase) cycle,
latched on the rising edge of either CE# or WE#, which-
in order to optimize the system Write cycle time. The
ever occurs first. The third step is the internal Program
software detection includes two status bits : Data# Polling
operation which is initiated after the rising edge of the
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
fourth WE# or CE#, whichever occurs first. The Program
mode is enabled after the rising edge of WE# which
operation, once initiated, will be completed, within 20 µs.
initiates the internal Program or Erase operation.
See Figures 5 and 6 for WE# and CE# controlled Program
operation timing diagrams and Figure 15 for flowcharts. The actual completion of the nonvolatile write is asyn-
During the Program operation, the only valid reads are chronous with the system; therefore, either a Data#
Data# Polling and Toggle Bit. During the internal Program Polling or Toggle Bit read may be simultaneous with the
operation, the host is free to perform additional tasks. Any completion of the Write cycle. If this occurs, the system
commands written during the internal Program operation may possibly get an erroneous result, i.e., valid data may
will be ignored. appear to conflict with either DQ7 or DQ6. In order to
prevent spurious rejection, if an erroneous result occurs,
Sector-Erase Operation the software routine should include a loop to read the
The Sector-Erase operation allows the system to erase accessed location an additional two (2) times. If both
the device on a sector-by-sector basis. The sector reads are valid, then the device has completed the Write
architecture is based on uniform sector size of 4 KByte. cycle, otherwise the rejection is valid.
The Sector-Erase operation is initiated by executing a
six-byte-command load sequence for Software Data Data# Polling (DQ7)
Protection with Sector-Erase command (30H) and sector When the SST39SF040 device is in the internal Program
address (SA) in the last bus cycle. The address lines operation, any attempt to read DQ7 will produce the
A12-A18 will be used to determine the sector address. complement of the true data. Once the Program opera-
The sector address is latched on the falling edge of the tion is completed, DQ7 will produce true data. The device
sixth WE# pulse , while the command (30H) is latched on is then ready for the next operation. During internal Erase
the rising edge of the sixth WE# pulse. The internal Erase operation, any attempt to read DQ7 will produce a ‘0’.
operation begins after the sixth WE# pulse. The End-of- Once the internal Erase operation is completed, DQ7 will
Erase can be determined using either Data# Polling or produce a ‘1’. The Data# Polling is valid after the rising
Toggle Bit methods. See Figure 9 for timing waveforms. edge of fourth WE# (or CE#) pulse for Program opera-
Any commands written during the Sector-Erase operation tion. For Sector or Chip-Erase, the Data# Polling is valid
will be ignored. after the rising edge of sixth WE# (or CE#) pulse. See
Figure 6 for Data# Polling timing diagram and Figure 16 for
a flowchart.
13
4,194,304 bit
X-Decoder EEPROM
Cell Array
14
A18 - A0 Address Buffers & Latches
Y-Decoder 15
CE#
OE# Control Logic I/O Buffers and Data Latches 16
WE#
DQ7 - DQ0
398 ILL B1.0
A11 1 32 OE#
A9 2 31 A10
A8 3 30 CE#
A13 4 29 DQ7
A14 5 28 DQ6
A17 6 Standard Pinout 27 DQ5
WE# 7 26 DQ4
VDD 8 Top View 25 DQ3
A18 9 24 VSS
A16 10 Die Up 23 DQ2
A15 11 22 DQ1
A12 12 21 DQ0
A7 13 20 A0
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3
A18 1 32 VDD
A16 2 31 WE#
A15 3 30 A17
A12 4 29 A14
A7 5 28 A13
A6 6 32-Pin 27 A8
A5 7 PDIP 26 A9
A4 8 Top View 25 A11
A3 9 24 OE#
A2 10 23 A10
A1 11 22 CE#
A0 12 21 DQ7
DQ0 13 20 DQ6
DQ1 14 19 DQ5
DQ2 15 18 DQ4
VSS 16 17 DQ3
A15
A16
A18
A17
4 3 2 1 32 31 30
A7 5 29 A14
A6 6 28 A13
A5 7 27 A8
A4 8 26 A9
32-Pin PLCC
A3 9 25 A11
10
Top View 24
A2 OE#
A1 11 23 A10
A0 12 22 CE#
DQ0 13 21 DQ7
14 15 16 17 18 19 20
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
11
12
13
14
15
16
10
11
12
13
14
15
16
Note: (1)This
398 PGM T10.0
parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
14
15
16
TRC TAA
ADDRESS A18-0
TCE
CE#
TOE
OE#
TCHZ
TOH
HIGH-Z TCLZ HIGH-Z
DQ7-0
DATA VALID DATA VALID
TBP
OE#
TCH
CE#
TCS
DQ7-0 AA 55 A0 DATA
OE# 4
TCH
WE# 5
TCS
DQ7-0 AA 55 A0 DATA 6
SW0 SW1 SW2 BYTE
(ADDR/DATA) 398 ILL F05.0
7
FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
8
ADDRESS A18-0
10
TCE
CE#
11
TOES
TOEH
OE#
12
TOE
WE# 13
DQ7 D D# D# D 14
398 ILL F06.0
15
16
FIGURE 7: DATA# POLLING TIMING DIAGRAM
ADDRESS A18-0
TCE
CE#
TOE TOES
TOEH
OE#
WE#
DQ6
TSE
SIX-BYTE CODE FOR SECTOR-ERASE
CE#
OE#
TWP
WE#
DQ7-0
AA 55 80 AA 55 30
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 10)
SAX = Sector Address
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are 7
interchageable as long as minmum timings are met. (See Table 10)
8
FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
9
Three-byte sequence for
Software ID Entry 10
ADDRESS A14-0 5555 2AAA 5555 0000 0001
11
CE#
12
OE#
TIDA
13
TWP
WE#
TWPH
14
TAA
DQ7-0
AA 55 90 BF B7
15
SW0 SW1 SW2
DQ7-0 AA 55 F0
TIDA
CE#
OE#
TWP
WE#
T WHP
VIHT 1
INPUT VIT REFERENCE POINTS VOT OUTPUT
2
VILT
3
AC test inputs are driven at VIHT (3.0 V) for a logic “1” and VILT (0 V) for a logic “0”.
Measurement reference points for inputs and outputs are at VIT (1.5 V) and VOT (1.5 V)
Input rise and fall times (10% « 90%) are <5 ns. 4
Note: VIT–VINPUT Test
VOT–VOUTPUT Test
VIHT–VINPUT HIGH Test
VILT–VINPUT LOW Test 5
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
6
7
TEST LOAD EXAMPLE
VDD
8
TO TESTER
9
RL HIGH
10
TO DUT
11
CL RL LOW
12
13
398 ILL F12.0
15
16
Start
Load data: AA
Address: 5555
Load data: 55
Address: 2AAA
Load data: A0
Address: 5555
Load Byte
Address/Byte
Data
Program
Completed
1
Internal Timer Toggle Bit Data# Polling
2
Byte Byte Byte
Program/Erase Program/Erase Program/Erase
Initiated Initiated Initiated 3
4
Read byte Read DQ7
Wait TBP,
TSCE, or TSE 5
No Does DQ6 8
Program/Erase
match? Completed
Yes 9
Program/Erase 10
Completed
398 ILL F14.0
11
12
13
FIGURE 16: WAIT OPTIONS
14
15
16
Chip-Erase Sector-Erase
Command Sequence Command Sequence 1
Load data: AA Load data: AA
Address: 5555 Address: 5555 2
3
Load data: 55 Load data: 55
Address: 2AAA Address: 2AAA
4
6
Load data: AA Load data: AA
Address: 5555 Address: 5555 7
8
Load data: 55 Load data: 55
Address: 2AAA Address: 2AAA
9
11
Wait TSCE Wait TSE
12
15
FIGURE 18: ERASE COMMAND SEQUENCE
16
Package Modifier
H = 32 pins
Numeric = Die modifier
Package Type
P = PDIP
N = PLCC
W = TSOP (die up) (8mm x 14mm)
Temperature Range
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
45 = 45 ns, 55 = 55 ns, 70 = 70 ns
SST39SF040-45-4I-WH SST39SF040-45-4I-NH
SST39SF040-55-4I-WH SST39SF040-55-4I-NH
SST39SF040-70-4I-WH SST39SF040-70-4I-NH
Example : Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
pin 1 index
1
1
CL
2
.600
3
32 .625
.530
.550
.065
.075
1.645
1.655
7˚
4 PLCS.
4
.170
Base Plane
Seating Plane
.200
5
.015 0˚
.050 15˚
.120
.008
.012 6
.150
.070 .045 .016 .100 BSC .600 BSC
.080 .065 .022
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 7
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32.pdipPH-ILL.1
8
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
SST PACKAGE CODE: PH
9
TOP VIEW SIDE VIEW BOTTOM VIEW
10
.485
.495
.106
.447
Optional Pin #1
Identifier .042
.453
.020 R. .023
x 30˚
.112
.030
R.
11
.048 2 1 32 MAX. .029 .040
.042 .013
12
.048 .021
.585 .547 .026 .400 .490
.595 .553 .032 BSC .530
13
.050
BSC.
.015 Min. 14
.075
.050 .095
BSC. .026
.125 .032
.140 15
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
32.PLCC.NH-ILL.1
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
16
32-PIN PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
1.05
PIN # 1 IDENTIFIER 0.95
.50
BSC
.270
8.10 .170
7.90
12.50 0.15
0.05
12.30
0.70
0.50
14.20
13.80
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max). 32.TSOP-WH-ILL.3
3. Coplanarity: 0.1 (±.05) mm.
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873
© 2000 Silicon Storage Technology, Inc. 398-03 3/00
22