Am29LV160D: Data Sheet

Am29LV160D
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new and current designs,
S29AL016D supersedes Am29LV160D and is the factory-recommended migration path for this
device. Please refer to the S29AL016D data sheet for specifications and ordering information. Avail-
ability of this document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information

Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 22358 Revision B Amendment 7 Issue Date May 5, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29LV160D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29AL016D supersedes Am29LV160D and is the factory-recommended migration path
for this device. Please refer to the S29AL016D data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation ■ Embedded Algorithms
— Full voltage range: 2.7 to 3.6 volt read and write — Embedded Erase algorithm automatically
operations for battery-powered applications preprograms and erases the entire chip or any
— Regulated voltage range: 3.0 to 3.6 volt read and combination of designated sectors
write operations and for compatibility with high — Embedded Program algorithm automatically
performance 3.3 volt microprocessors writes and verifies data at specified addresses
■ Manufactured on 0.23 µm process technology ■ Minimum 1,000,000 write cycle guarantee
— Fully compatible with 0.32 µm Am29LV160B device per sector
■ 20-year data retention at 125°C
■ High performance
— Reliable operation for the life of the system
— Access times as fast as 70 ns
■ Package option
■ Ultra low power consumption (typical values at
5 MHz) — 48-ball FBGA
— 200 nA Automatic Sleep mode current — 48-pin TSOP
— 200 nA standby mode current — 44-pin SO
— 9 mA read current ■ CFI (Common Flash Interface) compliant
— 20 mA program/erase current — Provides device-specific information to the
system, allowing host software to easily
■ Flexible sector architecture
reconfigure for different Flash devices
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode) ■ Compatibility with JEDEC standards
— One 8 Kword, two 4 Kword, one 16 Kword, and — Pinout and software compatible with single-
thirty-one 32 Kword sectors (word mode) power supply Flash
— Supports full chip erase — Superior inadvertent write protection
— Sector Protection features: ■ Data# Polling and toggle bits
— A hardware method of locking a sector to prevent any — Provides a software method of detecting program
program or erase operations within that sector or erase operation completion
— Sectors can be locked in-system or via programming
equipment ■ Ready/Busy# pin (RY/BY#)
Temporary Sector Unprotect feature allows code — Provides a hardware method of detecting
changes in previously locked sectors program or erase cycle completion (not available
on 44-pin SO)
■ Unlock Bypass Program Command
■ Erase Suspend/Erase Resume
— Reduces overall programming time when issuing
multiple program command sequences — Suspends an erase operation to read data from,
or program data to, a sector that is not being
■ Top or bottom boot block configurations erased, then resumes the erase operation
available
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Publication# 22358 Rev: B Amendment: 7
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Issue Date: May 5, 2006
D A T A S H E E T
GENERAL DESCRIPTION
The Am29LV160D is a 16 Mbit, 3.0 Volt-only Flash The host system can detect whether a program or
memory organized as 2,097,152 bytes or 1,048,576 erase operation is complete by observing the RY/BY#
words. The device is offered in 48-ball FBGA, 44-pin pin, or by reading the DQ7 (Data# Polling) and DQ6
SO, and 48-pin TSOP packages. The word-wide data (toggle) status bits. After a program or erase cycle
(x16) appears on DQ15–DQ0; the byte-wide (x8) data has been completed, the device is ready to read array
appears on DQ7–DQ0. This device is designed to be data or accept another command.
programmed in-system with the standard system 3.0
The sector erase architecture allows memory sec-
volt VCC supply. A 12.0 V VPP or 5.0 VCC are not re-
tors to be erased and reprogrammed without affecting
quired for write or erase operations. The device can
the data contents of other sectors. The device is fully
also be programmed in standard
erased when shipped from the factory.
EPROM programmers.
Hardware data protection measures include a low
The device offers access times of 70, 90, and 120 ns,
VCC detector that automatically inhibits write opera-
allowing high speed microprocessors to operate with-
tions during power transitions. The hardware sector
out wait states. To eliminate bus contention the device
protection feature disables both program and erase
has separate chip enable (CE#), write enable (WE#)
operations in any combination of the sectors of mem-
and output enable (OE#) controls.
o r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a
The device requires only a single 3.0 volt power sup- programming equipment.
ply for both read and write functions. Internally
The Erase Suspend/Erase Resume feature enables
generated and regulated voltages are provided for the
the user to put erase on hold for any period of time to
program and erase operations.
read data from, or program data to, any sector that is
The Am29LV160D is entirely command set compatible not selected for erasure. True background erase can
with the JEDEC single-power-supply Flash stan- thus be achieved.
dard. Commands are written to the command register
The hardware RESET# pin terminates any operation
using standard microprocessor write timings. Register
in progress and resets the internal state machine to
contents serve as input to an internal state-machine
reading array data. The RESET# pin may be tied to
that controls the erase and programming circuitry.
the system reset circuitry. A system reset would thus
Write cycles also internally latch addresses and data
also reset the device, enabling the system micropro-
needed for the programming and erase operations.
cessor to read the boot-up firmware from the Flash
Reading data out of the device is similar to reading
memory.
from other Flash or EPROM devices.
The device offers two power-saving features. When
Device programming occurs by executing the program
addresses have been stable for a specified amount of
command sequence. This initiates the Embedded
time, the device enters the automatic sleep mode.
Program algorithm—an internal algorithm that auto-
The system can also place the device into the
matically times the program pulse widths and verifies
standby mode. Power consumption is greatly re-
proper cell margin. The Unlock Bypass mode facili-
duced in both these modes.
tates faster programming times by requiring only two
write cycles to program data instead of four. AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
Device erasure occurs by executing the erase com-
highest levels of quality, reliability and cost effective-
mand sequence. This initiates the Embedded Erase
ness. The device electrically erases all bits within a
algorithm—an internal algorithm that automatically
sector simultaneously via Fowler-Nordheim tunnel-
preprograms the array (if it is not already programmed)
ing. The data is programmed using hot electron
before executing the erase operation. During erase,
injection.
the device automatically times the erase pulse widths
and verifies proper cell margin.
2 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 DQ3: Sector Erase Timer ....................................................... 28
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 10. Write Operation Status ................................................... 28
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. Maximum Negative Overshoot Waveform ...................... 30
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 8. Maximum Positive Overshoot Waveform........................ 30
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 30
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 1. Am29LV160D Device Bus Operations ................................9 Figure 9. ICC1 Current vs. Time (Showing Active and
Word/Byte Configuration .......................................................... 9 Automatic Sleep Currents) ............................................................. 32
Figure 10. Typical ICC1 vs. Frequency ........................................... 32
Requirements for Reading Array Data ..................................... 9
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Writing Commands/Command Sequences .............................. 9
Figure 11. Test Setup..................................................................... 33
Program and Erase Operation Status .................................... 10 Table 11. Test Specifications ......................................................... 33
Standby Mode ........................................................................ 10 Figure 12. Input Waveforms and Measurement Levels ................. 33
Automatic Sleep Mode ........................................................... 10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
RESET#: Hardware Reset Pin ............................................... 11 Read Operations .................................................................... 34
Output Disable Mode .............................................................. 11 Figure 13. Read Operations Timings ............................................. 34
Table 2. Sector Address Tables (Am29LV160DT) ..........................12 Hardware Reset (RESET#) .................................................... 35
Table 3. Sector Address Tables (Am29LV160DB) ..........................13 Figure 14. RESET# Timings .......................................................... 35
Autoselect Mode ..................................................................... 14 Word/Byte Configuration (BYTE#) ........................................ 36
Table 4. Am29LV160D Autoselect Codes (High Voltage Method) ..14 Figure 15. BYTE# Timings for Read Operations............................ 36
Sector Protection/Unprotection ............................................... 14 Figure 16. BYTE# Timings for Write Operations............................ 36
Temporary Sector Unprotect .................................................. 15 Erase/Program Operations ..................................................... 37
Figure 1. Temporary Sector Unprotect Operation........................... 15 Figure 17. Program Operation Timings.......................................... 38
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 16 Figure 18. Chip/Sector Erase Operation Timings .......................... 39
Common Flash Memory Interface (CFI) . . . . . . . 17 Figure 19. Data# Polling Timings (During Embedded Algorithms). 40
Table 5. CFI Query Identification String ..........................................17 Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 40
Table 6. System Interface String .....................................................18 Figure 21. DQ2 vs. DQ6 for Erase and
Table 7. Device Geometry Definition ..............................................18 Erase Suspend Operations ............................................................ 41
Table 8. Primary Vendor-Specific Extended Query ........................19 Figure 22. Temporary Sector Unprotect/Timing Diagram .............. 41
Hardware Data Protection ...................................................... 19 Figure 23. Sector Protect/Unprotect Timing Diagram .................... 42
Low VCC Write Inhibit .............................................................. 19 Figure 24. Alternate CE# Controlled Write Operation Timings ...... 44
Write Pulse “Glitch” Protection ............................................... 19 Erase and Programming Performance . . . . . . . 45
Logical Inhibit .......................................................................... 19 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 45
Power-Up Write Inhibit ............................................................ 19 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 45
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Reading Array Data ................................................................ 20 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 46
Reset Command ..................................................................... 20 TS 048—48-Pin Standard TSOP ............................................ 46
Autoselect Command Sequence ............................................ 20 TSR048—48-Pin Reverse TSOP ........................................... 47
Word/Byte Program Command Sequence ............................. 20 FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
Unlock Bypass Command Sequence ..................................... 21 8 x 9 mm ................................................................................ 48
Figure 3. Program Operation .......................................................... 21 SO 044—44-Pin Small Outline Package ................................ 49
Chip Erase Command Sequence ........................................... 21 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 50
Sector Erase Command Sequence ........................................ 22 Revision A (January 1999) ..................................................... 50
Erase Suspend/Erase Resume Commands ........................... 22 Revision A+1 (April 19, 1999) ................................................. 50
Figure 4. Erase Operation............................................................... 23 Revision B (November 23, 1999) ............................................ 50
Command Definitions ............................................................. 24 Revision B+1 (February 22, 2000) .......................................... 50
Table 9. Am29LV160D Command Definitions ................................24 Revision B+2 (November 7, 2000) ......................................... 50
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 25 Revision B+3 (November 10, 2000) ....................................... 50
DQ7: Data# Polling ................................................................. 25 Revision B+4 (April 5, 2004) ................................................... 50
Figure 5. Data# Polling Algorithm ................................................... 25 Revision B+5 (June 4, 2004) .................................................. 50
RY/BY#: Ready/Busy# ........................................................... 26 Revision B+6 (October 7, 2004) ............................................. 50
DQ6: Toggle Bit I .................................................................... 26 Revision B7 (May 5, 2006) ..................................................... 50
DQ2: Toggle Bit II ................................................................... 26
Reading Toggle Bits DQ6/DQ2 .............................................. 26
Figure 6. Toggle Bit Algorithm......................................................... 27
22358B7 May 5, 2006 Am29LV160D 3

D A T A S H E E T
PRODUCT SELECTOR GUIDE

Family Part Number Am29LV160D
Speed Option Voltage Range: VCC = 2.7–3.6 V -70 -90 -120
Max access time, ns (tACC) 70 90 120
Max CE# access time, ns (tCE) 70 90 120
Max OE# access time, ns (tOE) 30 35 50
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
RY/BY# DQ0–DQ15 (A-1)
VCC
Sector Switches
VSS
Erase Voltage Input/Output
RESET# Generator Buffers
WE# State
Control
BYTE#
Command
Register
PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
Logic
OE#
Y-Decoder Y-Gating
STB
Address Latch
VCC Detector Timer
X-Decoder Cell Matrix
A0–A19
4 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
CONNECTION DIAGRAMS
A15 1 48 A16
A14 2 47 BYTE#
A13 3 46 VSS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
A19 9 40 DQ5
NC 10 39 DQ12
WE# 11 Standard TSOP 38 DQ4
RESET# 12 37 VCC
NC 13 36 DQ11
NC 14 35 DQ3
RY/BY# 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 VSS
A2 23 26 CE#
A1 24 25 A0
A16 1 48 A15
BYTE# 2 47 A14
VSS 3 46 A13
DQ15/A-1 4 45 A12
DQ7 5 44 A11
DQ14 6 43 A10
DQ6 7 42 A9
DQ13 8 41 A8
DQ5 9 40 A19
DQ12 10 39 NC
DQ4 11 38 WE#
VCC 12 Reverse TSOP 37 RESET#
DQ11 13 36 NC
DQ3 14 35 NC
DQ10 15 34 RY/BY#
DQ2 16 33 A18
DQ9 17 32 A17
DQ1 18 31 A7
DQ8 19 30 A6
DQ0 20 29 A5
OE# 21 28 A4
VSS 22 27 A3
CE# 23 26 A2
A0 24 25 A1
22358B7 May 5, 2006 Am29LV160D 5

D A T A S H E E T
CONNECTION DIAGRAMS
RESET# 1 44 WE#
A18 2 43 A19
A17 3 42 A8
A7 4 41 A9
A6 5 40 A10
A5 6 39 A11
A4 7 38 A12
A3 8 37 A13
A2 9 36 A14
A1 10 35 A15
A0 11 34 A16
CE# 12 SO 33 BYTE#
VSS 13 32 VSS
OE# 14 31 DQ15/A-1
DQ0 15 30 DQ7
DQ8 16 29 DQ14
DQ1 17 28 DQ6
DQ9 18 27 DQ13
DQ2 19 26 DQ5
DQ10 20 25 DQ12
DQ3 21 24 DQ4
DQ11 22 23 VCC
FBGA
Top View, Balls Facing Down
A6 B6 C6 D6 E6 F6 G6 H6
A13 A12 A14 A15 A16 BYTE# DQ15/A-1 VSS
A5 B5 C5 D5 E5 F5 G5 H5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
A4 B4 C4 D4 E4 F4 G4 H4
WE# RESET# NC A19 DQ5 DQ12 VCC DQ4
A3 B3 C3 D3 E3 F3 G3 H3
RY/BY# NC A18 NC DQ2 DQ10 DQ11 DQ3
A2 B2 C2 D2 E2 F2 G2 H2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A1 B1 C1 D1 E1 F1 G1 H1
A3 A4 A2 A1 A0 CE# OE# VSS
Special Handling Instructions Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.
Special handling is required for Flash Memor y
The package and/or data integrity may be compromised
products in FBGA packages.
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
6 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
PIN CONFIGURATION LOGIC SYMBOL

A0–A19 =20 addresses
20
DQ0–DQ14 =15 data inputs/outputs A0–A19 16 or 8
DQ15/A-1 =DQ15 (data input/output, word mode),
DQ0–DQ15
A-1 (LSB address input, byte mode)
(A-1)
BYTE# =Selects 8-bit or 16-bit mode
CE# =Chip enable CE#
OE# =Output enable OE#
WE# =Write enable
WE#
RESET# =Hardware reset pin
RESET#
RY/BY# =Ready/Busy output
(N/A SO 044) BYTE# RY/BY#
(N/A SO 044)
VCC =3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS =Device ground
NC =Pin not connected internally
22358B7 May 5, 2006 Am29LV160D 7

D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV160D T -70 E C
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
D = Commercial (0°C to +70°C) with Pb-Free Package
I = Industrial (–40°C to +85°C)
F = Industrial (–40°C to +85°C) with Pb-Free Package
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
WC = 48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 8 x 9 mm package (FBC048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29LV160D
16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations For TSOP and SO Packages Valid Combinations for FBGA Packages
Am29LV160DT-70, Order Number Package Marking

Am29LV160DB-70
Am29LV160DT-70, L160DT70V,
EC, EI, ED, EF
Am29LV160DT-90, Am29LV160DB-70 L160DB70V
FC, FI WCC,
Am29LV160DB-90
SC, SI, SD, SF Am29LV160DT-90, WCI, L160DT90V, C, I,
Am29LV160DT-120, Am29LV160DB-90 WCD, L160DB90V D, F
Am29LV160DB-120 WCF
Am29LV160DT-120, L160DT12V,
Am29LV160DB-120 L160DB12V
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
8 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
DEVICE BUS OPERATIONS

This section describes the requirements and use of the register serve as inputs to the internal state ma-
the device bus operations, which are initiated through chine. The state machine outputs dictate the function
the internal command register. The command register of the device. Table 1 lists the device bus operations,
itself does not occupy any addressable memory loca- the inputs and control levels they require, and the re-
tion. The register is composed of latches that store the sulting output. The following subsections describe
commands, along with the address and data informa- each of these operations in further detail.
tion needed to execute the command. The contents of
Table 1. Am29LV160D Device Bus Operations

DQ8–DQ15
Addresses DQ0– BYTE# BYTE#
Operation CE# OE# WE# RESET# (Note 1) DQ7 = VIH = VIL
Read L L H H AIN DOUT DOUT DQ8–DQ14 = High-Z,
Write L H L H AIN DIN DIN DQ15 = A-1
VCC ± VCC ±
Standby X X X High-Z High-Z High-Z
0.3 V 0.3 V
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Address,
Sector Protect (Note 2) L H L VID A6 = L, A1 = H, DIN X X
A0 = L
Sector Address,
Sector Unprotect (Note 2) L H L VID A6 = H, A1 = H, DIN X X
A0 = L
Temporary Sector
X X X VID AIN DIN DIN High-Z
Unprotect
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration The internal state machine is set for reading array
data upon device power-up, or after a hardware re-
The BYTE# pin controls whether the device data I/O
set. This ensures that no spurious alteration of the
pins DQ15–DQ0 operate in the byte or word configura-
memory content occurs during the power transition.
tion. If the BYTE# pin is set at logic ‘1’, the device is in
No command is necessary in this mode to obtain
word configuration, DQ15–DQ0 are active and con-
array data. Standard microprocessor read cycles that
trolled by CE# and OE#.
assert valid addresses on the device address inputs
If the BYTE# pin is set at logic ‘0’, the device is in byte produce valid data on the device data outputs. The
configuration, and only data I/O pins DQ0–DQ7 are device remains enabled for read access until the
active and controlled by CE# and OE#. The data I/O command register contents are altered.
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
See “Reading Array Data” for more information. Refer
used as an input for the LSB (A-1) address function.
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. ICC1 in
Requirements for Reading Array Data
the DC Characteristics table represents the active cur-
To read array data from the outputs, the system must rent specification for reading array data.
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control Writing Commands/Command Sequences
and gates array data to the output pins. WE# should re-
To write a command or command sequence (which in-
main at VIH. The BYTE# pin determines whether the
cludes programming data to the device and erasing
device outputs array data in words or bytes.
22358B7 May 5, 2006 Am29LV160D 9

D A T A S H E E T
sectors of memory), the system must drive WE# and and ICC read specifications apply. Refer to “Write Op-
CE# to VIL, and OE# to VIH. eration Status” for more information, and to “AC
Characteristics” for timing diagrams.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
Standby Mode
words. Refer to “Word/Byte Configuration” for more
information. When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
The device features an Unlock Bypass mode to facili- this mode, current consumption is greatly reduced,
tate faster programming. Once the device enters the and the outputs are placed in the high impedance
Unlock Bypass mode, only two write cycles are re- state, independent of the OE# input.
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section The device enters the CMOS standby mode when the
has details on programming data to the device using CE# and RESET# pins are both held at VCC ± 0.3 V.
b o t h s t a n d a r d a n d U n l o ck B y p a s s c o m m a n d (Note that this is a more restricted voltage range than
sequences. V IH .) If CE# and RESET# are held at V IH , but not
within VCC ± 0.3 V, the device will be in the standby
An erase operation can erase one sector, multiple sec- mode, but the standby current will be greater. The de-
tors, or the entire device. Tables 2 and 3 indicate the vice requires standard access time (t CE ) for read
address space that each sector occupies. A “sector access when the device is in either of these standby
address” consists of the address bits required to modes, before it is ready to read data.
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire If the device is deselected during erasure or program-
chip, or suspending/resuming the erase operation. ming, the device draws active current until the
operation is completed.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The In the DC Characteristics table, ICC3 and ICC4 repre-
system can then read autoselect codes from the inter- sents the standby current specification.
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in Automatic Sleep Mode
this mode. Refer to the “Autoselect Mode” and “Au- The automatic sleep mode minimizes Flash device
toselect Command Sequence” sections for more energy consumption. The device automatically
information. enables this mode when addresses remain stable for
ICC2 in the DC Characteristics table represents the ac- tACC + 30 ns. The automatic sleep mode is
tive current specification for the write mode. The “AC independent of the CE#, WE#, and OE# control
Characteristics” section contains timing specification signals. Standard address access timings provide new
tables and timing diagrams for write operations. data when addresses are changed. While in sleep
mode, output data is latched and always available to
Program and Erase Operation Status the system. I CC4 in the DC Characteristics table
repr esen ts th e automatic sleep mo de cu rren t
During an erase or program operation, the system specification.
may check the status of the operation by reading the
status bits on DQ7–DQ0. Standard read cycle timings
10 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
RESET#: Hardware Reset Pin memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the If RESET# is asserted during a program or erase op-
system drives the RESET# pin to VIL for at least a pe- eration, the RY/BY# pin remains a “0” (busy) until the
riod of tRP, the device immediately terminates any internal reset operation is complete, which requires a
operation in progress, tristates all data output pins, time of t READY (during Embedded Algorithms). The
and ignores all read/write attempts for the duration of system can thus monitor RY/BY# to deter mine
the RESET# pulse. The device also resets the internal whether the reset operation is complete. If RESET#
state machine to reading array data. The operation is asserted when a program or erase operation is not
that was interrupted should be reinitiated once the de- executing (RY/BY# pin is “1”), the reset operation is
vice is ready to accept another command sequence, completed within a time of tREADY (not during Embed-
to ensure data integrity. ded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device Refer to the AC Characteristics tables for RESET# pa-
draws CMOS standby current (I CC4 ). If RESET# is rameters and to Figure 14 for the timing diagram.
held at VIL but not within VSS±0.3 V, the standby cur-
rent will be greater. Output Disable Mode
The RESET# pin may be tied to the system reset cir- When the OE# input is at VIH, output from the device is
cuitry. A system reset would thus also reset the Flash disabled. The output pins are placed in the high im-
pedance state.
22358B7 May 5, 2006 Am29LV160D 11

D A T A S H E E T
Table 2. Sector Address Tables (Am29LV160DT)
Sector Size Address Range (in hexadecimal)

(Kbytes/
Sector A19 A18 A17 A16 A15 A14 A13 A12 Kwords) Byte Mode (x8) Word Mode (x16)
SA0 0 0 0 0 0 X X X 64/32 000000–00FFFF 00000–07FFF
SA1 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF
SA2 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF
SA3 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF
SA4 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF
SA5 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF
SA6 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF
SA7 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF
SA8 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF
SA9 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF
SA10 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF
SA11 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF
SA12 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF
SA13 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF
SA14 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF
SA15 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF
SA16 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF
SA17 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF
SA18 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF
SA19 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF
SA20 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF
SA21 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF
SA22 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF
SA23 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF
SA24 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF
SA25 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF
SA26 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF
SA27 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF
SA28 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF
SA29 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF
SA30 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF
SA31 1 1 1 1 1 0 X X 32/16 1F0000–1F7FFF F8000–FBFFF
SA32 1 1 1 1 1 1 0 0 8/4 1F8000–1F9FFF FC000–FCFFF
SA33 1 1 1 1 1 1 0 1 8/4 1FA000–1FBFFF FD000–FDFFF
SA34 1 1 1 1 1 1 1 X 16/8 1FC000–1FFFFF FE000–FFFFF
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.
12 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
Table 3. Sector Address Tables (Am29LV160DB)
Sector Size Address Range (in hexadecimal)

(Kbytes/
Sector A19 A18 A17 A16 A15 A14 A13 A12 Kwords) Byte Mode (x8) Word Mode (x16)
SA0 0 0 0 0 0 0 0 X 16/8 000000–003FFF 00000–01FFF
SA1 0 0 0 0 0 0 1 0 8/4 004000–005FFF 02000–02FFF
SA2 0 0 0 0 0 0 1 1 8/4 006000–007FFF 03000–03FFF
SA3 0 0 0 0 0 1 X X 32/16 008000–00FFFF 04000–07FFF
SA4 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF
SA5 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF
SA6 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF
SA7 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF
SA8 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF
SA9 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF
SA10 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF
SA11 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF
SA12 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF
SA13 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF
SA14 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF
SA15 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF
SA16 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF
SA17 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF
SA18 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF
SA19 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF
SA20 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF
SA21 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF
SA22 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF
SA23 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF
SA24 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF
SA25 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF
SA26 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF
SA27 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF
SA28 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF
SA29 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF
SA30 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF
SA31 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF
SA32 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF
SA33 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF
SA34 1 1 1 1 1 X X X 64/32 1F0000–1FFFFF F8000–FFFFF
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.
22358B7 May 5, 2006 Am29LV160D 13

D A T A S H E E T
Autoselect Mode Table 4. In addition, when verifying sector protection,

the sector address must appear on the appropriate
The autoselect mode provides manufacturer and de-
highest order address bits (see Tables 2 and 3). Table
vice identification, and sector protection verification,
4 shows the remaining address bits that are don’t
through identifier codes output on DQ7–DQ0. This
care. When all necessary bits have been set as re-
mode is primarily intended for programming equip-
quired, the programming equipment may then read the
m e n t t o a u t o m a t i c a l l y m a t c h a d ev i c e t o b e
corresponding identifier code on DQ7-DQ0.
programmed with its corresponding programming al-
gorithm. However, the autoselect codes can also be To access the autoselect codes in-system, the host
accessed in-system through the command register. system can issue the autoselect command via the
command register, as shown in Table 9. This method
When using programming equipment, the autoselect
does not require VID. See “Command Definitions” for
mode requires VID (11.5 V to 12.5 V) on address pin
details on using the autoselect mode.
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. Am29LV160D Autoselect Codes (High Voltage Method)

A19 A11 A8 A5 DQ8 DQ7
to to to to to to
Description Mode CE# OE# WE# A12 A10 A9 A7 A6 A2 A1 A0 DQ15 DQ0
Manufacturer ID: AMD L L H X X VID X L X L L X 01h
Device ID: Word L L H 22h C4h

Am29LV160D X X VID X L X L H
(Top Boot Block) Byte L L H X C4h
Device ID: Word L L H 22h 49h

Am29LV160D X X VID X L X L H
(Bottom Boot Block) Byte L L H X 49h
01h
X
(protected)
Sector Protection Verification L L H SA X VID X L X H L
00h
X
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.
Sector Protection/Unprotection The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
The hardware sector protection feature disables both
programming equipment. Figure 2 shows the algo-
program and erase operations in any sector. The hard-
rithms and Figure 23 shows the timing diagram. This
ware sector unprotection feature re-enables both
method uses standard microprocessor bus cycle tim-
program and erase operations in previously protected
ing. For sector unprotect, all unprotected sectors must
sectors.
first be protected prior to the first sector unprotect
The device is shipped with all sectors unprotected. write cycle.
AMD offers the option of programming and protecting
The alternate method intended only for programming
sectors at its factory prior to shipping the device
equipment requires VID on address pin A9 and OE#.
through AMD’s ExpressFlash™ Service. Contact an
This method is compatible with programmer routines
AMD representative for details.
written for earlier 3.0 volt-only AMD flash devices. De-
It is possible to determine whether a sector is pro- tails on this method are provided in a supplement,
tected or unprotected. See “Autoselect Mode” for publication number 21468. Contact an AMD represen-
details. tative to request a copy.
Sector protection/unprotection can be implemented
via two methods.
14 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
Temporary Sector Unprotect

This feature allows temporary unprotection of previ- START
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected RESET# = VID
sectors can be programmed or erased by selecting the (Note 1)
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
Perform Erase or
protected again. Figure shows the algorithm, and Fig- Program Operations
ure 22 shows the timing diagrams, for this feature.
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
22358B7 May 5, 2006 Am29LV160D 15

D A T A S H E E T
START START
Protect all sectors:

PLSCNT = 1 The indicated portion PLSCNT = 1
of the sector protect
RESET# = VID algorithm must be RESET# = VID
performed for all
unprotected sectors
Wait 1 μs Wait 1 μs
prior to issuing the
first sector
unprotect address
No First Write No
Temporary Sector First Write Temporary Sector
Unprotect Mode Cycle = 60h? Cycle = 60h? Unprotect Mode
Yes Yes
Set up sector
No All sectors
address
protected?
Sector Protect:
Yes
Write 60h to sector
address with Set up first sector
A6 = 0, A1 = 1, address
A0 = 0
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
Verify Sector A6 = 1, A1 = 1,
Protect: Write 40h A0 = 0
to sector address Reset
Increment with A6 = 0, PLSCNT = 1 Wait 15 ms
PLSCNT A1 = 1, A0 = 0
Verify Sector
Read from
Unprotect: Write
sector address
40h to sector
with A6 = 0,
address with
A1 = 1, A0 = 0 Increment A6 = 1, A1 = 1,
No PLSCNT A0 = 0
No
PLSCNT Data = 01h? Read from
= 25? sector address
with A6 = 1,
Yes A1 = 1, A0 = 0
Yes No
Set up
next sector
Yes No
PLSCNT address
Protect another Data = 00h?
Device failed = 1000?
sector?
No Yes Yes
Remove VID
from RESET# Last sector No
Device failed verified?
Write reset
Yes
command
Remove VID
Sector Protect Sector Protect
Sector Unprotect from RESET#
Algorithm complete Algorithm

Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
16 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
COMMON FLASH MEMORY INTERFACE tem can read CFI information at the addresses given
(CFI) in Tables 5–8. In word mode, the upper address bits
(A7–MSB) must be all zeros. To terminate reading CFI
The Common Flash Interface (CFI) specification out- data, the system must write the reset command.
lines device and host system software interrogation
handshake, which allows specific vendor-specified The system can also write the CFI query command
software algorithms to be used for entire families of when the device is in the autoselect mode. The device
devices. Software support can then be device-inde- enters the CFI query mode, and the system can read
pendent, JEDEC ID-independent, and forward- and CFI data at the addresses given in Tables 5–8. The
backward-compatible for the specified flash device system must write the reset command to return the
families. Flash vendors can standardize their existing device to the autoselect mode.
interfaces for long-term compatibility. For further information, please refer to the CFI Specifi-
This device enters the CFI Query mode when the sys- cation and CFI Publication 100, available via the World
tem writes the CFI Query command, 98h, to address Wide Web at http://www.amd.com/products/nvd/over-
55h in word mode (or address AAh in byte mode), any v i ew / c f i . h t m l . A l t e r n a t i ve l y, c o n t a c t a n A M D
time the device is ready to read array data. The sys- representative for copies of these documents.
Table 5. CFI Query Identification String

Addresses Addresses
(Word Mode) (Byte Mode) Data Description
10h 20h 0051h

11h 22h 0052h Query Unique ASCII string “QRY”
12h 24h 0059h
13h 26h 0002h

Primary OEM Command Set
14h 28h 0000h
15h 2Ah 0040h

Address for Primary Extended Table
16h 2Ch 0000h
17h 2Eh 0000h

Alternate OEM Command Set (00h = none exists)
18h 30h 0000h
19h 32h 0000h

Address for Alternate OEM Extended Table (00h = none exists)
1Ah 34h 0000h
22358B7 May 5, 2006 Am29LV160D 17

D A T A S H E E T
Table 6. System Interface String

Addresses Addresses
VCC Min. (write/erase)

1Bh 36h 0027h
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)

1Ch 38h 0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs
20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 42h 000Ah Typical timeout per individual block erase 2N ms
22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 46h 0005h Max. timeout for byte/word write 2N times typical
24h 48h 0000h Max. timeout for buffer write 2N times typical
25h 4Ah 0004h Max. timeout per individual block erase 2N times typical
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7. Device Geometry Definition

Addresses Addresses
27h 4Eh 0015h Device Size = 2N byte
28h 50h 0002h

Flash Device Interface description (refer to CFI publication 100)
29h 52h 0000h
2Ah 54h 0000h Max. number of byte in multi-byte write = 2N

2Bh 56h 0000h (00h = not supported)
2Ch 58h 0004h Number of Erase Block Regions within device
2Dh 5Ah 0000h

2Eh 5Ch 0000h Erase Block Region 1 Information
2Fh 5Eh 0040h (refer to the CFI specification or CFI publication 100)
30h 60h 0000h
31h 62h 0001h

32h 64h 0000h
Erase Block Region 2 Information
33h 66h 0020h
34h 68h 0000h
35h 6Ah 0000h

36h 6Ch 0000h
37h 6Eh 0080h
38h 70h 0000h
39h 72h 001Eh

3Ah 74h 0000h
3Bh 76h 0000h
3Ch 78h 0001h
18 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
Table 8. Primary Vendor-Specific Extended Query

Addresses Addresses
40h 80h 0050h

41h 82h 0052h Query-unique ASCII string “PRI”
42h 84h 0049h
43h 86h 0031h Major version number, ASCII
44h 88h 0030h Minor version number, ASCII
Address Sensitive Unlock

45h 8Ah 0000h
0 = Required, 1 = Not Required
Erase Suspend
46h 8Ch 0002h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
47h 8Eh 0001h
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect

48h 90h 0001h
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme

49h 92h 0004h 01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
4Ah 94h 0000h
Burst Mode Type

4Bh 96h 0000h
Page Mode Type

4Ch 98h 0000h
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Hardware Data Protection

The command sequence requirement of unlock cycles Write Pulse “Glitch” Protection
for programming or erasing provides data protection Noise pulses of less than 5 ns (typical) on OE#, CE#
against inadvertent writes (refer to Table 9 for com- or WE# do not initiate a write cycle.
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure Logical Inhibit
or programming, which might otherwise be caused by
Write cycles are inhibited by holding any one of OE# =
spurious system level signals during VCC power-up
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
and power-down transitions, or from system noise.
CE# and WE# must be a logical zero while OE# is a
Low VCC Write Inhibit logical one.
When VCC is less than VLKO, the device does not ac- Power-Up Write Inhibit
cept any write cycles. This protects data during VCC
If WE# = CE# = VIL and OE# = VIH during power up,
power-up and power-down. The command register
the device does not accept commands on the rising
and all internal program/erase circuits are disabled,
edge of WE#. The internal state machine is automati-
and the device resets. Subsequent writes are ignored
cally reset to reading array data on power-up.
until VCC is greater than VLKO. The system must pro-
vide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO.
22358B7 May 5, 2006 Am29LV160D 19

D A T A S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or se- The reset command may be written between the se-
quences into the command register initiates device quence cycles in an autoselect command sequence.
operations. Table 9 defines the valid register command Once in the autoselect mode, the reset command
sequences. Writing incorrect address and data val- must be written to return to reading array data (also
ues or writing them in the improper sequence resets applies to autoselect during Erase Suspend).
the device to reading array data.
If DQ5 goes high during a program or erase operation,
All addresses are latched on the falling edge of WE# writing the reset command returns the device to read-
or CE#, whichever happens later. All data is latched on ing array data (also applies during Erase Suspend).
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the Autoselect Command Sequence
“AC Characteristics” section. The autoselect command sequence allows the host
system to access the manufacturer and devices
Reading Array Data codes, and determine whether or not a sector is pro-
The device is automatically set to reading array data t e c t e d . Ta bl e 9 s h ow s t h e a d d r e s s a n d d a t a
after device power-up. No commands are required to requirements. This method is an alternative to that
retrieve data. The device is also ready to read array shown in Table 4, which is intended for PROM pro-
data after completing an Embedded Program or Em- grammers and requires VID on address bit A9.
bedded Erase algorithm.
The autoselect command sequence is initiated by writ-
After the device accepts an Erase Suspend com- ing two unlock cycles, followed by the autoselect
mand, the device enters the Erase Suspend mode. command. The device then enters the autoselect
The system can read array data using the standard mode, and the system may read at any address any
read timings, except that if it reads at an address number of times, without initiating another command
within erase-suspended sectors, the device outputs sequence.
status data. After completing a programming opera-
A read cycle at address XX00h retrieves the manufac-
tion in the Erase Suspend mode, the system may
turer code. A read cycle at address XX01h returns the
once again read array data with the same exception.
device code. A read cycle containing a sector address
See “Erase Suspend/Erase Resume Commands” for
(SA) and the address 02h in word mode (or 04h in
more information on this mode.
byte mode) returns 01h if that sector is protected, or
The system must issue the reset command to re-en- 00h if it is unprotected. Refer to Tables 2 and 3 for
able the device for reading array data if DQ5 goes valid sector addresses.
high, or while in the autoselect mode. See the “Reset
The system must write the reset command to exit the
Command” section, next.
autoselect mode and return to reading array data.
See also “Requirements for Reading Array Data” in
the “Device Bus Operations” section for more informa- Word/Byte Program Command Sequence
tion. The Read Operations table provides the read The system may program the device by word or byte,
parameters, and Figure 13 shows the timing diagram. depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
Reset Command command sequence is initiated by writing two unlock
Writing the reset command to the device resets the write cycles, followed by the program set-up com-
device to reading array data. Address bits are don’t mand. The program address and data are written
care for this command. next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
The reset command may be written between the se-
controls or timings. The device automatically gener-
quence cycles in an erase command sequence before
ates the program pulses and verifies the programmed
erasing begins. This resets the device to reading array
cell margin. Table 9 shows the address and data re-
data. Once erasure begins, however, the device ig-
q u i r e m e n t s fo r t h e by t e p r o gra m c o m m a n d
nores reset commands until the operation is complete.
sequence.
The reset command may be written between the se-
When the Embedded Program algorithm is complete,
quence cycles in a program command sequence
the device then returns to reading array data and ad-
before programming begins. This resets the device to
dresses are no longer latched. The system can
reading array data (also applies to programming in
determine the status of the program operation by
Erase Suspend mode). Once programming begins,
using DQ7, DQ6, or RY/BY#. See “Write Operation
however, the device ignores reset commands until the
Status” for information on these status bits.
operation is complete.
20 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
Any commands written to the device during the Em- 90h; the second cycle the data 00h. Addresses are
bedded Program Algorithm are ignored. Note that a don’t care for both cycles. The device then returns to
hardware reset immediately terminates the program- reading array data.
m i n g o p e ra t i o n . T h e B y t e P r o gra m c o m m a n d
Figure 3 illustrates the algorithm for the program oper-
sequence should be reinitiated once the device has
ation. See the Erase/Program Operations table in “AC
reset to reading array data, to ensure data integrity.
Characteristics” for parameters, and to Figure 17 for
Programming is allowed in any sequence and across timing diagrams.
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was START
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
Write Program
Unlock Bypass Command Sequence Command Sequence
The unlock bypass feature allows the system to pro-

gram bytes or words to the device faster than using the
standard program command sequence. The unlock Data Poll
bypass command sequence is initiated by first writing from System
Embedded
two unlock cycles. This is followed by a third write Program
cycle containing the unlock bypass command, 20h. algorithm
The device then enters the unlock bypass mode. A in progress
two-cycle unlock bypass program command sequence Verify Data?
is all that is required to program in this mode. The first No
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the Yes
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
No
with the initial two unlock cycles required in the stan- Increment Address Last Address?
dard program command sequence, resulting in faster
total programming time. Table 9 shows the require-
ments for the command sequence. Yes
During the unlock bypass mode, only the Unlock By- Programming
pass Program and Unlock Bypass Reset commands Completed
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
Note: See Table 9 for program command sequence.
Figure 3. Program Operation the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
Chip Erase Command Sequence ded Erase algor ithm are ignored . Note that a
Chip erase is a six bus cycle operation. The chip erase hardware reset during the chip erase operation im-
command sequence is initiated by writing two unlock mediately terminates the operation. The Chip Erase
cycles, followed by a set-up command. Two additional command sequence should be reinitiated once the de-
unlock write cycles are then followed by the chip erase vice has returned to reading array data, to ensure data
command, which in turn invokes the Embedded Erase integrity.
algorithm. The device does not require the system to The system can determine the status of the erase op-
preprogram prior to erase. The Embedded Erase algo- eration by using DQ7, DQ6, DQ2, or RY/BY#. See
rithm automatically preprograms and verifies the entire “Write Operation Status” for information on these sta-
memory for an all zero data pattern prior to electrical tus bits. When the Embedded Erase algorithm is
erase. The system is not required to provide any con- complete, the device returns to reading array data and
trols or timings during these operations. Table 9 shows addresses are no longer latched.
22358B7 May 5, 2006 Am29LV160D 21

D A T A S H E E T
Figure 4 illustrates the algorithm for the erase opera- status of the erase operation by using DQ7, DQ6,
tion. See the Erase/Program Operations tables in “AC DQ2, or RY/BY#. (Refer to “Write Operation Status” for
Characteristics” for parameters, and to Figure 18 for information on these status bits.)
timing diagrams.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
Sector Erase Command Sequence
the “AC Characteristics” section for parameters, and to
Sector erase is a six bus cycle operation. The sector Figure 18 for timing diagrams.
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad- Erase Suspend/Erase Resume
ditional unlock write cycles are then followed by the Commands
address of the sector to be erased, and the sector
erase command. Table 9 shows the address and data The Erase Suspend command allows the system to in-
r e q u i r e m e n t s fo r t h e s e c t o r e r a s e c o m m a n d terrupt a sector erase operation and then read data
sequence. from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
The device does not require the system to preprogram erase operation, including the 50 µs time-out period
the memory prior to erase. The Embedded Erase al- during the sector erase command sequence. The
gorithm automatically programs and verifies the sector Erase Suspend command is ignored if written during
for an all zero data pattern prior to electrical erase. the chip erase operation or Embedded Program algo-
The system is not required to provide any controls or rithm. Writing the Erase Suspend command during the
timings during these operations. Sector Erase time-out immediately terminates the
After the command sequence is written, a sector erase time-out period and suspends the erase operation. Ad-
time-out of 50 µs begins. During the time-out period, dresses are “don’t-cares” when writing the Erase
additional sector addresses and sector erase com- Suspend command.
mands may be written. Loading the sector erase buffer When the Erase Suspend command is written during a
may be done in any sequence, and the number of sec- sector erase operation, the device requires a maxi-
tors may be from one sector to all sectors. The time mum of 20 µs to suspend the erase operation.
between these additional cycles must be less than 50 However, when the Erase Suspend command is writ-
µs, otherwise the last address and command might ten during the sector erase time-out, the device
not be accepted, and erasure may begin. It is recom- immediately terminates the time-out period and sus-
mended that processor interrupts be disabled during pends the erase operation.
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector After the erase operation has been suspended, the
Erase command is written. If the time between addi- system can read array data from or program data to
tional sector erase commands can be assumed to be any sector not selected for erasure. (The device “erase
less than 50 µs, the system need not monitor DQ3. suspends” all sectors selected for erasure.) Normal
Any command other than Sector Erase or Erase read and write timings and command definitions apply.
Suspend during the time-out period resets the de- Reading at any address within erase-suspended sec-
vice to reading array data. The system must rewrite tors produces status data on DQ7–DQ0. The system
the command sequence and any additional sector ad- can use DQ7, or DQ6 and DQ2 together, to determine
dresses and commands. if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
The system can monitor DQ3 to determine if the sec- status bits.
tor erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the After an erase-suspended program operation is com-
rising edge of the final WE# pulse in the command plete, the system can once again read array data
sequence. within non-suspended sectors. The system can deter-
mine the status of the program operation using the
Once the sector erase operation has begun, only the DQ7 or DQ6 status bits, just as in the standard pro-
Erase Suspend command is valid. All other com- gram operation. See “Write Operation Status” for more
mands are ignored. Note that a hardware reset information.
during the sector erase operation immediately termi-
nates the operation. The Sector Erase command The system may also write the autoselect command
sequence should be reinitiated once the device has re- sequence when the device is in the Erase Suspend
turned to reading array data, to ensure data integrity. mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
When the Embedded Erase algorithm is complete, the codes are not stored in the memory array. When the
device returns to reading array data and addresses device exits the autoselect mode, the device reverts to
are no longer latched. The system can determine the the Erase Suspend mode, and is ready for another
22 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
valid operation. See “Autoselect Command Sequence”

for more information.
The system must write the Erase Resume command START
(address bits are “don’t care”) to exit the erase sus-
pend mode and continue the sector erase operation.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after Write Erase
the device has resumed erasing. Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 9 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
22358B7 May 5, 2006 Am29LV160D 23

D A T A S H E E T
Command Definitions
Table 9. Am29LV160D Command Definitions
Bus Cycles (Notes 2–5)
Cycles
Command
Sequence First Second Third Fourth Fifth Sixth
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Word 555 2AA 555
Manufacturer ID 4 AA 55 90 X00 01
Byte AAA 555 AAA
Autoselect (Note 8)
Device ID, Word 555 2AA 555 X01 22C4

4 AA 55 90
Top Boot Block Byte AAA 555 AAA X02 C4
Device ID, Word 555 2AA 555 X01 2249
4 AA 55 90
Bottom Boot Block Byte AAA 555 AAA X02 49
(SA) XX00
Word 555 2AA 555
Sector Protect Verify X02 XX01
4 AA 55 90
(Note 9) (SA) 00
Byte AAA 555 AAA
X04 01
Word 55
CFI Query (Note 10) 1 98
Byte AA
Word 555 2AA 555
Program 4 AA 55 A0 PA PD
Byte AAA 555 AAA
Word 555 2AA 555
Unlock Bypass 3 AA 55 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 11) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 12) 2 XXX 90 XXX 00
Word 555 2AA 555 555 2AA 555
Chip Erase 6 AA 55 80 AA 55 10
Byte AAA 555 AAA AAA 555 AAA
Word 555 2AA 555 555 2AA
Sector Erase 6 AA 55 80 AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 13) 1 XXX B0
Erase Resume (Note 14) 1 XXX 30
Legend:
X = Don’t care PD = Data to be programmed at location PA. Data latches on the rising
RA = Address of the memory location to be read. edge of WE# or CE# pulse, whichever happens first.
RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal. 9. The data is 00h for an unprotected sector and 01h for a
3. Except for the read cycle and the fourth cycle of the autoselect protected sector. See “Autoselect Command Sequence” for
command sequence, all bus cycles are write cycles. more information.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command 10. Command is valid when device is ready to read array data or
cycles. when device is in autoselect mode.
5. Address bits A19–A11 are don’t cares for unlock and 11. The Unlock Bypass command is required prior to the Unlock
command cycles, unless SA or PA required. Bypass Program command.
6. No unlock or command cycles required when reading array 12. The Unlock Bypass Reset command is required to return to
data. reading array data when the device is in the unlock bypass
mode.
7. The Reset command is required to return to reading array data
when device is in the autoselect mode, or if DQ5 goes high 13. The system may read and program in non-erasing sectors, or
(while the device is providing status data). enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector
8. The fourth cycle of the autoselect command sequence is a
erase operation.
read cycle.
14. The Erase Resume command is valid only during the Erase Suspend mode.
24 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
WRITE OPERATION STATUS

The device provides several bits to determine the sta- Table 10 shows the outputs for Data# Polling on DQ7.
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, Figure 5 shows the Data# Polling algorithm.
and RY/BY#. Table 10 and the following subsections
describe the functions of these bits. DQ7, RY/BY#,
and DQ6 each offer a method for determining whether
a program or erase operation is complete or in
progress. These three bits are discussed first. START
DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or Read DQ7–DQ0
Addr = VA
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command
sequence.
Yes
During the Embedded Program algorithm, the device DQ7 = Data?
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em- No
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
No
must provide the program address to read valid status DQ5 = 1?
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading Yes
array data.
During the Embedded Erase algorithm, Data# Polling Read DQ7–DQ0
produces a “0” on DQ7. When the Embedded Erase Addr = VA
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum out-
put described for the Embedded Program algorithm:
Yes
the erase function changes all the bits in a sector to DQ7 = Data?
“1”; prior to this, the device outputs the “complement,”
or “0.” The system must provide an address within any
of the sectors selected for erasure to read valid status No
information on DQ7.
After an erase command sequence is written, if all FAIL PASS
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the Notes:
device returns to reading array data. If not all selected 1. VA = Valid address for programming. During a sector
sectors are protected, the Embedded Erase algorithm erase operation, a valid address is an address within
erases the unprotected sectors, and ignores the se- any sector selected for erasure. During chip erase, a
lected sectors that are protected. valid address is any non-protected sector address.
When the system detects DQ7 has changed from the 2. DQ7 should be rechecked even if DQ5 = “1” because
complement to true data, it can read valid data at DQ7 may change simultaneously with DQ5.
DQ7–DQ0 on the following read cycles. This is be-
cause DQ7 may change asynchronously with DQ0– Figure 5. Data# Polling Algorithm
DQ6 while Output Enable (OE#) is asserted low. Fig-
ure 19, Data# Po l l i n g Timings
(During Embedded Algorithms), in the “AC Character-
istics” section illustrates this.
22358B7 May 5, 2006 Am29LV160D 25

D A T A S H E E T
RY/BY#: Ready/Busy# DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-
The RY/BY# is a dedicated, open-drain output pin that
gram algorithm is complete.
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after Table 10 shows the outputs for Toggle Bit I on DQ6.
the rising edge of the final WE# pulse in the command Figure 6 shows the toggle bit algorithm in flowchart
sequence. Since RY/BY# is an open-drain output, sev- form, and the section “Reading Toggle Bits DQ6/DQ2”
eral RY/BY# pins can be tied together in parallel with a explains the algorithm. Figure 20 in the “AC Character-
pull-up resistor to VCC. (The RY/BY# pin is not avail- istics” section shows the toggle bit timing diagrams.
able on the 44-pin SO package.) Figure 21 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
If the output is low (Busy), the device is actively eras-
“DQ2: Toggle Bit II”.
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
DQ2: Toggle Bit II
(Ready), the device is ready to read array data (includ-
ing during the Erase Suspend mode), or is in the The “Toggle Bit II” on DQ2, when used with DQ6, indi-
standby mode. cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
Table 10 shows the outputs for RY/BY#. Figures 13, or whether that sector is erase-suspended. Toggle Bit
14, 17 and 18 shows RY/BY# for read, reset, program, II is valid after the rising edge of the final WE# pulse in
and erase operations, respectively. the command sequence.
DQ6: Toggle Bit I DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
Toggle Bit I on DQ6 indicates whether an Embedded
sure. (The system may use either OE# or CE# to
Program or Erase algorithm is in progress or com-
control the read cycles.) But DQ2 cannot distinguish
plete, or whether the device has entered the Erase
whether the sector is actively erasing or is erase-sus-
Suspend mode. Toggle Bit I may be read at any ad-
pended. DQ6, by comparison, indicates whether the
dress, and is valid after the rising edge of the final
device is actively erasing, or is in Erase Suspend, but
WE# pulse in the command sequence (prior to the
cannot distinguish which sectors are selected for era-
program or erase operation), and during the sector
sure. Thus, both status bits are required for sector and
erase time-out.
mode information. Refer to Table 10 to compare out-
During an Embedded Program or Erase algorithm op- puts for DQ2 and DQ6.
eration, successive read cycles to any address cause
Figure 6 shows the toggle bit algorithm in flowchart
DQ6 to toggle. (The system may use either OE# or
form, and the section “Reading Toggle Bits DQ6/DQ2”
CE# to control the read cycles.) When the operation is
explains the algorithm. See also the DQ6: Toggle Bit I
complete, DQ6 stops toggling.
subsection. Figure 20 shows the toggle bit timing dia-
After an erase command sequence is written, if all gram. Figure 21 shows the differences between DQ2
sectors selected for erasing are protected, DQ6 tog- and DQ6 in graphical form.
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Reading Toggle Bits DQ6/DQ2
Embedded Erase algorithm erases the unprotected Refer to Figure 6 for the following discussion. When-
sectors, and ignores the selected sectors that are ever the system initially begins reading toggle bit
protected. status, it must read DQ7–DQ0 at least twice in a row
The system can use DQ6 and DQ2 together to deter- to determine whether a toggle bit is toggling. Typi-
mine whether a sector is actively erasing or is erase- cally, the system would note and store the value of
suspended. When the device is actively erasing (that the toggle bit after the first read. After the second
is, the Embedded Erase algorithm is in progress), DQ6 read, the system would compare the new value of the
toggles. When the device enters the Erase Suspend toggle bit with the first. If the toggle bit is not toggling,
mode, DQ6 stops toggling. However, the system must the device has completed the program or erase oper-
also use DQ2 to determine which sectors are erasing ation. The system can read array data on DQ7–DQ0
or erase-suspended. Alternatively, the system can use on the following read cycle.
DQ7 (see the subsection on “DQ7: Data# Polling”). However, if after the initial two read cycles, the system
If a program address falls within a protected sector, determines that the toggle bit is still toggling, the sys-
DQ6 toggles for approximately 1 µs after the program tem also should note whether the value of DQ5 is high
command sequence is written, then returns to reading (see the section on DQ5). If it is, the system should
array data. then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
26 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-
vice did not complete the operation successfully, and
the system must write the reset command to return to START
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has Read DQ7–DQ0
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the
previous paragraph. Alternatively, it may choose to Read DQ7–DQ0 (Note 1)
perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it re-
turns to determine the status of the operation (top of
Figure 6). Toggle Bit No
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
(Notes
Twice 1, 2)
Toggle Bit No
= Toggle?
Yes
Program/Erase
Operation Not Program/Erase
Complete, Write Operation Complete
Reset Command
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 6. Toggle Bit Algorithm
22358B7 May 5, 2006 Am29LV160D 27

D A T A S H E E T
DQ5: Exceeded Timing Limits tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
DQ5 indicates whether the program or erase time has
mand. When the time-out is complete, DQ3 switches
exceeded a specified internal pulse count limit. Under
from “0” to “1.” The system may ignore DQ3 if the sys-
these conditions DQ5 produces a “1.” This is a failure
tem can guarantee that the time between additional
condition that indicates the program or erase cycle
sector erase commands will always be less than 50
was not successfully completed.
μs. See also the “Sector Erase Command Sequence”
The DQ5 failure condition may appear if the system section.
tries to program a “1” to a location that is previously
After the sector erase command sequence is written,
programmed to “0.” Only an erase operation can
the system should read the status on DQ7 (Data# Poll-
change a “0” back to a “1.” Under this condition, the
ing) or DQ6 (Toggle Bit I) to ensure the device has
device halts the operation, and when the operation
accepted the command sequence, and then read
has exceeded the timing limits, DQ5 produces a “1.”
DQ3. If DQ3 is “1”, the internally controlled erase cycle
Under both these conditions, the system must issue has begun; all further commands (other than Erase
the reset command to return the device to reading Suspend) are ignored until the erase operation is com-
array data. plete. If DQ3 is “0”, the device will accept additional
sector erase commands. To ensure the command has
DQ3: Sector Erase Timer been accepted, the system software should check the
After writing a sector erase command sequence, the status of DQ3 prior to and following each subsequent
system may read DQ3 to determine whether or not an sector erase command. If DQ3 is high on the second
erase operation has begun. (The sector erase timer status check, the last command might not have been
does not apply to the chip erase command.) If addi- accepted. Table 10 shows the outputs for DQ3.
Table 10. Write Operation Status

DQ7 DQ5 DQ2
Operation (Note 2) DQ6 (Note 1) DQ3 (Note 2) RY/BY#
Standard Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase
1 No toggle 0 N/A Toggle 1
Erase Suspended Sector
Suspend Reading within Non-Erase
Data Data Data Data Data 1
Mode Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
28 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS

Storage Temperature VCC (Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C A9, OE#, and RESET# (Note 2) . –0.5 V to +12.5 V
Ambient Temperature All other pins (Note 1) . . . . . . . –0.5 V to VCC+0.5 V
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Output Short Circuit Current (Note 3) . . . . . . . 200 mA
Voltage with Respect to Ground
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions,
input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input voltage on pins A9, OE#, and RESET# 3. No more than one output may be shorted to ground at a
is -0.5 V. During voltage transitions, A9, OE#, and RESET# time. Duration of the short circuit should not be greater than
may overshoot VSS to –2.0 V for periods of up to 20 ns. See one second.
Figure 7. Maximum DC input voltage on pin A9 is +12.5 V
which may overshoot to 14.0 V for periods up to 20 ns.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections
of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect
device reliability.
22358B7 May 5, 2006 Am29LV160D 29

D A T A S H E E T
20 ns 20 ns 20 ns
+0.8 V VCC
+2.0 V
–0.5 V VCC
+0.5 V
–2.0 V
2.0 V
20 ns
20 ns 20 ns
Figure 7. Maximum Negative Figure 8. Maximum Positive

Overshoot Waveform Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
30 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
VIN = VSS to VCC,

ILI Input Load Current ±1.0 µA
VCC = VCC max
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
VOUT = VSS to VCC,

ILO Output Leakage Current ±1.0 µA
VCC = VCC max
CE# = VIL, OE# = VIH, 5 MHz 9 16

Byte Mode 1 MHz 2 4
VCC Active Read Current
ICC1 mA
(Notes 1, 2) 5 MHz 9 16
CE# = VIL, OE# = VIH,
Word Mode 1 MHz 2 4
VCC Active Write Current

ICC2 CE# = VIL, OE# = VIH 20 30 mA
(Notes 2, 3, 5)
ICC3 VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC±0.3 V 0.2 5 µA
VCC Standby Current During Reset

ICC4 RESET# = VSS ± 0.3 V 0.2 5 µA
(Notes 2, 4)
Automatic Sleep Mode VIH = VCC ± 0.3 V;

ICC5 0.2 5 µA
(Notes 2, 4, 6) VIL = VSS ± 0.3 V
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
Voltage for Autoselect and

VID VCC = 3.3 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 IOH = -2.0 mA, VCC = VCC min 0.85 x VCC V

Output High Voltage
VOH2 IOH = -100 µA, VCC = VCC min VCC–0.4
VLKO Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
6. Not 100% tested.
22358B7 May 5, 2006 Am29LV160D 31

D A T A S H E E T
DC CHARACTERISTICS (Continued)
Zero Power Flash
25
Supply Current in mA
20
15
10
0
0 500 1000 1500 2000 2500 3000 3500 4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
3.6 V
8
Supply Current in mA
2.7 V
0
1 2 3 4 5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
32 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
TEST CONDITIONS
Table 11. Test Specifications
3.3 V
Test Condition -70 -90, -120 Unit
2.7 kΩ Output Load 1 TTL gate

Device
Under Output Load Capacitance, CL
30 100 pF
Test (including jig capacitance)
CL 6.2 kΩ Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement

1.5 V
reference levels
Note: Diodes are IN3064 or equivalent Output timing measurement

1.5 V
reference levels
Figure 11. Test Setup
Key to Switching Waveforms
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
Input 1.5 V Measurement Level 1.5 V Output
0.0 V
Figure 12. Input Waveforms and Measurement Levels
22358B7 May 5, 2006 Am29LV160D 33

D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter Speed Options
JEDEC Std Description Test Setup -70 -90 -120 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 70 90 120 ns
CE# = VIL
tAVQV tACC Address to Output Delay Max 70 90 120 ns
OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 ns
tGLQV tOE Output Enable to Output Delay Max 30 35 50 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 30 30 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 30 30 ns
Read Min 0 ns
Output Enable
tOEH Toggle and
Hold Time (Note 1) Min 10 ns
Data# Polling
Output Hold Time From Addresses, CE# or

tAXQX tOH Min 0 ns
OE#, Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 11 for test specifications.
tRC
Addresses Addresses Stable

tACC
CE#
tDF
tOE
OE#
tOEH
WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid
RESET#
RY/BY#
0V
Figure 13. Read Operations Timings
34 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC Std Description Test Setup All Speed Options Unit
RESET# Pin Low (During Embedded Algorithms)

tREADY Max 20 µs
to Read or Write (See Note)
RESET# Pin Low (NOT During Embedded

tREADY Max 500 ns
Algorithms) to Read or Write (See Note)
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14. RESET# Timings
22358B7 May 5, 2006 Am29LV160D 35

D A T A S H E E T
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
JEDEC Std Description -70 -90 -120 Unit
tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns
tFLQZ BYTE# Switching Low to Output HIGH Z Max 25 30 30 ns
tFHQV BYTE# Switching High to Output Active Min 70 90 120 ns
CE#
OE#
BYTE#
tELFL
BYTE# DQ0–DQ14 Data Output Data Output
Switching (DQ0–DQ14) (DQ0–DQ7)
from word
to byte
mode DQ15/A-1 DQ15 Address
Output Input
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte DQ0–DQ14 Data Output Data Output
to word (DQ0–DQ7) (DQ0–DQ14)
mode
DQ15/A-1 Address DQ15
Input Output
tFHQV
Figure 15. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal

WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16. BYTE# Timings for Write Operations
36 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
AC CHARACTERISTICS
Erase/Program Operations
tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 45 45 50 ns
tDVWH tDS Data Setup Time Min 35 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

tGHWL tGHWL Min 0 ns
(OE# High to WE# Low)
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 35 50 ns
tWHWL tWPH Write Pulse Width High Min 30 ns
Byte Typ 5
tWHWH1 tWHWH1 Programming Operation (Note 2) µs
Word Typ 7
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# Min 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
22358B7 May 5, 2006 Am29LV160D 37

D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
Addresses 555h PA PA PA
tAH
CE#
tCH
OE#
tWP tWHWH1
WE#
tWPH
tCS
tDS
tDH
Data A0h PD Status DOUT
tBUSY tRB
RY/BY#
tVCS
VCC
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
38 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) Read Status Data
tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#
OE# tCH
tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete
10 for Chip Erase
tBUSY tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
22358B7 May 5, 2006 Am29LV160D 39

D A T A S H E E T
AC CHARACTERISTICS
tRC
Addresses VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data
High Z
DQ0–DQ6 Status Data Status Data True Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses VA VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
tBUSY
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
40 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
AC CHARACTERISTICS
Enter
Embedded Erase Enter Erase Erase
Erasing Suspend Suspend Program Resume
WE# Erase Erase Suspend Erase Erase Suspend Erase Erase
Read Suspend Read Complete
Program
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 21. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations

Parameter
JEDEC Std Description All Speed Options Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
RESET# Setup Time for Temporary Sector

tRSP Min 4 µs
Unprotect
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
tVIDR tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 22. Temporary Sector Unprotect/Timing Diagram
22358B7 May 5, 2006 Am29LV160D 41

D A T A S H E E T
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
Valid* Valid* Valid*
A1, A0
Sector Protect/Unprotect Verify
Data 60h 60h 40h Status
Sector Protect: 150 µs

1 µs Sector Unprotect: 15 ms
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Protect/Unprotect Timing Diagram
42 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 45 50 ns
tDVEH tDS Data Setup Time Min 35 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

tGHEL tGHEL Min 0 ns
(OE# High to WE# Low)
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 35 50 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
Byte Typ 5
tWHWH1 tWHWH1 Programming Operation (Note 2) µs
Word Typ 7
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
22358B7 May 5, 2006 Am29LV160D 43

D A T A S H E E T
AC CHARACTERISTICS
555 for program PA for program

2AA for erase SA for sector erase
555 for chip erase
Data# Polling
Addresses PA
tWC tAS
tAH
tWH
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tCPH
tBUSY
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
Figure 24. Alternate CE# Controlled Write Operation Timings
44 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.7 15 s Excludes 00h programming

Chip Erase Time 25 s prior to erasure (Note 4)
Byte Programming Time 5 150 µs
Word Programming Time 7 210 µs Excludes system level

Byte Mode 11 33 s overhead (Note 5)
Chip Programming Time
(Note 3) Word Mode 7.2 21.6 s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 9
for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
–1.0 V 12.5 V
(including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE

Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Test Conditions Min Unit
150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years
22358B7 May 5, 2006 Am29LV160D 45

D A T A S H E E T
PHYSICAL DIMENSIONS*
TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
46 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
PHYSICAL DIMENSIONS
TSR048—48-Pin Reverse TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
22358B7 May 5, 2006 Am29LV160D 47

D A T A S H E E T
PHYSICAL DIMENSIONS
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm
Dwg rev AF; 10/99
48 Am29LV160D May 5, 2006 22358B7

D A T A S H E E T
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
22358B7 May 5, 2006 Am29LV160D 49

D A T A S H E E T
REVISION SUMMARY
Revision A (January 1999) Ordering Information

The Am29LV160D is fully form, fit, and function com- Added dash to OPN.
patible with the Am29LV160B device, with the
following differences: Revision B+2 (November 7, 2000)
A 70 ns device at full voltage range is now available. Global
The 80 ns speed option has been deleted. Deleted Preliminary status from data sheet. Deleted
burn-in option. Added table of contents.
Byte and word programming times, and byte- and
word-mode chip programming times are now reduced.
Revision B+3 (November 10, 2000)
At extended temperatures (>+85°C), sleep and Command Definitions
standby currents increase.
Reset Command: Deleted reference to Figure 14, RE-
Revision A+1 (April 19, 1999) SET# Timings, which applies only to hardware reset.
Global Revision B+4 (April 5, 2004)

Reclassified the document from advance information Erase/Program Operations
to preliminary.
Changed standard parameter tBUSY from Min to Max.
The 70 ns speed option is now also available with the
industrial and extended temperature range ratings. Revision B+5 (June 4, 2004)
Ordering Information
Revision B (November 23, 1999)
Added Pb-Free OPNs.
AC Characteristics—Figure 17. Program
Operations Timing and Figure 18. Chip/Sector
Revision B+6 (October 7, 2004)
Erase Operations
Cover Sheet and Title Page
Deleted tGHWL and changed OE# waveform to start at
high. Added notation to superseding document.
Physical Dimensions Revision B7 (May 5, 2006)

Replaced figures with more detailed illustrations. Updated migration and obsolescence statement on
cover page and first page of data sheet.
Revision B+1 (February 22, 2000)
Updated trademarks.
Global
Added dash to speed options.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-
vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-
sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 1999–2006 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
50 Am29LV160D May 5, 2006 22358B7

Am29LV160D: Data Sheet

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Am29LV160D

The following document contains information on Spansion memory products.

For More Information

Publication Number 22358 Revision B Amendment 7 Issue Date May 5, 2006

2 Am29LV160D May 5, 2006 22358B7

22358B7 May 5, 2006 Am29LV160D 3

PRODUCT SELECTOR GUIDE

Speed Option Voltage Range: VCC = 2.7–3.6 V -70 -90 -120

Max access time, ns (tACC) 70 90 120

Max CE# access time, ns (tCE) 70 90 120

Max OE# access time, ns (tOE) 30 35 50

Note: See “AC Characteristics” for full specifications.

VCC Detector Timer

X-Decoder Cell Matrix

4 Am29LV160D May 5, 2006 22358B7

22358B7 May 5, 2006 Am29LV160D 5

A13 A12 A14 A15 A16 BYTE# DQ15/A-1 VSS

Special Handling Instructions Flash memory devices in FBGA packages may be

6 Am29LV160D May 5, 2006 22358B7

PIN CONFIGURATION LOGIC SYMBOL

22358B7 May 5, 2006 Am29LV160D 7

Am29LV160DT-70, Order Number Package Marking

8 Am29LV160D May 5, 2006 22358B7

DEVICE BUS OPERATIONS

Table 1. Am29LV160D Device Bus Operations

22358B7 May 5, 2006 Am29LV160D 9

10 Am29LV160D May 5, 2006 22358B7

22358B7 May 5, 2006 Am29LV160D 11

Table 2. Sector Address Tables (Am29LV160DT)

Sector Size Address Range (in hexadecimal)

12 Am29LV160D May 5, 2006 22358B7

Table 3. Sector Address Tables (Am29LV160DB)

Sector Size Address Range (in hexadecimal)

22358B7 May 5, 2006 Am29LV160D 13

Autoselect Mode Table 4. In addition, when verifying sector protection,

Table 4. Am29LV160D Autoselect Codes (High Voltage Method)

Manufacturer ID: AMD L L H X X VID X L X L L X 01h

Device ID: Word L L H 22h C4h

Device ID: Word L L H 22h 49h

14 Am29LV160D May 5, 2006 22358B7

Temporary Sector Unprotect

Figure 1. Temporary Sector Unprotect Operation

22358B7 May 5, 2006 Am29LV160D 15

Protect all sectors:

Algorithm complete Algorithm

Figure 2. In-System Sector Protect/Unprotect Algorithms

16 Am29LV160D May 5, 2006 22358B7

Table 5. CFI Query Identification String

10h 20h 0051h

13h 26h 0002h

15h 2Ah 0040h

17h 2Eh 0000h

19h 32h 0000h

22358B7 May 5, 2006 Am29LV160D 17

Table 6. System Interface String

VCC Min. (write/erase)

VCC Max. (write/erase)

1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs

21h 42h 000Ah Typical timeout per individual block erase 2N ms