Am29BL162C: Data Sheet

www.DataSheet4U.
com
Am29BL162C
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 22142 Revision F Amendment +8 Issue Date July 8, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.
Am29BL162C
16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
32 words sequential with wrap around 20-year data retention
(linear 32), bottom boot CFI (Common Flash Interface) compliant
One 8 Kword, two 4 Kword, one 112 Kword, and — Provides device-specific information to the
seven 128 Kword sectors system, allowing host software to easily
Single power supply operation reconfigure for different Flash devices
— Regulated voltage range: 3.0 to 3.6 volt read and Compatibility with JEDEC standards
write operations and for compatibility with high — Pinout and software compatible with single-
performance 3.3 volt microprocessors power supply Flash
Read access times — Superior inadvertent write protection
Burst access times as fast as 17 ns at industrial — Backward-compatible with AMD Am29LVxxx
temperature range (18 ns at extended and Am29Fxxx flash memories: powers up in
temperature range) asynchronous mode for system boot, but can
Initial/random access times as fast as 65 ns immediately be placed into burst mode
Alterable burst length via BAA# pin Data# Polling and toggle bits
Power dissipation (typical) — Provides a software method of detecting
— Burst Mode Read: 15 mA @ 25 MHz, program or erase operation completion
20 mA @ 33 MHz, 25 mA @ 40 MHz Ready/Busy# pin (RY/BY#)
— Program/Erase: 20 mA — Provides a hardware method of detecting
— Standby mode, CMOS: 3 µA program or erase cycle completion
5 V-tolerant data, address, and control signals Erase Suspend/Erase Resume
Sector Protection — Suspends an erase operation to read data from,
— Implemented using in-system or via or program data to, a sector that is not being
programming equipment erased, then resumes the erase operation
— Temporary Sector Unprotect feature allows code Hardware reset pin (RESET#)
changes in previously locked sectors — Hardware method to reset the device for reading
Unlock Bypass Program Command array data
— Reduces overall programming time when Package Option
issuing multiple program command sequences — 56-pin SSOP
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
Minimum 100,000 erase cycle guarantee
per sector
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may Publication# 22142 Rev: F Amendment/+8
be revised by subsequent versions or modifications due to changes in technical specifications. Issue Date: July 8, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29BL162C is a 16 Mbit, 3.0 Volt-only burst The sector erase architecture allows memory sectors
mode Flash memory devices organized as 1,048,576 to be erased and reprogrammed without affecting the
words. The device is offered in a 56-pin SSOP data contents of other sectors. The device is fully
package. These devices are designed to be pro- erased when shipped from the factory.
grammed in-system with the standard system 3.0-volt
Hardware data protection measures include a low VCC
VCC supply. A 12.0-volt VPP or 5.0 VCC is not required
detector that automatically inhibits write operations dur-
for program or erase operations. The device can also
ing power transitions. The hardware sector protection
be programmed in standard EPROM programmers.
feature disables both program and erase operations in
The device offers access times of 65, 70, 90, and 120 any combination of the sectors of memory. This can be
ns, allowing high speed microprocessors to operate achieved in-system or via programming equipment.
without wait states. To eliminate bus contention the
The Erase Suspend/Erase Resume feature enables
device has separate chip enable (CE#), write enable
the user to put erase on hold for any period of time to
(WE#) and output enable (OE#) controls.
read data from, or program data to, any sector that is
Burst Mode Features not selected for erasure. True background erase can
thus be achieved.
The Am29BL162C offers a Linear Burst mode—a
32 word sequential burst with wrap around—in a The hardware RESET# pin terminates any operation
bottom boot configuration only. This devices require in progress and resets the internal state machine to
additional control pins for burst operations: Load reading array data. The RESET# pin may be tied to the
Burst Address (LBA#), Burst Address Advance system reset circuitry. A system reset would thus also
(BAA#), and Clock (CLK). This implementation allows reset the device, enabling the system microprocessor
easy interface with minimal glue logic to a wide range to read the boot-up firmware from the Flash memory.
of microprocessors/microcontrollers for high perfor-
The device offers two power-saving features. When ad-
mance read operations.
dresses have been stable for a specified amount of
AMD Flash Memory Features time, the device enters the automatic sleep mode.
The system can also place the device into the standby
Each device requires only a single 3.0 volt power
mode. Power consumption is greatly reduced in both
supply for both read and write functions. Internally
these modes.
generated and regulated voltages are provided for the
program and erase operations. The I/O and control AMD’s Flash technology combines years of Flash
signals are 5V tolerant. memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device is entirely command set compatible with the
The device electrically erases all bits within a sector
JEDEC single-power-supply Flash standard. Com-
simultaneously via Fowler-Nordheim tunneling. The
mands are written to the command register using stan-
data is programmed using hot electron injection.
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
2 Am29BL162C July 8, 2005

D A T A S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . 21
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5 Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8 Table 8. Am29BL162C Command Definitions . . . . . . . . . . . . . . . . 23
Table 1. Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Write Operation Status . . . . . . . . . . . . . . . . . . . . 24
Requirements for Reading Array Data Array in Asynchronous DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
(Non-Burst) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 24
Requirements for Reading Array Data in Synchronous RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
(Burst) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Burst Suspend/Burst Resume Operations . . . . . . . . . . . . . . . 10 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IND# End of Burst Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . 25
Writing Commands/Command Sequences . . . . . . . . . . . . . . 10 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . 26
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . 10 DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 28
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . 10
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 28
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2. Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 11. ICC1 Current vs. Time (Showing Active and Automatic
Autoselect Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sleep Currents) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3. Am29BL162C Autoselect Codes (High Voltage Method) .12
Figure 12. Typical ICC1 vs. Frequency . . . . . . . . . . . . . . . . . . . . . 30
Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 12
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 1. In-System Sector Protect/Unprotect Algorithms . . . . . . . 13
Figure 13. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 2. Temporary Sector Unprotect Operation . . . . . . . . . . . . . 14
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 31
Hardware Data Protection . . . . . . . . . . . . . . . . . . 14 Figure 14. Input Waveforms and Measurement Levels . . . . . . . . 31
Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
Write Pulse “Glitch” Protection . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 15. Conventional Read Operations Timings . . . . . . . . . . . 34
Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 16. Burst Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Common Flash Memory Interface (CFI) . . . . . . . 15 Figure 17. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 4. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . .15 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5. System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 18. Program Operation Timings. . . . . . . . . . . . . . . . . . . . . 37
Table 6. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . .16 Figure 19. Chip/Sector Erase Operation Timings . . . . . . . . . . . . . 38
Table 7. Primary Vendor-Specific Extended Query . . . . . . . . . . . .16 Figure 20. Data# Polling Timings (During Embedded Algorithms) 39
Command Definitions . . . . . . . . . . . . . . . . . . . . . 17 Figure 21. Toggle Bit Timings (During Embedded Algorithms). . . 39
Reading Array Data in Non-burst Mode . . . . . . . . . . . . . . . . 17 Figure 22. DQ2 vs. DQ6 for Erase and
Reading Array Data in Burst Mode . . . . . . . . . . . . . . . . . . . . 17 Erase Suspend Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3. Burst Mode Read with 40 MHz CLK, 65 ns Figure 23. Temporary Sector Unprotect Timing Diagram . . . . . . . 40
tIACC, 18 ns tBACC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 24. Sector Protect/Unprotect Timing Diagram . . . . . . . . . . 41
Figure 4. Burst Mode Read with 25 MHz CLK, 70 ns Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . 42
tIACC, 24 ns tBACC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 25. Alternate CE# Controlled Write Operation Timings . . . 43
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Erase and Programming Performance . . . . . . . 44
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . 18 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 19 SSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Unlock Bypass Command Sequence . . . . . . . . . . . . . . . . . . . . . . .19 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 5. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 45
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . 20 SSO056—56-Pin Shrink Small Outline Package . . . . . . . . . . . . . . . . 45
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . 20 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 6. Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
July 8, 2005 Am29BL162C 3

D A T A S H E E T
PRODUCT SELECTOR GUIDE

Family Part Number Am29BL162C
Speed Regulated Voltage Range: VCC =3.0–3.6 V 65R 70R 90R 120R
Option Temperature Range: Industrial (I), Extended (E) I E I, E I, E I, E
Max access time, ns (tACC) 65 70 90 120
Max CE# access time, ns (tCE) 65 70 90 120
Max burst access time, ns (tBACC) 17 18 24 26 26
Note:
1. See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15
RY/BY#
IND#
VCC
VSS Sector
Switches
Input/Output IND#
RESET# Buffers Buffer
Erase Voltage
Generator
WE# State
Control
Command
PGM Voltage
Register
Generator Chip Enable
Output Enable
CE# STB
Logic Data Latch
OE#
A3, A4
Y-Gating A0–A2
STB Y-Decoder
VCC Detector Timer
Address Latch
A0–A19
X-Decoder Cell Matrix
A0–A4
A3, A4
LBA# Burst Burst A0–A2

BAA# State Address
CLK Counter Counter
4 Am29BL162C July 8, 2005

D A T A S H E E T
CONNECTION DIAGRAMS
WE# 1 56 LBA#
RESET# 2 55 VCC
RY/BY# 3 54 NC
A18 4 53 A19
A17 5 56-Pin SSOP 52 A8
A7 6 51 A9
A6 7 50 A10
A5 8 49 A11
A4 9 48 A12
A3 10 47 A13
A2 11 46 A14
A1 12 45 A15
A0 13 44 A16
CE# 14 43 NC
NC 15 42 NC
VSS 16 41 VSS
OE# 17 40 DQ15
DQ0 18 39 DQ7
DQ8 19 38 DQ14
DQ1 20 37 DQ6
DQ9 21 36 DQ13
DQ2 22 35 DQ5
DQ10 23 34 DQ12
DQ3 24 33 DQ4
DQ11 25 32 VCC
VSS 26 31 VCC
CLK 27 30 IND#
BAA# 28 29 NC
July 8, 2005 Am29BL162C 5

D A T A S H E E T
PIN CONFIGURATION
A0–A19 = 20 addresses BAA# = Burst Address Advance input.
Increments the address during the
DQ0–DQ15 = 16 data inputs/outputs
burst mode operation
CE# = Chip Enable Input. This signal shall be
BAA# Low enables the burst mode
asynchronous relative to CLK for the
Flash device to read from the next
burst mode.
word when gated with the rising edge
OE# = Output Enable Input. This signal shall of the clock. Data becomes available
be asynchronous relative to CLK for tBACC ns of burst access time after the
the burst mode. rising edge of the clock
WE# = Write enable. This signal shall be BAA # High prevents the rising edge of
asynchronous relative to CLK for the the clock from advancing the data to
burst mode. the next word output. The output data
remains unchanged.
VSS = Device ground
IND# = Highest burst counter address
NC = No connect. Pin not connected
reached. IND# is low at the end of a
internally
32-word burst sequence (when word
RY/BY# = Ready Busy output Da + 31 is output). The output wraps
around to Da on the next CLK cycle
CLK = Clock Input that can be tied to the
(with BAA# low).
system or microprocessor clock and
provides the fundamental timing and RESET# = Hardware reset input
internal operating frequency. CLK
Note: The address, data, and control signals (RY/BY#, LBA,
latches input addresses in conjunction BAA, IND, RESET, OE#, CE#, and WE#) are 5 V tolerant.
with LBA# input and increments the
burst address with the BAA# input.
LOGIC SYMBOL
LBA# = Load Burst Address input. Indicates
that the valid address is present on the 20
address inputs. A0–A19 16
LBA# Low at the rising edge of the DQ0–DQ15
clock latches the address on the CLK
address inputs into the burst mode
Flash device. Data becomes available CE#
tPACC ns of initial access time after the OE#
rising edge of the same clock that
latches the address. WE# IND#
LBA# High indicates that the address RESET#

is not valid LBA# RY/BY#
BAA#
6 Am29BL162C July 8, 2005

D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29BL162C B 65R Z I
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
E= Extended (–40°C to +125°C)
F= Industrial –40°C to +°85C) for Pb-free Package
K= Extended –55°C to +125°C) for Pb-free Package
PACKAGE TYPE
Z= 56-Pin Shrink Small Outline Package (SSOP 056)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE

B= Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29BL162C
16 Megabit (1 M x 16-Bit)
CMOS 3.0 Volt-only High Performance Burst Mode Flash Memory
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
Am29BL162CB-65R ZI, ZE, ZF, ZK ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
Am29BL162CB-70R ZI, ZE, ZF, ZK
to check on newly released combinations.
For information on full voltage range options (2.7 – 3.6 V),

please contact AMD.
July 8, 2005 Am29BL162C 7

D A T A S H E E T
DEVICE BUS OPERATIONS

This section describes the requirements and use of the the register serve as inputs to the internal state ma-
device bus operations, which are initiated through the chine. The state machine outputs dictate the function of
internal command register. The command register it- the device. Table 1 lists the device bus operations, the
self does not occupy any addressable memory loca- inputs and control levels they require, and the resulting
tion. The register is composed of latches that store the output. The following subsections describe each of
commands, along with the address and data informa- these operations in further detail.
tion needed to execute the command. The contents of
Table 1. Device Bus Operations

Addresses Data
Operation CE# OE# WE# RESET# CLK LBA# BAA# (Note 1) (DQ0–DQ15)
Read L L H H X X X AIN DOUT
Write L H L H X X X AIN DIN
VCC ± VCC ±
Standby X X X X X X HIGH Z
0.3 V 0.3 V
Output Disable L H H H X X X HIGH Z HIGH Z
Reset X X X L X X X X HIGH Z
Sector Address,
Sector Protect (Note 2) L H L VID X X X A6 = L, A1 = H, DIN
A0 = L
Sector Address,
Sector Unprotect (Note 2) L H L VID X X X A6 = H, A1 = H, DIN
A0 = L
Temporary Sector Unprotect X X X VID X X X AIN HIGH Z
Burst Read Operations
Load Starting Burst Address L X H H L H AIN X
Advance Burst to Next Address (no

L H H H H L X HIGH Z
data presented on the data bus)
Advance Burst to Next address

Data Out
(appropriate data presented on the L L H H H L X
DQ0-DQ15
data bus)
Terminate Current Burst Read Cycle H X H H X X X HIGH Z
Terminate Current Burst Read Cycle;

L X H H L H AIN X
Start New Burst Read Cycle
Burst Suspend (all data is retained

L H H H X H H X HIGH Z
internally in the device)
Burst Resume (same data as Burst Data Out

L L H H H H X
Suspend) DQ0–DQ15
Burst Resume (incremented data from Data Out

L L H H H L X
Burst Suspend) DQ0–DQ15
Legend:
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Notes:
1. Addresses are A19:A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
8 Am29BL162C July 8, 2005

D A T A S H E E T
Requirements for Reading Array Data LBA#, and BAA# inputs are ignored. The device oper-
Array in Asynchronous (Non-Burst) Mode ates as a conventional flash device, as described in the
previous section.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power To enable burst mode operation, the system must issue
control and selects the device. OE# is the output control the Burst Mode Enable command sequence (see
and gates array data to the output pins. WE# should re- Table 8). After the device has entered the burst mode,
main at VIH. the system must assert Load Burst Address (LBA#) low
for one clock period, which loads the starting address
Address access time (tACC) is equal to the delay from into the device. The first burst data is available after the
stable addresses to valid output data. The chip enable initial access time (tIACC) from the rising edge of the
access time (t C E ) is the delay from the stable CLK that loads the burst address. After the initial
addresses and stable CE# to valid data at the output access, subsequent burst data is available tBACC after
pins. The output enable access time is the delay from each rising edge of CLK.
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least The device increments the address at each rising edge
tACC–tOE time). of the clock cycles while BAA# is asserted low. The 5-
bit burst address counter is set to 00000b at the
The internal state machine is set for reading array starting address. When the burst address counter is
data in the upon device power-up, or after a hardware reaches 11111b, the device outputs the last word in the
reset. This ensures that no spurious alteration of the burst sequence, and outputs a low on IND#. If the
memory content occurs during the power transition. system continues to assert BAA#, on the next CLK the
No command is necessary in this mode to obtain array device outputs the data for the starting address—the
data. Standard microprocessor read cycles that as- burst address counter is “wrapped around” to 00000b.
sert valid addresses on the device address inputs pro- For example, if the initial address is xxxx0h, the data
duce valid data on the device data outputs. The device order is 0-1-2-3…28-29-30-31-0-1…; if the initial
remains enabled for read access until the command address is xxxx2h, the data order is 2-3-4-5…28-29-
register contents are altered. 30-31-0-1-2-3…; if the initial address is xxxx8h, the
See “Reading Array Data in Non-burst Mode” for more data order is 8-9-10-11…30-31-0-1-2-3-4-5-6-7-8-9…;
information. Refer to the AC Read Operations table for and so on. Data is repeated if more than 32 clocks are
timing specifications and to Figure 15 for the timing di- supplied, and BAA# remains asserted low.
agram. ICC1 in the DC Characteristics table represents
A burst mode read operation is terminated using one of
the active current specification for reading array data. three methods:
Requirements for Reading Array Data in — In the first method, CE# is asserted high. The
Synchronous (Burst) Mode device in this case remains in burst mode;
asserting LBA# low terminates the previous
The device offers fast 32-word sequential burst reads burst read cycle and starts a new burst read
and is used to support microprocessors that implement cycle with the address that is currently valid.
an instruction prefetch queue, as well as large data
transfers during system configuration. — In the second method, the Burst Disable
command sequence is written to the device. The
Three additional pins—Load Burst Address (LBA#), device halts the burst operation and returns to
Burst Address Advance (BAA#), and Clock (CLK)— the asynchronous mode.
allow interfacing to microprocessors and microcontrol- — In the third method, RESET# is asserted low. All
lers with minimal glue logic. Burst mode read is a syn- operations are immediately terminated, and the
chronous operation tied to the rising edge of CLK. CE#, device reverts to the asynchronous mode.
OE#, and WE# are asynchronous (relative to CLK).
Note that writing the reset command does not termi-
When the device is in asynchronous mode (after nate the burst mode.
power-up or RESET# pulse), any signals on the CLK,
July 8, 2005 Am29BL162C 9

D A T A S H E E T
Burst Suspend/Burst Resume Operations Characteristics” section contains timing specification ta-
bles and timing diagrams for write operations.
The device offers Burst Suspend and Burst Resume
operations. When both OE# and BAA# are taken high,
Program and Erase Operation Status
the device removes (“suspends”) the data from the
outputs (because OE# is high), but “holds” the data During an erase or program operation, the system may
internally. The device resumes burst operation when check the status of the operation by reading the status
either OE# and/or BAA# is asserted low. Asserting the bits on DQ7–DQ0. Standard read cycle timings and ICC
OE# only causes the device to present the same data read specifications apply. Refer to “Write Operation Sta-
that was held during the Burst Suspend operation. As tus” for more information, and to “AC Characteristics” for
long as BAA# is high, the device continues to output timing diagrams.
that word of data. Asserting both OE# and BAA# low
resumes the burst operation, and on the next rising Standby Mode
edge of CLK, increments the counter and outputs the When the system is not reading or writing to the device,
next word of data. it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
IND# End of Burst Indicator outputs are placed in the high impedance state, inde-
The IND# output signal goes low when the device is pendent of the OE# input.
outputting the last word of a 32-word burst sequence The device enters the CMOS standby mode when the
(word Da+31). When the starting address was loaded CE# and RESET# pins are both held at VCC ± 0.3 V.
with LBA#, the 5-bit burst address counter was set to (Note: This is a more restricted voltage range than VIH.)
00000b. The counter increments to 11111b on the If CE# and RESET# are held at VIH, but not within VCC
32nd word in the burst sequence. If the system con- ± 0.3 V, the device is in the standby mode, but the
tinues to assert BAA# low, on the next CLK the device standby current is greater. The device requires standard
outputs the starting address data (Da). The burst access time (tCE) for read access when the device is in
address counter is again set to 00000b, and is either of these standby modes, before it is ready to read
“wrapped around.” data.
Writing Commands/Command Sequences If the device is deselected during erasure or program-
ming, the device draws active current until the operation
To write a command or command sequence (which in-
is completed.
cludes programming data to the device and erasing sec-
tors of memory), the system must drive WE# and CE# to In the DC Characteristics table, ICC3 and ICC4 represents
VIL, and OE# to VIH. the standby current specification.
The device features an Unlock Bypass mode to facili-
Automatic Sleep Mode
tate faster programming. Once the device enters the Un-
lock Bypass mode, only two write cycles are required to The automatic sleep mode minimizes Flash device
program a word, instead of four. The “Program Com- energy consumption. The device automatically enables
mand Sequence” section has details on programming this mode when addresses remain stable for tACC + 30
data to the device using both standard and Unlock By- ns. The automatic sleep mode is independent of the
pass command sequences. CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
An erase operation can erase one sector, multiple sec- changed. While in sleep mode, output data is latched
tors, or the entire device. Table 2 indicates the address and always available to the system. ICC4 in the DC
space that each sector occupies. A “sector address” Characteristics table represents the automatic sleep
consists of the address bits required to uniquely select a mode current specification.
sector. The “Command Definitions” section has details
on erasing a sector or the entire chip, or suspending/re- RESET#: Hardware Reset Pin
suming the erase operation.
The RESET# pin provides a hardware method of reset-
After the system writes the autoselect command se- ting the device to reading array data. When the system
quence, the device enters the autoselect mode. The sys- drives the RESET# pin to VIL for at least a period of tRP,
tem can then read autoselect codes from the internal the device immediately terminates any operation in
register (which is separate from the memory array) on progress, tristates all data output pins, and ignores all
DQ7–DQ0. Standard read cycle timings apply in this read/write attempts for the duration of the RESET#
mode. Refer to the “Autoselect Mode” and “Reset Com- pulse. The device also resets the internal state machine
mand” sections for more information. to reading array data. The operation that was interrupted
ICC2 in the DC Characteristics table represents the ac- should be reinitiated once the device is ready to accept
tive current specification for the write mode. The “AC another command sequence, to ensure data integrity.
10 Am29BL162C July 8, 2005

D A T A S H E E T
Current is reduced for the duration of the RESET# pulse. eration is complete. If RESET# is asserted when a pro-
When RESET# is held at VSS±0.3 V, the device draws gram or erase operation is not executing (RY/BY# pin is
CMOS standby current (ICC4). If RESET# is held at VIL “1”), the reset operation is completed within a time of
but not within VSS±0.3 V, the standby current is greater. tREADY (not during Embedded Algorithms). The system
can read data tRH after the RESET# pin returns to VIH.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash Refer to the AC Characteristics tables for RESET# pa-
memory, enabling the system to read the boot-up firm- rameters and to Figure 17 for the timing diagram.
ware from the Flash memory.
Output Disable Mode
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the inter- When the OE# input is at VIH, output from the device is
nal reset operation is complete, which requires a time of disabled. The output pins are placed in the high imped-
tREADY (during Embedded Algorithms). The system can ance state.
thus monitor RY/BY# to determine whether the reset op-
Table 2. Sector Address Table

Sector Sector Size A19 A18 A17 A16 A15 A14 A13 A12 Address Range
SA0 8 Kwords 0 0 0 0 0 0 0 X 00000h–01FFFh
SA1 4 Kwords 0 0 0 0 0 0 1 0 02000h–02FFFh
SA2 4 Kwords 0 0 0 0 0 0 1 1 03000h–03FFFh
SA3 112 Kwords 0 0 0 00100–11111 04000h–1FFFFh
SA4 128 Kwords 0 0 1 X X X X X 20000h–3FFFFh
SA8 128 Kwords 1 0 1 X X X X X A0000h–BFFFFh
SA9 128 Kwords 1 1 0 X X X X X C0000h–DFFFFh
SA10 128 Kwords 1 1 1 X X X X X E0000h–FFFFFh
July 8, 2005 Am29BL162C 11

D A T A S H E E T
Autoselect Mode Table 1. In addition, when verifying sector protection,

the sector address must appear on the appropriate
The autoselect mode provides manufacturer and de-
highest order address bits (see Table 2). Table 1 shows
vice identification, and sector protection verification,
the remaining address bits that are don’t care. When all
through identifier codes output on DQ7–DQ0. This
necessary bits have been set as required, the program-
mode is primarily intended for programming equipment
ming equipment may then read the corresponding
to automatically match a device to be programmed with
identifier code on DQ7-DQ0.
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system To access the autoselect codes in-system, the host
through the command register. system can issue the autoselect command via the
command register, as shown in Table 8. This method
When using programming equipment, the autoselect
does not require VID. See “Command Definitions” for
mode requires VID (11.5 V to 12.5 V) on address pin
details on using the autoselect mode.
A9. Address pins A6, A1, and A0 must be as shown in
Table 3. Am29BL162C Autoselect Codes (High Voltage Method)

A19 A11 A8 A5
to to to to DQ15 to
Description CE# OE# WE# A12 A10 A9 A7 A6 A2 A1 A0 DQ0
Manufacturer ID: AMD L L H X X VID X L X L L 0001h
Device ID:
Am29BL162CB L L H X X VID X L X L H 2203h
(Bottom Boot Block)
Sector Protection X VID X L X H L 0001h (protected)

L L H SA
Verification X VID X L X H L 0000h (unprotected)
0000h
(non-burst mode)
Burst Mode Status L L H X X VID X L X H H
0001h
(burst mode)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 8.
Sector Protection/Unprotection The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
The hardware sector protection feature disables both
programming equipment. Figure 2 shows the algo-
program and erase operations in any sector. The hard-
rithms and Figure 24 shows the timing diagram. This
ware sector unprotection feature re-enables both program
method uses standard microprocessor bus cycle
and erase operations in previously protected sectors.
timing. For sector unprotect, all unprotected sectors
The device is shipped with all sectors unprotected. must first be protected prior to the first sector unprotect
AMD offers the option of programming and protecting write cycle.
sectors at its factory prior to shipping the device
The alternate method intended only for programming
through AMD’s ExpressFlash™ Service. Contact an
equipment requires VID on address pin A9 and OE#.
AMD representative for details.
This method is compatible with programmer routines
It is possible to determine whether a sector is protected written for earlier 3.0 volt-only AMD flash devices. De-
or unprotected. See “Autoselect Mode” for details. tails on this method are provided in a supplement, pub-
lication number 22240. Contact an AMD representative
Sector protection/unprotection can be implemented via
to request a copy.
two methods.
12 Am29BL162C July 8, 2005

D A T A S H E E T
START START
Protect all sectors:

PLSCNT = 1 The indicated portion PLSCNT = 1
of the sector protect
RESET# = VID algorithm must be RESET# = VID
performed for all
unprotected sectors
Wait 1 μs Wait 1 μs
prior to issuing the
first sector
unprotect address
No First Write No
Temporary Sector First Write Temporary Sector
Unprotect Mode Cycle = 60h? Cycle = 60h? Unprotect Mode
Yes Yes
Set up sector
No All sectors
address
protected?
Sector Protect:
Yes
Write 60h to sector
address with Set up first sector
A6 = 0, A1 = 1, address
A0 = 0
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
Verify Sector A6 = 1, A1 = 1,
Protect: Write 40h A0 = 0
to sector address Reset
Increment with A6 = 0, PLSCNT = 1 Wait 15 ms
PLSCNT A1 = 1, A0 = 0
Verify Sector
Read from
Unprotect: Write
sector address
40h to sector
with A6 = 0,
address with
A1 = 1, A0 = 0 Increment A6 = 1, A1 = 1,
No PLSCNT A0 = 0
No
PLSCNT Data = 01h? Read from
= 25? sector address
with A6 = 1,
Yes A1 = 1, A0 = 0
Yes No
Set up
next sector
Yes No
PLSCNT address
Protect another Data = 00h?
Device failed = 1000?
sector?
No Yes Yes
Remove VID
from RESET# Last sector No
Device failed verified?
Write reset
Yes
command
Remove VID
Sector Protect Sector Protect
Sector Unprotect from RESET#
Algorithm complete Algorithm

Write reset
command
Sector Unprotect
complete
Figure 1. In-System Sector Protect/Unprotect Algorithms
July 8, 2005 Am29BL162C 13

D A T A S H E E T
Temporary Sector Unprotect HARDWARE DATA PROTECTION

This feature allows temporary unprotection of previ- The command sequence requirement of unlock cycles
ously protected sectors to change data in-system. The for programming or erasing provides data protection
Sector Unprotect mode is activated by setting the RE- against inadvertent writes (refer to Table 8 for com-
SET# pin to VID. During this mode, formerly protected mand definitions). In addition, the following hardware
sectors can be programmed or erased by selecting the data protection measures prevent accidental erasure
sector addresses. Once VID is removed from the RE- or programming, which might otherwise be caused by
SET# pin, all the previously protected sectors are spurious system level signals during VCC power-up and
protected again. Figure 2 shows the algorithm, and power-down transitions, or from system noise.
Figure 23 shows the timing diagrams, for this feature.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
START
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
RESET# = VID
(Note 1)
is greater than V LKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Perform Erase or
Program Operations
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
RESET# = VIH WE# do not initiate a write cycle.
Logical Inhibit
Temporary Sector Write cycles are inhibited by holding any one of OE# =
Unprotect Completed VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
(Note 2) CE# and WE# must be a logical zero while OE# is a
logical one.
Notes:
Power-Up Write Inhibit
1. All protected sectors unprotected.
2. All previously protected sectors are protected once If WE# = CE# = VIL and OE# = VIH during power up, the
again. device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
Figure 2. Temporary Sector Unprotect Operation reset to reading array data on power-up.
14 Am29BL162C July 8, 2005

D A T A S H E E T
COMMON FLASH MEMORY INTERFACE addresses given in Tables 4–7. To terminate reading
(CFI) CFI data, the system must write the reset command.
The Common Flash Interface (CFI) specification out- The system can also write the CFI query command
lines device and host system software interrogation when the device is in the autoselect mode. The device
handshake, which allows specific vendor-specified enters the CFI query mode, and the system can read
software algorithms to be used for entire families of CFI data at the addresses given in Tables 4–7. The
devices. Software support can then be device-indepen- system must write the reset command to return the
dent, JEDEC ID-independent, and forward- and back- device to the autoselect mode.
ward-compatible for the specified flash device families. For further information, please refer to the CFI Specifi-
Flash vendors can standardize their existing interfaces cation and CFI Publication 100, available via the World
for long-term compatibility. Wide Web at http://www.amd.com/products/nvd/over-
This device enters the CFI Query mode when the view/cfi.html. Alternatively, contact an AMD represen-
system writes the CFI Query command, 98h, to tative for copies of these documents.
address 55h, any time the device is ready to read array To terminate reading CFI data, the system must write
data. The system can read CFI information at the the reset command.
Table 4. CFI Query Identification String

Addresses Data Description
10h 0051h
11h 0052h Query Unique ASCII string “QRY”
12h 0059h
13h 0002h
Primary OEM Command Set
14h 0000h
15h 0040h
Address for Primary Extended Table
16h 0000h
17h 0000h
Alternate OEM Command Set (00h = none exists)
18h 0000h
19h 0000h
Address for Alternate OEM Extended Table (00h = none exists)
1Ah 0000h
Table 5. System Interface String

VCC Min. (write/erase)

1Bh 0027h
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)

1Ch 0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 0004h Typical timeout per single word write 2N µs
20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 000Ah Typical timeout per individual block erase 2N ms
22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 0005h Max. timeout for word write 2N times typical
24h 0000h Max. timeout for buffer write 2N times typical
25h 0004h Max. timeout per individual block erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
July 8, 2005 Am29BL162C 15

D A T A S H E E T
Table 6. Device Geometry Definition

27h 0015h Device Size = 2N byte
28h 0001h
Flash Device Interface description (refer to CFI publication 100)
29h 0000h
2Ah 0000h Max. number of bytes in multi-byte write = 2N

2Bh 0000h (00h = not supported)
2Ch 0004h Number of Erase Block Regions within device
2Dh 0000h
2Eh 0000h Erase Block Region 1 Information
2Fh 0040h (refer to the CFI specification or CFI publication 100)
30h 0000h
31h 0001h
32h 0000h
Erase Block Region 2 Information
33h 0020h
34h 0000h
35h 0000h
36h 0000h
37h 0080h
38h 0003h
39h 0006h
3Ah 0000h
3Bh 0000h
3Ch 0004h
Table 7. Primary Vendor-Specific Extended Query

40h 0050h
41h 0052h Query-unique ASCII string “PRI”
42h 0049h
43h 0031h Major version number, ASCII
44h 0030h Minor version number, ASCII
Address Sensitive Unlock

45h 0000h
0 = Required, 1 = Not Required
Erase Suspend
46h 0002h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
47h 0001h
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect

48h 0001h
00 = Not Supported, 01 = Supported
49h 0004h Sector Protect/Unprotect scheme
Simultaneous Operation
4Ah 0000h
00 = Not Supported, 01 = Supported
Burst Mode Type

4Bh 0003h 00 = Not Supported, 01 = 4 word Linear Burst, 02 = 8 Word linear Burst,
03 = 32 Word Linear Burst, 04 = 4 Word Interleave Burst
Page Mode Type

4Ch 0000h
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
16 Am29BL162C July 8, 2005

D A T A S H E E T
COMMAND DEFINITIONS Reading Array Data in Burst Mode

Writing specific address and data commands or se- The device powers up in the non-burst mode. To read
quences into the command register initiates device op- array data in burst mode, the system must write the
erations. Table 8 defines the valid register command four-cycle Burst Mode Enable command sequence
sequences. Writing incorrect address and data val- (see Table 8). The device then enters burst mode. In
ues or writing them in the improper sequence resets addition to asserting CE#, OE#, and WE# control sig-
the device to reading array data. nals, burst mode operation requires that the system
provide appropriate LBA#, BAA#, and CLK signals. For
All addresses are latched on the falling edge of
successful burst mode reads, the following events must
WE# or CE#, whichever happens later. All data is
occur (refer to Figures 3 and 4 for this discussion):
latched on the rising edge of WE# or CE#, whichever
happens first. Refer to the appropriate timing diagrams 1. The system asserts LBA# low, indicating to the de-
in the AC Characteristics section. vice that a valid initial burst address is available on
the address bus. LBA# must be kept low until at
Reading Array Data in Non-burst Mode least the next rising edge of the CLK signal, upon
The device is automatically set to reading array data which the device loads the initial burst address.
after device power-up. No commands are required to 2. The system returns LBA# to a logic high. The device
retrieve data. The device is also ready to read array requires that the next rising edge of CLK occur with
data after completing an Embedded Program or Em- LBA# high for proper burst mode operation. Typi-
bedded Erase algorithm. cally, the initial number of CLK cycles depends on
the clock frequency and the rated speed of the de-
After the device accepts an Erase Suspend com-
vice.
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard 3. After the initial data has been read, the system as-
read timings, except that if it reads at an address serts BAA# low to indicate it is ready to read the re-
within erase-suspended sectors, the device outputs maining burst read cycles. Each successive rising
status data. After completing a programming opera- edge of the CLK signal then causes the flash device
tion in the Erase Suspend mode, the system may to increment the burst address and output sequen-
once again read array data with the same exception. tial burst data.
See “Erase Suspend/Erase Resume Commands” for 4. When the device outputs the last word of data in the
more information on this mode. 32-word burst mode read sequence, the device out-
The system must issue the reset command to re-en- puts a logic low on the IND# pin. This indicates to
able the device for reading array data if DQ5 goes high, the system that the burst mode read sequence is
or while in the autoselect mode. See the “Reset Com- complete.
mand” section, next. 5. To exit the burst mode, the system must write the
four-cycle Burst Mode Disable command sequence.
See also “Requirements for Reading Array Data Array in
The device also exits the burst mode if powered
Asynchronous (Non-Burst) Mode” in the “Key to Switch-
down or if RESET# is asserted. The device does not
ing Waveforms” section for more information. The Read
exit the burst mode if the reset command is written.
Operations table provides the read parameters, and
Figure 15 shows the timing diagram.
July 8, 2005 Am29BL162C 17

D A T A S H E E T
Step 1 Step 2 Step 3
25 ns 25 ns 25 ns 25 ns 25 ns
CLK
LBA#
BAA#
Da Da +1 Da +2
Data
65 ns 18 ns 18 ns
OE#
Figure 3. Burst Mode Read with 40 MHz CLK, 65 ns tIACC, 18 ns tBACC Parameters
Step 1 Step 2 Step 3
40 ns 40 ns 40 ns 40 ns 40 ns
CLK
LBA#
BAA#
Da Da +1 Da +2 Da +3
Data
70 ns 24 ns 24 ns 24 ns
OE#
Figure 4. Burst Mode Read with 25 MHz CLK, 70 ns tIACC, 24 ns tBACC Parameters
Reset Command The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Writing the reset command to the device resets the de-
Once in the autoselect mode, the reset command must
vice to reading array data. Address bits are don’t care
be written to return to reading array data (also applies
for this command.
to autoselect during Erase Suspend).
The reset command may be written between the se-
If DQ5 goes high during a program or erase operation,
quence cycles in an erase command sequence before
writing the reset command returns the device to read-
erasing begins. This resets the device to reading array
ing array data (also applies during Erase Suspend).
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete. See “AC Characteristics” for parameters, and to
Figure 17 for the timing diagram.
The reset command may be written between the se-
quence cycles in a program command sequence be-
Autoselect Command Sequence
fore programming begins. This resets the device to
reading array data (also applies to programming in The autoselect command sequence allows the host
Erase Suspend mode). Once programming begins, system to access the manufacturer and devices codes,
however, the device ignores reset commands until the and determine whether or not a sector is protected.
operation is complete. Table 8 shows the address and data requirements.
18 Am29BL162C July 8, 2005

D A T A S H E E T
This method is an alternative to that shown in Table 1, hardware reset immediately terminates the program-
which is intended for PROM programmers and requires ming operation.
VID on address bit A9.
Programming is allowed in any sequence and across
The autoselect command sequence is initiated by writ- sector boundaries. A bit cannot be programmed
ing two unlock cycles, followed by the autoselect com- from a “0” back to a “1.” Attempting to do so may halt
mand. The device then enters the autoselect mode, the operation and set DQ5 to “1,” or cause the Data#
and the system may read at any address any number Polling algorithm to indicate the operation was suc-
of times, without initiating another command sequence. cessful. However, a succeeding read shows that the
data is still “0.” Only erase operations convert a “0” to a
A read cycle at address 00h retrieves the manufacturer
“1.”
code. A read cycle at address 01h returns the device
code. A read cycle containing a sector address (SA) Unlock Bypass Command Sequence
and the address 02h in word mode returns 0001h if that The unlock bypass feature allows the system to pro-
sector is protected, or 0000h if it is unprotected. Refer gram words to the device faster than using the standard
to Table 2 for valid sector addresses. A read cycle at program command sequence. The unlock bypass com-
address 03h returns 0000h if the device is in asynchro- mand sequence is initiated by first writing two unlock
nous mode, or 0001h if in synchronous (burst) mode. cycles. This is followed by a third write cycle containing
The system must write the reset command to exit the the unlock bypass command, 20h. The device then en-
autoselect mode and return to reading array data. ters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required
Program Command Sequence to program in this mode. The first cycle in this se-
quence contains the unlock bypass program com-
Programming is a four-bus-cycle operation. The pro-
mand, A0h; the second cycle contains the program
gram command sequence is initiated by writing two
address and data. Additional data is programmed in
unlock write cycles, followed by the program set-up
the same manner. This mode dispenses with the initial
command. The program address and data are written
two unlock cycles required in the standard program
next, which in turn initiate the Embedded Program al-
command sequence, resulting in faster total program-
gorithm. The system is not required to provide further
ming time. Table 8 shows the requirements for the com-
controls or timings. The device automatically gener-
mand sequence.
ates the program pulses and verifies the programmed
cell margin. Table 8 shows the address and data re- During the unlock bypass mode, only the Unlock By-
quirements for the program command sequence. pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
When the Embedded Program algorithm is complete,
must issue the two-cycle unlock bypass reset com-
the device then returns to reading array data and ad-
mand sequence. The first cycle must contain the data
dresses are no longer latched. The system can deter-
90h; the second cycle the data 00h. Addresses are
mine the status of the program operation by using DQ7,
don’t care for both cycles. The device then returns to
DQ6, or RY/BY#. See “Write Operation Status” for in-
reading array data.
formation on these status bits.
Figure 5 illustrates the algorithm for the program oper-
Any commands written to the device during the Em-
ation. See the Erase/Program Operations table in “AC
bedded Program Algorithm are ignored. Note that a
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
July 8, 2005 Am29BL162C 19

D A T A S H E E T
The system can determine the status of the erase op-

eration by using DQ7, DQ6, DQ2, or RY/BY#. See
START “Write Operation Status” for information on these status
bits. When the Embedded Erase algorithm is complete,
the device returns to reading array data and addresses
are no longer latched.
Write Program
Figure 6 illustrates the algorithm for the erase opera-
Command Sequence
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 19 for
timing diagrams.
Data Poll
from System Sector Erase Command Sequence
Embedded
Program Sector erase is a six bus cycle operation. The sector
algorithm erase command sequence is initiated by writing two un-
in progress
lock cycles, followed by a set-up command. Two addi-
Verify Data? tional unlock write cycles are then followed by the
No
address of the sector to be erased, and the sector
erase command. Table 8 shows the address and data
Yes requirements for the sector erase command sequence.
The device does not require the system to preprogram
No the memory prior to erase. The Embedded Erase algo-
Increment Address Last Address?
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
Yes system is not required to provide any controls or tim-
ings during these operations.
Programming
Completed After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
Note: See Table 8 for program command sequence. mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
Figure 5. Program Operation tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
Chip Erase Command Sequence accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
Chip erase is a six bus cycle operation. The chip erase ensure all commands are accepted. The interrupts can
command sequence is initiated by writing two unlock be re-enabled after the last Sector Erase command is
cycles, followed by a set-up command. Two additional written. If the time between additional sector erase
unlock write cycles are then followed by the chip erase commands can be assumed to be less than 50 µs, the
command, which in turn invokes the Embedded Erase system need not monitor DQ3. Any command other
algorithm. The device does not require the system to than Sector Erase or Erase Suspend during the
preprogram prior to erase. The Embedded Erase algo- time-out period resets the device to reading array
rithm automatically preprograms and verifies the entire data. The system must rewrite the command sequence
memory for an all zero data pattern prior to electrical and any additional sector addresses and commands.
erase. The system is not required to provide any con-
trols or timings during these operations. Table 8 shows The system can monitor DQ3 to determine if the sector
the address and data requirements for the chip erase erase timer has timed out. (See the “DQ3: Sector Erase
command sequence. Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware Once the sector erase operation has begun, only the
reset during the chip erase operation immediately ter- Erase Suspend command is valid. All other commands
minates the operation. The Chip Erase command se- are ignored. Note that a hardware reset during the
quence should be reinitiated once the device has sector erase operation immediately terminates the op-
returned to reading array data, to ensure data integrity. eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
20 Am29BL162C July 8, 2005

D A T A S H E E T
When the Embedded Erase algorithm is complete, the device from entering Burst Mode. To enter Burst Mode
device returns to reading array data and addresses are either the Erase operation must be allowed to complete
no longer latched. The system can determine the sta- normally, or it can be prematurely terminated by issuing
tus of the erase operation by using DQ7, DQ6, DQ2, or a Hardware Reset.
RY/BY#. (Refer to “Write Operation Status” for informa-
Burst Mode
tion on these status bits.)
While in Burst Mode the Erase Suspend command is
Figure 6 illustrates the algorithm for the erase opera- ignored and the device continues to operate normally in
tion. Refer to the Erase/Program Operations tables in Burst Mode. If Erase Suspend operation is required,
the “AC Characteristics” section for parameters, and to then Burst Mode must be terminated and Asynchro-
Figure 19 for timing diagrams. nous Mode initiated.
General
This command is valid only during the sector erase op-
START
eration, including the 50 µs time-out period during the
sector erase command sequence. The Erase Suspend
command is ignored if written during the chip erase op-
eration or Embedded Program algorithm. Writing the
Write Erase
Erase Suspend command during the Sector Erase
Command Sequence
time-out immediately terminates the time-out period
and suspends the erase operation. Addresses are
“don’t-cares” when writing the Erase Suspend com-
Data Poll mand.
from System
Embedded When the Erase Suspend command is written during a
Erase sector erase operation, the device requires a maximum
algorithm of 20 µs to suspend the erase operation. However, when
in progress the Erase Suspend command is written during the sec-
No tor erase time-out, the device immediately terminates
Data = FFh?
the time-out period and suspends the erase operation.
After the erase operation has been suspended, the
Yes system can read array data from or program data to
any sector not selected for erasure. (The device “erase
Erasure Completed suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Note that burst read is not available when the device is
erase-suspended. Only asynchronous reads are al-
Notes:
lowed. Reading at any address within erase-sus-
1. See Table 8 for erase command sequence.
pended sectors produces status data on DQ7–DQ0.
2. See “DQ3: Sector Erase Timer” for more information. The system can use DQ7, or DQ6 and DQ2 together,
to determine if a sector is actively erasing or is erase-
Figure 6. Erase Operation
suspended. See “Write Operation Status” for informa-
tion on these status bits.
Erase Suspend/Erase Resume Commands After an erase-suspended program operation is com-
The Erase Suspend command allows the system to in- plete, the system can once again read array data within
terrupt a sector erase operation and then read data non-suspended sectors. The system can determine
from, or program data to, any sector not selected for the status of the program operation using the DQ7 or
erasure. The Erase Suspend command has a different DQ6 status bits, just as in the standard program oper-
effect depending on whether the Flash device is in ation. See “Write Operation Status” for more informa-
Asynchronous Mode or Burst Mode. tion.
Asynchronous Mode The system may also write the autoselect command
sequence when the device is in the Erase Suspend
The Erase Suspend command is only valid when the mode. The device allows reading autoselect codes
Flash device is in Asynchronous Mode. During Erase even at addresses within erasing sectors, since the
Suspend operation Asynchronous read/program oper- codes are not stored in the memory array. When the
ations behave normally in non-erasing sectors. How- device exits the autoselect mode, the device reverts to
ever, Erase Suspend operation prevents the Flash the Erase Suspend mode, and is ready for another
July 8, 2005 Am29BL162C 21

D A T A S H E E T
valid operation. See “Reset Command” for more infor- Erase Suspend command can be written after the de-
mation. vice has resumed erasing.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
22 Am29BL162C July 8, 2005

D A T A S H E E T
Command Definitions
Table 8. Am29BL162C Command Definitions
Bus Cycles (Notes 2–5)
Cycles
Command
Sequence First Second Third Fourth Fifth Sixth
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID, Bottom Boot Block 4 555 AA 2AA 55 555 90 X01 2203
Autoselect
(Note 8)
(SA) 0000
Sector Protect Verify (Note 9) 4 555 AA 2AA 55 555 90
X02 0001
0000
Burst Mode Status (Note 10) 4 555 AA 2AA 55 555 90 X03
0001
CFI Query (Note 11) 1 55 98
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 12) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 13) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 14) 1 XXX B0
Erase Resume (Note 15) 1 XXX 30
Burst Mode
Burst Mode Enable 4 555 AA 2AA 55 555 C0 XXX 01
Burst Mode Disable 4 555 AA 2AA 55 555 C0 XXX 00
Legend:
X = Don’t care PD = Data to be programmed at location PA. Data latches on the
RA = Address of the memory location to be read. rising edge of WE# or CE# pulse, whichever happens first.
RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations. 10. The data is 00h if the device is in asynchronous mode and
2. All values are in hexadecimal. 01h if in synchronous (burst) mode.
3. Except for the read cycle and the fourth cycle of the 11. Command is valid when device is ready to read array data or
autoselect command sequence, all bus cycles are write when device is in autoselect mode.
cycles. 12. The Unlock Bypass command is required prior to the Unlock
4. Data bits DQ15–DQ8 are don’t cares for unlock and Bypass Program command.
command cycles. 13. The Unlock Bypass Reset command is required to return to
5. Address bits A19–A11 are don’t cares for unlock and reading array data when the device is in the unlock bypass
command cycles, unless SA or PA required. mode.
6. No unlock or command cycles required when reading array 14. The system may read and program in non-erasing sectors, or
data. enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
7. The Reset command is required to return to reading array
sector erase operation.
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data). 15. The Erase Resume command is valid only during the Erase
Suspend mode.
8. The fourth cycle of the autoselect command sequence is a
read cycle.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Reset Command” for more
information.
July 8, 2005 Am29BL162C 23

D A T A S H E E T
WRITE OPERATION STATUS

The device provides several bits to determine the sta- Table 9 shows the outputs for Data# Polling on DQ7.
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, Figure 7 shows the Data# Polling algorithm.
and RY/BY#. Table 9 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress. START
These three bits are discussed first.
DQ7: Data# Polling

Read DQ7–DQ0
The Data# Polling bit, DQ7, indicates to the host system Addr = VA
whether an Embedded Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
DQ7 = Data? Yes
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the No
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system No
must provide the program address to read valid status DQ5 = 1?
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 µs, then the device returns to reading Yes
array data.
During the Embedded Erase algorithm, Data# Polling Read DQ7–DQ0
produces a “0” on DQ7. When the Embedded Erase al- Addr = VA
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the Yes
erase function changes all the bits in a sector to “1”; DQ7 = Data?
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in- No
formation on DQ7.
FAIL PASS
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de- Notes:
vice returns to reading array data. If not all selected 1. VA = Valid address for programming. During a sector
sectors are protected, the Embedded Erase algorithm erase operation, a valid address is an address within any
erases the unprotected sectors, and ignores the se- sector selected for erasure. During chip erase, a valid
lected sectors that are protected. address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
When the system detects DQ7 has changed from the DQ7 may change simultaneously with DQ5.
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
Figure 7. Data# Polling Algorithm
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 20, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
24 Am29BL162C July 8, 2005

D A T A S H E E T
RY/BY#: Ready/Busy# Table 9 shows the outputs for Toggle Bit I on DQ6.
Figure 8 shows the toggle bit algorithm in flowchart
The RY/BY# is a dedicated, open-drain output pin that
form, and the section “Reading Toggle Bits DQ6/DQ2”
indicates whether an Embedded Algorithm is in
explains the algorithm. Figure 21 in the “AC Character-
progress or complete. The RY/BY# status is valid after
istics” section shows the toggle bit timing diagrams.
the rising edge of the final WE# pulse in the command
Figure 22 shows the differences between DQ2 and
sequence. Since RY/BY# is an open-drain output, sev-
DQ6 in graphical form. See also the subsection on
eral RY/BY# pins can be tied together in parallel with a
“DQ2: Toggle Bit II”.
pull-up resistor to VCC. (The RY/BY# pin is not available
on the 44-pin SO package.)
DQ2: Toggle Bit II
If the output is low (Busy), the device is actively erasing The “Toggle Bit II” on DQ2, when used with DQ6, indi-
or programming. (This includes programming in the cates whether a particular sector is actively erasing
Erase Suspend mode.) If the output is high (Ready), (that is, the Embedded Erase algorithm is in progress),
the device is ready to read array data (including during or whether that sector is erase-suspended. Toggle Bit
the Erase Suspend mode), or is in the standby mode. II is valid after the rising edge of the final WE# pulse in
Table 9 shows the outputs for RY/BY#. Figures 15, 17, the command sequence.
18 and 19 shows RY/BY# for read, reset, program, and DQ2 toggles when the system reads at addresses
erase operations, respectively. within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
DQ6: Toggle Bit I trol the read cycles.) But DQ2 cannot distinguish
Toggle Bit I on DQ6 indicates whether an Embedded whether the sector is actively erasing or is erase-sus-
Program or Erase algorithm is in progress or complete, pended. DQ6, by comparison, indicates whether the
or whether the device has entered the Erase Suspend device is actively erasing, or is in Erase Suspend, but
mode. Toggle Bit I may be read at any address, and is cannot distinguish which sectors are selected for era-
valid after the rising edge of the final WE# pulse in the sure. Thus, both status bits are required for sector and
command sequence (prior to the program or erase op- mode information. Refer to Table 9 to compare outputs
eration), and during the sector erase time-out. for DQ2 and DQ6.
During an Embedded Program or Erase algorithm op- Figure 8 shows the toggle bit algorithm in flowchart
eration, successive read cycles to any address cause form, and the section “Reading Toggle Bits DQ6/DQ2”
DQ6 to toggle. (The system may use either OE# or explains the algorithm. See also the DQ6: Toggle Bit I
CE# to control the read cycles.) When the operation is subsection. Figure 21 shows the toggle bit timing dia-
complete, DQ6 stops toggling. gram. Figure 22 shows the differences between DQ2
and DQ6 in graphical form.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
Reading Toggle Bits DQ6/DQ2
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em- Refer to Figure 8 for the following discussion. When-
bedded Erase algorithm erases the unprotected sec- ever the system initially begins reading toggle bit sta-
tors, and ignores the selected sectors that are protected. tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
The system can use DQ6 and DQ2 together to deter- the system would note and store the value of the tog-
mine whether a sector is actively erasing or is erase- gle bit after the first read. After the second read, the
suspended. When the device is actively erasing (that is, system would compare the new value of the toggle bit
the Embedded Erase algorithm is in progress), DQ6 with the first. If the toggle bit is not toggling, the device
toggles. When the device enters the Erase Suspend has completed the program or erase operation. The
mode, DQ6 stops toggling. However, the system must system can read array data on DQ7–DQ0 on the fol-
also use DQ2 to determine which sectors are erasing lowing read cycle.
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”). However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
If a program address falls within a protected sector, tem also should note whether the value of DQ5 is high
DQ6 toggles for approximately 1 µs after the program (see the section on DQ5). If it is, the system should
command sequence is written, then returns to reading then determine again whether the toggle bit is toggling,
array data. since the toggle bit may have stopped toggling just as
DQ6 also toggles during the erase-suspend-program DQ5 went high. If the toggle bit is no longer toggling,
mode, and stops toggling once the Embedded Pro- the device has successfully completed the program or
gram algorithm is complete. erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system
July 8, 2005 Am29BL162C 25

D A T A S H E E T
must write the reset command to return to reading

array data.
The remaining scenario is that the system initially START
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, Read Byte
determining the status as described in the previous (DQ0-DQ7)
paragraph. Alternatively, it may choose to perform Address = VA
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to Read Byte
(DQ0-DQ7) (Note 1)
determine the status of the operation (top of Figure 8).
Address = VA
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
No
exceeded a specified internal pulse count limit. Under DQ6 = Toggle?
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed. Yes
The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro- No
DQ5 = 1?
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex- Yes
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the Read Byte Twice
reset command to return the device to reading array (DQ 0-DQ7) (Notes
Adrdess = VA 1, 2)
data.
DQ3: Sector Erase Timer

No
After writing a sector erase command sequence, the DQ6 = Toggle?
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional Yes
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
FAIL PASS
When the time-out is complete, DQ3 switches from “0” to
“1.” The system may ignore DQ3 if the system can
guarantee that the time between additional sector
erase commands always are less than 50 μs. See also Notes:
the “Sector Erase Command Sequence” section. 1. Read toggle bit twice to determine whether or not it is
toggling. See text.
After the sector erase command sequence is written,
2. Recheck toggle bit because it may stop toggling as DQ5
the system should read the status on DQ7 (Data# Poll-
changes to “1.” See text.
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If Figure 8. Toggle Bit Algorithm
DQ3 is “1,” the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0,” the device accepts additional sector erase
commands. To ensure the command has been ac-
cepted, the system software should check the status of
DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 9 shows the outputs for DQ3.
26 Am29BL162C July 8, 2005

D A T A S H E E T
Table 9. Write Operation Status

DQ7 DQ5 DQ2
Operation (Note 2) DQ6 (Note 1) DQ3 (Note 2) RY/BY#
Standard Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase
1 No toggle 0 N/A Toggle 1
Erase Suspended Sector
Suspend Reading within Non-Erase
Data Data Data Data Data 1
Mode Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
July 8, 2005 Am29BL162C 27

D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns 20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C +0.8 V
Voltage with Respect to Ground
–0.5 V
VCC (Note 1) . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
–2.0 V
A9, OE#, and RESET# (Note 2) . . –0.5 V to +13.0 V
All other pins (Note 1). . . . . . –0.5 V to +VCC+0.5 V 20 ns
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: Figure 9. Maximum Negative Overshoot
1. Minimum DC voltage on input and I/O pins is –0.5 V. Waveform
During voltage transitions, input and I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns. See
Figure 9. Maximum DC voltage on input and I/O pins is
VCC + 0.5 V. During voltage transitions input or I/O pins
may overshoot to VCC + 2.0 V for periods up to 20 ns. See
20 ns
Figure 10.
2. Minimum DC input voltage on pins A9, OE#, and RESET# VCC
is –0.5 V. During voltage transitions, A9, OE#, and +2.0 V
RESET# may overshoot VSS to –2.0 V for periods of up to VCC
20 ns. See Figure 9. Maximum DC input voltage on pin A9 +0.5 V
and OE# is +13.0 V which may overshoot to 14.0 V for 2.0 V
periods up to 20 ns.
3. No more than one output may be shorted to ground at a 20 ns 20 ns
time. Duration of the short circuit should not be greater
than one second. Figure 10. Maximum Positive Overshoot
4. Stresses above those listed under “Absolute Maximum Waveform
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the de-
vice at these or any other conditions above those indicated
in the operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating condi-
tions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –40°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range. . . . . . . 3.0 V to 3.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
28 Am29BL162C July 8, 2005

D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
VIN = VSS to 5.5 V,

ILI Input Load Current ±1.0 µA
VCC = VCC max
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
VOUT = VSS to 5.5 V,

ILO Output Leakage Current ±1.0 µA
VCC = VCC max
VCC Active Read Current

ICC1 CE# = VIL, OE# = VIH, 5 MHz 9 16 mA
(Notes 1, 2)
VCC Active Write Current

ICC2 CE# = VIL, OE# = VIH 20 30 mA
(Notes 2, 3, 6)
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.3 V 3 10 µA
VCC Standby Current During

ICC4 RESET# = VSS ± 0.3 V 3 10 µA
Reset (Note 2)
Automatic Sleep Mode VIH = VCC ± 0.3 V; OE# = VIH 3 10 µA

ICC5
(Notes 2, 4) VIL = VSS ± 0.3 V OE# = VIL 8 20 µA
25 MHz 15 30 mA
VCC Burst Mode Read Current CE# = VIL,
ICC6 33 MHz 20 35 mA
(Notes 2, 5) OE# = VIH
40 MHz 25 40 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC 5.5 V
Voltage for Autoselect and

VID VCC = 3.3 V 11.5 12.5 V
Temporary Sector Unprotect
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 IOH = –2.0 mA, VCC = VCC min 0.85 x VCC V

Output High Voltage
VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4
Low VCC Lock-Out Voltage (Note

VLKO 2.3 2.5 V
4)
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 3 µA.
5. 32-word average.
6. Not 100% tested.
July 8, 2005 Am29BL162C 29

D A T A S H E E T
DC CHARACTERISTICS (Continued)
Zero Power Flash
25
Supply Current in mA
20
15
10
0
0 500 1000 1500 2000 2500 3000 3500 4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
3.6 V
8
Supply Current in mA
2.7 V
0
1 2 3 4 5
Frequency in MHz
Note: T = 25 °C
Figure 12. Typical ICC1 vs. Frequency
30 Am29BL162C July 8, 2005

D A T A S H E E T
TEST CONDITIONS
Table 10. Test Specifications
3.3 V
65R, 90R,
Test Condition 70R 120R Unit
2.7 kΩ
Device Output Load 1 TTL gate
Under
Test Output Load Capacitance, CL
30 100 pF
(including jig capacitance)
CL 6.2 kΩ
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement

1.5 V
reference levels
Note: Diodes are IN3064 or equivalent
Output timing measurement
1.5 V
Figure 13. Test Setup reference levels
Key to Switching Waveforms
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
Input 1.5 V Measurement Level 1.5 V Output
0.0 V
Figure 14. Input Waveforms and Measurement Levels
July 8, 2005 Am29BL162C 31

D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Speed Options and
Parameter Temperature Ranges
65R 70R 90R 120R
JEDEC Std. Description Test Setup I E I, E I, E I, E Unit
tAVAV tRC Read Cycle Time (Note 1) Min 65 70 90 120 ns
CE# = VIL
tAVQV tACC Address to Output Delay Max 65 70 90 120 ns
OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 65 70 90 120 ns
tGLQV tOE Output Enable to Output Delay Max 17 18 24 26 26 ns
Chip Enable to Output High Z

tEHQZ tDF Max 17 18 24 26 26 ns
(Note 1)
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 20 25 30 30 ns
Read Min 0 ns
Output Enable
tOEH Toggle and
Hold Time (Note 1) Min 10 ns
Data# Polling
Output Hold Time From Addresses, CE# or

tAXQX tOH Min 0 ns
OE#, Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 13 and Table 10 for test specifications
32 Am29BL162C July 8, 2005

D A T A S H E E T
AC CHARACTERISTICS
Burst Mode Read
Parameter Speed Options and Temperature Ranges
65R 70R 90R 120R
JEDEC Std. Description I E I, E I, E I, E Unit
Initial Access Time

tIACC LBA# Valid Clock to Output Delay Max 65 70 90 120 ns
(See Note)
Burst Access Time

tBACC Max 17 18 24 26 26 ns
BAA# Valid Clock to Output Delay
tLBAS LBA# Setup Time Min 6 ns
tLBAH LBA# Hold Time Min 2 ns
tBAAS BAA# Setup Time Min 6 ns
tBAAH BAA# Hold Time Min 2 ns
tBDH Data Hold Time from Next Clock Cycle Max 4 ns
Address Setup Time to CLK

tACS Min 6 ns
(See Note)
Address Hold Time from CLK

tACH Min 2 ns
(See Note)
tOE Output Enable to Output Valid Max 17 18 24 26 26 ns
tOEZ Output Enable to Output High Z Max 20 25 30 30 ns
tCEZ Chip Enable to Output High Z Min 20 25 30 30 ns
tCES CE# Setup Time to Clock Min 6 ns
Note: Initial valid data is output after second clock rising edge of LBA# assertion.
July 8, 2005 Am29BL162C 33

D A T A S H E E T
AC CHARACTERISTICS
tRC
Addresses Addresses Stable

tACC
CE#
tDF
tOE
OE#
tOEH
WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid
RESET#
RY/BY#
0V
Figure 15. Conventional Read Operations Timings
tCES tCEZ
CE#
CLK
tLBAS
LBA#
tLBAH tBAAS
BAA# tACS
tBAAH
A0: A18 Aa
tBDH tBACC
tACH
DQ0: DQ15
tIACC Da Da + 1 Da + 2 Da + 3 Da + 31
tOE tOEZ
OE#*
IND#
Figure 16. Burst Mode Read
34 Am29BL162C July 8, 2005

D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC Std Description Test Setup All Speed Options Unit
RESET# Pin Low (During Embedded

tREADY Max 20 µs
Algorithms) to Read or Write (See Note)
RESET# Pin Low (NOT During Embedded

tREADY Max 500 ns
Algorithms) to Read or Write (See Note)
tRP RESET# Pulse Width Min 500 ns
RESET# High Time Before Read (See

tRH Min 50 ns
Note)
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 17. RESET# Timings
July 8, 2005 Am29BL162C 35

D A T A S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter Speed Options
JEDEC Std Description 65R 70R 90R 120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 65 70 90 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 45 45 45 50 ns
tDVWH tDS Data Setup Time Min 35 35 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

tGHWL tGHWL Min 0 ns
(OE# High to WE# Low)
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 35 35 50 ns
tWHWL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# Min 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
36 Am29BL162C July 8, 2005

D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
Addresses 555h PA PA PA
tAH
CE#
tCH
OE#
tWP tWHWH1
WE#
tWPH
tCS
tDS
tDH
Data A0h PD Status DOUT
tBUSY tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 18. Program Operation Timings
July 8, 2005 Am29BL162C 37

D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) Read Status Data
tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#
OE# tCH
tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete
10 for Chip Erase
tBUSY tRB
RY/BY#
tVCS
VCC
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 19. Chip/Sector Erase Operation Timings
38 Am29BL162C July 8, 2005

D A T A S H E E T
AC CHARACTERISTICS
tRC
Addresses VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data
High Z
DQ0–DQ6 Status Data Status Data True Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 20. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses VA VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
tBUSY
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 21. Toggle Bit Timings (During Embedded Algorithms)
July 8, 2005 Am29BL162C 39

D A T A S H E E T
AC CHARACTERISTICS
Enter
Embedded Erase Enter Erase Erase
Erasing Suspend Suspend Program Resume
WE# Erase Erase Suspend Erase Erase Suspend Erase Erase
Read Suspend Read Complete
Program
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 22. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations
Temporary Sector Unprotect

Parameter
JEDEC Std. Description All Speed Options Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
RESET# Setup Time for Temporary Sector

tRSP Min 4 µs
Unprotect
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
tVIDR tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 23. Temporary Sector Unprotect Timing Diagram
40 Am29BL162C July 8, 2005

D A T A S H E E T
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
Valid* Valid* Valid*
A1, A0
Sector Protect/Unprotect Verify
Data 60h 60h 40h Status
Sector Protect: 150 µs

1 µs Sector Unprotect: 15 ms
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 24. Sector Protect/Unprotect Timing Diagram
July 8, 2005 Am29BL162C 41

D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program
Operations
Parameter Speed Options
JEDEC Std Description 65R 70R 90R 120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 65 70 90 120 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 45 45 50 ns
tDVEH tDS Data Setup Time Min 35 35 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

tGHEL tGHEL Min 0 ns
(OE# High to WE# Low)
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 35 35 50 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWsH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
42 Am29BL162C July 8, 2005

D A T A S H E E T
AC CHARACTERISTICS
555 for program PA for program

2AA for erase SA for sector erase
555 for chip erase
Data# Polling
Addresses PA
tWC tAS
tAH
tWH
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tCPH
tBUSY
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 25. Alternate CE# Controlled Write Operation Timings
July 8, 2005 Am29BL162C 43

D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 5 15 s Excludes 00h programming

Chip Erase Time 55 s prior to erasure (Note 4)
Excludes system level

Word Programming Time 9 360 µs
overhead (Note 5)
Chip Programming Time (Note 3) 18 54 s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 8 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
–1.0 V 12.5 V
(including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
SSOP PIN CAPACITANCE

Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Test Conditions Min Unit
150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years
* For reference only. BSC is an ANSI standard for Basic Space Centering
44 Am29BL162C July 8, 2005

D A T A S H E E T
PHYSICAL DIMENSIONS*
SSO056—56-Pin Shrink Small Outline Package
Dwg rev AB; 10/99
July 8, 2005 Am29BL162C 45

D A T A S H E E T
REVISION SUMMARY Common Flash Memory Interface (CFI)

Corrected data for the following hex CFI addresses: 28,
Revision A (September 1998)
38, 39, 3C.
Initial release.
Command Definitions
Revision B (December 1998) Reorganized and rewrote the “Reading Array Data”
Global section into two sections entitled “Reading Array Data
Expanded data sheet into full version. in Non-burst Mode” and “Reading Array Data in Burst
Mode”. Added burst mode read figures comparing
Revision C (December 1998) system frequency and device speed. Added burst
Global mode status to autoselect command sequence in
command definitions table.
Added a separate set of read access specifications for
devices at industrial temperature range. Changed read Absolute Maximum Ratings
access specifications for 90 and 120 ns devices at Corrected the maximum VCC rating to +4.0 V, and the
extended temperature range to 28 ns. maximum all other pins rating to +5.5 V.
Ordering Information DC Characteristics table
Deleted commercial temperature rating. Corrected the maximum rating for VIH to 5.5 V.
Revision D (May 17, 1999) AC Characteristics
Global In the read operations and burst mode operations
Changed data sheet status to preliminary. Deleted the tables, reflected the global changes in speed options
70R speed option. Deleted the 70 speed option at (see the “global” revision entry).
extended temperature range. Added the 90R and 120R Burst Mode Read figure
speed options at extended temperature range. Deleted
Corrected figure. Deleted note; OE# and BAA# should
the 90 and 120 speed options at extended temperature
not be tied together. LBA# should be returned high
range.
after it coincides with a rising edge of CLK. BAA#
Distinctive Characteristics should not be asserted before the first word of data
Changed device endurance from program/erase cycles appears on the bus. The data is held on the outputs for
to erase cycles. only tBDH after the next clock.
Block Diagram Revision D+1 (July 2, 1999)

Deleted redundant path between state control and Command Definitions
erase voltage generator. Added sector switch block. Reading Array Data in Burst Mode: Added reference to
Deleted RY/BY# buffer. VCC and VSS are now shown figure 3 to the first paragraph.
properly.
Revision E (November 2, 1999)
Pin Configuration
Global
Clarified the explanation of IND#.
All speed options are now offered only at the regulated
Device Bus Operations voltage range of 3.0 to 3.6 V. The 90 and 120 ns speed
Reorganized and rewrote the following subsections: options now have a tOE of 26 ns at the industrial tem-
Requirements for Reading Array Data, Read Mode, perature range. The 70R speed option is now available
Burst Mode Read, IND# End of Burst Indicator, and at the extended temperature range.
Burst Mode Status. “Reading Array Data in Non-burst AC Characteristics
Mode”. The Burst Mode Status section is now inte-
grated into the autoselect mode section. In figures 17 and 18, deleted tGHWL. Modified OE#
waveform.
Device Bus Operations table: In the notes, deleted ref-
erence to BYTE# pin. Physical Dimensions
Updated drawing of SSOP to new version.
Sector Address table: Added sector address bit set-
tings for A19–A12.
46 Am29BL162C July 8, 2005

D A T A S H E E T
Revision F (June 20, 2000) Table 1, Device Bus Operations

Global In burst read operations section, changed BAA# to “H”
for “Load star ting Burst Address” and Terminate
The “preliminary” designation has been removed from
Current Burst Read Cycle; Start New Burst Read
the document. Parameters are now stable, and only
Cycle.”
speed, package, and temperature range combinations
are expected to change in future data sheet revisions. Requirements for Reading Array Data in
Synchronous (Burst) Mode
Distinctive Characteristics
Modified section to clarify the description of the IND#
Changed burst access time specification for the 65R
and burst read functions.
speed option in the industrial temperature range from
19 to 18 ns. Burst Sequence Table
Product Selector Guide Deleted table.
Replaced tOE with tBACC to more clearly distinguish Absolute Maximum Ratings
burst mode access from asynchronous access times. Modified maximum DC voltage and maximum positive
Note however, that in burst mode, tOE and tBACC spec- overshoot in Note 1 to refer to input and I/O pins.
ifications are identical. Changed tBACC for the 65R
speed option in the industrial temperature range from Revision F+3 (August 19, 2002)
19 to 18 ns. Product Selector Guide
Ordering Information Added Note #2.
Burn-in processing is no longer available.
Revision F+4 (September 12, 2002)
Requirements for Reading Array Data Array in Product Selector Guide
Asynchronous (Non-Burst) Mode
Removed Note #2.
Clarified the description of how to terminate a burst
mode read operation. Revision F+5 (November 22, 2002)
Burst Mode Read with 40 MHz CLK figure Distinctive Characteristics
Changed tBACC for the 65R speed option in the indus- Changed endurance to 1 million cycles.
trial temperature range from 19 to 18 ns. Erase Suspend/Erase Resume Command
Read Operations table Sequence
Changed tOE and tDF for the 65R speed option in the Noted that only asynchronous reads are allowed during
industrial temperature range from 19 to 18 ns. the erase suspend mode.
Burst Mode Read table Erase/Program Operations table, Alternate CE#

Controlled Erase/Program Operations table
Changed tOE and tBACC for the 65R speed option in the
industrial temperature range from 19 to 18 ns. Changed typical sector erase time from 3 s to 1 s.
Burst Mode Read figure Erase and Programming Performance

Corrected BAA# waveform to return high before the Changed typical/maximum sector erase time from 3
final clock cycle shown. s/60 s to 1 s/15 s, respectively. Changed typical chip
erase time from 40 s to 15 s. Changed endurance to 1
Erase and Programming Performance table, Erase million cycles. Added Asynchronous mode and Burst
and Program Operations table, Alternate CE# mode sections.
Controlled Erase and Program Operations table
Resolved differences in typical sector erase times. The Revision F+6 (June 10, 2004)
typical sector erase time for all sectors is 3 sec. Ordering Information
Revision F+1 (November 21, 2000) Changed temperature range from -55°C to -40°C.
Added table of contents. Added Figure 1, In-System Revision F+7 (October 29, 2004)
Sector Protect/Unprotect Algorithms figure to docu-
Ordering Information
ment (was missing from previous revisions).
Added:
Revision F+2 (July 22, 2002) F= Industrial –40°C to +°85C) for Pb-free Package
Pin Description, IND# End of Burst Indicator K= Extended –55°C to +125°C) for Pb-free Package
Clarified description of IND# function.
July 8, 2005 Am29BL162C 47

D A T A S H E E T
Valid Combinations Erase and Programming Performance Table

Added: ZF, ZK to each selection Updated Typical Sector Erase Time.
Revision F+8 (July 8, 2005) Updated Typical Chip Erase Time.
Distinctive Characteristics Update Note 1 and 6.

Updated Minimum sector erase cycles. Global
Updated Colophon and Trademark.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright ©2003-2005 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
48 Am29BL162C July 8, 2005

Am29BL162C: Data Sheet

Uploaded by

Copyright:

Available Formats

Am29BL162C: Data Sheet

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Am29BL162C: Data Sheet

Uploaded by

Copyright:

Available Formats

www.DataSheet4U.

Continuity of Ordering Part Numbers

For More Information

Publication Number 22142 Revision F Amendment +8 Issue Date July 8, 2005

2 Am29BL162C July 8, 2005

July 8, 2005 Am29BL162C 3

PRODUCT SELECTOR GUIDE

Max access time, ns (tACC) 65 70 90 120

Max CE# access time, ns (tCE) 65 70 90 120

Max burst access time, ns (tBACC) 17 18 24 26 26

LBA# Burst Burst A0–A2

4 Am29BL162C July 8, 2005

July 8, 2005 Am29BL162C 5

LBA# High indicates that the address RESET#

6 Am29BL162C July 8, 2005

BOOT CODE SECTOR ARCHITECTURE

Am29BL162CB-120R ZI, ZE, ZF, ZK

For information on full voltage range options (2.7 – 3.6 V),

July 8, 2005 Am29BL162C 7

DEVICE BUS OPERATIONS

Table 1. Device Bus Operations

Read L L H H X X X AIN DOUT

Write L H L H X X X AIN DIN

Output Disable L H H H X X X HIGH Z HIGH Z

Temporary Sector Unprotect X X X VID X X X AIN HIGH Z

Burst Read Operations

Load Starting Burst Address L X H H L H AIN X

Advance Burst to Next Address (no

Advance Burst to Next address

Terminate Current Burst Read Cycle H X H H X X X HIGH Z

Terminate Current Burst Read Cycle;

Burst Suspend (all data is retained

Burst Resume (same data as Burst Data Out

Burst Resume (incremented data from Data Out

8 Am29BL162C July 8, 2005

July 8, 2005 Am29BL162C 9

10 Am29BL162C July 8, 2005

Table 2. Sector Address Table

SA0 8 Kwords 0 0 0 0 0 0 0 X 00000h–01FFFh

SA1 4 Kwords 0 0 0 0 0 0 1 0 02000h–02FFFh

SA2 4 Kwords 0 0 0 0 0 0 1 1 03000h–03FFFh

SA3 112 Kwords 0 0 0 00100–11111 04000h–1FFFFh

SA4 128 Kwords 0 0 1 X X X X X 20000h–3FFFFh

SA5 128 Kwords 0 1 0 X X X X X 40000h–5FFFFh

SA6 128 Kwords 0 1 1 X X X X X 60000h–7FFFFh

SA7 128 Kwords 1 0 0 X X X X X 80000h–9FFFFh

SA8 128 Kwords 1 0 1 X X X X X A0000h–BFFFFh

SA9 128 Kwords 1 1 0 X X X X X C0000h–DFFFFh

SA10 128 Kwords 1 1 1 X X X X X E0000h–FFFFFh

July 8, 2005 Am29BL162C 11

Autoselect Mode Table 1. In addition, when verifying sector protection,

Table 3. Am29BL162C Autoselect Codes (High Voltage Method)

Manufacturer ID: AMD L L H X X VID X L X L L 0001h

Sector Protection X VID X L X H L 0001h (protected)

12 Am29BL162C July 8, 2005

Protect all sectors:

Algorithm complete Algorithm

Figure 1. In-System Sector Protect/Unprotect Algorithms

July 8, 2005 Am29BL162C 13