PM49FL002

PMC Pm49FL002 / Pm49FL004
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
FEATURES
• Single Power Supply Operation • Firmware HUB (FWH)/Low Pin Count

- Low voltage range: 3.0 V - 3.6 V (LPC) Mode
- 33 MHz synchronous operation with PCI bus
• Standard Intel Firmware Hub/LPC Inter- - 5-signal communication interface for in-
face system read and write operations
- Read compatible to Intel® 82802 Firmware - Standard SDP Command Set
Hub devices - Data# Polling and Toggle Bit features
- Conforms to Intel LPC Interface Specification - Register-based read and write protection for
Revision 1.1 each block (FWH mode only)
- 4 ID pins for multiple Flash chips selection
• Memory Configuration (FWH mode only)
- Pm49FL002: 256K x 8 (2 Mbit) - 5 GPI pins for General Purpose Input Register
- Pm49FL004: 512K x 8 (4 Mbit) - TBL# pin for hardware write protection to Boot
Block
• Cost Effective Sector/Block Architecture - WP# pin for hardware write protection to whole
- Pm49FL002: Sixty-four uniform 4 Kbyte memory array except Boot Block
sectors, or sixteen uniform 16 Kbyte blocks
(sector group) • Address/Address Multiplexed (A/A Mux)
- Pm49FL004: One hundred and twenty-eight Mode
uniform 4 Kbyte sectors, or eight uniform 64 - 11-pin multiplexed address and 8-pin data I/O
Kbyte blocks (sector group) interface
- Supports fast programming on EPROM
• Top Boot Block programmers
- Pm49FL002: 16 Kbyte top Boot Block - Standard SDP Command Set
- Pm49FL004: 64 Kbyte top Boot Block
- Data# Polling and Toggle Bit features
• Automatic Erase and Program Operation
- Build-in automatic program verification for • Lower Power Consumption
extended product endurance - Typical 2 mA active read current
- Typical 25 µs/byte programming time - Typical 7 mA program/erase current
- Typical 50 ms sector/block/chip erase time
• High Product Endurance
• Two Configurable Interfaces - Guarantee 100,000 program/erase cycles per
- In-System hardware interface: Auto detection single sector (preliminary)
of Firmware Hub (FWH) or Low Pin Count - Minimum 20 years data retention
(LPC) memory cycle for in-system read and
write operations • Compatible Pin-out and Packaging
- Address/Address-Multiplexed (A/A Mux)
- 32-pin (8 mm x 14 mm) VSOP
interface for programming on EPROM Pro-
- 32-pin PLCC
grammers during manufacturing
- Optional lead-free (Pb-free) package
• Hardware Data Protection
Programmable Microelectronics Corp. 1 Issue Date: December, 2003 Rev:1.4

PMC and P-Flash are registered trademark of Programmable Microelectronics Corporation.
Intel is a registered trademark of Intel Corporation.
PMC Pm49FL002 / 004
GENERAL DESCRIPTION
The Pm49FL002/004 are 2 Mbit/4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These
devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform in-
system or off-system read, erase and program operations. The 12.0 Volt VPP power supply are not required for the
program and erase operations of devices. The devices conform to Intel® Low Pin Count (LPC) Interface specification
revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applica-
tions. The Pm49FL002/004 support two configurable interfaces: In-system hardware interface which can automatic
detect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed
(A/A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both
Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great
flexibility and simplicity for design, procurement, and material inventory.
The memory array of Pm49FL002 is divided into uniform 4 Kbyte sectors, or uniform 16 Kbytes blocks (sector
group - consists of four adjecent sectors). The memory array of Pm49FL004 is divided into uniform 4 Kbyte sectors,
or uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). The sector or block erase feature
allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase
operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one
single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase opera-
tion.
The program operation of Pm49FL002/004 is executed by issuing the program command code into command
register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase
operation of the devices is executed by issuing the sector, block, or chip erase command code into command
register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming
on the array which has not been programmed is not required before an erase operation. The devices offer Data#
Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and
erase operations can be detected by reading the Data# Polling on I/O7 or Toggle Bit on I/O6.
The Pm49FL002 has a 16 Kbyte top boot block which can be used to store user security data and code. The
Pm49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled
by the TBL# pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The
rest of blocks except boot block in the devices also can be write protected by WP# pin or Block Locking Registers
(FWH mode only).
The Pm49FL002/004 are manufactured on PMC’s advanced nonvolatile technology, P-FLASH™. The devices are
offered in 32-pin VSOP and PLCC packages with optional environmental friendly lead-free package.
Programmable Microelectronics Corp. 2 Issue Date: December, 2003 Rev: 1.4

PMC Pm49FL002 / 004
CONNECTION DIAGRAMS
FWH
RST#
GPI2
GPI3
GPI4
CLK
VCC
NC
RST# RST#
GPI2
GPI3
A/A Mux LPC
GPI4
R/C# CLK
VCC
NC
A10
VCC
NC
A8
A9
FWH LPC A/A Mux
A/A Mux LPC FWH
4 3 2 1 32 31 30
GPI1 GPI1 A7 5 29 IC IC IC
GPI0 GPI0 A6 6 28 GND GND GND
WP# WP# A5 7 27 NC NC NC
TBL# TBL# A4 8 26 NC NC NC
ID3 RES A3 9 25 VCC VCC VCC
ID2 RES A2 10 24 OE# INIT# INIT#
ID1 RES A1 11 23 WE# LFRAME# FWH4
ID0 RES A0 12 22 NC NC NC
FWH0 LAD0 I/O0 13 21 I/O7 RES RES

14 15 16 17 18 19 20
A/A Mux
I/O6
I/O1
I/O2
GND
I/O3
I/O4
I/O5
LAD1
RES
RES
LAD2
LPC
LAD3
RES
GND
GND
FWH2
RES
FWH1
RES
RES
FWH3
FWH
32-PIN PLCC
FWH LPC A/A Mux A/A Mux LPC FWH

VCC VC C VCC 1 32 OE# INIT# INIT#
NC NC NC 2 31 WE# LFRAME# FWH4
NC NC NC 3 30 NC NC NC
GND GND GND 4 29 I/O7 RES RES
IC IC IC 5 28 I/O6 RES RES
GPI4 GPI4 A10 6 27 I/O5 RES RES
CLK CLK R/C# 7 26 I/O4 RES RES
VCC VC C VCC 8 25 I/O3 LAD3 FWH3
NC NC NC 9 24 GND GND GND
RST# RST# RST# 10 23 I/O2 LAD2 FWH2
GPI3 GPI3 A9 11 22 I/O1 LAD1 FWH1
GPI2 GPI2 A8 12 21 I/O0 LAD0 FWH0
GPI1 GPI1 A7 13 20 A0 RES ID0
GPI0 GPI0 A6 14 19 A1 RES ID1
WP# WP# A5 15 18 A2 RES ID2
TBL# TBL# A4 16 17 A3 RES ID3
32-PIN (8mm x 14mm) VSOP

PMC Pm49FL002 / 004
PRODUCT ORDERING INFORMATION
Pm49FL00x T -33 J C E
Environmental Attribute
E = Lead-free (Pb-free) Package
Blank = Standard Package
Temperature Range
C = Commercial (0°C to +70°C)
Package Type
J = 32-pin Plastic J-Leaded Chip Carrier (32J)
V = 32-pin (8 mm x 14 mm) VSOP (32V)
Speed Option
Boot Block Location

T = Top Boot Block
PMC Device Number

Pm49FL002 (2 Mbit)
Pm49FL004 (4 Mbit)
Boot Block Temperature

Part Number MHz P ackag e
Location R an g e
Pm49FL002T-33JCE
32J
Pm49FL002T-33JC Commercial
33 Top
Pm49FL002T-33VCE (0°C to +70°C)
32V
Pm49FL002T-33VC
Pm49FL004T-33JCE
32J
Pm49FL004T-33JC Commercial
33 Top
Pm49FL004T-33VCE (0°C to +70°C)
32V
Pm49FL004T-33VC

PMC Pm49FL002 / 004
PIN DESCRIPTIONS
Interface
SYMB OL TYPE D ESC R IPTION
PP FWH LP C
Address Inputs: For i nputi ng the multi plex addresses and commands i n
A[10:0] I X PP mode. Row and column addresses are latched duri ng a read or
wri te cycle controlled by R/C # pi n.
Row/C olumn Select: To i ndi cate the row or column address i n PP
R/C # I X mode. When thi s pi n goes low, the row address i s latched. When thi s
pi n goes hi gh, the column address i s latched.
D ata Inputs/Outputs: Used for A/A Mux mode only, to i nput
I/O[7:0] I/O X command/data duri ng wri te operati on and to output data duri ng read
operati on. The data pi ns float to tri -state when OE# i s di sabled.
WE# I X Wri te Enable: Acti vate the devi ce for wri te operati on. WE# i s acti ve low.
Output Enable: C ontrol the devi ce's output buffers duri ng a read cycle.
OE# I X
OE# i s acti ve low.
Interface C onfi gurati on Select: Thi s pi n determi nes whi ch mode i s
selected. When pulls hi gh, the devi ce enters i nto A/A Mux mode. When
IC I X X X pulls low, FWH/LPC mode i s selected. Thi s pi n must be setup duri ng
power-up or system reset, and stays no change duri ng operati on. Thi s
pi n i s i nternally pulled down wi th a resi stor between 20-100 KΩ.
RST# I X X X Reset: To reset the operati on of the devi ce and return to standby mode.
Ini ti ali ze: Thi s i s a second reset pi n for i n-system use. INIT# or RST# pi n
INIT# I X X
pulls low wi ll i ni ti ate a devi ce reset.
FWH/LPC General Purpose Inputs: Used to set the GPI_REG for
system desi gn purpose only. The value of GPI_REG can be read
through FWH i nterface. These pi ns should be set at desi red state
GPI[4:0] I X X
before the start of the PC I clock cycle for read operati on and should
remai n no change unti l the end of the read cycle. Unused GPI pi ns must
not be floated.
Top Block Lock: When pulls low, i t enables the hardware wri te protecti on
TBL# I X X for top boot block. When pulls hi gh, i t di sables the hardware wri te
protecti on.
Wri te Protect: When pulls low, i t enables the hardware wri te protecti on
WP# I X X to the memory array except the top boot block. When pulls hi gh, i t
di sables hardware wri te protecti on.
FWH Address and D ata: The major I/O pi ns for transmi tti ng data,
FWH[3:0] I/O X
addresses and command code i n FWH mode.
FWH Input: To i ndi cate the start of a FWH memory cycle operati on.
FWH4 I X
Also used to abort a FHW memory cycle i n progress.
LPC Address and D ata: The major I/O pi ns for transmi tti ng data,
LAD [3:0] I/O X
addresses and command code i n LPC mode.
LPC Frame: To i ndi cate the start of a LPC memory cycle operati on.
LFRAME# I X
Also used to abort a LPC memory cycle i n progress.
FWH/LPC C lock: To provi de a synchronous clock for FWH and LPC
C LK I X X
mode operati ons.
Identi fi cati on Inputs: These four pi ns are part of the mechani sm that
allows multi ple FWH devi ces to be attached to the same bus. The
strappi ng of these pi ns i s used to i denti fy the component. The boot
ID [3:0] I X
devi ce must have ID [3:0] = 0000b and i t i s recommended that all
subsequent devi ces should use sequenti al up-count strappi ng. These
pi ns are i nternally pulled-down wi th a resi stor between 20-100 KΩ.
V CC X X X D evi ce Power Supply
GND X X X Ground
NC X X X No C onnecti on
RES X X Reserved: Reserved functi on pi ns for future use.
Note: I = Input, O = Output

PMC Pm49FL002 / 004
BLOCK DIAGRAM
ERASE/PROGRAM
TBL# VOLTAGE
WP# GENERATOR
INIT#
I/O BUFFERS
FWH[3:0] or
LAD[3:0]
FWH4 or LFRAME# FWH/LPC
MODE HIGH VOLTAGE
CLK
GPI[4:0] INTERFACE SWITCH
A[10:0]
I/O[7:0]
PP MODE
WE# INTERFACE CONTROL DATA SENSE
OE#
LOGIC LATCH
R/C# AMP
IC
RST#
Y-GATING
ADDRESS
Y-DECODER
LATCH MEMORY
ARRAY
X-DECODER
DEVICE OPERATION
MODE SELECTION PRODUCT IDENTIFICATION
The Pm49FL002/004 can operate in two configurable The product identification mode can be used to read the
interfaces: The In-System Hardware interface and Ad- Manufacturer ID and the Device ID by a software Prod-
dress/Address Multiplexed (A/A Mux) interface con- uct ID Entry command in both in-system hardware in-
trolled by IC pin. If the IC pin is set to logic high (VIH), terface and A/A Mux interface modes. The product
the devices enter into A/A Mux interface mode. If the IC indentification mode is activated by three-bus-cycle com-
pin is set logic low (VIL), the devices will be in in-system mand. Refer to Table 1 for the Manufacturer ID and De-
hardware interface mode. During the in-system hard- vice ID of Pm49FL00x and Table 14 for the SDP Com-
ware interface mode, the devices can automatically de- mand Definition.
tect the Firmware Hub (FWH) or Low Pin Count (LPC)
memory cycle sent from host system and response to In FWH mode, the product identification can also be
the command accordingly. The IC pin must be setup read directly at FFBC0000h for Manufacturer ID - “9Dh”
during power-up or system reset, and stays no change and FFBC0001h for Device ID in the 4 GByte system
during device operation. memory map.
When working in-system, typically on a PC or Note- Table 1: Product Identification

book, the Pm49FL002/004 are connected to the host
system through a 5-pin communication interface oper-
ated based on a 33-MHz synchronous clock. The 5-pin Description Address Data
interface is defined as FWH[3:0] and FWH4 pins under
FWH mode or as LAD[3:0] and LFRAME# pins under 00000h 9D h
Manufacturer ID
LPC mode for easy understanding as to those existing 00002h 7F h
compatible products. When working off-system, typi-
cally on a EPROM Programmer, the devices are oper- Device ID
ated through 11-pin multiplexed address - A[10:0] and Pm49FL002 2Mb 00001h 6D h
8-pin data I/O - I/O[7:0] interfaces. The memory ad- Pm49FL004 4Mb 6E h
dresses of devices are input through two bus cycles as
row and column addresses controlled by a R/C# pin.

PMC Pm49FL002 / 004
DEVICE OPERATION (CONTINUED)
The Pm49FL002/004 provide three levels of data protec- SOFTWARE DATA PROTECTION
tion for the critical BIOS code of PC and Notebook. It
includes memory hardware write protection, hardware The devices feature a software data protection function
data protection and software data protection. to protect the device from an unintentional erase or pro-
gram operation. It is performed by JEDEC standard Soft-
MEMORY HARDWARE WRITE PROTECTION ware Data Protection (SDP) command sequences. See
Table 14 for SDP Command Definition. A program op-
The Pm49FL002 has a 16 Kbyte top boot block and the eration is initiated by three memory write cycles of un-
Pm49FL004 has a 64 Kbyte top boot block. When work- lock command sequence. A chip (only available in A/A
ing in-system, the memory hardware write protection fea- Mux mode), sector or block erase operation is initiated
ture can be activated by two control pins - Top Block by six memory write cycles of unlock command se-
Lock (TBL#) and Write Protection (WP#) for both FWH quence. During SDP command sequence, any invalid
and LPC modes. When TBL# is pulled low (VIL), the boot command or sequence will abort the operation and force
block is hardware write protected. A sector erase, block the device back to standby mode.
erase, or byte program command attempts to erase or
program the boot block will be ignored. When WP# is BYTE PROGRAMMING
pulled low (VIL), the Block 0 ~ Block 14 of Pm49FL002,
or the Block 0 ~ Block 6 of Pm49FL004 (except the boot In program operation, the data is programmed into the
block) are hardware write protected. Any attemp to erase devices (to a logical “0”) on a byte-by-byte basis. In FWH
or program a sector or block within this area will be ig- and LPC modes, a program operation is activated by
nored. writing the three-byte command sequence and program
address/data through four consecutive memory write
Both TBL# and WP# pins must be set low (VIL) for pro- cycles. In A/A Mux mode, a program operation is acti-
tection or high (VIH) for un-protection prior to a program vated by writing the three-byte command sequence and
or erase operation. A logic level change on TBL# or WP# program address/data through four consecutive bus
pin during a program or erase operation may cause un- cycles. The row address (A10 - A0) is latched on the
predictable results. falling edge of R/C# and the column address (A21 - A11)
is latched on the rising edge of R/C#. The data is latched
The TBL# and WP# pins work in combination with the on the rising edge of WE#. Once the program operation
block locking registers. When active, these pins write is started, the internal control logic automatically handles
protect the appropriate blocks regardless of the associ- the internal programming voltages and timing.
ated block locking registers setting.
A data “0” can not be programmed back to a “1”. Only
HARDWARE DATA PROTECTION erase operation can convert “0”s to “1”s. The Data# Poll-
ing on I/O7 or Toggle Bit on I/O6 can be used to detect
Hardware data protection protects the devices from un- when the programming operation is completed in FWH,
intentional erase or program operation. It is performed LPC, and A/A Mux modes.
by the devices automatically in the following three ways:
(a) VCC Detection: if VCC is below 1.8 V (typical), the CHIP ERASE
program and erase functions are inhibited.
(b) Write Inhibit Mode: holding any of the signal OE# The entire memory array can be erased by chip erase
low, or WE# high inhibits a write cycle (A/A Mux mode operation available under the A/A Mux mode operated
only). by EPROM Programmer only. Pre-programs the device
(c) Noise/Glitch Protection: pulses of less than 5 ns (typi- is not required prior to the chip erase operation. Chip
cal) on the WE# input will not initiate a write cycle (A/A erase starts immediately after a six-bus-cycle chip erase
Mux mode only). command sequence. All commands will be ignored once
the chip erase operation has started. The Data# Polling
on I/O7 or Toggle Bit on I/O6 can be used to detect the
progress or completion of erase operation. The devices
will return back to standy mode after the completion of
chip erase.
PMC Pm49FL002 / 004
DEVICE OPERATION (CONTINUED)
SECTOR AND BLOCK ERASE I/O6 TOGGLE BIT
The Pm49FL002 contains sixty-four uniform 4 Kbyte sec- The Pm49FL002/004 also provide a Toggle Bit feature to
tors, or sixteen uniform 16 Kbyte blocks (sector group - detect the progress or the completion of a program or
consists of four adjecent sectors). The Pm49FL004 con- erase operation. During a program or erase operation,
tains one hundred and twenty-eight uniform 4 Kbyte sec- an attempt to read data from the devices will result in I/
tors, or eight uniform 64 Kbyte blocks (sector group - O6 toggling between “1” and “0”. When the program or
consists of sixteen adjecent sectors). A sector erase erase operation is complete, I/O6 will stop toggling and
command is used to erase an individual sector. A block valid data will be read. Toggle bit may be accessed at
erase command is used to erase an individual block. any time during a program or erase operation.
See Table 12 - 13 for Sector/Block Address Tables.
RESET
In FWH/LPC mode, an erase operation is activated by
writing the six-byte command sequence through six con- Any read, program, or erase operation to the devices
secutive write memory cycles. In A/A Mux mode, an can be reset by the INIT# or RST# pins. INIT# and RST#
erase operation is activated by writing the six-byte com- pins are internally hard-wired and have same function to
mand in six consecutive bus cycles. Pre-programs the the devices. The INIT# pin is only available in FWH and
sector or block is not required prior to an erase opera- LPC modes. The RST# pin is available in all modes. It
tion. is required to drive INIT# or RST# pins low during sys-
tem reset to ensure proper initialization.
I/O7 DATA# POLLING
During a memory read operation, pulls low the INIT# or
The devices provide a Data# Polling feature to indicate RST# pin will reset the devices back to standby mode
the progress or the completion of a program or erase and then the FWH[3:0] of FWH interface or the LAD[3:0]
operation in all modes. During a program operation, an of LPC interface will go to high impedance state. During
attempt to read the device will result in the complement a program or erase operation, pulls low the INIT# or RST#
of the last loaded data on I/O7. Once the program cycle pin will abort the program or erase operation and reset
is complete, the true data of the last loaded data is valid the devices back to standby mode. A reset latency will
on all outputs. During an erase operation, an attempt to occur before the devices resume to standby mode when
read the device will result a “0” on I/O7. After the erase such reset is performed. When a program or erase op-
cycle is complete, an attempt to read the device will eration is reset before the completion of such opera-
result a “1” on I/O7. tion, the memory contents of devices may become
invalid due to an incomplete program or erase opera-
tion.

PMC Pm49FL002 / 004
FWH MODE OPERATION
FWH MODE MEMORY READ/WRITE OPERATION FWH ABORT OPERATION
In FWH mode, the Pm49FL002/004 are connected The FWH4 signal indicates the start of a memory cycle
through a 5-pin communication interface - FWH[3:0] and or the termination of a cycle in FWH mode. Asserting
FWH4 pins to work with Intel® Family of I/O Controller FWH4 for one or more clock cycle with a valid START
Hubs (ICH) chipset platforms. The FWH mode also sup- value on FWH[3:0] will initiate a memory read or memory
port JEDEC standard Software Data Protection (SDP) write cycle. If the FWH4 is driven low again for one or
product ID entry, byte program, sector erase, and block more clock cycles during this cycle, this cycle will be
erase command sequences. The chip erase command terminated and the device will wait for the ABORT com-
sequence is only available in A/A Mux mode. mand “1111b” to release the FWH[3:0] bus. If the abort
occurs during the program or erase operation such as
The addresses and data are transmitted through the 4- checking the operation status with Data# Polling (I/O7)
bit FWH[3:0] bus synchronized with the input clock on or Toggle Bit (I/O6) pins, the read status cycle will be
CLK pin during a FWH memory cycle operation. The aborted but the internal program or erase operation will
address or data on FWH[3:0] bus is latched on the ris- not be affected. Only the reset operation initiated by RST#
ing edge of the clock. The pulse of FWH4 pin inserted or INIT# pin can terminate the program or erase opera-
for one clock indicates the start of a FWH memory read tion.
or memory write cycle.
Once the FWH memory cycle is started, asserted by

FWH4, a START value “11xxb” is expected by
Pm49FL002/004 as a valid command cycle and is used
to indicates the type of memory cycle (“1101b” for FWH
memory read cycle or “1110b” for FWH memory write
cycle). Addresses and data are transferred to and from
the device decided by a series of “fields”. Field sequences
and contents are strictly defined for FWH memory read
and write operations. Refer to Table 2 and 3 for FWH
Memory Read Cycle Definition and FWH Memory Write
Cycle Definition.
There are 7 clock fields in a FWH memory cycle that

gives a 28 bit memory address A27 - A0 through
FWH[3:0] pins, but only the last five address fields will
be decoded by the FWH devices. The Pm49FL002 de-
codes A17 - A0 with A19 and A18 ignored. The
Pm49FL004 decodes A18 - A0 with A19 ignored. The
address A22 has the special function of directing reads
and writes to the Flash array when A22 = 1 or to the
register space with A22 = 0. The A27 - A23 and A21 -
A20 are don’t care for the devices under FWH mode.
The Pm49FL002/004 are mapped within the top 4 Mbyte

address range devoted to the FWH devices in the 4 Gbyte
system memory space. Please see Table 11 for System
Memory Map.

PMC Pm49FL002 / 004
FWH MODE OPERATION (CONTINUED)
Table 2: FWH Memory Read Cycle Definition
Clock Cycle Field FWH[3: 0] Direction Description

Start of Cycle: "1101b" to indicate the start of a memory
1 START 1101 IN
read cycle.
ID Select Cycle: Indicates which FWH device should respond.
0000 to If the IDSEL field matches the value set on ID[3:0] pins, then
2 IDSEL IN
1111 the particular FWH device will respond to subsequent
commands.
Address Cycles: This is the 28-bit memory address. The
addresses transfer most-significant nibble first and least-
3-9 IMADDR YYYY IN
significant nibble last. (i.e., A27 - 24 on FWH[3:0] first, and
A3 - A0 on FWH[3:0] last).
Memory Size Cycle: Indicates how many bytes will be or
10 IMSIZE 0000 IN transferred during multi-byte operations. The Pm49FL00x only
support "0000b" for one byte operation.
IN then Turn-Around Cycle 0: The Intel ICH has driven the bus then
11 TAR0 1111
Float float it to all "1"s and then floats the bus.
1111 Float then Turn-Around Cycle 1: The device takes control of the bus
12 TAR1
(float) OUT during this cycle.
0000 Ready Sync: The FWH device indicates the least-significant
13 RSYNC OUT
(READY) nibble of data byte will be ready in next clock cycle.
Data Cycles: The 8-bits data transferred with least-significant
14-15 DATA YYYY OUT nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on
LAD[3:0] first, then I/O7 - I/O4 on FWH[3:0] last).
OUT then Turn -Around Cycle 0: The FWH device has driven the bus
16 TAR0 1111
Float then float it to all "1"s and then floats the bus.
1111 Float then Turn-Around Cycle 1: The Intel ICH resumes control of the bus
17 TAR1
(float) IN during this cycle.
FWH MEMORY READ CYCLE WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Read
IDSEL Address IMSIZE TAR RSYNC Data TAR Next Start
Start
FWH[3:0] 1101b ID[3:0] xxxxb x1xxb A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 0000b 1111b Tri-State 0000b D[3:0] D[7:4] 1111b Tri-State 1101b
1 Clock 1 Clock Load Address in 7 Clocks 2 Clocks 1 Clock Data Out 2 Clocks 2 Clocks 1 Clock
From Host to Device From Device to Host

PMC Pm49FL002 / 004
Table 3: FWH Memory Write Cycle Definition
Clock Cycle Field FWH[3: 0] Direction Description

Start of Cycle: "1110b" to indicate the start of a memory
1 START 1110 IN
write cycle.
ID Select Cycle: Indicates which FWH device should respond.
0000 to If the IDSEL field matches the value set on ID[3:0] pins, then
2 IDSEL IN
1111 the particular FWH device will respond to subsequent
commands.
3-9 IMADDR YYYY IN
significant nibble last. (i.e., A27 - 24 on FWH[3:0] first, and
A3 - A0 on FWH[3:0] last).
Memory Size Cycle: Indicates how many bytes will be or
10 IMSIZE 0000 IN transferred during multi-byte operations. The Pm49FL00x only
support "0000b" for one byte operation.
11-12 DATA YYYY IN nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on
LAD[3:0] first, then I/O7 - I/O4 on FWH[3:0] last).
IN then Turn-Around Cycle 0: The Intel ICH has driven the bus then
13 TAR0 1111
Float float it to all "1"s and then floats the bus.
14 TAR1
0000 Ready Sync: The FWH device indicates that it has received
15 RSYNC OUT
(READY) the data or command.
OUT then Turn-Around Cycle 0: The FWH device has driven the bus
16 TAR0 1111
Float then float it to all "1"s and then floats the bus.
1111 Float then Turn-Around Cycle 1: The Intel ICH resumes control of the bus
17 TAR1
FWH MEMORY WRITE CYCLE WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Write
IDSEL Address IMSIZE Data TAR RSYNC TAR Next Start
Start
FWH[3:0] 1110b ID[3:0] xxxxb x1xxb A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 0000b D[3:0] D[7:4] 1111b Tri-State 0000b 1111b Tri-State 1110b
1 Clock 1 Clock Load Address in 7 Clocks 1 Clock Load Data in 2 Clocks 2 Clocks 1 Clock 2 Clocks 1 Clock

PMC Pm49FL002 / 004
FWH BYTE PROGRAM WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Write
IDSEL Address IMSIZE Data TAR RSYNC TAR
Cycle
FWH[3:0] 1110b ID[3:0] xxxxb x1xxb xxxxb 0101b 0101b 0101b 0101b 0000b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State
1 Clock 1 Clock Load "5555h" in 7 Clocks 1 Clock Load "AAh" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
Host to Device Device to Host
CLK
RST# or INIT#
FWH4
2nd Start IDSEL Address IMSIZE Data TAR RSYNC TAR
1 Clock 1 Clock Load "2AAAh" in 7 Clocks 1 Clock Load "55h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
FWH4
3rd Start IDSEL Address IMSIZE Data TAR RSYNC TAR
1 Clock 1 Clock Load "5555h" in 7 Clocks 1 Clock Load "A0h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
FWH4
4th Start IDSEL Address IMSIZE Data TAR RSYNC TAR
FWH[3:0] 1110b ID[3:0] xxxxb x1xxb A[19:16] A[15:12] A[11:8] A[7:4] A[3:1] 0000b D[3:0] D[7:4] 1111b Tri-State 0000b 1111b Tri-State
1 Clock 1 Clock Load Address in 7 Clocks 1 Clock Load Data in 2 Clocks 2 Clocks 1 Clock 2 Clocks

PMC Pm49FL002 / 004
FWH SECTOR ERASE WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Write Cycle IDSEL Address IMSIZE Data TAR RSYNC TAR
1110b ID[3:0] 0000b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State
FWH[3:0] xxxxb x1xxb xxxxb 0101b 0101b 0101b 0101b
CLK
RST# or INIT#
FWH4
xxxxb x1xxb 0010b 1010b 0000b 0101b 0101b Tri-State

FWH[3:0] 1110b ID[3:0] xxxxb 1010b 1010b 1111b Tri-State 0000b 1111b
CLK
RST# or INIT#
FWH4
1110b ID[3:0] xxxxb x1xxb xxxxb 0101b 0101b 0101b 0101b 0000b 0000b 1000b 1111b Tri-State 0000b 1111b Tri-State
FWH[3:0]
1 Clock 1 Clock Load "5555h" in 7 Clocks 1 Clock Load "80h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
FWH4
1 Clock 1 Clock Load "5555" in 7 Clocks 1 Clock Load "AAh" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
FWH4
FWH[3:0]
CLK
RST# or INIT#
FWH4 Internal Erase

Start
FWH[3:0] 1110b ID[3:0] xxxxb x1xxb xxxxb SA[19:16] SA[15:12] xxxxb xxxxb 0000b 0000b 0011b 1111b Tri-State 0000b 1111b Tri-State
1 Clock 1 Clock Load Sector Address in 7 Clocks 1 Clock Load "30h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
SA = Sector Address

PMC Pm49FL002 / 004
FWH BLOCK ERASE WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Write Cycle IDSEL Address IMSIZE Data TAR RSYNC TAR
1110b ID[3:0] 0000b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State
FWH[3:0] xxxxb x1xxb xxxxb 0101b 0101b 0101b 0101b
CLK
RST# or INIT#
FWH4
xxxxb x1xxb 0010b 1010b 0000b 0101b 0101b Tri-State

FWH[3:0] 1110b ID[3:0] xxxxb 1010b 1010b 1111b Tri-State 0000b 1111b
CLK
RST# or INIT#
FWH4
FWH[3:0]
1 Clock 1 Clock Load "5555h" in 7 Clocks 1 Clock Load "80h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
FWH4
1 Clock 1 Clock Load "5555" in 7 Clocks 1 Clock Load "AAh" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
FWH4
FWH[3:0]
CLK
RST# or INIT#
FWH4 Internal Erase

Start
FWH[3:0] 1110b ID[3:0] xxxxb x1xxb xxxxb BA[19:16] BA[15:14]

+ xxb
xxxxb xxxxb 0000b 0000b 0101b 1111b Tri-State 0000b 1111b Tri-State
1 Clock 1 Clock Load Block Address in 7 Clocks 1 Clock Load "50h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
BA = Block Address

PMC Pm49FL002 / 004
FWH GPI REGISTER READ WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Read IDSEL RSYNC
Address IMSIZE TAR Data TAR Next Start
Cycle
FWH[3:0] 1101b ID[3:0] xxxxb x0xxb 1100b 0000b 0001b 0000b 0000b 0000b 1111b Tri-State 0000b D[3:0] D[7:4] 1111b Tri-State 1101b
1 Clock 1 Clock Load Address "xBC0100h" in 7 Clocks 1 Clock 2 Clocks 1 Clock Data Out 2 Clocks 2 Clocks 1 Clock
FWH BLOCK LOCKING REGISTER READ WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Read IDSEL RSYNC
Address IMSIZE TAR Data TAR Next Start
Cycle
FWH[3:0] 1101b ID[3:0] xxxxb x0xxb A[19:16] 0000b 0000b 0000b 0010b 0000b 1111b Tri-State 0000b D[3:0] D[7:4] 1111b Tri-State 1101b
1 Clock 1 Clock Load Address "xBx0002h" in 7 Clocks 1 Clock 2 Clocks 1 Clock Data Out 2 Clocks 2 Clocks 1 Clock

PMC Pm49FL002 / 004
LPC MODE OPERATION
LPC MODE MEMORY READ/WRITE OPERATION
In LPC mode, the Pm49FL002/004 use the 5-pin LPC

interface includes 4-bit LAD[3:0] and LFRAME# pins to
communicate with the host system. The addresses and
data are transmitted through the 4-bit LAD[3:0] bus syn-
chronized with the input clock on CLK pin during a LPC
memory cycle operation. The address or data on LAD[3:0]
bus is latched on the rising edge of the clock. The pulse
of LFRAME# signal inserted for one or more clocks
indicates the start of a LPC memory read or write cycle.
Once the LPC memory cycle is started, asserted by

LFRAME#, a START value “0000b” is expected by the
devices as a valid command cycle. Then a CYCTYPE +
DIR value (“010xb” for memory read cycle or “011xb” for
memory write cycle) is used to indicates the type of
memory cycle. Refer to Table 4 and 5 for LPC Memory
Read and Write Cycle Definition.
There are 8 clock fields in a LPC memory cycle that

gives a 32 bit memory address A31 - A0 through LAD[3:0]
with the most-significant nibble first. The memory space
of Pm49FL002/004 are mapped directly to top of 4 Gbyte
system memory space. See Table 11 for System Memory
Map.
The Pm49FL002 is mapped to the address location of

(FFFFFFFFh - FFFC0000h), the A31- A18 must be
loaded with “1” to select and activate the device during a
LPC memory read or write operation. Only A17 - A0 is
used to decode and access the 256 Kbyte memory. The
I/O7 - I/O0 data is loaded onto LAD[3:0] in 2 clock cycles
with least-significant nibble first and most-significant
nibble last.
The Pm49FL004 is mapped to the address location of

(FFFFFFFFh - FFF80000h), the A31- A19 must be
loaded with “1” to select and activate the device during a
LPC memory operation. Only A18 - A0 is used to de-
code and access the 512 Kbyte memory.

PMC Pm49FL002 / 004
LPC MODE OPERATION (CONTINUED)
Table 4: LPC Memory Read Cycle Definition
Clock Cycle Field LAD[3: 0] Direction Description

Start of Cycle: "0000b" indicates the start of a LPC memory
1 START 0000 IN
cycle.
Cycle Type: Indicates the type of a LPC memory read cycle.
CYCTYPE
CYCTYPE: Bits 3 - 2 must be "01b" for memory cycle. DIR:
2 + 010x IN
Bit 1 = "0b" indicates the type of cycle for Read. Bit 0 is
DIR
reserved.
3 - 10 AD D R YYYY IN
significant nibble last. (i.e., A31 - 28 on LAD[3:0] first, and A3
- A0 on LAD[3:0] last).
IN then Turn-Around Cycle 0: The Chipset has driven the bus to all
11 TAR0 1111
Float "1"s and then float the bus.
12 TAR1
Sync: The device indicates the least-significant nibble of data
13 SYNC 0000 OUT
byte will be ready in next clock cycle.
14 - 15 DATA YYYY OUT nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on
LAD[3:0] first, then I/O7 - I/O4 on LAD[3:0] last).
OUT then Turn-Around Cycle 0: The device has driven the bus to all
16 TAR0 1111
Float "1"s and then floats the bus.
1111 Float then Turn-Around Cycle 1: The Chipset resumes control of the bus
17 TAR1
LPC MEMORY READ CYCLE WAVEFORMS
CLK
RST# or INIT#
LFRAME#
Memory
Read
Start Cycle Address TAR SYNC Data TAR Next Start
11b +
LAD[3:0] 0000b 010Xb 1111b 1111b 1111b
A[17:16]
A[15:12] A[11:8] A[7:4] A[3:0] 1111b Tri-State 0000b D[3:0] D[7:4] 1111b Tri-State 0000b
1 Clock 1 Clock Load Address in 8 Clocks 2 Clocks 1 Clock Data Out 2 Clocks 2 Clocks 1 Clock

PMC Pm49FL002 / 004
Table 5: LPC Memory Write Cycle Definition
Clock Cycle Field LAD[3: 0] Direction Description

Start of Cycle: "0000b" to indicate the start of a LPC
1 START 0000 IN
memory cycle.
Cycle Type: Indicates the type of a LPC memory write cycle.
CYCTYPE
CYCTYPE: Bits 3 - 2 must be "01b" for memory cycle. DIR:
2 + 011x IN
Bit 1 = "1b" indicates the type of cycle for Write. Bit 0 is
DIR
reserved.
3 - 10 AD D R YYYY IN
significant nibble last. (i.e., A31 - 28 on LAD[3:0] first, and A3
- A0 on LAD[3:0] last).
11 - 12 DATA YYYY IN nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on
LAD[3:0] first, then I/O7 - I/O4 on LAD[3:0] last).
IN then Turn-Around Cycle 0: The Chipset has driven the bus to all
13 TAR0 1111
Float "1"s and then float the bus.
14 TAR1
Sync: The device indicates that it has received the data or
15 SYNC 0000 OUT
command.
OUT then Turn-Around Cycle 0: The device has driven the bus to all
16 TAR0 1111
Float "1"s and then floats the bus.
1111 Float then Turn-Around Cycle 1: The Chipset resumes control of the bus
17 TAR1
LPC MEMORY WRITE CYCLE WAVEFORMS
CLK
RST# or INIT#
LFRAME#
Memory
Write
Start Cycle Address Data TAR SYNC TAR Next Start
LAD[3:0] 0000b 011Xb 1111b 1111b 1111b A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] D[7:4] 1111b Tri-State 0000b 1111b Tri-State 0000b
1 Clock 1 Clock Load Address in 8 Clocks Load Data in 2 Clocks 2 Clocks 1 Clock 2 Clocks 1 Clock

PMC Pm49FL002 / 004
LPC BYTE PROGRAM WAVEFORMS
CLK
RST# or INIT#
LFRAME# Memory
Write
1st Start Cycle Address Data TAR Sync TAR
LAD[3:0] 0000b 011Xb 1111b 1111b 1111b 11xxb 0101b 0101b 0101b 0101b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "AAh" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
LFRAME# Memory
Write
2nd Start Cycle Address Data TAR Sync TAR
1 Clock 1 Clock Load "2AAAh" in 8 Clocks Load "55h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
LFRAME# Memory
Write
3rd Start Cycle Address Data TAR Sync TAR
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "A0h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
LFRAME# Memory
Write
4th Start Cycle Address Data TAR Sync TAR
LAD[3:0] 0000b 011Xb 1111b 1111b 1111b A[19:16] A[15:12] A[11:8] A[7:4] A[3:1] D[3:0] D[7:4] 1111b Tri-State 0000b 1111b Tri-State
1 Clock 1 Clock Load Address in 8 Clocks Load Data in 2 Clocks 2 Clocks 1 Clock 2 Clocks

PMC Pm49FL002 / 004
LPC SECTOR ERASE WAVEFORMS
CLK
RST# or INIT#
LFRAME# Memory
Write
0101b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State

LAD[3:0] 0000b 011Xb 1111b 1111b 1111b 11xxb 0101b 0101b 0101b
CLK
RST# or INIT#
LFRAME# Memory
Write
1111b 1111b 11xxb 1010b 0101b 0101b

LAD[3:0] 0000b 011Xb 1111b 0010b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State
CLK
RST# or INIT#
LFRAME# Memory
Write
0000b 011Xb 1111b 1111b 1111b 11xxb 0101b 0101b 0101b 0101b 0000b 1000b 1111b Tri-State 0000b 1111b Tri-State
LAD[3:0]
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "80h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
LFRAME# Memory
Write
1 Clock 1 Clock Load "5555" in 8 Clocks Load "AAh" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
LFRAME# Memory
Write
LAD[3:0]
CLK
RST# or INIT#
LFRAME# Memory Internal Erase

Write Start
LAD[3:0] 0000b 011Xb 1111b 1111b 1111b SA[19:16] SA[15:12] xxxxb xxxxb xxxxb 0000b 0011b 1111b Tri-State 0000b 1111b Tri-State
1 Clock 1 Clock Load Sector Address in 8 Clocks Load "30h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
SA = Sector Address

PMC Pm49FL002 / 004
LPC BLOCK ERASE WAVEFORMS
CLK
RST# or INIT#
LFRAME# Memory
Write
0000b 011Xb 0101b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State
LAD[3:0] 1111b 1111b 1111b 11xxb 0101b 0101b 0101b
CLK
RST# or INIT#
LFRAME# Memory
Write
1111b 1111b 11xxb 1010b 1010b 0101b 0101b Tri-State

LAD[3:0] 0000b 011Xb 1111b 0010b 1010b 1111b Tri-State 0000b 1111b
CLK
RST# or INIT#
LFRAME# Memory
Write
LAD[3:0]
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "80h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
LFRAME# Memory
Write
1 Clock 1 Clock Load "5555" in 8 Clocks Load "AAh" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
CLK
RST# or INIT#
LFRAME# Memory
Write
LAD[3:0]
CLK
RST# or INIT#
LFRAME# Memory Internal Erase

Write Start
LAD[3:0] 0000b 011Xb 1111b 1111b 1111b BA[19:16] BA[15:14]

+ xxb
xxxxb xxxxb xxxxb 0000b 0101b 1111b Tri-State 0000b 1111b Tri-State
1 Clock 1 Clock Load Block Address in 8 Clocks Load "50h" in 2 Clocks 2 Clocks 1 Clock 2 Clocks
BA = Block Address

PMC Pm49FL002 / 004
LPC GPI REGISTER READ WAVEFORMS
CLK
RST# or INIT#
LFRAME#
Memory
Read
Start Cycle Address TAR SYNC Data TAR Next Start
LAD[3:0] 0000b 010Xb 1111b 1111b 1011b 1100b 0000b 0001b 0000b 0000b 1111b Tri-State 0000b D[3:0] D[7:4] 1111b Tri-State 0000b
1 Clock 1 Clock Load Address "FFBC0100h" in 8 Clocks 2 Clocks 1 Clock Data Out 2 Clocks 2 Clocks 1 Clock

PMC Pm49FL002 / 004
REGISTERS
The Pm49FL002/004 have two registers include the Gen- BLOCK LOCKING REGISTERS
eral Purpose Inputs Register (GPI_REG - available in
FWH and LPC modes) and the Block Locking Register The devices support block read-lock, write-lock, and lock-
(BL_REG - available in FWH mode only). The GPI_REG down features through a set of Block Locking Registers.
can be read at FFBC0100h in the 4 Gbyte system Each memory block has an associated 8-bit read/writ-
memory map. And the BL_REG can be read through able block locking register. Only Bit 2 to Bit 0 are used
FFBx0002h where x = F - 0h. See Table 8 and 9 for the in current version and Bit 7 to Bit 3 are reserved for future
address of BL_REG. use. The default value of BL_REG is “01h” at power up.
The definition of BL_REG is listed in Table 7. The FWH
GENERAL PURPOSE INPUTS REGISTER Register Configuration Map of Pm49FL002 is shown in
Table 8. The FWH Register Configuration Map of
The Pm49FL002/004 contain an 8-bit General Purpose Pm49FL004 is shown in Table 9. Unused register will be
Inputs Register (GPI_REG) available in FWH and LPC read as 00h.
modes. Only Bit 4 to Bit 0 are used in current version
and Bit 7 to Bit 5 are reserved for future use. The
GPI_REG is a pass-through register with the value set
by GPI[4:0] pin during power-up. The GPI_REG is used
for system design purpose only, the devices do not use
this register. This register is read only and can be read
at address location FFBC0100h in the 4 GByte system
memory map through a memory read cycle. Refer to
Table 6 for General Purpose Input Register Definition.
Table 6. General Purpose Inputs Register Definition
Bit Bit Name Function 32-PLCC Pin# 32-VSOP Pin#
7:5 Reserved - -
4 GPI4 GPI_REG Bit 4 30 6

PMC Pm49FL002 / 004
REGISTERS (CONTINUED)
Table 7. Block Locking Register Definition
Bit Function
7:3 Reserved
Read-Lock
2 "1" = Prevents read operations in the block where set.
"0" = Normal operation for reads in the block where clear. Default state.
Lock-Dow n
"1" = Prevents further set or clear operations to the Write-Lock and Read-Lock bits. Lock-
Down only can be set, but not cleared. The block will remain locked-down until reset (with
1
RST# or INIT#), or until the device is power-on reset.
"0" = Normal operation for Write-Lock and Read-Lock bit altering in the block where clear.
Default state.
Write-Lock
0 "1" = Prevents program or erase operations in the block where set. Default state.
"0" = Normal operation for programming and erase in the block where clear.
Data Bit[7: 3] Bit 2 Bit 1 Bit 0 Resulting Block State
00h 00000 0 0 0 Full access.
01h 00000 0 0 1 Write locked. Default state at power-up.
02h 00000 0 1 0 Locked open (full access locked down).
03h 00000 0 1 1 Write-locked down.
04h 00000 1 0 0 Read locked.
05h 00000 1 0 1 Read and write locked.
06h 00000 1 1 0 Read-locked down.
07h 00000 1 1 1 Read-locked and write-locked down.

PMC Pm49FL002 / 004
REGISTERS (CONTINUED)
Table 8. Pm49FL002 Block Locking Register Address
Block Siz e Protected Block

Register Memory Map Address
(Kbytes) Address Range
T_BLOCK_LK 16 3C 000h - 3F F F F h F F B F 8002h
16 38000h - 3B F F F h
T_MINUS01_LK 16 34000h - 37F F F h F F B F 0002h
16 30000h - 33F F F h
16 2C 000h - 2F F F F h
T_MINUS02_LK F F B E 8002h
16 28000h - 2B F F F h
16 24000h - 27F F F h
T_MINUS03_LK F F B E 0002h
16 20000h - 23F F F h
16 1C 000h - 1F F F F h
T_MINUS04_LK F F B D 8002h
16 18000h - 1B F F F h
16 14000h - 17F F F h
T_MINUS05_LK F F B D 0002h
16 10000h - 13F F F h
16 0C 000h - 0F F F F h
T_MINUS06_LK F F B C 8002h
16 08000h - 0B F F F h
16 04000h - 07F F F h
T_MINUS07_LK F F B C 0002h
16 00000h - 03F F F h
Table 9. Pm49FL004 Block Locking Register Address
Block Siz e Protected Block

Register Memory Map Address
(Kbytes) Address Range
T_BLOCK_LK 64 70000h - 7F F F F h F F B F 0002h
T_MINUS01_LK 64 60000h - 6F F F F h F F B E 0002h
T_MINUS02_LK 64 50000h - 5F F F F h F F B D 0002h
T_MINUS03_LK 64 40000h - 4F F F F h F F B C 0002h
T_MINUS04_LK 64 30000h - 3F F F F h F F B B 0002h
T_MINUS05_LK 64 20000h - 2F F F F h F F B A 0002h
T_MINUS06_LK 64 10000h - 1F F F F h F F B 90002h
T_MINUS07_LK 64 00000h - 0F F F F h F F B 80002h

PMC Pm49FL002 / 004
A/A MUX MODE OPERATION
A/A MUX MODE READ/WRITE OPERATION are latched on the falling edge of R/C# pin. The column
addresses (internal address A21 - A11) are latched on
The Pm49FL002/004 offers a Address/Address Multi- the rising edge of R/C# pin. The Pm49FL002 uses A17
plexed (A/A Mux) mode for off-system operation, typi- - A0 internally to decode and access the 256 Kbytes
cally on an EPROM Programmer, similar to a traditional memory space. The Pm49FL004 use A18 - A0 respec-
Flash memory except the address input is multiplexed. tively.
In the A/A Mux mode, the programmer must drive the
OE# pin to low (VIL) for read or WE# pins to low for write During a read operation, the OE# signal is used to con-
operation. The devices have no Chip Enable (CE#) pin trol the output of data to the 8 I/O pins - I/O[7:0]. During
for chip selection and activation as traditional Flash a write operation, the WE# signal is used to latch the
memory. The R/C#, OE# and WE# pins are used to ac- input data from I/O[7:0]. See Table 10 for Bus Operation
tivate the device and control the power. The 11 multiplex Modes.
address pins - A[10:0] and a R/C# pin are used to load
the row and column addresses for the target memory
location. The row addresses (internal address A10 - A0)
Table 10. A/A Mux Mode Bus Operation Modes
Mode R S T# OE# WE# Address I/O
Read VIH VIL VIH X (1) DOUT
Write VIH VIH VIL X DIN
Standby VIH VIH VIH X High Z
Output Disable VIH VIH X X High Z
Reset VIL X X X High Z

A 2 - A 21 = X ,
A1 = VIL, A0 = VIL (2)
and
Manufacturer ID
Product Identification VIH VIL VIH A1 = VIH, A0 = VIH
A 2 - A 21 = X , (2)
A1 = VIL, A0 = VIH
Device ID
Notes:
1. X can be VIL or VIH.
2. Refer to Table 1 for the Manufacturer ID and Device ID of devices.

PMC Pm49FL002 / 004
SYSTEM MEMORY MAP
System Memory
(Top 4 MBytes)
FFFFFFFFh
Pm49FL002
(2 Mbits)
Pm49FL004
FFFC0000h (4 Mbits)
Pm49FL008
FFF80000h
(8 Mbits)
FFF00000h
Range for other

FWH Devices
FFC00000h
Table 11. System Memory Map

PMC Pm49FL002 / 004
MEMORY BLOCKS AND ADDRESSES
Table 12. Pm49FL002 Sector/Block Address Table
Hardw are Block Siz e Sector Siz e

Block Sector Address Range
Protection (Kbytes) (Kbytes)
Block 15 (Boot
TBL#
Block)
16 " " 3C 000h - 3F F F F h
Block 14 16 " " 38000h - 3B F F F h
Block 13 16 " " 34000h - 37F F F h
Block 12 16 " " 30000h - 33F F F h
Block 11 16 " " 2C 000h - 2F F F F h
Block 10 16 " " 28000h - 2B F F F h
Block 9 16 " " 24000h - 27F F F h
Block 8 16 " " 20000h - 23F F F h
Block 7 16 " " 1C 000h - 1F F F F h
Block 6 16 " " 18000h - 1B F F F h

WP#
Block 5 16 " " 14000h - 17F F F h
Block 4 16 " " 10000h - 13F F F h
Block 3 16 " " 0C 000h - 0F F F F h
Block 2 16 " " 08000h - 0B F F F h
Block 1 16 " " 04000h - 07F F F h
Sector 3 4 03000h - 03F F F h
Sector 2 4 02000h - 02F F F h

Block 0 16
Sector 1 4 01000h - 01F F F h
Sector 0 4 00000h - 00F F F h

PMC Pm49FL002 / 004
MEMORY BLOCKS AND ADDRESSES (CONTINUED)
Table 13. Pm49FL004 Sector/Block Address Table
Hardw are Block Siz e Sector Siz e

Block Sector Address Range
Protection (Kbytes) (Kbytes)
Block 7 (Boot
TBL#
Block)
64 " " 70000h - 7F F F F h
Block 6 64 " " 60000h - 6F F F F h
Block 5 64 " " 50000h - 5F F F F h
Block 4 64 " " 40000h - 4F F F F h
Block 3 64 " " 30000h - 3F F F F h
Block 2 64 " " 20000h - 2F F F F h

WP#
Block 1 64 " " 10000h - 1F F F F h
Sector 15 4 0F 000h - 0F F F F h
: : :
Block 0 64
Sector 1 4 01000h - 01F F F h
Sector 0 4 00000h - 00F F F h

PMC Pm49FL002 / 004
COMMAND DEFINITION
Table 14. Software Data Protection Command Definition
1st B u s 2n d B u s 3rd Bus 4th Bus 5th Bus 6th Bus

Command B us
Cycle Cycle Cycle Cycle Cylce Cycle
S eq u en ce Cycle
Addr(2) Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read 1 Addr DOUT
Chip Erase (1) 6 5555h A A h 2A A A h 55h 5555h 80h 5555h A A h 2A A A h 55h 5555h 10h
Sector Erase 6 5555h A A h 2A A A h 55h 5555h 80h 5555h A A h 2A A A h 55h SA (3) 30h
Block Erase 6 5555h A A h 2A A A h 55h 5555h 80h 5555h A A h 2A A A h 55h BA (4) 50h
Byte Program 4 5555h A A h 2A A A h 55h 5555h A0h Addr DIN
Product ID Entry 3 5555h A A h 2A A A h 55h 5555h 90h
Product ID Exit (5) 3 5555h A A h 2A A A h 55h 5555h F 0h
Product ID Exit (5) 1 X X X X h F 0h
Notes:
1. Chip erase is available in A/A Mux Mode only.
2. Address A[15:0] is used for SDP command decoding internally and A15 must be “0” in FWH/LPC and A/A
Mux modes. AMS - A16 = Don’t care where AMS is the most-significant address of Pm49FL00x.
3. SA = Sector address to be erased.
4. BA = Block address to be erased.
5. Either one of the Product ID Exit command can be used.

PMC Pm49FL002 / 004
DEVICE OPERATIONS FLOWCHARTS
AUTOMATIC PROGRAMMING
Start
Load Data AAh

to
Address 5555h
Load Data 55h

to
Address 2AAAh
Load Data A0h

Address
to
Increment Address 5555h
Load Program
Data to
Program Address
I/O7 = Data?
or
I/O6 Stop Toggle? No
Yes
Last Address?
No
Yes
Programming
Completed
Chart 1. Automatic Programming Flowchart

PMC Pm49FL002 / 004
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
AUTOMATIC ERASE
Start
Write Chip, Sector,

or Block
Erase Command
Data = FFh?
or
I/O6 Stop Toggle? Notes:
No 1. Please see Table 12 to Table 13 for
Sector/Block Address Tables.
Yes
2. Only erase one sector or one block per
erase operation.
Erasure
Completed 3. When the TBL# pin is pulled low (VIL),
the boot block will not be erased.
CHIP ERASE COMMAND SECTOR ERASE COMMAND BLOCK ERASE COMMAND
Load Data AAh Load Data AAh Load Data AAh

to to to
Address 5555h Address 5555h Address 5555h
Load Data 55h Load Data 55h Load Data 55h

to to to
Address 2AAAh Address 2AAAh Address 2AAAh

to to to
Load Data AAh Load Data AAh Load Data AAh

to to to

to to to
Address 2AAAh Address 2AAAh Address 2AAAh

to to to
(1,2,3)
Address 5555h (3) S A (1,2,3) BA
Chart 2. Automatic Erase Flowchart

PMC Pm49FL002 / 004
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
SOFTWARE PRODUCT IDENTIFICATION ENTRY SOFTWARE PRODUCT IDENTIFICATION EXIT
Load Data AAh Load Data AAh

to to
Address 5555h Address 5555h
Load Data 55h Load Data 55h Load Data F0h

to to to
Address 2AAAh Address 2AAAh Address XXXXh
or
Load Data 90h Load Data F0h Exit Product
to to Identification
Address 5555h Address 5555h Mode (3)
Enter Product Exit Product

Identification Identification
Mode (1,2) Mode (3)
Notes:
1. After entering Product Identification Mode, the Manufacturer ID and the Device ID of Pm49FL00x can be read.
2. Product Identification Exit command is required to end the Product Identification mode and return to standby mode.
3. Either Product Identification Exit command can be used, the device returns to standby mode.
Chart 3. Software Product Identification Entry/Exit Flowchart

PMC Pm49FL002 / 004
ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias -55oC to +125oC
Storage Temperature -65oC to +150oC
Standard Package 240oC 3 Seconds

Surface Mount Lead Soldering Temperature
Lead-free Package 260oC 3 Seconds
Input Voltage with Respect to Ground on All Pins (2) -0.5 V to VCC + 0.5 V
All Output Voltage with Respect to Ground -0.5 V to VCC + 0.5 V
VCC (2) -0.5 V to +6.0 V
Notes:
1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only. The functional operation of the device
or any other conditions under those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating condition for extended periods
may affected device reliability.
2. Maximum DC voltage on input or I/O pins are +6.25 V. During voltage transitioning period,
input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum
DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O
pins may undershoot GND to -2.0 V for a period of time up to 20 ns.
DC AND AC OPERATING RANGE
Part Number Pm49FL002 Pm49FL004
Operating Temperature 0oC to 70oC 0oC to 70oC
Vcc Power Supply 3.0 V - 3.6 V 3.0 V - 3.6 V

PMC Pm49FL002 / 004
DC CHARACTERISTICS
Symbol Parameter Condition Min Typ Max Units
Input Leakage Current for

II VIN = 0 V to VCC, VCC = VCC max 100 µA
IC, ID[3:0] pins
ILI Input Leakage Current VIN = 0 V to VCC, VCC = VCC max ±1 µA
ILO Output Leakage Current VI/O = 0 V to VCC, VCC = VCC max ±1 µA
Standby VCC Current FWH4 or LFRAME# = VIH,

ISB 500 µA
(FWH/LPC Mode) f = 33 MHz; VCC = VCC max
FWH4 or LFRAME# = VIL,

Ready Mode VCC Current
IRY f = 33 MHz; IOUT = 0 mA, 10 mA
(FWH/LPC Mode)
VCC = VCC max
FWH4 or LFRAME# = VIL,

VCC Active Read Current
ICC1 f = 33 MHz; IOUT = 0 mA, 2 15 mA
(FWH/LPC Mode)
VCC = VCC max
ICC2 (1) VCC Program/Erase Current 7 20 mA
VIL Input Low Voltage -0.5 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC + 0.5 V
VOL Output Low Voltage IOL = 2.0 mA, VCC = VCC min 0.1 VCC V
VOH Output High Voltage IOH = -100 µA, VCC = VCC min 0.9 VCC V
Note: 1. Characterized but not 100% tested.
AC CHARACTERISTICS
PIN IMPEDANCE (VCC = 3.3 V, f = 1 MHz, T = 25°C )
Typ Max Units Conditions
CI/O (1) I/O Pin Capacitance 12 pF VI/O = 0 V
CIN (1) Input Capacitance 12 pF VIN = 0 V
LPIN (2) Pin Inductance 20 nH
Notes:
1. These parameters are characterized but not 100% tested.
2. Refer to PCI specification.

PMC Pm49FL002 / 004
AC CHARACTERISTICS (CONTINUED)
FWH/LPC INTERFACE AC INPUT/OUTPUT CHARACTERISTICS
Symbol Parameter Condition Min Max Units
0 < VOUT < 0.3 VCC -12 VCC mA

Switching current
IOH (AC) 0.3 VCC < VOUT < 0.9 VCC -17.1 (VCC - VOUT) mA
high
0.7 VCC < VOUT < VCC Equation C (1)
(Test point) VOUT = 0.7 VCC -32 VCC mA
VCC > VOUT > 0.6 VCC 16 V C C mA
IOL (AC) Switching current low 0.6 VCC > VOUT > 0.1 VCC -17.1 (VCC - VOUT) mA
0.18 VCC > VOUT > 0 Equation D (1)
(Test point) VOUT = 0.18 VCC 38 V C C mA
ICL Low clamp current -3 < VIN < -1 -25 + (VIN + 1) / 0.015 mA
25 + (VIN - VCC - 1) /
ICH High clamp current VCC + 4 > VIN > VCC + 1 mA
0.015
slewr (2) Output rise slew rate 0.2 VCC - 0.6 VCC load 1 4 V/ns
slewf (2) Output fall slew rate 0.6 VCC - 0.2 VCC load 1 4 V/ns
Notes:
1. See PCI specification.
2. PCI specification output load is used.
FWH/LPC INTERFACE CLOCK CHARACTERISTICS
Symbol Parameter Min Max Units
tCYC Clock Cycle Time 30 ns
tHIGH Clock High Time 11 ns
tLOW Clock Low Time 11 ns
Clock Slew Rate 1 4 V/ns
INIT# or RST# Slew Rate 50 mV/ns

PMC Pm49FL002 / 004
FWH/LPC INTERFACE CLOCK WAVEFORM
tC Y C
tH I G H
tL O W 0.6 V C C
0.5 V C C
0.4 V C C p-to-p
0.4 V C C (minimum)
0.3 V C C
0.2 V C C
FWH/LPC INTERFACE MEASUREMENT CONDITION PARAMETERS
Symbol Value Units
VTH1 0.6 VCC V
VTL1 0.2 VCC V
VTEST 0.4 VCC V
VMAX1 0.4 VCC V
Input Signal Edge Rate 1 V/ns
Note: 1. The input test environment is done with 0.1 VCC of overdrive over VIH and VIL. Timing parameters must
be met with no more overdrive that this. VMAX specifies the maximum peak-to-peak waveform allowed
for measuring input timing. Production testing may use different voltage values, but must correlate
results back to these parameter.
FWH/LPC MEMORY READ/WRITE OPERATIONS CHARACTERISTICS
TCYC Clock Cycle Time 30 ns
TSU Input Set Up Time 7 ns
TH Input Hold Time 0 ns
TVAL Clock to Data Out 2 11 ns
TON Clock to Active Time (float to active delay) 2 ns
TOFF Clock to Inactive Time (active to float delay) 28 ns

PMC Pm49FL002 / 004
FWH/LPC INPUT TIMING PARAMETERS
V TH
CLK V TEST
V TL
tS U tH
FWH[3:0] or
LAD[3:0] INPUT VALID V MAX
(Valid Input Data)
FWH/LPC OUTPUT TIMING PARAMETERS
V TH
CLK V TEST
V TL
tV A L
FWH[3:0] or
LAD[3:0]
(Valid Output Data)
tO F F
FWH[3:0] or
LAD[3:0]
(Float Output Data)
tO N

PMC Pm49FL002 / 004
FWH/LPC RESET OPERATION CHARACTERISTICS
TPRST Reset Active Time to VCC Stable 1 ms
TKRST Reset Active Time to Clock Stable 100 µs
TRSTP Reset Pulse Width 100 ns
TRSTF Reset Active to Output Float Delay 50 ns

(1) Reset Inactive Time to Input Active 1 µs
TRST
Note: 1. There will be a 10 µs reset latency if a reset procedure is performed during a programming or erase
operation.
FWH/LPC RESET AC WAVEFORMS
VCC TPRST
CLK
TKRST
TRSTP
RST#/INIT# TRST
T RSTF
FWH[3:0] or
LAD[3:0]
FWH4 or
LFRAME#
A/A MUX MODE INPUT TEST MEASUREMENT CONDITION PARAMETERS
3.0 V
AC
Input 1.5 V Measurement
Level
0.0 V
A/A MUX MODE TEST LOAD CONDITION
TO TESTER
TO DUT
CL
30 pF

PMC Pm49FL002 / 004
A/A MUX MODE READ OPERATIONS CHARACTERISTICS
tRC Read Cycle Time 270 ns
tACC Address to Output Delay 120 ns
tRST RST# High to Row Address Set-up Time 1 ms
tAS R/C# Address Set-up Time 45 ns
tAH R/C# Address Hold Time 45 ns
tOE OE# to Output Delay 50 ns
tDF OE# to Output High Z 0 30 ns
tOH Output Hold from OE# or Address, whichever occured first 0 ns
tVCS VCC Set-up Time 50 µs
A/A MUX MODE READ OPERATIONS AC WAVEFORMS
RST#
tR S T tR C
ADDRESS ROW ADDRESS COLUMN ADDRESS
tA S tA H tA S tA H
R/C#
tA C C
OE#
tO E tD F
WE#
tO H
HIGH Z OUTPUT
OUTPUT VALID
tV C S
V CC

PMC Pm49FL002 / 004
A/A MUX MODE WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS
tRST RST# High to Row Address Set-up Time 1 ms
tAS R/C# Address Set-up Time 50 ns
tAH R/C# Address Hold Time 50 ns
tCWH R/C# to WE# High Time 50 ns
tOES OE# High Set-up Time 20 ns
tOEH OE# High Hold Time 20 ns
tDS Data Set-up Time 50 ns
tDH Data Hold Time 5 ns
tWP Write Pulse Width 100 ns
tWPH Write Pulse Width High 100 ns
tBP Byte Programming Time 40 µs
tEC Chip, Sector or Block Erase Cycle Time 80 ms
tVCS VCC Set-up Time 50 µs
A/A MUX MODE WRITE OPERATIONS AC WAVEFORMS
RST#
tR S T tR C
ADDRESS ROW ADDRESS COLUMN ADDRESS
tA S tA H tA S tA H
R/C#
tV C S tC W H tO E H
OE#
tO E S
WE#
tD S tD H
HIGH Z INPUT
OUTPUT DATA
V CC

PMC Pm49FL002 / 004
A/A MUX MODE BYTE PROGRAM OPERATIONS AC WAVEFORMS
4-Byte Program Command

ADDRESS
5555 2AAA 5555 BYTE ADDRESS
R/C#
tW P H
tC W H tW P tB P
WE#
OE#
tD S tD H
INPUT VALID
DATA AA 55 A0 DATA DATA
A/A MUX MODE CHIP ERASE OPERATIONS AC WAVEFORMS
6-Byte Chip Erase Command
ADDRESS
5555 2AAA 5555 5555 2AAA 5555
R/C#
tC W H tW P tW P H tE C
WE#
OE#
tD S tD H
DATA IN AA 55 80 AA 55 10

PMC Pm49FL002 / 004
A/A MUX MODE SECTOR/BLOCK ERASE OPERATIONS AC WAVEFORMS
6-Byte Block Erase Command
ADDRESS
5555 2AAA 5555 5555 2AAA SECTOR OR
BLOCK ADDRESS
R/C#
tC W H tW P tW P H tE C
WE#
OE#
tD S tD H
DATA IN AA 55 80 AA 55 30/50
A/A MUX MODE TOGGLE BIT AC WAVEFORMS
ADDRESS ROW COLUMN
R/C#
WE#
tO E H
OE#
tO E
I/O6 D D
Note: 1. Toggling OE# will operate Toggle Bit.

2. I/O6 may start and end from “1” or “0” in random.

PMC Pm49FL002 / 004
A/A MUX MODE DATA# POLLING AC WAVEFORMS
ADDRESS ROW COLUMN
R/C#
WE#
tO E H
OE#
tO E
I/O7 D D# D# D# D
Note: Toggling OE# will operate Data# Polling.
PROGRAM/ERASE PERFORMANCE
Parameter Unit Typ Max Remarks
Sector/Block Erase Time ms 50 80 From writing erase command to erase completion
Chip Erase Time ms 50 80 From writing erase command to erase completion
Excludes the time of four-cycle program command

Byte Programming Time µs 25 40
execution
Note: These parameters are characterized but not 100% tested.
RELIABILITY CHARACTERISTICS (1)
Parameter Min Typ Unit Test Method

(2)
Endurance 100,000 Cycles JEDEC Standard A117
Data Retention 20 Years JEDEC Standard A103
ESD - Human Body Model 2,000 >4,000 Volts JEDEC Standard A114
ESD - Machine Model 200 >400 Volts JEDEC Standard A115
Latch-Up 100 + ICC1 mA JEDEC Standard 78
Notes: 1. These parameters are characterized but not 100% tested.

2. Preliminary specification only and will be formalized after cycling qualification test.

PMC Pm49FL002 / 004
PACKAGE TYPE INFORMATION
32V
32-Pin Thin Small Outline Package (VSOP - 8 mm x 14 mm)( measure in millimeters)
1.05
0.95
Pin 1 I.D.
0.27
0.17
8.10
7.90
0.50
BSC
0.15
12.50 0.05
12.30
14.20
13.80
1.20
MAX 0.20
0° 0.10
0.25 5°
0.70
0.50
32J
32-Pin Plastic Leaded Chip Carrier (measured in millimeters)
12.57
12.32
11.51
11.35
0.74X30°
15.11
14.86 3.56
Pin 1 I.D. 3.18
2.41
14.05 1.93
13.89 SEATING
PLANE
13.46
12.45
0.53
0.33
0.81 1.27 Typ.

0.66
TOP VIEW SIDE VIEW

PMC Pm49FL002 / 004
REVISION HISTORY
Date Revision No. Description of Changes P ag e N o .
June, 2002 1.0 Preliminary publication All
July, 2002 1.1 Formal publication All
Revised program and erase time specification 1, 41, 44

January, 2003 1.2 Corrected typo on the part number for Block Locking
23
Register
Removed Pm49FL008 information All

November, 2003 1.3 Removed inch measurement for package type
45
information
Changed product ordering information for lead-free

1, 4, 34
package option
December, 2003 1.4
Upgraded guranteed program/erase cycles from
1, 44
50,000 to 100,000 (preliminary)

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PMC Pm49FL002 / Pm49FL004

2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory

• Single Power Supply Operation • Firmware HUB (FWH)/Low Pin Count

• Hardware Data Protection

Programmable Microelectronics Corp. 1 Issue Date: December, 2003 Rev:1.4

Programmable Microelectronics Corp. 2 Issue Date: December, 2003 Rev: 1.4

GPI0 GPI0 A6 6 28 GND GND GND

ID3 RES A3 9 25 VCC VCC VCC

ID2 RES A2 10 24 OE# INIT# INIT#

ID1 RES A1 11 23 WE# LFRAME# FWH4

FWH0 LAD0 I/O0 13 21 I/O7 RES RES

FWH LPC A/A Mux A/A Mux LPC FWH

32-PIN (8mm x 14mm) VSOP

Programmable Microelectronics Corp. 3 Issue Date: December, 2003 Rev: 1.4

PRODUCT ORDERING INFORMATION

Boot Block Location

PMC Device Number

Boot Block Temperature

Programmable Microelectronics Corp. 4 Issue Date: December, 2003 Rev: 1.4

Note: I = Input, O = Output

Programmable Microelectronics Corp. 5 Issue Date: December, 2003 Rev: 1.4

MODE SELECTION PRODUCT IDENTIFICATION

When working in-system, typically on a PC or Note- Table 1: Product Identification

Programmable Microelectronics Corp. 6 Issue Date: December, 2003 Rev: 1.4

DEVICE OPERATION (CONTINUED)

DEVICE OPERATION (CONTINUED)

SECTOR AND BLOCK ERASE I/O6 TOGGLE BIT

Programmable Microelectronics Corp. 8 Issue Date: December, 2003 Rev: 1.4

FWH MODE MEMORY READ/WRITE OPERATION FWH ABORT OPERATION

Once the FWH memory cycle is started, asserted by

There are 7 clock fields in a FWH memory cycle that

The Pm49FL002/004 are mapped within the top 4 Mbyte

Programmable Microelectronics Corp. 9 Issue Date: December, 2003 Rev: 1.4

FWH MODE OPERATION (CONTINUED)

Table 2: FWH Memory Read Cycle Definition

Clock Cycle Field FWH[3: 0] Direction Description

FWH MEMORY READ CYCLE WAVEFORMS

Programmable Microelectronics Corp. 10 Issue Date: December, 2003 Rev: 1.4

FWH MODE OPERATION (CONTINUED)

Table 3: FWH Memory Write Cycle Definition

Clock Cycle Field FWH[3: 0] Direction Description

FWH MEMORY WRITE CYCLE WAVEFORMS

Programmable Microelectronics Corp. 11 Issue Date: December, 2003 Rev: 1.4

FWH MODE OPERATION (CONTINUED)

FWH BYTE PROGRAM WAVEFORMS

Programmable Microelectronics Corp. 12 Issue Date: December, 2003 Rev: 1.4

xxxxb x1xxb 0010b 1010b 0000b 0101b 0101b Tri-State

FWH4 Internal Erase

Programmable Microelectronics Corp. 13 Issue Date: December, 2003 Rev: 1.4

FWH BLOCK ERASE WAVEFORMS

xxxxb x1xxb 0010b 1010b 0000b 0101b 0101b Tri-State

FWH4 Internal Erase

FWH[3:0] 1110b ID[3:0] xxxxb x1xxb xxxxb BA[19:16] BA[15:14]

Programmable Microelectronics Corp. 14 Issue Date: December, 2003 Rev: 1.4

FWH GPI REGISTER READ WAVEFORMS

FWH BLOCK LOCKING REGISTER READ WAVEFORMS

Programmable Microelectronics Corp. 15 Issue Date: December, 2003 Rev: 1.4

LPC MODE OPERATION

LPC MODE MEMORY READ/WRITE OPERATION

In LPC mode, the Pm49FL002/004 use the 5-pin LPC