SST 28Sf040 5.0V-Only 4 Megabit Superflash Eeprom: Data Sheet

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Data Sheet
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
June 1997
©1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
This specification is subject to change without notice.
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Features:
Single 5.0-Volt Read and Write Operations Latched Address and Data
CMOS SuperFlash EEPROM Technology Hardware and Software Data Protection
Endurance: 100,000 Cycles (typical) 7-Read-Cycle-Sequence Software Data
Greater than 100 years Data Retention Protection
Memory Organization: 512K x 8 End of Write Detection
Sector Erase Capability: 256 bytes per Sector Toggle Bit
Low Power Consumption: Data# Polling
Active Current: 15 mA (typical) TTL I/O Compatibility
Standby Current: 5 µA (typical) Packages Available
Fast Sector Erase/Byte Program Operation 40-Pin TSOP (10 mm x 20 mm)
Byte Program Time: 35 µs (typical) 32-Pin TSOP (8 mm x 20 mm)
Sector Erase Time: 2 ms (typical) 32-Pin PLCC
Complete Memory Rewrite: 20 sec (typical) 32-Pin PDIP
Fast Access Time: 120, 150, and 200 ns
Product Description diskettes or EPROM approaches. EEPROM tech-

nology makes possible convenient and economical
The 28SF040 is a 512K x 8 bit CMOS sector erase, updating of codes and control programs on-line. The
byte program EEPROM. The 28SF040 is manufac- 28SF040 improves flexibility, while lowering the cost
tured using SST’s proprietary, high performance of program and configuration storage application.
CMOS SuperFlash EEPROM Technology. The split
gate cell design and thick oxide tunneling injector Figure 1 shows the functional blocks of the
attain better reliability and manufacturability com- 28SF040. Figures 2A, 2B, and 3 show the pin as-
pared with alternative approaches. The 28SF040 signments for the 40 pin TSOP, 32 pin TSOP, 32 pin
erases and programs with a 5.0-volt only power PDIP, and 32 pin PLCC packages. Pin description
supply. The 28SF040 conforms to JEDEC standard and operation modes are described in Tables 1
pinouts for byte wide memories and is compatible through 4.
with existing industry standard EPROM, flash
Device Operation
EPROM and EEPROM pinouts.
Commands are used to initiate the memory opera-
Featuring high performance programming, the
tion functions of the device. Commands are written
28SF040 typically byte programs in 35 µs. The
to the device using standard microprocessor write
28SF040 typically sector erases in 2 ms. Both pro-
sequences. A command is written by asserting WE#
gram and erase times can be optimized using
low while keeping CE# low. The address bus is
interface features such as Toggle bit or Data# Polling
latched on the falling edge of WE# or CE#, which-
to indicate the completion of the write cycle. To pro-
ever occurs last. The data bus is latched on the
tect against an inadvertent write, the 28SF040 has
rising edge of WE# or CE#, whichever occurs first.
on chip hardware and software data protection
Note, during the software data protection sequence
schemes. Designed, manufactured, and tested for a
the address are latched on the rising edge of OE# or
wide spectrum of applications, the 28SF040 is of-
CE#, whichever occurs first.
fered with a guaranteed sector endurance of 104 and
103 cycles. Data retention is rated greater than 100 Command Definitions
years.
Table 3 contains a command list and a brief sum-
The 28SF040 is best suited for applications that er- mary of the commands. The following is a detailed
quire reprogrammable nonvolatile mass storage of description of the operations initiated by each com-
program, configuration, or data memory. For all mand.
system applications, the 28SF040 significantly m-i
proves performance and reliability, while lowering
power consumption when compared with floppy
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Sector_Erase Operation erase command can be reissued as many times as

necessary to complete the erase operation. The
The Sector_Erase operation erases all bytes within a 28SF040 cannot be “overerased”. (See Figure 8)
sector and is initiated by a setup command and an
execute command. A sector contains 256 bytes. Byte_Program Operation
This sector erasability enhances the flexibility and
The Byte_Program operation is initiated by writing
usefulness of the 28SF040, since most applications
the setup command (10H). Once the program setup
only need to change a small number of bytes or
is performed, programming is executed by the next
sectors, not the entire chip.
WE# pulse. See Figures 5 and 6 for timing wave-
The setup command is performed by writing 20H to forms. The address bus is latched on the falling edge
the device. The execute command is performed by of WE# or CE#, whichever occurs last. The data bus
writing D0H to the device. The erase operation be- is latched on the rising edge of WE# or CE#, which-
gins with the rising edge of the WE# or CE#, ever occurs first, and begins the program operation.
whichever occurs first and terminates automatically The program operation is terminated automatically
by using an internal timer. The end of Erase can be by an internal timer. See Figure 16 for the program-
determined using either Data# Polling, Toggle Bit, or ming flowchart.
Successive Reads detection methods. See Figure 9
The two-step sequence of a setup command fol-
for timing waveforms.
lowed by an execute command ensures that only the
The two-step sequence of setup command followed addressed byte is programmed and other bytes are
by an execute command ensures that only memory not inadvertently programmed.
contents within the addressed sector are erased and
The Byte_Program Flowchart Description
other sectors are not inadvertently erased.
Programming data into the 28SF040 is accom-
Sector_Erase Flowchart Description
plished by following the Byte_Program flowchart
Fast and reliable erasing of the memory contents shown in Figure 16. The Byte_Program command
within a sector is accomplished by following the sets up the byte for programming. The address bus
sector erase flowchart as shown in Figure 18. The is latched on the falling edge of WE# or CE#, which-
entire procedure consists of the execution of two ever occurs last. The data bus is latched on the
commands. The Sector_Erase operation will termi- rising edge of WE# or CE#, whichever occurs first
nate after a maximum of 4 ms. A Reset command and begins the program operation. The end of pro-
can be executed to terminate the erase operation; gram can be detected using either the Data# Polling,
however, if the erase operation is terminated prior to Toggle bit, or Successive reads.
the 4 ms time-out, the sector may not be fully
Reset Operation
erased. An erase command can be reissued as
many times as necessary to complete the erase op- The Reset command is provided as a means to
eration. The 28SF040 cannot be “overerased”. safely abort the erase or program command se-
quences. Following either setup commands (erase
Chip_Erase Operation
or program) with a write of FFH will safely abort the
The Chip_Erase operation is initiated by a setup operation. Memory contents will not be altered. After
command (30H) and an execute command (30H). the Reset command, the device returns to the read
The Chip_Erase operation allows the entire array of mode. The Reset command does not enable soft-
the 28SF040 to erase in one operation, as opposed ware data protection. See Figure 7 for timing
to 2048 sector erase operations. Using the waveforms.
Chip_Erase operation will minimize the time to e r-
write the entire memory array. The Chip_Erase
operation will terminate after a maximum of 20 ms. A
Reset command can be executed to terminate the
erase operation; however, if the erase operation is
terminated prior to the 20 ms time-out, the Chip may
not be completely erased. If an erase error occurs an
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Read Software Data Protection (SDP)

The Read operation is initiated by setting CE#, and The 28SF040 has software methods to further pre-
OE# to logic low and setting WE# to logic high (See vent inadvertent writes. In order to perform an erase
Table 2). See Figure 4 for read memory timing or program operation, a two-step command se-
waveform. The read operation from the host e r- quence consisting of a set-up command followed by
trieves data from the array. The device remains an execute command avoids inadvertent erasing and
enabled for read until another operation mode is ac- programming of the device.
cessed. During initial power-up, the device is in the
The 28SF040 will default to software data protection
read mode and is software data protected. The de-
after power up. A sequence of seven consecutive
vice must be unprotected to execute a write
reads at specific addresses will unprotect the device
command.
The address sequence is 1823H, 1820H, 1822H,
The read operation of the 28SF040 is controlled by 0418H, 041BH, 0419H, 041AH. The address bus is
OE# and CE# at logic low. When CE # is high, the latched on the rising edge of OE# or CE#, whichever
chip is deselected and only standby power will be occurs first. A similar seven read sequence of
consumed. OE# is the output control and is used to 1823H, 1820H, 1822H, 0418H, 041BH, 0419H,
gate data from the output pins. The data bus is in 040AH will protect the device. Also refer to Figures
high impedance state when CE# and OE# are high. 10 and 11 for the 7 read cycle sequence Software
Data Protection. The I/O pins can be in any state
Read_ID operation
(i.e., high, low, or tristate).
The Read_ID operation is initiated by writing a single
Write Operation Status Detection
command (90H). A read of address 0000H will out-
put the manufacturer’s code (BFH). A read of The 28SF040 provides three means to detect the
address 0001H will output the device code (04H). completion of a write cycle, in order to optimize the
Any other valid command will terminate this opera- system write cycle time. The end of a write cycle
tion. (erase or program) can be detected by three means:
1) monitoring the Data# Polling bit; 2) monitoring the
Data Protection
Toggle bit; or 3) by two successive read of the same
In order to protect the integrity of nonvolatile data data. These three detection mechanisms are de-
storage, the 28SF040 provides both hardware and scribed below.
software features to prevent inadvertent writes to the The actual completion of the nonvolatile write is
device, for example, during system power-up or asynchronous with the system; therefore, either a
power-down. Such provisions are described below. Data# Polling or Toggle Bit read may be simultane-
Hardware Data Protection ous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous
The 28SF040 is designed with hardware features to result, i.e., valid data may appear to conflict with the
prevent inadvertent writes. This is done in the follow- DQ used. In order to prevent spurious rejection, if an
ing ways: erroneous result occurs, the software routine should
1. Write Inhibit Mode: OE# low, CE#, or WE# high include a loop to read the accessed location an addi-
will inhibit the write operation. tional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the
2. Noise/Glitch Protection: A WE# pulse width of rejection is valid.
less than 15 ns will not initiate a write cycle.
Data# Polling (DQ 7)
3. VCC Power Up/Down Detection: The write op-
eration is inhibited when VCC is less than 2.5V. The 28SF040 features Data# Polling to indicate the
write operation status. During a write operation, any
4. After power-up the device is in the read mode attempt to read the last byte loaded during the byte-
and the device is in the software data protect load cycle will receive the complement of the true
state. data on DQ7. Once the write cycle is completed, DQ7
will show true data. The device is then ready for the
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
next operation. See Figure 12 for Data Polling timing Product Identification
waveforms. In order for Data# Polling to function cor-
The Product Identification mode identifies the device
rectly , the byte being polled must be erased prior to
as 28SF040 and the manufacturer as SST. This
programming.
mode may be accessed by hardware and software
Toggle Bit ( DQ 6) operations. The hardware operation is typically used
by an external programmer to identify the correct al-
An alternative means for determining the write op-
gorithm for the 28SF040. Users may wish to use the
eration status is by monitoring the Toggle Bit, DQ6.
software operation to identify the device (i.e., using
During a write operation, consecutive attempts to
the device code). For details see Table 2 for the
read data from the device will result in DQ6 toggling
hardware operation and Figure 19 for the software
between logic 0 (low) and logic 1 (high). When the
operation. The manufacturer and device codes are
write cycle is completed, the toggling will stop. The
the same for both operations.
device is then ready for the next operation. See Fig-
ure 13 for Toggle Bit timing waveforms. Product Identification Table
Successive Reads Byte Data
An Alternative means for determining an end of a
Manufacturer Code 0000 H BF H
write cycle is by reading the same address for two
consecutive data matches. Device Code 0001 H 04 H
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
4,194,304 Bit
X-Decoder EEPROM
Cell Array
A18-A0 Address buffer & Latches

Y-Decoder
CEH#
OE# Control Logic I/O Buffers and Data Latches
WE#
DQ7 - DQ0
Figure 1: Functional Block Diagram of SST 28SF040
Pin #1 indicator
N/C 1 40 N/C
N/C 2 39 N/C
A11 3 38 OE#
A9 4 37 A10
A8 5 Standard Pinout 36 CE#
A13 6 35 DQ7
A14 7 Top View 34 DQ6
A17 8 33 DQ5
WE# 9 32 DQ4
VCC 10 31 DQ3
A18 11 30 VSS
A16 12 Die up 29 DQ2
A15 13 28 DQ1
A12 14 27 DQ0
A7 15 26 A0
A6 16 25 A1
A5 17 24 A2
A4 18 23 A3
N/C 19 22 N/C
N/C 20 21 N/C
Figure 2A: Standard Pin Assignments for 40-pin TSOP Pac kages
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
A11 1 32 OE#
A9 2 31 A10
A8 3 30 CE#
A13 4 29 DQ7
A14 5 Standard Pinout 28 DQ6
A17 6 27 DQ5
WE# 7 Top View 26 DQ4
VCC 8 25 DQ3
A18 9 24 VSS
A16 10 23 DQ2
A15 11 22 DQ1
A12 12 Die up 21 DQ0
A7 13 20 A0
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3
Figure 2B: Standard Pin Assignments for 32-pin TSOP Packages
A18 1 32 Vcc A15 A18 WE#

A16 2 A12 A16 Vcc A17
31 WE#
A15 3 30 A17
A12 4 29 A14 4 3 2 1 32 31 30
A7 5 A7 5 29 A14
28 A13
A6 6 27 A8 A6 6 28 A13
A5 7 26 A9 A5 7 27 A8
32-Pin PDIP
A4 8 25 A11 26 A9
A4 8
A3 9 Top View 24 OE#
A3 9 32-Lead PLCC 25 A11
A2 10 23 A10
A2 10 Top View 24 OE#
A1 11 22 CE#
A0 A1 11 23 A10
12 21 DQ7
DQ0 13 20 DQ6 A0 12 22 CE#
DQ1 14 19 DQ5 DQ0 13 21 DQ7
DQ2 15 18 DQ4 14 15 16 17 18 19 20
Vss 16 17 DQ3
DQ1 Vss DQ4 DQ6
DQ2 DQ3 DQ5
Figure 3: Pin Assignments for 32-pin Plastic DIPs and 32-pin PLCCs
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Table 1: Pin Description

Symbol Pin Name Functions
A18-A8 Row Address Inputs To provide memory addresses. Row addresses define a sector.
A7-A0 Column Address Inputs Selects the byte within the sector.
DQ7-DQ0 Data Input/Output To output data during read cycles and receive input data during
write cycles. Data is internally latched during a write cycle. The ou
t-
puts are in tri-state when OE#, CE # is high.
CE# Chip Enable To activate the device when CE # is low.(1)
OE# Output Enable To gate the data output buffers.(1)
WE# Write Enable To control the write operations.(1)
Vcc Power Supply To provide 5-volt supply (± 10%)
Vss Ground
(1)
Note: This pin is considered an input for the purposes of the DC Operation Characteristics Table.
Table 2: Operation Modes Selection

Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Byte Program VIL VIH VIL DIN AIN, See Table 3
Sector Erase VIL VIH VIL DIN AIN, See Table 3
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
Write Inhibit X X VIH High Z/ DOUT X
Software Chip Erase VIL VIH VIL DIN See Table 3
Product Identification
Hardware Mode VIL VIL VIH Manufacturer A18-A1=VIL, A9=VH, A0=V IL
Code (BF)
Device Code (04) A18-A1=VIL, A9=VH, A0=V IH
Software Mode VIL VIH VIL See Table 3
SDP Enable & Disable Mode VIL VIH VIL See Table 3
Reset VIL VIH VIL See Table 3
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Table 3: Software Command Summary

Command Su mmary Required Setup Command Cycle Execute Command C ycle SDP (5)
Cycle(s) Type (1) Addr (2,3) Data (4) Type (1) Addr (2,3) Data (4)
Sector_Erase 2 W X 20H W SA D0H N
Byte_Program 2 W X 10H W PA PD N
Chip_Erase 2 W X 30H W X 30H N
Reset 1 W X FFH Y
Read_ID 3 W X 90H R (8) (8) Y
Software_Data_Protect 7 R (6)
Software_Data_Unprotect 7 R (7)
Notes:
1. Type definition: W = Write, R = Read, X= don’t care
2. Addr (Address) definition: SA = Sector Address = A18 - A8, sector size = 256 bytes; A7- A0 = X for this
command.
3. Addr (Address) definition: PA = Program Address = A18 - A0.
4. Data definition: PD = Program Data, H = number in hex.
5. SDP = Software Data Protect mode using 7 Read CycleSequence.
a) Y = the operation can be executed with protection enabled
b) N = the operation cannot be executed with protection enabled
6. Refer to Figure 11 for the 7 Read Cycle sequence for Software_Data_Protect.
7. Refer to Figure 10 for the 7 Read Cycle sequence for Software_Data_Unprotect.
8. Address 0000H retrieves the manufacturer’ code of BFH and address 0001H retrieves the device code of
04H.
Table 4: Memory Array Detail

Sector Select Byte Select
A18 - A8 A7 - A0
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional oper a-
tion of the device at these conditions or conditions greater than those defined in the operational sections of this
data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias ........................................................................ -55°C to +125°C
Storage Temperature ............................................................................. -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ........................................ -0.5V to VCC+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential ................... -1.0V to VCC+ 1.0V
Voltage on A9 Pin to Ground Potential .................................................... -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) ................................. 1.0W
Through Soldering Temperature (10 Seconds)......................................... 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) ...................... 240°C
Output Short Circuit Current(1) ................................................................. 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 5: Operating Range Table 6: AC Conditions of Test
Range Ambient Temp VCC Input Rise/Fall Time...............10 ns
Commercial 0 °C to +70 °C 5V±10% Output Load...........................1 TTL Gate and CL = 100 pF
Industrial -40 °C to +85 °C 5V±10% See Figures 14 and 15
Table 7: DC Operating Characteristics

Symbol Parameter Limits Units Test Conditions
Min Max
ICC Power Supply Current CE# = OE# =VIL, WE# =VIH,
all I/Os open
Read 25 mA Address input = VIL/VIH, at f=1/TRC Min.
VCC = VCC Max
Program and Erase 40 mA CE# =WE# =VIL, OE# =VIH
VCC =VCC Max.
ISB1 Standby VCC Current (TTL in- 3 mA CE# =OE# =WE# = VIH, VCC=VCC Max
put)
ISB2 Standby VCC Current 20 µA CE# = OE# = WE# = VCC -0.3V,
(CMOS input) VCC=VCC Max
ILI Input Leakage Current 1 µA VIN = GND to VCC, VCC = VCC Max.
ILO Output Leakage Current 10 µA VOUT =GND to VCC, VCC = VCC Max.
VIL Input Low Voltage 0.8 V VCC = VCC Max.
VIH Input High Voltage 2.0 V VCC = VCC Max.
VOL Output Low Voltage 0.4 V IOL= 2.1 mA, VCC = VCC Min.
VOH Output High Voltage 2.4 V IOH = -400 µA, VCC = VCC Min.
VH Supervoltage for A9 11.6 12.4 V CE#=OE#=VIL,WE#=VIH
IH Supervoltage Current for A9 200 µA CE#=OE#=VIL,WE#=VIH, A9 = VH Max.
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Table 8: Power-up Timings

Symbol Parameter Maximum Units
(1)
TPU-READ Power-up to Read Operation 10 ms
TPU-WRITE (1) Power-up to Write Operation 10 ms
Table 9: Capacitance (Ta = 25 °C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum
(1)
CI/O I/O Pin Capacitance VI/O = 0V 12 pF
CIN(1) Input Capacitance VIN = 0v 6 pF
(1)
Note: This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 10: Reliability Characteristics

Symbol Parameter Minimum Units Test Method
Specification
NEND Endurance 1,000 & 10,000(2) Cycles MIL-STD-883, Method 1033
TDR(1) Data Retention 100 Years MIL-STD-883, Method 1008
VZAP_HBM (1) ESD Susceptibility 1000 Volts MIL-STD-883, Method 3015
Human Body Model
VZAP_MM (1) ESD Susceptibility 200 Volts JEDEC Standard A115
Machine Model
(1)
ILTH Latch Up 100 mA JEDEC Standard 17
(1)
Note: This parameter is measured only for initial qualification and after a design or process change that
(2)
See Ordering Information for desired type.
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
AC Characteristics
Table 11: Read Cycle Timing Parameters
IEEE Industry 28SF040-120 28SF040-150 28SF040-200
Symbol Symbol Parameter Min Max Min Max Min Max Units
tAVAV TRC Read Cycle Time 120 150 200 ns
tAVQV TAA Address Access Time 120 150 200 ns
tELQV TCE Chip Enable Access Time 120 150 200 ns
tGLQV TOE Output Enable Access Time 50 70 75 ns
tEHQZ TCLZ(1) CE# Low to Active Output 0 0 0 ns
(1)
tGHQZ TOLZ OE# Low to Active Output 0 0 0 ns
(1)
tELQX TCHZ CE# High to High-Z Output 30 40 40 ns
tGLQX TOHZ (1) OE# High to High-Z Output 30 40 40 ns
(1)
tAXQX TOH Output Hold from Address 0 0 0 ns
Change
Table 12: Erase/Program Cycle Timing Parameters

IEEE Industry
Symbol Symbol Parameter Min Max Units
tAVA TBP Byte Program Cycle Time 40 µs
tWLWH TWP Write Pulse Width (WE#) 100 ns
tAVWL TAS Address Setup Time 10 ns
tWLAX TAH Address Hold Time 50 ns
tELWL TCS CE# Setup Time 0 ns
tWHEX TCH CE# Hold Time 0 ns
tGHWL TOES OE# High Setup Time 10 ns
tWGL TOEH OE# High Hold Time 10 ns
tWLEH TCP Write Pulse Width (CE#) 100 ns
tDVWH TDS Data Setup Time 50 ns
tWHDX TDH Data Hold Time 10 ns
tWHWL2 TSE Sector Erase Cycle Time 4 ms
TRST(1) Reset Command Recovery Time 4 µs
tWHWL3 TSCE Software Chip_Erase Cycle Time 20 ms
tEHEL TCPH CE# High Pulse Width 50 ns
tWHWL1 TWPH WE# High Pulse Width 50 ns
TPCP (1) Protect Chip Enable Pulse Width 10 ns
(1)
TPCH Protect Chip Enable High Time 10 ns
TPAS(1) Protect Address Setup Time 0 ns
TPAH (1) Protect Address Hold Time 50 ns
(1)
Note: This parameter is measured only for initial qualification and after the design or process change that
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Figure 4: Read Cycle Timing Diagram
Figure 5: WE# Controlled Byte Program Timing Diagram
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Figure 6: CE# Controlled Byte Program Timing Diagram
Figure 7: Reset Command Timing Dia gram
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Figure 8: Chip_Erase Timing Diagram
Figure 9: Sector Erase Timing Diagram
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Figure 10: Software Data Unprotect Timing Diagram
Figure 11: Software Data Protect Timing Diagram
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Figure 12: Data# Polling Timing Diagram
Figure 13: Toggle Bit Timing Diagram
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
2.4
2.0 2.0
INPUT REFERENCE POINTS OUTPUT
0.8 0.8
0.4
AC test inputs are driven at VOH (2.4 VTTL ) for a logic “1” and VOL (0.4 VTTL ) for a logic “0”. Measure-
ment reference points for inputs and outputs are VIH (2.0 VTTL ) and VIL (0.8 VTTL ). Inputs rise and fall
times (10% ↔ 90%) are <10 ns.
Figure 14: AC Input/Output Reference Wav eform
TEST LOAD EXAMPLE
VCC
TO TESTER
RL HIGH
TO DUT
CL RL LOW
Figure 15: Test Load Example
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Figure 16: Byte Program Flowchart
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Internal Timer Toggle Bit Data # Polling
Byte Program/ Byte Program/

Sector Erase Byte Program
Sector Erase
Initiated Initiated
Initiated
Wait TBP or
TSE Read byte Read DQ7
Write
Completed Read same No
byte Is DQ7 =
true data?
Yes
No Does DQ6 Write

match ? Completed
Yes
Write
Completed
Figure 17: Write Wait Options
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Figure 18: Sector_Erase Flowchart
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Execute Read_ID
Command (90H)
To enter ID mode
Read Address 0000H

MFG’s Code =
SST (BF)
Read Address 0001H

Device Code =
28SF040 (04)
Execute Reset
Command (FFH)
to exit from mode
Figure 19: Software Product ID Flow
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Product Ordering Information
Device Speed Suffix1 Suffix2
SST28SF040 - XXX - XX - XX
Package Modifier
I =40 leads
H = 32 leads
Numeric = Die modifier
Package Type
P = PDIP
N = PLCC
E = TSOP (die up)
U = Unencapsulated die
Operating Temperature
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
Minimum Endurance
3 = 1000 cycles
4 = 10,000 cycles
Read Access Speed

200 = 200 ns
150 = 150 ns
120 = 120 ns
SST 28SF040
5.0V-only 4 Megabit
SuperFlash EEPROM
Valid combinations
SST28SF040-120-4C- EH SST28SF040-120-4C- EI SST28SF040-120-4C- NH

SST28SF040-120-4C- PH
SST28SF040-150-4C- PH
SST28SF040-200-4C- PH

SST28SF040-120-3C- PH
SST28SF040-150-3C- PH
SST28SF040-200-3C- PH
SST28SF040-150-4I- EH SST28SF040-150-4I- EI SST28SF040-150-4I- NH
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales represent a-
tive to confirm availability of valid combinations and to determine availability of new combin ations.

SST 28Sf040 5.0V-Only 4 Megabit Superflash Eeprom: Data Sheet

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SST 28Sf040 5.0V-Only 4 Megabit Superflash Eeprom: Data Sheet

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查询SST 28SF040B供应商 捷多邦，专业PCB打样工厂，24小时加急出货

Product Description diskettes or EPROM approaches. EEPROM tech-

Sector_Erase Operation erase command can be reissued as many times as

Read Software Data Protection (SDP)

A18-A0 Address buffer & Latches

Figure 1: Functional Block Diagram of SST 28SF040

Figure 2B: Standard Pin Assignments for 32-pin TSOP Packages

A18 1 32 Vcc A15 A18 WE#

Table 1: Pin Description

Table 2: Operation Modes Selection

Table 3: Software Command Summary

Table 4: Memory Array Detail

Table 7: DC Operating Characteristics

Table 8: Power-up Timings

Table 9: Capacitance (Ta = 25 °C, f=1 Mhz, other pins open)

Table 10: Reliability Characteristics

Table 12: Erase/Program Cycle Timing Parameters

Figure 4: Read Cycle Timing Diagram

Figure 5: WE# Controlled Byte Program Timing Diagram

Figure 6: CE# Controlled Byte Program Timing Diagram

Figure 7: Reset Command Timing Dia gram

Figure 8: Chip_Erase Timing Diagram

Figure 9: Sector Erase Timing Diagram

Figure 10: Software Data Unprotect Timing Diagram

Figure 11: Software Data Protect Timing Diagram

Figure 12: Data# Polling Timing Diagram

Figure 13: Toggle Bit Timing Diagram

Figure 14: AC Input/Output Reference Wav eform

TEST LOAD EXAMPLE

Figure 15: Test Load Example

Figure 16: Byte Program Flowchart

Internal Timer Toggle Bit Data # Polling

Byte Program/ Byte Program/

No Does DQ6 Write

Figure 17: Write Wait Options

Figure 18: Sector_Erase Flowchart

Read Address 0000H

Read Address 0001H

Figure 19: Software Product ID Flow

Product Ordering Information

Device Speed Suffix1 Suffix2

Read Access Speed

SST28SF040-120-4C- EH SST28SF040-120-4C- EI SST28SF040-120-4C- NH

SST28SF040-120-3C- EH SST28SF040-120-3C- EI SST28SF040-120-3C- NH

SST28SF040-150-4I- EH SST28SF040-150-4I- EI SST28SF040-150-4I- NH

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查询SST 28SF040B供应商捷多邦，专业PCB打样工厂，24小时加急出货