SST26VF080A: 2.5V/3.0V 8-Mbit Serial Quad I/O™ (SQI™) Flash Memory

SST26VF080A
2.5V/3.0V 8-Mbit Serial Quad I/O™ (SQI™) Flash Memory

Features • Security ID:
- One-Time-Programmable (OTP) 2-Kbyte
• Single Voltage Read and Write Operations:
Secure ID:
- 2.7V-3.6V or 2.3V-3.6V
- 128-bit unique, factory preprogrammed
• Serial Interface Architecture: identifier
- Nibble-wide multiplexed I/O’s with SPI-like - User-programmable area
serial command structure:
• Temperature Range:
- Mode 0 and Mode 3
- Industrial: -40°C to +85°C
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
- Extended: -40°C to +125°C
• High-Speed Clock Frequency:
• Automotive AEC-Q100 Qualified
- 2.7V-3.6V: 104 MHz maximum (Industrial)
• Packages Available:
- 2.3V-3.6V: 80 MHz maximum (Industrial and
- 8-contact WDFN (6 mm x 5 mm)
Extended)
- 8-lead SOIC (3.90 mm)
• Burst Modes:
• All Devices are RoHS Compliant
- Continuous linear burst
- 8/16/32/64-byte linear burst with wrap-around
Product Description
• Superior Reliability:
- Endurance: 100,000 cycles (minimum) The Serial Quad I/O™ (SQI™) family of Flash memory
devices features a six-wire, 4-bit I/O interface that
- Greater than 100 years data retention
allows for low-power, high-performance operation in a
• Low-Power Consumption: low pin count package. SST26VF080A also supports
- Active Read current: 15 mA (typical @ full command-set compatibility to traditional Serial
104 MHz) Peripheral Interface (SPI) protocol. System designs
- Standby Current: 15 µA (typical) using SQI Flash devices occupy less board space and
• Fast Erase Time: ultimately lower system costs.
- Sector/Block Erase: 20 ms (typical), 25 ms All members of the 26 Series, SQI family are manufac-
(maximum) tured with proprietary, high-performance CMOS Super-
- Chip Erase: 40 ms (typical), 50 ms Flash® technology. The split-gate cell design and
(maximum) thick-oxide tunneling injector attain better reliability and
• Page-Program: manufacturability compared with alternate approaches.
- 256 bytes per page in x1 or x4 mode SST26VF080A significantly improves performance and
• End-of-Write Detection: reliability, while lowering power consumption. These
devices write (Program or Erase) with a single-power
- Software polling the BUSY bit in STATUS
supply of 2.3V-3.6V. The total energy consumed is a
register
function of the applied voltage, current and time of
• Flexible Erase Capability: application. Since for any given voltage range, the
- Uniform 4-Kbyte sectors SuperFlash technology uses less current to program
- Uniform 32-Kbyte overlay blocks and has a shorter erase time, the total energy
- Uniform 64-Kbyte overlay blocks consumed during any erase or program operation is
less than alternative Flash memory technologies.
• Write-Suspend:
- Suspend program or erase operation to See Figure 2-1 for pin assignments.
access another block/sector
• Software Reset (RST) mode
• Software Write Protection:
- Write protection through Block Protection bits
in STATUS register
 2019-2020 Microchip Technology Inc. DS20006203B-page 1

SST26VF080A
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SST26VF080A
1.0 BLOCK DIAGRAM
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM
OTP
SuperFlash®
X - Decoder Memory
Address
Buffers
and
Latches
Y - Decoder
Page Buffer,
Control Logic I/O Buffers
and
Data Latches
Serial Interface
WP# HOLD# SCK CE# SIO [3:0] RESET#

SST26VF080A
2.0 PIN DESCRIPTION
FIGURE 2-1: PIN DESCRIPTIONS
PIN ASSIGNMENT FOR 8-LEAD SOIC PIN ASSIGNMENT FOR 8-CONTACT WDFN
CE# 1 8 VDD CE# 1 8 VDD
SO/SIO1 2 7 RESET#/HOLD#/SIO3 SO/SIO1 2 7 RESET#/HOLD#/SIO3

Top View Top View
WP#/SIO2 3 6 SCK WP#/SIO2 3 6 SCK
Vss 4 5 SI/SIO0 Vss 4 5 SI/SIO0
TABLE 2-1: PIN DESCRIPTION

Symbol Pin Name Functions
SCK Serial Clock Provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SIO[3:0] Serial Data Transfer commands, addresses, or data serially into the device or data out of
Input/Output the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
SI Serial Data Input Transfer commands, addresses or data serially into the device. Inputs are
for SPI mode latched on the rising edge of the serial clock. SI is the default state after a
Power-on Reset or hardware Reset.
SO Serial Data Output Transfer data serially out of the device. Data is shifted out on the falling edge of
for SPI mode the serial clock. SO is the default state after a Power-on Reset or hardware
Reset.
CE# Chip Enable The device is enabled by a high-to-low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of write operations,
for the command/data input sequence.
WP# Write-Protect The WP# pin is used in conjunction with the WPEN and IOC bits in the Configu-
ration register to prohibit write operations to the Block Protection register. This
pin only works in SPI, single-bit and dual-bit Read mode.
HOLD# Hold Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read mode
and must be tied high when not in use.
RESET# Reset Reset the operation and internal logic of the device.
VDD Power Supply Provide power supply voltage.
VSS Ground

SST26VF080A
3.0 MEMORY ORGANIZATION
The SST26VF080A SQI memory array is organized in SQI Flash memory supports both Mode 0 (0,0) and
uniform, 4-Kbyte erasable sectors with the following Mode 3 (1,1) bus operations. The difference between
erasable blocks: with 32-Kbyte overlay erasable blocks the two modes is the state of the SCK signal when the
and 64-Kbyte overlay erasable blocks. bus master is in Standby mode and no data is being
transferred. The SCK signal is low for Mode 0 and SCK
signal is high for Mode 3. For both modes, the Serial
4.0 DEVICE OPERATION
Data I/O (SIO[3:0]) is sampled at the rising edge of the
SST26VF080A supports both Serial Peripheral SCK clock signal for input, and driven after the falling
Interface (SPI) bus protocol and a 4-bit multiplexed SQI edge of the SCK clock signal for output. The traditional
bus protocol. To provide backward compatibility to SPI protocol uses separate input (SI) and output (SO)
traditional SPI Serial Flash devices, the device’s initial data signals as shown in Figure 4-1. The SQI protocol
state after a Power-on Reset is SPI mode which uses four multiplexed signals, SIO[3:0], for both data in
supports multi-I/O (x1/x2/x4) read/write commands. A and data out, as shown in Figure 4-2. This means the
command instruction configures the device to SQI SQI protocol quadruples the traditional bus transfer
mode. The dataflow in the SQI mode is similar to the speed at the same clock frequency, without the need
SPI mode, except it uses four multiplexed I/O signals for more pins on the package.
for command, address, and data sequence.
FIGURE 4-1: SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)
CE#
MODE 3 MODE 3
SCK MODE 0 MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Don’t Care
MSB
High-Impedance
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
FIGURE 4-2: SQI SERIAL QUAD I/O PROTOCOL
CE#
MODE 3 MODE 3
CLK
MODE 0 MODE 0
SIO[3:0] C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3
MSB

SST26VF080A
4.1 Device Protection 4.2 Hardware Write Protection
SST26VF080A offers a software write protection The hardware Write Protection pin (WP#) is used in
scheme that allows group protection of selected blocks conjunction with the WPEN and IOC bits in the
in memory array. The Write Protection Pin (WP#) Configuration register to enable the lock-down function
enables or disables the lock-down (BPL bit) of the of the BPL bit (bit 7) in the STATUS register and the
STATUS register. In addition, the Lock-Down Configuration register. The WP# pin function only
Protection Settings command also prevents any works in SPI Single-Bit and Dual-Bit Read mode when
changes to the block protection setting (BP0, BP1 and the IOC bit in the Configuration register is set to ‘0’. The
BP2) during device operation. To avoid inadvertent WP# pin function is disabled when the WPEN bit in the
writes during power-up, the device is write-protected by Configuration register is ‘0’. This allows installation of
default after a Power-on Reset cycle. the device in a system with a grounded WP# pin while
still enabling write to the BP bits in the STATUS
4.1.1 GROUP BLOCK PROTECTION register.
The Block Protection bits (BP0, BP1, BP2, and BPL) in The factory default setting at power-up of the WPEN bit
the STATUS register provide write protection to the is ‘0’, disabling the Write-Protect function of the
memory array and the STATUS register. See Table 4-4 WP# pin after power-up. WPEN is a nonvolatile bit;
for the Block Protection description. once the bit is set to ‘1’, the Write-Protect function of
the WP# pin continues to be enabled after power-up.
4.1.2 VOLATILE LOCK PROTECTION The WP# pin only protects the BPL bit in STATUS
To prevent changes to the Block Protection settings, register and Configuration register from changes.
use the Lock-Down Protection Settings (LDPS) Therefore, if the WP# pin is set to low while an internal
command to enable Volatile Lock Protection. Once write is in progress, it will have no effect on the write
Volatile Lock Protection is enabled, the Block command. The IOC bit takes priority over the WPEN bit
Protection settings cannot be changed. To avoid in the Configuration register. When the IOC bit is ‘1’, the
inadvertent lock-down, the WREN command must be function of the WP# pin is disabled and the WPEN bit
executed prior to the LDPS command. To reset Volatile serves no function. When WP# is driven low and IOC
Lock Protection, performing a hardware Reset or bit = 0, the execution of the Write STATUS Register
power cycle on the device is required. The Volatile Lock (WRSR) instruction to change the BP bits in the STATUS
Protection status may be read from the Configuration register is determined by the value of the BPL bit (see
register. Table 4-1). When WP# is high, the lock-down function
of the BPL bit is disabled.
TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES

WRSR Instruction to Change BP0, WRSR Instruction to
VLP WP# IOC WPEN BPL BP1, BP2, BP3 Bits in STATUS Change Configuration
Register Register
0 L 0 0 X Allowed Allowed
0 L 0 1 0 Allowed Not Allowed
0 L 0 1 1 Not Allowed Not Allowed
0 L 1 X X Allowed Allowed
0 H X X X Allowed Allowed
1 L 0 0 X Not Allowed Allowed
1 L 0 1 X Not Allowed Not Allowed
1 L 1 X X Not Allowed Allowed
1 H X X X Not Allowed Allowed
Note 1: X = “Don’t care”.

SST26VF080A
4.3 Security ID SST26VF080A ships with the IOC bit set to ‘0’ and the
HOLD# pin function enabled. The HOLD# pin is always
SST26VF080A offers a 2-Kbyte Security ID (Sec ID) disabled in SQI mode and only works in SPI single-bit
feature. The Security ID space is divided into two parts: and dual-bit read mode.
one factory-programmed, 128-bit segment, and one
user-programmable segment. To activate the Hold mode, CE# must be in active-low
The factory-programmed segment is programmed state. The Hold mode begins when the SCK active-low
during part manufacture with a unique number and state coincides with the falling edge of the HOLD#
cannot be changed. The user-programmable segment signal. The Hold mode ends when the HOLD# signal’s
is left unprogrammed for the customer to program as rising edge coincides with the SCK active-low state.
desired. If the falling edge of the HOLD# signal does not
Use the Program Security ID (PSID) command to coincide with the SCK active-low state, then the device
program the Security ID using the address shown in enters Hold mode when the SCK next reaches the
Table 5-5. The Security ID can be locked using the active-low state. Similarly, if the rising edge of the
Lockout Security ID (LSID) command. This prevents HOLD# signal does not coincide with the SCK
any future write operations to the Security ID. active-low state, then the device exits Hold mode when
the SCK next reaches the active-low state. See
The factory-programmed portion of the Security ID can Figure 4-3.
not be programmed by the user; neither the
factory-programmed nor user-programmable areas Once the device enters Hold mode, SO will be in
can be erased. high-impedance state while SI and SCK can be VIL or
VIH.
4.4 Hold Operation If CE# is driven active-high during a Hold condition, it
resets the internal logic of the device. As long as
The HOLD# pin pauses active serial sequences HOLD# signal is low, the memory remains in the Hold
without resetting the clocking sequence. This pin is condition. To resume communication with the device,
active after every power-up and only operates HOLD# must be driven active-high, and CE# must be
during SPI single-bit and dual-bit modes. driven active-low.
FIGURE 4-3: HOLD CONDITION WAVEFORM
SCK
HOLD#
Active Hold Active Hold Active
4.5 Reset Operation 4.5.1 HARDWARE RESET OPERATION

If the RST#/HOLD#SIO3 pin is used as a Reset pin, To configure the RESET#/HOLD#/SIO3 pin as a
RST# pin provides a hardware method for resetting the RESET# pin, bit 6 of the Configuration register must be
device. SST26VF080A supports both hardware and set to ‘1’. The factory default setting of bit 6 is
software Reset operation. Hardware Reset is only ‘0’-HOLD# pin enabled. This is a nonvolatile bit, so the
allowed using SPI x1 and x2 protocol. Software Reset register value at power-up will be the value prior to
commands 66H and 99H are supported in all protocols. power-down. Driving the RESET# pin high puts the
See Table 4-2 and for Figure 4-4 for hardware and device in normal operating mode. The RESET# pin
software Reset functionality. must be driven low for a minimum of TRST time to reset
the device. The SIO1 pin (SO) is in high-impedance
Note: A device Reset during an active program state while the device is in Reset. A successful Reset
or erase operation aborts the operation operation will reset the protocol to SPI mode, STATUS
and data of the targeted address range register bits will become as follows: BUSY = 0,
may be corrupted or lost due to the WEL = 0, BP0 = 1, BP1 = 1, BP2 = 1 and BPL = 0;
aborted erase or program operation. reset the burst length to 8 bytes. Reset during an active
Depending on the prior operation, the Reset timing may program or erase operation aborts the operation and
vary. Recovery from a write operation requires more data of the targeted address range may be corrupted or
latency time than recovery from other operations. lost due to the aborted erase or program operation.

SST26VF080A
4.5.2 SOFTWARE RESET OPERATION Once the Reset Enable and Reset commands are
successfully executed, the device returns to normal
The Reset operation requires the Reset Enable
operation Read mode and then does the following:
command 66H followed by the Reset command 99H.
resets the protocol to SPI mode, resets the burst length
Note: Any command other than the Reset com- to 8 bytes, STATUS register bits BUSY = 0, WEL = 0;
mand after the Reset Enable command and clears bit 1 (IOC) in the Configuration register to its
will disable the Reset Enable. default state.
FIGURE 4-4: PERFORMING SOFTWARE RESET DURING READ
Device requires Software Reset

while performing Read.
Was the previous Issue either a Reset Quad I/O command

Instruction a (0xFF instruction) or a Software Reset
mode Read with command (0x66 instruction followed by
Yes 0x99 instruction) to exit mode Read.
M[7:0]=AXH
No
Issue Software Reset command (0x66

instruction followed by 0x99 instruction)
to reset the device.
Device is Reset.

SST26VF080A
TABLE 4-2: REGISTER SETTINGS AFTER HARDWARE AND SOFTWARE RESET

After Power Cycle After Hardware Reset After Software Reset
Status Register Bits
Busy Bit 0 0 0
WEL Bit 0 0 0
BP0 Bit 1 1 Unchanged
BPL Bit 0 0 Unchanged
Configuration Register Bits
IOC Bit 0 0 0
VLP Bit 0 0 Unchanged
SEC Bit Unchanged Unchanged Unchanged
WSE Bit 0 0 0
WSP Bit 0 0 0
RSTHLD Bit Unchanged Unchanged Unchanged
WPEN Bit Unchanged Unchanged Unchanged
4.6 STATUS Register

The software STATUS register provides status on
whether the Flash memory array is available for any
read or write operation, whether the device is
write-enabled, and the state of the memory write
protection. During an internal erase or program
operation, the STATUS register may be read only to
determine the completion of an operation in progress.
Table 4-3 describes the function of each bit in the
software STATUS register.
TABLE 4-3: SOFTWARE STATUS REGISTER

Default at
Bit Name Function Read/Write
Power-Up
0 BUSY 1 = Internal write operation is in progress 0 R
0 = No internal write operation is in progress
1 WEL 1 = Device is memory write-enabled 0 R
0 = Device is not memory write-enabled
2 BP0 Indicate current level of block write protection (see Table 4-4) 1 R/W
6 RES Reserved 0 R
7 BPL 1 = BP3, BP2, BP1, BP0 are read-only bits 0 R/W
0 = BP3, BP2, BP1, BP0 are read/writable

SST26VF080A
4.6.1 BUSY 4.6.3 BLOCK PROTECTION (BP3, BP2,
The BUSY bit determines whether there is an internal BP1, BP0)
erase or program operation in progress. A ‘1’ for the The Block Protection (BP3, BP2, BP1, BP0) bits define
BUSY bit indicates the device is busy with an operation the size of the memory area, as defined in Table 4-4, to
in progress. A ‘0’ indicates the device is ready for the be software-protected against any memory write (pro-
next valid operation. gram or erase) operations.
The Write STATUS Register (WRSR) instruction is used
4.6.2 WRITE ENABLE LATCH (WEL)
to program the BP3, BP2, BP1 and BP0 bits as long as
The Write Enable Latch bit indicates the status of the WP# pin is high or the Block Protect Lock (BPL) bit is
internal memory Write Enable Latch. If the Write ‘0’. Chip Erase can only be executed if Block Protection
Enable Latch bit is set to ‘1’, it indicates the device is bits are ‘0’. After power-up, BP3, BP2, BP1 and BP0
write-enabled. If the bit is set to ‘0’ (Reset), it indicates are set to defaults specified in Table 4-4.
the device is not write-enabled and does not accept
any memory write (program/erase) commands. The 4.6.4 BLOCK PROTECTION LOCK-DOWN
Write Enable Latch bit is automatically reset under the (BPL)
following conditions:
WP# pin driven low (VIL), IO bit = 0 and WPEN bit = 1
• Power-Up enable the Block Protection Lock-Down (BPL) bit.
• Write Disable (WRDI) instruction completion When BPL is set to ‘1’, it prevents any further alteration
• Page Program instruction completion of the BPL, BP3, BP2, BP1, and BP0 bits. When the
• Sector Erase instruction completion WP# pin is driven high (VIH), the BPL bit has no effect
and its value is “don’t care”. After power-up and
• Block Erase instructions (32-Kbyte and 64-Kbyte)
hardware Reset, the BPL bit is reset to ‘0’.
completion
• Chip Erase instruction completion
• Write STATUS Register instruction completion
• Software or hardware Reset
• Lock-Down Protection Setting instruction comple-
tion
• Program Security ID instruction completion
• Lockout Security ID instruction completion
• Write-Suspend instruction
• SPI Quad Page program instruction completion
TABLE 4-4: SOFTWARE STATUS REGISTER BLOCK PROTECTION

STATUS Register Bit Protected Memory Address
Protected Level
BP3 BP2 BP1 BP0 8 Mbit
None X 0 0 0 None
Upper 1/16 X 0 0 1 F0000H-FFFFFH
Upper 1/8 X 0 1 0 E0000H-FFFFFH
Upper 1/4 X 0 1 1 C0000H-FFFFFH
Upper 1/2 X 1 0 0 80000H-FFFFFH
All X 1 0 1 00000H-FFFFFH
Note 1: X = “Don’t care” (Reserved) default is ‘0’.
2: Default at power-up for BP3, BP2, BP1 and BP0 is ‘0111’.

SST26VF080A
4.7 Configuration Register
The Configuration register is a Read/Write register that
stores a variety of configuration information. See
Table 4-5 for the function of each bit in the register.
TABLE 4-5: CONFIGURATION REGISTER

Default at Read/Write
Bit Name Function
Power-Up (R/W)
0 Reserved R
(1)
1 IOC I/O Configuration 0 R/W
1 = WP# and RST# or HOLD# pins disabled
0 = WP# and RST# or HOLD# pins enabled
2 VLP Volatile Lock Protection 0(1) R
1 = Locks Protection bit setting of BP0, BP1, BP2, BP3
of STATUS register
0 = Protection bit BP0, BP1, BP2, BP3 setting not
locked by VLP bit
3 SEC Security ID Status 0(2) R
1 = Security ID space locked
0 = Security ID space not locked
4 WSE Write Suspend Erase Status 0 R
1 = Erase suspended
0 = Erase is not suspended
5 WSP Write Suspend Program Status 0 R
1 = Program suspended
0 = Program is not suspended
6 RSTHLD RST# pin or HOLD# Pin Enable 0(3) R/W
1 = RST# pin enabled
0 = HOLD# pin enabled
7 WPEN Write Protection Pin (WP#) Enable 0(3) R/W
1 = WP# enabled
0 = WP# disabled
Note 1: Default at power-up or after hardware Reset is ‘0’.
2: The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout Security
ID instruction, otherwise default at power-up is ‘0’.
3: Factory default setting. This is a nonvolatile bit, default at power-up will be the setting prior to
power-down.
4.7.1 I/O CONFIGURATION (IOC) 4.7.2 VOLATILE LOCK PROTECTION

The I/O Configuration (IOC) bit reconfigures the I/O (VLP)
pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the The Volatile Lock Protection (VLP) bit is a volatile bit
Configuration register. When IOC bit is ‘0’ the WP# pin which is set to ‘1’ when a lock-down protection settings
and HOLD# pin or RST# pin are enabled (SPI or Dual (LDPS) command is executed. When VLP bit is set
configuration setup). When IOC bit is set to ‘1’ the SIO2 to ‘1’, it locks the protection bit BP0, BP1, BP2, BP3
pin and SIO3 pin are enabled (SPI Quad I/O configura- settings of the STATUS register. The VLP bit can be
tion setup). The IOC bit must be set to ‘1’ before issuing cleared to ‘0’ only by performing a hardware Reset or
the following SPI commands: SQOR (6BH), SQIOR by performing a power cycle.
(EBH), SPI Quad page program (32H) and RBSPI
(ECH). Without setting the IOC bit to ‘1’, those SPI 4.7.3 SECURITY ID STATUS (SEC)
commands are not valid. The I/O Configuration bit does The Security ID Status (SEC) bit indicates when the
not apply when in SQI mode. The default at power-up Security ID space is locked to prevent a write com-
and after hardware/software Reset is ‘0’. mand. The SEC bit is ‘1’ after the host issues a Lockout
SID command. Once the host issues a Lockout SID
command, the SEC bit can never be reset to ‘0’.

SST26VF080A
4.7.4 WRITE SUSPEND ERASE STATUS
(WSE)
The Write Suspend Erase status (WSE) indicates when
an erase operation is suspended. The WSE bit is ‘1’
after the host issues a suspend command during an
erase operation. Once the suspended Erase resumes,
the WSE bit is reset to ‘0’.
4.7.5 WRITE SUSPEND PROGRAM

STATUS (WSP)
The Write Suspend Program status (WSP) bit indicates
when a program operation is suspended. The WSP
is ‘1’ after the host issues a suspend command during
the program operation. Once the suspended program
operation resumes, the WSP bit is reset to ‘0’.
4.7.6 RESET/HOLD ENABLE (RSTHLD)

The Reset/Hold Enable (RSTHLD) bit is a nonvolatile
bit that configures RST#/HOLD#/SIO3 pin to be either
RST# pin or Hold# pin when not configured as an I/O.
There is latency associated with writing to the RSTHLD
bit. Poll the BUSY bit in the STATUS register or wait
TCONFIG for the completion of the internal, self-timed
write operation.
4.7.7 WRITE-PROTECT ENABLE (WPEN)

The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that enables the WP# pin. The Write-Protect (WP#)
pin and the Write-Protect Enable (WPEN) bit control
the programmable hardware write-protect feature.
Setting the WP# pin to low, and the WPEN bit to ‘1’,
enables hardware write protection. To disable
hardware write protection, set either the WP# pin to
high or the WPEN bit to ‘0’. There is latency associated
with writing to the WPEN bit. Poll the BUSY bit in the
STATUS register or wait TCONFIG for the completion
of the internal, self-timed write operation. When the
chip is hardware write-protected, only write operations
to BPL bit in STATUS register and Configuration
register are disabled. See Section 4.2 “Hardware
Write Protection” and Table 4-1 for more information
about the functionality of the WPEN bit.

SST26VF080A
5.0 INSTRUCTIONS
Instructions are used to read, write (erase and pro-
gram), and configure the SST26VF080A. The com-
plete list of the instructions is provided in Table 5-1.
TABLE 5-1: DEVICE OPERATION INSTRUCTIONS

Op Mode
Address Dummy Data Maximum
Instruction Description Code
Cycle(s)(2,3) Cycle(s)(3) Cycle(s)(3) Frequency (4)
Cycle(1) SPI SQI
Configuration
NOP No Operation 00H X X 0 0 0
RSTEN Reset Enable 66H X X 0 0 0
RST Reset Memory 99H X X 0 0 0
EQIO Enable Quad I/O 38H X 0 0 0
RSTQIO Reset Quad I/O FFH X X 0 0 0
RDSR(5) Read STATUS 05H X 0 0 1 to ∞ 104 MHz/80 MHz
Register X 0 1 1 to ∞
WRSR Write STATUS 01H X X 0 0 1 to 2
Register
RDCR Read Configuration 35H X 0 0 1 to ∞
Register X 0 1 1 to ∞
Read
READ Read Memory 03H X 3 0 1 to ∞ 40 MHz
High-Speed Read Memory at 0BH X 3 1 1 to ∞
Read Higher Speed X 3 3 1 to ∞ 104 MHz/80 MHz
SDOR(6) SPI Dual Output Read 3BH X 3 1 1 to ∞
SDIOR (7,8) SPI Dual I/O Read BBH X 3 1 1 to ∞ 80 MHz
(9) SPI Quad Output 6BH X 3 1 1 to ∞
SQOR
Read
SQIOR (10) SPI Quad I/O Read EBH X 3 3 1 to ∞
SB Set Burst Length C0H X X 0 0 1
104 MHz/80 MHz
RBSQI SQI nB Burst with 0CH X 3 3 n to ∞
Wrap
RBSPI SPI nB Burst with ECH X 3 3 n to ∞
Wrap
Identification
JEDEC ID JEDEC® ID Read 9FH X 0 0 3 to ∞
Quad J-ID Quad I/O J-ID Read AFH X 0 1 3 to ∞
104 MHz/80 MHz
SFDP Serial Flash Discover- 5AH X 3 1 1 to ∞
able Parameters

SST26VF080A
TABLE 5-1: DEVICE OPERATION INSTRUCTIONS (CONTINUED)
Op Mode
Cycle(1) SPI SQI
Write
WREN Write Enable 06H X X 0 0 0
WRDI Write Disable 04H X X 0 0 0
4-Kbyte Erase 4 Kbyte of 20H X X 3 0 0
Sector Memory Array
Erase(11)
32-Kbyte Erase 32 Kbyte of 52H X X 3 0 0
Block Block Memory Array
Erase(12)
64-Kbyte Erase 64 Kbyte of D8H X X 3 0 0
Block Block Memory Array
Erase(13) 104 MHz/80 MHz
Chip Erase Erase Full Memory 60H or X X 0 0 0
Array C7H
Page To Program 1 to 256 02H X X 3 0 1 to 256
Program Data Bytes
SPI Quad SPI Quad Page 32H X 3 0 1 to 256
PP(9) Program
WRSU Suspends B0H X X 0 0 0
Program/Erase
WRRE Resume 30H X X 0 0 0
Program/Erase
Protection
LDPS Lock-Down 8DH X X 0 0 0
Protection Settings
RSID Read Security ID 88H X 2 1 1 to 1024
X 2 3 1 to 1024
104 MHz/80 MHz
PSID Program User A5H X X 2 0 1 to 256
Security ID Area
LSID Lockout Security ID 85H X X 0 0 0
Programming

SST26VF080A
TABLE 5-1: DEVICE OPERATION INSTRUCTIONS (CONTINUED)
Op Mode
Cycle(1) SPI SQI
Power-Saving
DPD Deep Power-Down B9H X X 0 0 0
Mode
RDPD Release from Deep ABH X X 3 0 1 to ∞ 104 MHz/80 MHz
Power-Down and
Read ID
Note 1: Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode.
2: Address bits above the Most Significant bit of each density can be VIL or VIH.
3: Address, Dummy/Mode bits, and data cycles are two clock periods in SQI and eight clock periods in SPI mode.
4: The maximum frequency for all instructions is up to 104 MHz from 2.7V-3.6V and up to 80 MHz from 2.3V-3.6V
unless otherwise noted. For extended temperature (125°C) the maximum frequency is up to 80 MHz.
5: The Read STATUS register is continuous with ongoing clock cycles until terminated by a low-to-high transition
on CE#.
6: Data cycles are four clock periods.
7: The maximum frequency for SDIOR is up to 80 MHz from 2.3V-3.6V.
8: Address, Dummy/Mode bits, and data cycles are four clock periods.
9: Data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.
10: Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the
command.
11: 4-Kbyte Sector Erase addresses: use AMS-A12, remaining addresses are “don’t care” but must be set either at
VIL or VIH.
12: 32-Kbyte Block Erase addresses: use AMS-A15, remaining addresses are “don’t care” but must be set either at
VIL or VIH.
13: 64-Kbyte Block Erase addresses: use AMS-A16, remaining addresses are “don’t care” but must be set either at
VIL or VIH.
5.1 No Operation (NOP) Once the Reset Enable and Reset commands are
successfully executed, the device returns to normal
The No Operation command only cancels a Reset operation Read mode and then does the following:
Enable command. NOP has no impact on any other resets the protocol to SPI mode, resets the burst length
command. to 8 bytes, clears BUSY bit and WEL bit in the STATUS
register to their default states, and clears IOC bit,
5.2 Reset Enable (RSTEN) and Reset WSE bit and WSP bit in the Configuration register to its
(RST) default state. A device Reset during an active program
or erase operation aborts the operation, which can
The Reset operation is used as a system (software) cause the data of the targeted address range to be
Reset that puts the device in normal operating Ready corrupted or lost. Depending on the prior operation, the
mode. This operation consists of two commands: Reset timing may vary. Recovery from a write operation
Reset Enable (RSTEN) followed by Reset (RST). requires more latency time than recovery from other
To reset SST26VF080A, the host drives CE# low, operations. See Table 8-2 for Reset timing parameters.
sends the Reset Enable command (66H), and drives
CE# high. Next, the host drives CE# low again, sends
the Reset command (99H), and drives CE# high, see
Figure 5-1.
The Reset operation requires the Reset Enable
command followed by the Reset command. Any
command other than the Reset command after the
Reset Enable command will disable the Reset Enable.

SST26VF080A
FIGURE 5-1: RESET SEQUENCE
TCPH
CE#
MODE 3 MODE 3 MODE 3
CLK
SIO[3:0] C1 C0 C3 C2
Note: C[1:0] = 66H; C[3:2] = 99H
5.3 Read (40 MHz) Initiate the READ instruction by executing an 8-bit
command, 03H, followed by address bits A[23:0].
The READ instruction, 03H, is supported in SPI bus CE# must remain active-low for the duration of the
protocol only with clock frequencies up to 40 MHz. Read cycle. See Figure 5-2 for the Read sequence.
This command is not supported in SQI bus protocol.
The device outputs the data starting from the specified
address location, then continuously streams the data
output through all addresses until terminated by a
low-to-high transition on CE#. The internal Address
Pointer will automatically increment until the highest
memory address is reached. Once the highest memory
address is reached, the Address Pointer will
automatically return to the beginning (wrap-around) of
the address space.
FIGURE 5-2: READ SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70
SCK MODE 0
SI 03 ADD. ADD. ADD.

MSB MSB
N N+1 N+2 N+3 N+4
High-Impedance DOUT DOUT DOUT DOUT DOUT
SO
MSB

SST26VF080A
5.4 Enable Quad I/O (EQIO)
The Enable Quad I/O (EQIO) instruction, 38H, enables
the Flash device for SQI bus operation. Upon comple-
tion of the instruction, all instructions thereafter are
expected to be 4-bit multiplexed input/output (SQI
mode) until a power cycle or a Reset Quad I/O instruc-
tion is executed. See Figure 5-3.
FIGURE 5-3: ENABLE QUAD I/O SEQUENCE
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 38
SIO[3:1]
Note: SIO[3:1] must be driven VIH.
5.5 Reset Quad I/O (RSTQIO) To execute a Reset Quad I/O operation, the host drives
CE# low, sends the Reset Quad I/O command cycle
The Reset Quad I/O instruction, FFH, resets the device (FFH) then drives CE# high. Execute the instruction in
to 1-bit SPI protocol operation or exits the Set Mode either SPI (8 clocks) or SQI (2 clocks) command
configuration during a read sequence. This command cycles. For SPI, SIO[3:1] are “don’t care” for this
allows the Flash device to return to the default I/O state command, but should be driven to VIH or VIL. See
(SPI) without a power cycle, and executes in either Figures 5-4 and 5-5.
1-bit or 4-bit mode. If the device is in the Set Mode con-
figuration, while in SQI High-Speed Read mode, the
RSTQIO command will only return the device to a state
where it can accept new command instruction. An addi-
tional RSTQIO is required to reset the device to SPI
mode.
FIGURE 5-4: RESET QUAD I/O SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 FF
SIO[3:1]

SST26VF080A
FIGURE 5-5: RESET QUAD I/O SEQUENCE (SQI)
CE#
MODE 3 0 1
SCK MODE 0
SIO[3:0] F F
5.6 High-Speed Read Initiate High-Speed Read by executing an 8-bit

command, 0BH, followed by address bits A[23:0] and a
The High-Speed Read instruction, 0BH, is supported in dummy byte. CE# must remain active-low for the
both SPI bus protocol and SQI protocol. This instruc- duration of the High-Speed Read cycle. See Figure 5-6
tion supports frequencies of up to 104 MHz from for the High-Speed Read sequence for SPI bus
2.7V-3.6V and up to 80 MHz from 2.3V-3.6V. On protocol.
power-up, the device is set to use SPI.
FIGURE 5-6: HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SCK MODE 0
SI/SIO0 0B ADD. ADD. ADD. X
N N+1 N+2 N+3 N+4

High-Impedance
SO/SIO1 DOUT DOUT DOUT DOUT DOUT
MSB
In SQI protocol, the host drives CE# low then sends When M[7:0] = AXH, the device expects the next
one High-Speed Read command cycle, 0BH, followed continuous instruction to be another read command,
by three address cycles, a Set Mode configuration 0BH, and does not require the opcode to be entered
cycle, and two dummy cycles. Each cycle is two nibbles again. The host may initiate the next read cycle by
(clocks) long, Most Significant nibble first. driving CE# low, then sending the 4-bit input for
After the dummy cycles, the device outputs data on the address A[23:0], followed by the Set Mode
falling edge of the SCK signal starting from the Configuration bits M[7:0], and two dummy cycles. After
specified address location. The device continually the two dummy cycles, the device outputs the data
streams data output through all addresses until starting from the specified address location. There are
terminated by a low-to-high transition on CE#. The no restrictions on address location access.
internal Address Pointer automatically increments until When M[7:0] is any value other than AXH, the device
the highest memory address is reached, at which point expects the next instruction initiated to be a command
the Address Pointer returns to address location instruction. To reset/exit the Set Mode configuration,
000000H. During this operation, blocks that are execute the Reset Quad I/O command, FFH. While in
read-locked will output data 00H. the Set Mode configuration, the RSTQIO command will
The Set Mode Configuration bit M[7:0] indicates if the only return the device to a state where it can accept a
next instruction cycle is another SQI High-Speed Read new command instruction. An additional RSTQIO is
command. required to reset the device to SPI mode. See
Figure 5-10 for the SPI Quad I/O Mode Read sequence
when M[7:0] = AXH.

SST26VF080A
FIGURE 5-7: HIGH-SPEED READ SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 20 21
SCK
MODE 0 MSN LSN
SIO[3:0] C0 C1 A5 A4 A3 A2 A1 A0 M1 M0 X X X X H0 L0 H8 L8
Command Address Mode Dummy Data Byte 0 Data Byte 7
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble

Hx = High Data Nibble, Lx = Low Data Nibble C[1:0] = 0BH
5.7 SPI Quad Output Read

The SPI Quad Output Read instruction supports fre- Following the dummy byte, the device outputs data
quencies of up to 104 MHz from 2.7V-3.6V and up to from SIO[3:0] starting from the specified address
80 MHz from 2.3V-3.6V. SST26VF080A requires the location. The device continually streams data output
IOC bit in the Configuration register to be set to ‘1’ prior through all addresses until terminated by a low-to-high
to executing the command. Initiate SPI Quad Output transition on CE#. The internal Address Pointer
Read by executing an 8-bit command, 6BH, followed automatically increments until the highest memory
by address bits A[23:0] and a dummy byte. CE# must address is reached, at which point the Address Pointer
remain active-low for the duration of the SPI Quad returns to the beginning of the address space.
Mode Read. See Figure 5-8 for the SPI Quad Output
Read sequence.
FIGURE 5-8: SPI QUAD OUTPUT READ
CE#
MODE 3
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 41
SCK MODE 0
SIO0 6BH A[23:16] A[15:8] A[7:0] X b4 b0 b4 b0

Data Data
OP Code Address Dummy Byte 0 Byte N
SIO1 b5 b1 b5 b1
SIO2 b6 b2 b6 b2
SIO3 b7 b3 b7 b3

SST26VF080A
5.8 SPI Quad I/O Read
The SPI Quad I/O Read (SQIOR) instruction supports The Set Mode Configuration bit M[7:0] indicates if the
frequencies of up to 104 MHz from 2.7V-3.6V and up to next instruction cycle is another SPI Quad I/O Read
80 MHz from 2.3V-3.6V. SST26VF080A requires the command. When M[7:0] = AXH, the device expects the
IOC bit in the Configuration register to be set to ‘1’ prior next continuous instruction to be another read com-
to executing the command. Initiate SQIOR by execut- mand, EBH, and does not require the opcode to be
ing an 8-bit command, EBH. The device then switches entered again. The host may set the next SQIOR cycle
to 4-bit I/O mode for address bits A[23:0], followed by by driving CE# low, then sending the 4-bit wide input for
the Set Mode Configuration bits M[7:0], and two address A[23:0], followed by the Set Mode Configura-
dummy bytes. CE# must remain active-low for the tion bits M[7:0], and two dummy cycles. After the two
duration of the SPI Quad I/O Read. See Figure 5-9 for dummy cycles, the device outputs the data starting
the SPI Quad I/O Read sequence. from the specified address location. There are no
Following the dummy bytes, the device outputs data restrictions on address location access.
from the specified address location. The device When M[7:0] is any value other than AXH, the device
continually streams data output through all addresses expects the next instruction initiated to be a command
until terminated by a low-to-high transition on CE#. The instruction. To reset/exit the Set Mode configuration,
internal Address Pointer automatically increments until execute the Reset Quad I/O command, FFH. See
the highest memory address is reached, at which point Figure 5-10 for the SPI Quad I/O Mode Read sequence
the Address Pointer returns to the beginning of the when M[7:0] = AXH.
address space.
FIGURE 5-9: SPI QUAD I/O READ SEQUENCE
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK MODE 0
SIO0 EBH A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0 b4 b0
SIO1 A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1 b5 b1

MSN LSN

Set Data Data
Address Mode Dummy Byte 0 Byte 1

SST26VF080A
FIGURE 5-10: BACK-TO-BACK SPI QUAD I/O READ SEQUENCES WHEN M[7:0] = AXH
CE#
0 1 2 3 4 5 6 7 8 9 10 11 12 13
SCK
SIO0 b4 b0 b4 b0 A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0

MSN LSN
Data Data Set Data
Byte Byte Address Mode Dummy Byte 0
N N+1
5.9 Set Burst

The Set Burst command specifies the number of bytes
to be output during a Read Burst command before the
device wraps around. It supports both SPI and SQI pro-
tocols. To set the burst length the host drives CE# low,
sends the Set Burst command cycle (C0H) and one
data cycle, then drives CE# high. After power-up or
Reset, the burst length is set to eight bytes (00H). See
Table 5-2 for burst length data and Figures 5-11 and
5-12 for the sequences.
TABLE 5-2: BURST LENGTH DATA

Burst Length High Nibble (H0) Low Nibble (L0)
8 Bytes 0h 0h
16 Bytes 0h 1h
32 Bytes 0h 2h
64 Bytes 0h 3h
FIGURE 5-11: SET BURST LENGTH SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3
SCK MODE 0
SIO[3:0] C1 C0 H0 L0
MSN LSN
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = C0H

SST26VF080A
FIGURE 5-12: SET BURST LENGTH SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK MODE 0
SIO0 C0 DIN
SIO[3:1]
5.10 SQI Read Burst with Wrap (RBSQI) 5.11 SPI Read Burst with Wrap (RBSPI)
SQI Read Burst with Wrap is similar to High-Speed SPI Read Burst with Wrap (RBSPI) is similar to SPI
Read in SQI mode, except data will output continuously Quad I/O Read except the data will output continuously
within the burst length until a low-to-high transition on within the burst length until a low-to-high transition on
CE#. To execute a SQI Read Burst operation, drive CE#. To execute a SPI Read Burst with Wrap opera-
CE# low then send the Read Burst command cycle tion, drive CE# low, then send the Read Burst com-
(0CH), followed by three address cycles, and then mand cycle (ECH), followed by three address cycles,
three dummy cycles. Each cycle is two nibbles (clocks) and then three dummy cycles.
long, Most Significant nibble first. After the dummy cycle, the device outputs data on the
After the dummy cycles, the device outputs data on the falling edge of the SCK signal starting from the
falling edge of the SCK signal starting from the specified address location. The data output stream is
specified address location. The data output stream is continuous through all addresses until terminated by a
continuous through all addresses until terminated by a low-to-high transition on CE#.
low-to-high transition on CE#. During RBSPI, the internal Address Pointer automati-
During RBSQI, the internal Address Pointer automatically increments until the last byte of the burst is
cally increments until the last byte of the burst is reached, then it wraps around to the first byte of the
reached, then it wraps around to the first byte of the burst. All bursts are aligned to addresses within the
burst. All bursts are aligned to addresses within the burst length, see Table 5-3. For example, if the burst
burst length, see Table 5-3. For example, if the burst length is eight bytes, and the start address is 06h, the
length is eight bytes, and the start address is 06h, the burst sequence would be: 06h, 07h, 00h, 01h, 02h,
burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. The pattern repeats until the
03h, 04h, 05h, 06h, etc. The pattern repeats until the command is terminated by a low-to-high transition on
command is terminated by a low-to-high transition on CE#.
CE#. During this operation, blocks that are read-locked will
During this operation, blocks that are read-locked will output data 00H.
output data 00H.
TABLE 5-3: BURST ADDRESS RANGES

Burst Length Burst Address Ranges
8 Bytes 00-07H, 08-0FH, 10-17H, 18-1FH...
16 Bytes 00-0FH, 10-1FH, 20-2FH, 30-3FH...
32 Bytes 00-1FH, 20-3FH, 40-5FH, 60-7FH...
64 Bytes 00-3FH, 40-7FH, 80-BFH, C0-FFH

SST26VF080A
5.12 SPI Dual Output Read Following the dummy byte, SST26VF080A outputs
data from SIO[1:0] starting from the specified address
The SPI Dual Output Read instruction supports location. The device continually streams data output
frequencies of up to 104 MHz from 2.7V-3.6V and up to through all addresses until terminated by a low-to-high
80 MHz from 2.3V-3.6V. Initiate SPI Dual Output Read transition on CE#. The internal Address Pointer
by executing an 8-bit command, 3BH, followed by automatically increments until the highest memory
address bits A[23:0] and a dummy byte. CE# must address is reached, at which point the Address Pointer
remain active-low for the duration of the SPI Dual returns to the beginning of the address space.
Output Read operation. See Figure 5-13 for the SPI
Dual Output Read sequence.
FIGURE 5-13: FAST READ, DUAL-OUTPUT SEQUENCE
CE#
MODE 3
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 41
SCK MODE 0
SIO0 3BH A[23:16] A[15:8] A[7:0] X b6 b5 b3 b1 b6 b5 b3 b1

MSB
SIO1 b7 b4 b2 b0 b7 b4 b2 b0
Data Data
OP Code Address Dummy Byte 0 Byte N
Note: MSB = Most Significant Bit
5.13 SPI Dual I/O Read When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
The SPI Dual I/O Read (SDIOR) instruction supports up instruction. To reset/exit the Set Mode configuration,
to 80 MHz frequency. Initiate SDIOR by executing an execute the Reset Quad I/O command, FFH. See
8-bit command, BBH. The device then switches to 2-bit Figure 5-15 for the SPI Dual I/O Read sequence when
I/O mode for address bits A[23:0], followed by the Set M[7:0] = AXH.
Mode Configuration bits M[7:0]. CE# must remain
active-low for the duration of the SPI Dual I/O Read.
See Figure 5-14 for the SPI Dual I/O Read sequence.
Following the Set Mode Configuration bits, the
SST26VF080A outputs data from the specified address
location. The device continually streams data output
through all addresses until terminated by a low-to-high
transition on CE#. The internal Address Pointer
automatically increments until the highest memory
address is reached, at which point the Address Pointer
returns to the beginning of the address space.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Dual I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another SDIOR
command, BBH, and does not require the opcode to be
entered again. The host may set the next SDIOR cycle
by driving CE# low, then sending the 2-bit wide input for
address A[23:0], followed by the Set Mode
Configuration bits M[7:0]. After the Set Mode
Configuration bits, the device outputs the data starting
from the specified address location. There are no
restrictions on address location access.

SST26VF080A
FIGURE 5-14: SPI DUAL I/O READ SEQUENCE
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK MODE 0
SIO0 BBH 6 4 2 0 6 4 2 0 6 4 2 0 6 4
SIO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5
A[23:16] A[15:8] A[7:0] M[7:0]
CE#(cont’)
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK(cont’)
I/O Switches from Input to Output
SIO0(cont’) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSB MSB MSB MSB
SIO1(cont’) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 0 Byte 1 Byte 2 Byte 3
Note: MSB = Most Significant Bit
FIGURE 5-15: BACK-TO-BACK SPI DUAL I/O READ SEQUENCES WHEN M[7:0] = AXH
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK MODE 0
I/O Switch
SIO0 6 4 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4
MSB MSB
SIO1 7 5 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5
A[23:16] A[15:8] A[7:0] M[7:0]
CE#(cont’)
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK(cont’)
I/O Switches from Input to Output
SIO0(cont’) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSB MSB MSB MSB
SIO1(cont’) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 0 Byte 1 Byte 2 Byte 3
Note: MSB = Most Significant Bit, LSB = Least Significant Bit

SST26VF080A
5.14 JEDEC ID Read (SPI Protocol) Immediately following the command cycle,
SST26VF080A output data on the falling edge of the
Using traditional SPI protocol, the JEDEC ID Read SCK signal. The data output stream is continuous until
instruction identifies the device as SST26VF080A and terminated by a low-to-high transition on CE#. The
the manufacturer as Microchip. To execute a JEDEC ID device outputs three bytes of data: manufacturer,
operation the host drives CE# low then sends the device type, and device ID, see Table 5-4. See
JEDEC ID command cycle (9FH). Figure 5-16 for instruction sequence.
TABLE 5-4: DEVICE ID DATA OUTPUT

Device ID
Product Manufacturer ID (Byte 1)
Device Type (Byte 2) Device ID (Byte 3)
SST26VF080A BFH 26H 18H
FIGURE 5-16: JEDEC ID SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK MODE 0
SI 9F
High-Impedance
SO BF 26 Device ID
MSB MSB
5.15 Read Quad J-ID Read (SQI Immediately following the command cycle and one
Protocol) dummy cycle, SST26VF080A outputs data on the
falling edge of the SCK signal. The data output stream
The Read Quad J-ID Read instruction identifies the is continuous until terminated by a low-to-high
device as SST26VF080A and manufacturer as transition of CE#. The device outputs three bytes of
Microchip. To execute a Quad J-ID operation the host data: manufacturer, device type, and device ID, see
drives CE# low and then sends the Quad J-ID Table 5-4. See Figure 5-17 for instruction sequence.
command cycle (AFH). Each cycle is two nibbles
(clocks) long, Most Significant nibble first.
FIGURE 5-17: QUAD J-ID READ SEQUENCE
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 N
SCK
MODE 0 MSN LSN
SIO[3:0] C0 C1 X X H0 L0 H1 L1 H2 L2 H0 L0 H1 L1 HN LN
Dummy BFH 26H Device ID BFH 26H N
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = AFH

SST26VF080A
5.16 Serial Flash Discoverable Initiate SFDP by executing an 8-bit command, 5AH,
Parameters (SFDP) followed by address bits A[23:0] and a dummy byte.
CE# must remain active-low for the duration of the
The Serial Flash Discoverable Parameters (SFDP) SFDP cycle. For the SFDP sequence, see Figure 5-18.
contain information describing the characteristics of the
device. This allows device-independent, JEDEC
ID-independent, and forward/backward-compatible
software support for all future Serial Flash device
families. See Table 11-1 for address and data values.
FIGURE 5-18: SERIAL FLASH DISCOVERABLE PARAMETERS SEQUENCE
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SCK MODE 0
SI 5A ADD. ADD. ADD. X
N N+1 N+2 N+3 N+4

High-Impedance
SO DOUT DOUT DOUT DOUT DOUT
MSB
5.17 Sector Erase To execute a Sector Erase operation, the host drives
CE# low, then sends the Sector Erase command cycle
The Sector Erase instruction clears all bits in the (20H) and three address cycles, and then drives CE#
selected 4-KByte sector to ‘1’, but it does not change a high. Address bits [AMS:A12] (AMS = Most Significant
protected memory area. Prior to any write operation, Address) determine the sector address (SAX); the
the Write Enable (WREN) instruction must be executed. remaining address bits can be VIL or VIH. To identify the
completion of the internal, self-timed, write operation,
poll the BUSY bit in the STATUS register, or wait TSE.
See Figures 5-19 and 5-20 for the Sector Erase
sequence.
FIGURE 5-19: 4-KBYTE SECTOR ERASE SEQUENCE – SQI MODE
CE#
MODE 3 0 1 2 4 6
SCK MODE 0
SIO[3:0] C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 20H

SST26VF080A
FIGURE 5-20: 4-KBYTE SECTOR ERASE SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SI 20 ADD. ADD. ADD.

MSB MSB
SO High-Impedance
5.18 32-Kbyte Block Erase and The 64-Kbyte Block Erase instruction is initiated by
64-Kbyte Block Erase executing an 8-bit command D8H, followed by address
bits [A23:A0]. Address bits [AMS:A16] (AMS = Most
The 32-Kbyte Block Erase instruction clears all bits in Significant Address) are used to determine block
the selected 32-Kbyte block to FFH. The 64-Kbyte address (BAX), remaining address bits can be VIL or
Block Erase instruction clears all bits in the selected VIH. CE# must be driven high before the instruction is
64-Kbyte block to FFH. A 32-Kbyte Block Erase or executed. The user may poll the BUSY bit in the
64-Kbyte Block Erase instruction applied to a protected software STATUS register or wait TBE for the
memory area will be ignored. Prior to any block erase completion of the internal self-timed 32-Kbyte Block
operation, the Write Enable (WREN) instruction must be Erase or 64-Kbyte Block Erase cycles. See
executed. CE# must remain active-low for the duration Figures 5-21 and 5-22 for the 32-Kbyte Block Erase
of any command sequence. The 32-Kbyte Block Erase sequence and Figures 5-23 and 5-24 for the 64-Kbyte
instruction is initiated by executing an 8-bit command Block Erase sequence.
52H, followed by address bits [A23:A0]. Address bits
[AMS:A15] (AMS = Most Significant Address) are used
to determine block address (BAX), remaining address
bits can be VIL or VIH. CE# must be driven high before
the instruction is executed.
FIGURE 5-21: 32-KBYTE BLOCK-ERASE SEQUENCE (SQI)
CE#
MODE 3 0 1 2 4 6
SCK MODE 0
SIO[3:0] C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 52H

SST26VF080A
FIGURE 5-22: 32-KBYTE BLOCK-ERASE SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SI 52 ADDR ADDR ADDR

MSB MSB
SO High-Impedance
FIGURE 5-23: 64-KBYTE BLOCK-ERASE SEQUENCE (SQI)
CE#
MODE 3 0 1 2 4 6
SCK MODE 0
SIO[3:0] C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = D8H
FIGURE 5-24: 64-KBYTE BLOCK-ERASE SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SI D8 ADDR ADDR ADDR

MSB MSB
SO High-Impedance

SST26VF080A
5.19 Chip Erase To execute a Chip Erase operation, the host drives CE#
low, sends the Chip Erase command cycle (C7H or
The Chip Erase instruction clears all bits in the device 60H), then drives CE# high. Poll the BUSY bit in the
to ‘1’. The Chip Erase instruction is ignored if any of the STATUS register, or wait TSCE, for the completion of the
memory area is protected. Prior to any write operation, internal, self-timed, write operation. See Figures 5-25
execute the WREN instruction. and 5-26 for the Chip Erase sequence.
FIGURE 5-25: CHIP ERASE SEQUENCE (SQI)
CE#
MODE 3 0 1
SCK MODE 0
SIO[3:0] C1 C0
Note: C[1:0] = C7H
FIGURE 5-26: CHIP ERASE SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI C7
MSB
SO High-Impedance

SST26VF080A
5.20 Page Program When executing Page Program, the memory range for
the SST26VF080A is divided into 256-byte page
The Page Program instruction programs up to boundaries. The device handles shifting of more than
256 bytes of data in the memory, and supports both SPI 256 bytes of data by maintaining the last 256 bytes of
and SQI protocols. The data for the selected page data as the correct data to be programmed. If the target
address must be in the erased state (FFH) before address for the Page Program instruction is not the
initiating the Page Program operation. A Page Program beginning of the page boundary (A[7:0] are not all
applied to a protected memory area will be ignored. zero), and the number of bytes of data input exceeds or
Prior to the program operation, execute the WREN overlaps the end of the address of the page boundary,
instruction. the excess data inputs wrap around and will be
To execute a Page Program operation, the host drives programmed at the start of that target page.
CE# low then sends the Page Program command cycle
(02H), three address cycles followed by the data to be
programmed, then drives CE# high. The programmed
data must be between 1 to 256 bytes and in whole-byte
increments; sending less than a full byte will cause the
partial byte to be ignored. Poll the BUSY bit in the
STATUS register, or wait TPP for the completion of the
internal, self-timed, write operation. See Figures 5-27
and 5-28 for the Page Program sequence.
FIGURE 5-27: PAGE-PROGRAM SEQUENCE (SQI)
CE#
MODE 3 0 2 4 6 8 10 12
SCK MODE 0
SIO[3:0] C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 HN LN
MSN LSN
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 255
FIGURE 5-28: PAGE-PROGRAM SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39
SCK MODE 0
SI 02 ADD. ADD. ADD. Data Byte 0

MSB LSB MSB LSB MSB LSB
SO
High-Impedance
CE#(cont’)
2072
2073
2074
2075
2076
2077
2078
2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK(cont’)
SI(cont’) Data Byte 1 Data Byte 2 Data Byte 255

MSB LSB MSB LSB MSB LSB
SO(cont’)
High-Impedance

SST26VF080A
5.21 SPI Quad Page Program When executing SPI Quad Page Program, the memory
range for the SST26VF080A is divided into 256-byte
The SPI Quad Page Program instruction programs up page boundaries. The device handles shifting of more
to 256 bytes of data in the memory. The data for the than 256 bytes of data by maintaining the last
selected page address must be in the erased state 256 bytes of data as the correct data to be
(FFH) before initiating the SPI Quad Page Program programmed. If the target address for the SPI Quad
operation. A SPI Quad Page Program applied to a Page Program instruction is not the beginning of the
protected memory area will be ignored. SST26VF080A page boundary (A[7:0] are not all zero), and the of
requires the ICO bit in the Configuration register to be bytes of data input exceeds or overlaps the end of the
set to ‘1’ prior to executing the command. Prior to the address of the page boundary, the excess data inputs
program operation, execute the WREN instruction. wrap around and will be programmed at the start of that
To execute a SPI Quad Page Program operation, the target page.
host drives CE# low then sends the SPI Quad Page
Program command cycle (32H), three address cycles
followed by the data to be programmed, then drives
CE# high. The programmed data must be between 1 to
256 bytes and in whole-byte increments. The com-
mand cycle is eight clocks long, the address and data
cycles are each two clocks long, Most Significant bit
first. Poll the BUSY bit in the STATUS register, or wait
TPP for the completion of the internal, self-timed, write
operation. See Figure 5-29.
FIGURE 5-29: SPI QUAD PAGE-PROGRAM SEQUENCE
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SCK MODE 0
SIO0 32H A20A16A12 A8 A4 A0 b4 b0 b4 b0 b4 b0
SIO1 A21 A17A13 A9 A5 A1 b5 b1 b5 b1 b5 b1
SIO2 A22 A18A14A10 A6 A2 b6 b2 b6 b2 b6 b2

MSN LSN
SIO3 A23 A19 A15 A11 A7 A3 b7 b3 b7 b3 b7 b3

Data Data Data
Address Byte 0 Byte 1 Byte
255
5.22 Write Suspend and Write Resume The Write Resume command is ignored until any write
operation (Program or Erase) initiated during the Write
Write Suspend allows the interruption of Sector Erase, Suspend is complete. The device requires a minimum
32-Kbyte Block Erase, 64-Kbyte Block Erase, SPI of 500 µs between each Write Suspend command.
Quad Page Program, or Page Program operations in
order to erase, program or read data in another portion
of memory. The original operation can be continued
with the Write Resume command. This operation is
supported in both SQI and SPI protocols.
Only one write operation can be suspended at a time;
if an operation is already suspended, the device will
ignore the Write Suspend command. Write Suspend
during Chip Erase is ignored; Chip Erase is not a valid
command while a write is suspended.

SST26VF080A
5.23 Write Suspend During Sector 5.26 Read Security ID
Erase or Block Erase The Read Security ID operation is supported in both
Issuing a Write Suspend instruction during Sector SPI and SQI modes. To execute a Read Security ID
Erase or 32-Kbyte Block Erase or 64-Kbyte Block (SID) operation in SPI mode, the host drives CE# low,
Erase allows the host to program or read any sector sends the Read Security ID command cycle (88H), two
that was not being erased. The device will ignore any address cycles, and then one dummy cycle. To execute
programming commands pointing to the suspended a Read Security ID operation in SQI mode, the host
sector(s). Any attempt to read from the suspended sec- drives CE# low and then sends the Read Security ID
tor(s) will output unknown data because the Sector or command, two address cycles, and three dummy
32-Kbyte Block Erase or 64-Kbyte Block Erase will be cycles.
incomplete. After the dummy cycles, the device outputs data on the
To execute a Write Suspend operation, the host drives falling edge of the SCK signal, starting from the speci-
CE# low, sends the Write Suspend command cycle fied address location. The data output stream is contin-
(B0H), then drives CE# high. The Configuration uous through all SID addresses until terminated by a
register indicates that the erase has been suspended low-to-high transition on CE#. See Table 5-5 for the
by changing the WSE bit from ‘0’ to ‘1’, but the device Security ID address range.
will not accept another command until it is ready. To
determine when the device will accept a new 5.27 Program Security ID
command, poll the BUSY bit in the STATUS register or
wait TWS. The Program Security ID instruction programs one to
2032 bytes of data in the user-programmable, Security
ID space. This Security ID space is one-time-program-
5.24 Write Suspend During Page mable (OTP). The device ignores a Program Security
Programming or SPI Quad Page ID instruction pointing to an invalid or protected
Programming address, see Table 5-5. Prior to the program operation,
execute WREN.
Issuing a Write Suspend instruction during Page
Programming allows the host to erase or read any To execute a Program SID operation, the host drives
sector that is not being programmed. Erase commands CE# low, sends the Program Security ID command
pointing to the suspended sector(s) will be ignored. Any cycle (A5H), two address cycles, the data to be pro-
attempt to read from the suspended page will output grammed, then drives CE# high. The programmed data
unknown data because the program will be incomplete. must be between 1 to 256 bytes and in whole-byte
increments.
To execute a Write Suspend operation, the host drives
CE# low, sends the Write Suspend command cycle The device handles shifting of more than 256 bytes of
(B0H), then drives CE# high. The Configuration regis- data by maintaining the last 256 bytes of data as the
ter indicates that the programming has been sus- correct data to be programmed. If the target address for
pended by changing the WSP bit from ‘0’ to ‘1’, but the the Program Security ID instruction is not the beginning
device will not accept another command until it is ready. of the page boundary, and the number of data input
To determine when the device will accept a new com- exceeds or overlaps the end of the address of the page
mand, poll the BUSY bit in the STATUS register or wait boundary, the excess data inputs wrap around and will
TWS. be programmed at the start of that target page.
The Program Security ID operation is supported in both
5.25 Write Resume SPI and SQI mode. To determine the completion of the
internal, self-timed Program SID operation, poll the
Write Resume restarts a write command that was sus- BUSY bit in the software STATUS register, or wait
pended, and changes the suspend Status bit in the TPSID for the completion of the internal self-timed
Configuration register (WSE or WSP) back to ‘0’. Program Security ID operation.
To execute a Write Resume operation, the host drives
CE# low, sends the Write Resume command cycle
(30H), then drives CE# high. To determine if the inter-
nal, self-timed write operation is completed, poll the
BUSY bit in the STATUS register, or wait the specified
time TSE, TBE or TPP for Sector-Erase, Block-Erase, or
Page-Programming, respectively. The total write time
before suspend and after resume will not exceed the
uninterrupted write times TSE, TBE or TPP.

SST26VF080A
TABLE 5-5: PROGRAM SECURITY ID

Program Security ID Address Range
Unique ID Preprogrammed at Factory 0000-000FH
User-Programmable 0010H-07FFH
5.28 Lockout Security ID These commands function in both SPI and SQI modes.
The STATUS register may be read at any time, even
The Lockout Security ID instruction prevents any future during a write operation. When a write is in progress,
changes to the Security ID, and is supported in both poll the BUSY bit before sending any new commands
SPI and SQI modes. Prior to the operation, execute to assure that the new commands are properly
WREN. received by the device.
To execute a Lockout SID, the host drives CE# low, To read the STATUS or Configuration registers, the
sends the Lockout Security ID command cycle (85H), host drives CE# low, then sends the Read STATUS
then drives CE# high. Poll the BUSY bit in the software Register command cycle (05H) or the Read Configura-
STATUS register, or wait TPSID for the completion of the tion Register command (35H). A dummy cycle is
Lockout Security ID operation. required in SQI mode. Immediately after the command
cycle, the device outputs data on the falling edge of the
5.29 Read STATUS Register (RDSR) SCK signal. The data output stream continues until ter-
and Read Configuration Register minated by a low-to-high transition on CE#. See
(RDCR) Figures 5-30 and 5-31 for the instruction sequence.
The Read STATUS Register (RDSR) and Read Config-

uration Register (RDCR) commands output the con-
tents of the STATUS and Configuration registers.
FIGURE 5-30: READ STATUS REGISTER AND READ CONFIGURATION REGISTER SEQUENCE
(SQI)
CE#
MODE 3 0 2 4 6 8
SCK MODE 0
MSN LSN
SIO[3:0] C1 C0 X X H0 L0 H0 L0 H0 L0
Dummy STATUS ByteSTATUS Byte STATUS Byte
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 05H or 35H
FIGURE 5-31: READ STATUS REGISTER AND READ CONFIGURATION REGISTER SEQUENCE
(SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK MODE 0
SI 05 or 35H
MSB
High-Impedance
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB STATUS or Configuration
Register Out

SST26VF080A
5.30 Write STATUS Register (WRSR)
The Write STATUS Register (WRSR) command writes
new values to the STATUS register and Configuration
register. To execute a Write STATUS Register opera-
tion, the host drives CE# low, then sends the Write
STATUS Register command cycle (01H), and one or
two cycles of data, and then drives CE# high. The first
cycle of data points to the STATUS register, the second
points to the Configuration register. See Figures 5-32
and 5-33.
FIGURE 5-32: WRITE STATUS REGISTER SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5
SCK MODE 0
MSN LSN
SIO[3:0] C1 C0 H0 L0 H0 L0
Command STATUS Configura-
Byte tion
Byte
Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble, XX = “Don’t Care”, C[1:0] = 01H
FIGURE 5-33: WRITE STATUS REGISTER SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK MODE 0 MODE 0
STATUS Configuration
Register Register
SI 06 01 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB MSB
SO High-Impedance
Note: XX = “Don’t Care”

SST26VF080A
5.31 Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write
Enable Latch bit in the STATUS register to ‘1’, allowing
write operations to occur. The WREN instruction must be
executed prior to any of the following operations:
Sector Erase, 32-Kbyte Block Erase or 64-Kbyte Block
Erase, Chip Erase, Page Program, Program Security
ID, Lockout Security ID, Lock-Down Protection
Settings, SPI Quad Page program, and Write STATUS
register. To execute a Write Enable the host drives CE#
low then sends the Write Enable command cycle (06H)
then drives CE# high. See Figures 5-34 and 5-35 for
the WREN instruction sequence.
FIGURE 5-34: WRITE ENABLE SEQUENCE (SQI)
CE#
MODE 3 0 1
SCK MODE 0
SIO[3:0] 0 6
FIGURE 5-35: WRITE ENABLE SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 06
MSB
SO High-Impedance

SST26VF080A
5.32 Write Disable (WRDI)
The Write Disable (WRDI) instruction sets the Write
Enable Latch bit in the STATUS register to ‘0’, prevent-
ing write operations. The WRDI instruction is ignored
during any internal write operations. Any write opera-
tion started before executing WRDI will complete. Drive
CE# high before executing WRDI.
To execute a Write Disable, the host drives CE# low,
sends the Write Disable command cycle (04H), then
drives CE# high. See Figures 5-36 and 5-37.
FIGURE 5-36: WRITE DISABLE (WRDI) SEQUENCE (SQI)
CE#
MODE 3 0 1
SCK MODE 0
SIO[3:0] 0 4
FIGURE 5-37: WRITE DISABLE (WRDI) SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 04
MSB
SO High-Impedance

SST26VF080A
5.33 Lock-Down Protection Settings
(LDPS)
The Lock-Down Protection Settings instruction
prevents changes to the Block Protection bits (BP0,
BP1, BP2, BP3) of the STATUS register during device
operation. Lock-Down resets after power cycling or
hardware Reset; this allows the Block Protection
settings to be changed. Execute WREN before
initiating the Lock-Down Protection Settings
instruction. To execute a Lock-Down Protection
Settings command, the host drives CE# low, then
sends the Lock-Down Protection Settings command
cycle (8DH), then drive CE# high. Executing the LDPS
instruction will set the VLP bit in the Configuration
register.
FIGURE 5-38: LOCK-DOWN PROTECTION SETTINGS (SQI)
CE#
MODE 3 0 1
SCK MODE 0
SIO[3:0] C1 C0
Note: C[1:0] = 8DH
FIGURE 5-39: LOCK-DOWN PROTECTION SETTINGS (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 8D
SIO[3:1]

SST26VF080A
5.34 Deep Power-Down Enter Deep Power-Down mode by initiating the Deep
Power-Down (DPD) instruction (B9H) while driving CE#
The Deep Power-Down (DPD) instruction puts the low. CE# must be driven high before executing the DPD
device in the lowest power consumption mode – the instruction. After CE# is driven high, it requires a delay
Deep Power-Down mode. The Deep Power-Down of TDPD before the standby current ISB is reduced to
instruction is ignored during an internal write operation. deep power-down current IDPD. See Table 5-6 for Deep
While the device is in Deep Power-Down mode, all Power-Down timing. If the device is busy performing an
instructions will be ignored except for the Release internal erase or program operation, initiating a Deep
Deep Power-Down instruction. Power-Down instruction will not place the device in
Deep Power-Down mode. See Figures 5-40 and 5-41
for the DPD instruction sequence.
TABLE 5-6: DEEP POWER-DOWN

Symbol Parameter Min. Max. Units
TDPD CE# High to Deep Power-Down — 3 µs
TSBR CE# High to Standby Mode — 10 µs
FIGURE 5-40: DEEP POWER-DOWN (DPD) SEQUENCE – SQI MODE
CE# TDPD
MODE 3 0 1
SCK MODE 0
SIO[3:0] B 9
MSN LSN
Standby Mode Deep Power-Down Mode
Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble
FIGURE 5-41: DEEP POWER-DOWN (DPD) SEQUENCE – SPI MODE
CE#
TDPD
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI B9
MSB
SO High-Impedance
Standby Mode Deep Power-Down Mode

SST26VF080A
5.35 Release from Deep Power-Down To execute RDPD and read the Device ID, the host
and Read ID drives CE# low then sends the Deep Power-Down
command cycle (ABH), three dummy clock cycles, and
Release from Deep Power-Down (RDPD) and Read ID then drives CE# high. The device outputs the Device ID
instruction exits Deep Power-Down mode. To exit Deep on the falling edge of the SCK signal following the
Power-Down mode, execute the RDPD. During this dummy cycles. The data output stream is continuous
command, the host drives CE# low, then sends the until terminated by a low-to-high transition on CE, and
Deep Power-Down command cycle (ABH), and then will return to Standby mode and be ready for the next
drives CE# high. The device will return to Standby instruction after TSBR. See Figures 5-42 and 5-43 for
mode and be ready for the next instruction after TSBR. the command sequence.
FIGURE 5-42: RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE – SQI MODE
TSBR
CE#
MODE 3 0 1
SCK MODE 0
Op Code
SIO[3:0] C1 C0 X X X X X X D1 D0
MSN LSN Device ID
Deep Power-Down Mode Standby Mode
Note: C[1:0] = ABH
FIGURE 5-43: RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE – SPI MODE
TSBR
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 32 33 40
SCK MODE 0
Op Code
SIO[3:0] AB XX XX XX
Device ID
Deep Power-Down Mode Standby Mode

SST26VF080A
6.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (†)

Temperature under bias ..........................................................................................................................-55°C to +125°C
Storage temperature ...............................................................................................................................-65°C to +150°C
DC voltage on any pin to ground potential ...........................................................................................-0.5V to VDD+0.5V
Transient voltage (<20 ns) on any pin to ground potential ...................................................................-2.0V to VDD+2.0V
Package power dissipation capability (TA = 25°C)....................................................................................................1.0W
Surface mount solder reflow temperature .......................................................................................260°C for 10 seconds
Output short circuit current(1) ..................................................................................................................................50 mA
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 6-1: OPERATING RANGE 6.1 Power-Up Specifications

Range Ambient Temp. VDD
All functionalities and DC specifications are specified
Industrial -40°C to +85°C for a VDD ramp rate of greater than 1V per 100 ms
2.3V-3.6V
Extended(1) -40°C to +125°C (0V to 3.0V in less than 300 ms). See Table 6-3 and
Note 1: Maximum operating frequency for Figure 6-1 for more information.
Extended temperature is 80 MHz. When VDD drops from the operating voltage to below
the minimum VDD threshold at power-down, all opera-
tions are disabled and the device does not respond to
TABLE 6-2: AC CONDITIONS OF TEST(1) commands. Data corruption may result if a power-down
Input Rise/Fall Time Output Load occurs while a write registers, program, or erase oper-
3 ns CL = 30 pF ation is in progress. See Figure 6-2.
Note 1: See Figure 8-6.
TABLE 6-3: RECOMMENDED SYSTEM POWER-UP/POWER-DOWN TIMINGS

Symbol Parameter Minimum Maximum Units Condition
TPU-READ(1) VDD Minimum to Read Operation 100 — µs
TPU-WRITE(1) VDD Minimum to Write Operation 100 — µs
TPD(1) Power-Down Duration 100 — ms
VOFF VDD Off — 0.3 V 0V recommended
Note 1: This parameter is measured only for initial qualification and after a design or process change that could
affect this parameter.

SST26VF080A
FIGURE 6-1: POWER-UP TIMING DIAGRAM
VDD
VDD Max
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
VDD Min
TPU-READ
TPU-WRITE Device fully accessible
Time
FIGURE 6-2: POWER-DOWN AND VOLTAGE DROP DIAGRAM

VDD
VDD Max
No Device Access Allowed
VDD Min
TPU Device
Access
Allowed
VOFF
TPD
Time

SST26VF080A
7.0 DC CHARACTERISTICS
TABLE 7-1: DC OPERATING CHARACTERISTICS (VDD = 2.3V-3.6V)
Limits
Symbol Parameter Min. Typical Max. Unit Test Conditions
IDDR1 Read Current — 8 15 mA VDD = VDD Max,
CE# = 0.1 VDD/0.9 VDD@40 MHz,
SO = Open
IDDR2 Read Current — — 20 mA VDD = VDD Max,
CE# = 0.1 VDD/0.9 VDD@104 MHz,
SO = Open
IDDW Program and Erase Current — — 25 mA VDD Max
ISB1 Standby Current — 15 30 µA CE# =VDD, VIN=VDD or VSS
ISB2 Standby Current — — 50 µA CE# =VDD, VIN=VDD or VSS @125°C
IDPD1 Deep Power-Down Current — 8 20 µA CE# = VDD, VIN=VDD or VSS
IDPD2 Deep Power-Down Current — — 30 µA CE# = VDD, VIN=VDD or VSS@125°C
ILI Input Leakage Current — — 2 µA VIN = GND to VDD, VDD=VDD Max
ILO Output Leakage Current — — 2 µA VOUT = GND to VDD, VDD = VDD Max
VIL Input Low Voltage — — 0.8 V VDD = VDD Min
VIH Input High Voltage 0.7 VDD — — V VDD = VDD Max
VOL Output Low Voltage — — 0.2 V IOL = 100 µA, VDD = VDD Min
VOH Output High Voltage VDD-0.2 — — V IOH = -100 µA, VDD = VDD Min
TABLE 7-2: Capacitance (TA = 25°C, f = 1 MHz, Other Pins Open)

Parameter Description Test Condition Maximum
COUT(1) Output Pin Capacitance VOUT = 0V 8 pF
CIN(1) Input Capacitance VIN = 0V 6 pF
TABLE 7-3: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Unit Test Method
NEND(1) Endurance 100,000 Cycles JEDEC Standard A117 and AEC-Q100-005
TDR(1) Data Retention 100 Years JEDEC Standard A103 and AEC-Q100-005
ILTH(1) Latch Up 100 + IDD mA JEDEC Standard 78 and AEC-Q100-004
TABLE 7-4: WRITE TIMING PARAMETERS (VDD = 2.3V-3.6V)

Symbol Parameter Minimum Maximum Unit
TSE Sector Erase — 25 ms
TBE Block Erase — 25 ms
TSCE Chip Erase — 50 ms
TPP(1) Page Program — 1.5 ms
TPSID Program Security ID — 1.5 ms
TWS Write Suspend Latency — 25 µs
TCONFIG Configuration Register Write Latency — 25 ms
Note 1: Estimate for typical conditions less than 256 bytes: Programming Time (µs) = 55 + (3.75 x # of bytes).

SST26VF080A
8.0 AC CHARACTERISTICS
TABLE 8-1: AC OPERATING CHARACTERISTICS (VDD(1) = 2.3V-3.6V)

Limits - 40 MHz Limits - 80 MHz(2) Limits - 104 MHz
Symbol Parameter Units
Min. Max. Min. Max. Min. Max.
FCLK Serial Clock Frequency — 40 — 80 — 104 MHz

TCLK Serial Clock Period — 25 — 12.5 — 9.6 ns
TSCKH Serial Clock High Time 11 — 5.5 — 4.5 — ns
TSCKL Serial Clock Low Time 11 — 5.5 — 4.5 — ns
TSCKR(3) Serial Clock Rise Time (slew rate) 0.1 — 0.1 — 0.1 — V/ns
TSCKF(3) Serial Clock Fall Time (slew rate) 0.1 — 0.1 — 0.1 — V/ns
TCES(4) CE# Active Setup Time 8 — 5 — 5 — ns
TCEH(4) CE# Active Hold Time 8 — 5 — 5 — ns
TCHS(4) CE# Not Active Setup Time 8 — 5 — 5 — ns
TCHH(4) CE# Not Active Hold Time 8 — 5 — 5 — ns
TCPH CE# High Time 25 — 12.5 — 12 — ns
TCHZ CE# High-to-High Z Output — 19 — 12.5 — 12 ns
TCLZ SCK Low-to-Low Z Output 0 — 0 — 0 — ns
THLS HOLD# Low Setup Time 8 — 5 — 5 — ns
THHS HOLD# High Setup Time 8 — 5 — 5 — ns
THLH HOLD# Low Hold Time 8 — 5 — 5 — ns
THHH HOLD# High Hold Time 8 — 5 — 5 — ns
THZ HOLD# Low-to-High Z Output — 8 — 8 — 8 ns
TLZ HOLD# High-to-Low Z Output — 8 — 8 — 8 ns
TDS Data In Setup Time 3 — 3 — 3 — ns
TDH Data In Hold Time 4 — 4 — 4 — ns
TOH Output Hold from SCK Change 0 — 0 — 0 — ns
TV Output Valid from SCK — 8/5(5) — 8/5(5) — 8/5(5) ns
Note 1: Maximum operating frequency for 2.7V-3.6V is 104 MHz and for 2.3V-3.6V is 80 MHz.
2: Maximum frequency for 125°C is 80 MHz.
3: Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements.
4: Relative to SCK.
5: 30 pF/10 pF

SST26VF080A
FIGURE 8-1: HOLD TIMING DIAGRAM
CE#
THHH THLS THHS
SCK
THLH
THZ TLZ
SO
SI
HOLD#
FIGURE 8-2: SERIAL INPUT TIMING DIAGRAM
TCPH
CE#
TCHH TCES TCEH TCHS

TSCKF
SCK
TDS TDH
TSCKR
SIO[3:0] MSB LSB
FIGURE 8-3: SERIAL OUTPUT TIMING DIAGRAM
CE#
TSCKH TSCKL
SCK
TOH
TCLZ TCHZ
SIO[3:0] MSB LSB

TV

SST26VF080A
FIGURE 8-4: RESET TIMING DIAGRAM
TCPH
CE#
CLK
SIO[3:0] C1 C0 C3 C2
Note: C[1:0] = 66H; C[3:2] = 99H
TABLE 8-2: RESET TIMING PARAMETERS

TR(I) Parameter Minimum Maximum Units
TRECR Reset to Read (non-data operation) — 20 ns
TRECP Reset Recovery from Program or Suspend — 100 µs
TRECE Reset Recovery from Erase — 1 ms
TRST Reset Pulse Width (Hardware Reset) 100 — ns
TRHZ Reset to High Z Output — 105 ns
FIGURE 8-5: HARDWARE RESET TIMING DIAGRAM
CE#
TRECR
TRECP
TRECE
SCK
TRST
RST#
TRHZ
SO
SI

SST26VF080A
FIGURE 8-6: AC INPUT/OUTPUT REFERENCE WAVEFORMS
VIHT
VHT VHT
INPUT REFERENCE POINTS OUTPUT
VLT VLT
VILT
AC test inputs are driven at VIHT (0.9VDD) for a logic ‘1’ and VILT (0.1VDD) for a logic ‘0’. Measurement reference
points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10%  90%) are <3 ns.
Note: VHT - VHIGH Test

VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

SST26VF080A
9.0 PACKAGING INFORMATION
9.1 Package Marking
8-Lead SOIC (3.90 mm) Example
26F080A
26F016B
SM e3
SN2005
1503343
343
8-Lead WDFN (5x6 mm) Example
26F080A
MF e3
2005343
1st Line Marking Codes

Part Number
SOIC WDFN
SST26VF080A 26F080A 26F080A
Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

SST26VF080A
9.2 Packaging Diagrams
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A D
NOTE 5
N
E
2
E1
2
E1 E
NOTE 1 1 2
e NX b
B 0.25 C A–B D
NOTE 5
TOP VIEW
0.10 C
C A A2
SEATING
PLANE 8X
0.10 C
A1 SIDE VIEW
h
R0.13
h
R0.13
H 0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2

SST26VF080A
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Foot Angle 0° - 8°
Lead Thickness c 0.17 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2

SST26VF080A
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
SILK SCREEN
Y1
X1
E
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X8) X1 0.60
Contact Pad Length (X8) Y1 1.55
Notes:
Microchip Technology Drawing C04-2057-SN Rev B

SST26VF080A
8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN]
D A B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.15 C
1 2
2X
0.15 C
TOP VIEW
A1
C 0.10 C
SEATING A
PLANE
A3
SIDE VIEW 0.08 C
0.10 C A B
D2
e
1 2
0.10 C A B
NOTE 1
E2
K N
8Xb
0.10 C A B
SEE DETAIL A
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-210B Sheet 1 of 2

SST26VF080A
(DATUM A)
e/2
e
DETAIL A
Units MILLIMETERS
Number of Terminals N 8
Pitch e 1.27 BSC
Overall Height A 0.70 0.75 0.80
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.20 REF
Overall Width D 5.00 BSC
Exposed Pad Width D2 4.00 BSC
Overall Length E 6.00 BSC
Exposed Pad Length E2 3.40 BSC
Terminal Width b 0.35 0.42 0.48
Terminal Length L 0.50 0.60 0.70
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-210B Sheet 2 of 2

SST26VF080A
C
X2
X1
Y2
Y1
SILK SCREEN
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Contact Pitch E 1.27 BSC
Optional Center Pad Width X2 3.50
Optional Center Pad Length Y2 4.10
Contact Pad Spacing C 5.70
Contact Pad Width (X8) X1 0.45
Contact Pad Length (X8) Y1 1.10
Notes:
Microchip Technology Drawing C04-2210A

SST26VF080A
10.0 REVISION HISTORY
Revision B (February 2020)

Updated Table 7-1, Table 7-3 and PIS.
Revision A (June 2019)

Initial release of the document.

SST26VF080A
THE MICROCHIP WEBSITE CUSTOMER SUPPORT
Microchip provides online support via our website at Users of Microchip products can receive assistance
www.microchip.com. This website is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the website contains the following information:
• Field Application Engineer (FAE)
• Product Support – Data sheets and errata, appli-
• Technical Support
cation notes and sample programs, design
resources, user’s guides and hardware support Customers should contact their distributor, representa-
documents, latest software releases and archived tive or Field Application Engineer (FAE) for support.
software Local sales offices are also available to help custom-
• General Technical Support – Frequently Asked ers. A listing of sales offices and locations is included in
Questions (FAQ), technical support requests, the back of this document.
online discussion groups, Microchip consultant Technical support is available through the website
program member listing at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registra-
tion instructions.

SST26VF080A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) –XXX X /XX

Valid Combinations(2):
Device Tape and Reel Operating Temperature Package a) SST26VF080A-104I/SN
Indicator Frequency b) SST26VF080AT-104I/SN
c) SST26VF080A-104I/MF
d) SST26VF080AT-104I/MF
Device: SST26VF080A = 8 Mbit, 2.5V/3.0V, SQI Flash memory
WP#/Hold# pin enable at power-up
e) SST26VF080A-80E/SN
f) SST26VF080AT-80E/SN
Tape and Reel Blank = Standard packaging (tube or tray) g) SST26VF080A-80E/MF
Indicator: T = Tape and Reel(1) h) SST26VF080AT-80E/MF
Note 1: Tape and Reel identifier only appears in

Operating 104 = 104 MHz
the catalog part number description. This
Frequency 80 = 80 MHz
identifier is used for ordering purposes
and is not printed on the device package.
Check with your Microchip Sales Office
Temperature I = -40C to +85C (Industrial)
for package availability with the Tape and
Range: E = -40C to +125C (Extended)
Reel option.
2: Contact your Microchip sales office for

Package: SN = SOIC (3.90 mm Body), 8-lead
MF = WDFN (6 mm x 5 mm Body), 8-lead Automotive AEC-Q100 ordering informa-
tion. Valid automotive part numbers are
not listed on this page.

SST26VF080A
11.0
Appendix
TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 1 OF 13)
Bit
Address Data Comments
Address
SFDP Header
SFDP Header: 1st DWORD
00H A7:A0 53H
01H A15:A8 46H SFDP Signature
02H A23:A16 44H SFDP Signature = 50444653H
03H A31:A24 50H
nd
SFDP Header: 2 DWORD
04H A7:A0 06H SFDP Minor Revision Number
05H A15:A8 01H SFDP Major Revision Number
06H A23:A16 02H Number of Parameter Headers (NPH) = 3
07H A31:A24 FFH Unused. Contains FF and cannot be changed.
Parameter Headers
JEDEC Flash Parameter Header: 1st DWORD
Parameter ID LSB Number
When this field is set to 00H, it indicates a JEDEC-specified header. For
08H A7:A0 00H
vendor-specified headers, this field must be set to the vendor’s manufacturer
ID.
Parameter Table Minor Revision Number
Minor revisions are either clarifications or changes that add parameters in
09H A15:A8 06H
existing Reserved locations. Minor revisions do NOT change overall struc-
ture of SFDP. Minor revision starts at 00H.
Parameter Table Major Revision Number
Major revisions are changes that reorganize or add parameters to locations
0AH A23:A16 01H that are NOT currently Reserved. Major revisions would require code
(BIOS/firmware) or hardware change to get previously defined discoverable
parameters. Major revision starts at 01H.
Parameter Table Length
0BH A31:A24 10H
Number of DWORDs that are in the Parameter table.
JEDEC Flash Parameter Header: 2nd DWORD
0CH A7:A0 30H Parameter Table Pointer (PTP)
0DH A15:A8 00H A 24-bit address that specifies the start of this header’s Parameter table in
the SFDP structure. The address must be DWORD-aligned.
0EH A23:A16 00H
0FH A31:A24 FFH Parameter ID MSB Number
JEDEC Sector Map Parameter Header: 3rd DWORD
Parameter ID LSB Number
10H A7:A0 81H
Sector Map Function specific table is assigned 81H.
Parameter Table Minor Revision Number
Minor revisions are either clarifications or changes that add parameters in
11H A15:A8 00H
existing Reserved locations. Minor revisions do NOT change overall struc-
ture of SFDP. Minor revision starts at 00H.
Parameter Table Major Revision Number
Major revisions are changes that reorganize or add parameters to locations
12H A23:A16 01H that are NOT currently Reserved. Major revisions would require code
(BIOS/firmware) or hardware change to get previously defined discoverable
parameters. Major revision starts at 01H.

SST26VF080A
Bit
Address
Parameter Table Length
13H A31:A24 02H
Number of DWORDs that are in the Parameter table.
JEDEC Sector Map Parameter Header: 4th DWORD
14H A7:A0 00H Parameter Table Pointer (PTP)
15H A15:A8 01H This 24-bit address specifies the start of this header’s Parameter table in the
SFDP structure. The address must be DWORD-aligned.
16H A23:A16 00H
17H A31:A24 FFH Parameter ID MSB Number
Microchip (Vendor) Parameter Header: 5th DWORD
ID Number
18H A7:A0 BFH
Manufacture ID (vendor specified header)
19H A15:A8 00H Parameter Table Minor Revision Number
1AH A23:A16 01H Parameter Table Major Revision Number, Revision 1.0
1BH A31:A24 13H Parameter Table Length, 19 Double Words
Microchip (Vendor) Parameter Header: 6th DWORD
1CH A7:A0 00H Parameter Table Pointer (PTP)
1DH A15:A8 02H This 24-bit address specifies the start of this header’s Parameter table in the
SFDP structure. The address must be DWORD-aligned.
1EH A23:A16 00H
1FH A31:A24 01H Used to indicate bank number (vendor specific).
JEDEC Flash Parameter Table
JEDEC Flash Parameter Table: 1st DWORD
Block/Sector Erase Sizes
00: Reserved
A1:A0 01: 4-Kbyte Erase
10: Reserved
11: Use this setting only if the 4-Kbyte erase is unavailable.
Write Granularity
0: Single-byte programmable devices or buffer programmable devices with
A2 buffer is less than 64 bytes (32 words).
1: For buffer programmable devices when the buffer size is 64 bytes
30H FDH (32 words) or larger.
Volatile STATUS Register
0: Target Flash has nonvolatile STATUS bit. Write/Erase commands do not
A3
require STATUS register to be written on every power-on.
1: Target Flash has volatile STATUS bits.
Write Enable Opcode Select for Writing to Volatile STATUS Register
A4 0: 0x50. Enables a STATUS register write when bit 3 is set to ‘1’.
1: 0x06 Enables a STATUS register write when bit 3 (A3) is set to ‘1’.
A7:A5 Unused. Contains 111b and cannot be changed.
31H A15:A8 20H 4-Kbyte Erase Opcode

SST26VF080A
Bit
Address
Supports (1-1-2) Fast Read
A16 0: (1-1-2) Fast Read NOT supported
1: (1-1-2) Fast Read supported
Address Bytes
Number of bytes used in addressing Flash array read, write and erase
00: 3-Byte only addressing
A18:A17 01: 3- or 4-Byte addressing (e.g., defaults to 3-Byte mode; enters 4-Byte
mode on command)
10: 4-Byte only addressing
11: Reserved
Supports Double Transfer Rate (DTR) Clocking
Indicates the device supports some type of double transfer rate clocking.
A19
0: DTR NOT supported
1: DTR Clocking supported
32H F1H
Device supports single input opcode, dual input address, and dual output
A20 data Fast Read.
0: (1-2-2) Fast Read NOT supported
Device supports single input opcode, quad input address, and quad output
A21 data Fast Read
Device supports single input opcode & address and quad output data Fast
A22 Read.
A23 Unused. Contains ‘1’ cannot be changed.
33H A31:A24 FFH Unused. Contains FF cannot be changed.
JEDEC Flash Parameter Table: 2nd DWORD
34H A7:A0 FFH
35H A15:A8 FFH Flash Memory Density
36H A23:A16 7FH SST26VF080A = 007FFFFFH
37H A31:A24 00H
JEDEC Flash Parameter Table: 3rd DWORD
(1-4-4) Fast Read Number of Wait states (dummy clocks) needed before
valid output
A4:A0
00100b: 4 dummy clocks (16 dummy bits) are needed with a Quad Input
Address Phase instruction.
38H 44H
Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode
Bits
A7:A5
010b: 2 dummy clocks (8 mode bits) are needed with a single input opcode,
quad input address and quad output data Fast Read instruction.
(1-4-4) Fast Read Opcode
39H A15:A8 EBH Opcode for single input opcode, quad input address and quad output data
Fast Read instruction.

SST26VF080A
Bit
Address
valid output
A20:A16
01000b: 8 dummy bits are needed with a single input opcode & address and
3AH 08H quad output data Fast Read instruction.
(1-1-4) Fast Read Number of Mode Bits
A23:A21 000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read instruction.
3BH A31:A24 6BH Opcode for single input opcode & address and quad output data Fast Read
instruction.
JEDEC Flash Parameter Table: 4th DWORD
valid output
A4:A0
01000b: 8 dummy clocks are needed with a single input opcode, address
3CH 08H and dual output data Fast Read instruction.
A7:A5 000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read instruction.
3DH A15:A8 3BH Opcode for single input opcode & address and dual output data Fast Read
instruction.
A20:A16 valid output
3EH 80H 00000b: 0 clocks of dummy cycle.
(1-2-2) Fast Read Number of Mode Bits (in clocks)
A23:A21
100b: 4 clocks of mode bits are needed.
3FH A31:A24 BBH Opcode for single input opcode, dual input address, and dual output data
Fast Read instruction.
Device supports dual input opcode & address and dual output data Fast
A0 Read.
A3:A1 Reserved. Bits default to all 1’s.
40H FEH
Device supports Quad input opcode & address and quad output data Fast
A4 Read.
41H A15:A8 FFH Reserved. Bits default to all 1’s.

SST26VF080A
Bit
Address
A20:A16 valid output
46H 00H 00000b: No dummy bit is needed
A23:A21
000b: No mode bits are needed
47H A31:A24 FFH Opcode for dual input opcode & address and dual output data Fast Read (not
supported).
valid output
A20:A16
00100b: 4 clocks dummy are needed with a quad input opcode & address
4AH 44H and quad output data Fast Read instruction.
A23:A21 010b: 2 clocks mode bits are needed with a quad input opcode & address
and quad output data Fast Read instruction.
4BH A31:A24 0BH
Opcode for quad input opcode/address, quad output data Fast Read.
Sector Type 1 Size
4CH A7:A0 0CH
4-Kbyte, Sector/Block size = 2N bytes
Sector Type 1 Opcode
4DH A15:A8 20H
Opcode used to erase the number of bytes specified by Sector Type 1 Size.
Sector Type 2 Size
4EH A23:A16 0FH
4FH A31:A24 D8H
Sector Type 3 Size
50H A7:A0 10H
51H A15:A8 D8H
Sector Type 4 Size
52H A23:A16 00H
53H A31:A24 00H
Multiplier from typical erase time to maximum erase time.
Maximum time = 2*(count +1)*Typical erase time
A3:A0
Count = 0
A3:A0 = 0000b
54H 20H Erase Type 1 Erase, Typical time

Typical time = (count+1)*units
1 ms to 32 ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s
A7:A4
10:9 units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s)
A8:A4 count = 18 = 10010b
A10:A9 unit = 1 ms = 00b

SST26VF080A
Bit
Address
A10:A8 A10:A8 = 001b
Erase Type 2 Erase, Typical time
55H 91H 1 ms to 32 ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s
A15:A11
A15:A11 count = 18 = 10010b
A17:A16 unit = 1 ms = 00b
A17:A16 A17:A16 = 00b
A23:A18
A22:A18 count = 18 = 10010b
A24:A23 unit = 1ms = 00b
A24 A24 = 0b
A31:A25
A29:A25 count = 18 = 10010b
A31:A30 unit = 1 ms = 00b
Multiplier from typical program time to maximum program time
Maximum time = 2*(count +1)*Typical program time
A3:A0
Count = 0
A3:A0 = 0000b
58H 80H
Page Size
Page size = 2^N bytes
A7:A4
N=8
A7:A4 = 1000b
Page Program Typical time,
Program time = (count+1)*units
A31:A8 13 units (0b: 8 µs, 1b: 64 µs)
A12:A8 count = 11 = 01111b
A13 unit = 64 µs = 1b
59H 6FH
Byte Program Typical time, first byte
A15:A14 18 units (0b: 1 µs, 1b: 8 µs)
A17:A14 count = 5 = 0101b
A18 = 8 µs = 1b
A18:A16 A18:A16 = 101b
Byte Program Typical time, additional byte
5AH 1DH Typical time = (count+1)*units
A23:A19 23 units (0b: 1 µs, 1b: 8 µs)
A22:A19 count = 0011b
A23 = 1 µs = 0b

SST26VF080A
Bit
Address
Chip Erase Typical time
A30:A24 16 ms to 512 ms, 256 ms to 8192 ms, 4s to 128s, 64s to 2048s
5AH 81H A28:A24 count = 1 = 00001b
A30:A29 units = 16 ms = 00b
Reserved
A31
A31 = 1b
Prohibited Operations During Program Suspend
xxx0b: May not initiate a new erase anywhere
xxx1b: May not initiate a new erase in the program suspended page
size
xx0xb: May not initiate a new page program anywhere
A3:A0 xx1xb: May not initiate a new page program in program suspended page
size
x0xxb: Refer to the data sheet
x1xxb: May not initiate a read in the program suspended page size
0xxxb: Additional erase or program restrictions apply
5CH EDH 1xxxb: The erase and program restrictions in bits 1:0 are sufficient
Prohibited Operation During Erase Suspend
xxx0b: May not initiate a new erase anywhere
xxx1b: May not initiate a new erase in the erase suspended page size
xx0xb: May not initiate a new page program anywhere
xx1xb: May not initiate a new page program in erase suspended erase
A7:A4
type size
x0xxb: Refer to the data sheet
x1xxb: May not initiate a read in the erase suspended page size
0xxxb: Additional erase or program restrictions apply
1xxxb: The erase and program restrictions in bits 5:4 are sufficient
A8 Reserved = 1b
Program Resume to Suspend Interval
The device requires this typical amount of time to make progress on the
program operation before allowing another suspend.
A12:A9
Interval = 500 µs
Program resume to suspend interval = (count+1)*64 µs
A12:A9 = 7 = 0111b
5DH 0FH Suspend in-progress program max latency
Maximum time required by the Flash device to suspend an in-progress
program and be ready to accept another command which accesses the
Flash array.
A15:A13 Max. latency = 25 µs
program max. latency =(count+1)*units
units (00b: 128 ns, 01b: 1 µs, 10b: 8 µs, 11b: 64 µs)
A17:A13 = count = 24 = 11000b
A19:A18 = 1 µs = 01b
A19:A16 0111b
Erase Resume to Suspend Interval
The device requires this typical amount of time to make progress on the
5EH 77H erase operation before allowing another suspend.
A23:A20
Interval = 500 µs
Erase resume to suspend interval = (count+1)*64 µs
A23:A20 = 7 = 0111b

SST26VF080A
Bit
Address
Suspend in-progress erase max. latency
Maximum time required by the Flash device to suspend an in-progress erase
and be ready to accept another command which accesses the Flash array.
Max. latency = 25 µs
A30:A24
Erase max. latency = (count+1)*units
5FH 38H units (00b: 128 ns, 01b: 1µs, 10b: 8 µs, 11b: 64 µs)
A28:A24= count = 24 = 11000b
A30:A29 = 1 µs = 01b
Suspend/Resume supported
A31 0: supported
1: not supported
60H A7:A0 30H Program Resume Instruction
61H A15:A8 B0H Program Suspend Instruction
62H A23:A16 30H Resume Instruction
63H A31:A24 B0H Suspend Instruction
A1:A0 Reserved = 11b
64H F7H STATUS Register Polling Device Busy

A7:A2 111101b: Use of legacy polling is supported by reading the STATUS register
with 05h instruction and checking WIP bit [0] (0 = ready, 1 = busy)
Exit Deep Power-Down to next operation delay – 10 µs
Delay = (count+1)*unit
A14:A8
A12:A8 = count = 9 = 01001b
65H A9H A14:A13 units = 01b = 1 µs
Exit Power-Down Instruction – ABH= 10101011b
A15
A15 = 1b
A22:A16 A22:A16 = 1010101b
66H D5H Enter Power-Down Instruction – B9H = 10111001b
A23
A23 = 1b
A30:A24 A30:A24 = 1011100
67H 5CH Deep Power-Down Supported

A31 0: supported
1: not supported
4-4-4 mode disable sequences
A3:A0 Xxx1b: issue FF instruction
68H 29H 1xxxb: issue the Soft Reset 66/99 sequence
4-4-4 mode enable sequences
A7:A4
X_xx1xb: issue instruction 38H
4-4-4 mode enable sequences
A8
A8 = 0
0-4-4 mode supported
A9 0: not supported
69H C2H
1: supported
0-4-4 Mode Exit Method
A15:A10 X1_xxxx: Mode Bit[7:0] Not = AXh
1x_xxxx: Reserved = 1

SST26VF080A
Bit
Address
0-4-4 Mode Entry Method
A19:A16 X1xxb: M[7:0] = AXh
1xxxb: Reserved = 1
6AH 5CH Quad Enable Requirements (QER)
A22:A20
101b: Quad Enable is bit 1 of the Configuration register.
HOLD and Reset Disable
A23
0: feature is not supported
6BH A31:A24 FFH Reserved bits = 0xFF
Volatile or Nonvolatile Register and Write Enable Instructions for STATUS
Register 1
Xx1_xxxxb: STATUS Register 1 contains a mix of volatile and nonvolatile
A6:A0
6C F0H bits. The 06h instruction is used to enable writing to the register.
X1x_xxxxb: Reserved = 1
1xx_xxxxb: Reserved = 1
A7 Reserved =1b
Soft Reset and Rescue Sequence Support
X1_xxxxb: Reset Enable instruction 66h is issued followed by Reset
A13:A8
instruction 99h.
6D 30H 1x_xxxxb: exit 0-4-4 mode is required prior to other Reset sequences.
Exit 4-Byte Addressing
A15:A14
Not supported
Exit 4-Byte Addressing
Not supported
6E A23:A16 C0H
A21:A14 = 00000000b
A23 and A22 are Reserved bits which are = 1
Enter 4-Byte Addressing
6F A31:A24 80H Not supported
1xxx_xxxx: Reserved = 1
JEDEC Sector Map Parameter Table
A7:A2 = Reserved = 111111b
100H A7:A0 FFH A1 = Descriptor Type = Map = 1b
A0 = Last map = 1b
101H A15:A8 00H Configuration ID = 00h
102H A23:A16 00H Region Count = 1 Region
103H A31:A24 FFH Reserved = FFh
104H A7:A0 F7H Region 0 supports 4-Kbyte erase, 32-Kbyte erase and 64-Kbyte erase
A3:A0 = 0111b
A7:A4 = Reserved = 1111b
105H A15:A8 FFH Region 0 Size
For 8 Mbit device

1 Mbyte
Count = 1 Mbyte/256 bytes = 4096
Value = count -1 = 4095
A31:A8 = 000FFFh
106H A23:A16 0FH
107H A31:A24 00H

SST26VF080A
Bit
Address
SST26VF080A (Vendor) Parameter Table
SST26VF080A Identification
200H A7:A0 BFH Manufacturer ID
201H A15:A8 26H Memory Type
Device ID
202H A23:A16 18H
SST26VF080A = 18H
SST26VF080A Interface
Interfaces Supported
000: SPI only
001: Power-up default is SPI; Quad can be enabled/disabled
010: Reserved
A2:A0
●
●
●
111: Reserved
Supports Enable Quad
204H A3 B9H 0: not supported
1: supported
Supports Hold#/RST# Function
000: Hold#
A6:A4 001: RST#
010: HOLD/RST#
011: I/O when in SQI(4-4-4), 1-4-4 or 1-1-4 Read
Supports Software Reset
A7 0: not supported
1: supported
Supports Quad Reset
A8 0: not supported
1: supported
Byte-Program or Page-Program (256 Bytes)
A13:A11 011: Byte Program/Page Program in SPI and Quad Page Program once
205H DFH Quad is enabled
Program-Erase Suspend Supported
A14 0: Not Supported
1: Program/Erase Suspend Supported
Deep Power-Down Mode Supported
A15 0: Not Supported
1: Deep Power-Down Mode Supported

SST26VF080A
Bit
Address
OTP Capable (Security ID) Supported
A16 0: not supported
1: supported
Supports Block Group Protect
1: supported
Supports Independent Block Protect
206H F3H
1: supported
Supports Independent Nonvolatile Lock (Block or Sector becomes
OTP)
A19
0: not supported
1: supported
208H A7:A0 30H VDD Minimum Supply Voltage
209H A15:A8 F2H 2.30V (F230)
20AH A23:A16 60H VDD Maximum Supply Voltage
20BH A31:A24 F3H 3.60V (F360H)
Typical Time-out for Byte Program: 50 µs
20CH A7:A0 32H Typical time-out for Byte Program is in µs. Represented by conversion of the
actual time from the decimal to hexadecimal number.
20DH A15:A8 FFH Reserved. Bits default to all 1’s.
20EH A23:A16 0AH Typical Time-out for Page Program: 1.0 ms (xxH*(0.1 ms)
Typical Time-out for Sector Erase/Block Erase: 18 ms
20FH A31:A24 12H Typical time-out for Sector/Block-Erase is in ms. Represented by conversion
of the actual time from the decimal to hexadecimal number.
Typical Time-out for Chip Erase: 35 ms
210H A7:A0 23H Typical time-out for Chip Erase is in ms. Represented by conversion of the
Maximum Time-out for Byte Program: 70 µs
211H A15:A8 46H Typical time-out for Byte Program is in µs. Represented by conversion of the
Maximum Time-out for Page Program: 1.5 ms
213H A31:A24 0FH
Typical time-out for Page Program in xxH*(0.1 ms) ms
Maximum Time-out for Sector Erase/Block Erase: 25 ms
214H A7:A0 19H
Maximum time-out for Sector/Block Erase in ms
Maximum Time-out for Chip Erase: 50 ms.
215H A15:A8 32H
Maximum time-out for Chip Erase in ms.
Maximum Time-out for Program Security ID: 1.5 ms
216H A23:A16 0FH
Maximum time-out for Program Security ID in xxH*(0.1 ms) ms
Maximum Time-out for Write Protection Enable Latency: 25 ms
Maximum time-out for Write Protection Enable Latency is in ms. Repre-
217H A31:A24 19H
sented by conversion of the actual time from the decimal to hexadecimal
number.
Maximum Time-out for Write Suspend Latency: 25 µs
218H A7:A0 19H Maximum time-out for Write Suspend Latency is in µs. Represented by con-
version of the actual time from the decimal to hexadecimal number.

SST26VF080A
Bit
Address
Maximum Time to Deep Power-Down
219H A15:A8 03H
3 µs = 03H
Maximum Time-out from Deep Power-Down mode to Standby mode
21AH A23:A16 0AH
10 µs = 0AH
21BH A31:A24 FFH Reserved. Bits default to all 1’s.
21CH A7:A0 FFH Reserved. Bits default to all 1’s.
21DH A15:A8 FFH Reserved. Bits default to all 1’s.
21EH A23:A16 FFH Reserved. Bits default to all 1’s.
21FH A31:A24 FFH Reserved. Bits default to all 1’s.
Supported Instructions
220H A7:A0 00H No Operation
221H A15:A8 66H Reset Enable
222H A23:A16 99H Reset Memory
223H A31:A24 38H Enable Quad I/O
224H A7:A0 FFH Reset Quad I/O
225H A15:A8 05H Read STATUS Register
226H A23:A16 01H Write STATUS Register
227H A31:A24 35H Read Configuration Register
228H A7:A0 06H Write Enable
229H A15:A8 04H Write Disable
22AH A23:A16 02H Byte Program or Page Program
22BH A31:A24 32H SPI Quad Page Program
22CH A7:A0 B0H Suspends Program/Erase
22DH A15:A8 30H Resumes Program/Erase
22EH A23:A16 FFH Reserved
22FH A31:A24 FFH Reserved
230H A7:A0 FFH Reserved
233H A31:A24 88H Read Security ID
234H A7:A0 A5H Program User Security ID Area
235H A15:A8 85H Lockout Security ID Programming
236H A23:A16 C0H Set Burst Length
237H A31:A24 9FH JEDEC-ID
238H A7:A0 AFH Quad J-ID
239H A15:A8 5AH SFDP
23AH A23:A16 B9H Deep Power-Down Mode
23BH A31:A24 ABH Release Deep Power-Down Mode
(1-4-4) SPI nB Burst with Wrap Number of Wait states (dummy clocks)
A4:A0 needed before valid output
23CH 06H 00110b: 6 clocks of dummy cycle
(1-4-4) SPI nB Burst with Wrap Number of Mode Bits
A7:A5
000b: Set Mode bits are not supported
23DH A15:A8 ECH (1-4-4) SPI nB Burst with Wrap Opcode

SST26VF080A
Bit
Address
(4-4-4) SQI nB Burst with Wrap Number of Wait states (dummy clocks)
A20:A16 needed before valid output
23EH 06H 00110b: 6 clocks of dummy cycle
A23:A21 000b: Set Mode bits are not supported
23FH A31:A24 0CH (4-4-4) SQI nB Burst with Wrap Opcode
(1-1-1) Read Memory Number of Wait states (dummy clocks) needed
A4:A0 before valid output
240H 00H 00000b: Wait states/dummy clocks are not supported
(1-1-1) Read Memory Number of Mode Bits
A7:A5
000b: Mode bits are not supported
241H A15:A8 03H (1-1-1) Read Memory Opcode
(1-1-1) Read Memory at Higher Speed Number of Wait states (dummy
A20:A16 clocks) needed before valid output
242H 08H 01000: 8 clocks (8 bits) of dummy cycle
(1-1-1) Read Memory at Higher Speed Number of Mode Bits
A23:A21
000b: Mode bits are not supported
243H A31:A24 0BH (1-1-1) Read Memory at Higher Speed Opcode
248H A7:A0 FFH Security ID size in bytes
Example: If the size is 2 Kbytes, this field would be 07FFH
Security ID Range
249H A15:A8 07H Unique ID 0000H-000FH
(preprogrammed at factory)
User-programmable 0010H-07FFH
24AH A23:A16 FFH Reserved. Bits default to all 1’s.

24BH A31:A24 FFH Reserved. Bits default to all 1’s.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec,
and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in
FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries.
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company,
the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019-2020, Microchip Technology Incorporated, All Rights

Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality. ISBN: 978-1-5224-5652-0

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05/14/19
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SST26VF080A-80E/MF SST26VF080A-80E/SN SST26VF080AT-104I/MF SST26VF080AT-104I/SN
SST26VF080AT-80E/MF SST26VF080AT-80E/SN SST26VF080A-104I/MF SST26VF080A-104I/SN

SST26VF080A: 2.5V/3.0V 8-Mbit Serial Quad I/O™ (SQI™) Flash Memory

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SST26VF080A

2.5V/3.0V 8-Mbit Serial Quad I/O™ (SQI™) Flash Memory

 2019-2020 Microchip Technology Inc. DS20006203B-page 1

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

 2019-2020 Microchip Technology Inc. DS20006203B-page 2

FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM

WP# HOLD# SCK CE# SIO [3:0] RESET#

 2019-2020 Microchip Technology Inc. DS20006203B-page 3

FIGURE 2-1: PIN DESCRIPTIONS

CE# 1 8 VDD CE# 1 8 VDD

SO/SIO1 2 7 RESET#/HOLD#/SIO3 SO/SIO1 2 7 RESET#/HOLD#/SIO3

WP#/SIO2 3 6 SCK WP#/SIO2 3 6 SCK

Vss 4 5 SI/SIO0 Vss 4 5 SI/SIO0

TABLE 2-1: PIN DESCRIPTION

 2019-2020 Microchip Technology Inc. DS20006203B-page 4

FIGURE 4-1: SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

FIGURE 4-2: SQI SERIAL QUAD I/O PROTOCOL

 2019-2020 Microchip Technology Inc. DS20006203B-page 5

TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES

 2019-2020 Microchip Technology Inc. DS20006203B-page 6

FIGURE 4-3: HOLD CONDITION WAVEFORM

Active Hold Active Hold Active

4.5 Reset Operation 4.5.1 HARDWARE RESET OPERATION

 2019-2020 Microchip Technology Inc. DS20006203B-page 7

FIGURE 4-4: PERFORMING SOFTWARE RESET DURING READ

Device requires Software Reset

Was the previous Issue either a Reset Quad I/O command

Issue Software Reset command (0x66

 2019-2020 Microchip Technology Inc. DS20006203B-page 8

TABLE 4-2: REGISTER SETTINGS AFTER HARDWARE AND SOFTWARE RESET

4.6 STATUS Register

TABLE 4-3: SOFTWARE STATUS REGISTER

 2019-2020 Microchip Technology Inc. DS20006203B-page 9

TABLE 4-4: SOFTWARE STATUS REGISTER BLOCK PROTECTION

 2019-2020 Microchip Technology Inc. DS20006203B-page 10

TABLE 4-5: CONFIGURATION REGISTER

4.7.1 I/O CONFIGURATION (IOC) 4.7.2 VOLATILE LOCK PROTECTION

 2019-2020 Microchip Technology Inc. DS20006203B-page 11

4.7.5 WRITE SUSPEND PROGRAM

4.7.6 RESET/HOLD ENABLE (RSTHLD)

4.7.7 WRITE-PROTECT ENABLE (WPEN)

 2019-2020 Microchip Technology Inc. DS20006203B-page 12

TABLE 5-1: DEVICE OPERATION INSTRUCTIONS

 2019-2020 Microchip Technology Inc. DS20006203B-page 13

 2019-2020 Microchip Technology Inc. DS20006203B-page 14

 2019-2020 Microchip Technology Inc. DS20006203B-page 15

Note: C[1:0] = 66H; C[3:2] = 99H

FIGURE 5-2: READ SEQUENCE (SPI)

SI 03 ADD. ADD. ADD.

 2019-2020 Microchip Technology Inc. DS20006203B-page 16

FIGURE 5-3: ENABLE QUAD I/O SEQUENCE

Note: SIO[3:1] must be driven VIH.

FIGURE 5-4: RESET QUAD I/O SEQUENCE (SPI)

Note: SIO[3:1] must be driven VIH.

 2019-2020 Microchip Technology Inc. DS20006203B-page 17

5.6 High-Speed Read Initiate High-Speed Read by executing an 8-bit

FIGURE 5-6: HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)