25WQ020 040
25WQ020 040
IS25WQ040
IS25WQ020
4M/2M-BIT
1.8V QUAD SERIAL FLASH
MEMORY WITH
104MHZ MULTI I/O SPI
DATA SHEET
FEATURES
Industry Standard Serial Interface Low Power with Wide Temp. Ranges
- IS25WQ040: 4M-bit/ 512K-byte - Single 1.65V to 1.95V Voltage Supply
- IS25WQ020: 2M-bit/ 256K-byte - 8 mA Active Read Current (typ)
- 256-bytes per Programmable Page Standard - 15 µA Standby Current (typ.)
- Standard SPI/Dual/Quad Multi-I/O SPI - 2 µA Deep Power Down (typ.)
- Temp Grades:
High Performance Serial Flash (SPI) Extended: -40°C to +105°C
GENERAL DESCRIPTION
The IS25WQ040/020 (4M/2Mbit) Serial Flash memory offers a storage solution with flexibility and performance in a
simplified pin count package. ISSI’s “Industry Standard Serial Interface” is for systems that have limited space, pins,
and power. The IS25WQ040/020 is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial
Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also serve as multi-function I/O pins in Dual
and Quad modes (see pin descriptions). The IS25xQ series of Flash is ideal for code shadowing to RAM, execute in
place (XIP) operations, and storing non-volatile data.
The memory array is organized into programmable pages of 256-bytes each. The IS25WQ040/020 supports page
program mode where 1 to 256 bytes of data can be programmed into the memory with one command. Pages can be
erased in groups of 4K-byte sectors, 32K-byte blocks, 64K-byte blocks, and/or the entire chip. The uniform sectors and
blocks allow greater flexibility for a variety of applications requiring solid data retention.
The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad output (SPI), and Dual/Quad I/O (SPI).
Clock frequencies of up to 104MHz for all read modes allow for equivalent clock rates of up to 416MHz (104MHz x 4)
allowing up to 52MBytes/S of throughput. These transfer rates can outperform 16-bit Parallel Flash memories allowing
for efficient memory access for a XIP (execute in place) operation. The IS25WQ040/020 is manufactured using industry
leading non-volatile memory technology and offered in industry standard lead-free packages. See Ordering Information
for the density and package combinations available.
Note1: 100,000 Continuous Chip and Block cycling, 100,000 Continuous Sector cycling.
FEATURES .......................................................................................................................................................... 2
GENERAL DESCRIPTION .................................................................................................................................. 2
1. PIN CONFIGURATION ................................................................................................................................. 5
2. PIN DESCRIPTIONS .................................................................................................................................... 6
3. BLOCK DIAGRAM ........................................................................................................................................ 7
4. SPI MODES DESCRIPTION ........................................................................................................................ 8
5. SYSTEM CONFIGURATION ...................................................................................................................... 10
5.1 BLOCK/SECTOR ADDRESSES .......................................................................................................... 11
6. REGISTERS ............................................................................................................................................... 12
6.1. STATUS REGISTER ........................................................................................................................... 12
6.2. FUNCTION REGISTER ....................................................................................................................... 15
7. PROTECTION MODE................................................................................................................................. 16
7.1 HARDWARE WRITE PROTECTION.................................................................................................... 16
7.2 SOFTWARE WRITE PROTECTION .................................................................................................... 16
8. DEVICE OPERATION ................................................................................................................................ 17
8.1 READ DATA OPERATION (RD, 03h) .................................................................................................. 18
8.2 FAST READ DATA OPERATION (FR, 0Bh) ........................................................................................ 20
8.3 HOLD OPERATION .............................................................................................................................. 21
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ........................................................................... 21
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) .................................................................. 24
8.6 FAST READ QUAD OUTPUT (FRQO, 6Bh) ........................................................................................ 26
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh) .......................................................................... 28
8.8 PAGE PROGRAM OPERATION (PP, 02h) .......................................................................................... 31
8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h) ............................................................... 32
8.10 ERASE OPERATION ......................................................................................................................... 33
8.11 SECTOR ERASE OPERATION (SER, D7h/20h) ............................................................................... 33
8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................ 34
8.13 CHIP ERASE OPERATION (CER, C7h/60h) ..................................................................................... 35
8.14 WRITE ENABLE OPERATION (WREN, 06h) .................................................................................... 36
8.15 WRITE DISABLE OPERATION (WRDI, 04h) ..................................................................................... 36
8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ................................................................... 37
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................. 37
8.18 READ FUNCTION REGISTER OPERATION (RDFR, 07h) ............................................................... 38
8.19 PROGRAM/ERASE SUSPEND & RESUME ...................................................................................... 39
8.20 DEEP POWER DOWN (DP, B9h) ...................................................................................................... 41
8.21 RELEASE DEEP POWER DOWN (RDPD, ABh) ............................................................................... 42
8.22 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................ 43
CE# 1 8 Vcc
CE# 1 8 Vcc
SO (IO1) 2 7 HOLD# (IO3)
SO (IO1) 2 7 HOLD# (IO3)
GND 4 5 SI (IO0)
GND 4 5 SI (IO0)
CE# 1 8 Vcc
GND 4 5 SI (IO0)
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard
SPI instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
SI (IO0), Standard SPI also uses the unidirectional SO (Serial Output) to read data or status
SO (IO1) INPUT/OUTPUT from the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written in conjunction with the SRWD bit. When the SRWD is set to “1” and
the WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0)
WP# (IO2) INPUT/OUTPUT are write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the
Status Register is not write-protected regardless of WP# state.
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
SCK INPUT Serial Data Clock: Synchronized Clock for input and output timing operations.
NC Unused NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
SCK
WP#
(IO2) Y-Decoder
SI
(IO0)
SO
(IO1)
HOLD#
X-Decoder
(IO3)
Memory Array
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the
serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer
to Figure 4.2 for SPI mode. In SPI mode, the input data is latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of SCK.
Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDO
Notes:
1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as necessary.
2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during Multi-IO mode.
SCK
Mode 0 (0,0)
SCK
Mode 3 (1,1)
SI MSB
SO MSB
The memory array of IS25WQ040/020 is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte blocks (a
block consists of eight/sixteen adjacent sectors respectively).
Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is protected.
The BP0, BP1, BP2, BP3 and SRWD are non-volatile memory cells that can be written by a Write Status Register
(WRSR) instruction. The default value of the BP3, BP2, BP1, BP0, and SRWD bits were set to “0” at factory. The
Status Register can be read by the Read Status Register (RDSR).
WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a
program or erase operation. When the WIP bit is “0”, the device is ready for Write Status Register, program or
erase operation. When the WIP bit is “1”, the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the WEL
is “0”, the write enable latch is disabled and all write operations described in Table 6.3 are inhibited. When the
WEL bit is “1”, write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each write
register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be reset by a
Write Disable (WRDI) instruction. It will automatically be reset after the completion of any write operation.
BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of
the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a
defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any
program or erase operation to that area will be inhibited.
Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.
SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#)
signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not write-
protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register (SRWD, BP3,
BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to “1” and WP# is
pulled high (VIH), the Status Register can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the
QE bit is set to “0”, the pin WP# and HOLD# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins are
enabled.
WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply.
ESUS bit: The Erase Suspend Status indicates when an Erase operation has been suspended. The ESUS bit is
‘1’ after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the ESUS
bit is reset to ‘0’.
PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The PSUS
changes to ‘1’ after a suspend command is issued during the program operation. Once the suspended Program
resumes, the PSUS bit is reset to ‘0’.
Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence will
be ignored when Vcc drops to VWI.
Note: Before the execution of any program, erase or Write Status Register instruction, the Write Enable Latch (WEL)
bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the program,
erase or write register instruction will be ignored.
The RD instruction code is transmitted via the SI line, followed by three address bytes (A23 - A0) of the first memory
location to be read. A total of 24 address bits are shifted in, but only AVMSB (Valid Most Significant Bit) - A0 are decoded.
The remaining bits (A23 – AMSB) are ignored. The first byte address can be at any memory location. Upon completion,
any data on the SI will be ignored. Refer to Table 8.2 for the related Address Key.
The first byte data (D7 - D0) address is shifted out on the SO line, MSB first. A single byte of data, or up to the whole
memory array, can be read out in one READ instruction. The address is automatically incremented after each byte of
data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after the data comes
out. When the highest address of the device is reached, the address counter will roll over to the 000000h address,
allowing the entire memory to be read in one continuous READ instruction.
If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
CE #
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
SCK
Mode 0
3-byte Address
SI ...
Instruction = 03h 23 22 21 3 2 1 0
SO High Impedance
CE #
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
SI
The FAST_READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte from the
address is shifted out on the SO line, with each bit shifted out at a maximum frequency f CT, during the falling edge of
SCK.
The first byte addressed can be at any memory location. The address is automatically incremented after each byte
of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address,
allowing the entire memory to be read with a single FAST_READ instruction. The FAST_READ instruction is
terminated by driving CE# high (VIH).
If a Fast Read Data instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction
is ignored and will not have any effects on the current cycle.
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
SCK
Mode 0
3-byte Address
SI ...
Instruction = 0Bh 23 22 21 3 2 1 0
SO High Impedance
CE #
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
SI Dummy Byte
Data Out
tV
SO 7 6 5 4 3 2 1 0 ...
The FRDIO instruction code is followed by three address bytes (A23 – A0) and a mode byte, transmitted via the IO1
and IO0 lines, with each pair of bits latched-in during the rising edge of SCK. The address MSB is input on IO1, the
next bit on IO0, and continue to shift in alternating on the two lines. If AXh (X: don’t care) is input for the mode byte,
the device will enter AX read mode. In the AX read mode, the next instruction expected from the device will be another
FRDIO instruction and will not need the BBh instruction code so that it saves cycles as described in Figure 8.4. If the
following mode byte is not set to AXh, the device will exit AX read mode. To avoid any I/O contention problem, X
should be Hi-Z.
Once address and mode byte are input the device will read out data at the specified address. The first data byte
addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency f CT, during
the falling edge of SCK. The first bit (MSB) is output on IO1, while simultaneously the second bit is output on IO0.
Figure 8.3 illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented by one after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is terminated by
driving CE# high (VIH).
If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not affect the current cycle.
CE #
0 1 2 3 4 5 6 7 8 9 10 ... 18 19 20 21
Mode 3
SCK
High Impedance
IO1 23 21 19 ... 3 1 7 5
CE #
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
SCK
tV
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits are
different from AXh (X: don’t care), the device exits the AX read operation.
2. To avoid I/O contention, X should be Hi-Z.
CE #
0 1 2 3 ... 11 12 13 14 15 16 17 18 19 20 21 22
Mode 3
SCK
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits are
different from AXh (X: don’t care), the device exits the AX read operation.
2. To avoid I/O contention, X should be Hi-Z.
The FRDO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks), transmitted
via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted
out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of
SCK. The first bit (MSB) is output on IO1. Simultaneously the second bit is output on IO0.
The first byte addressed can be at any memory location. The address is automatically incremented by one after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRDO instruction. FRDO instruction is terminated by
driving CE# high (VIH).
If a FRDO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is
ignored and will not have any effects on the current cycle.
CE #
0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31
Mode 3
SCK
Mode 0
3-byte Address
High Impedance
IO1
CE #
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
tV
IO0 6 4 2 0 6 4 2 0 ...
IO1 7 5 3 1 7 5 3 1 ...
The FRQO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed
is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted out at a maximum frequency
fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while simultaneously the second bit is
output on IO2, the third bit is output on IO1, etc.
The first byte addressed can be at any memory location. The address is automatically incremented after each byte
of data is shifted out. W hen the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is terminated by
driving CE# high (VIH).
If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is
ignored and will not have any effects on the current cycle.
CE #
0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31
Mode 3
SCK
Mode 0
3-byte Address
High Impedance
IO1
High Impedance
IO2
High Impedance
IO3
CE #
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
tV
IO0 4 0 4 0 4 0 4 0 ...
8 Dummy Cycles Data Out 1 Data Out 2 Data Out 3 Data Out 4
IO1 5 1 5 1 5 1 5 1 ...
IO2 6 2 6 2 6 2 6 2 ...
IO3 7 3 7 3 7 3 7 3 ...
The FRQIO instruction code is followed by three address bytes (A23 – A0), a mode byte, and 4 dummy cycles,
transmitted via the IO3, IO2, IO0 and IO1 lines, with each group of four bits latched-in during the rising edge of
SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit on IO0, and continue
to shift in alternating on the four. The mode byte contains the value AXh, where X is a “don’t care” value. After
four dummy clocks, the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group
of four bits shifted out at a maximum frequency f CT, during the falling edge of SCK. The first bit (MSB) is output on
IO3, while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.7.1 illustrates
the timing sequence.
If the mode byte is AXh, the AX read mode is enabled. In the mode, the device expects that the next operation
will be another FRQIO and subsequent FRQIO execution skips command code. It saves command cycles as
described in Figure 8.7.2. The device will remain in this mode until the mode byte is different from AXh.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is terminated
by driving CE# high (VIH).
If a FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
CE #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
SCK
Mode 0
3-byte Address Mode Bits
High Impedance
IO1 21 17 13 9 5 1 5 1
IO2 22 18 14 10 6 2 6 2
IO3 23 19 15 11 7 3 7 3
CE #
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SCK
4 Dummy Cycles
tV Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5 Data Out 6
IO0 4 0 4 0 4 0 4 0 4 0 4 0 ...
5 1 5 1 5 1 5 1 5 1 5 1 ...
IO1
6 2 6 2 6 2 6 2 6 2 6 2 ...
IO2
7 3 7 3 7 3 7 3 7 3 7 3 ...
IO3
Note: If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). Anything but AXh
in the mode byte cycle will exit the AX read mode.
CE #
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ...
SCK
IO1 21 17 13 9 5 1 5 1 5 1 5 1 ...
IO2 22 18 14 10 6 2 6 2 6 2 6 2 ...
IO3 23 19 15 11 7 3 7 3 7 3 7 3 ...
Mode Bits
Note: If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). Anything but AXh
in the mode byte cycle will exit the AX read mode.
The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the SI line. Program
operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be executed.
The internal control logic automatically handles the programming voltages and timing. During a program operation,
all instructions will be ignored except the RDSR instruction. The progress or completion of the program operation
can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the
program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
CE #
2079
2086
2087
0 1 ... 7 8 9 ... 31 32 33 ... 39 ... ...
Mode 3
SCK
Mode 0
3-byte Address Data In 1 Data In 256
SO High Impedance
The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are input
via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought high,
otherwise the Quad Input Page Program instruction will not be executed. The internal control logic automatically
handles the programming voltages and timing. During a program operation, all instructions will be ignored except
the RDSR instruction. The progress or completion of the program operation can be determined by reading the
WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If
WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
CE #
0 1 2 3 4 5 6 7 8 9 ... 31 32 33 34 35
Mode 3
SCK
Mode 0
3-byte Address Data In 1 Data In 2
High Impedance
IO1 5 1 5 1 ...
IO2 6 2 6 2 ...
IO3 7 3 7 3 ...
Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to
“1”). In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase
(BER) and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without affecting
the data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block erase or chip erase operation can be executed prior to any
programming operation.
A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire instruction
sequence The SER instruction code, and three address bytes are input via SI. Erase operation will start
immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing.
During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction. The
progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register
using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase
operation has been completed.
CE #
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
SCK
Mode 0
3-byte Address
SI ...
Instruction = D7h/20h 23 22 21 3 2 1 0
SO High Impedance
The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic automatically
handles the erase voltage and timing.
CE #
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
SCK
Mode 0
3-byte Address
SI ...
Instruction = D8h 23 22 21 3 2 1 0
SO High Impedance
CE #
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
SCK
Mode 0
3-byte Address
SI ...
Instruction = 52h 23 22 21 3 2 1 0
SO High Impedance
The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,
otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase
voltage and timing.
CE#
0 1 2 3 4 5 6 7
Mode 3
SCK
Mode 0
SI Instruction = C7h/60h
SO High Impedance
CE#
0 1 2 3 4 5 6 7
Mode 3
SCK
Mode 0
Address
SO High Impedance
CE#
0 1 2 3 4 5 6 7
Mode 3
SCK
Mode 0
SO High Impedance
CE #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
SCK
Mode 0
SI
Instruction = 05h
tV Data Out
SO 3 2 1 0
7 6 5 4
CE #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
SCK
Mode 0
Data In
SI
Instruction = 01h 7 6 5 4 3 2 1 0
SO High Impedence
CE #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
SCK
Mode 0
SI
Instruction = 07h
tV Data Out
SO 3 2 1 0
7 6 5 4
Note: It needs 500ns delay time from write command to suspend command
To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the erase has been
suspended by changing the ESUS bit from ‘0’ to ‘1’, but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or wait
tSUS. When ESUS bit is issued, the Write Enable Latch (WEL) bit will be reset.
To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the programming has been
suspended by changing the PSUS bit from ‘0’ to ‘1’, but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or wait
tSUS.
CE # tDP
0 1 2 3 4 5 6 7
Mode 3
SCK
Mode 0
SI ...
Instruction = B9h
Release from power-down will take the time duration of tRES1 before the device will resume normal operation and
other instructions are accepted. The CE# pin must remain high during the tRES1 time duration. If the Release from
Power-down / RDID instruction is issued while an Erase, Program or Write cycle is in process (when WIP equals
1) the instruction is ignored and will not have any effects on the current cycle.
CE # tRES1
0 1 2 3 4 5 6 7
Mode 3
SCK
Mode 0
SI ...
Instruction = ABh
The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising
SCK edge. Then the Device ID1 is shifted out on SO with the MSB first, each bit been shifted out during the falling
edge of SCK. The RDID instruction is ended by CE# going high. The Device ID1 outputs repeatedly if additional
clock cycles are continuously sent on SCK while CE# is at low.
ID1 9Dh
Manufacturer ID
ID2 7Fh
CE #
Mode 0
SI
Instruction = ABh 3 Dummy Bytes
tV Data Out
SO Device ID1
(ID7-ID0)
CE #
Mode 0
SI
Instruction = 9Fh
Data Out
tV
SO Manufacturer ID1 Device ID2
Device ID1
CE #
Mode 0
SI 3 Byte Address
Instruction = 90h
(A0=0)
tV Data Out
SO Manufacturer Manufacturer
Device ID1
ID1 ID2
Notes:
1. ADDRESS A0 = 0, will output the Manufacturer ID1 Device ID1 Manufacturer ID2
ADDRESS A0 = 1, will output the Device ID1 Manufacturer ID1 Manufacturer ID2
2. The Manufacture and Device IDs can be read continuously and will alternate from one to the other until CE# pin is
pulled high.
CE #
Mode 0
SI
Instruction = A1h 3 Byte Address Dummy Byte
tV
SO
Data Out
To lock the Security Information Row (OTP memory), the Bit 0 of the OTP control byte (byte 256) is used to
permanently lock the OTP memory array.
- When the bit 0 of byte 256 = ’1’, the 256 bytes of the OTP memory array can be programmed.
- When the bit 0 of byte 256 = ‘0’, the 256 bytes of the OTP memory array are read-only and cannot be
programmed anymore.
Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’. Therefore, as soon
as bit 0 of byte 256 (control byte) is set to ‘0’, the 256 bytes of the OTP memory array become read-only in a
permanent way.
BIT
The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input via
the SI line. Three address bytes has to be input as specified in the Table 8.6 Information Row Address. Program
operation will start once the CE# goes high, otherwise the IRP instruction will not be executed. The internal control
logic automatically handles the programming voltages and timing. During a program operation, all instructions will
be ignored except the RDSR instruction. The progress or completion of the program operation can be determined
by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still
in progress. If WIP bit is “0”, the program operation has completed.
At least one program data should be input. The starting byte can be anywhere within the 256 addresses. The data
to be programmed is not allowed to exceed the last address. If the number of the data to be programmed are less
than the one between starting address and the last address, the data of all remaining addresses will be
unchanged.
After CE# pin is driven HIGH, the self-timed page program cycle (whose duration is tPOTP) is initiated. While the
program cycle is in progress, the status register may be read to check the value of the write in progress (WIP)
bit. The write in progress (WIP) bit is “1” during the self-timed program cycle, and it is “0” when the program
cycle is completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit will
be reset.
If an IRP instruction is issued while an erase, program or write cycle is in progress the instruction is ignored
without having any effect on the cycle that is in progress
Note: Information Row is only one time programmable (OTP). Once Information Row is programmed, the data
cannot be altered.
CE #
2079
2086
2087
0 1 ... 7 8 9 ... 31 32 33 ... 39 ... ...
Mode 3
SCK
Mode 0
3-byte Address Data In 1 Data In n
SO High Impedance
Note:
1. The “n” must not exceed the last address. (1 ≤ n ≤ 256)
2. The lock bit of Security Information Row is in the address of 0000FFh.
The IRRD instruction code is followed by three address bytes (A23 - A0), transmitted via the SI line, and with each
bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO line, with
each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.
The address is automatically incremented after each byte of data is shifted out. When the last address is reached,
the address counter will not wrap around to the 000000h address since there is no rollover mechanism in the
IRRD instruction. This means that the IRRD instruction must be sent with a maximum of 256 bytes to read and
the data of the last address keeps being read on the SO pin once the last address is reached. The IRRD instruction
is terminated by driving CE# high (VIH).
If an IRRD instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle
CE #
Mode 0
SI
Instruction = 4Bh 3 Byte Address
tV
The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.
This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, and
BP3 bits in the Status Register. Only one sector can be enabled at any time. If many SECUNLOCK commands
are input, only the last sector designated by the last SECUNLOCK command will be unlocked. The instruction
code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The
remaining sectors within the same block remain as read-only.
CE #
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
SCK
Mode 0
3-byte Address
SI ...
Instruction = 26h 23 22 21 3 2 1 0
SO High Impedance
The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The
instruction code does not require an address to be specified, as only one sector can be enabled at a time. The
remaining sectors within the same block remain in read-only mode.
CE #
0 1 2 3 4 5 6 7
Mode 3
SCK
Mode 0
SI
Instruction = 24h
SO High Impedance
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. ANSI/ESDA/JEDEC JS-001
Notes:
1. Maximum DC voltage on input or I/O pins is VCC + 0.5V. During voltage transitions, input or I/O pins may overshoot
VCC by + 2.0V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot GND by -2.0V for a period of time not to exceed 20ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C.
3. Outputs are unconnected during reading data so that output switching current is not included.
4. These parameters are characterized and not 100% tested.
0.8VCC
AC
Input VCC/2 Measurement
1.8k Level
0.2VCC
OUTPUT PIN
1.2k 30pf
Notes:
1. These parameters are characterized and are not 100% tested.
Notes:
1. These parameters are characterized and not 100% tested.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C.
VIH
SCK tCKH tCKL
VIL
tDS tDH
VIH
SI VALID IN
VIL
tV tOH tDIS
VOH HI-Z HI-Z
SO
VOL
CE#
tHLCH
tCHHL tHHCH
SCK
tCHHH
tHZ tLZ
SO
SI
HOLD#
Power up timing
VCC
VCC(max)
All Write Commands are Rejected
VCC(min)
Reset State
tVCE Read Access Allowed Device fully
V(write inhibit) accessible
tPUW
Note1. These parameters are characterized and are not 100% tested.
Note: These parameters are characterized and are not 100% tested.
Notes:
1. These parameters are characterized and are not 100% tested.
2. 100,000 Continuous Chip and Block cycling, 100,000 Continuous Sector cycling
10.5 8-PIN JEDEC 208MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (JB)
TEMPERATURE RANGE
E = Extended (-40°C to +105°C)
PACKAGING CONTENT
L = RoHS compliant
Die Revision
Blank = A Revision
Density
040 = 4 Mbit
020 = 2 Mbit
Note:
1. Call Factory for other package options available