A25l032 Amic

A25L032 Series
32Mbit Low Voltage, Dual-I/O Serial Flash Memory

with 100MHz Uniform 4KB Sectors
Document Title
32Mbit, Low Voltage, Dual-I/O Serial Flash Memory with 100MHz Uniform 4KB Sectors
Revision History
Rev. No. History Issue Date Remark

0.0 Initial issue August 18, 2008 Preliminary
0.1 Spec. change for new commands July 13, 2009
0.2 Add packing description in Part Numbering Scheme May 3, 2010
0.3 P31: Modify Read Device Identification July 27, 2010
P40: Remove the min. value of ICC1 and ICC2
0.4 P32: ID code error correction September 21, 2010
0.5 P39: Change Data Retention and Endurance value from Max. to Min. October 7, 2010
1.0 Change tPP, tSE, tBE and tCE data values May 26, 2011 Final
Final version release
1.1 P1: Add “Provide 64Bytes Security ID (application note is available September 19, 2011
by request)” in Features
1.2 Change tSE(typ.) from 150ms to 80ms November 15, 2011
Change tSE(max.) from 280ms to 200s
Change tBE(typ,) from 0.7s to 0.5s
Change tCE(typ,) from 40s to 32s
Add 8-pin WSON (6*5mm) package type
1.3 P40: Change ICC6 & ICC7(max.) from 15mA to 25ma March 29, 2012
1.4 Remove SOP 16L (300mil) package type May 15, 2014
1.5 P.1: Add “AEC-Q100 Grade 3 Certification” in FEATURES December 18, 2014
P.43 & P.44: Add –E grade specification
(December, 2014, Version 1.5) AMIC Technology Corp.

A25L032 Series
32Mbit Low Voltage, Dual-I/O Serial Flash Memory

with 100MHz Uniform 4KB Sectors
FEATURES
Family of Serial Flash Memories Additional 64-byte user-lockable, one-time programmable
- A25L032: 32M-bit /4M-byte (OTP) area
Flexible Sector Architecture with 4KB sectors 32Mbit Flash memory
- Sector Erase (4K-bytes) in 80ms (typical) - Uniform 4-Kbyte Sectors
- Block Erase (64K-bytes) in 0.5s (typical) - Uniform 64-Kbyte Blocks
Page Program (up to 256 Bytes) in 1.5ms (typical) Electronic Signatures
2.7 to 3.6V Single Supply Voltage - JEDEC Standard Two-Byte Signature
Dual input / output instructions resulting in an equivalent A25L032: (3016h)
clock frequency of 200MHz: - RES Instruction, One-Byte, Signature, for backward
- FAST_READ_DUAL_OUTPUT Instruction compatibility
- FAST_READ_DUAL_INPUT_OUTPUT Instruction A25L032: (15h)
- Dual Input Fast Program (DIFP) Instruction AEC-Q100 Grade 3 Certification
SPI Bus Compatible Serial Interface Package options
100MHz Clock Rate (maximum) - 8-pin SOP (209mil), 8-pin DIP (300mil), or 8-pin WSON
Deep Power-down Mode 15µA (Max.) (6*5mm)
Advanced Protection Features - All Pb-free (Lead-free) products are RoHS compliant
- Software and Hardware Write-Protect Provide 64Bytes Security ID (application note is available by
- Top/Bottom, 4KB Complement Array Protection request)
GENERAL DESCRIPTION
The A25L032 is 32M bit Serial Flash Memory, with advanced sectors. Each sector is composed of 16 pages. Each page is
write protection mechanisms, accessed by a high speed 256 bytes wide. Thus, the whole memory can be viewed as
SPI-compatible bus. consisting of 16,384 pages, or 4,194,304 bytes.
The memory can be programmed 1 to 256 bytes at a time, The whole memory can be erased using the Chip Erase
using the Page Program instruction. instruction, a block at a time, using Block Erase instruction, or a
sector at a time, using the Sector Erase instruction.
The memory is organized as 64 blocks, each containing 16
Pin Configurations
SOP8 / DIP8 Connections WSON8 Connections
A25L032 A25L032
S 1 8 VCC
S 1 8 VCC
DO (IO1) DO (IO1) 2 7 HOLD
2 7 HOLD
3 6 C W 3 6 C
W
VSS VSS 4 5 DI (IO0)
4 5 DI (IO0)
(December, 2014, Version 1.5) 1 AMIC Technology Corp.

A25L032 Series
Pin Descriptions
Pin No. Pin Name I/O Description
1 S I Chip Select Input
2 DO (IO1) I/O Data Output (Data Input Output 1)(1)
3 W I Write Protect Input
4 VSS Ground
5 DI (IO0) I/O Data Input (Data Input Output 0) (1)
6 C I Serial Clock Input
7 HOLD I Hold Input
8 VCC Power Supply
Notes:
(1) IO0 and IO1 are used for Dual Instruction.
Block Diagram
HOLD
High Voltage
W Control Logic
Generator
S 64 OTP bytes
DI (IO0) I/O Shift Register

DO (IO1)
Address register 256 Byte Status

and Counter Data Buffer Register
3FFFFF (32M)
Size of the
Y Decoder
memory area
00000h 000FFh
256 Byte (Page Size)
X Decoder

A25L032 Series
PIN DESCRIPTION
Chip Select ( S ) Write Protect ( W )
The SPI Chip Select ( S ) pin enables and disables device The Write Protect ( W ) pin can be used to prevent the Status
operation. When Chip Select ( S ) is high the device is Register from being written. Used in conjunction with the
Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1
deselected and the Serial Data Output (DO, or IO0, IO1) pins
and BP0) bits and Status Register Protect (SRP1, SRP0) bits,
are at high impedance. When deselected, the devices power
a portion or the entire memory array can be hardware
consumption will be at standby levels unless an internal
erase, program or write status register cycle is in progress. protected. The Write Protect ( W ) pin is active low.
When Chip Select ( S ) is brought low the device will be
selected, power consumption will increase to active levels Hold ( HOLD )
and instructions can be written to and data read from the The Hold ( HOLD ) pin allows the device to be paused while
device. After power-up, Chip Select ( S ) must transition from it is actively selected. When Hold ( HOLD ) pin is brought low,
high to low before a new instruction will be accepted. while Chip Select ( S ) pin is low, the DO pin will be at high
impedance and signals on the DI and Serial Clock (C) pins
Serial Data Input, Output and IOs (DI, DO and IO0, IO1)
The A25L032 support standard SPI and Dual SPI operation. will be ignored (don’t care). When Hold ( HOLD ) pin is
Standard SPI instructions use the unidirectional DI (input) pin brought high, device operation can resume. The Hold
to serially write instructions, addresses or data to the device function can be useful when multiple devices are sharing the
on the rising edge of the Serial Clock (C) input pin. Standard same SPI signals. The Hold ( HOLD ) pin is active low.
SPI also uses the unidirectional DO (output) to read data or
status from the device on the falling edge of Serial Clock (C). Serial Clock (C)
Dual SPI instructions use the bidirectional IO pins to serially The SPI Serial Clock Input (C) pin provides the timing for
write instructions, addresses or data to the device on the serial input and output operations.
rising edge of Serial clock (C) and read data or status from
the device on the falling edge of Serial Clock (C).

A25L032 Series
SPI MODES
These devices can be driven by a microcontroller with its SPI falling edge of Serial Clock (C).
peripheral running in either of the two following modes: The difference between the two modes, as shown in Figure 1,
– CPOL=0, CPHA=0 is the clock polarity when the bus master is in Stand-by mode
– CPOL=1, CPHA=1 and not transferring data:
For these two modes, input data is latched in on the rising – C remains at 0 for (CPOL=0, CPHA=0)
edge of Serial Clock (C), and output data is available from the – C remains at 1 for (CPOL=1, CPHA=1)
Figure 1. SPI Modes Supported
CPOL CPHA
0 0 C
1 1 C
DI MSB
DO MSB

A25L032 Series
SPI OPERATIONS
Standard SPI Instructions To enter the Hold condition, the device must be selected, with
The A25L032 is accessed through an SPI compatible bus Chip Select ( S ) Low.
consisting of four signals: Serial Clock (C), Chip Select ( S ), The Hold condition starts on the falling edge of the Hold
Serial Data Input (DI), and Serial Data Output (DO). Standard ( HOLD ) signal, provided that this coincides with Serial Clock
SPI instructions use the DI input pin to serially write (C) being Low (as shown in Figure 2.).
instructions, addresses or data to the device on the rising The Hold condition ends on the rising edge of the Hold
edge of Serial Clock (C). The DO output pin is used to read
data or status from the device on the falling edge of Serial ( HOLD ) signal, provided that this coincides with Serial Clock
Clock (C). (C) being Low.
If the falling edge does not coincide with Serial Clock (C)
Dual SPI Instructions being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
The A25L032 supports Dual SPI operation when using the with Serial Clock (C) being Low, the Hold condition ends after
“FAST_READ_DUAL_OUTPUT and FAST_READ_DUAL_ Serial Clock (C) next goes Low. This is shown in Figure 2.
INPUT_OUTPUT” (3B and BB hex) instructions. These During the Hold condition, the Serial Data Output (DO) is high
instructions allow data to be transferred to or from the device impedance, and Serial Data Input (DI) and Serial Clock (C)
at two to three times the rate of ordinary Serial Flash devices. are Don’t Care.
The Dual Read instructions are ideal for quickly downloading
code to RAM upon power-up (code-shadowing) or for Normally, the device is kept selected, with Chip Select ( S )
executing non-speed-critical code directly from the SPI bus driven Low, for the whole duration of the Hold condition. This
(XIP). When using Dual SPI instructions the DI and DO pins is to ensure that the state of the internal logic remains
become bidirectional I/O pins; IO0 and IO1. unchanged from the moment of entering the Hold condition.
If Chip Select ( S ) goes High while the device is in the Hold
Hold Condition condition, this has the effect of resetting the internal logic of
The Hold ( HOLD ) signal is used to pause any serial the device. To restart communication with the device, it is
communications with the device without resetting the clocking necessary to drive Hold ( HOLD ) High, and then to drive Chip
sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle Select ( S ) Low. This prevents the device from going back to
the Hold condition.
that is currently in progress. The HOLD function is only
available for standard SPI and Dual SPI operation, not during
Quad SPI.
Figure 2. Hold Condition Activation
HOLD
Hold Hold
Condition Condition
(standard use) (non-standard use)

A25L032 Series
OPERATING FEATURES
(the Release from Deep Power-down Mode and Read
Page Programming Electronic Signature (RES) instruction) is executed.
To program one data byte, two instructions are required: Write All other instructions are ignored while the device is in the
Enable (WREN), which is one byte, and a Page Program (PP) Deep Power-down mode. This can be used as an extra
sequence, which consists of four bytes plus data. This is software protection mechanism, when the device is not in
followed by the internal Program cycle (of duration tPP). active use, to protect the device from inadvertent Write,
To spread this overhead, the Page Program (PP) instruction Program or Erase instructions.
allows up to 256 bytes to be programmed at a time (changing Status Register
bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory. The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific
Dual Input Fast Program instructions. See Read Status Register (RDSR) for a detailed
The Dual Input Fast Program (DIFP) instruction makes it description of the Status Register bits.
possible to program up to 256 bytes using two input pins at Protection Modes
the same time (by changing bits from 1 to 0).
For optimized timings, it is recommended to use the Dual The environments where non-volatile memory devices are
Input Fast Program (DIFP) instruction to program all used can be very noisy. No SPI device can operate correctly
consecutive targeted bytes in a single sequence rather to in the presence of excessive noise. To help combat this, the
using several Dual Input Fast Program (DIFP) sequences A25L032 boasts the following data protection mechanisms:
each containing only a few bytes. Power-On Reset and an internal timer (tPUW) can provide
protection against inadvertent changes while the power
Sector Erase, Block Erase, and Chip Erase supply is outside the operating specification.
The Page Program (PP) instruction and Dual Input Fast Program, Erase and Write Status Register instructions are
Program (DIFP) instruction allow bits to be reset from 1 to 0. checked that they consist of a number of clock pulses that
Before this can be applied, the bytes of memory need to have is a multiple of eight, before they are accepted for
been erased to all 1s (FFh). This can be achieved, a sector at execution.
a time, using the Sector Erase (SE) instruction, a block at a All instructions that modify data must be preceded by a
time, using the Block Erase (BE) instruction, or throughout the Write Enable (WREN) instruction to set the Write Enable
entire memory, using the Chip Erase (CE) instruction. This Latch (WEL) bit. This bit is returned to its reset state by
starts an internal Erase cycle (of duration tSE, tBE, or tCE). the following events:
The Erase instruction must be preceded by a Write Enable - Power-up
(WREN) instruction. - Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
Polling During a Write, Program or Erase Cycle - Program OTP (POTP) instruction completion
A further improvement in the time to Write Status Register - Page Program (PP) instruction completion
(WRSR), Program OTP (POTP), Program (PP, DIFP), or - Dual Input Fast Program (DIFP) instruction completion
Erase (SE, BE, or CE) can be achieved by not waiting for the - Sector Erase (SE) instruction completion
worst case delay (tW, tPP, tSE, tBE, tCE). The Write In Progress - Block Erase (BE) instruction completion
(WIP) bit is provided in the Status Register so that the - Chip Erase (CE) instruction completion
application program can monitor its value, polling it to The Block Protect (BP2, BP1, BP0) bits conjunction with
establish when the previous Write cycle, Program cycle or Sector Protect (SEC) bit , Top/Bottom (TB) bit and
Erase cycle is complete. Complement Protect (CMP) bit allow part of the memory to
be configured as read-only. This is the Software Protected
Active Power, Stand-by Power and Deep Power-Down Mode (SPM).
Modes The Write Protect ( W ) signal allows the Block Protect
(BP2, BP1, BP0) bits, Sector Protect (SEC) bit,
When Chip Select ( S ) is Low, the device is enabled, and in
Top/Bottom (TB) bit, All Protect (APT), Complement
the Active Power mode.
Protect (CMP) bit and Status Register Protect (SRP1,
When Chip Select ( S ) is High, the device is disabled, but SRP0) bits to be protected. This is the Hardware
could remain in the Active Power mode until all internal cycles Protected Mode (HPM).
have completed (Program, Erase, Write Status Register). The In addition to the low power consumption feature, the
device then goes in to the Stand-by Power mode. The device Deep Power-down mode offers extra software protection
consumption drops to ICC1. from inadvertent Write, Program and Erase instructions, as
The Deep Power-down mode is entered when the specific all instructions are ignored except one particular instruction
instruction (the Deep Power-down Mode (DP) instruction) is (the Release from Deep Power-down instruction).
executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction

A25L032 Series
Table 1-1. Protected Area Sizes (CMP=0)
A25L032
Status Register Content (32M-Bit) Memory Protection

SEC TB BP2 BP1 BP0 Block(s) Addresses Density(Byte) Portion
X X 0 0 0 None None None None
0 0 0 0 1 63 3F0000h – 3FFFFFh 64KB Upper 1/64
0 0 0 1 0 62 – 63 3E0000h – 3FFFFFh 128KB Upper 1/32
0 0 0 1 1 60 – 63 3C0000h – 3FFFFFh 256KB Upper 1/16
0 0 1 0 0 56 – 63 380000h – 3FFFFFh 512KB Upper 1/8
0 0 1 0 1 48 – 63 300000h – 3FFFFFh 1MB Upper 1/4
0 0 1 1 0 32 – 63 200000h – 3FFFFFh 2MB Upper 1/2
0 1 0 0 1 0 000000h – 00FFFFh 64KB Lower 1/64
0 1 0 1 0 0–1 000000h – 01FFFFh 128KB Lower 1/32
0 1 0 1 1 0–3 000000h – 03FFFFh 256KB Lower 1/16
0 1 1 0 0 0–7 000000h – 07FFFFh 512KB Lower 1/8
0 1 1 0 1 0 – 15 000000h – 0FFFFFh 1MB Lower 1/4
0 1 1 1 0 0 – 31 000000h – 1FFFFFh 2MB Lower 1/2
X X 1 1 1 0 – 63 000000h – 3FFFFFh 4MB ALL
1 0 0 0 1 63 3FF000h – 3FFFFFh 4KB Top Block
1 0 0 1 0 63 3FE000h – 3FFFFFh 8KB Top Block
1 0 0 1 1 63 3FC000h – 3FFFFFh 16KB Top Block
1 0 1 0 X 63 3F8000h – 3FFFFFh 32KB Top Block
1 0 1 1 0 63 3F0000h – 3FFFFFh 64KB Top Block
1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block
1 1 1 0 X 0 000000h – 007FFFh 32KB Bottom Block
1 1 1 1 0 0 000000h – 00FFFFh 64KB Bottom Block
Note:
1. X = don’t care
2. When CMP is 0, the device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) bits
are 0.

A25L032 Series
Table 1-2. Protected Area Sizes (CMP=1)
A25L032
Status Register Content (32M-Bit) Memory Protection

SEC TB BP2 BP1 BP0 Block(s) Addresses Density(Byte) Portion
X X 0 0 0 0 - 63 000000h – 3FFFFFh 4MB All
0 0 0 0 1 0 - 62 000000h – 3EFFFFh 4032KB Lower 63/64
0 0 0 1 0 0 – 61 000000h – 3DFFFFh 3968KB Lower 31/32
0 0 0 1 1 0 – 59 000000h – 3BFFFFh 3840KB Lower 15/16
0 0 1 0 0 0 – 55 000000h – 37FFFFh 3584KB Lower 7/8
0 0 1 0 1 0 – 47 000000h – 2FFFFFh 3MB Lower 3/4
0 0 1 1 0 0 – 31 000000h – 1FFFFFh 2MB Lower 1/2
0 1 0 0 1 1 - 63 010000h – 3FFFFFh 4032KB Upper 63/64
0 1 0 1 0 2 - 63 020000h – 3FFFFFh 3968KB Upper 31/32
0 1 0 1 1 4 - 63 040000h – 3FFFFFh 3840KB Upper 15/16
0 1 1 0 0 8 - 63 080000h – 3FFFFFh 3584KB Upper 7/8
0 1 1 0 1 16 - 63 100000h – 3FFFFFh 3MB Upper 3/4
0 1 1 1 0 32 - 63 200000h – 3FFFFFh 2MB Upper 1/2
X X 1 1 1 None None None None
1 0 0 0 1 0 - 62 000000h – 3FEFFFh 4092KB Lower 1023/1024
1 0 0 1 0 0 - 62 000000h – 3FDFFFh 4088KB Lower 511/512
1 0 0 1 1 0 - 62 000000h – 3FBFFFh 4080KB Lower 255/256
1 0 1 0 X 0 - 62 000000h – 3F7FFFh 4064KB Lower 127/128
1 0 1 1 0 0 - 62 000000h – 3EFFFFh 4032KB Lower 63/64
1 1 0 0 1 1 – 63 001000h – 3FFFFFh 4092KB Upper 1023/1024
1 1 0 1 0 1 – 63 002000h – 3FFFFFh 4088KB Upper 511/512
1 1 0 1 1 1 – 63 004000h – 3FFFFFh 4080KB Upper 255/256
1 1 1 0 X 1 – 63 008000h – 3FFFFFh 4064KB Upper 127/128
1 1 1 1 0 1 - 63 010000h – 3FFFFFh 4032KB Upper 63/64
Note:
1. X = don’t care
2. When CMP is 1, the device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) bits
are 1.

A25L032 Series
MEMORY ORGANIZATION
The memory is organized as: Each page can be individually programmed (bits are
4,194,304 bytes (8 bits each) programmed from 1 to 0). The device is Sector, Block, or Chip
64 blocks (64 Kbytes each) Erasable (bits are erased from 0 to 1) but not Page Erasable.
1024 sectors (4 Kbytes each)
16384 pages (256 bytes each)
64 bytes OTP located outside the main memory array
Table 2. Memory Organization

A25L032 Address Table
Block Sector Address range Block Sector Address range
1023 3FF000h 3FFFFFh 335 14F000h 14FFFFh

20
...
...
...
...
...
...
63
1008 3F0000h 3F0FFFh 320 140000h 140FFFh
1007 3EF000h 3EFFFFh 319 13F000h 13FFFFh
19
...
...
...
62
...
...
...
992 3E0000h 3E0FFFh 304 130000h 130FFFh

303 12F000h 12FFFFh
18
...
...
...
……
……
……
….
288 120000h 120FFFh

287 11F000h 11FFFFh
463 1CF000h 1CFFFFh 17
...
...
...
28 272 110000h 110FFFh
...
...
...
448 1C0000h 1C0FFFh 271 10F000h 10FFFFh

447 1BF000h 1BFFFFh 16
...
...
...
27 256 100000h 100FFFh
...
...
...
432 1B0000h 1B0FFFh 255 FF000h FFFFFh

431 1AF000h 1AFFFFh 15
...
...
26 240 F0000h ...

F0FFFh
...
...
...
416 1A0000h 1A0FFFh 239 EF000h EFFFFh

415 19F000h 19FFFFh 14
...
...
...
25 224 E0000h E0FFFh

...
...
...
400 190000h 190FFFh 223 DF000h DFFFFh

399 18F000h 18FFFFh 13
...
...
...
24 208 D0000h D0FFFh

...
...
...
384 180000h 180FFFh 207 CF000h CFFFFh

383 17F000h 17FFFFh 12
...
...
...
23 192 C0000h C0FFFh

...
...
...
368 170000h 170FFFh 191 BF000h BFFFFh

367 16F000h 16FFFFh 11
...
...
...
22 176 B0000h B0FFFh

...
...
...
352 160000h 160FFFh 175 AF000h AFFFFh

351 15F000h 15FFFFh 10
...
...
...
21 160 A0000h A0FFFh

...
...
...
336 150000h 150FFFh

A25L032 Series
Memory Organization (continued)
Block Sector Address range Block Sector Address range
159 9F000h 9FFFFh 63 3F000h 3FFFFh

9 3
...
...
...
...
...
...
144 90000h 90FFFh 48 30000h 30FFFh
8 2
...
...
...
...
...
...
128 80000h 80FFFh 32 20000h 20FFFh
7 1
...
...
...
...
...
...
112 70000h 70FFFh 16 10000h 10FFFh

6
...
...
...
...
...
...
96 60000h 60FFFh 4 04000h 04FFFh

95 5F000h 5FFFFh 3 03000h 03FFFh
5 0
...
...
...
2 02000h 02FFFh
80 50000h 50FFFh
1 01000h 01FFFh
79 4F000h 4FFFFh
4 0 00000h 00FFFh
...
...
...
64 40000h 40FFFh

A25L032 Series
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of Identification and Read Electronic Signature (RES) instruction,
the device, most significant bit first. the shifted-in instruction sequence is followed by a data-out
Serial Data Input(s) IO0 (IO1) is (are) sampled on the first sequence. Chip Select ( S ) can be driven High after any bit of
rising edge of Serial Clock (C) after Chip Select ( S ) is driven the data-out sequence is being shifted out.
Low. Then, the one-byte instruction code must be shifted in to In the case of a Page Program (PP), Program OTP (POTP),
the device, most significant bit first, on Serial Data Input(s) IO0 Dual Input Fast Program (DIFP), Sector Erase (SE), Block
(IO1), each bit being latched on the rising edges of Serial Erase (BE), Chip Erase (CE), Write Status Register (WRSR),
Clock (C). Write Enable (WREN), Write Disable (WRDI) or Deep
The instruction set is listed in Table 3. Power-down (DP) instruction, Chip Select ( S ) must be driven
Every instruction sequence starts with a one-byte instruction High exactly at a byte boundary, otherwise the instruction is
code. Depending on the instruction, this might be followed by rejected, and is not executed. That is, Chip Select ( S ) must
address bytes, or by data bytes, or by dummy bytes (don’t driven High when the number of clock pulses after Chip Select
care), or by a combination or none.
( S ) being driven Low is an exact multiple of eight.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Data Bytes at Higher Speed All attempts to access the memory array during a Write Status
by Dual Output (FAST_READ_DUAL_OUTPUT), Read Data Register cycle, Program cycle or Erase cycle are ignored, and
Bytes at Higher Speed by Dual Input and Dual Output the internal Write Status Register cycle, Program cycle or
(FAST_READ_DUAL_INPUT_OUTPUT), Read OTP (ROTP), Erase cycle continues unaffected.
Read Identification (RDID), Read Electronic Manufacturer and
Device Identification (REMS), Read Status Register (RDSR)
or Release from Deep Power-down, Read Device

A25L032 Series
Table 3. Instruction Set
One-byte Address Dummy Data

Instruction Description
Instruction Code Bytes Bytes Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDSR-1 Read Status Register-1 0000 0101 05h 0 0 1 to ∞
RDSR-2 Read Status Register-2 0011 0101 35h 0 0 1 to ∞
WRSR Write Status Register 0000 0001 01h 0 0 2
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
FAST_READ_DUAL Read Data Bytes at Higher Speed by (1)
0011 1011 3Bh 3 1 1 to ∞
_OUTPUT Dual Output (1)
FAST_READ_DUAL Read Data Bytes at Higher Speed by
(1)(2) 1011 1011 BBh 3(2) 1(2) 1 to ∞(1)
_INPUT_OUTPUT Dual Input and Dual Output
Read OTP (Read 64 bytes of OTP
ROTP 0100 1011 4Bh or 48h 3 1 1 to ∞
area)
Program OTP (Program 64 bytes of
POTP 0100 0010 42h 3 0 1 to 64
OTP area)
PP Page Program 0000 0010 02h 3 0 1 to 256
DIFP Dual Input Fast Program 1010 0010 A2h 3 0 1 to 256(3)
SE Sector Erase 0010 0000 20h 3 0 0
BE Block Erase 1101 1000 D8h or 52h 3 0 0
CE Chip Erase 1100 0111 C7h or 60h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RDID Read Device Identification 1001 1111 9Fh 0 0 1 to ∞
Read Electronic Manufacturer & Device (4)
REMS 1001 0000 90h 1 2 1 to ∞
Identification
Release from Deep Power-down, and
0 3 1 to ∞
RES Read Electronic Signature 1010 1011 ABh
Release from Deep Power-down 0 0 0
HPM High Performance Mode 1010 0011 A3h 0 3 0
Continuous Read 1111 1111
(5) Reset Mode Bit M<4> to 1 FFFFh 0 0 0
Mode Reset 1111 1111
Note: (1) Dual Output Data

IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
(2) Dual Input Address
IO0 = (A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0)
IO1 = (A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1)
(3) Dual Input Fast Program Input Data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
(4) ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first
(5) This instruction is recommended when using the Dual “Continuous Read Mode” features. See page 22 for
more information.

A25L032 Series
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 3.) sets the instruction.
Write Enable Latch (WEL) bit. The Write Enable (WREN) instruction is entered by driving
The Write Enable Latch (WEL) bit must be set prior to every Chip Select ( S ) Low, sending the instruction code, and then
Page Program (PP), Dual Input Fast Program (DIFP),
Program OTP (POTP), Sector Erase (SE), Block Erase (BE), driving Chip Select ( S ) High.
and Chip Erase (CE) and Write Status Register (WRSR)
Figure 3. Write Enable (WREN) Instruction Sequence
0 1 2 3 4 5 6 7
C
Instruction (06h)
DI
High Impedance
DO
Write Disable (WRDI) ﹣ Power-up

The Write Disable (WRDI) instruction (Figure 4.) resets the ﹣ Write Disable (WRDI) instruction completion
﹣ Write Status Register (WRSR) instruction completion
Write Enable Latch (WEL) bit. ﹣ Page Program (PP) instruction completion
The Write Disable (WRDI) instruction is entered by driving Chip ﹣ Dual Input Fast Program (DIFP) instruction completion
Select ( S ) Low, sending the instruction code, and then driving ﹣ Program OTP (POTP) instruction completion
Chip The Write Enable Latch (WEL) bit is reset under the ﹣ Sector Erase (SE) instruction completion
following conditions: ﹣ Block Erase (BE) instruction completion
﹣ Chip Erase (CE) instruction completion
Figure 4. Write Disable (WRDI) Instruction Sequence
0 1 2 3 4 5 6 7
C
Instruction (04h)
DI
High Impedance
DO

A25L032 Series
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Erase, Chip Erase, and Write Status Register.
Status Register to be read. The instruction code of “05h” is BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, and BP0)
for Status Register-1 and “35h” is for Status Register-2. The bits are non-volatile read/write bits in the status register (b4,
Status Register may be read at any time, even while a b3, and b2) that provide Write Protection control and status.
Program, Erase or Write Status Register cycle is in progress. Block Protect bits can be set using the Write Status Register
When one of these cycles is in progress, it is recommended Instruction (see tW in AC characteristics). All, none or a
to check the Write In Progress (WIP) bit before sending a portion of the memory array can be protected from Program
new instruction to the device. It is also possible to read the and Erase instructions (see Table 1. Protected Area Sizes).
Status Register continuously, as shown in Figure 5. These bits can be set with the Write Status Register
Instruction depending on the state of the SRP1, SRP0, and
WEL bit. The factory default setting for the Block Protect Bits
Table 4-a Status Register-1 Format
is 0 which means none of the array protected. For value of
BP2, BP1, BP0 after power-on, see note please.
b7 b6 b5 b4 b3 b2 b1 b0
SRP0 SEC TB BP2 BP1 BP0 WEL WIP TB bit. The non-volatile Top/Bottom (TB) bit controls if the
Status Register Protect 0 Block Protect Bits (BP2, BP1, BP0) protect from the Top
(Non-volatile)
(TB=0) or the Bottom (TB=1) of the array as shown in Table 1.
Sector Protect Protected Area Sizes. The factory default setting is TB=0.
(Non-volatile)
The TB bit can be set with the Write Status Register
Top/Bottom Bit Instruction depending on the state of the SRP1, SRP0, and
(Non-volatile) WEL bit.
Block Protect Bits
(Non-volatile) SEC bit. The non-volatile Sector Protect (SEC) bit in the
status register (b6) controls if the Block Protect Bits (BP2,
Write Enable Latch Bit
BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks
(SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
Write In Progress Bit as shown in Table 1. Protected Area Sizes. This bit can be
set with the Write Status Register Instruction depending on
Table 4-b Status Register-2 Format the state of the SRP1, SRP0, and WEL bit. The factory
default setting for SEC is 0.
b15 b14 b13 b12 b11 b10 b9 b8

SRP1, SRP0 bits. The Status Register Protect bits (SRP1
0 CMP 0 0 0 APT 0 SRP1
and SRP0) are non-volatile read/write bits in the status
Reserved
register (b8 and b7). The SRP bits control the method of write
Complement Protect protection: software protection, hardware protection, or one
(Non-volatile)
time programmable protection.
Reserved
All Protect (Non-volatile) APT bit. The All Protect (APT) bit is a non-volatile read/write
bit in the status register (b10). Whole chip will be kept in
Reserved
write-protect state after power-on if this bit is set to 1. This bit
Status Register Protect 1 can be set with the Write Status Register Instruction
(Non-volatile) depending on the state of the SRP1, SRP0, and WEL bit.
The factory default setting for APT is 0.
The status and control bits of the Status Register are as
CMP bit. The Complement Protect (CMP) bit is a non-volatile
follows:
read/write bit in the status register (b14). It’s used in
conjunction with SEC, TB, BP2, BP1, BP0 bits to provide
WIP bit. The Write In Progress (WIP) bit is a read only bit in
more flexibility for the array protection. Once CMP is set to 1,
the status register (b0) that is set to a 1 state when the
previous array protection set by SEC, TB, BP2, BP1 and BP0
device is busy with a Write Status Register, Program or
will be reversed. Please refer to table 1 for more details. The
Erase cycle. During this time the device will ignore further
factory default setting for CMP is 0.
instructions except for the Read Status Register instruction
(see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the
program, erase, or write status register instruction has Note:
completed, the WIP bit will be cleared to a 0 state indicating 1. When APT is 0, BP2, BP1, BP0 won’t be changed after
the device is ready for further instructions. power-on.
2. When APT is 1 and CMP is 0, all BP2, BP1, BP0 will be
WEL bit. The Write Enable Latch (WEL) bit is a read only bit set to 1 after power-on.
in the status register (b1) that is set to a 1 after executing a 3. When APT is 1 and CMP is 1, all BP2, BP1, BP0 will be
Write Enable Instruction. The WEL status bit is cleared to a 0 set to 0 after power-on.
when the device is write disabled. A write disable state
occurs upon power-up or after any of the following
instructions: Write Disable, Page Program, Dual Input Fast
Program, Quad Input Fast Program, Sector Erase, Block

A25L032 Series
Figure 5. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction (05h or 35h)
DI
Status Register 1 or 2 Out Status Register 1 or 2 Out

High Impedance
DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB

A25L032 Series
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new CMP, QE and SRP1 bits will be cleared to 0.
values to be written to the Status Register. Before it can be
As soon as Chip Select ( S ) is driven High, the self-timed
accepted, a Write Enable (WREN) instruction must
Write Status Register cycle (whose duration is tW) is initiated.
previously have been executed. After the Write Enable
While the Write Status Register cycle is in progress, the
(WREN) instruction has been decoded and executed, the
Status Register may still be read to check the value of the
device sets the Write Enable Latch (WEL).
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
The Write Status Register (WRSR) instruction is entered by
is 1 during the self-timed Write Status Register cycle, and is
driving Chip Select ( S ) Low, followed by the instruction 0 when it is completed. When the cycle is completed, the
code and the data byte on Serial Data Input (DI). Write Enable Latch (WEL) is reset.
The instruction sequence is shown in Figure 6. Only The Write Status Register (WRSR) instruction allows the
non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, user to change the values of the Block Protect (APT, CMP,
BP0 (bits 7, 6, 5, 4, 3, 2 of Status Register-1) and CMP, SEC, TB, BP2, BP1, BP0) bits, to define the size of the area
APT, SRP1 (bits 14, 10 and 8 of Status Register-2) can be that is to be treated as read-only, as defined in Table 1. The
written. All other Status Register bits are always read as ‘0’ Write Status Register (WRSR) instruction also allows the
and will not be affected by the Write Status Register user to set the Status Register Protect (SRP1, SRP0) bits.
instruction. Those bits are used in conjunction with the Write Protect
Chip Select ( S ) must be driven High after the eighth or ( W ) pin to disable writes to the Status Register. Factory
sixteenth bit of the data byte has been latched in. If not, the default for all Status Register bits are 0.
Write Status Register (WRSR) instruction is not executed.
If Chip Select ( S ) is driven high after the eighth clock the
Figure 6. Write Status Register (WRSR) Instruction Sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction (01h) Status Register In
DI 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
MSB
High Impedance
DO
Table 5. Protection Modes
SRP1 SRP0 W Status Register Description

Status Register is Writable (if the WREN instruction has set the WEL
0 0 X Software Protection bit). The values in the CMP, APT, SRP1, SRP0, SEC, TB, BP2,
BP1, BP0 bits can be changed.
Status Register is hardware write protected. The values in the CMP,
0 1 0 Hardware Protection APT, SRP1, SRP0, SEC, TB, BP2, BP1, BP0 bits cannot be
changed.
When W pin is high. Status Register is Writable (if the WREN
0 1 1 Software Protection instruction has set the WEL bit). The values in the CMP, APT,
SRP1, SRP0, SEC, TB, BP2, BP1, BP0 bits can be changed.
Status Register is permanently protected. The values in the CMP,
1 1 X One Time Program APT, SRP1, SRP0, SEC, TB, BP2, BP1, BP0 bits cannot be
changed.

A25L032 Series
Read Data Bytes (READ)
therefore, be read with a single Read Data Bytes (READ)
The device is first selected by driving Chip Select ( S ) Low.
The instruction code for the Read Data Bytes (READ) instruction. When the highest address is reached, the
instruction is followed by a 3-byte address (A23-A0), each bit address counter rolls over to 000000h, allowing the read
being latched-in during the rising edge of Serial Clock (C). sequence to be continued indefinitely.
Then the memory contents, at that address, is shifted out on The Read Data Bytes (READ) instruction is terminated by
Serial Data Output (DO), each bit being shifted out, at a driving Chip Select ( S ) High. Chip Select ( S ) can be driven
maximum frequency fR, during the falling edge of Serial Clock High at any time during data output. Any Read Data Bytes
(C). (READ) instruction, while an Erase, Program or Write cycle is
The instruction sequence is shown in Figure 7. The first byte in progress, is rejected without having any effects on the
addressed can be at any location. The address is cycle that is in progress.
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
Figure 7. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (03h) 24-Bit Address
DI 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
DO 7 6 5 4 3 2 1 0 7
MSB
Note: Address bits A23 to A22 are Don’t Care, for A25L032.

A25L032 Series
Read Data Bytes at Higher Speed (FAST_READ)
Speed (FAST_READ) instruction. When the highest address
is reached, the address counter rolls over to 000000h,
The instruction code for the Read Data Bytes at Higher
allowing the read sequence to be continued indefinitely.
Speed (FAST_READ) instruction is followed by a 3-byte
The Read Data Bytes at Higher Speed (FAST_READ)
address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then the instruction is terminated by driving Chip Select ( S ) High.
memory contents, at that address, is shifted out on Serial Chip Select ( S ) can be driven High at any time during data
Data Output (DO), each bit being shifted out, at a maximum output. Any Read Data Bytes at Higher Speed (FAST_READ)
frequency fC, during the falling edge of Serial Clock (C). instruction, while an Erase, Program or Write cycle is in
The instruction sequence is shown in Figure 8. The first byte progress, is rejected without having any effects on the cycle
addressed can be at any location. The address is that is in progress.
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher
Figure 8. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction (0Bh) 24-Bit Address
DI 23 22 21 3 2 1 0
MSB
High Impedance
DO
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
DI 7 6 5 4 3 2 1 0
Data Out 1 Data Out 2
DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB MSB

A25L032 Series
Read Data Bytes at Higher Speed by Dual Output (FAST_READ_DUAL_OUTPUT)
The FAST_READ_DUAL_OUTPUT (3Bh) instruction is This is accomplished by adding eight “dummy” clocks after
similar to the FAST_READ (0Bh) instruction except the data the 24-bit address as shown in figure 9. The dummy clocks
is output on two pins, IO0 and IO1, instead of just DO. This allow the device’s internal circuits additional time for setting
allows data to be transferred from the A25L032 at twice the up the initial address. The input data during the dummy
rate of standard SPI devices. clocks is “don’t care”. However, the IO0 and IO1 pins should
Similar to the FAST_READ instruction, the be high-impedance prior to the falling edge of the first data
FAST_READ_DUAL_OUTPUT instruction can operate at the out clock.
highest possible frequency of fC (See AC Characteristics).
Figure 9. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction (3Bh) 24-Bit Address
IO0 23 22 21 3 2 1 0
MSB
High Impedance
IO1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte DIO switches from input to output
IO0 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
IO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
MSB MSB MSB
Data Out 1 Data Out 2 Data Out 3 Data Out 4

A25L032 Series
Read Data Bytes at Higher Speed by Dual Input and Dual Output (FAST_READ_DUAL_INPUT_OUTPUT)
The FAST_READ_DUAL_INPUT_OUTPUT (BBh) instruction The lower nibble bits of the Mode (M3-0) bits are don’t care
is similar to the FAST_READ (0Bh) instruction except the (“x”). However, the IO pins should be high-impedance prior to
data is input and output on two pins, IO0 and IO1, instead of the falling edge of the first data out clock.
just DO. This allows data to be transferred from the A25L032 If the Mode bits (M5-4) equal “10” hex, then the chip is into
at twice the rate of standard SPI devices. “Continuous Read” Mode and the next
Similar to the FAST_READ instruction, the FAST_READ_DUAL_INPUT_OUTPUT instruction (after S
FAST_READ_DUAL_INPUT_OUTPUT instruction can
is raised and then lowered) does not require the BBh
operate at the highest possible frequency of fC (See AC
instruction code, as shown in figure 10-b. This reduces the
Characteristics). The FAST_READ_DUAL_INPUT_OUTPUT
instruction sequence by eight clocks and allows the address
instruction can further reduce instruction overhead through
setting the Mode bits (M7-0) after the input Address bits to be immediately entered after S is asserted low. If the
(A23-0), as shown in Figure 10-a. The upper nibble of the Mode bits (M5-4) are any value other than “10” hex, the next
Mode (M7-4) bits controls the length of the next instruction (after S is raised and then lowered) requires the
FAST_READ_DUAL_INPUT_OUTPUT instruction through first byte instruction code, thus returning to normal operation.
the inclusion or exclusion of the first byte instruction code.
Figure 10-a. FAST_READ_DUAL_INPUT_OUTPUT Instruction Sequence and Data-Out Sequence

(M5-4≠10h)
0 1 2 3 4 5 6 7 8 9 10 16 17 18 19
C
Instruction (BBh) 24-Bit Address
IO0 22 20 18 6 4 2 0
MSB
High Impedance
IO1 23 21 19 7 5 3 1
S
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
C
M7-0 DIO switches from input to output
IO0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
IO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
MSB MSB MSB MSB
Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5

A25L032 Series
Figure 10-b. FAST_READ_DUAL_INPUT_OUTPUT Instruction Sequence and Data-Out Sequence
Continuous Read Mode, (M5-4=10h)
0 1 2 3 4 … 7 8 9 10 11
C
24-Bit Address
IO0 22 20 18 6 4 2 0
IO1 23 21 19 7 5 3 1
S
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
C
M7-0 DIO switches from input to output
IO0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
IO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
MSB MSB MSB MSB
Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5

A25L032 Series
Read OTP (ROTP)
000000h, allowing the read sequence to be continued
indefinitely.
The instruction code for the Read OTP (ROTP) instruction is
The Read OTP (ROTP) instruction is terminated by driving
followed by a 3-byte address (A23- A0) and a dummy byte.
Each bit is latched in on the rising edge of Serial Clock (C). Chip Select ( S ) High. Chip Select ( S ) can be driven High at
Then the memory contents at that address are shifted out on any time during data output. Any Read OTP (ROTP)
Serial Data output (DO). instruction issued while an Erase, Program or Write Status
Each bit is shifted out at the maximum frequency, fC(Max.) on Register cycle is in progress, is rejected without having any
the falling edge of Serial Clock (C). effect on the cycle that is in progress.
The instruction sequence is shown in Figure 11.
The address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached, the address counter rolls over to
Figure 11. Read OTP (ROTP) instruction and data-out sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction 24-Bit Address
(4Bh or 48h)
DI 23 22 21 3 2 1 0
MSB
High Impedance
DO
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
DI 7 6 5 4 3 2 1 0
DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB MSB
Data Out 1 Data Out n
Note: A23 to A6 are don’t care. (1 ≤ n ≤ 64)

A25L032 Series
Program OTP (POTP)
The Program OTP instruction (POTP) is used to program at completed. At some unspecified time before the cycle is
most 64 bytes to the OTP memory area (by changing bits complete, the Write Enable Latch (WEL) bit is reset.
from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. To lock the OTP memory:
After the Write Enable (WREN) instruction has been decoded, Bit 0 of the OTP control byte, that is byte 63, (see Figure 12)
the device sets the Write Enable Latch (WEL) bit. is used to permanently lock the OTP memory array.
The Program OTP instruction is entered by driving Chip • When bit 0 of byte 63 = ’1’, the OTP memory array can be
Select ( S ) Low, followed by the instruction code, three programmed.
address bytes and at least one data byte on Serial Data input • When bit 0 of byte 63 = ‘0’, the OTP memory array are
(DI). read-only and cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to ‘0’,
Chip Select ( S ) must be driven High after the eighth bit of it can no longer be set to ‘1’.
the last data byte has been latched in, otherwise the Therefore, as soon as bit 0 of address 63h (control byte) is
Program OTP instruction is not executed. set to ‘0’, the 64 bytes of the OTP memory array become
The instruction sequence is shown in Figure 12. read-only in a permanent way.
As soon as Chip Select ( S ) is driven High, the self-timed Any Program OTP (POTP) instruction issued while an Erase,
Page Program cycle (whose duration is tPP) is initiated. While Program or Write Status Register cycle is in progress is
the Program OTP cycle is in progress, the Status Register rejected without having any effect on the cycle that is in
may be read to check the value of the Write In Progress progress.
(WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Program OTP cycle, and it is 0 when it is
Figure 12. Program OTP (POTP) instruction sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (42h) 24-Bit Address Data Byte 1
DI 23 22 21 3 2 1 0 7 6 5 0
4 3 2 1 0
MSB MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data Byte 2 Data Byte 3 Data Byte n
DI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB MSB
Note: A23 to A6 are don’t care. (1 ≤ n ≤ 64)
Figure 13. How to permanently lock the 64 OTP bytes

64 Data Byte OTP Control Byte
Byte Byte Byte Byte Byte

0 1 2 62 63
Bit Bit Bit Bit Bit Bit Bit Bit When bit 0 =0
7 6 5 4 3 2 1 0 the OTP bytes
become READ only

A25L032 Series
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed correctly within the same page. If less than 256
programmed in the memory (changing bits from 1 to 0). Data bytes are sent to device, they are correctly programmed
Before it can be accepted, a Write Enable (WREN) instruction at the requested addresses without having any effects on the
must previously have been executed. After the Write Enable other bytes of the same page.
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL). Chip Select ( S ) must be driven High after the eighth bit of the
last data byte has been latched in, otherwise the Page
The Page Program (PP) instruction is entered by driving Chip Program (PP) instruction is not executed.
Select ( S ) Low, followed by the instruction code, three
address bytes and at least one data byte on Serial Data Input As soon as Chip Select ( S ) is driven High, the self-timed
(DI). If the 8 least significant address bits (A7-A0) are not all Page Program cycle (whose duration is tPP) is initiated. While
zero, all transmitted data that goes beyond the end of the the Page Program cycle is in progress, the Status Register
current page are programmed from the start address of the may be read to check the value of the Write In Progress (WIP)
same page (from the address whose 8 least significant bits bit. The Write In Progress (WIP) bit is 1 during the self-timed
Page Program cycle, and is 0 when it is completed. At some
(A7-A0) are all zero). Chip Select ( S ) must be driven Low for unspecified time before the cycle is completed, the Write
the entire duration of the sequence. Enable Latch (WEL) bit is reset.
The instruction sequence is shown in Figure 14. If more than A Page Program (PP) instruction applied to a page which is
256 bytes are sent to the device, previously latched data are protected by the Block Protect (CMP, SEC, TB, BP2, BP1,
discarded and the last 256 data bytes are guaranteed to be BP0) bits (see table 1) is not executed.
Figure 14. Page Program (PP) Instruction Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (02h) 24-Bit Address Data Byte 1
DI 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
S
2072
2073
2074
2075
2076
2077
2078
2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data Byte 2 Data Byte 3 Data Byte 256
DI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB

A25L032 Series
Dual Input Fast Program (DIFP)
having any effects on the other bytes in the same page.
The Dual Input Fast Program (DIFP) instruction is very For optimized timings, it is recommended to use the Dual
similar to the Page Program (PP) instruction, except that the Input Fast Program (DIFP) instruction to program all
data are entered on two pins IO0 and IO1 instead of only one. consecutive targeted bytes in a single sequence rather to
Inputting the data on two pins instead of one doubles the using several Dual Input Fast Program (DIFP) sequences
data transfer bandwidth compared to the Page Program (PP) each containing only a few bytes.
instruction. Chip Select ( S ) must be driven High after the eighth bit of
The Dual Input Fast Program (DIFP) instruction is entered by the last data byte has been latched in, otherwise the Dual
driving Chip Select ( S ) Low, followed by the instruction code, Input Fast Program (DIFP) instruction is not executed.
three address bytes and at least one data byte on Serial As soon as Chip Select ( S ) is driven High, the self-timed
Data Output (IO0 and IO1). Page Program cycle (whose duration is tPP) is initiated. While
If the 8 least significant address bits (A7-A0) are not all zero, the Dual Input Fast Program (DIFP) cycle is in progress, the
all transmitted data that goes beyond the end of the current Status Register may be read to check the value of the Write
page are programmed from the start address of the same In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
page (from the address whose 8 least significant bits (A7-A0) during the self-timed Page Program cycle, and 0 when it is
are all zero). Chip Select ( S ) must be driven Low for the completed. At some unspecified time before the cycle is
entire duration of the sequence. completed, the Write Enable Latch (WEL) bit is reset.
The instruction sequence is shown in Figure 15. A Dual Input Fast Program (DIFP) instruction applied to a
If more than 256 bytes are sent to the device, previously page that is protected by the Block Protect (CMP, SEC, TB,
latched data are discarded and the last 256 data bytes are BP2, BP1, BP0) bits (see Table 1) is not executed.
guaranteed to be programmed correctly within the same
page. If less than 256 data bytes are sent to device, they are
correctly programmed at the requested addresses without
Figure 15. Dual Input Fast Program (DIFP) instruction sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction (A2h) 24-Bit Address
IO0 23 22 21 3 2 1 0
MSB
High Impedance
IO1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
IO0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
Data In 1 Data In 2 Data In 3 Data In 4 Data In 5 Data In 256
IO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
MSB MSB MSB MSB MSB MSB

A25L032 Series
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits
instruction is not executed. As soon as Chip Select ( S ) is
inside the chosen sector. Before it can be accepted, a Write
driven High, the self-timed Sector Erase cycle (whose
Enable (WREN) instruction must previously have been ex-
duration is tSE) is initiated. While the Sector Erase cycle is in
ecuted. After the Write Enable (WREN) instruction has been
progress, the Status Register may be read to check the value
decoded, the device sets the Write Enable Latch (WEL).
of the Write In Progress (WIP) bit. The Write In Progress
The Sector Erase (SE) instruction is entered by driving Chip
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
Select ( S ) Low, followed by the instruction code on Serial 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
Data Input (DI). Chip Select ( S ) must be driven Low for the
A Sector Erase (SE) instruction applied to a page which is
entire duration of the sequence.
protected by the Block Protect (CMP, SEC, TB, BP2, BP1,
The instruction sequence is shown in Figure 16. Chip Select
BP0) bits (see table 1) is not executed.
( S ) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Sector Erase
Figure 16. Sector Erase (SE) Instruction Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction (20h) 24-Bit Address
DI 23 22 21 3 2 1 0
MSB

A25L032 Series
Block Erase (BE)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside
the chosen block. Before it can be accepted, a Write Enable
driven High, the self-timed Block Erase cycle (whose duration
(WREN) instruction must previously have been executed.
is tBE) is initiated. While the Block Erase cycle is in progress,
After the Write Enable (WREN) instruction has been decoded,
the Status Register may be read to check the value of the
the device sets the Write Enable Latch (WEL).
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
The Block Erase (BE) instruction is entered by driving Chip
is 1 during the self-timed Block Erase cycle, and is 0 when it
Select ( S ) Low, followed by the instruction code on Serial is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a page which is
protected by the Block Protect (CMP, SEC, TB, BP2, BP1,
BP0) bits (see table 1) is not executed.
code has been latched in, otherwise the Block Erase
Figure 17. Block Erase (BE) Instruction Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
24-Bit Address
Instruction (D8h or 52h)
DI 23 22 21 3 2 1 0
MSB

A25L032 Series
Chip Erase (CE)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before code has been latched in, otherwise the Chip Erase
it can be accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
driven High, the self-timed Chip Erase cycle (whose duration
(WREN) instruction has been decoded, the device sets the
is tCE) is initiated. While the Chip Erase cycle is in progress,
Write Enable Latch (WEL).
the Status Register may be read to check the value of the
The Chip Erase (CE) instruction is entered by driving Chip
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
Select ( S ) Low, followed by the instruction code on Serial 1 during the self-timed Chip Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is ignored if one, or more,
sectors/blocks are protected.
Figure 18. Chip Erase (CE) Instruction Sequence
0 1 2 3 4 5 6 7
C
Instruction
(C7h or 60h)
DI

A25L032 Series
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only The Deep Power-down mode automatically stops at
way to put the device in the lowest consumption mode (the Power-down, and the device always Powers-up in the
Deep Power-down mode). It can also be used as an extra Standby mode.
software protection mechanism, while the device is not in The Deep Power-down (DP) instruction is entered by driving
active use, since in this mode, the device ignores all Write,
Chip Select ( S ) Low, followed by the instruction code on
Program and Erase instructions.
Serial Data Input (DI). Chip Select ( S ) must be driven Low for
Driving Chip Select ( S ) High deselects the device, and puts the entire duration of the sequence. The instruction sequence
the device in the Standby mode (if there is no internal cycle is shown in Figure 19.
currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be Chip Select ( S ) must be driven High after the eighth bit of the
entered by executing the Deep Power-down (DP) instruction, instruction code has been latched in, otherwise the Deep
to reduce the standby current (from ICC1 to ICC2, as specified in Power-down (DP) instruction is not executed. As soon as
DC Characteristics Table.). Chip Select ( S ) is driven High, it requires a delay of tDP
Once the device has entered the Deep Power-down mode, all before the supply current is reduced to ICC2 and the Deep
instructions are ignored except the Release from Deep Power-down mode is entered.
Power-down and Read Electronic Signature (RES) instruction. Any Deep Power-down (DP) instruction, while an Erase,
This releases the device from this mode. The Release from Program or Write Status Register cycle is in progress, is
Deep Power-down and Read Electronic Signature (RES) rejected without having any effects on the cycle that is in
instruction also allows the Electronic Signature of the device progress.
to be output on Serial Data Output (DO).
Figure 19. Deep Power-down (DP) Instruction Sequence
S
tDP
0 1 2 3 4 5 6 7
C
Instruction (B9h)
DI
Stand-by Mode Deep Power-down Mode

A25L032 Series
Read Device Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit This is followed by the 24-bit device identification, stored in
manufacturer identification code to be read, followed by two the memory, being shifted out on Serial Data Output (DO),
bytes of device identification. The manufacturer identification each bit being shifted out during the falling edge of Serial
is assigned by JEDEC, and has the value 37h. The device Clock (C).
identification is assigned by the device manufacturer, and The instruction sequence is shown in Figure 20. The Read
indicates the memory in the first byte (30h), and the memory Identification (RDID) instruction is terminated by driving Chip
capacity of the device in the second byte (16h for A25L032).
Any Read Identification (RDID) instruction while an Erase, or Select ( S ) High at any time during data output.
Program cycle is in progress, is not decoded, and has no
When Chip Select ( S ) is driven High, the device is put in the
effect on the cycle that is in progress.
Stand-by Power mode. Once in the Stand-by Power mode,
The device is first selected by driving Chip Select ( S ) Low. the device waits to be selected, so that it can receive, decode
Then, the 8-bit instruction code for the instruction is shifted in. and execute instructions.
Table 6. Read Identification (READ_ID) Data-Out Sequence
Manufacture Identification Device Identification

Manufacture ID Memory Type Memory Capacity
37h 30h 16h (A25L032)
Figure 20. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 21 22 23 24 25 26 29 30 31
C
Instruction (9Fh)
IO0
IO1 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0
High Impedance
Manufacture ID Memory Type Memory Capacity

A25L032 Series
Read Electronic Manufacturer ID & Device ID (REMS)
The Read Electronic Manufacturer ID & Device ID (REMS) If the one-byte address is set to 01h, then the device ID will
instruction allows the 8-bit manufacturer identification code to be read first and then followed by the Manufacturer ID. On
be read, followed by one byte of device identification. The the other hand, if the one-byte address is set to 00h, then the
manufacturer identification is assigned by JEDEC, and has Manufacturer ID will be read first and then followed by the
the value 37h for AMIC. The device identification is assigned device ID.
by the device manufacturer, and has the value 15h for The instruction sequence is shown in Figure 21. The Read
A25L032. Electronic Manufacturer ID & Device ID (REMS) instruction is
Any Read Electronic Manufacturer ID & Device ID (REMS)
instruction while an Erase, or Program cycle is in progress, is terminated by driving Chip Select ( S ) High at any time during
not decoded, and has no effect on the cycle that is in data output.
progress. When Chip Select ( S ) is driven High, the device is put in the
Stand-by Power mode. Once in the Stand-by Power mode,
The device is first selected by driving Chip Select ( S ) Low. the device waits to be selected, so that it can receive, decode
The 8-bit instruction code is followed by 2 dummy bytes and and execute instructions.
one byte address (A7~A0), each bit being latched-in on Serial
Data Input (DI) during the rising edge of Serial Clock (C).
Table 7. Read Electronic Manufacturer ID & Device ID (REMS) Data-Out Sequence
Manufacture Identification Device Identification
37h 15h (A25L032)
Figure 21. Read Electronic Manufacturer ID & Device ID (REMS) Instruction Sequence and Data-Out Sequence
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
C
Instruction (90h) 2 Dummy Bytes
DI 15 14 13 3 2 1 0
MSB
High Impedance
DO
S
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
ADD(1)
DI 7 6 5 4 3 2 1 0
Manufacturer ID Device ID
DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB
Notes:
(1) ADD=00h will output the manufacturer ID first and ADD=01h will output device ID first

A25L032 Series
Release from Deep Power-down and Read Electronic Signature (RES)
Once the device has entered the Deep Power-down mode, stored in the memory, is shifted out on Serial Data Output
all instructions are ignored except the Release from Deep (DO), each bit being shifted out during the falling edge of
Power-down and Read Electronic Signature (RES) Serial Clock (C).
instruction. Executing this instruction takes the device out of The instruction sequence is shown in Figure 22.
the Deep Power-down mode. The Release from Deep Power-down and Read Electronic
The instruction can also be used to read, on Serial Data Signature (RES) instruction is terminated by driving Chip
Output (DO), the 8-bit Electronic Signature, whose value for Select ( S ) High after the Electronic Signature has been read
A25L032 is 15h. at least once. Sending additional clock cycles on Serial Clock
Except while an Erase, Program or Write Status Register (C), while Chip Select ( S ) is driven Low, cause the
cycle is in progress, the Release from Deep Power-down and
Electronic Signature to be output repeatedly.
Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and When Chip Select ( S ) is driven High, the device is put in the
can be applied even if the Deep Power-down mode has not Stand-by Power mode. If the device was not previously in the
been entered. Deep Power-down mode, the transition to the Stand-by
Any Release from Deep Power-down and Read Electronic Power mode is immediate. If the device was previously in the
Signature (RES) instruction while an Erase, Program or Write Deep Power-down mode, though, the transition to the Stand-
Status Register cycle is in progress, is not decoded, and has by Power mode is delayed by tRES2, and Chip Select ( S )
no effect on the cycle that is in progress. must remain High for at least tRES2 (max), as specified in AC
Characteristics Table . Once in the Stand-by Power mode,
The instruction code is followed by 3 dummy bytes, each bit the device waits to be selected, so that it can receive, decode
being latched-in on Serial Data Input (DI) during the rising and execute instructions.
edge of Serial Clock (C). Then, the 8-bit Electronic Signature,
Figure 22. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and
Data-Out Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
C
Instruction (ABh) 3 Dummy Bytes tRES2
DI 23 22 21 3 2 1 0
MSB
High Impedance
DO 7 6 5 4 3 2 1 0
MSB
Deep Power-down Mode Stand-by Mode
Note: The value of the 8-bit Electronic Signature, for A25L032 is 15h.

A25L032 Series
Figure 23. Release from Deep Power-down (RES) Instruction Sequence
tRES1
0 1 2 3 4 5 6 7
C
Instruction (ABh)
DI
High Impedance
DO
Deep Power-down Mode Stand-by Mode
previously in the Deep Power-down mode, though, the

Driving Chip Select ( S ) High after the 8-bit instruction byte
transition to the Stand-by Power mode is delayed by tRES1,
has been received by the device, but before the whole of the
8-bit Electronic Signature has been transmitted for the first and Chip Select ( S ) must remain High for at least tRES1 (max),
time (as shown in Figure 23.), still insures that the device is as specified in AC Characteristics Table. Once in the
put into Stand-by Power mode. If the device was not pre- Stand-by Power mode, the device waits to be selected, so
viously in the Deep Power-down mode, the transition to the that it can receive, decode and execute instructions.
Stand-by Power mode is immediate. If the device was

A25L032 Series
High Performance Mode (A3h)
The High Performance Mode (HPM) instruction can be instruction is executed, the device will maintain a slightly
executed prior to Dual instructions if chip is operated at high higher standby current than standard SPI operation. The
frequencies. This instruction allows pre-charging of internal Release from Power-down (ABh) can be used to return to
charge pumps so the voltages required for accessing the standard SPI standby current (ICC1). In addition, Write Enable
Flash memory array are readily available. The instruction instruction (06h) and Power Down instruction (B9h) will also
sequence includes the A3h instruction code followed by three release the device from HPM mode back to standard SPI
dummy byte clocks shown in Fig.28. After the HPM standby state.
Figure 24. High Performance Mode Instruction Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction (A3) 3 Dummy Bytes tRES2
DI 23 22 21 3 2 1 0
MSB High Performance
Current
DO

A25L032 Series
Continuous Read Mode Reset (FFFFh)
Continuous Read Mode Reset instruction can be used to set Continuous Read Mode and allow Standard SPI instructions
mode bit M4 to 1, thus the device will release the Continuous to be recognized.
Read Mode and return to normal SPI operation, as shown in To reset “Continuous Read Mode” during Dual I/O operation,
Fig.29. sixteen clocks are needed to shift in instruction “FFFFh”.
If user wants to issue a new command after A25L032 is set Mode bit M5, M4 will be reset to 0 after power-on, so it’s
to Continuous Mode Read, it is recommended to issue a unnecessary to issue Continuous Read Mode Reset
Continuous Read Mode Reset instruction before any instruction even the controller resets while A25L032 is set to
command. Doing so will release the device from the Continuous Mode Read.
Figure 25. Continuous Read Mode Reset for Fast Read Dual I/O
Mode Bit Reset for Dual I/O

S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
C
I/O0 FFh FFh
I/O1 Do not care
I/O2 Do not care
I/O3 Do not care

A25L032 Series
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be tPUW after VCC passed the VWI threshold
- tVSL afterVCC passed the VCC(min) level
selected (that is Chip Select ( S ) must follow the voltage
These values are specified in Table 8.
applied on VCC) until VCC reaches the correct value:
If the delay, tVSL, has elapsed, after VCC has risen above
VCC (min) at Power-up, and then for a further delay of tVSL VCC(min), the device can be selected for Read instructions
VSS at Power-down even if the tPUW delay is not yet fully elapsed.
Usually a simple pull-up resistor on Chip Select ( S ) can be At Power-up, the device is in the following state:
used to insure safe and proper Power-up and Power-down. The device is in the Standby mode (not the Deep
To avoid data corruption and inadvertent write operations Power-down mode).
during power up, a Power On Reset (POR) circuit is included. The Write Enable Latch (WEL) bit is reset.
The logic inside the device is held reset while VCC is less than Normal precautions must be taken for supply rail decoupling,
the POR threshold value, VWI – all operations are disabled, to stabilize the VCC feed. Each device in a system should
and the device does not respond to any instruction. have the VCC rail decoupled by a suitable capacitor close to
Moreover, the device ignores all Write Enable (WREN), the package pins. (Generally, this capacitor is of the order of
Program OTP (POTP), Page Program (PP), Dual Input Fast 0.1µF).
Program (DIFP), Sector Erase (SE), Block Erase (BE), Chip At Power-down, when VCC drops from the operating voltage,
Erase (CE) and Write Status Register (WRSR) instructions to below the POR threshold value, VWI, all operations are
until a time delay of tPUW has elapsed after the moment that disabled and the device does not respond to any instruction.
VCC rises above the VWI threshold. However, the correct (The designer needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in progress, some
operation of the device is not guaranteed if, by this time, VCC
data corruption can result.)
is still below VCC(min). No Write Status Register, Program or
Erase instructions should be sent until the later of:
Figure 26. Power-up Timing
VCC
VCC(max)
VCC(min)
Reset tVSL Read Full Device Access

State Access
allowed
VWI
tPUW
time

A25L032 Series
Table 8. Power-Up Timing
Symbol Parameter Min. Max. Unit
tVSL VCC(min) to S Low 10 μs
tPUW Time Delay Before Write Instruction 3 ms
VWI Write Inhibit Threshold Voltage 2.3 2.5 V
Note: These parameters are characterized only.
INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains
00h (all Status Register bits are 0).

A25L032 Series
Absolute Maximum Ratings* *Comments
Storage Temperature (TSTG) . . . . . . . . . . -65°C to + 150°C Stressing the device above the rating listed in the Absolute
Lead Temperature during Soldering (Note 1) Maximum Ratings" table may cause permanent damage to
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . the device. These are stress ratings only and operation of
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC+0.6V the device at these or any other conditions above those
Transient Voltage (<20ns) on Any Pin to Ground Potential . . indicated in the Operating sections of this specification is not
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VCC+2.0V implied. Exposure to Absolute Maximum Rating conditions
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . -0.6V to +4.0V for extended periods may affect device reliability. Refer also
Electrostatic Discharge Voltage (Human Body model) to the AMIC SURE Program and other relevant quality
(VESD) (Note 2) . . . . . . . . . . . . . . . . . . . -2000V to 2000V documents.
Notes:
1. Compliant with JEDEC Std J-STD-020B (for small body,
Sn-Pb or Pb assembly).
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω ,
R2=500Ω)
DC AND AC PARAMETERS
This section summarizes the operating and measurement Measurement Conditions summarized in the relevant tables.
conditions, and the DC and AC characteristics of the device. Designers should check that the operating conditions in their
The parameters in the DC and AC Characteristic tables that circuit match the measurement conditions when relying on
follow are derived from tests performed under the the quoted parameters.
Table 9. Operating Conditions

VCC Supply Voltage 2.7 3.6 V
TA Ambient Operating Temperature –40 85 °C
Table 10. Data Retention and Endurance

Parameter Condition Min. Max. Unit
Erase/Program Cycles At 85°C 100,000 Cycles
Data Retention At 85°C 20 Years
Table 11. Capacitance

Symbol Parameter Test Condition Min. Max. Unit
COUT Output Capacitance (DO) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz.

A25L032 Series
Table 12. DC Characteristics
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current ±2 µA

ILO Output Leakage Current ±2 µA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 15 µA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 15 µA
C= 0.1VCC / 0.9.VCC at 100MHz, DO = open 24 mA
Operating Current (Read) C= 0.1VCC / 0.9.VCC at 50MHz, DO = open 21 mA
ICC3
C= 0.1VCC / 0.9.VCC at 33MHz, DO = open 17 mA
Operating Current (Dual Read) C= 0.1VCC / 0.9.VCC at 100MHz, IO0, IO1 = open 26 mA
ICC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 12 mA
ICC6 Operating Current (SE) S = VCC 25 mA
ICC7 Operating Current (BE) S = VCC 25 mA
VIL Input Low Voltage –0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6mA 0.4 V
VOH Output High Voltage IOH = –100µA VCC–0.2 V
Note: 1. This is preliminary data at 85°C
Table 13. AC Measurement Conditions

CL Load Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Reference Voltages VCC / 2 V
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 27. AC Measurement I/O Waveform
Input Levels Input and Output

Timing Reference Levels
0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC

A25L032 Series
Table 14. AC Characteristics
Symbol Alt. Parameter Min. Typ. Max. Unit
fC fC Clock Frequency for all instructions, except READ (03h) D.C. 100 MHz
fR Clock Frequency for READ (03h) instruction D.C. 65 MHz
1
tCH tCLH Clock High Time 5 ns
1
tCL tCLL Clock Low Time 5 ns
tCLCH 2 Clock Rise Time3 (peak to peak) 0.1 V/ns
tCHCL 2 Clock Fall Time3 (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 5 ns
tCHSL S Not Active Hold Time (relative to C) 5 ns
tDVCH tDSU Data In Setup Time 3 ns

tCHDX tDH Data In Hold Time 3 ns
tCHSH S Active Hold Time (relative to C) 5 ns
tSHCH S Not Active Setup Time (relative to C) 5 ns
tSHSL tCSH S Deselect Time 30 ns
tSHQZ 2 tDIS Output Disable Time 7 ns

tCLQV tV Clock Low to Output Valid 7 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 5 ns
tCHHH HOLD Hold Time (relative to C) 5 ns
tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns
tHHQX 2 tLZ HOLD to Output Low-Z 7 ns
2
tHLQZ tHZ HOLD to Output High-Z 7 ns
4
tWHSL Write Protect Setup Time 20 ns
tSHWL 4 Write Protect Hold Time 100 ns
tDP 2 S High to Deep Power-down Mode 3 µs
tRES1 2 S High to Standby Mode without Electronic Signature Read 1 µs
tRES2 2 S High to Standby Mode with Electronic Signature Read 1 µs

tW Write Status Register Cycle Time 5 20 ms
Page Program Cycle Time 2 6 ms
tpp
Program OTP Cycle Time 2 3 ms
tSE Sector Erase Cycle Time 80 200 ms
tBE Block Erase Cycle Time 0.5 2 s
tCE Chip Erase Cycle Time of A25L032 32 64 s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for WRSR instruction when Status Register Protect bits (SRP1, SRP0) = (0, 1)

A25L032 Series
Figure 28. Serial Input Timing
tSHSL
S
tCHSL tSLCH tCHSH tSHCH
C
tCHCL
tDVCH
tCHDX tCLCH
DI MSB IN LSB IN
High Impedance
DO
Figure 29. Write Protect Setup and Hold Timing during WRSR when (SRP1, SRP0) = (0, 1)
W
tSHWL
tWHSL
DI
High Impedance
DO

A25L032 Series
Figure 30. Hold Timing
tHLCH
tCHHL tHHCH
C
tCHHH
DI
tHLQZ tHHQX
DO
HOLD
Figure 31. Output Timing
tCH
C
DI ADDR.LSB IN
tCLQV tCLQV tCL tSHQZ
tCLQX tCLQX
DO LSB OUT
tQLQH
tQHQL

A25L032 Series
Part Numbering Scheme
A25 X X XXX X X X X / X
Packing
Blank: for DIP8
G: for SOP8 In Tube
Q: for Tape & Reel
Package Material
Blank: normal
F: PB free
Temperature*
Blank = 0°C ~ +70°C
U = -40°C ~ +85°C
E = -40°C ~ +85°C (With AEC-Q100
Grade 3 Certification)
Package Type
Blank = DIP8
M = 209 mil SOP 8
Q4 = WSON 8 (6*5mm)
Device Version*
Device Density
512 = 512 Kbit (4KB uniform sectors)
010 = 1 Mbit (4KB uniform sectors)
Quad SPI Operation

Q = Support Quad SPI Operation
Blank = Do not support Quad SPI Operation
Device Voltage
L = 2.7-3.6V
Device Type
A25 = AMIC Serial Flash
* Optional

A25L032 Series
Ordering Information
Part No. Speed (MHz) Active Read Program/Erase Standby Package

Current Current Current
Max. (mA) Max. (mA) Max. (μA)
A25L032-F 8 Pin Pb-Free DIP (300 mil)
A25L032-UF 8 Pin Pb-Free DIP (300 mil)
A25L032-EF 8 Pin Pb-Free DIP (300 mil)
A25L032M-F 8 Pin Pb-Free SOP (209mil)

100 24 15 15
A25L032M-UF 8 Pin Pb-Free SOP (209mil)
A25L032M-EF 8 Pin Pb-Free SOP (209mil)
8 Pin Pb-Free WSON (6*5mm)

A25L032Q4-F Operating temperature range:
-40°C ~ +85°C
-U is for industrial operating temperature range: -40°C ~ +85°C

-E is for industrial operating temperature range: -40°C ~ +85°C (With AEC-Q100 Grade 3 Certification)

A25L032 Series
Package Information
P-DIP 8L Outline Dimensions unit: inches/mm
Dimensions in inches Dimensions in mm

Symbol Min Nom Max Min Nom Max
A - - 0.180 - - 4.57
A1 0.015 - - 0.38 - -
A2 0.128 0.130 0.136 3.25 3.30 3.45
B 0.014 0.018 0.022 0.36 0.46 0.56
B1 0.050 0.060 0.070 1.27 1.52 1.78
B2 0.032 0.039 0.046 0.81 0.99 1.17
C 0.008 0.010 0.013 0.20 0.25 0.33
D 0.350 0.360 0.370 8.89 9.14 9.40
E 0.290 0.300 0.315 7.37 7.62 8.00
E1 0.254 0.260 0.266 6.45 6.60 6.76
e1 - 0.100 - - 2.54 -
L 0.125 - - 3.18 - -
EA 0.345 - 0.385 8.76 - 9.78
S 0.016 0.021 0.026 0.41 0.53 0.66
Notes:
1. Dimension D and E1 do not include mold flash or protrusions.
2. Dimension B1 does not include dambar protrusion.
3. Tolerance: ±0.010” (0.25mm) unless otherwise specified.

A25L032 Series
Package Information
SOP 8L (209mil) Outline Dimensions unit: mm
8 5
E1
E
1 4
C
D
A2
A
GAGE PLANE
SEATING PLANE
A1
e b θ
0.25
Dimensions in mm
Symbol
Min Nom Max
A 1.75 1.95 2.16
A1 0.05 0.15 0.25
A2 1.70 1.80 1.91
b 0.35 0.42 0.48
C 0.19 0.20 0.25
D 5.13 5.23 5.33
E 7.70 7.90 8.10
E1 5.18 5.28 5.38
e 1.27 BSC
L 0.50 0.65 0.80
θ 0° - 8°
Notes:
Maximum allowable mold flash is 0.15mm at the package
ends and 0.25mm between leads

A25L032 Series
Package Information
WSON 8L (6 X 5 X 0.8mm) Outline Dimensions unit: mm/mil
0.25 C
e
b
4 1 0.25 C 1 2 3 4
L
C0.30
D
D2
Pin1 ID Area
5 8 8 7 6 5
E E2
// 0.10 C
A
A1
y C
A3
Seating Plane
Dimensions in mm Dimensions in mil

Symbol
Min Nom Max Min Nom Max
A 0.700 0.750 0.800 27.6 29.5 31.5
A1 0.000 0.020 0.050 0.0 0.8 2.0
A3 0.203 REF 8.0 REF
b 0.350 0.400 0.480 13.8 15.8 18.9
D 5.900 6.000 6.100 232.3 236.2 240.2
D2 3.200 3.400 3.600 126.0 133.9 141.7
E 4.900 5.000 5.100 192.9 196.9 200.8
E2 3.800 4.000 4.200 149.6 157.5 165.4
L 0.500 0.600 0.750 19.7 23.6 29.5
e 1.270 BSC 50.0 BSC
y 0 - 0.080 0 - 3.2
Note:
1. Controlling dimension: millimeters
2. Leadframe thickness is 0.203mm (8mil)

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A25L032 Series

32Mbit Low Voltage, Dual-I/O Serial Flash Memory

Rev. No. History Issue Date Remark

(December, 2014, Version 1.5) AMIC Technology Corp.

32Mbit Low Voltage, Dual-I/O Serial Flash Memory

(December, 2014, Version 1.5) 1 AMIC Technology Corp.

Pin No. Pin Name I/O Description

1 S I Chip Select Input

2 DO (IO1) I/O Data Output (Data Input Output 1)(1)

3 W I Write Protect Input

5 DI (IO0) I/O Data Input (Data Input Output 0) (1)

6 C I Serial Clock Input

7 HOLD I Hold Input

8 VCC Power Supply

DI (IO0) I/O Shift Register

Address register 256 Byte Status

(December, 2014, Version 1.5) 2 AMIC Technology Corp.

(December, 2014, Version 1.5) 3 AMIC Technology Corp.

Figure 1. SPI Modes Supported

(December, 2014, Version 1.5) 4 AMIC Technology Corp.

Figure 2. Hold Condition Activation

(December, 2014, Version 1.5) 5 AMIC Technology Corp.

(December, 2014, Version 1.5) 6 AMIC Technology Corp.

Status Register Content (32M-Bit) Memory Protection

(December, 2014, Version 1.5) 7 AMIC Technology Corp.

Status Register Content (32M-Bit) Memory Protection

(December, 2014, Version 1.5) 8 AMIC Technology Corp.

Table 2. Memory Organization

Block Sector Address range Block Sector Address range

1023 3FF000h 3FFFFFh 335 14F000h 14FFFFh

992 3E0000h 3E0FFFh 304 130000h 130FFFh

288 120000h 120FFFh

448 1C0000h 1C0FFFh 271 10F000h 10FFFFh

432 1B0000h 1B0FFFh 255 FF000h FFFFFh

26 240 F0000h ...

416 1A0000h 1A0FFFh 239 EF000h EFFFFh

25 224 E0000h E0FFFh

400 190000h 190FFFh 223 DF000h DFFFFh

24 208 D0000h D0FFFh

384 180000h 180FFFh 207 CF000h CFFFFh

23 192 C0000h C0FFFh

368 170000h 170FFFh 191 BF000h BFFFFh

22 176 B0000h B0FFFh

352 160000h 160FFFh 175 AF000h AFFFFh

21 160 A0000h A0FFFh

336 150000h 150FFFh

(December, 2014, Version 1.5) 9 AMIC Technology Corp.

Block Sector Address range Block Sector Address range

159 9F000h 9FFFFh 63 3F000h 3FFFFh

112 70000h 70FFFh 16 10000h 10FFFh

96 60000h 60FFFh 4 04000h 04FFFh

(December, 2014, Version 1.5) 10 AMIC Technology Corp.

(December, 2014, Version 1.5) 11 AMIC Technology Corp.

Table 3. Instruction Set

One-byte Address Dummy Data

Note: (1) Dual Output Data

(December, 2014, Version 1.5) 12 AMIC Technology Corp.

Figure 3. Write Enable (WREN) Instruction Sequence