CHAPTER 04: Peripherals Interfacing With 8086 and Applications
CHAPTER 04: Peripherals Interfacing With 8086 and Applications
CHAPTER 04: Peripherals Interfacing With 8086 and Applications
8086-Interrupt structure.
Programmable peripheral Interface 8255.
Programmable interval Timer 8254.
Elementary features of 8259A and 8257 and interface.
Interfacing 8255, 8254 with 8086 and their applications.
University Questions
1. Write a program to blink bit 4 of port C using BSR mode of 8255 [5M_May-2015]
2. Draw and explain interrupt structure of 8086 with its IVT. [10M_May-2015, Dec_2015
3. Explain Mode 0 and Mode 1 of 8254 Timer/Counter IC with the help of timing diagram.
[10M_May-2015]
4. Explain different modes of operation of 8257 DMA controller. [10M_May-2015,May-
2017]
5. Explain the importance of DMA controller. Explain method of its interfacing with
8086. [10M_Dec-2015, Dec-2016,Dec-2017]
6. Explain in brief about programmable interval timer 8254. [5M_May-2016]
7. Explain 8086 interrupt structure and its method of interfacing with 8086
microprocessor with a suitable example.(any one interrupt) [10M_May-2016,May-
2018]
8. Explain in brief about programmable peripheral interface 8255. [5M_Dec-2016]
9. Write control word of 8255 to initialize port A as input port, port B and C as output port
group A and B in mode 0.[5M_May-2017]
10. State purpose of interfacing 8259 PIC to 8086. Explain interfacing of 8086-minimum
mode and 8259 single mode.[10M_May-2017]
11. What are the different types of interrupts supported by 8086 and explain IVT.
[10M_May-2017,Dec-2017]
12. Write control word of 8255 to initialize port A as input port, port B and C as output port
group A in mode 0 and Group B in mode 1.[5M_Dec-2017]
13. Explain Bit Set Reset mode of 8255 with application. [10M_Dec-2017]
14. Explain input output control word format of 8255.
Write control word of 8255 to initialize port A as input port, port B and C as output port
group A and B in mode 0. [10M_May-2018]
An interrupt is a condition that halts the microprocessor temporarily to work on a different task
and then return to its previous task. Interrupt is an event or signal that request to attention of
CPU. This halt allows peripheral devices to access the microprocessor.
Whenever an interrupt occurs the processor completes the execution of the current instruction
and starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a
program that tells the processor what to do when the interrupt occurs. After the execution of
ISR, control returns back to the main routine where it was interrupted.
The following image shows the types of interrupts we have in a 8086 microprocessor −
The different types of interrupts present in 8086 microprocessor are given by:
1. Hardware interrupt - 8086 has two pins to accept hardware interrupts, NMI and INTR.
2. Software Interrupts - These interrupts are caused by writing the software interrupt
instruction INT n where ‘n’ can be any value from 0 to 255 (00H to FFH). Hence all 256
interrupts can be invoked by software.
3. Error conditions (Exception or types) - 8086 is interrupted when some special
conditions occur while executing certain instructions in the program. Example: An error
in division automatically causes the INT 0 interrupt.
1. Hardware Interrupts –
Hardware interrupts are those interrupts which are caused by any peripheral device by sending
a signal through a specified pin to the microprocessor. There are two hardware interrupts in
8086 microprocessor. They are:
(A) NMI (Non Maskable Interrupt) – It is a single pin non-maskable hardware interrupt
which cannot be disabled. It is the highest priority interrupt in 8086 microprocessor. After its
2. Software Interrupts –
These are instructions that are inserted within the program to generate interrupts. There are 256
software interrupts in 8086 microprocessor. The instructions are of the format INT type where
type ranges from 00 to FF. The starting address ranges from 00000 H to 003FF H. These are 2
byte instructions.
The total interrupt vector table is divided into three groups namely,
A. Dedicated interrupts (INT 0…..INT 4)
B. Reserved interrupts (INT 5…..INT 31)
C. Available interrupts (INT 32…..INT 225
In an 8086 Interrupt system the first 1 Kbyte of memory from 00000H to 003FFH is reserved
for storing the starting addresses of interrupt service routines. This block of memory is often
called the interrupt vector table or the interrupt pointer table. Since 4 bytes are required to store
the CS and IP values for each interrupt service procedure, the table can hold the starting
addresses for 256 interrupt service routines. Following figure shows how the 256 interrupt
pointers are arranged in the memory table.
The control word format of the 8255 is shown in Fig. below. The contents of the control register
are called the control word that specifies the input/ output functions of each port.
Port-C operates in BIT SET/RESET (BSR) mode with D7=0 as shown in above figure.
The BSR Mode in no way affects the functioning of port-A and port-B. Following steps are
essential to communicate with the peripherals through the ports of the 8255.
Determine address of ports-A, B, or C and of the control register according to the chip
select logic and the address lines A1 and A0.
Write the control word in the control word register.
Write input/output instructions in order to communicate with the peripherals through
ports-A, B, and C of the 8255.
The Intel 8254 are Programmable Interval Timers (PITs), which perform timing and
counting functions using three 16-bit counters.
The timer has three counters, numbered 0 to 2. Each channel can be programmed to operate
in one of six modes. Once programmed, the channels operate independently.
Each counter has two input pins – "CLK" (clock input) and "GATE" – and one pin, "OUT",
for data output. The three counters are 16-bit down counters independent of each other,
and can be easily read by the CPU.
Data bus buffer contains the logic to buffer the data bus between the microprocessor and
the internal registers. It has 8 input pins, usually labelled as D7-D0, where D7 is the MSB.
Read/write logic has 5 pins, which are listed below. The "X" denotes X is an active low
signal.
RD: read signal, WR: write signal, CS: chip select signal, A0, A1: address lines
Operation mode of the PIT is changed by setting the above hardware signals. For example,
to write to the Control Word Register, one needs to set CS=0, RD=1, WR=0, A1=A0=1.
The control word register contains the programmed information which will be sent (by the
microprocessor) to the device. It defines how each channel of the PIT logically works.
Each access to these ports takes about 1 µs.
The Control Word Register is selected by the Read/Write Logic when A1, A0 are 11.
To initialize the counters, the microprocessor must write a control word (CW) in this register.
Control Word of 8254 decide the operating mode of 8254.
Counter selection is also done using CWR of 8254.
OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the
one-shot pulse, and will remain low until the counter reaches zero.
Initially value of OUT is low. When counting is enabled, it becomes high and this process
repeats periodically. Value of count = Input Frequency / Output Frequency. This mode works
as a frequency divider.
Counting is enabled when GATE = 1 and disabled when GATE = 0. This mode is used to
generate square waveform and time period (equal to count) is generated.
If N is count and is even then ontime of wave = N/2 and offtime = N/2
If N is odd the ontime = (N + 1) / 2 and offtime = (N – 1) / 2
In this mode counting is enabled by using GATE = 1 and disabled by GATE = 0. Initially value
of OUT is high and becomes low when value of count is at last stage. Count is reloaded again
for subsequent clock pulse.
OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial
count has expired, OUT will go low for one clock pulse and then go high again. After writing
the Control Word and initial count, the counter will not be loaded until the clock pulse after a
trigger.
Features of 8257
- It has four channels which can be used over four I/O devices.
- Each channel has 16-bit address and 14-bit counter.
- Each channel can transfer data up to 64kb.
- Each channel can be programmed independently.
- Each channel can perform read transfer, write transfer and verify transfer operations.
- It generates MARK signal to the peripheral device that 128 bytes have been transferred.
- It requires a single phase clock.
- Its frequency ranges from 250Hz to 3MHz.
- It operates in 2 modes, i.e., Master mode and Slave mode.
Thus, with rotating priority in a single chip DMA system, any device requesting service is
guaranteed to be recognized after no more than three higher priority services have occurred.
This prevents any one channel from monopolizing the system. The rotating priority mode can
be set by writing logic ‘1’ in the bit 4 of the mode set register.
4. TC STOP Mode:
If the TC stop bit is set, a channel is disabled (i.e. its enable bit is reset) after the terminal count
(TC) output goes high, thus automatically preventing further DMA operation on that channel.
To enable DMA operation on the channel it is necessary to set enable bit of the corresponding
channel in the mode set register. If the TC STOP bit is not set, the occurrence of the TC output
has no effect on the channel enable bits.
The 8259A is a programmable interrupt controller specially designed to work with Intel
microprocessor 8080, 8085A, 8086, 8088. The main features of 8259A programmable interrupt
controller are given below:
1. It can handle eight interrupt inputs. This is equivalent to providing eight interrupt pins
on the processor in place of one INTR (in 8085A)/INT(in 8086) pin.
2. The chip can vector an interrupt request anywhere in the memory map from 0000H to
FFFFH in 8085A microprocessor. However, all the eight interrupts are spaced at an
interval of either four or eight locations. This eliminates the major drawback of 8085A
interrupts in which all interrupts are vectored to memory location on page 00 H i.e.,
TRAP, RST7.5, RST6.5 and RST5.5 are vectored to memory locations 0024H, 003CH,
0034H and 002CH respectively.
3. It can resolve eight levels of interrupt priorities in a variety of modes. The priorities of
interrupts can be changed under running condition. Some of the desired lower priority
interrupts may be allowed to be acknowledged during the service of higher priority
interrupts.
4. Each of the interrupt requests can be masked individually similar to RST7.5, RST6.5
and RST5.5 interrupts of 8085A.
5. The status of pending interrupts, in service interrupts, and masked interrupts can be read
at any time similar to RST interrupts of 8085A.
6. The chip can be programmed to accept interrupt requests either as level triggered or
edge triggered interrupt request unlike your RST interrupts where some are edge
triggered and some are level triggered. However, all interrupts must be either level
triggered or edge triggered.
7. If required, nine 8259As can be cascaded in a master-slave configuration mode to
handle 64 interrupt inputs. In this case, the interrupting devices send their interrupt
requests either to slave 8259A or to master 8259A directly. The slave 8259As send their
interrupt to master interrupt request inputs and the master will send a single interrupt to
microprocessor interrupt pin INTR/INT.
- The data lines of an 8259 are connected to the lower half of the system data bus; because
the 8086 expects to receive interrupt types on these lower eight data lines.
- RD and WR signals are connected to the system RD and WR lines.
- The interrupt request signal INT from the 8259 is connected to the INTR input of the
8086 and ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 from the 8086 is connected to ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 on the 8259A.
- As we are using single 8259 in the system SP/EN pin is tied high and CAS0-CAS2 lines
are left open.
- The eight IR inputs are available for interrupt signals.