3930

A3930 and A3931
Automotive 3-Phase BLDC Controller and MOSFET Driver
Features and Benefits Description

▪ High current 3-phase gate drive for N-channel MOSFETs The A3930 and A3931 are 3-phase brushless DC (BLDC) motor
▪ Synchronous rectification controllers for use with N-channel external power MOSFETs.
▪ Cross-conduction protection They incorporate much of the circuitry required to design a
▪ Charge pump and top-off charge pump for 100% PWM cost effective three-phase motor drive system, and have been
▪ Integrated commutation decoder logic specifically designed for automotive applications.
▪ Operation over 5.5 to 50 V supply voltage range A key automotive requirement is functionality over a wide
▪ Extensive diagnostics output input supply range. A unique charge pump regulator provides
▪ Provides +5 V Hall sensor power adequate (>10 V) gate drive for battery voltages down to 7 V,
▪ Low-current sleep mode and allows the device to operate with a reduced gate drive at
battery voltages down to 5.5 V. Power dissipation in the charge
pump is minimized by switching from a voltage doubling mode
at low supply voltage to a dropout mode at the nominal running
Package: 48 Lead LQFP with exposed voltage of 14 V.
thermal pad (suffix JP) A bootstrap capacitor is used to provide the above-battery
supply voltage required for N-channel MOSFETs. An internal
charge pump for the high-side drive allows for DC (100% duty
cycle) operation.
Internal fixed-frequency PWM current control circuitry can
be used to regulate the maximum load current. The peak
load current limit is set by the selection of an input reference
voltage and external sensing resistor. The PWM frequency is
set by a user-selected external RC timing network. For added
flexibility, the PWM input can be used to provide speed and
Approximate Scale 1:1 Continued on the next page…
Typical Application
3930-DS Rev. 4
A3930 and Automotive 3-Phase BLDC Controller
A3931 and MOSFET Driver
Description (continued)
torque control, allowing the internal current control circuit to set combination on the Hall inputs. In this state, the A3930 indicates
the maximum current limit. a logic fault, but the A3931 pre-positions the motor in an unstable
Efficiency is enhanced by using synchronous rectification. The starting position suitable for start-up algorithms in microprocessor-
power FETs are protected from shoot-through by integrated driven “sensor-less” control systems.
crossover control with dead time. The dead time can be set by a Both devices are supplied in a 48-pin LQFP with exposed thermal
single external resistor. pad. This is a small footprint (81 mm2) power package, that is lead
The A3930 and A3931 only differ in their response to the all-zero (Pb) free, with 100% matte tin leadframe plating.
Selection Guide
Part Number Option Packing Terminals Package
A3930KJPTR-T Hall short detection 1500 pieces/reel 48 LQFP surface mount
A3931KJPTR-T Pre-positioning 1500 pieces/reel
Absolute Maximum Ratings

Parameter Symbol Conditions Rating Units
Load Supply Voltage VBB VBB pin –0.3 to 50 V
VRESET RESET pin input –0.3 to 6 V
Logic Input/Output Voltage
Remaining logic pins –0.3 to 7 V
VGHx GHA, GHB, and GHC pins VSx to VSx+ 15 V
VGLx GLA, GLB, and GLC pins –5 to 16 V
VCx CA, CB, and CC pins VSx+ 15 V
Output Voltage Range VSx SA, SB, and SC pins –5 to 55 V
CSP, CSN, and LSS pins –4 to 6.5 V
CSO, VDSTH pins –0.3 to 6.5 V
VDRAIN pin –0.3 to 55 V
Operating Temperature Range (K) TA –40 to 150 °C
Junction Temperature TJ 150 °C
Overtemperature event not exceed-
ing 1 s, lifetime duration not exceed-
Transient Junction Temperature TtJ 175 °C
ing 10 hr; guaranteed by design
characterization
Storage Temperature Range TS –55 to 150 °C
AEC-Q100-002, all pins except CP1 2000 V
ESD Rating, Human Body Model
AEC-Q100-002, pin CP1 1000 V
ESD Rating, Charged Device Model AEC-Q100-011, all pins 1050 V
Allegro MicroSystems, Inc. 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
VBAT+
CP
VBB CP2 CP1 P
QV5 V5BD
Charge
VREG
+5V Ref Pump
V5 Regulator
CREG
CV5
VDRAIN
MODE
Phase A of three phases
COAST
Charge V5
Pump
BRAKE CA
Boostrap CBOOTA H1
RESET Monitor H2
H3
GHA
High-Side
DIR Drive &C
RGHA
&B
Control SA
H1
Logic
H2
&A
H3 VREG
GLA
Low-Side
RDEAD Drive RGLA
LSS
PWM
TACHO
R Blanking TEST
DIRO Q
S
ESF
Diagnostics and
Protection OSC
–UVLO CSP
FF1 –TSD
–Short to Supply RSENSE
–Short to Ground CSN
FF2 –Shorted Winding
–Low Load
Pad P
VDSTH RC REF CSOUT AGND
RT CT

ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1

Characteristics Symbol Test Conditions Min. Typ. Max. Units
Supply and Reference
Function correct, parameters not
VBB Functional Operating Range6 VBB 5.5 – 50 V
guaranteed
IBBQ RESET = High, outputs = Low – 11 14 mA
VBB Quiescent Current
IBBS RESET = Low, sleep mode – – 10 μA
V5 Quiescent Current IV5Q RESET = High, outputs = Low – – 5 mA
VBB ≥ 7.4 V, IREG = 0 to 15 mA 12.10 13 13.75 V
6 V < VBB < 7.4 V 2 × VBB
VREG Output Voltage VREG – – V
IREG = 0 to 15 mA –2.7
5.5 V < VBB < 6 V, IREG < 10 mA 9 10 – V
ID = 10 mA 0.4 0.7 1.0 V
Bootstrap Diode Forward Voltage VfBOOT
ID = 100 mA 1.5 2.2 2.8 V
rD(100 mA) = (VfBOOT(150 mA) –
Bootstrap Diode Resistance rD 6 10 20 Ω
VfBOOT(50 mA)) / 100 mA
Bootstrap Diode Current Limit IDBOOT 250 500 750 mA
Top-off Charge Pump Current Limit ITOCPM – 200 – μA
High-Side Gate Drive Static Load
RGSH 250 – – kΩ
Resistance
V5 Output Voltage V5 4.75 5 5.25 V
VBE of External Transistor QV5 VBEEXT – – 1 V
V5BD Base Drive Capability for QV52 I5BD – – –2 mA
Gate Output Drive
Turn-On Rise Time tr CLOAD = 3300 pF, 20% to 80% points – 60 – ns
Turn-Off Fall Time tf CLOAD = 3300 pF, 80% to 20% points – 40 – ns
TJ = 25C, IGHx = –150 mA 3 4 5 Ω
Pull-Up On Resistance RDS(on)UP
TJ = 150C, IGHx = –150 mA 4.6 5.6 6.6 Ω
TJ = 25C, IGLx = 150 mA 1 1.5 2 Ω
Pull-Down On Resistance RDS(on)DN
TJ = 150C, IGLx = 150 mA 1.5 2.3 3 Ω
Short-Circuit Current – Source2 ISC(source) TJ = 25C – –500 – mA
Short-Circuit Current – Sink ISC(sink) TJ = 25C – 850 – mA
tw < 10 μs
GHx Output Voltage VGHx VCx – 0.2 – – V
Bootstrap capacitor fully charged
VREG –
GLx Output Voltage VGLx – – V
0.2
Continued on the next page...

ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1

From Hall input change to unloaded
300 500 700 ns
gate output change
Turn-Off Propagation Delay tp(off)
From other control input change to
– 150 200 ns
unloaded gate output change
RDEAD = 5 kΩ – 180 – ns
RDEAD = 50 kΩ 835 960 1090 ns
Dead Time (turn-off to turn-on delay) tDEAD
RDEAD = 400 kΩ – 3.3 – μs
RDEAD = tied to V5 – 6 – μs
Logic Inputs and Outputs
FFx Fault Output (Open Drain) VOL IOL = 1 mA, fault asserted – – 0.4 V
FFx Fault Output Leakage Current2 IOH VO = 5 V, fault not asserted –1 – 1 μA
TACHO and DIRO Output High Voltage VOH IOH = –1 mA V5 – 1 V – – V
TACHO and DIRO Output Low Voltage VOL IOL = 1 mA – – 0.4 V
Input Low Voltage VIL – – 0.8 V
Input High Voltage (Except RESET) VIH 2 – – V
RESET Input High Voltage VIHR 2.2 – – V
Input Hysteresis VIHys 300 500 – mV
Input Current (Except H1, H2, H3, and
IIN –1 – 1 μA
RESET)2
RESET Input Pull-Down Resistor RPD VIN = 5 V – 50 – kΩ
Hx Input Pull-Up Resistor RPU VIN = 0 V – 100 – kΩ
Current Sense Differential Amplifier
Input Bias Current2 IIBS CSP = CSN = 0 V –250 –200 –150 μA
Input Offset Current2 IIOS CSP = CSN = 0 V –10 – 10 μA
CSP Input Resistance RCSP Measured with respect to AGND – 80 – kΩ
CSN Input Resistance RCSN Measured with respect to AGND – 4 – kΩ
VID = CSP – CSN, –1.3 V < CSP < 4 V,
Differential Input Voltage VID 0 – 200 mV
–1.3 V < CSN < 4 V
Output Offset Voltage VOOS CSP = CSN = 0 V 100 320 550 mV
Output Offset Voltage Drift VOOS(∆t) CSP = CSN = 0 V – 100 – μV/°C
Input Common Mode Range VCM CSP = CSN –1.5 – 4 V
Differential Input Voltage Gain AV 40 mV < VID < 175 mV, VCM in range 18.5 19 19.5 V/V
0 < VID < 40 mV,
Low Output Voltage Error Verr –20 – 20 mV
VCSOUT = (19 × VID) + VOOS + Verr
DC Common Mode Gain ACMdc CSP = CSN = 200 mV – –30 – dB
Source Resistance rCSOUT VCSOUT = 2 V, –2 mA < ICSOUT < 0.5 mA – 80 – Ω
V5
Output Dynamic Range VCSOUT –100 μA < ICSOUT < 100 μA 0.1 – V
– 0.2
Output Current – Sink ICSOUT(sink) VCSOUT= 2 V ±5% – 1 – mA
Output Current – Source2 ICSOUT(source) VCSOUT= 2 V ±5% – –19 – mA
Continued on the next page…

ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1

Supply Rejection PSRR CSP = CSN = AGND, 0 to 300 kHz – 45 – dB
Small Signal 3 dB Bandwidth Frequency f3dB VID=10 mVPP – 1.6 – MHz
To within 10%, VCSOUT = 1 VPP square
Settling Time tSETTLE – 400 – ns
wave
AC Common Mode Gain ACMac VICR= 250 mVPP, 0 to 1 MHz – –28 – dB
To within 100 mV, VICR= +4.1 to 0 V
Common Mode Recovery Time tCMrec – 1 – μs
step
10% to 90% points, VID= 0 to 175 mV
Output Slew Rate SR – 20 – V/μs
step
Input Overload Recovery Time tIDREC To within 10%, VID=250 mV to 0 V step – 500 – ns
Current Limit
Reference Comparator Input Offset Voltage VIOC –15 0 15 mV
Reference Input Clamp Voltage VREFC External pull-up to 5 V RREF = 200 kΩ 3.75 4 4.2 V
Comparator Blank Time tRC RT= 56 kΩ, CT = 470 pF – 650 – ns
REF Input Bias Current IIBREF – 0 – μA
RC Charge Current2 IRC –1.15 –1 –0.85 mA
RC HIgh Voltage Threshold VRCH 1.7 1.9 2.1 V
RC Low Voltage Threshold VRCL 0.6 0.7 0.8 V
Protection
VREG rising 7.5 8 8.5 V
VREG Undervoltage Lockout VREGUV
VREG falling 6.75 7.25 7.75 V
Bootstrap Capacitor Undervoltage Lockout VBOOTUV VBOOT falling, VCx – VSx 59 – 69 %
Bootstrap Capacitor Undervoltage Lockout
VBOOTUVHys VBOOTUVHys = %VREG – 13 – %
Hysteresis
V5 Undervoltage Lockout V5UV V5 falling 3.4 3.65 4.0 V
V5 Undervoltage Lockout Hysteresis V5UVHys 300 400 500 mV
VDSTH Input Voltage Range VDSTH 0.3 – 4 V
VDSTH Input Current2 IDSTH –1 – 1 μA
VDRAIN Input Voltage Range VDRAIN 7 VBB 45 V
VDSTH > 1 V – ±300 – mV
Short-to-Ground Threshold Offset3,5 VSTGO
VDSTH ≤ 1 V, 7 V ≤ VDRAIN ≤ 30 V –150 – 150 mV
VDSTH > 1 V – ±300 – mV
Short-to-Battery Threshold Offset4,5 VSTBO
VDSTH ≤ 1 V, 7 V ≤ VDRAIN ≤ 30 V –150 – 150 mV
Low Load Current Detection Voltage VCSOL – 500 – mV
Overtemperature Flag TJF Temperature increasing – 170 – ºC
Overtemperature Flag Hysteresis TJFHys Recovery = TJF – TJFHys – 15 – ºC
1Parameters are tested at 135C. Values at 150C are guaranteed by design or correlation.
2Forinput and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
3High side on. As V
SX decreases, fault occurs if VBAT – VSX > VSTG .
4Low side on. As V
SX increases, fault occurs if VSX – VLSS > VSTB .
5V
STG threshold is VDTSTH + VSTGO. VSTB threshold is VDTSTH + VSTBO .
6Function is correct but parameters not guaranteed above or below general limits (7 to 45 V).

Thermal Characteristics
THERMAL CHARACTERISTICS may require derating at maximum conditions, see Applications Information section
Characteristic Symbol Test Conditions* Value Units

4-layer PCB, based on JEDEC standard 23 ºC/W
Package Thermal Resistance RθJA 2-layer PCB, with 3 in.2 of copper area each side connected
44 ºC/W
by thermal vias
Die-to-Exposed Pad Thermal Resis-
RθJP 2 ºC/W
tance
*Additional thermal information available on Allegro Web site.
Power Dissipation versus Ambient Temperature
6.0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
5.0
4.0
R
3.0 QJ
A =
23
°C
/W
2.0 R
QJA
=4
4°C
/W
1.0
0
25 50 75 100 125 150
AMBIENT TEMPERATURE IN °C

Functional Description
Basic Operation AGND. If an external 5 V supply is not required, the V5BD pin
The A3930 and A3931 devices provide commutation and current and the V5 pin should be connected together.
control for 3-phase brushless DC (BLDC) motors with integrated CP1, CP2, and VREG The gate drive outputs are powered by
Hall-effect (HE) sensors. The motor current is provided by an an internal charge pump, which requires a pump capacitor, typi-
external 3-phase N-channel MOSFET bridge which is controlled cally 470 nF, CP, connected between the CP1 and CP2 pins. The
by the A3930/A3931, using fixed-frequency pulse width modu- output from the charge pump, 13 V nominal, is used to power
lation (PWM). The use of PWM with N-channel MOSFETs
each of the three high- and low-side driver pairs and is also
provides the most cost-effective solution for a high-efficiency
available on the VREG pin. A sufficiently large storage capaci-
motor drive.
tor, CREG, must be connected to this pin to provide the tran-
The A3930/A3931 provides all the necessary circuits to ensure sient charging current to the low-side drivers. The charge pump
that the gate-source voltage of both high-side and low-side exter- also provides the charging current for the bootstrap capacitors,
nal MOSFETs are above 10 V, at supply voltages down to 7 V. CBOOTx.
For extreme battery voltage drop conditions, functional operation
is guaranteed down to 5.5 V but with a reduced gate drive. The An additional “top-off” charge pump is provided for each high-
A3930/A3931 also decodes the commutation sequence from three side drive which allows the high-side drive to maintain the gate
HE sensors spaced at 120° in the electrical cycle, and ensure no voltage on the external FET indefinitely, ensuring so-called 100%
cross-conduction (shoot through) in the external bridge. Individ- PWM if required. This is a low-current trickle charge pump
ual pins provide direction, brake and coast control. (< 100 μA typical), and is only operated after a high-side driver
has been signaled to turn on. There is a small amount of bias
Motor current can be sensed by a low-value sense resistor,
current (< 20 μA) drawn from the Cx pin to operate the floating
RSENSE, in the ground connection to the bridge, amplified and
compared to a reference value. The A3930/A3931 then limits the high-side circuit, and the charge pump simply provides enough
bridge current on a cycle-by-cycle basis. Bridge current can also drive to ensure that the bootstrap voltage, and hence the gate volt-
be controlled using an external PWM signal with the internal cur- age, will not droop due to this bias current. The charge required
rent control either disabled or used to set the absolute maximum for initial turn-on of the high-side gate is always supplied by
motor current. Specific functions are described more fully in the bootstrap capacitor charge cycles.
following sections.
Hall Effect Sensor Inputs
Power Supplies H1, H2, and H3 Hall-effect sensor inputs are configured for
Only one power connection is required because all internal motors with 120° electrically-spaced HE sensors, but may be
circuits are powered by integrated regulators. The main power used for 60° electrical spacing with an external inverter. HE sen-
supply should be connected to VBB through a reverse battery sors usually require an additional pull-up resistor to be connected
protection circuit. between the sensor output and 5 V. This 5 V can be provided by
V5 and V5BD A 5 V supply for external pull-up and bias cur- the integrated 5 V regulator. HE inputs have a hysteresis of typi-
rents is provided by an integrated 5 V regulator controller and an cally 500 mV to reduce the effects of switching noise on the HE
external NPN transistor, QV5. The A3930/A3931 provides the connections to the motor. These inputs are also filtered to further
base drive current on the V5BD pin, and the 5 V reference on the reduce the effects of switching noise. The HE inputs are pulled-
V5 pin. This regulator is also used by the internal logic circuits up to 5 V inside the A3930/A3931 through a high value (100
and must always be decoupled by at least a 200 nF capacitor, kΩ typical) resistor in series with a diode. This internal pull-up
CV5, between the V5 pin and AGND. For stability, a 100 nF makes the HE input appear high if the Hall sensor signal is miss-
capacitor, C5BD, also should be connected between V5BD and ing, allowing detection of an HE input logic fault.

In order to provide a known start-up position for the motor, an which should have low-impedance traces to the FET bridge.
optional prepositioning function is available in the A3931. When
GHA, GHB, and GHC High-side gate drive outputs for exter-
the Hall inputs are all driven low (H1 = H2 = H3 = 0), the power
nal NMOS drivers. External series-gate resistors, RGATE, can
FETs in the A phase source current from the supply, and those in
be used to control the slew rate seen at the power-driver gate,
both the B and C phases sink current. This forces the motor to
thereby controlling the di/dt and dv/dt of the Sx inputs. Referring
move to an unstable position midway between two detent points
to table 2, GHx = 1 (high) means that the upper half (PMOS) of
and allows any start-up algorithm to ensure correct initial direc-
the driver is turned on, and that its drain will source current to the
tion of rotation. Note that this is only available in the A3931. The
gate of the high-side FET in the external motor-driving bridge.
A3930 will indicate a logic fault when all Hall inputs are driven GHx = 0 (low) means that the lower half (NMOS) of the driver
low. The commutation truth table for these inputs is shown in is turned on, and that its drain will sink current from the corre-
table 2. The inputs can also be driven directly from a microcon- sponding external FET gate circuit to the respective Sx pin.
troller or similar external circuit.
CA, CB, and CC High-side connections for the bootstrap
Gate Drive capacitors and positive supply for high-side gate drivers. The
The A3930/A3931 is designed to drive external N-channel power bootstrap capacitors, CBOOTx, are charged to approximately
MOSFETs. They supply the large transient currents necessary to VREG when the corresponding Sx terminal is low. When the Sx
quickly charge and discharge the gate capacitance of the external output swings high, the voltage on the Cx pin rises with the out-
FETs in order to reduce dissipation in the external FETs during put to provide the boosted gate voltage needed for the high-side
switching. The charge and discharge rate can be controlled using N-channel power MOSFETs.
external resistors in series with the connections to the gate of the
FETs. VDRAIN High impedance sense input (Kelvin connection) to
the top of the external FET bridge. This input allows accurate
RDEAD Cross-conduction is prevented by the gate drive circuits measurement of the voltage at the drain of the high-side FETs and
which introduce a dead time, tDEAD, between switching one FET should be connected directly to the bridge, close to the drain con-
off and the complementary FET on. The dead time is derived nections of the high-side FETs, with an independent trace.
from the value of a resistor, RDEAD, connected between the
RDEAD pin and AGND. If RDEAD is connected to V5, tDEAD LSS Low-side return path for discharge of the gate capacitors.
defaults to 6 μs typical. It is connected to the common sources of the low-side external
FETs through an independent low-impedance trace.
GLA, GLB, and GLC Low-side gate drive outputs for external
NMOS drivers. External series-gate resistors, RGATE, (as close Logic Control Inputs
as possible to the NMOS gate) can be used to control the slew Additional logic-level inputs are provided to enable specific
rate seen at the power-driver gate, thereby controlling the di/dt features described below. These logic inputs all have a nominal
and dv/dt of the Sx outputs. Referring to table 2, GLx = 1 (high) hysteresis of 500 mV to improve noise performance.
means that the upper half (PMOS) of the driver is turned on, and RESET Allows minimum current consumption from the VBB
that its drain will source current to the gate of the low-side FET supply. When RESET is low, all internal circuitry is disabled
in the external motor-driving bridge. GLx = 0 (low) means that including the V5 output. When coming out of sleep state, the
the lower half (NMOS) of the driver is turned on, and that its protection logic ensures that the gate drive outputs are off until
drain will sink current from the corresponding external FET gate the charge pump reaches proper operating conditions. The charge
circuit to the LSS pin. pump stabilizes in approximately 3 ms under nominal conditions.
SA, SB, and SC Directly connected to the motor, these RESET has an internal pull-down resistor, 50 kΩ typical.
terminals sense the voltages switched across the load. These However, to allow the A3930/A3931 to start-up without the
terminals are also connected to the negative side of the bootstrap need for an external logic input, the RESET pin can be pulled
capacitors and are the negative supply connections for the to the battery voltage with an external pull-up resistor. Because
floating high-side drivers. The discharge current from the high- RESET also has an internal clamp diode, 6 V typical, to limit the
side FET gate capacitance flows through these connections, input current, the value of the external pull-up resistor should be

greater than 20 kΩ. The upper limit for the resistor must be low RSENSE, connected between CSP and CSN, the output of the
enough to ensure that the input voltage reaches the input high sense amplifier will be approximately:
threshold, VINR.
VCSOUT ≈ (ILOAD × AV × RSENSE) + VOOS ,
COAST An active-low input which turns all FETs off without
where VOOS is the output offset voltage (the voltage at zero load
disabling the supplies or control logic. This allows the external
current), and AV is the differential voltage gain of the sense
FETs and the motor to be protected in case of a short circuit.
amplifier, 19 typical.
MODE Sets the current-decay method. Referring to table 3, when
Internal Current Control: REF A fixed reference voltage
in slow-decay mode, MODE = 1, only the high-side MOSFET
can be applied to provide a maximum current limit. A variable
is switched off during a PWM-off cycle. In the fast-decay mode,
reference voltage will provide a variable torque control. The
MODE = 0, the device switches both the high-side and low-side
output voltage of the current sense differential amplifier, VCSOUT ,
MOSFETs.
is compared to the reference voltage available on the REF
Slow decay allows a lower ripple current in the motor at the pin. When the outputs of the MOSFETs are turned on, current
PWM frequency, but reduces the dynamic response of the cur- increases in the motor winding until it reaches a trip point value,
rent control. It is suitable for motors which run at a more-or-less ITRIP, given by:
constant speed. Fast decay provides improved current-control
ITRIP = (VREF – VOOS) / (RSENSE × AV) .
dynamic response, but increases the motor current ripple. It is
suitable for motors used in start-stop and positioning applications. At the trip point, the sense comparator resets the source enable
latch, turning off the source driver. At this point, load inductance
DIR Determines the direction of motor torque output, as shown in
causes the current to recirculate until the start of the next PWM
table 2. For an unloaded, low-inertia motor, this will also usually
period.
be the direction of mechanical rotation. With a motor that has a
high inertial load, the DIR input can be used to apply a controlled The current path during recirculation is determined by the
breaking torque, when fast decay is used (MODE = 0). configuration of the MODE pin. Torque control can therefore be
implemented by varying the voltage on the REF pin, provided
BRAKE An active-low input that provides a braking function.
that the PWM input remains high. If direct control of the torque
When BRAKE = 0 (see table 3), all the low-side FETs are turned
or current by PWM input is desired, a voltage can be applied to
on and the high-side FETs are turned off. This effectively short- the REF pin to set an absolute maximum current limit. The REF
circuits the back EMF in the windings, and brakes the motor. input is internally limited to 4 V, which allows the use of a simple
The braking torque applied depends on the speed. RESET = 0 or pull-up resistor to V5, RREF, to set the maximum reference
COAST = 0 overrides BRAKE and coasts the motor. Note that voltage, avoiding the need for an externally generated reference
when BRAKE is used to dynamically brake the motor, the wind- voltage. RREF should have a value between 20 kΩ and 200 kΩ.
ings are shorted with no control over the winding current.
Internal PWM Frequency The internal oscillator frequency,
ESF The state of the enable stop on fault (ESF) pin determines fOSC, is determined by an external resistor, RT, and capacitor, CT,
the action taken when a short is detected. See the Diagnostics connected in parallel from the RC pin to AGND. The frequency
section for details. is approximately:
TEST Test is for Allegro production use and must be connected fOSC ≈ 1 / (RTCT + tBLANK + tDEAD) .
to AGND.
where fOSC in the range 20 to 50 kHz.
Current Regulation
PWM Input Can be used to control the motor torque by an exter-
Load current can be regulated by an internal fixed frequency
nal control circuit signal on the PWM pin. Referring to table 3,
PWM control circuit or by external input on the PWM pin.
when PWM = 0, the selected drivers are turned off and the load
Current Sense Amplifier: CSP, CSN, and CSOUT A dif- inductance causes the current to recirculate. The current path dur-
ferential current sense amplifier with a gain, AV, of 19 typical, is ing recirculation is determined by the configuration of the MODE
provided to allow the use of low-value sense resistors or current pin. Setting PWM = 1 will turn on selected drivers as determined
shunts as the current sensing elements. Because the output of by the Hx input logic. Holding PWM=1 allows speed and torque
this sense amplifier is available at CSOUT, it can be used for control solely by the internal current-limit circuit, using the volt-
either internal or external current sensing. With the sense resistor, age on the REF pin.

In some circumstances, it may be desirable to completely disable Note that there are some circumstances in which the direction
the internal PWM control. This can be done by pulling the RC reported on the DIRO output pin and the direction demanded
pin directly to AGND. This will disable the internal PWM oscil- on the DIR input pin may not be the same. This may happen if
lator and ensure that the output of the PWM latch is always high. the motor and load have reasonably high inertia. In this case,
changing the state of the DIR pin will cause the torque to reverse,
Blank Time When the source driver is turned on, a current spike braking the motor. During this braking, the direction indicated on
occurs due to the reverse-recovery currents of the clamp diodes the DIRO output will not change.
and switching transients related to distributed capacitance in the
load. To prevent this current spike from erroneously resetting ESF The state of the enable stop on fault (ESF) pin will deter-
the source enable latch, the current-control comparator output mine the action taken when a short is detected. For other fault
is blanked for a short period of time, tBLANK, when the source conditions, the action is defined by the type of fault. The action
driver is turned on. taken follows the states shown in table 1.
The length of tBLANK is different for internal versus external When ESF = 1, any short fault condition will disable all the
PWM. It is set by the value of the timing capacitor, CT, according gate drive outputs and coast the motor. This disabled state will
to the following formulas: be latched until the next phase commutation or until COAST or
RESET go low.
for internal PWM: tBLANK (μs) = 1260 × CT (μF), and
When ESF = 0, under most conditions, although the fault flags,
for external PWM: tBLANK (μs) = 2000 × CT (μF) . FF1 and FF2, are still activated, the A3930/A3931will not disrupt
A nominal CT value of 680 pF yields a tBLANK of 1.3 μs for normal operation and will therefore not protect the motor or the
external PWM, and 860 ns for internal PWM. The user must drive circuit from damage. It is imperative that the master control
ensure that CT is large enough to cover the current spike duration circuit or an external circuit take any necessary action when a
when using the internal sense amplifier. fault occurs, to prevent damage to components.
Diagnostics If desired, the active low COAST input can be used as a crude
disable circuit by connecting the fault flags FF1 and FF2 to the
Several diagnostic features integrated into the A3930/A3931 COAST input and a pull-up resistor to V5.
provide speed and direction feedback and indications of fault
conditions. FF1, FF2, and VDSTH Fault conditions are indicated by the
state of two open drain output fault flags, FF1 and FF2, as shown
TACHO and DIRO These outputs provide speed and direction in table 1. In addition to internal temperature, voltage, and logic
information based on the HE inputs from the motor. As shown in monitoring, the A3930/A3931 monitors the state of the external
figure 1, at each commutation point, the TACHO output changes MOSFETs and the motor current to determine if short circuit
state independent of motor direction. The DIRO output is updated faults occur or a low load condition exists. In the event that two
at each commutation point to show the motor direction. When or more faults are detected simultaneously, the state of the fault
the motor is rotating in the “forward” or positive direction, DIRO flags will be determined by a logical AND of the fault states of
will be high. When rotation is in the “reverse” or negative direc- each flag.
tion, DIRO will be low. The actual direction of rotation is deter-
mined from the sequence of the three Hall inputs, Hx. Forward • Undervoltage VREG supplies the low-side gate driver and the
is when the sequence follows table 2 top-to-bottom and reverse bootstrap charge current. It is critical to ensure that the voltages
when the sequence follows table 2 bottom-to-top. are sufficiently high before enabling any of the outputs. The
undervoltage circuit is active during power-up, and will pull
DIRO
both fault flags low and coast the motor (all gate drives low)
until VREG is greater than approximately 8 V. Note that this is
TACHO sufficient to turn on the external power FETs at a battery voltage
Commutation as low as 5.5 V, but will not normally provide the rated on-resis-
Points
tance of the FET. This could lead to excessive power dissipation
"Forward" Motor Rotation "Reverse" Motor Rotation
in the external FET.
Figure 1. Direction Indication Outputs

In addition to a monitor on VREG, the A3930/A3931 also be used to detect if an open load condition is present. If, during
monitors both the bootstrap charge voltage, to ensure sufficient a commutation period, the output from the sense amplifier does
high-side drive, and the 5 V reference voltage at V5, to ensure not go above a minimum value, VCSOL, FF1 will go low. No
correct logical operation. If either of these fall below the lock- further action will be taken.
out voltage level, the fault flags are set. Short Fault Operation Because motor capacitance may cause
• Overtemperature This event pulls both fault flags low but the measured voltages to show a fault as the phase switches, the
does not disable any circuitry. It is left to the user to turn off voltages are not sampled until one tDEAD interval after the exter-
the device to prevent overtemperature damage to the chip and nal FET is turned on.
unpredictable device operation.
If a short circuit fault occurs when ESF = 0, the external FETs
• Logic Fault: Hall Invalid The A3930 and the A3931 differ are not disabled by the A3930/A3931. Under some conditions,
slightly in how they handle error conditions on the Hall inputs, some measure of protection will be provided by the internal cur-
Hx. When all Hx are 1s, both devices evaluate this as an illegal rent limit but in many cases, particularly for a short to ground,
code, and they pull both fault flags, FFx, low and coast the mo- the current limit will provide no protection for the external
tor. This action can be used, if desired, to disable all FET drives FETs. To limit any damage to the external FETs or the motor, the
under bridge or motor fault conditions. The Hall logic fault A3930/A3931 can either be fully disabled by the RESET input
condition is not latched, so if the fault occurs while the motor is or all FETs can be switched off by pulling the COAST input low.
running, the external FETs will be reenabled, according to the Alternatively, setting ESF = 1 will allow the A3930/A3931 to dis-
commutation truth table (table 2), when the Hx inputs become able the outputs as soon as the fault is detected. The fault will be
valid. latched until any of the following conditions occur:
When all Hx are 0s, the A3930 handles this in the same manner a phase commutation
as all 1s, described in the preceding paragraph. The A3931, RESET goes low
however, evaluates this as a prepositioning code, and does not
register it as a fault. COAST goes low
The Hx inputs have pull-up resistors to ensure that a fault condi- This will allow a running motor to coast to the next phase
tion will be indicated in the event of an open connection to a commutation without the risk of damage to the external power
MOSFETs.
Hall sensor.
• Short to Ground A short from any of the motor phase con- Low Load Current Fault Operation No action is taken for
nections to ground is detected by monitoring the voltage across a low load current condition. If the low load occurs due to an
the top FETs in each phase using the appropriate Sx pin and the open circuit on a phase connection while the motor is running,
voltage at VDRAIN. This drain-source voltage is then compared the A3930/A3931 will continue to commutate the motor phases
to the voltage on the VDSTH pin. If the drain source voltage according to the commutation truth table, table 2.
exceeds the voltage at the VDSTH pin, FF2 will be pulled low. In some cases, this will allow the motor to continue operating at
• Short to Supply A short from any of the motor phase connec- a much reduced performance. The low load condition is checked
tions to the battery or VBB connection is detected by monitor- during a commutation period and is only flagged at the next com-
ing the voltage across the bottom FETs in each phase using the mutation event. The flag is cleared at the end of any subsequent-
appropriate Sx pin and the LSS pin. This drain-source voltage commutation period where no low load current fault is detected.
is then compared to the voltage on the VDSTH pin. If the drain If the motor stalls or is stationary, then the remaining phase con-
source voltage exceeds the voltage at the VDSTH pin, FF2 will nections will usually be insufficient to start rotating the motor. At
be pulled low. start-up or after a reset, the low load condition is flagged until the
• Shorted Motor Winding A short across the motor phase first time the motor current exceeds the threshold value, VCSOL.
winding is detected by monitoring the voltage across both the This allows detection of a possible open phase from startup, even
top and bottom FETs in each phase. This fault will pull FF2 low. if the motor is not able to start running.
• Low Load Current The sense amplifier output is monitored Note that a low load current condition can also exist if the motor
independently to allow detection of a low load current. This can being driven has no mechanical load.

Table 1. Fault Action Table

Action*
FF1 FF2 Fault
ESF = 0 ESF = 1
0 0 Undervoltage Disable Disable
0 0 Overtemperature No Action No Action
0 0 Logic Fault Disable Disable
1 0 Short to ground No Action Disable
1 0 Short to supply No Action Disable
1 0 Shorted motor winding No Action Disable
0 1 Low load current No Action No Action
1 1 None No Action No Action
*Disable indicates that all gate outputs are low and all MOSFETs are
turned off.
Table 2. Commutation Truth Table*

Device H1 H2 H3 DIR GLA GLB GLC GHA GHB GHC SA SB SC
Both 1 0 1 1 0 0 1 1 0 0 High Z Low
Both 1 0 0 1 0 0 1 0 1 0 Z High Low
Both 1 1 0 1 1 0 0 0 1 0 Low High Z
Both 0 1 0 1 1 0 0 0 0 1 Low Z High
Both 0 1 1 1 0 1 0 0 0 1 Z Low High
Both 0 0 1 1 0 1 0 1 0 0 High Low Z
A3930 0 0 0 X 0 0 0 0 0 0 Z Z Z
A3931 0 0 0 X 0 1 1 1 0 0 High Low Low
Both 1 1 1 X 0 0 0 0 0 0 Z Z Z
Both 1 0 1 0 1 0 0 0 0 1 Low Z High
Both 1 0 0 0 0 1 0 0 0 1 Z Low High
Both 1 1 0 0 0 1 0 1 0 0 High Low Z
Both 0 1 0 0 0 0 1 1 0 0 High Z Low
Both 0 1 1 0 0 0 1 0 1 0 Z High Low
Both 0 0 1 0 1 0 0 0 1 0 Low High Z
*X indicates “don’t care,” Z indicates high impedance state
Table 3. INPUT LOGIC

MODE PWM BRAKE COAST RESET Decay Mode of Operation
0 0 1 1 1 Fast PWM chop – current decay with opposite of selected drivers ON
0 1 1 1 1 Fast Peak current limit – selected drivers ON
1 0 1 1 1 Slow PWM chop – current decay with both low-side drivers ON
1 1 1 1 1 Slow Peak current limit – selected drivers ON
X X 0 1 1 n/a Brake mode - All low-side gates ON
X X X 0 1 X Coast mode - All gates OFF
X X X X 0 X Sleep mode – All gates OFF, low power state, 5 V OFF
*X indicates “don’t care”

Applications Information
Power Power Dissipation In applications where a high ambient tem-

All supply connections to the A3930/A3931 should have capaci- perature is expected the on-chip power dissipation may become
tors mounted between the supply pins and the ground pin. These a critical factor. Careful attention should be paid to ensure the
capacitors will provide the transient currents which occur during operating conditions allow the A3930/A3931 to remain in a safe
switching and decouple any voltage transients on the pin from the range of junction temperature.
main supply. The power consumed, PTOT , by the A3930/A3931 can be esti-
VBB Decouple with at least a 100 nF ceramic capacitor mounted mated using the following formulas:
between the VBB pin and the AGND pin. A larger electrolytic PTOT = PBIAS + PCPUMP + PSWITCHING ,
capacitor, typically 10 μF, in parallel with the ceramic capacitor PBIAS = VBB × IBB ,
is also recommended. where IBB is 3 mA, typical, and
VREG Supplies current for the gate-drive circuit. As the gates PCPUMP = (2 × VBB–VREG) × IAV
are driven high, they require current from an external capacitor where VBB < 15 V, or
connected to VREG to support the transients. This capacitor PCPUMP = (VBB–VREG) × IAV
should be placed as close as possible to the VREG pin with the where VBB > 15 V, and
ground connection close to the AGND pin. Its value should be at IAV = QGATE × N × fPWM ,
least 20 times larger than the bootstrap capacitor. The capacitor PSWITCHING = QGATE × VREG × N × fPWM × Ratio
should have a very low series resistance (ESR) and inductance where N = 2 for slow decay, or N = 4 for fast decay, and
(ESL) to avoid large voltage drops during the initial transient. Ratio = 10 / (RGATE + 10)
The optimum capacitor type is a high quality ceramic such as
X7R. However, when the required capacitance is too large, an Bootstrap Capacitors
aluminium electrolytic capacitor may be used, with a smaller Bootstrap Capacitor Selection The value for CBOOT must
ceramic capacitor (≈100 nF) in parallel. be correctly selected to ensure proper operation of the device. If
the value is too large, time will be wasted charging the capacitor,
V5 When the 5V regulator is used with an external pass transistor
resulting in a limit on the maximum duty cycle and PWM
to provide power to other circuits, a 10 μF decoupling capacitor
frequency. If the value is too small, there can be a large voltage
should be connected between the V5 pin and AGND as close to
drop at the time when the charge is transferred from CBOOT to the
the pins as possible. If an electrolytic capacitor is used, then a
MOSFET gate.
100 nF ceramic capacitor should be added in parallel. To improve
stability, a 100 nF capacitor also should be connected between To keep the voltage drop small, QBOOT  QGATE . A factor of 20 is
the V5BD pin and AGND. If 5V is not required for external a reasonable value. To calculate CBOOT, the following formulas
circuits, the external pass transistor may be omitted, but in that can be used:
case, V5 must connected directly to V5BD and decoupled with at
QBOOT = CBOOT × VBOOT ,
least a 220 nF capacitor between V5 and AGND.
= QGATE × 20,
AGND The A3930/A3931 has a single ground connection at the therefore
AGND pin. The design ensures that only the operating current CBOOT = QGATE × 20 / VBOOT
for the controller stage passes through this pin. The charge and The voltage drop on the Cx pin as the MOSFET is being turned
discharge current for the external FETs does not pass though this on can be approximated by:
pin. The AGND pin is the ground reference for the current trip
threshold, the VDS monitor threshold, and the timing components. ΔV = QGATE / CBOOT
It should therefor be kept as quiet as possible. A suggested ground Bootstrap Charging It is good practice to ensure that the high-
connection scheme is described in the layout section below. side bootstrap capacitor, CBOOT, is completely charged before a

high-side PWM cycle is requested. The minimum time required A3931 will not limit the current. Short-circuit detection will still
to charge the capacitor is approximated by: be available in case of faults. The output of the sense amplifier is
also available, but provision must be made in the external control
tCHARGE(min) ≈ CBOOT × ΔV /250 mA
circuits to ignore (blank) the transients at the switching points.
At power-on, and when the drivers have been disabled for a long
External and Internal Combined PWM Control Where
time, the CBOOT may be completely discharged. In these cases,
external PWM control is used but current limitation is still
ΔV can be considered to be the full high-side drive voltage,
required, internal PWM current control can be used at the
12 V. Otherwise, ΔV is the amount of voltage dropped during the
charge transfer, which should be 400 mV or less. The capacitor is same time as external PWM control. To do so, usually the
charged whenever the Sx pin is pulled low via a GLx PWM cycle, internal PWM frequency is set lower than the external PWM
and current flows from VREG through the internal bootstrap frequency. This allows the external PWM signal to dominate and
diode circuit to CBOOT. synchronize the internal PWM circuit. It does this by discharging
the timing capacitor, CT, when the PWM pin is low. When
Bootstrap Charge Monitor The A3930 and A3931 provide internal and external PWM control are used together, all control
automatic bootstrap capacitor charge management. The boot- features of the A3930/A3931 are available and active, including:
strap capacitor voltage for each phase, VBOOTx , is continuously dead time, current comparator, and comparator blanking.
checked to ensure that it is above the bootstrap undervoltage
threshold, VBOOTUV. If VBOOT drops below this threshold, the PWM Frequency Should be set high enough to avoid any
A3930 and A3931 will turn on the necessary low-side FET until audible noise, but low enough to ensure adequate charging of the
the VBOOT exceeds VBOOTUV plus the hysteresis, VBOOTUVHys . boot capacitor, CBOOT. The external resistor RT and capacitor
The minimum charge time is typically 7 μs, but may be longer for CT, connected in parallel from the RC pin to AGND, set the
very large values of the bootstrap capacitor (CBOOT >1000 nF). If PWM frequency to approximately:
VBOOT does not exceed VBOOTUV within approximately 200 μs, fOSC ≈ 1 / (RTCT + tBLANK + tDEAD) .
an undervoltage fault will be flagged, as shown in table 1.
RT should be in the range of 5 to 400 kΩ.
PWM Control
PWM Blank The timing capacitor, CT, also serves as the
The A3930 and A3931 have the flexibility to be used in many means to set the blank time duration. tBLANK. At the end of the
different motor control schemes. The internal PWM control can PWM off-cycle, a high-side gate selected by the commutation
be used to provide fully integrated, closed-loop current control. logic turns on. At this time, large current transients can occur
Alternatively, current-mode or voltage-mode control are possible during the reverse recovery time of the intrinsic source drain
using external control circuits with either the DIR or the PWM body diodes of the external power MOSFETs. To prevent false
input pins. tripping of the current-sense comparator, the output of the current
Internal PWM Control The internal PWM current control comparator is ignored during the blank time.
function is useful in applications where motor torque control The length of tBLANK is different for internal versus external
or simple maximum current limitation is required. However,
PWM. It is set by the value of the timing capacitor, CT, according
for motor speed control applications, it is usually better to use
to the following formulas:
external PWM control either as a closed- or open-loop system.
for internal PWM: tBLANK (μs) = 1260 × CT (μF), and
External PWM Control When external PWM control is used, it
is possible to completely disable the internal PWM control circuit for external PWM: tBLANK (μs) = 2000 × CT (μF) .
by connecting the RC pin to AGND.
A nominal CT value of 680 pF will give a blanking time of 1.3 μs
With the internal control disabled, however, care should be taken for external PWM and 860 ns for internal PWM. The user must
to avoid excessive current in the power FETs because the A3930/ ensure that CT is large enough to cover the current-spike duration.

Note that this blank time is only used to mask the internal cur- Synchronous Rectification To reduce power dissipation in
rent comparator. If the current sense amplifier output, CSOUT, the external MOSFETs, the A3930/A3931 control logic turns
is being used in an external PWM control circuit, then it will on the appropriate low-side and high-side driver during the load
be necessary to externally generate a blank time for that control current recirculation PWM-off cycle. Synchronous rectification
loop. allows current to flow through the FET selected by the MODE
pin setting during the decay time, rather than through the source-
Dead Time The potential for cross-conduction occurs with
drain body diode. The body diodes of the recirculating power
synchronous rectification, direction changes, PWM, or after a
FETs conduct only during the dead time that occurs at each PWM
bootstrap capacitor charging cycle. To prevent cross-conduction
transition. For internal current control using fast decay mode,
in any phase of the power FET bridge, it is necessary to have a
reversal of load current is prevented by turning off synchronous
dead-time delay, tDEAD, between a high- or low-side turn-off and
rectification when a zero current level is detected. For external
the next turn-on event. tDEAD is in the range of between 96 ns and
PWM control using fast decay mode, the load current will not be
6.3 μs, and is set by the value of a resistor, RDEAD, between the
limited to zero but will rise to the set current limit in the reverse
RDEAD pin and the GND pin. The maximum dead time of typi-
direction before disabling synchronous rectification.
cally 6μs can be set by leaving the RDEAD pin unconnected, or
connected to the V5 pin. Braking. The A3930 and A3931 provide dynamic braking by
forcing all low-side MOSFETs on, and all high-side MOSFETs
At 25°C, the value of tDEAD (μs) can be approximated by:
off. This effectively short-circuits the back EMF of the motor,
tDEAD(nom) ≈ 0.1 + 33 / (5 + IDEAD), which forces a reverse current in the windings, and creating a
breaking torque.
IDEAD = 2000 / RDEAD
During braking, the load current can be approximated by:
where IDEAD is in μA, and RDEAD is between 5 and 400 kΩ. The
greatest accuracy is obtained with values of RDEAD between IBRAKE ≈ VBEMF / RLOAD
10 and 100 kΩ.
Because the load current does not flow through the sense resistor,
The choice of power MOSFET and external series gate resistance RSENSE, during a dynamic brake, care must be taken to ensure
determines the selection of RDEAD. The dead time should be that the power MOSFET maximum ratings are not exceeded.
made long enough to cover the variation of the MOSFET gate
It is possible to apply a PWM signal to the BRAKE input to
capacitance and the tolerances of the series gate resistance, both
limit the motor braking current. However, because there is
external and internal to the A3930/A3931.
no measurement of this current, the PWM duty cycle must be
Current
determined for each set of conditions. Typically the duty cycle
Trip Points of such a brake PWM input would start at a value which limits
GHx the current and then drops to 0%, that is, BRAKE goes to low, to
tDEAD tDEAD hold the motor stationary.
GLx Setting RESET = 1 and COAST = 0 overrides BRAKE and turns
all motor bridge FETs off, coasting the motor.
+V
Driving a Full-Bridge. The A3930 and A3931 may be used
VRCH to drive a full-bridge (for example, a brush DC motor load) by
RC hard-wiring a single state for the Hall inputs and leaving the
corresponding phase driver outputs floating. For example, with a
VRCL configuration of H1 = H2 = 1, and H3 = 0, the outputs CC, GHC,
SC, and GLC would be floated, according to the commutation
0
tBLANK truth table, table3, which indicates a state of high-impedence (Z)
tRC Note: For reasons of for SC with that Hall input configuration. The DIR input
clarity, t DEAD is shown
tOSC
exaggerated. controls the motor rotation, while the PWM and MODE
inputs control the motor current behavior, as described in the
Figure 2. Internal PWM RC Timing input logic table, table 3.

Circuit Layout 6. The AGND pin should be connected by an independent low

Because this is a switch-mode application, where rapid current impedance trace to the Supply common at a single point.
changes are present, care must be taken during layout of the 7. Check the peak voltage excursion of the transients on the
application PCB. The following points are provided as guidance LSS pin with reference to the AGND pin using a close-
for layout (refer to figure 3). Following all guidelines will not grounded (tip and barrel) probe. If the voltage at LSS
always be possible. However, each point should be carefully exceeds the absolute maximum specified in this datasheet,
considered as part of any layout procedure. add additional clamping, capacitance or both between the
Ground connection layout recommendations: LSS pin and the AGND pin.
1. Sensitive connections such as RDEAD and VDSTH, which
Other layout recommendations:
have very little ground current, should be referenced to the
Quiet ground, which is connected independently closest to 1. Gate charge drive paths and gate discharge return paths may
the AGND pin. The components associated with these sensi- carry large transient current pulses. Therefore, the traces
tive pins should never be connected directly to the Supply from GHx, GLx, Sx, and LSS should be as short as possible
common or to the Power ground; they must be referenced to reduce the inductance of the circuit trace.
directly to the AGND pin. 2. Provide an independent connection from LSS to the common
2. Supply decoupling for the supply pins VBB, VREG, and point of the power bridge. It is not recommended to connect
V5 should be connected to Controller Supply ground, which LSS directly to the AGND pin, as this may inject noise into
is connected independently, close to the AGND pin. The sensitive functions such as the dead-timer. The LSS connec-
decoupling capacitors should also be connected as close as tion should not be used for the CSP connection.
possible to the corresponding supply pin. 3. The inputs to the sense amplifier, CSP and CSN, should be
3. The oscillator timing components can be connected to Quiet independent traces and for best results should be matched in
ground or Controller Supply ground. They should not be length and route.
connected to the Supply common or the Power ground. 4. Minimize stray inductance by using short, wide copper runs
4. The exposed thermal pad on the package should be con- at the drain and source terminals of all power FETs. This
nected to the AGND pin and may form part of the Controller includes motor lead connections, the input power bus, and
Supply ground. the common source of the low-side power FETs. This will
5. If the layout space is limited, then the Quiet ground and the minimize voltages induced by fast switching of large load
Controller Supply ground may be combined, provided that currents.
the ground return of the dead-time resistor, RDEAD, is close 5. Consider the use of small (100 nF) ceramic decoupling
to the AGND pin. capacitors across the source and drain of the power FETs

to limit fast transient voltage spikes caused by trace induc-

tance.
6. Ensure that the TEST pin is connected to AGND. This pin is
used for production test only.
The above are only recommendations. Each application is differ-

ent and may encounter different sensitivities. A driver running
with a few amperes will be less susceptible than one running with
150 A, and each design should be tested at the maximum current,
to ensure any parasitic effects are eliminated.
VBB VDRAIN
+ Supply
GHC
VREG
GHB
GHA
A3930
V5 A3931
SA
SB Motor
SC
RC GLA
VDSTH GLB
GLC
RDEAD
LSS
AGND
RSENSE
Optional components
Quiet Ground
to limit LSS transients Supply
Power Ground
Common
Controller Supply Ground
Figure 3. Supply and Ground Connections

Gate Drive Outputs Sense Amplifier

VREG
Cx
18 V 18 V 160μA 76k
22V
GHx 18 V
4 k7
CSN
18 V
19 V 22V 160μA CSOUT
Sx
4 k7
20 V CSP
VREG 8.5 V 8.5 V
18 V 2V
18 V
72 k7
32.4 k7
GLx
20 V
4.6 k7
LSS
Supplies REF
CP1 CP2 VDRAIN VBB V5 V5BD
3 k7
REF
19 V 19 V
6V 10 V 8V 8.5 V
18 V 19 V 19 V
20 V 20 V
Logic Inputs Hall Sensor Inputs V5 Reset Input
COAST
ESF
BRAKE 3 k7 100 k7 3 k7
H1 3 k7 RESET
DIR
H2
PWM
H3
MODE
8V 8.5 V 6V 6V 50 k7
8V 8.5 V
VDS Monitor Threshold Input Oscillator RC Pin Fault Output

V5
FF1 100 7
1 k7 40 k7
FF2
VDSTH
1 k7
RC
8V 8V
8V 8.5 V
8V 8.5 V
RDEAD Logic Output V5
2V
100 7
100 7
RDEAD TACHO
DIRO
8V 8.5 V 8V 8V
Figure 4. Input and Output Structures

Pin-out Diagrams
JP Package
26 GHC
32 GHA
29 GHB
34 GLC
36 GLA
35 GLB
27 CC
33 CA
30 CB
25 SC
31 SA
28 SB
NC 37 Low 24 VDRAIN
LSS 38 Side Bootstrapped 23 VDSTH
Drives High-Side Drives
ESF 39 22 CSP
VREG 40 21 CSN
Current
AGND 41 Charge Sense 20 REF
Pump
CP1 42 19 CSOUT
CP2 43 18 RDEAD
DIRO 44 17 TEST
VBB 45 Control 16 RC
COAST 46 Logic 15 MODE
NC 47 Hall 14 PWM
NC 48 13 NC
H1 10
H3 12
H2 11
NC 1
RESET 2
V5BD 3
V5 4
FF2 5
FF1 6
TACHO 7
BRAKE 8
DIR 9
Terminal List Table

Number Name Description Number Name Description
1 N.C. No connection 25 SC Motor connection phase C
2 RESET Control for sleep mode 26 GHC High-side gate drive phase C
3 V5BD 5V regulator base drive 27 CC Bootstrap capacitor phase C
4 V5 5V regulator reference 28 SB Motor connection phase B
5 FF2 Fault flag 2 29 GHB High-side gate drive phase B
6 FF1 Fault flag 1 30 CB Bootstrap capacitor phase B
7 TACHO Speed output 31 SA Motor connection phase A
8 BRAKE Brake input 32 GHA High-side gate drive phase A
9 DIR Direction control input 33 CA Bootstrap capacitor phase A
10 H1 Hall sensor input 34 GLC Low-side gate drive phase C
11 H2 Hall sensor input 35 GLB Low-side gate drive phase B
12 H3 Hall sensor input 36 GLA Low-side gate drive phase A
13 N.C. No connection 37 N.C. No connection
14 PWM Control input 38 LSS Low-side source
15 MODE Decay control input 39 ESF Enable stop on fault input
16 RC PWM oscillator control input 40 VREG Gate drive supply output
17 TEST Test pin; tie to AGND 41 AGND Analog ground
18 RDEAD Dead time setting 42 CP1 Pump capacitor
19 CSOUT Current sense output 43 CP2 Pump capacitor
20 REF Current limit setting 44 DIRO Direction output
21 CSN Current sense input – 45 VBB Supply voltage
22 CSP Current sense input + 46 COAST Coast input
23 VDSTH Fault threshold voltage 47 N.C. No connection
24 VDRAIN High-side drain voltage sense 48 N.C. No connection
– Pad Thermal dissipation, tie to AGND

Package JP, 48-pin LQFP with Exposed Thermal Pad
0.30
9.00 ±0.20 0.50

1.70
7.00 ±0.20 7º
4° ±4
0º
+0.05
0.15 –0.06
B C
9.00 ±0.20 7.00 ±0.20
5.00±0.04 5.00 8.60
0.60 ±0.15
48 A (1.00)
48
1 2
5.00±0.04 0.25 1 2
SEATING PLANE
5.00
GAGE PLANE
8.60
C PCB Layout Reference View

48X C
SEATING
0.08 C PLANE
For Reference Only
0.22 ±0.05 0.50 (reference JEDEC MS-026 BBCHD)
1.60 MAX Dimensions in millimeters
1.40 ±0.05 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.10 ±0.05
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
QFP50P900X900X160-48M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Copyright ©2006-2010, Allegro MicroSystems, Inc.

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:

www.allegromicro.com


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A3930 and A3931

Automotive 3-Phase BLDC Controller and MOSFET Driver

Features and Benefits Description

Approximate Scale 1:1 Continued on the next page…

Absolute Maximum Ratings

Allegro MicroSystems, Inc. 2

Functional Block Diagram

VBB CP2 CP1 P

Phase A of three phases

Allegro MicroSystems, Inc. 3

ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1

Continued on the next page...

Allegro MicroSystems, Inc. 4

ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1

Continued on the next page…

Allegro MicroSystems, Inc. 5

ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1

Allegro MicroSystems, Inc. 6

Characteristic Symbol Test Conditions* Value Units

Power Dissipation versus Ambient Temperature

Allegro MicroSystems, Inc. 7

Allegro MicroSystems, Inc. 8

Allegro MicroSystems, Inc. 9

Allegro MicroSystems, Inc. 10

Figure 1. Direction Indication Outputs

Allegro MicroSystems, Inc. 11

Allegro MicroSystems, Inc. 12

Table 1. Fault Action Table

Table 2. Commutation Truth Table*

Table 3. INPUT LOGIC

Allegro MicroSystems, Inc. 13

Power Power Dissipation In applications where a high ambient tem-

Allegro MicroSystems, Inc. 14

Allegro MicroSystems, Inc. 15

Allegro MicroSystems, Inc. 16

Circuit Layout 6. The AGND pin should be connected by an independent low

Allegro MicroSystems, Inc. 17

to limit fast transient voltage spikes caused by trace induc-

The above are only recommendations. Each application is differ-

Figure 3. Supply and Ground Connections

Allegro MicroSystems, Inc. 18

Gate Drive Outputs Sense Amplifier

Logic Inputs Hall Sensor Inputs V5 Reset Input

VDS Monitor Threshold Input Oscillator RC Pin Fault Output

RDEAD Logic Output V5

Figure 4. Input and Output Structures

Allegro MicroSystems, Inc. 19

COAST 46 Logic 15 MODE

Terminal List Table

Allegro MicroSystems, Inc. 20

Package JP, 48-pin LQFP with Exposed Thermal Pad

9.00 ±0.20 0.50

C PCB Layout Reference View

Copyright ©2006-2010, Allegro MicroSystems, Inc.

For the latest version of this document, visit our website:

Allegro MicroSystems, Inc. 21

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