SN65176B, SN75176B

SLLS101G – JULY 1985 – REVISED JULY 2021

SNx5176B Differential Bus Transceivers

1 Features 3 Description
• Bidirectional transceivers The SN65176B and SN75176B differential bus
• Meet or exceed the requirements of ANSI transceivers are designed for bidirectional data
standards TIA/EIA-422-B and TIA/EIA-485-A communication on multipoint bus transmission lines.
and ITU Recommendations V.11 and X.27 They are designed for balanced transmission lines
• Designed for multipoint transmission on and meet ANSI Standards TIA/EIA-422-B and TIA/
long bus lines in noisy environments EIA-485-A and ITU Recommendations V.11 and X.27.
• 3-State driver and receiver outputs
The SN65176B and SN75176B devices combine a
• Individual driver and receiver enables
3-state differential line driver and a differential input
• Wide positive and negative input/output bus
line receiver, both of which operate from a single 5-
voltage ranges
V power supply. The driver and receiver have active-
• ± 60-mA Maximum driver output capability
high and active-low enables, respectively, that can
• Thermal shutdown protection
be connected together externally to function as a
• Driver positive and negative current limiting
direction control. The driver differential outputs and
• 12-kΩ Minimum Receiver Input Impedance
the receiver differential inputs are connected internally
• ± 200-mV Receiver input sensitivity
to form differential input/output (I/O) bus ports that
• 50-mV Typical receiver input hysteresis
are designed to offer minimum loading to the bus
• Operate from single 5-V supply
when the driver is disabled or VCC = 0. These ports
2 Applications feature wide positive and negative common-mode
voltage ranges, making the device suitable for party-
• Chemical and gas sensors
line applications.
• Digital signage
• HMI (human machine interfaces) The driver is designed for up to 60 mA of sink
• Motor controls: AC induction, brushed and brush- or source current. The driver features positive
less dc, low- and high-voltage, stepper motors, and negative current limiting and thermal shutdown
and permanent magnets for protection from line-fault conditions. Thermal
• TETRA Base stations shutdown is designed to occur at a junction
• Telecom towers: remote electrical tilt units (ret) and temperature of approximately 150°C. The receiver
tower mounted amplifiers (TMA) features a minimum input impedance of 12 kΩ, an
• Weigh scales input sensitivity of ±200 mV, and a typical input
• Wireless repeaters hysteresis of 50 mV.
Device Information
PART NUMBER PACKAGE (PIN)(1) BODY SIZE (NOM)
SOIC (8) 4.90 mm × 3.91 mm
SNx5176 PDIP (8) 9.81 mm × 6.35 mm
SOP (8) 6.20 mm × 5.30 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.
3
DE
4
D
2
RE 6
1 A
R 7 Bus
B

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.3 Feature Description...................................................12
2 Applications..................................................................... 1 7.4 Device Functional Modes..........................................13
3 Description.......................................................................1 8 Application and Implementation.................................. 14
4 Revision History.............................................................. 2 8.1 Application Information............................................. 14
5 Pin Configuration and Functions...................................3 8.2 Typical Application.................................................... 14
6 Specifications.................................................................. 4 8.3 System Examples..................................................... 15
6.1 Absolute Maximum Ratings........................................ 4 9 Power Supply Recommendations................................16
6.2 Recommended Operating Conditions.........................4 10 Layout...........................................................................16
6.3 Thermal Information....................................................4 10.1 Layout Guidelines................................................... 16
6.4 Electrical Characteristics – Driver............................... 5 10.2 Layout Example...................................................... 16
6.5 Electrical Characteristics – Receiver.......................... 6 11 Device and Documentation Support..........................17
6.6 Switching Characteristics – Driver.............................. 6 11.1 Related Links.......................................................... 17
6.7 Switching Characteristics – Receiver..........................6 11.2 Trademarks............................................................. 17
6.8 Typical Characteristics................................................ 7 11.3 Electrostatic Discharge Caution.............................. 17
Parameter Measurement Information............................... 9 11.4 Glossary.................................................................. 17
7 Detailed Description......................................................12 12 Mechanical, Packaging, and Orderable
7.1 Overview................................................................... 12 Information.................................................................... 17
7.2 Functional Block Diagram......................................... 12

4 Revision History
Changes from Revision F (January 2015) to Revision G (July 2021) Page
• Changed the Thermal Information table............................................................................................................. 4
• Changed the VO Output voltage MAX value from: 6 V to: VCC in the Electrical Characteristics – Driver .......... 5
• Changed the VODI Differential output voltage MAX value from: 6 V to: VCC in the Electrical Characteristics –
Driver ................................................................................................................................................................. 5

Changes from Revision E (January 2014) to Revision F (January 2015) Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information
table, Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.............................................................................. 1
• Moved Typical Characteristics inside of the Specifications section.................................................................... 7

Changes from Revision D (April 2003) to Revision E (January 2014) Page

• Updated document to new TI data sheet format - no specification changes...................................................... 1
• Deleted Ordering Information table.....................................................................................................................1

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5 Pin Configuration and Functions

R 1 8 VCC
RE 2 7 B
DE 3 6 A
D 4 5 GND

Figure 5-1. Top View

Table 5-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME NO.
R 1 O Logic Data Output from RS-485 Receiver
RE 2 I Receive Enable (active low)
DE 3 I Driver Enable (active high)
D 4 I Logic Data Input to RS-485 Driver
GND 5 — Device Ground Pin
A 6 I/O RS-422 or RS-485 Data Line
B 7 I/O RS-422 or RS-485 Data Line
VCC 8 — Power Input. Connect to 5-V Power Source.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage(2) 7 V
Voltage range at any bus terminal –10 15 V
VI Enable input voltage 5.5 V
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature range –65 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.

6.2 Recommended Operating Conditions

MIN TYP MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VI or VIC Voltage at any bus terminal (separately or common mode) -7 12 V
VIH High-level input voltage D, DE, and RE 2 V
VIL Low-level input voltage D, DE, and RE 0.8 V
VID Differential input voltage(1) ±12 V
Driver –60 mA
IOH High-level output current
Receiver –400 µA
Driver 60
IOL Low-level output current mA
Receiver 8
SN65176B –40 105
TA Operating free-air temperature °C
SN75176B 0 70

(1) Differential input/output bus voltage is measured at the non-inverting terminal A, with respect to the inverting terminal B.

6.3 Thermal Information

SNx5176
THERMAL METRIC(1) D (SOIC) PS (SO) P (PDIP) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 114.4 113.2 88.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 55.1 57.9 65.9 °C/W
RθJB Junction-to-board thermal resistance 61.6 69.0 69.0 °C/W
ψJT Junction-to-top characterization parameter 78.8 14.6 35.2 °C/W
ψJB Junction-to-board characterization parameter 60.8 68.1 64.3 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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6.4 Electrical Characteristics – Driver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
VO Output voltage IO = 0 0 Vcc V
|VOD1| Differential output voltage IO = 0 1.5 3.6 Vcc V
RL = 100 Ω, see Figure 7-1 ½ VOD1 or 2 (4)
|VOD2| Differential output voltage V
RL = 54 Ω, see Figure 7-1 1.5 2.5 5
VOD3 Differential output voltage See (5) 1.5 5 V
Change in magnitude of
∆|VOD| RL = 54 Ω or 100 Ω, see Figure 7-1 ±0.2 V
differential output voltage(3)
VOC Common-mode output voltage RL = 54 Ω or 100 Ω, see Figure 7-1 -1 +3 V
Change in magnitude
∆|VOC| of common-mode output RL = 54 Ω or 100 Ω, see Figure 7-1 ±0.2 V
voltage(3)
VO = 12 V 1
IO Output current Output disabled(6) mA
VO = –7 V –0.8
IIH High-level input current VI = 2.4 V 20 µA
IIL Low-level input current VI = 0.4 V –400 µA
VO = –7 V –250
VO = 0 –150
IOS Short-circuit output current mA
VO = VCC 250
VO = 12 V 250
Outputs enabled 42 70
ICC Supply current (total package) No load mA
Outputs disabled 26 35

(1) The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs
and outputs.
(2) All typical values are at VCC = 5 V and TA = 25°C.
(3) Δ|VOD| and Δ|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level
to a low level.
(4) The minimum VOD2 with a 100-Ω load is either ½ VOD1 or 2 V, whichever is greater.
(5) See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
(6) This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not
apply for a combined driver and receiver terminal.

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6.5 Electrical Characteristics – Receiver

over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2(2) V
Vhys Input hysteresis voltage (VIT+ – VIT–) 50 mV
VIK Enable Input clamp voltage II = –18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH = –400 µA, see Figure 7-2 2.7 V
VOL Low-level output voltage VID = –200 mV, IOL = 8 mA, see Figure 7-2 0.45 V
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA
VI = 12 V 1
II Line input current Other input = 0 V(3) mA
VI = –7 V –0.8
IIH High-level enable input current VIH = 2.7 V 20 µA
IIL Low-level enable input current VIL = 0.4 V –100 µA
rI Input resistance VI = 12 V 12 kΩ
IOS Short-circuit output current –15 –85 mA
Outputs enabled 42 55
ICC Supply current (total package) No load mA
Outputs disabled 26 35

(1) All typical values are at VCC = 5 V, TA = 25°C.

(2) The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for
common-mode input voltage and threshold voltage levels only.
(3) This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.

6.6 Switching Characteristics – Driver

VCC = 5 V, RL = 110 Ω, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential-output delay time RL = 54 Ω, see Figure 7-3 15 22 ns
tt(OD) Differential-output transition time RL = 54 Ω, see Figure 7-3 20 30 ns
tPZH Output enable time to high level See Figure 7-4 85 120 ns
tPZL Output enable time to low level See Figure 7-5 40 60 ns
tPHZ Output disable time from high level See Figure 7-4 150 250 ns
tPLZ Output disable time from low level See Figure 7-5 20 30 ns

6.7 Switching Characteristics – Receiver

VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output 21 35
VID = 0 to 3 V, see Figure 7-6 ns
tPHL Propagation delay time, high- to low-level output 23 35
tPZH Output enable time to high level 10 20
See Figure 7-7 ns
tPZL Output enable time to low level 12 20
tPHZ Output disable time from high level 20 35
See Figure 7-7 ns
tPLZ Output disable time from low level 17 25

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6.8 Typical Characteristics

5 5
VCC = 5 V VCC = 5 V
4.5 TA = 25°C 4.5 TA = 25°C
VOH – High-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

4 4

3.5 3.5

3 3

2.5 2.5

2 2

1.5 1.5
VOH

1 1

0.5 0.5

0 0
0 –20 –40 –60 –80 –100 –120 0 20 40 60 80 100 120
IOH – High-Level Output Current – mA IOL – Low-Level Output Current – mA
Figure 6-1. Driver High-Level Output Voltage vs High-Level Figure 6-2. Driver Low-Level Output Voltage vs Low-Level
Output Current Output Current
4 5
VID = 0.2 V
VCC = 5 V
4.5 TA = 25°C
3.5 TA = 25°C
VOD – Differential Output Voltage – V

VOH – High-Level Output Voltage – V

4
3
3.5
2.5
3

2 2.5
VCC = 5.25 V
2 VCC = 5 V
1.5
1.5
VCC = 4.75 V
1
VOD

1
VOH

0.5 0.5

0 0
0 10 20 30 40 50 60 70 80 90 100 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50
IO – Output Current – mA IOH – High-Level Output Current – mA
Figure 6-3. Driver Differential Output Voltage vs Output Current Figure 6-4. Receiver High-Level Output Voltage vs High-Level
Output Current
5 0.6
VCC = 5 V VCC = 5 V
4.5 VID = 200 mV TA = 25°C
VOL – Low-Level Output Voltage – V

IOH = –440 µA
VOH – High-Level Output Voltage – V

0.5
4

3.5
0.4
3

2.5 0.3

2
0.2
1.5
VOL

1
VOH

0.1
0.5

0 0
–40 –20 0 20 40 60 80 100 120 0 5 10 15 20 25 30
TA – Free-Air Temperature – °C IOL – Low-Level Output Current – mA

Only the 0°C to 70°C portion of the curve applies to the Only the 0°C to 70°C portion of the curve applies to the
SN75176B device. SN75176B device.
Figure 6-5. Receiver High-Level Output Voltage vs Free-Air Figure 6-6. Receiver Low-Level Output Voltage vs Low-Level
Temperature Output Current

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6.8 Typical Characteristics (continued)

0.6 5
VCC = 5 V VID = 0.2 V
VID = –200 mV Load = 8 kΩ to GND
VOL – Low-Level Output Voltage – V

0.5 IOL = 8 mA TA = 25°C

4 VCC = 5.25 V

VO – Output Voltage – V
0.4
VCC = 5 V
3 VCC = 4.75 V

0.3

2
0.2

VO
VOL

1
0.1

0 0
–40 –20 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3
TA – Free-Air Temperature – °C VI – Enable Voltage – V

Figure 6-7. Receiver Low-Level Output Voltage vs Free-Air Figure 6-8. Receiver Output Voltage vs Enable Voltage
Temperature
6
VID = –0.2 V
VCC = 5.25 V
Load = 1 kΩ to VCC
5 TA = 25°C
VCC = 4.75 V
VO – Output Voltage – V

VCC = 5 V
4

2
VO

0
0 0.5 1 1.5 2 2.5 3
VI – Enable Voltage – V
Figure 6-9. Receiver Output Voltage vs Enable Voltage

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Parameter Measurement Information

RL
2
VOD2
RL
VOC
2

Figure 7-1. Driver VOD and VOC

ID
VOH
+IOL –IOH
VOL

Figure 7-2. Receiver VOH and VOL

3V
Input 1.5 V 1.5 V
CL = 50 pF 0V
(see Note A) td(OD) td(OD)
RL = 54 Ω
Generator 50 Ω Output
90% ≈2.5 V
(see Note B)
Output 50% 50%
10% 10% ≈–2.5 V
3V
tt(OD) tt(OD)
TEST CIRCUIT VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50
Ω.

Figure 7-3. Driver Test Circuit and Voltage Waveforms

Output 3V
S1 Input 1.5 V 1.5 V
0 V or 3 V 0V
CL = 50 pF tPZH 0.5 V
RL = 110 Ω
(see Note A) VOH
Generator
50 Ω Output 2.3 V
(see Note B)
tPHZ Voff ≈0 V

TEST CIRCUIT VOLTAGE WAVEFORMS

A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50
Ω.

Figure 7-4. Driver Test Circuit and Voltage Waveforms

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5V
3V
RL = 110 Ω Input 1.5 V 1.5 V
S1 Output 0V
3 V or 0 V
CL = 50 pF tPZL tPLZ
(see Note A)
Generator 50 Ω 5V
(see Note B) 0.5 V
Output 2.3 V
VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50
Ω.

Figure 7-5. Driver Test Circuit and Voltage Waveforms

3V
Input 1.5 V 1.5 V
Generator Output 0V
51 Ω
(see Note B) tPLH tPHL
1.5 V CL = 15 pF
(see Note A) VOH
Output 1.3 V 1.3 V
0V
VOL
TEST CIRCUIT VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50
Ω.

Figure 7-6. Receiver Test Circuit and Voltage Waveforms

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1.5 V S1

2 kΩ S2
–1.5 V 5V

CL = 15 pF
(see Note A) 5 kΩ 1N916 or Equivalent

Generator
50 Ω
(see Note B)
S3

TEST CIRCUIT

3V 3V
Input 1.5 V Input 1.5 V
S1 to 1.5 V S1 to –1.5 V
0V S2 Open 0 V S2 Closed
tPZH S3 Closed S3 Open
tPZL
VOH
1.5 V ≈4.5 V
Output
Output 1.5 V
0V
VOL

3V 3V
S1 to 1.5 V S1 to –1.5 V
Input 1.5 V S2 Closed Input 1.5 V S2 Closed
S3 Closed S3 Closed
0V 0V
tPHZ
tPLZ
VOH ≈1.3 V
0.5 V
Output Output 0.5 V
≈1.3 V VOL

VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50
Ω.

Figure 7-7. Receiver Test Circuit and Voltage Waveforms

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7 Detailed Description
7.1 Overview
The SN65176B and SN75176B differential bus transceivers are integrated circuits designed for bidirectional data
communication on multipoint bus transmission lines. They are designed for balanced transmission lines and
meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27.
The SN65176B and SN75176B devices combine a 3-state differential line driver and a differential input line
receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, that can be connected together externally to function as a direction control.
The driver differential outputs and the receiver differential inputs are connected internally to form differential
input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled
or VCC = 0. These ports feature wide positive and negative common-mode voltage ranges, making the device
suitable for party-line applications.
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative
current limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to
occur at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12
kΩ, an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B devices can be used in transmission-line applications employing the SN75172
and SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
7.2 Functional Block Diagram
3
DE
4
D
2
RE 6
1 A
R 7 Bus
B

7.3 Feature Description

7.3.1 Driver
The driver converts a TTL logic signal level to RS-422 and RS-485 compliant differential output. The TTL logic
input, DE pin, can be used to turn the driver on and off.
Table 7-1. Driver Function Table(1)
INPUT ENABLE DIFFERENTIAL OUTPUTS
D DE
A B
H H H L
L H L H
X L Z Z

(1) H = high level,

L = low level,
X = irrelevant,
Z = high impedance (off)

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7.3.2 Receiver
The receiver converts a RS-422 or RS-485 differential input voltage to a TTL logic level output. The TTL logic
input, RE pin, can be used to turn the receiver logic output on and off.
Table 7-2. Receiver Function Table(1)
DIFFERENTIAL INPUTS ENABLE OUTPUT
A–B RE R
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L U
VID ≤ –0.2 V L L
X H Z
Open L U

(1) H = high level,

L = low level,
U = unknown,
Z = high impedance (off)

7.4 Device Functional Modes

7.4.1 Device Powered
Both the driver and receiver can be individually enabled or disabled in any combination. DE and RE can be
connected together for a single port direction control bit.
7.4.2 Device Unpowered
The driver differential outputs and the receiver differential inputs are connected internally to form differential
input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or
VCC = 0.
7.4.3 Symbol Cross Reference
Table 7-3. Symbol Equivalents
DATA SHEET
TIA/EIA-422-B TIA/EIA-485-A
PARAMETER
VO Voa, Vob Voa, Vob
|VOD1| Vo Vo
|VOD2| Vt ®L = 100 Ω) Vt ®L = 54 Ω)
Vt (test termination
|VOD3|
measurement 2)
∆|VOD| | |Vt| – | V t| | | |Vt – | V t| |
VOC |Vos| |Vos|
∆|VOC| |Vos – V os| |Vos – V os|
IOS |Isa|, |Isb|
IO |Ixa|, |Ixb| Iia, Iib

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The device can be used in RS-485 and RS-422 physical layer communications.
8.2 Typical Application
SN65176B SN65176B
SN75176B SN75176B

RT RT

Up to 32
Transceivers

The line should be terminated at both ends in its characteristic impedance ®T = ZO). Stub lengths off the main line should be kept as
short as possible.

Figure 8-1. Typical RS-485 Application Circuit

8.2.1 Design Requirements

• 5-V power source
• RS-485 bus operating at 10 Mbps or less
• Connector that ensures the correct polarity for port pins
• External fail safe implementation
8.2.2 Detailed Design Procedure
• Place the device close to bus connector to keep traces (stub) short to prevent adding reflections to the bus
line
• If desired, add external fail-safe biasing to ensure +200 mV on the A-B port.

14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: SN65176B SN75176B

 SN65176B, SN75176B
www.ti.com SLLS101G – JULY 1985 – REVISED JULY 2021

8.2.3 Application Curves

Figure 8-2. Eye Diagram for 10-Mbits/s over 100 feet of standard CAT-5E cable 120-Ω Termination at
both ends. Scale is 1 V per division and 25 nS per division

8.3 System Examples

EQUIVALENT OF EACH INPUT TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT

VCC VCC VCC

85 Ω
R(eq) NOM

16.8 kΩ 960 Ω
Input NOM NOM

960 Ω
NOM Output

GND
Driver input: R(eq) = 3 kΩ NOM Input/Output
Enable inputs: R(eq )= 8 kΩ NOM Port
R(eq) = Equivalent Resistor

Figure 8-3. Schematics of Inputs and Outputs

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: SN65176B SN75176B
SN65176B, SN75176B
SLLS101G – JULY 1985 – REVISED JULY 2021 www.ti.com

9 Power Supply Recommendations

Power supply should be 5 V with a tolerance less than 10%
10 Layout
10.1 Layout Guidelines
Traces from device pins A and B to connector must be short and capable of 250 mA maximum current.
10.2 Layout Example
GND

1.5 μF
TTL Logic 1 R VCC 8 5V

TTL Logic 2 RE B 7 B
Connector
TTL Logic 3 DE A 6 A
TTL Logic 4 D GND 5 GND

Figure 10-1. Layout Diagram

16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: SN65176B SN75176B

 SN65176B, SN75176B
www.ti.com SLLS101G – JULY 1985 – REVISED JULY 2021

11 Device and Documentation Support

11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN65176B Click here Click here Click here Click here Click here
SN75176B Click here Click here Click here Click here Click here

11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.4 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17

Product Folder Links: SN65176B SN75176B
 PACKAGE OPTION ADDENDUM

www.ti.com 29-Sep-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN65176BD NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 65176B
SN65176BDG4 NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 65176B
SN65176BDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 65176B

SN65176BDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 65176B

SN65176BDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 65176B

SN65176BP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 105 SN65176BP

SN75176BD NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75176B

SN75176BDE4 NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75176B
SN75176BDG4 NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75176B
SN75176BDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75176B

SN75176BDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75176B

SN75176BDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75176B

SN75176BP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75176BP

SN75176BPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75176BP

SN75176BPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 A176B

SN75176BPSRG4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 A176B

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 29-Sep-2021

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65176BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65176BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65176BDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75176BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75176BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75176BDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75176BPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Dec-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65176BDR SOIC D 8 2500 340.5 336.1 25.0
SN65176BDR SOIC D 8 2500 340.5 338.1 20.6
SN65176BDRG4 SOIC D 8 2500 340.5 336.1 25.0
SN75176BDR SOIC D 8 2500 340.5 338.1 20.6
SN75176BDR SOIC D 8 2500 340.5 336.1 25.0
SN75176BDRG4 SOIC D 8 2500 340.5 336.1 25.0
SN75176BPSR SO PS 8 2000 853.0 449.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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