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Design of DDR4 SDRAM controller

Conference Paper · December 2014

DOI: 10.1109/ICECE.2014.7026950

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 8th International Conference on Electrical and Computer Engineering 148
20-22 December, 2014, Dhaka, Bangladesh

Design of DDR4 SDRAM Controller

Md. Ashraful Islam,1,* Md. Yeasin Arafath,2 and Md. Jahid Hasan3
1
ASIC Design Engineer, Fastrack Design Ltd., Bangladesh
2
ASIC Design Engineer, Fastrack Design Ltd., Bangladesh
3
ASIC Design Engineer, Fastrack Design Ltd., Bangladesh
*1
ashraful@fastrack-design.com, 2yeasin@fastrack-design.com, 3jahid@fastrack-design.com

Abstract— Currently, the demand of memories has been

increasing due to its higher speed, lower cost and lower power
consumption. The complexity of instructions to control the
memory devices increases with the increase in technology. DDR4
is the latest generation family of DDR SDRAM. This memory
device provides higher reliability, availability and serviceability
than other DDR memories. In this paper, the overall architecture
of the DDR4 SDRAM controller is proposed .The detailed design
and operation of its individual sub blocks is described. Also the
advantages of DDR4 over DDR3 SDRAM are discussed.

Index Terms—DDR4, SDRAM Controller, Rank.

I. INTRODUCTION
DDR4 SDRAM, an abbreviation for Double Data Rate
type 4 Synchronous Dynamic Random Access Memory is the Fig.1 New Features of DDR4 SDRAM
latest member of DDR family of technologies mostly for the Now Table 1 shows the comparison of DDR4 SDRAM than
computing, server, biomedical and embedded applications. others.
Recently DDR3 SDRAM is widely used in PC, Smart phones, TABLE 1
Tablets, High-end servers and micro server systems. DDR4 is COMPARISON TABLE OF DDR3 AND DDR4 SDRAM
focusing on data reliability. A large number of server systems
are required for increasing high-bandwidth and high capacity Feature DDR3 DDR4 DDR4 Advantage
of multimedia contents [1]. Hence, a main memory of server Voltage 1.5V 1.2V Reduces memory
systems is one of the vital components, so it should definitely (core and power demand
I/O)
have high performance feature [2]. The increasing demand of
Prefetch 8n 8n DDR4 also have 8n
faster operating systems as well as big size applications prefetch but parallel
created the need of using high capacity memory. Due to the bank group
use of high capacity memory, power consumption is also Densities 512Mb–8Gb 2Gb–16Gb Better enablement
increased immensely which is one of the major concerns for for large-capacity
memory market. DDR4 not only increased its volume but also memory subsystems
reduced the power consumption. Data rate 800, 1066, 1600, 1866, Migration to higher
The main changes of DDR4 SDRAM are supply voltage, (MT/s) 1333, 1600, 2133, 2400, data bandwidth
higher data rate, higher densities, more banks, faster bursts 1866, 2133 2667, 3200
access and higher system reliability compared with DDR3 Internal 8 16 More Banks
banks
SDRAM.
Bank 0 4 Faster burst
Figure 1 shows the new features which is introduced in
groups accesses
DDR4 SDRAM such as : CRC, C/A parity, data bus inversion (BG)
(DBI), Command address latency (CAL), per-DRAM
addressability , CAL (command address latency), MPR DDR4 SDRAM controller is used as a bridge to interface with
(multi-purpose registers), gear-down mode, FGREF (fine SDRAM memory devices and processors subsystem. It
granularity refresh) and temperature controlled refresh. manages bi-directional data flow of memory. The main
Among these, CRC, C/A parity, data bus inversion (DBI) for function of controller is data read and write. It also assists the
solving the data reliability issue. Using Per DRAM DRAM to retain the data such as periodic refresh, precharge
addressability mode only selected DRAM programmed is etc. Data transfer is accomplished with the bi-directional
possible in a single Rank. differential data strobe (DQS, DQS#). The DDR4 SDRAM
memory device transmits data strobe (DQS) for read operation
and controller device transmits DQS for write operation.

This paper is divided by following sectors: sector 1 is

introduction. Sector 2 is discussed the functional description
of DDR4 SDRAM. Sector 3 is described the overall
architecture of DDR4 SDRAM controller and finally the
conclusion sector.

978-1-4799-4166-7/14/$31.00 ©2014 IEEE

 149

II. FUCNTIONAL DESCRIPTION OF DDR4 SDRAM III. ARCHITECTURE OF DDR4 SDRAM CONTROLLER
DDR4 SDRAM has 8n prefetch with parallel bank for Fig. 4 shows the proposed overall architecture of DDR4
higher data transfer rate. The memory internally configured as SDRAM controller.
16 banks, 4 bank group with 4 banks for each bank group [4].
Bank is independent memory array. The row and column
address is used to locate the requested address of bank in
memory. And Page is unique address comprise of bank group,
bank and row address. A page size is a total number of
columns in a row. Rank architecture is very important to
enhance data rate without increasing burst length [3]. Figure 2
shows the organization of memory.

Fig. 2 RAM organization

DDR4 SDRAM read and writes operation is burst oriented.

It begins at a specific selected location, and continues for a Fig. 4 Architecture of DDR4 SDRAM Controller
burst length of eight in a programmed sequence. The memory
starts operation begins with an ACTIVATE Command, which A. Rank status machine
is then followed by a Read or Write command. To select the In the controller we propose a Bank management unit (we
bank and row to be activated, address bits registered is used called Rank status machine) which tracks the present state of
with the ACTIVATE Command. Also to select the starting each memory bank in the original DRAM. This provides
column location for the burst operation, address bits registered greater flexibility to perform parallel read write command
is used with the Read or Write command [4]. processing. The rank status machine architecture is shown in
The following state diagram shows in figure 3 is described Fig.5.
the possible state transitions and commands to control DDR4
SDRAM [4].

Fig. 5 Rank architecture

There are 4 Bank groups status processor and each Bank

group contains 4 banks status processor, so total 16 banks can
be managed at one time. Each status processor contains
specific timing counter such as tCCD, tRRD, tFAW etc. The
status is: bank active, readable, writeable, prechagable and
row address. This ensures read-to-write and write-to-read bus
turnaround time; active-to-precharge, activate delay between
different banks and bank groups. When a command is sent to
DDR4; timing constraint’s counters corresponding to that
command start to count and updated the status upon counting.
For an example if a bank “x” in DDR4 is in idle state and a
activate command is issued to the DDR4. The timing
Fig. 3 State diagram of DDR4 SDRAM
constraints related to activate command are tRRD (active-to-
active command delay), tRCD (active-to-read/write delay),
 150

tRAS (active-to-precharge delay) etc. In rank status machine is output with a “0” until the rising edge is detected by the
corresponding bank “x” status processor starts counting of DQS at which time the DQ will be output with a “1”. The
these times i.e. tRRD, tRCD, tRAS etc. after issuing activate calibration unit will detect these “1” on the DQ bus and then
command. At beginning the bank “x” status was bank active knows the correct DQS compensation to align the DQS and
=0, readable =0, writeable =0, prechagable =0. After the tRCD CLK on the write path. Once all DQS have been adjusted,
time counts bank “x” status updated as bank active =1, these compensation values of DLL stored for each DQS for
readable =1, writeable =1, prechagable =0. future usage. Then the memory controller sends another MRS
DDR4 introduces new specifications for read to read or command to exit the write level mode.
write to write delay which are called tCCD_S and tCCD_L
time for read or writes to banks of different Bank group and
same Bank groups respectively.

Fig. 6 tCCD variation of rank operation

The full bandwidth of DDR4 cannot be used, until Bank group

interleaving access is not employed [5]. To achieve the better
performance the controller can performs the bank interleaving
operations by monitoring rank status.

B. CMD pipelining
Today’s most of system shares the common RAM (Such
as multiple processor, GPU, GPIO shares the DRAM). So the Fig. 7 Write Leveling
controller queues up multiple commands from different
peripherals using command pipeline. The command pipeline As DDR4 write leveling manages the DQS/DQ on write
is used for optimal bandwidth utilization. Command pipeline data, the DDR4 read leveling manages the DQS/DQ on read
is used by the Command generation unit to pre-process the data. DDR4 read leveling is to compensate the imbalanced
target bank for read or write operation such as active and loading on the read path. First the memory controller puts the
precharge. DDR4 memory devices into MPR mode by writing to the
MR3 register. This puts the DDR4 memory devices into the
read leveling mode which outputs a training pattern of
C. Command address latency consecutive “01” on each memory read command. Since the
Command-to-Address Latency (CAL) function offers by memory controller knows that data stream, so it will adjust the
DDR4 memory that can be used to save power. Basically, internal DQS delay to capture the DQ using DQS. Memory
CAL is the delay between enable a Chip select and controller repeats these calibration reads until read data
command/Address in clock cycles which is defined by mode capture at memory controller is optimized.
register. Before issuing a command, it provides the DRAM ZQ Calibration command is used to calibrate DRAM Ron
time to active the CMD/ADDR receivers. The receivers can & ODT values. The ZQ calibration accounts the voltage and
be latched, whenever the command and the address are temperature variation on DRAM output driver.
latched. In case of providing consecutive commands, the
receiver will have enabled by DRAM for the period of E. Command Generation Unit
command sequence [4]. The command generator accepts user commands from the
CMD pipelining unit. When the unit receives a single request,
D. Calibration Unit from pipelining unit request is processed immediately. For
specified read or write request, Command Generation Unit
Calibration Unit performs write leveling, read leveling and
lookup in the rank status to ensure the timing constraints for
ZQ calibration. DDR4 memory used fly-by topology for better
each previous memory transaction is met up before start new
signal integrity. To reduce the number of stubs and their
transaction. It also checks for availability of target bank for
length this topology is used. Despite benefiting, it causes skew
read or write operation from the rank status. Bank availability
problem between clock and strobe at every DRAM on the
means the requested row in corresponding bank is active. If
DIMM module. Hence, to solve the skew problem memory
the requested bank is not active then it generates the necessary
controller uses the ‘write leveling’ feature and feedback from
precharge and active command to activate the bank in DDR4.
the DDR4 SDRAM to adjust the data strobe to clock
The command generation unit halt itself from throwing next
relationship [4]. This feature can compensate for unbalanced
command until the timing requirements of DDR4 are met.
loading on the board for write and read operations. Calibration
Upon availability of the bank; the requested read or write
unit put the DDR4 into write leveling state by writing mode
command is send to the DDR4 and internal rank status
register MR1 of DDR4. The write strobe DQS is repeatedly
machine so that rank can update itself each time when a new
delayed in small increments by the Delay Locked Loop (DLL).
command is throwing to the DDR4. If there are outstanding
DDR4 samples the CLK with the rising edge of DQS and
requests from two or more queues, the Command generation
provide feedback on DQ. During this protocol, each set of DQ
unit process the requests in look-ahead way. While processing
 151

the active request from pipeline if there are any unsatisfied latency, cas latency etc. After setting the mode register the
timing constraints which lead the controller to stall the Initialization and refresh unit switch on the calibration unit to
transaction, controller then check the next upcoming request perform the read and write leveling. Upon completion of
from queue. Command generation unit check the next requests coalition the DDR4 is ready for normal operation. It has a
bank address to find out the upcoming requests bank whether tREFI counter, which counts DDR4 refresh interval. On each
it is in active and activated row does match with the requested tREFI count the controller issues refresh command to DDR4.
row address or not. If the condition does not met then
command generation unit perform necessary precharge IV. CONCLUSIONS
activate sequence to active that bank, so that when the request
The proposed architecture is designed and implemented
will be active the request will incur minimum stall time. Such
according to DDR4 SDRAM JEDEC specification. DDR4 has
deliberately bank active of future requests utilize the active
reduced power consumption whereas it transfer rate is more
requests stall time. This opportunistically look-ahead activates
above of its predecessor i.e. DDR3, DDR2, DDR. Its
improve overall throughput.
application will be more widely used from low power mobile
computing device to high density servers. To enhance the
F. Data Transfer Unit throughput and reliability the controller should be aware of
both parallel bank operation and error detection. For that
Data transfer unit consist a read FIFO and a write FIFO.
reason we proposed parallel bank group and bank status
The read FIFO receives data from the DDR4 and passes that
machine co-ordinated by rank and separate data transfer unit
data to the user. The write FIFO receives write data from the
with CRC generator. For better performance upon notifying
user interface and passes that data to the DDR4. Read data
error status from DDR4 the controller should be able to handle
from DDR4 arrive at the controller at both positive and
the ongoing transaction and suspended transaction traffic. This
negative edge of clock. The burst length of DDR4 is 8. Read
is the upcoming challenge for DDR4 controller which we will
FIFO captures these data in 4 clock cycles and provides the
try in future.
user read data in a single clock cycle on next positive edge of
clock. Similarly write FIFO loads the user write data in a REFERENCES
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DDR4 it also added up CRC code at trail of each burst. [2] M. E. Tolentino, J. Turner, and K. W. Cameron, “Memory MISER:
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Fig. 8 CRC Generator

H. Initialization and Refresh Unit

Initialization and Refresh Unit performs the power up
initialization and periodic refresh. After power up or reset the
DDR4 must be initialized before start read or write transaction.
The reset pin of DDR4 is kept low by the controller for 100ns
to begin the initialization process. To active DDR4 clock,
reset pin set to high and CKE pin set to low for 5100us. Then
CKE pin drive to high. After tXPR period of time when
DRAM is initialized Mode Register Set commands are issued
for proper mode of operation such as burst length, additive

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