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TL103W, TL103WA

SLOS437M – APRIL 2004 – REVISED OCTOBER 2016

TL103W Dual Operational Amplifiers

With Internal Reference
1 Features 3 Description
1• Operational Amplifier The TL103W and TL103WA combine the building
blocks of a dual operational amplifier and a fixed
– Low Offset Voltage Max of: voltage reference – both of which often are used in
– TL103WA…3 mV (25°C) and 5 mV the control circuitry of both switch-mode and linear
(Full Temperature) power supplies. OP AMP1 has its noninverting input
– TL103W…4 mV (25°C) and 5 mV internally tied to a fixed 2.5-V reference, while OP
(Full Temperature) AMP2 is independent, with both inputs uncommitted.
– Low Supply Current…350 μA/Channel (Typ) For the A grade, especially tight voltage regulation
can be achieved through low offset voltages for both
– Unity Gain Bandwidth…0.9 MHz (Typ)
operational amplifiers (typically 0.5 mV) and tight
– Input Common-Mode Range Includes GND tolerances for the voltage reference (0.4% at 25°C
– Large Output-Voltage Swing… and 0.8% over operating temperature range).
0 V to VCC – 1.5 V The TL103W and TL103WA are characterized for
– Wide Supply-Voltage Range…3 V to 32 V operation from –40°C to 105°C.
– 2.5-kV ESD Protection (HBM)
Device Information(1)
• Voltage Reference
PART NUMBER PACKAGE BODY SIZE (NOM)
– Fixed 2.5-V Reference
TL103W SOIC (8) 4.90 mm x 3.91 mm
– Tight Tolerance Max of: TL103WA WSON (8) 4.00 mm x 4.00 mm
– TL103WA…0.4% (25°C) and 0.8%
(1) For all available packages, see the orderable addendum at
(Full Temperature) the end of the data sheet.
– TL103W . . . 0.7% (25°C) and 1.4%
(Full Temperature) Typical Application Circuit
R1
– Low Temperature Drift…7 mV (Typ) Over
Operating Temperature Range
– Wide Sink-Current Range . . .
0.5 mA (Typ) to 100 mA Opto
Isolator
R2
– Output Impedance…0.2 Ω (Typ) R8
OP AMP2
_
AC
SMPS
2 Applications Line +

Constant Current Control

• Battery Chargers
Battery

• Switch-Mode Power Supplies R3 R4 R5

• Linear Voltage Regulation

• Data-Acquisition Systems Current
Sense
R6 OP AMP1
2.5 V _ R7

VREF +
Constant Voltage Control R9
TL103W/A

Figure 1. TL103W/A in a Constant-Current and

Constant-Voltage Battery Charger

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 6.6 OP AMP2, Independent Operational Amplifier,
Electrical Characteristics............................................ 6
2 Applications ........................................................... 1
6.7 Voltage Reference, Electrical Characteristics.......... 7
3 Description ............................................................. 1
6.8 Total Device, Electrical Characteristics.................... 7
4 Revision History..................................................... 2
7 Device and Documentation Support.................... 8
5 Pin Configuration and Functions ......................... 3
7.1 Related Links ............................................................ 8
6 Specifications......................................................... 4 7.2 Receiving Notification of Documentation Updates.... 8
6.1 Absolute Maximum Ratings .................................... 4 7.3 Community Resources.............................................. 8
6.2 ESD Ratings ............................................................ 4 7.4 Trademarks ............................................................... 8
6.3 Recommended Operating Conditions...................... 4 7.5 Electrostatic Discharge Caution ................................ 8
6.4 Thermal Information .................................................. 4 7.6 Glossary .................................................................... 8
6.5 OP AMP1, Operational Amplifier With Noninverting
Input Connected to the Internal VREF 8 Mechanical, Packaging, and Orderable
Electrical Characteristics............................................ 5 Information ............................................................. 8

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision L (February 2016) to Revision M Page

• Changed positive and negative terminals OP AMP 2 in the D Package image of Pin Configuration and Functions ............ 3

Changes from Revision K (October 2010) to Revision L Page

• Added the Device Information table, Pin Configuration and Functions, ESD Ratings, Thermal Information, Device
and Documentation Support, and Mechanical, Packaging, and Orderable Information sections .......................................... 1
• Changed Features From: 2 kV ESD Protection (HBM) To: 2.5-kV ESD Protection (HBM) ................................................... 1
• Changed the Zener diode component to VREF in the Typical Application Circuit ................................................................... 1
• Changed the Zener diode component to VREF in the D Package of Pin Configuration and Functions .................................. 3

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5 Pin Configuration and Functions

D Package
8 Pin (SOIC) DRJ Package
Top View 8 Pin (WSON)
Top View

1OUT 1 OP 8 VCC+
AMP 1
1OUT 1 8 VCC+
- +
1IN– 2 7 2OUT
1IN− 2 7 2OUT

+ - 1IN+ 3 6 2IN−
1IN+ 3 6 2IN–
OP VCC− 4 5 2IN+
AMP 2
VCC- 4 VREF 5 2IN+

Pin Functions
PIN
I/O DESCRIPTION
NAME D DRJ
1OUT 1 1 O Opamp 1 output
1IN– 2 2 I Opamp 1 inverting input
1IN+ 3 3 I Opamp 1 non-inverting input and Shunt reference cathode terminal
VCC– 4 4 I Negative Supply Voltage
2IN+ 5 5 O Opamp 2 output
2IN– 6 6 I Opamp 2 inverting input
2OUT 7 7 I Opamp 2 non-inverting input
VCC+ 8 8 I Positive Supply Voltage

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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage 36 V
VID Operational amplifier input differential voltage 36 V
VI Operational amplifier input voltage range –0.3 36 V
IKA Voltage reference cathode current 100 mA
TJ Maximum junction temperature 150 °C
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply voltage 3 32 V
IK Cathode current 1 100 mA
TA Operating free-air temperature –40 105 °C

6.4 Thermal Information

TL103W / TL103W
(1)
THERMAL METRIC D (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 97 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 OP AMP1, Operational Amplifier With Noninverting Input Connected to the Internal VREF
Electrical Characteristics
VCC+ = 5 V, VCC = GND, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
25°C 1 4
TL103W Vicm = 0 V
Full range 5
VIO Input offset voltage mV
25°C 0.5 3
TL103WA Vicm = 0 V
Full range 5
αVIO Input offset-voltage drift 25°C 7 μV/°C
IIB Input bias current (negative input) 25°C 20 nA
AVD Large-signal voltage gain VCC+ = 15 V, RL = 2 kΩ, Vicm = 0 V 25°C 100 V/mV
kSVR Supply-voltage rejection ratio VCC+ = 5 V to 30 V, Vicm = 0 V 25°C 65 100 dB
IO(source) Output source current VCC+ = 15 V, VO = 2 V, Vid = 1 V 25°C 20 40 mA
ISC Short circuit to GND VCC+ = 15 V 25°C 40 60 mA
VCC+ = 15 V, VO = 2 V, Vid = –1 V 10 12 mA
IO(sink) Output sink current 25°C
VCC+ = 15 V, VO = 0.2 V, Vid = –1 V 12 50 μA
25°C 26 27
VCC = 30 V, RL = 2 kΩ
Full range 26
VOH High-level output voltage V
25°C 27 28
VCC = 30 V, RL = 10 kΩ
Full range 27
25°C 5 20
VOL Low-level output voltage RL = 10 kΩ mV
Full range 20
VCC+ = 15 V, CL = 100 pF,
SR Slew rate at unity gain 25°C 0.2 0.4 V/μs
RL = 2 kΩ, VI = 0.5 V to 2 V, unity gain
VCC+ = 30 V, VI = 10 mV,
GBW Gain bandwidth product 25°C 0.5 0.9 MHz
CL = 100 pF, RL = 2 kΩ, f = 100 kHz
VCC+ = 30 V, VO = 2 Vpp, CL = 100 pF,
THD Total harmonic distortion 25°C 0.02%
RL = 2 kΩ, f = 1 kHz, AV = 20 dB

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6.6 OP AMP2, Independent Operational Amplifier, Electrical Characteristics

VCC+ = 5 V, VCC = GND, VO = 1.4 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
25°C 1 4
TL103W Vicm = 0 V
Full range 5
VIO Input offset voltage mV
25°C 0.5 3
TL103WA Vicm = 0 V
Full range 5
αVIO Input offset voltage drift 25°C 7 μV/°C
25°C 2 75
IIO Input offset current nA
Full range 150
25°C 20 150
IIB Input bias current nA
Full range 200
VCC+ = 15 V, RL = 2 kΩ, 25°C 50 100
AVD Large-signal voltage gain V/mV
VO = 1.4 V to 11.4 V Full range 25
kSVR Supply-voltage rejection ratio VCC+ = 5 V to 30 V 25°C 65 100 dB
25°C 0 VCC+ – 1.5
VICR Input common-mode voltage range VCC+ = 30 V (1) V
Full range 0 VCC+ – 2
25°C 70 85
CMRR Common-mode rejection ratio dB
Full range 60
IO(source) Output source current VCC+ = 15 V, VO = 2 V, Vid = 1 V 25°C 20 40 mA
ISC Short circuit to GND VCC+ = 15 V 25°C 40 60 mA
VCC+ = 15 V, VO = 2 V,
10 12 mA
Vid = –1 V
IO(sink) Output sink current 25°C
VCC+ = 15 V, VO = 0.2 V,
12 50 μA
Vid = –1 V
25°C 26 27
VCC = 30 V, RL = 2 kΩ
Full range 26
VOH High-level output voltage V
25°C 27 28
VCC = 30 V, RL = 10 kΩ
Full range 27
25°C 5 20
VOL Low-level output voltage RL = 10 kΩ mV
Full range 20
VCC+ = 15 V, CL = 100 pF,
SR Slew rate at unity gain RL = 2 kΩ, VI = 0.5 V to 3 V, 25°C 0.2 0.4 V/μs
unity gain
VCC+ = 30 V, VI = 10 mV,
GBW Gain bandwidth product CL = 100 pF, RL = 2 kΩ, 25°C 0.5 0.9 MHz
f = 100 kHz
VCC+ = 30 V, VO = 2 Vpp,
THD Total harmonic distortion CL = 100 pF, RL = 2 kΩ, 25°C 0.02%
f = 1 kHz, AV = 20 dB
VCC = 30 V, RS = 100 Ω,
Vn Equivalent input noise voltage 25°C 50 nV/√Hz
f = 1 kHz

(1) The input common-mode voltage of either input should not be allowed to go below –0.3 V. The upper end of the common-mode voltage
range is VCC+ – 1.5 V, but either input can go to VCC+ + 0.3 V (but ≤36 V) without damage.

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6.7 Voltage Reference, Electrical Characteristics

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
25°C 2.482 2.5 2.518
TL103W IK = 10 mA
Full range 2.465 2.535
VREF Reference voltage V
25°C 2.49 2.5 2.51
TL103WA IK = 10 mA
Full range 2.48 2.52
Reference input voltage deviation
ΔVREF VKA = VREF, IK = 10 mA Full range 7 30 mV
over temperature range
Minimum cathode current for
Imin VKA = VREF 25°C 0.5 1 mA
regulation
VKA = VREF, ΔIK = 1 mA to 100 mA,
|zka| Dynamic impedance (1) 25°C 0.2 0.5 Ω
f < 1 kHz
DVKA
|z ka| +
(1) The dynamic impedance is defined as DI K .

6.8 Total Device, Electrical Characteristics

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
Total supply current, VCC+ = 5 V, No load 0.7 1.2
ICC Full range mA
excluding cathode-current reference VCC+ = 30 V, No load 2

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7 Device and Documentation Support

7.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TL103W Click here Click here Click here Click here Click here
TL103WA Click here Click here Click here Click here Click here

7.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

7.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

7.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
7.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

7.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

8 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE
D0008B SCALE 2.800
SOIC - 1.75 mm max height
SOIC

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]

.004-.010
0 -8 [ 0.11 -0.25]
.016-.050
[0.41-1.27]
DETAIL A
.041 TYPICAL
[1.04]

4221445/B 04/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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EXAMPLE BOARD LAYOUT

D0008B SOIC - 1.75 mm max height
SOIC

8X (.061 ) 8X (.055)
[1.55] SEE [1.4] SEE
SYMM DETAILS SYMM DETAILS
1 1
8 8

8X (.024) SYMM 8X (.024) SYMM

[0.6] [0.6]

5 5
4 4
6X (.050 ) 6X (.050 )
[1.27] [1.27]
(.213) (.217)
[5.4] [5.5]

IPC-7351 NOMINAL HV / ISOLATION OPTION

.150 [3.85] CLEARANCE / CREEPAGE .162 [4.1] CLEARANCE / CREEPAGE

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.0028 MAX .0028 MIN

[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221445/B 04/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

D0008B SOIC - 1.75 mm max height
SOIC

8X (.061 )
8X (.055)
[1.55] SYMM SYMM
[1.4]
1 1
8 8

8X (.024) 8X (.024)
[0.6] SYMM [0.6] SYMM

5 5
4 4
6X (.050 ) 6X (.050 )
[1.27] [1.27]
(.213) (.217)
[5.4] [5.5]

IPC-7351 NOMINAL HV / ISOLATION OPTION

.150 [3.85] CLEARANCE / CREEPAGE .162 [4.1] CLEARANCE / CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X

4221445/B 04/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TL103WAID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103WA

TL103WAIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103WA

TL103WID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103W

TL103WIDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103W

TL103WIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103W

TL103WIDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL103WAIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL103WIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL103WAIDR SOIC D 8 2500 340.5 336.1 25.0
TL103WIDR SOIC D 8 2500 340.5 336.1 25.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

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TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TL103WAID D SOIC 8 75 507 8 3940 4.32
TL103WID D SOIC 8 75 507 8 3940 4.32
TL103WIDG4 D SOIC 8 75 507 8 3940 4.32

Pack Materials-Page 3
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