AN-703

APPLICATION NOTE
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Driving High Power LEDs

by Yuxin Li, Gang Liu, and Alan Li

INTRODUCTION The current sensing resistor along with the voltage at

The ADP3806 is a switching mode power supply (SMPS) the ISET pin determines the output current. The required
controller featuring dual loop constant-voltage and voltage at the ISET pin should be generated from the
constant-current control; remote and accurate current 2.5 V precision reference source REF pin. The maximum
sensing; and shutdown and programmable, synchro- output current from the REF pin is 500 A. To generate
nizable switching frequency. For different application a higher setting voltage, the voltage divider can run off
requirements, it can be configured in a variety of topologies: the REG pin (6 V). Note that the accuracy for REF is 1%,
buck, boost, buck-boost, SEPIC, and CUK. This application and the accuracy for REG is 3%.
note guides the designs of controller circuits for driving Across CS+ and CS– pins, a filter capacitor of about 220 nF
high power LEDs (light emitting diodes) by using the should be placed right next to the pins in the PCB layout
ADP3806 to achieve an efficiency of up to 95%. to filter out noise.
Before using this application note for designing the
circuits, download the ADP3806 data sheet from the BUCK CONFIGURATION
www.analog.com. To drive LEDs with an output voltage lower than the
input power source voltage, a step-down topology buck
POWERING UP THE ADP3806 can be used.
The minimum VCC is 6.25 V (undervoltage lockout UVLO Figure 1 shows the buck configuration circuit. This
voltage) and the maximum VCC should not exceed 23 V, scheme utilizes the synchronous rectification func-
which brings the switch driver voltage BST to 30 V, the tionality of the controller to provide the highest power
junction breakdown voltage. The recommended VCC conversion efficiency. The controller and the power
range is from 6.5 V to 20 V. stage can be powered up by either the same or differ-
To ensure a clean voltage source at the VCC pin, an RC ent power sources. Using the same power source, the
bypass network is used between the input source and input voltage range should be within the range of 6.5 V
the IC. The decoupling capacitor can be in the value to 20 V. With different power sources, the power stage
range of 0.1 F to 22 F. The shutdown control pin SD input voltage can be as low as 6.5 V, while the maximum
accepts external control logic input. If automatic startup should not exceed 20 V.
is preferred, a voltage divider from VCC can be used to Using proper MOSFETs, the output current can go up
ensure that the voltage at this pin is below its limit, 10 V, to 4 A, the sense resistor value, and the ISET voltage.
and above its logic high, 2.0 V. The output voltage can go from 0 up to the power stage
A capacitor connected to the CT pin sets the switching input voltage.
frequency. Recommended switching frequency is from The current sensing resistor, RCS, should be low enough
300 kHz to 750 kHz for the optimized trade-off between to minimize its power loss but high enough to provide
the overall system physical size and the efficiency. A sufficient signal for the control. The voltage across the
higher switching frequency of up to 1 MHz demands CS+ and CS– pins should be higher than 50 mV to activate
more gate driving power and generates more switching the synchronous rectification function, that is, to switch
losses, resulting in lower efficiency, while the inductors’ the lower MOSFET on and off. When (CS+ – CS–) voltage
inductance can be scaled down to reduce the system’s is lower than 50 mV, the low-side MOSFET is not turned
physical size and cost. Another drawback of using a on so its body diode conducts, causing extra conduction
higher switching frequency is that the duty cycle range is loss. At the same time, the energy for driving the lower
reduced, so that the output voltage range is narrowed. MOSFET is saved. When the output current is lowered
The REG, REF, and BSTREG pins are output pins of three far enough, turning off the lower MOSFET may result in
internal low dropout (LDO) regulators. Decouple them higher overall system efficiency.
with the recommended capacitors to ensure the stability
of the regulators.

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By using the circuit shown in Figure 1, the output current CCH, CCL, and RC compose the loop compensation net-
equals work of the closed loop. They need to be designed
carefully to ensure system stability and control speed.
VISET
I LED = The control (duty cycle, d) to inductor current (iL) transfer
25RCS
function is a constant given by
If the current sensing signal in the design is lower than
50 mV, a bias circuit, shown in Figure 2, is needed to fully i L (S ) DVIN
=
activate the synchronous functionality. By using a voltage d 25RCSfSWL
divider composed of RB1 and RB2, a bias voltage, VBIAS, is
generated at the CS+ pin. Thus, the sensing signal needed where:
to activate the synchronous rectification function is VBIAS D is the duty cycle of the steady state.
lower than the 50 mV. If VBIAS equals 50 mV, the synchro- fSW is the switching frequency of the power stage.
nous function is effective all the time. With this bias, the
output current is This is valid below half of the switching frequency and
with the assumption that the output voltage is constant.
VISET − 25VBIAS
I LED = It is obvious that a simple integrator is adequate to com-
25RCS
pensate the loop with infinite dc gain. To set a bandwidth
The current limit setting accuracy is obviously a little of fC(C), the compensation component CCL needs to be
lower with this added offset term. Also, the biasing gMDVIN
circuitry should draw minimum current from the VREF C CL =
25RCSfSWLω C
pin, and filtering capacitor C4 should now be designed
to make a small enough time constant (recommend where:
0.3/f SW ) with RB2 instead of R CS . Thus, C4 is much
gM = 0.002 is the transconductance of the current loop
smaller than 200 nF.
error amplifier.
The output capacitor, COUT, is optional. It smoothes the
RC can be set to 0.
voltage and current across the LEDs.
CCH can be set to be open.
The input capacitor, CIN, is needed to absorb the input ripple
current. Normally, two 10 F/25 V ceramic capacitors are LEDs are not critical to the driving transition, so the sys-
enough. tem loop bandwidth can be low. It is recommended that
the bandwidth is designed to be 1/30th of the switching
The inductor, L, determines the ripple current. It is recom-
frequency for the buck configuration.
mended that the ripple current be about one-third of the
nominal output current to optimize both the system size MOSFETs can be chosen based on their dc voltage/
and the efficiency. The peak inductor current is therefore current ratings, switching speed (gate charges), and
thermal capability.
I LPEAK = 1.15I LEDM
Note that the BSTREG regulator needs to provide the
where: entire gate-driving energy to drive both the high-side
MOSFET and the high-side driver itself. Because the
ILPEAK is the peak current of the inductor.
maximum output current, IBSTREG , of the BSTREG regu-
ILEDM is the maximum average current in the LEDs. lator is  3 mA, the gate charge, QG , of the high-side
The inductor should be chosen based on two criteria. MOSFET and the switching frequency should satisfy
First, the inductor saturation current should be larger
I BSTREG > QGfSW
than the maximum peak current, ILPEAK, in the inductor.
Second, the inductor’s maximum dc current rating should If more gate-driving capability is needed, use an external
be larger than the load dc average current, ILED. NPN transistor, QBST, in the emitter follower configura-
The recommended bootstrap capacitance is 10 nF. A tion (see Figure 2) to deliver more current.
0.5 A Schottky diode is recommended as the bootstrap
diode. This diode must be placed on the PCB as close to
the BST pin and BSTREG pin as possible.

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 AN-703
VIN 7V–20V

C1 R1
22�F 10�
1 VCC SW 24
C6
10nF CIN
2 SYS– DRVH 23 SW1
R2
100k�
3 SYS+ BST 22
D1
MBR052 L VOUT = 0 TO VIN
4 ISYS BSTREG 21
C5
1�F LED1
5 LIMIT DRVL 20 SW2 COUT
CT LED2
6 CT PGND 19

ADP3806
7 SYNC CS+ 18
C2 C4
200nF RCS
100nF
8 REG CS– 17
C3
200pF TO SET THE OUTPUT CURRENT
9 REF ISET 16

RCLB RCLT
10 SD BATSEL 15
R3
CCL 51k�
11 COMP BAT 14
RC
CCH
12 LC AGND 13

Figure 1. Driving LEDs with the ADP3806 in Buck Configuration

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Figure 2. Biasing the Current Sensing Input to Accommodate Low Input Signal

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BOOST CONFIGURATION The output capacitor, COUT, is optional. Without it, the
If the output voltage is higher than the input power current flowing into the LEDs is discontinuous and fluc-
source voltage to power a series of LEDs, step-up con- tuates at a duty of (1 – D), where D is the duty cycle of
version is used. the PWM control. With the output capacitor, the current
Figure 3 shows the boost configuration using the ADP3806 in the LEDs can be shaped smoother. Appropriate output
to drive LEDs. This scheme utilizes the main driving out- capacitance is needed to achieve the required driving
put DRVH to control the main switch SW1, with the diode current pattern.
switch SW2 used for rectification. The current sensing resistor, RCS , needs to be large
To avoid overvoltage output, the voltage loop can be enough to generate sufficient signal for the controller.
connected to set the maximum allowable output volt- The maximum differential input voltage between CS+
age, VOUTM . Because the internal reference is 2.5 V, the and CS– is 160 mV.
maximum output voltage is set by CCH, CCL, and RC need to be designed carefully to ensure
system stability and control speed. This design is different
ROVPT + ROVPB
VOUTM = 2.5 from that of the buck configuration.
ROVPB
With this configuration, the output is always connected
Choose appropriate voltage divider resistance to set the to the input power supply via SW2 and the inductor, even
overvoltage protection point, VOUTM. when the controller is in shutdown mode. This may pose
some issues for specific applications.

VIN1 7V–20V VIN2

C1 R1
22�F 10�
1 VCC SW 24
CIN
2 SYS– DRVH 23
R2
100k� L
3 SYS+ BST 22

SW2 VOUT = VIN + 1 AND UP

4 ISYS BSTREG 21
C5
1�F LED1
5 LIMIT DRVL 20 SW1 COUT
CT LED2
6 CT PGND 19

ADP3806
7 SYNC CS+ 18
C2 C4
200nF RCS
100nF
8 REG CS– 17
C3 TO SET THE
200pF OUTPUT CURRENT
9 REF ISET 16

51k� ROVPB RCLB RCLT ROVPT

10 SD BATSEL 15
R3
CCL
11 COMP BAT 14
RC
CCH TO SET THE MAXIMUM
12 LC AGND 13 OUTPUT VOLTAGE

Figure 3. Driving LEDs with the ADP3806 in Boost Configuration

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 AN-703
SEPIC CONFIGURATION The output capacitor, COUT, is optional.
The SEPIC configuration provides an output that can be CCH, CCL, and RC need to be designed carefully to ensure
either higher or lower than the input voltage at a cost system stability and control speed. This design is different
of an additional inductor and capacitor. A SEPIC con- from that of the buck configuration.
figuration using the ADP3806 to drive LEDs is shown in
Figure 4. Unlike the boost configuration, the output is isolated to the
input source when the controller is in shutdown mode.
The output stage is very similar to the boost configura-
tion, except that the rectification switch, SW2, conducts
when the main switch, SW1, is on.

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Figure 4. Driving LEDs with the ADP3806 in the SEPIC Configuration

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AN-703
CUK CONFIGURATION Similarly, the output capacitor, COUT, is optional.
The CUK configuration provides an inverted output that CCH, CCL, and RC need to be designed carefully to ensure
can be either higher or lower in magnitude than the input system stability and control speed. This design is different
voltage. Figure 5 shows the CUK configuration using the from that of the buck configuration.
ADP3806 to drive LEDs.
The output is isolated to the input source when the
Similar to the buck configuration, the output current is controller is in shutdown mode.
continuous, with fewer pulsating components compared
to both the boost and the SEPIC configurations.

VIN1 7-20V VIN2

C1 R1
22�F 10�
1 VCC SW 24
CIN
2 SYS– DRVH 23
R2
100k� L1
3 SYS+ BST 22
CR L2 VOUT
4 ISYS BSTREG 21
C5
1�F LED1
5 LIMIT DRVL 20 SW1 SW2 COUT
CT LED2
6 CT PGND 19
RCS
ADP3806
7 SYNC CS+ 18
C2 C4
100nF 200nF
8 REG CS– 17
C3
200pF TO SET THE OUTPUT CURRENT
9 REF ISET 16

51k� RCLB RCLT

10 SD BATSEL 15
R3
CCL
11 COMP BAT 14
RC
CCH
12 LC AGND 13

Figure 5. Driving LEDs with the ADP3806 in the CUK Configuration

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 AN-703
BRIGHTNESS CONTROL current rating and lower at reduced current. To over-
Brightness control can be implemented easily by control- come this problem, a PWM brightness control scheme
ling the voltage at Pin ISET. Referring to the data sheet, can be used.
the output current, IOUT, is set by VISET (voltage at the ISET By periodically shorting the ISET pin down to AGND,
pin) by VISET shows a pattern of PWM, as does the output cur-
VISET rent, IOUT. With an open-drain MOSFET connected to the
IOUT = ISET pin, the brightness of the output can be controlled
25RCS
by a digital signal, which can be generated by a micro-
There are two basic ways to adjust the brightness con- controller.
trol. The first is to control the output current by changing It takes time for the controller to react to the control
VISET at the ISET pin. This can be done simply by using a signal, so the frequency of this brightness control PWM
potentiometer running off the 6 V VREG rail or 2.5 V VREF signal should be much lower than the bandwidth of the
reference. control loop, which is much slower than the switching
To minimize the board space, layout inflexibility, and frequency. The brightness PWM signal can be in the
reliability concern, users may consider using a digital range of 50 Hz to 500 Hz.
potentiometer, AD5228, rather than its mechanical Figure 7 shows a typical high brightness efficiency
counterpart for the brightness control. AD5228 is a low curve for an LED vs. its driving current. IOPT is the opti-
cost, 32-step, manual control digital potentiometer that mal driving current point with the highest light emitting
features a built-in debouncer and zero-scale/midscale efficiency. The efficiency optimized brightness control
selectable preset. As shown in Figure 6, an AD5228 with approach is to drive the LEDs with a PWM current pat-
two external push buttons adds in the circuit flexibility tern. The current changes from zero to IOPT at a duty
with brightness control. DBRI. This leads to the maximum light-emitting output
This control is simple but may be inefficient because at the continuous IOPT driving. When more light output
the efficiency of LEDs tends to be higher at their full is needed, raise the driving current.

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AN-703
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AN04636–0–1/06(0)
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Figure 6. Brightness Control Using AD5228 Manual Control Digital Potentiometer

LIGHT EMITTING EFFICIENCY

IOPT LED DRIVING CURRENT

Figure 7. Efficiency of a Typical High Brightness LED

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