Description Features: LT1963A Series 1.5A, Low Noise, Fast Transient Response LDO Regulators
Description Features: LT1963A Series 1.5A, Low Noise, Fast Transient Response LDO Regulators
Description Features: LT1963A Series 1.5A, Low Noise, Fast Transient Response LDO Regulators
TYPICAL APPLICATION
Dropout Voltage
3.3V to 2.5V Regulator 400
350
2.5V
DROPOUT VOLTAGE (mV)
IN OUT 300
+ + 1.5A
VIN > 3V 10µF* 10µF*
LT1963A-2.5 250
50
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
OUTPUT CURRENT (A)
1963A TA02
Rev. G
PIN CONFIGURATION
TOP VIEW
GND 1 16 GND
TOP VIEW
FRONT VIEW
OUT 1 8 IN
3 OUT
SENSE/ADJ* 2 7 GND
TAB IS
GND 2 GND GND 3 6 GND
NC 4 5 SHDN
1 IN
S8 PACKAGE
ST PACKAGE 8-LEAD PLASTIC SO
3-LEAD PLASTIC SOT-223 *PIN 2 = SENSE FOR LT1963A-1.5/LT1963A-1.8/
TJMAX = 125°C, θJA = 50°C/W LT1963A-2.5/LT1963A-3.3
= ADJ FOR LT1963A
TJMAX = 125°C, θJA = 70°C/W
Rev. G
Rev. G
Rev. G
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: To satisfy requirements for minimum input voltage, the LT1963A
may cause permanent damage to the device. Exposure to any Absolute (adjustable version) is tested and specified for these conditions with an
Maximum Rating condition for extended periods may affect device external resistor divider (two 4.12k resistors) for an output voltage of 2.4V.
reliability and lifetime. The external resistor divider will add a 300µA DC load on the output.
Note 2: Absolute maximum input to output differential voltage can not Note 7: Dropout voltage is the minimum input to output voltage differential
be achieved with all combinations of rated IN pin and OUT pin voltages. needed to maintain regulation at a specified output current. In dropout, the
With the IN pin at 20V, the OUT pin may not be pulled below 0V. The total output voltage will be equal to: VIN – VDROPOUT.
measured voltage from IN to OUT can not exceed ± 20V. Note 8: GND pin current is tested with VIN = VOUT(NOMINAL) + 1V and a
Note 3: The LT1963A regulators are tested and specified under pulse load current source load. The GND pin current will decrease at higher input
conditions such that TJ ≈ TA. The LT1963AE is 100% tested at TA = 25°C. voltages.
Performance at –40°C and 125°C is assured by design, characterization and Note 9: ADJ pin bias current flows into the ADJ pin.
correlation with statistical process controls. The LT1963AI is guaranteed Note 10: SHDN pin current flows into the SHDN pin.
over the full –40°C to 125°C operating junction temperature range. The Note 11: Reverse output current is tested with the IN pin grounded and the
LT1963AMP is 100% tested and guaranteed over the –55°C to 125°C OUT pin forced to the rated output voltage. This current flows into the OUT
operating junction temperature range. pin and out the GND pin.
Note 4: The LT1963A (adjustable version) is tested and specified for these Note 12: For the LT1963A, LT1963A-1.5 and LT1963A-1.8 dropout voltage
conditions with the ADJ pin connected to the OUT pin. will be limited by the minimum input voltage specification under some
Note 5: Operating conditions are limited by maximum junction output voltage/load conditions.
temperature. The regulated output voltage specification will not apply Note 13: For the ST package, the input reverse leakage current increases
for all possible combinations of input voltage and output current. When due to the additional reverse leakage current for the SHDN pin, which is
operating at maximum input voltage, the output current range must be tied internally to the IN pin.
limited. When operating at maximum output current, the input voltage
range must be limited.
Rev. G
150 200
150
100 100 IL = 100mA
100
50 50 IL = 1mA
0 0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –50 –25 0 25 50 75 100 125
OUTPUT CURRENT (A) OUTPUT CURRENT (A) TEMPERATURE (°C)
1963A G01 1963A G02 1963A G03
1.52 1.82
1.0
OUTPUT VOLTAGE (V)
LT1963A-2.5 Output Voltage LT1963A-3.3 Output Voltage LT1963A ADJ Pin Voltage
2.58 3.38 1.230
IL = 1mA IL = 1mA IL = 1mA
2.56 3.36 1.225
Rev. G
8 8 8
6 6 6
4 4 4
2 2 2
0 0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
1963A G41 1963A G09 1963A G10
LT1963A-3.3 Quiescent Current LT1963A Quiescent Current LT1963A-1.5 GND Pin Current
14 1.4 25
TJ = 25°C TJ = 25°C TJ = 25°C
RL = ∞ RL = 4.3k VSHDN = VIN
12 VSHDN = VIN 1.2 *FOR VOUT = 1.5V
VSHDN = VIN 20
QUIESCENT CURRENT (mA)
4 0.4
5 RL = 15, IL = 100mA*
2 0.2
0 0 0
0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 6 7 8 9 10
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
1963A G11 1963A G12 1963A G42
LT1963A-1.8 GND Pin Current LT1963A-2.5 GND Pin Current LT1963A-3.3 GND Pin Current
25 25 25
TJ = 25°C TJ = 25°C TJ = 25°C
VSHDN = VIN VSHDN = VIN VSHDN = VIN
20 *FOR VOUT = 1.8V 20 *FOR VOUT = 2.5V 20 *FOR VOUT = 3.3V
GND PIN CURRENT (mA)
GND PIN CURRENT (mA)
15 15 15
RL = 8.33, IL = 300mA*
RL = 11, IL = 300mA*
10 10 10
RL = 6, IL = 300mA*
Rev. G
LT1963A GND Pin Current LT1963A-1.5 GND Pin Current LT1963A-1.8 GND Pin Current
10 100 100
TJ = 25°C TJ = 25°C TJ = 25°C
VSHDN = VIN 90 VSHDN = VIN 90 VSHDN = VIN
*FOR VOUT = 1.21V *FOR VOUT = 1.5V 80 *FOR VOUT = 1.8V
8 80
4 40 RL = 1.5, IL = 1A* 40
10 10 RL = 3.6, IL = 500mA*
RL = 121, IL = 10mA*
0 0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
1963A G16 1963A G43 1963A G17
LT1963A-2.5 GND Pin Current LT1963A-3.3 GND Pin Current LT1963A GND Pin Current
100 100 100
TJ = 25°C TJ = 25°C TJ = 25°C
90 VSHDN = VIN 90 VSHDN = VIN 90 VSHDN = VIN
80 *FOR VOUT = 2.5V 80 *FOR VOUT = 3.3V 80 *FOR VOUT = 1.21V
GND PIN CURRENT (mA)
GND PIN CURRENT (mA)
GND Pin Current vs ILOAD SHDN Pin Threshold (On-to-Off) SHDN Pin Threshold (Off-to-On)
100 1.0 1.0
VIN = VOUT (NOMINAL) +1V IL = 1mA
90 0.9 0.9 IL = 1.5A
80 0.8 0.8
SHDN PIN THRESHOLD (V)
70 0.7 0.7
60 0.6 0.6
IL = 1mA
50 0.5 0.5
40 0.4 0.4
30 0.3 0.3
20 0.2 0.2
10 0.1 0.1
0 0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
OUTPUT CURRENT (A) TEMPERATURE (°C) TEMPERATURE (°C)
1963A G21 1963A G22 1963A G23
Rev. G
SHDN Pin Input Current SHDN Pin Input Current ADJ Pin Bias Current
5.0 7 5.0
VSHDN = 20V
4.5 4.5
6
4.0 4.0
2.0 TJ = –50°C
2.5
TJ = 125°C
1.5 2.0
1.5
1.0
1.0
0.5
0.5
ΔVOUT = 100mV
0 0
0 2 4 6 8 10 12 14 16 18 20 –50 –25 0 25 50 75 100 125
INPUT/OUTPUT DIFFERENTIAL (V) TEMPERATURE (°C)
1963A G27 1963A G28
V = 1.5V (LT1963A-1.5)
4.0 0.8 VOUT = 1.8V (LT1963A-1.8)
LT1963A-1.5 OUT
3.5 0.7 VOUT = 2.5V (LT1963A-2.5)
VOUT = 3.3V (LT1963A-3.3)
3.0 0.6
LT1963A LT1963A-1.8/-2.5/-3.3
2.5 0.5
2.0 0.4
LT1963A-3.3 T = 25°C
J LT1963A
1.5 VIN = 0V 0.3
LT1963A-2.5 CURRENT FLOWS INTO
1.0 0.2
OUTPUT PIN
0.5 VOUT = VADJ (LT1963A) 0.1
VOUT = VFB (LT1963A-1.5/1.8/-2.5/-3.3)
0 0
0 1 2 3 4 5 6 7 8 9 10 –50 –25 0 25 50 75 100 125
OUTPUT VOLTAGE (V) TEMPERATURE (°C)
1963A G29 1963A G30
Rev. G
70 74 2.5
IL = 1.5A
64 IL = 0.75A 0.5
10 IL = 0.75A
VIN = VOUT(NOMINAL) +1V + 0.5VP-P
VIN = VOUT(NOMINAL) +1V + 50mVRMS RIPPLE RIPPLE AT f = 120Hz
0 62 0
10 100 1k 10k 100k 1M –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
FREQUENCY (Hz) TEMPERATURE (°C) TEMPERATURE (°C)
1963A G31
1963A G32 1963A G33
0 LT1963A
LT1963A-2.5
LT1963A-1.8 LT1963A-3.3
–5 0.1
LT1963A-2.5
LT1963A-3.3
–10
VIN = VOUT(NOMINAL) +1V LT1963A
LT1963A-1.8
–15 (LT1963A-1.8/-2.5/-3.3)
VIN = 2.7V (LT1963A/LT1963A-1.5) LT1963A-1.5
ΔIL = 1mA TO 1.5A
–20 0.01
–50 –25 0 25 50 75 100 125 10 100 1k 10k 100k
TEMPERATURE (°C) FREQUENCY (Hz)
1963A G34 1963A G35
40 LT1963A-3.3
35
LT1963A-2.5
30
25 VOUT
LT1963A-1.8 100µV/DIV
20
15 LT1963A-1.5
LT1963A
10
5
0 1963A G37
0.0001 0.001 0.01 0.1 1 10 COUT = 10µF 1ms/DIV
LOAD CURRENT (A) ILOAD = 1.5A
1963A G36
Rev. G
OUTPUT VOLTAGE
DEVIATION (mV)
DEVIATION (mV)
100 50
50 0
0 –50
–50 –100
–100 –150
0.6 1.5
CURRENT (A)
CURRENT (A)
VIN = 4.3V
0.4 1.0 CIN = 33µF TANTALUM
LOAD
LOAD
0.2 COUT = 100µF TANTALUM
0.5
+10 × 1µF CERAMIC
0 0
0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 300 350 400 450 500
TIME (µs) TIME (µs)
1963A G38 1963A G39
Rev. G
LT1963A regulators into a low power shutdown state. Figure 1. Kelvin Sense Connection
Rev. G
systems. The devices are protected against both reverse Figure 2. Adjustable Operation
input and reverse output voltages. In battery backup appli-
cations where the output can be held up by a backup bat- make it stable. For the LT1963A, the frequency compensa-
tery when the input is pulled to ground, the LT1963A‑X tion is both internal and external—the output capacitor.
acts like it has a diode in series with its output and prevents The size of the output capacitor, the type of the output
reverse current flow. Additionally, in dual supply applica- capacitor, and the ESR of the particular output capacitor
tions where the regulator load is returned to a negative all affect the stability.
supply, the output can be pulled below ground by as much In addition to stability, the output capacitor also affects
as 20V and still allow the device to start and operate. the high frequency transient response. The regulator
loop has a finite band width. For high frequency transient
Adjustable Operation loads, recovery from a transient is a combination of the
The adjustable version of the LT1963A has an output volt- output capacitor and the bandwidth of the regulator. The
age range of 1.21V to 20V. The output voltage is set by LT1963A was designed to be easy to use and accept a
the ratio of two external resistors as shown in Figure 2. wide variety of output capacitors. However, the frequency
The device servos the output to maintain the voltage at compensation is affected by the output capacitor and opti-
the ADJ pin at 1.21V referenced to ground. The current mum frequency stability may require some ESR, espe-
in R1 is then equal to 1.21V/R1 and the current in R2 is cially with ceramic capacitors.
the current in R1 plus the ADJ pin bias current. The ADJ For ease of use, low ESR polytantalum capacitors
pin bias current, 3µA at 25°C, flows through R2 into the (POSCAP) are a good choice for both the transient
ADJ pin. The output voltage can be calculated using the response and stability of the regulator. These capacitors
formula in Figure 2. The value of R1 should be less than have intrinsic ESR that improves the stability. Ceramic
4.17k to minimize errors in the output voltage caused by capacitors have extremely low ESR, and while they are a
the ADJ pin bias current. Note that in shutdown the output
good choice in many cases, placing a small series resis-
is turned off and the divider current will be zero. tance element will sometimes achieve optimum stability
The adjustable device is tested and specified with the ADJ and minimize ringing. In all cases, a minimum of 10µF is
pin tied to the OUT pin for an output voltage of 1.21V. required while the maximum ESR allowable is 3Ω.
Specifications for output voltages greater than 1.21V will The place where ESR is most helpful with ceramics is
be proportional to the ratio of the desired output voltage low output voltage. At low output voltages, below 2.5V,
to 1.21V: VOUT/1.21V. For example, load regulation for an some ESR helps the stability when ceramic output capac-
output current change of 1mA to 1.5A is – 3mV typical at itors are used. Also, some ESR allows a smaller capaci-
VOUT = 1.21V. At VOUT = 5V, load regulation is: tor value to be used. When small signal ringing occurs
(5V/1.21V)(–3mV) = –12.4mV with ceramics due to insufficient ESR, adding ESR or
increasing the capacitor value improves the stability and
Output Capacitors and Stability reduces the ringing. Table 1 gives some recommended
The LT1963A regulator is a feedback circuit. Like any values of ESR to minimize ringing caused by fast, hard
feedback circuit, frequency compensation is needed to current transitions.
Rev. G
RESR (mΩ)
50mV/DIV
50mV/DIV
50 10
100 20
Figure 3. Figure 6.
RESR (mΩ)
50mV/DIV
50mV/DIV
50 10
100 20
Figure 4. Figure 7.
VOUT = 5V VOUT = 5V
0 IOUT = 500mA WITH 0 IOUT = 500mA WITH
500mA PULSE 500mA PULSE
COUT = 10µF COUT = 100µF
20 5
RESR (mΩ)
RESR (mΩ)
50mV/DIV
50mV/DIV
50 10
100 20
Figure 5. Figure 8.
VOUT = 1.2V
A IOUT = 500mA WITH 500mA PULSE
COUT =
A = 10µF CERAMIC
B = 10µF CERAMIC II 22µF/45mΩ POLY
C = 10µF CERAMIC II 100µF/35mΩ POLY
RESR (mΩ)
50mV/DIV
1963A F09
50µs/DIV
Figure 9.
Rev. G
20 40
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
20
0
X5R X5R
CHANGE IN VALUE (%)
0
–20
–20
–40
–40
Y5V
–60
Y5V –60
Figure 10. Ceramic Capacitor DC Bias Characteristics Figure 11. Ceramic Capacitor Temperature Characteristics
Rev. G
Rev. G
Rev. G
Rev. G
L1
500µH LT1963A-3.3
3.3VOUT
IN OUT
L2 1N4148 1.5A
10VAC AT
+ +
10000µF SHDN FB 22µF
115VIN GND
90-140 1k
VAC 34k*
10VAC AT
115VIN
1N4002 2.4k
TO ALL “+V” C1A
+ 200k
POINTS + 1/2
1N4148
22µF 750Ω LT1018
– 0.1µF
+V
C1B
750Ω + +V
0.033µF
1/2 A1 +
LT1018 1N4148
–
LT1006
– 10k 10k
+V
10k
1µF
+V
R2
0.01Ω LT1963A
IN OUT
R6
6.65k
SHDN SHDN FB
GND R7
4.12k
R3 R4 R5
2.2k 2.2k 1k
3 8
+
1/2 1
2 LT1366
– 4 C3
0.01µF
1963A TA05
Rev. G
.060
(1.524) .390 – .415
.060 TYP (9.906 – 10.541) .165 – .180
.256
(6.502) (1.524) (4.191 – 4.572) .045 – .055
15° TYP (1.143 – 1.397)
+.008
.004 –.004
.060 .183 .059
( )
.330 – .370
(1.524) (4.648) (1.499) +0.203
(8.382 – 9.398) TYP 0.102 –0.102
.095 – .115
(2.413 – 2.921)
.075
(1.905) DETAIL A
.067 .050 ±.012
.300 +.012 .013 – .023
.143 –.020 (1.702) (1.270 ±0.305)
(7.620) (0.330 – 0.584)
.028 – .038 BSC
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
( +0.305
3.632 –0.508 ) (0.711 – 0.965)
TYP
COPPER HEAT SINK
DETAIL A
0° – 7° TYP 0° – 7° TYP
.420
.080
.420 .276
.350 .325
.205
.585 .585
.320
.090 .090
Rev. G
.189 – .197
.045 ±.005 (4.801 – 5.004)
.050 BSC NOTE 3
8 7 6 5
.245
MIN .160 ±.005
.150 – .157
.228 – .244
(3.810 – 3.988)
(5.791 – 6.197)
NOTE 3
.030 ±.005
TYP
1 2 3 4
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45° .053 – .069
(0.254 – 0.508)
(1.346 – 1.752)
.004 – .010
.008 – .010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)
.016 – .050
.014 – .019 .050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
NOTE: TYP BSC
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 REV G 0212
Rev. G
.130 – .146
(3.30 – 3.71)
.039 MAX
.059 MAX
.090
BSC
.181 MAX
.0905 .033 – .041
RECOMMENDED SOLDER PAD LAYOUT
(2.30) (0.84 – 1.04)
BSC
10° – 16°
.010 – .014
.071 10°
(0.25 – 0.36)
(1.80) MAX
MAX
10° – 16°
.024 – .033 .012 .0008 – .0040
(0.60 – 0.84) (0.31) (0.0203 – 0.1016)
.181 MIN
ST3 (SOT-233) 0502
(4.60)
BSC
Rev. G
.230 – .270
(5.842 – 6.858)
.570 – .620
.620
.460 – .500 (14.478 – 15.748)
(15.75)
(11.684 – 12.700) TYP
.330 – .370
.700 – .728
(8.382 – 9.398)
(17.78 – 18.491)
.095 – .115
SEATING PLANE
(2.413 – 2.921)
.152 – .202
.260 – .320 (3.861 – 5.131) .155 – .195*
(6.60 – 8.13) (3.937 – 4.953)
.013 – .023
(0.330 – 0.584)
.067
BSC .028 – .038 .135 – .165
(1.70)
(0.711 – 0.965) (3.429 – 4.191) * MEASURED AT THE SEATING PLANE
T5 (TO-220) 0801
Rev. G
1.05 ±0.10
0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE16 (BB) TSSOP REV L 1216
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 5. BOTTOM EXPOSED PADDLE MAY HAVE METAL PROTRUSION
MILLIMETERS IN THIS AREA. THIS REGION MUST BE FREE OF ANY EXPOSED
2. DIMENSIONS ARE IN TRACES OR VIAS ON PCB LAYOUT
(INCHES)
3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
Rev. G
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 27
LT1963A Series
TYPICAL APPLICATION
Adjustable Current Source
R5
0.01Ω LT1963A-1.8
IN OUT LOAD
C1
+ R1
VIN > 2.7V 1k SHDN FB
10µF
LT1004-1.2 GND
R2 R4 R6 R8
C3
80.6k 2.2k 2.2k 100k
1µF
R3
2k R7
2 8 470Ω
+
1/2 1
LT1366
3
C2
– 4
NOTE: ADJUST R1 FOR 3.3µF
0A TO 1.5A CONSTANT CURRENT 1963A TA04
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1175 500mA, Micropower, Negative LDO VIN: –20V to –4.3V, VOUT(MIN) = –3.8V, VDO = 0.50V, IQ = 45µA, ISD 10µA,
DD, SOT-223, PDIP8 Packages
LT1185 3A, Negative LDO VIN: –35V to –4.2V, VOUT(MIN) = –2.40V, VDO = 0.80V, IQ = 2.5mA, ISD <1µA,
TO220-5 Package
LT1761 100mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 20µA, ISD <1µA
ThinSOT™ Package
LT1762 150mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 25µA, ISD <1µA, MS8 Package
LT1763 500mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 30µA, ISD <1µA, S8 Package
LT1764/ 3A, Low Noise, Fast Transient Response, VIN: 2.7V to 20V, VOUT(MIN) = 1.21V, VDO = 0.34V, IQ = 1mA, ISD <1µA,
LT1764A LDO DD, TO220 Packages
LTC1844 150mA, Very Low Drop-Out LDO VIN: 6.5V to 1.6V, VOUT(MIN) = 1.25V, VDO = 0.08V, IQ = 40µA, ISD < 1µA,
ThinSOT Package
LT1962 300mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.27V, IQ = 30µA, ISD <1µA, MS8 Package
LT1964 200mA, Low Noise Micropower, VIN: –0.9V to –20V, VOUT(MIN) = –1.21V, VDO = 0.34V, IQ = 30µA, ISD 3µA,
Negative LDO ThinSOT Package
LT1965 1.1A, Low Noise, Low Dropout Linear 290mV Dropout Voltage, Low Noise: 40µVRMS, VIN: 1.8V to 20V, VOUT: 1.2V to 19.5V,
Regulator stable with ceramic caps, TO-220, DD-Pak, MSOP and 3mm × 3mm DFN Packages
LT3020 100mA, Low Voltage VLDO, VIN: 0.9V to 10V, VOUT(MIN) = 0.20, VDO = 0.15V, IQ = 120µA, ISD <3µA,
VIN(MIN) = 0.9V DFN, MS8 Packages
LT3023 Dual, 2x 100mA, Low Noise VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 40µA, ISD <1µA,
Micropower, LDO DFN, MS10 Packages
LT3024 Dual, 100mA/500mA, Low Noise VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 60µA, ISD <1µA,
Micropower, LDO DFN, TSSOP Packages
LT3080/ 1.1A, Parallelable, Low Noise, Low 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V,
LT3080-1 Dropout Linear Regulator VOUT: 0V to 35.7V, current-based reference with 1-resistor VOUT set; directly parallelable
(no op amp required), stable with ceramic caps, TO-220, SOT-223, MSOP and 3mm × 3mm
DFN Packages; “–1” version has integrated internal ballast resistor
Rev. G
28
02/21
www.analog.com
For more information www.analog.com ANALOG DEVICES, INC. 2005-2021
Mouser Electronics
Authorized Distributor