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    Digital Logic Design Post Lab Task 4: Dr. Sikandar Gull

    Uploaded by

    Ahmad Afzal
    1) The document describes a digital logic design post lab task where students implemented Boolean functions using logic gates and wrote Verilog code. 2) The task involved expressing Boolean functions as sum of minterms and product of maxterms, drawing circuit diagrams, building circuits using gates, and writing Verilog test benches to simulate the circuits. 3) The critical analysis concluded that the lab helped students learn how to implement Boolean functions using ICs, Verilog, and how to graphically represent functions through simulation without physical implementation.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Digital Logic Design Post Lab Task 4: Dr. Sikandar Gull

    Uploaded by

    Ahmad Afzal
    31 views14 pages
    1) The document describes a digital logic design post lab task where students implemented Boolean functions using logic gates and wrote Verilog code. 2) The task involved expressing Boolean functions as sum of minterms and product of maxterms, drawing circuit diagrams, building circuits using gates, and writing Verilog test benches to simulate the circuits. 3) The critical analysis concluded that the lab helped students learn how to implement Boolean functions using ICs, Verilog, and how to graphically represent functions through simulation without physical implementation.

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    Post Lab 4

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    1) The document describes a digital logic design post lab task where students implemented Boolean functions using logic gates and wrote Verilog code. 2) The task involved expressing Boolean functions as sum of minterms and product of maxterms, drawing circuit diagrams, building circuits using gates, and writing Verilog test benches to simulate the circuits. 3) The critical analysis concluded that the lab helped students learn how to implement Boolean functions using ICs, Verilog, and how to graphically represent functions through simulation without physical implementation.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    31 views14 pages

    Digital Logic Design Post Lab Task 4: Dr. Sikandar Gull

    Uploaded by

    Ahmad Afzal
    1) The document describes a digital logic design post lab task where students implemented Boolean functions using logic gates and wrote Verilog code. 2) The task involved expressing Boolean functions as sum of minterms and product of maxterms, drawing circuit diagrams, building circuits using gates, and writing Verilog test benches to simulate the circuits. 3) The critical analysis concluded that the lab helped students learn how to implement Boolean functions using ICs, Verilog, and how to graphically represent functions through simulation without physical implementation.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 14

    Digital Logic Design

    Post Lab Task 4

    Submitted To:
    Dr. Sikandar Gull
    Submitted By:
    Ghulam Mujtaba (SP21-BSE-030)
    Abubakar (SP21-BSE-005)
    Ahmed Afzal (SP21-BSE-006)
    Ali Hamza (SP21-BSE-010)

    Date: 14th April 2022


    Pre-Lab Tasks:
    1. Express the Boolean function 𝐹 = 𝑥 + 𝑦𝑧 as a sum of minterms by
    using truth table.

    𝒙 𝒚 𝒛 𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝑴𝒂𝒙𝒕𝒆𝒓𝒎𝒔 𝑭 𝑥 + 𝑦z

    0 0 0 𝑚0 =𝑥′𝑦′𝑧′ 𝑀0 = 𝑥 + 𝑦 + 𝑧 0 0
    𝑚1 = 𝑥′𝑦′𝑧 𝑀1 = 𝑥 + 𝑦 + 𝑧′
    0 0 1 1 0
    𝑚2 = 𝑥′𝑦𝑧′ 𝑀2 = 𝑥 + 𝑦′ + 𝑧
    0 1 0 0 0
    𝑚3 =𝑥′𝑦𝑧 𝑀3 = 𝑥+𝑦 ′ +𝑧 ′
    0 1 1 1 1
    𝑚4 = 𝑥𝑦′𝑧′ 𝑀4 = 𝑥′ + 𝑦 + 𝑧
    1 0 0 1 1
    𝑚5 =𝑥𝑦′𝑧 𝑀5 =𝑥 ′ +𝑦+𝑧 ′
    1 0 1 0 1

    1 1 0 𝑚6 =𝑥𝑦𝑧′ 𝑀6 = 𝑥′+𝑦′ + 𝑧 0 1
    𝑚7 = 𝑥𝑦𝑧 𝑀7 = 𝑥′ +𝑦 ′ +𝑧 ′
    1 1 1 0 1
    Sum of minterms:
    F = ∑ (3, 4, 5, 6, 7)
    F = A’BC + AB’C’ + AB’C + ABC’ + ABC

    2. Express 𝐹′ = (𝑥 + 𝑦𝑧)′ as a product of maxterms.

    𝒙 𝒚 𝒛 𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝑴𝒂𝒙𝒕𝒆𝒓𝒎𝒔 𝑭 ′
    𝐹′ = (𝑥 + 𝑦𝑧)

    0 0 0 𝑚0 =𝑥′𝑦′𝑧′ 𝑀0 = 𝑥 + 𝑦 + 𝑧 0 1
    𝑚1 = 𝑥′𝑦′𝑧 𝑀1 = 𝑥 + 𝑦 + 𝑧′
    0 0 1 1 1
    𝑚2 = 𝑥′𝑦𝑧′ 𝑀2 = 𝑥 + 𝑦′ + 𝑧
    0 1 0 0 1
    𝑚3 =𝑥′𝑦𝑧 𝑀3 = 𝑥+𝑦 ′ +𝑧 ′
    0 1 1 1 0

    1 0 0 𝑚4 = 𝑥𝑦′𝑧′ 𝑀4 = 𝑥′ + 𝑦 + 𝑧 1 0
    𝑚5 =𝑥𝑦′𝑧 𝑀5 =𝑥 ′ +𝑦+𝑧 ′
    1 0 1 0 0

    1 1 0 𝑚6 =𝑥𝑦𝑧′ 𝑀6 = 𝑥′+𝑦′ + 𝑧 0 0
    𝑚7 = 𝑥𝑦𝑧 𝑀7 = 𝑥′ +𝑦 ′ +𝑧 ′
    1 1 1 0 0

    Product of maxterms:
    F = π (3,4,5,6,7)
    F = (x’+y+z)(x’+y+z’)(x’+y’+z)(x’+y’+z’)(x+y’+z’)
    3. Given the function as defined in the truth table (Table 4.4), express 𝐹
    using sum of minterms and product of maxterms.

    𝒙 𝒚 𝒛 𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝑴𝒂𝒙𝒕𝒆𝒓𝒎𝒔 𝑭 𝑭
    ̅

    0 0 0 𝑚0 = 𝑥′𝑦′𝑧′ 𝑀0 = 𝑥 + 𝑦 + 𝑧 0 1

    0 0 1 𝑚1 = 𝑥′𝑦′𝑧 𝑀1 = 𝑥 + 𝑦 + 𝑧′ 1 0

    0 1 0 𝑚2 = 𝑥′𝑦𝑧′ 𝑀2 = 𝑥 + 𝑦′ + 𝑧 0 1

    0 1 1 𝑚3 = 𝑥′𝑦𝑧 𝑀3 = 𝑥 + 𝑦′ + 𝑧′ 1 0

    1 0 0 𝑚4 = 𝑥𝑦′𝑧′ 𝑀4 = 𝑥′ + 𝑦 + 𝑧 1 0

    1 0 1 𝑚5 = 𝑥𝑦′𝑧 𝑀5 = 𝑥′ + 𝑦 + 𝑧′ 0 1

    1 1 0 𝑚6 = 𝑥𝑦𝑧′ 𝑀6 = 𝑥′+𝑦′ + 𝑧 0 1
    𝑚7 = 𝑥𝑦𝑧 𝑀7 = 𝑥′ + 𝑦′ + 𝑧′
    1 1 1 0 1

    Sum of minterms:
    F= ∑ (1,3,4)
    F=x’y’z+x’yz+xy’z’

    Product of maxterms using f:

    F= π (0,2,5,6,7)
    F=(x+y+z)(x+y’+z)(x’+y+z’)(x’+y’+z)(x’+y’+z’)
    In-Lab Tasks
    Circuit Implementation
    1. First, make the circuit diagram of the given Task.
    2. Select appropriate logic gate ICs which are needed.
    3. Make connections according to the circuit diagram you made.
    4. Connect the input to data switches and output to the logic indicator.
    5. Follow the input sequence and record the output.

    TASK: Implement the circuit for the given function “F”. Function’s output is
    given in Table 4.5 Finds its Boolean expression in SoP and PoS forms.
    Boolean Equations:
    Sum of Min-terms equation of F:
    A’B’CD+ A’BCD+ AB’C’D’+ ABC’D+ ABCD’+ ABCD

    Reduced SOP form equation of F:


    A’CD+AC’+ABC

    Product of Max-terms equation of F:

    (A+B+C+D)(A+B+C+D’)(A+B+C”+D)(A+B’+C+D)(A+B’+C+D’)(A+B’
    +C’+D)(A’+B+C+D’)(A’+B+C’+D)(A’+B+C’+D’)(A+B+C+D)

    Reduced POS form equation of F:

    (A+C)(A+D)(A+B’)(B’+C+D)(A’+B+D’)(B+C’+D)

    Reduced form calculation:


    Circuit Diagrams:
    1. Sum of Min-terms form:

    2.Reduced SoP form: (Implement circuit by NAND IC(s))


    3.POS Form:

    2. Reduced PoS form: (Implement circuit by using NOR


    IC(s))
    I

    Observed Outputs
    A B C D F
    F1 F2 F3
    I
    0 0 0
    0 0 0 0 0
    0 0 0
    0 0 0 1 0
    ' 0 0 0
    0 0 0 0
    1
    1 1 1
    0 0 1 1
    1
    0 0 0
    1 0 0 0
    0
    I 0 0 0
    0 1 1 0
    0
    0 0 0
    1 1 0
    0 0
    I
    1 1 1
    1 1 1 1
    0
    1 1 1
    1 0 0 0 1

    1 1 0 0 0
    0 0 0
    0 0 0
    1 0 1 0 0
    0 0 0
    1 0 1 1 0
    0 0 0
    1 1 0 0 0
    1 1 1
    1 0 1 1
    1
    1 1 1
    1 1 1 0 1
    1 1 1
    1 1 1 1
    1
    𝑭𝟏: Output of sum of Min-terms form circuit (Simulate on Proteus).
    𝑭𝟐: Output of reduced SoP form circuit implemented using NAND gates (can use
    inverter gates).
    𝑭𝟑: Output of reduced PoS form circuit implemented using NOR gates (can use
    inverter gates)

    Post-Lab Tasks:
    1. Write a Verilog code for the sum of minterms circuit, 𝑭𝟏,
    (Structural Level).
    2. Write a Verilog code for the reduced SoP circuit, 𝑭𝟐, (Structural
    Level).

    3. Write a Verilog code for the reduced PoS circuit 𝑭𝟑, (Structural
    Level).
    4. Simulate and verify the outputs by making an appropriate
    stimulus for the above modules.

    Test Bench:
    Stimulation of F1:

    Stimulation for F2:

    Stimulation for F3:


    Critical Analysis/Conclusion:
    In this lab we figured out how to carry out and plan the Boolean capacity in
    IC'S/Verilog. Through this lab we figured out how to utilize Verilog and
    likewise figured out how to carry out the graphical portrayal of Boolean
    capacities, through Verilog we can carry out capacities without doing
    genuinely.It is simple and accurate to simulate using software.

    -------------------------------------------

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