MX27C1100/27C1024

1M-BIT [128K x 8/64K x 16] CMOS EPROM

FEATURES

• 64K x 16 organization(MX27C1024, JEDEC pin out) • Operating current: 40mA

• 128K x 8 or 64K x 16 organization(MX27C1100, ROM • Standby current: 100uA
pin out compatible) • Package type:
• +12.5V programming voltage - 40 pin plastic DIP
• Fast access time: 55/70/85/100/120/150 ns - 40 pin plastic SOP
• Totally static operation - 44 pin PLCC
• Completely TTL compatible

GENERAL DESCRIPTION
The MX27C1024 is a 5V only, 1M-bit, One Time EPROM programmers may be used. The MX27C1100/
Programmable Read Only Memory. It is organized as 1024 supports a intelligent fast programming algorithm
64K words by 16 bits per word(MX27C1024), 128K x 8 which can result in programming time of less than thirty
or 64K x 16(MX27C1100), operates from a single + 5 seconds.
volt supply, has a static standby mode, and features
fast single address location programming. All program- This EPROM is packaged in industry standard 40 pin
ming signals are TTL levels, requiring a single pulse. For dual-in-line packages, 40 lead SOP and 44 lead PLCC
programming outside from the system, existing packages.

PIN CONFIGURATIONS BLOCK DIAGRAM (MX27C1100)

PDIP/SOP(MX27C1100)
CE
CONTROL OUTPUT Q0~Q14
NC 1 40 A8 OE
LOGIC BUFFERS Q15/A-1
A7 2 39 A9 BYTE/VPP
A6 3 38 A10
A5 4 37 A11
A4 5 36 A12
A3 6 35 A13
A14 . Y-DECODER . Y-SELECT
A2 7 34
A1 8 33 A15 . .
MX27C1100

A0 9 32 NC . .
CE 10 31 BYTE/VPP A0~A15 .
.
GND 11 30 GND ADDRESS 1M BIT
Q15/A-1 . .
OE 12 29
INPUTS X-DECODER CELL
Q0 13 28 Q7 . .
MAXTRIX
Q8 14 27 Q14 . .
Q1 15 26 Q6 .
.
Q9 16 25 Q13
Q2 17 24 Q5
Q10 18 23 Q12 VCC
Q3 19 22 Q4
GND
Q11 20 21 VCC

P/N: PM0156 REV. 4.6, JAN. 14, 2003

1
 MX27C1100/27C1024

PIN CONFIGURATIONS
PDIP/SOP(MX27C1024) PLCC(MX27C1024)

VPP 1 40 VCC

PGM
VCC
VPP
Q13
Q14
Q15

A15
A14
PGM

NC

NC
CE
CE 2 39
Q15 3 38 NC
Q14 4 37 A15 6 1 44 40
Q12 7 39 A13
Q13 5 36 A14
Q11 A12
Q12 6 35 A13
A12 Q10 A11
Q11 7 34
Q10 8 33 A11 Q9 A10
MX27C1024

Q9 9 32 A10 Q8 A9
A9 GND 12
MX27C1024 34 GND
Q8 10 31
GND 11 30 GND NC NC
Q7 12 29 A8 Q7 A8
Q6 13 28 A7
Q6 A7
Q5 14 27 A6
Q5 A6
Q4 15 26 A5
Q4 17 29 A5
Q3 16 25 A4 18 23 28
Q2 17 24 A3

Q3
Q2
Q1
Q0
OE
NC
A0
A1
A2
A3
A4
Q1 18 23 A2
Q0 19 22 A1
OE 20 21 A0

BLOCK DIAGRAM (MX27C1024)

CE
CONTROL OUTPUT Q0~Q15
PGM
LOGIC BUFFERS
OE

. Y-DECODER . Y-DECODER
. .
A0~A15 . .
ADDRESS . .
1M BIT
INPUTS . .
X-DECODER CELL
. .
MAXTRIX
. .
. .

VCC VPP
GND

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 MX27C1100/27C1024

PIN DESCRIPTION(MX27C1100) PIN DESCRIPTION(MX27C1024)

SYMBOL PIN NAME SYMBOL PIN NAME

A0~A15 Address Input A0~A15 Address Input

Q0~Q14 Data Input/Output Q0~Q15 Data Input/Output

CE Chip Enable Input CE Chip Enable Input

OE Output Enable Input OE Output Enable Input

BYTE/VPP Word/Byte Selection PGM Program Enable Input

/Program Supply Voltage VPP Program Supply Voltage

Q15/A-1 Q15(Word mode)/LSB addr. (Byte mode) VCC Power Supply Pin (+5V)

VCC Power Supply Pin (+5V) GND Ground Pin

GND Ground Pin

TRUTH TABLE OF BYTE FUNCTION(MX27C1100)

BYTE MODE(BYTE = GND)
CE OE Q15/A-1 MODE Q0-Q7 SUPPLY CURRENT
H X X Non selected High Z Standby(ICC2)

L H X Non selected High Z Operating(ICC1)

L L A-1 input Selected DOUT Operating(ICC1)

WORD MODE(BYTE = VCC)

CE OE Q15/A-1 MODE Q0-Q14 SUPPLY CURRENT
H X High Z Non selected High Z Standby(ICC2)

L H High Z Non selected High Z Operating(ICC1)

L L DOUT Selected DOUT Operating(ICC1)
NOTE : X = H or L

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 MX27C1100/27C1024

FUNCTIONAL DESCRIPTION VIL(for MX27C1024), OE at VIL, CE at VIH(for

MX27C1100)and VPP at its programming voltage.
THE PROGRAMMING OF THE MX27C1100/1024

When the MX27C1100/1024 is delivered, or it is AUTO IDENTIFY MODE

erased, the chip has all 1M bits in the "ONE" or HIGH
state. "ZEROs" are loaded into the MX27C1100/1024 The auto identify mode allows the reading out of a binary
through the procedure of programming. code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
For programming, the data to be programmed is applied programming equipment for the purpose of
with 16 bits in parallel to the data pins. automatically matching the device to be programmed
with its corresponding programming algorithm. This
VCC must be applied simultaneously or before VPP, and mode is functional in the 25°C ± 5°C ambient
removed simultaneously or after VPP. When temperature range that is required when programming
programming an MXIC EPROM, a 0.1uF capacitor is the MX27C1100/1024.
required across VPP and ground to suppress spurious
voltage transients which may damage the device. To activate this mode, the programming equipment
must force 12.0 ± 0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
FAST PROGRAMMING device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
The device is set up in the fast programming mode when auto identify mode.
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm Byte 0 ( A0 = VIL) represents the manufacturer code,
is shown in Figure 1). The programming is achieved by and byte 1 (A0 = VIH), the device identifier code. For the
applying a single TTL low level 100us pulse to the PGM MX27C1100/1024, these two identifier bytes are given
input after addresses and data line are stable. If the data in the Mode Select Table. All identifiers for manufacturer
is not verified, an additional pulse is applied for a and device codes will possess odd parity, with the MSB
maximum of 25 pulses. This process is repeated while (Q15) defined as the parity bit.
sequencing through each address of the device. When
the programming mode is completed, the data in all
address is verified at VCC = VPP = 5V ± 10%. READ MODE

The MX27C1100/1024 has two control functions, both

PROGRAM INHIBIT MODE of which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
Programming of multiple MX27C1100/1024's in parallel and should be used for device selection. Output Enable
with different data is also easily accomplished by using (OE) is the output control and should be used to gate
the Program Inhibit Mode. Except for CE and OE, all like data to the output pins, independent of device selection.
inputs of the parallel MX27C1100/1024 may be Assuming that addresses are stable, address access
common. A TTL low-level program pulse applied to an time (tACC) is equal to the delay from CE to output (tCE).
MX27C1100/1024 CE input with VPP = 12.5 ± 0.5 V will Data is available at the outputs tOE after the falling edge
program the MX27C1100/1024. A high-level CE input of OE's, assuming that CE has been LOW and
inhibits the other MX27C1100/1024s from being addresses have been stable for at least tACC - t OE.
programmed.

WORD-WIDE MODE
PROGRAM VERIFY MODE
With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present
Verification should be performed on the programmed data Q0-7 and outputs Q8-15 present data Q8-15, after
bits to determine that they were correctly programmed. CE and OE are appropriately enabled.
The verification should be performed with OE and CE at

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 MX27C1100/27C1024

BYTE-WIDE MODE arrays, a 4.7 uF bulk electrolytic capacitor should be

used between VCC and GND for each eight devices.
With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tri- The location of the capacitor should be close to where
stated. If Q15/A-1 = VIH, outputs Q0-7 present data bits the power supply is connected to the array.
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.

STANDBY MODE

The MX27C1100/1024 has a CMOS standby mode

which reduces the maximum VCC current to 100 uA. It
is placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX27C1100/1024 also has a TTL-standby mode
which reduces the maximum VCC current to 1.5 mA. It
is placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-

line control function is provided to allow for:

1. Low memory power dissipation,

2. Assurance that output bus contention will not
occur.

It is recommended that CE be decoded and used as the

primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby

conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM

P/N: PM0156 5 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

MODE SELECT TABLE (MX27C1024)

PINS

MODE CE OE PGM A0 A9 VPP OUTPUTS

Read VIL VIL X X X VCC DOUT
Output Disable VIL VIH X X X VCC High Z

Standby (TTL) VIH X X X X VCC High Z

Standby (CMOS) VCC±0.3V X X X X VCC High Z
Program VIL VIH VIL X X VPP DIN

Program Verify VIL VIL VIH X X VPP DOUT

Program Inhibit VIH X X X X VPP High Z
Manufacturer Code(3) VIL VIL X VIL VH VCC 00C2H

Device Code(3) VIL VIL X VIH VH VCC 0115H

NOTES:1. VH = 12.0 V ± 0.5 V 3. A1 - A8 = A10 - A15 = VIL(For auto select)

2 . X = Either VIH or VIL 4. See DC Programming Characteristics for VPP voltage during
programming.

MODE SELECT TABLE (MX27C1100)

BYTE/
MODE CE OE A9 A0 Q15/A-1 VPP(5) Q8-14 Q0-7
Read (Word) VIL VIL X X Q15 Out VCC Q8-14 Out Q0-7 Out

Read (Upper Byte) VIL VIL X X VIH GND High Z Q8-15 Out
Read (Lower Byte) VIL VIL X X VIL GND High Z Q0-7 Out
Output Disable VIL VIH X X High Z X High Z High Z

Standby VIH X X X High Z X High Z High Z

Program VIL VIH X X Q15 In VPP Q8-14 In Q0-7 In
Program Verify VIH VIL X X Q15 Out VPP Q8-14 Out Q0-7 Out

Program Inhibit VIH VIH X X High Z VPP High Z High Z

Manufacturer Code(3) VIL VIL VH VIL 0B VCC 00H C2H
Device Code(3) VIL VIL VH VIH 0B VCC 01H 12H

NOTES: 1. VH = 12.0V ± 0.5V 4. See DC Programming Characteristics for VPP voltages.

2. X = Either VIH or VIL 5. BYTE/VPP is intended for operation under DC Voltage conditions
3. A1 - A8, A10 - A15 = VIL(For auto select) only.

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 MX27C1100/27C1024

FIGURE 1. FAST PROGRAMMING FLOW CHART

START

ADDRESS = FIRST LOCATION

VCC = 6.25V
VPP = 12.75V

X=0

PROGRAM ONE 50us PULSE

INTERACTIVE INCREMENT X
SECTION

YES
X = 25?

NO

FAIL
VERIFY WORD
?

PASS

NO
INCREMENT ADDRESS LAST ADDRESS

FAIL
YES

VCC = VPP = 5.25V

VERIFY SECTION
FAIL
VERIFY ALL WORDS DEVICE FAILED
?

PASS
DEVICE PASSED

P/N: PM0156 7 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

SWITCHING TEST CIRCUITS

DEVICE 1.8K ohm

+5V
UNDER
TEST

DIODES = IN3064
CL
6.2K ohm OR EQUIVALENT

CL = 100 pF including jig capacitance (30pF for 55/70ns parts)

SWITCHING TEST WAVEFORMS

2.0V 2.0V
AC driving levels TEST POINTS
0.8V 0.8V

INPUT OUTPUT

AC TESTING: AC driving levels are 2.4V/0.4V .

Input pulse rise and fall times are <20ns.

AC driving levels 1.5V TEST POINTS 1.5V

INPUT OUTPUT

AC TESTING: (1) AC driving levels are 3.0V/0V.

Input pulse rise and fall times are < 10ns.
(2) For MX27C1100/1024-55/70

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 MX27C1100/27C1024

ABSOLUTE MAXIMUM RATINGS

NOTICE:
RATING VALUE Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
Ambient Operating Temperature -40oC to 85oC
stress rating only and functional operation of the device at these or
Storage Temperature -65oC to 125oC any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
Applied Input Voltage -0.5V to 7.0V maximum rating conditions for extended period may affect reliability.
Applied Output Voltage -0.5V to VCC + 0.5V
NOTICE:
VCC to Ground Potential -0.5V to 7.0V Specifications contained within the following tables are subject to
change.
A9 & Vpp -0.5V to 13.5V

DC/AC Operating Conditions for Read Operation

MX27C1100/1024
-55* -70 -85 -10 -12 -15

Operating Temperature Commercial 0°C to 55°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C
Industrial ** -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C
Vcc Power Supply Vcc ± 5% Vcc ± 10% Vcc ± 10% Vcc ± 10% Vcc ± 10% Vcc ± 10%

* : 55ns for MX27C1024 only

**:Industrial grade for MX27C1024 only

DC CHARACTERISTICS
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

VOH Output High Voltage 2.4 V IOH = -0.4mA

VOL Output Low Voltage 0.4 V IOL = 2.1mA
VIH Input High Voltage 2.0 VCC + 0.5 V

VIL Input Low Voltage -0.3 0.8 V

ILI Input Leakage Current -10 10 uA VIN = 0 to 5.5V
ILO Output Leakage Current -10 10 uA VOUT = 0 to 5.5V

ICC3 VCC Power-Down Current 100 uA CE = VCC ± 0.3V

ICC2 VCC Standby Current 1.5 mA CE = VIH
ICC1 VCC Active Current 40 mA CE = VIL, f=5MHz, Iout = 0mA

IPP VPP Supply Current Read 10 uA CE = OE = VIL, VPP = 5.5V

CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)

SYMBOL PARAMETER TYP. MAX. UNIT CONDITIONS

CIN Input Capacitance 8 12 pF VIN = 0V

COUT Output Capacitance 8 12 pF VOUT = 0V
CVPP VPP Capacitance 18 25 pF VPP = 0V

P/N: PM0156 9 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

AC CHARACTERISTICS
27C1024-55 27C1100/1024-70 27C1100/1024-85
SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS
tACC Address to Output Delay 55 70 85 ns CE = OE = VIL
tCE Chip Enable to Output Delay 55 70 85 ns OE = VIL
tOE Output Enable to Output Delay 30 35 40 ns CE = VIL
tDF OE High to Output Float, 0 20 0 20 0 25 ns
or CE High to Output Float
tOH Output Hold from Address, 0 0 0 ns
CE or OE which ever occurred first
*tBHA BYTE Access Time 70 85 ns
*tOHB BYTE Output Hold Time 0 0 ns
*tBHZ BYTE Output Delay Time 70 70 ns
*tBLZ BYTE Output Set Time 10 10 ns

* : for MX27C1100 only

AC CHARACTERISTICS
27C1100/1024-10 27C1100/1024-12 27C1100/1024-15
SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS
tACC Address to Output Delay 100 120 150 ns CE = OE = VIL
tCE Chip Enable to Output Delay 100 120 150 ns OE = VIL
tOE Output Enable to Output Delay 45 50 65 ns CE = VIL
tDF OE High to Output Float, 0 30 0 35 0 50 ns
or CE High to Output Float
tOH Output Hold from Address, 0 0 0 ns
CE or OE which ever occurred first
*tBHA BYTE Access Time 100 120 150 ns
*tOHB BYTE Output Hold Time 0 0 0 ns
*tBHZ BYTE Output Delay Time 70 70 70 ns
*tBLZ BYTE Output Set Time 10 10 10 ns

* : for MX27C1100 only

P/N: PM0156 10 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

DC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

VOH Output High Voltage 2.4 V IOH = -0.40mA

VOL Output Low Voltage 0.4 V IOL = 2.1mA
VIH Input High Voltage 2.0 VCC + 0.5 V

VIL Input Low Voltage -0.3 0.8 V

ILI Input Leakage Current -10 10 uA VIN = 0 to 5.5V
VH A9 Auto Select Voltage 11.5 12.5 V

ICC3 VCC Supply Current (Program & Verify) 50 mA

IPP2 VPP Supply Current(Program) 30 mA CE = VIL, OE = VIH
VCC1 Fast Programming Supply Voltage 6.00 6.50 V

VPP1 Fast Programming Voltage 12.5 13.0 V

AC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5°C

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

tAS Address Setup Time 2.0 us

tOES OE Setup Time 2.0 us
tDS Data Setup Time 2.0 us
tAH Address Hold Time 0 us

tDH Data Hold Time 2.0 us

tDFP Output Enable to Output Float Delay 0 130 ns
tVPS VPP Setup Time 2.0 us

tPW PGM Program Pulse Width 95 105 us

tVCS VCC Setup Time 2.0 us
tCES CE Setup Time 2.0 us

tOE Data valid from OE 150 ns

P/N: PM0156 11 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

WAVEFORMS(MX27C1024)
READ CYCLE(WORD MODE)

ADDRESS
DATA ADDRESS
INPUTS
tACC

CE

tCE

OE
tDF

DATA
VALID DATA
OUT
tOE tOH

FAST PROGRAMMING ALGORITHM WAVEFORMS

PROGRAM PROGRAM VERIFY

VIH

Addresses VIL

tAH
tAS Hi-z

DATA DATA IN STABLE DATA OUT VALID

tDS tDH tDFP

VPP1

VPP VCC

tVPS

VCC1

VCC VCC tVCS

VIH

CE VIL

tCES
VIH

PGM VIL

tPW tOES tOE

Max
VIH

OE VIL

P/N: PM0156 12 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

WAVEFORMS(MX27C1100)
READ CYCLE(BYTE MODE)

HIGH-Z HIGH-Z
A-1

tACC tOH
BYTE/VPP

Q0-Q7 VALID DATA VALID DATA

tBHA
tOHB

Q15-Q8 VALID DATA

tBHZ

tBLZ

FAST PROGRAMMING ALGORITHM WAVEFORM

PROGRAM VERIFY
VIH

Addresses VIL VALID ADDRESS

tAH
tAS

DATA DATA SET DATA OUT VALID

tDS tDH tDFP
VPP1

BYTE/VPP VCC

tVPS
VCC1

VCC VCC tVCS

VIH

CE
VIL

tPW tOES tOE

VIH

OE VIL

P/N: PM0156 13 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

ORDER INFORMATION

PLASTIC PACKAGE
PART NO. ACCESS TIME OPERATING CURRENT STANDBY CURRENT PACKAGE
(ns) MAX.(mA) MAX.(uA)
MX27C1100PC-70 70 40 100 40 Pin DIP(ROM pin out)
MX27C1100PC-85 85 40 100 40 Pin DIP(ROM pin out)
MX27C1100PC-10 100 40 100 40 Pin DIP(ROM pin out)
MX27C1100PC-12 120 40 100 40 Pin DIP(ROM pin out)
MX27C1100PC-15 150 40 100 40 Pin DIP(ROM pin out)
MX27C1100MC-70 70 40 100 40 Pin SOP
MX27C1100MC-85 85 40 100 40 Pin SOP
MX27C1100MC-10 100 40 100 40 Pin SOP
MX27C1100MC-12 120 40 100 40 Pin SOP
MX27C1100MC-15 150 40 100 40 Pin SOP
MX27C1024PC-55 55 40 100 40 Pin DIP(JEDEC pin out)
MX27C1024PC-70 70 40 100 40 Pin DIP(JEDEC pin out)
MX27C1024PC-85 85 40 100 40 Pin DIP(JEDEC pin out)
MX27C1024PC-10 100 40 100 40 Pin DIP(JEDEC pin out)
MX27C1024PC-12 120 40 100 40 Pin DIP(JEDEC pin out)
MX27C1024PC-15 150 40 100 40 Pin DIP(JEDEC pin out)
MX27C1024QC-55 55 40 100 44 Pin PLCC
MX27C1024QC-70 70 40 100 44 Pin PLCC
MX27C1024QC-85 85 40 100 44 Pin PLCC
MX27C1024QC-10 100 40 100 44 Pin PLCC
MX27C1024QC-12 120 40 100 44 Pin PLCC
MX27C1024QC-15 150 40 100 44 Pin PLCC
MX27C1024MC-55 55 40 100 40 Pin SOP
MX27C1024MC-70 70 40 100 40 Pin SOP
MX27C1024MC-85 85 40 100 40 Pin SOP
MX27C1024MC-10 100 40 100 40 Pin SOP
MX27C1024MC-12 120 40 100 40 Pin SOP
MX27C1024MC-15 150 40 100 40 Pin SOP

P/N: PM0156 14 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

PACKAGE INFORMATION

P/N: PM0156 15 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

P/N: PM0156 16 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

P/N: PM0156 17 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

REVISION HISTORY

Revision No. Description Page Date

3.0 Revise speed grade from 70/90/120/150ns to 55/70/85/100/ 10/15/1996
120/150ns.
Add 40 pin SOP package type.
4.0 1) Eliminate Interactive Programming Mode. 06/14/1997
2) 40-CDIP package quartz lens, change to square shape.
4.1 IPP : 100uA ----> 10uA 08/08/1997
4.2 Add industrial grade 70/85/100/120/150ns 40-TSOP(I) P15 11/19/1998
4.3 Cancel ceramic DIP package type P1,2,4,15,16 FEB/25/2000
4.4 Cancel "Ultraviolet Erasable" wording in General Description P1 AUG/20/2001
To modify Package Information P15~18
4.5 To modify Package Information P15~18 NOV/19/2002
4.6 1. To remove 10 x 14mm 40-TSOP package type. P1,2,14,18 JAN/14/2003
2. To modify 40-PDIP package information P15

P/N: PM0156 18 REV. 4.6, JAN. 14, 2003

 MX27C1100/27C1024

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