Course Course Course L T P C

18CSS201J ANALOG AND DIGITAL ELECTRONICS S Engineering Sciences

Code Name Category 3 0 2 4

Pre-requisite Co-requisite Progressive

Nil Nil Nil
Courses Courses Courses
Course Offering Department Computer Science and Engineering Data Book / Codes/Standards Nil

Course Learning Rationale (CLR): The purpose of learning this course is to: Learning Program Learning Outcomes (PLO)
CLR-1 : Identify the applications of analog electronics 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLR-2 : Identify the applications of digital logic families

Level of Thinking (Bloom)

Expected Proficiency (%)
Expected Attainment (%)

Individual & Team Work

Engineering Knowledge
CLR-3 : Design the combinational and sequential logic circuits

Design & Development

Project Mgt. & Finance

CLR-4 : Implement the combinational and sequential logic circuits

Modern Tool Usage

Life Long Learning

Society & Culture
Problem Analysis

Analysis, Design,
CLR-5 : Analyze the design of counters and registers

Communication
Environment &
CLR-6 : Utilize the concepts in real time scenarios

Sustainability
Research

PSO – 3
PSO - 1

PSO - 2
Ethics
Course Learning Outcomes (CLO): At the end of this course, learners will be able to:
CLO-1 : Identify the analog and digital components in circuit design 1 80 70 H H - - - - - - - - - - - - -
CLO-2 : Analyze the combinational and sequential logic circuits 2 85 75 H H - - - - - - - - - - - - -
CLO-3 : Apply gates and flip-flops in circuit design 2 75 70 H - H H - - - - - - - - - - -
CLO-4 : Use simulation package and realize 2 85 80 H H H H H - - - - - - H - - -
CLO-5 : Apply HDL code and synthesize 2 85 75 H - H H H - - - - - - - - - -
CLO-6 : Build the circuits in bread board and demonstrate and FGPA 3 80 70 - - H H - H - - H - H - - - -

Introduction to Analog electronics Logic Families Combinational Logic Circuits Sequential Logic circuits Registers & Counters
Duration
15 15 15 15 15
(hour)
Characteristics of BJT (CB, CE and CC Registers and Types of Registers- Serial In
SLO-1 Transistor as a Switch Quine-McCluskey minimization technique Sequential circuits, Latch and Flip-Flops
configurations) and DC biasing - Serial Out, Serial In - Parallel out
S-1
Parallel In - Serial Out, Parallel In - Parallel
SLO-2 BJT Uses Characteristics of Digital ICs Combinational Circuits RS Flip-Flops,
Out
Characteristics and uses of JFET (CS,
SLO-1 DL, RTL Multiplexer Gated Flip-Flops Universal Shift Register
Common Drain and Common Gate)
S-2
SLO-2 Differences between BJT and JFET DTL,TTL Demultiplexer Edge-triggered RS FLIP-FLOP Applications of Shift Registers

SLO-1 Transistor Amplifier: CE amplifier ECL Decoder Edge-triggered D FLIP-FLOPs Synchronous Counters
S-3
SLO-2 Transistor Amplifier: CC ,CB amplifier IIL Encoder Edge-triggered T FLIP-FLOPs Asynchronous Counters
S SLO-1 Lab 1:Design and Implement Half and Full Lab 4: Design and implement transistor Lab 7:Design and implement code Lab 13: Implement SISO, SIPO, PISO and
Lab 10:HDL implementation of Flip-Flop
4-5 SLO-2 Wave Rectifiers using simulation as a switch converters using logic gates simulation PIPO shift registers using Flip- flops
Power Amplifiers: Different classes of Characteristics and uses of MOSFET (CS,
SLO-1 Binary adder Edge-triggered JK FLIPFLOPs Changing the Counter Modulus
Amplifiers and its operation-Class A Common drain and Common gate)
S-6
JK Master-slave FLIP-FLOP
SLO-2 Class B, AB and C MOSFET Logic Binary adder as subtractor Decade Counters
Operational Amplifiers: Ideal v/s practical Analysis of SynchronousSequential Circuit,
SLO-1 PMOS,NMOS Carry look ahead adder Presettable counters
Op-amp State Equation, State table
S-7
SLO-2 Performance Parameters CMOS Logic Decimal adder State Diagram Counter Design as a Synthesis problem
Applications: Peak detector, Comparator, Synthesis of sequential circuit using Flip- Seven segment Display and A Digital
SLO-1 Propagation delay Magnitude Comparator
Inverting, Non-Inverting Amplifiers Flops Clock.
S-8
SLO-2 Problem solving session Problem solving session Problem solving session Problem solving session Problem solving session
S SLO-1 Lab 2: Design and implement Schmitt Lab 5: Design CMOS Inverter, measure Lab 8: Design and implement using Lab 11: Design and implement using
Lab 14:HDL for Registers and Counters
9-10 SLO-2 trigger using Op-Amp (simulation) propagation delay for rising & falling edge simulation the combinational circuits simulation; Synchronous sequential circuits
 Effect of positive and Negative Feedback
SLO-1 Tristate Logic Read Only Memory Asynchronous sequential circuit D/A Conversion
Amplifiers,
S-11
SLO-2 Analysis of Practical Feedback Amplifiers Tristate Logic Applications Arithmetic Logic Unit Transition Table Types of D/A Converters

SLO-1 Oscillator Operation FPGA Basics Programmable Logic Arrays State table Problem
S-12
A/D Conversion
SLO-2 Crystal Oscillator Introduction to HDL and logic simulation HDL Gate and Data Flow modeling Flow table
Overview of UJT, Relaxation Oscillator,555 HDL System primitives, user defined HDL Behavioral modeling Analysis of asynchronous sequential
SLO-1 Types of A/D conversion
Timer primitives, Stimulus to the design circuits
S-13
SLO-2 Problem solving session Problem solving session Problem solving session Problem solving session Problem solving session

S SLO-1 Lab 3:Design and implement using Lab 6: HDLProgram to realize delay and Lab 9: HDL program for combinational Lab 12: HDL program for Sequential Lab 15: Design and Implement an A/D
simulator a rectangular waveform
14-15 SLO-2 stimulus in simple circuit circuits circuits Converter.
generator (Op-Amp relaxation oscillator)

1. Robert L. Boylestad& Louis Nashelsky, Electronic Devices & Circuit Theory, 11th ed., Pearson, 2013 4. Douglas A, G.K. Kharate, Digital Electronics, Oxford university Press,2012
Learning 2. Anil K Maini, Varsha Agarwal: Electronic Devices and Circuits, Wiley, 2012 5. M. Morris R. Mano, Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, VHDL, and
Resources 3. Paul Tuinenga, SPICE: A Guide to Circuit Simulation and Analysis Using PSpice, 3rd ed., Prentice-Hall, SystemVerilog, 6th ed., Pearson, 2018
1995, 6. A.P. Malvino, Electronic Principles,7th Edition, Tata Mcgraw Hill Publications, 2013

Learning Assessment
Continuous Learning Assessment (50% weightage)
Bloom’s Final Examination (50% weightage)
CLA – 1 (10%) CLA – 2 (15%) CLA – 3 (15%) CLA – 4 (10%)#
Level of Thinking
Theory Practice Theory Practice Theory Practice Theory Practice Theory Practice
Remember
Level 1 20% 20% 15% 15% 15% 15% 15% 15% 15% 15%
Understand
Apply
Level 2 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
Analyze
Evaluate
Level 3 10% 10% 15% 15% 15% 15% 15% 15% 15% 15%
Create
Total 100 % 100 % 100 % 100 % 100 %
# CLA – 4 can be from any combination of these: Assignments, Seminars, Tech Talks, Mini-Projects, Case-Studies, Self-Study, MOOCs, Certifications, Conf. Paper etc.,

Course Designers
Experts from Industry Experts from Higher Technical Institutions Internal Experts
1. Dr.Devi Jayaraman , Virtusa, devij@virtusa.com 1.Dr. J. Dhalia Sweetlin, Anna University,jdsweetlin@mitindia.edu 1. Dr. Annapurani Panaiyappan.K, SRMIST
2. Dr. Viswanadhan, Teken BIM Technologies, viswanathan_alladi@yahoo.com 2. Dr. B. Latha, Sairam Engineering College, hod.cse@sairam. edu.in 2. Dr. D. Anitha, SRMIST 3. Ms. Kayalvizhi J, SRMIST