US007072190B2

(12) United States Patent (10) Patent No.: US 7,072,190 B2

Schlecht (45) Date of Patent: Jul. 4, 2006
(54) HIGH EFFICIENCY POWER CONVERTER 4,788,634 A 11/1988 Schlecht et al.
4,812,672 A 3, 1989 Cowan et al.
(75) Inventor: Martin F. Schlecht, Lexington, MA 5,019,954 A 5/1991 Bourgeault et al.
(US) 5,179,512 A 1/1993 Fisher et al.
5,274,543 A 12/1993 Loftus, Jr.
(73) Assignee: SynOor, Inc., Boxborough, MA (US) 5,303,138 A 4, 1994 ROZman
5,343,383 A 8, 1994 Shinada et al.
5,396.412 A 3/1995 Barlage
(*) Notice: Subject to any disclaimer, the term of this 5,442,534 A 8, 1995 Culk et al.
patent is extended or adjusted under 35 5,528,480 A 6/1996 Kikinis et al.
U.S.C. 154(b) by 0 days. 5,528,482 A 6/1996 ROZman
5,621,621 A 4/1997 Lilliestrale
(21) Appl. No.: 10/812,314 5,625,541 A 4/1997 ROZman

(22) Filed: Mar. 29, 2004 (Continued)

(65) Prior Publication Data FOREIGN PATENT DOCUMENTS
EP O 549 920 B1 7, 1993
US 2005/OO24906 A1 Feb. 3, 2005
Related U.S. Application Data (Continued)
OTHER PUBLICATIONS
(60) Continuation of application No. 10/359.457, filed on
Feb. 5, 2003, now Pat. No. 6,731,520, which is a Casey, Leo Francis, “Circuit Design For 1-10 MHZ DC-DC
continuation of application No. 09/821,655, filed on Conversion, MIT Doctoral Thesis, Jan. 1989, pp. 1-216.
Mar. 29, 2001, now Pat. No. 6,594,159, which is a
division of application No. 09/417,867, filed on Oct. (Continued)
13, 1999, now Pat. No. 6,222,742, which is a division Primary Examiner Matthew V. Nguyen
of application No. 09/012,475, filed on Jan. 23, 1998, (74) Attorney, Agent, or Firm Hamilton, Brook, Smith &
now Pat. No. 5,999,417. Reynolds, P.C.
(60) Provisional application No. 60/036.245, filed on Jan.
24, 1997. (57) ABSTRACT

(51) Int. Cl. A power converter nearly losslessly delivers energy and
H02M 3/335 (2006.01) recovers energy from capacitors associated with controlled
(52) U.S. Cl. ................................................... 363/21.06 rectifiers in a secondary winding circuit, each controlled
(58) Field of Classification Search ............ 363/15-17, rectifier having a parallel uncontrolled rectifier. First and
363/21.06, 21.14, 56.01, 56.02, 95, 97,98, second primary Switches in series with first and second
363/131, 132 primary windings, respectively, are turned on for a fixed
See application file for complete search history. duty cycle, each for approximately one half of the Switching
cycle. Switched transition times are short relative to the
(56) References Cited on-state and off-state times of the controlled rectifiers. The
control inputs to the controlled rectifiers are cross-coupled
U.S. PATENT DOCUMENTS from opposite secondary transformer windings.
3,663,941 A 5, 1972 Pasciutti
4,788,450 A 1 1/1988 Wagner 33 Claims, 7 Drawing Sheets

B L
-- Y-y
O ls
W
Cin
QR D
T
R

TER
T
i.
PRI

T2.-Q
C TER
 US 7,072,190 B2
Page 2

U.S. PATENT DOCUMENTS Shoyama, Masahito, et al., “Zero-Voltage-Switched Push

5,663,887 A * 9/1997 Warnet al. ................. TOOf 232 Pull DC-DC Converter.” IEEE, 1991, pp. 223-229.
5,726,869 A 3, 1998 Yamashita et al. Xiao, Li, et al., “Soft Switched PWM DC/DC Converter
5,774,350 A 6, 1998 Notaro et al. With Synchronous Rectifiers.” IEEE 1996, pp. 476-484.
5,870,299 A 2f1999 ROZman Blanchard, Richard, et al., “The Design of a High Efficiency,
5,872,705 A 2/1999 Loftus, Jr. et al. Low Voltage Power Supply Using MOSFET Synchronous
5,880,949 A 3, 1999 Melhem et al.
6,016,258 A 1/2000 Jain et al. Rectification and Current Mode Control.” IEEE, 1985, pp.
6,046,920 A 4/2000 CaZabat et al. 355-361.
6,066,943 A 5/2000 Hastings et al. Jitaru, Ionel Dan, et al., “High Efficiency DC-DC Converter.”
6,088,329 A 7/2000 Lindberg et al. IEEE, 1994, pp. 638-644.
6,252,781 B1* 6/2001 Rinne et al. .................. 363/16 Harper, D.J., et al., “Controlled Synchronous Rectifier.”
6,853,568 B1* 2/2005 Li et al. ...... ... 363.65 HFPC May 1988 Proceedings, pp. 165-172.
2003/0174522 A1* 9, 2003 Xu et al. ...................... 363/22 Acker, Brian, et al., “Current-Controlled Synchronous Rec
2005/0047177 A1* 3, 2005 Tobita ..................... 363.21.06
tification.” IEEE 1994, pp. 185-191.
FOREIGN PATENT DOCUMENTS Murakami, Naoki, et al., “A High-Efficiency 30-W Board
EP 1231705 * 8/2002
Mounted Power Supply Module.” IEEE 1991, pp. 122-127.
JP O6315263. A 11, 1994
Casey, Leo F., et al., “A High Frequency, Low Volume,
WO WO 88,09084 A1 11F1988 Point-of-Load Power Supply for Distributed Power Sys
tems.” IEEE 1987, pp. 439-450.
OTHER PUBLICATIONS Gachora, John Mburu, “Design of a Four-Phase Switchmode
High Efficiency Power Supply,” MIT Master of Engineering
Ferencz, Andrew, “A 250 W High Density Point-of-Load Thesis, 1994, pp. 1-66.
Converter.” MIT Master of Science Thesis, Sep. 1989, pp. Blanchard R., et al., “MOSFETs Move In On Low Voltage
1-117.
Mohandes, Bijan, MOSFET Synchronous Rectifiers Rectification.” Official Proceedings of the Ninth Interna
Achieve 90% Efficiency Part I and Part II, PCIM, Jun. tional PCI '84 Conference, Oct. 29-31, 1984, pp. 213-222.
Garcia, O. et al., “Zero Voltage Switching In The PWM Half
1991, pp. 10-13 & 55-61. Bridge Topology With Complementary Control And Syn
Cobos, J.A., et al., “Resonant Reset Forward Topologies for chronous Rectification,” Record of the Annual Power Elec
Low Output Voltage On Board Converters.” IEEE, 1994, pp. tronics Specialist Conference, Pesc, Atlanta, Jun. 12-15,
703-708.
Tabisz, W.A., et al., “A MOSFET Resonant Synchronous 1995, vol. 1, No. CONF. 26, Jun. 12, 1995, IEEE, pp.
286-291
Rectifier for High-Frequency DC/DC Converters.” Proceed Mweene, L. Haachitaba, et al., “A High-Efficiency 1.5 kW.
ings of the Power Electronics Specialists Conference, San 390-50 V Half-Bridge Converter Operated at 100% Duty
Antonio, TX, Jun. 10-15, 1990, pp. 769-779. Ratio, IEEE, 1992, pp. 723-730.
Wiegman, H.L.N., et al., “A Dual Active Bridge SMPS Mweene, Loveday Haachitaba, “The Design of Front-End
Using Synchronous Rectifiers.” HFPC May 1990 Proceed DC-DC Converters of Distributed Power Supply Systems
ings, pp. 336-346. with Improved Efficiency and Stability.” Thesis, Massachu
Shoyama, Masahito, et al., “Zero-Voltage-Switching Real setts Institute of Technology, Sep. 1992, pp. 1-184.
ized by Magnetizing Current of Transformer in Push-Pull
Current-Fed DC-DC Converter.” IEEE, 1993, pp. 178-184. * cited by examiner
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 US 7,072,190 B2
1. 2
HIGH EFFICIENCY POWER CONVERTER power circuit topology designed to work with synchronous
rectifiers in a manner that better addresses the challenges is
RELATED APPLICATIONS presented here.
In preferred embodiments of the invention, a power
This application is a continuation of application Ser. No. 5 converter comprises a power source and a primary trans
10/359,457, filed Feb. 5, 2003, now U.S. Pat. No. 6,731,520 former winding circuit having at least one primary winding
which continuation of application Ser. No. 09/821,655, filed connected to the source. A secondary transformer winding
Mar. 29, 2001, now U.S. Pat. No. 6,594,159, which is a circuit has at least one secondary winding coupled to the at
divisional of application Ser. No. 09/417,867, filed Oct. 13, least one primary winding. Plural controlled rectifiers, such
1999, now U.S. Pat. No. 6,222,742, which is a divisional of 10 as Voltage controlled field effect transistors, each having a
Ser. No. 09/012,475, filed Jan. 23, 1998, now U.S. Pat. No. parallel uncontrolled rectifier, are connected to a secondary
5,999,417, which claims the benefit of U.S. Provisional winding. Each controlled rectifier is turned on and off in
Application 60/036,245 filed Jan. 24, 1997. The entire synchronization with the Voltage waveform across a primary
teachings of the above applications are incorporated herein winding to provide an output. Each primary winding has a
by reference. 15 Voltage waveform with a fixed duty cycle and transition
times which are short relative to the on-state and off-state
BACKGROUND OF THE INVENTION times of the controlled rectifiers. A regulator regulates the
output while the fixed duty cycle is maintained.
This invention pertains to Switching power converters. A In the preferred embodiments, first and second primary
specific example of a power converter is a DC-DC power transformer windings are connected to the source and first
supply that draws 100 watts of power from a 48 volt DC and second primary Switches are connected in series with the
source and converts it to a 5 volt DC output to drive logic first and second primary windings, respectively. First and
circuitry. The nominal values and ranges of the input and second secondary transformer windings are coupled to the
output voltages, as well as the maximum power handling first and second primary windings, respectively. First and
capability of the converter, depend on the application. 25
second controlled rectifiers, each having a parallel uncon
It is common today for Switching power Supplies to have trolled rectifier, are in series with the first and second
a switching frequency of 100 kHz or higher. Such a high secondary windings, respectively. A controller turns on the
Switching frequency permits the capacitors, inductors, and first and second primary Switches in opposition, each for
transformers in the converter to be physically small. The approximately one half of the Switching cycle with transition
30 times which are short relative to the on-state and off-state
reduction in the overall volume of the converter that results
is desirable to the users of Such Supplies. times of the first and second controlled rectifiers. The first
Another important attribute of a power Supply is its and second controlled rectifiers are controlled to be on at
efficiency. The higher the efficiency, the less heat that is Substantially the same times that the first and second primary
dissipated within the Supply, and the less design effort, Switches, respectively, are on.
35
Volume, weight, and cost that must be devoted to remove In a system embodying the invention, energy may be
this heat. A higher efficiency is therefore also desirable to the nearly losslessly delivered to and recovered from capacitors
users of these Supplies. associated with the controlled rectifiers during their transi
A significant fraction of the energy dissipated in a power tion times.
Supply is due to the on-state (or conduction) loss of the 40 In the preferred embodiments, the first primary and sec
diodes used, particularly if the load and/or source Voltages ondary transformer windings and the second primary and
are low (e.g. 3.3, 5, or 12 volts). In order to reduce this secondary transformer windings are on separate uncoupled
conduction loss, the diodes are sometimes replaced with transformers, but the two primary windings and two sec
transistors whose on-state Voltages are much smaller. These ondary windings may be coupled on a single transformer.
transistors, called synchronous rectifiers, are typically power 45 Preferably, each controlled rectifier is turned on and off by
MOSFETs for converters switching in the 100 kHz and a signal applied to a control terminal relative to a reference
higher range. terminal of the controlled rectifier, and the reference termi
The use of transistors as Synchronous rectifiers in high nals of the controlled rectifiers are connected to a common
Switching frequency converters presents several technical node. Further, the signal that controls each controlled rec
challenges. One is the need to provide properly timed drives 50 tifier is derived from the voltage at the connection between
to the control terminals of these transistors. This task is made the other controlled rectifier and its associated secondary
more complicated when the converter provides electrical winding.
isolation between its input and output because the synchro Regulation may be through a separate regulation stage
nous rectifier drives are then isolated from the drives of the which in one form is on the primary side of the converter as
main, primary side transistors. Another challenge is the need 55 part of the power source. Power conversion may then be
to minimize losses during the Switch transitions of the regulated in response to a variable sensed on the primary
synchronous rectifiers. An important portion of these Switch side of the converter. Alternatively, the regulator may be a
ing losses is due to the need to charge and discharge the regulation stage on the secondary side of the converter, and
parasitic capacitances of the transistors, the parasitic induc power conversion may be regulated by control of the con
tances of interconnections, and the leakage inductance of 60 trolled rectifiers. Specifically, the on-state voltage of a
transformer windings. controlled rectifier may be made larger than its minimum
value to provide regulation, or the on-state duration of a
SUMMARY OF THE INVENTION controlled rectifier may be shorter than its maximum value
to provide regulation.
Various approaches to addressing these technical chal 65 The preferred systems include reset circuits associated
lenges have been presented in the prior art, but further with transformers for flow of magnetizing current. The
improvements are needed. In response to this need, a new energy stored in the magnetizing inductance may be recov
 US 7,072,190 B2
3 4
ered. In one form, the reset circuit comprises a tertiary DETAILED DESCRIPTION OF THE
transformer winding, and in another form it comprises a INVENTION
clamp.
In preferred embodiments, the power source has a current A description of preferred embodiments of the invention
fed output, the current fed output characteristic of the power 5 follows.
source being provided by an inductor. Alternatively, the One embodiment of the invention described herein per
power source may have a Voltage-fed output where the tains to an electrically isolated DC-DC converter that might
Voltage-fed output characteristic of the power source is be used to deliver power at a low DC voltage (e.g. 5 volts)
provided by a capacitor. In either case, the characteristics from a DC source such as a battery or a rectified utility. In
may alternatively be provided by active circuitry. 10 Such a converter a transformer is used to provide the
With the preferred current-fed output, the primary electrical isolation and to provide a step-down (or step-up)
Switches are both turned on during overlapping periods, and in Voltage level according to its turns-ratio. Switches in the
the overlapping periods may be selected to achieve maxi form of power semiconductor transistors and diodes are used
mum efficiency. With the voltage-fed output, the primary in conjunction with capacitors and inductors to create the
Switches are both turned off during overlapping periods. 15 conversion. A control circuit is typically included to provide
Additional leakage or parasitic inductance may be added to the drive signals to the transistors control terminals.
the circuit to accommodate an overlap period. When the switching frequency is high (e.g. 100 kHz and
In one embodiment, a signal controlling a controlled above) it is typical today to use power MOSFETs and
rectifier is derived with a capacitive divider circuit. A circuit Schottky diodes for the converter's switches since these
may determine the DC component of the signal controlling majority carrier devices can undergo faster Switch transi
the controlled rectifier, and the DC component of the signal tions than minority carrier devices such as power bipolar
may be adjusted to provide regulation. transistors and bipolar diodes.
In accordance with another aspect of the invention, an Most DC-DC converters are designed to provide regula
ORing controlled rectifier connects the converter's output to tion of their output voltage in the face of input Voltage and
an output bus to which multiple converter outputs are 25 output current variations. For example, a converter might
coupled, and the ORing controlled rectifier is turned off if need to maintain a 5 volt output (plus or minus a few
the power converter fails. Preferably, the signal controlling percent) as its input varies over the range of 36 to 75 volts
the ORing controlled rectifier is derived from one or more and its output current ranges from 1 to 25 amps. This ability
secondary windings. The ORing controlled rectifier is turned to provide regulation is usually the result of the power
on when the converters output voltage approximately 30 circuit's topology and the manner in which its Switching
matches the bus Voltage. devices are controlled. Sometimes the regulation function is
supplied by (or augmented with) a linear regulator.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a block diagram of a DC-DC converter that
represents one embodiment of the invention. It shows a two
The foregoing and other objects, features and advantages 35 stage converter structure where the power first flows through
of the invention will be apparent from the following more one stage and then through the next. One stage provides the
particular description of preferred embodiments of the regulation function and the other provides the electrical
invention, as illustrated in the accompanying drawings in isolation and/or step-down (or step-up) function. In this
which like reference characters refer to the same parts embodiment the regulation stage is situated before the
throughout the different views. The drawings are not nec 40 isolation stage, but this ordering is not necessary for the
essarily to Scale, emphasis instead being placed upon illus invention. Notice also that the block diagram shows a
trating the principles of the invention. control function. As mentioned, the purpose of this control
FIG. 1 is a block diagram illustrating a preferred embodi function is to determine when the transistors in the power
ment of the invention. circuit will be turned on and off (or to determine the drive
FIG. 2 is a schematic of an embodiment of the invention 45 of a linear regulator). To aid in this function the control
with synchronous rectifiers replaced by diodes. circuit typically senses Voltages and currents at the input, at
FIG. 3 is an illustration of a preferred embodiment of the the output, and/or within the power circuit.
invention with the controlled rectifiers and parallel uncon FIG. 2 shows one way to implement the two power stages
trolled rectifiers illustrated. represented in the block diagram of FIG. 1. In this figure
FIG. 4 illustrates an alternative location of the synchro 50 diodes, rather than synchronous rectifiers, are used to sim
nous rectifiers in the circuit of FIG. 3. plify the initial description of the circuit's operation. The
FIG. 5 illustrates the circuit of FIG. 3 with important topology of the regulation stage is that of a 'down con
parasitic capacitances and inductances illustrated. verter. This canonical Switching cell has a capacitor, C, a
FIG. 6A illustrates another embodiment of the invention transistor, Q, a diode, D, and an inductor, L. Regulation is
with the tertiary winding connected to the primary side. 55 by control of the duty cycle of the transistor Q in response
FIG. 6B illustrates another embodiment of the invention to one or more parameters sensed in the circuit. In a well
with a voltage fed isolation stage. known manner the regulation stage can be modified by
FIG. 7 illustrates a secondary circuit having capacitive providing higher order filters at its input and output, by
dividers to divide the voltages applied to the control termi replacing the diode with a synchronous rectifier, by adding
nals of the controlled rectifiers. 60 resonant elements to create a “multi-resonant converter and
FIG. 8 shows an alternative embodiment in which the the like.
output is regulated by controlling the Voltage applied to the The topology of the isolation stage shown in FIG. 2 has
control terminals of the controlled rectifiers. two transformers that are not, in this case, coupled. Each of
FIG. 9 illustrates an embodiment of the invention in these transformers T1 and T2 has three windings: a primary
which the primary windings are tightly coupled. 65 Winding T1PR, T2er, a secondary winding T1sec, T2sc.
FIG. 10 illustrates the use of an ORing controlled rectifier and a tertiary winding T1, T2. The transformer wind
to couple the power converter to an output bus. ings are connected through MOSFETs Q1 and Q2 on the
 US 7,072,190 B2
5 6
primary windings and through diodes D1, D2, D3, and D4 necessarily equally) between the two halves of the isolation
on the secondary and tertiary windings. The stage is "cur stage. The power flow through the isolation stage is there
rent-fed, in this case by the inductor L. from the output of fore not interrupted (except to charge/discharge parasitic
the regulation stage. By this it is meant that the current capacitances and inductances). This means the output filter
flowing into the primary side of the isolation stage is held 5
(C) can be made much smaller and simpler than would
relatively constant over the time frame of the switching otherwise be necessary. It also means that the isolation stage
cycle. It also means that the Voltage across the primary side does not impose a large fundamental frequency Voltage
of the isolation stage is free to have large, high frequency ripple across the inductor (L) which provides its current-fed
components. The output filter is simply a capacitor C. input characteristic.
whose voltage is relatively constant over the time frame of 10
After an appropriate amount of overlap time has elapsed,
the Switching cycle. Additional filtering stages could be the old primary side transistor (say Q1) is turned off. The
added to this output filter in a known manner. Voltage across this transistor rises as its parasitic capacitance
The operation of the isolation stage proceeds in the is charged by the current that had been flowing through the
following manner. First, for approximately one half of the channel. Once this Voltage rises high enough to forward bias
switching cycle, transistor Q1 is on and Q2 is off. The 15
diode D3 connected to the tertiary winding, the transistor
current flowing through inductor L therefore flows through Voltage becomes clamped, although an over-ring and/or a
the primary winding of transformer T1, and a corresponding commutation interval will occur due to parasitic leakage
current (transformed by the turns ratio) flows through the inductance. Eventually, all of the current in inductor L will
secondary winding of T1 and through diode D1 to the output flow through switch Q2, switch Q1 will be off, and the
filter capacitor C and the load. During this time the magnetizing current of T1 will flow through diode D3.
magnetizing current in T1 is increasing due to the positive
Voltage placed across its windings. This positive Voltage is Now replace output diodes D1 and D2 with MOSFET
determined by the output capacitor Voltage, V, plus the synchronous rectifiers Q3 and Q4, as shown in FIG. 3. Note
forward voltage drop of D1. that in this and later figures, the body diode of the MOSFET
During the second half of the Switching cycle, transistor 25 synchronous rectifier is explicitly shown since it plays a role
Q2 and diode D2 are on and Q1 and D1 are off. While the in the circuit's operation. More generally, the schematical
current of inductor L flows through transformer T2 in the drawings of Q3 and Q4 depict the need for a controlled
same manner as described above for T1, the magnetizing rectifier (e.g. a transistor) and an uncontrolled rectifier (e.g.
current of transformer T1 flows through its tertiary winding a diode) connected in parallel. These two devices may be
and diode D3 to the output filter capacitor, C. This 30 monolithically integrated, as they are for power MOSFETs,
arrangement of the tertiary winding provides a means to or they may be separate components. The positions of these
reset the T1 transformer core with a negative voltage and to synchronous rectifiers in the circuit are slightly different
recover most of the magnetizing inductance energy. The than the positions of the diodes in FIG. 2. They are still in
tertiary winding may alternatively be connected to other series with their respective secondary windings, but are
Suitable points in the power circuit, including those on the 35 connected to the minus output terminal rather than the
primary side of the transformer. positive output terminal. This is done to have the sources of
Other techniques for resetting the core and/or for recov both N-channel MOSFETs connected to a single, DC node.
ering the magnetizing energy are known in the art and may If P-channel MOSFETs are to be used, their position in the
be used here. In particular, the tertiary winding could be circuit would be as shown in the partial schematic of FIG.
eliminated and replaced with a conventional clamp circuit 40 4. This position permits the P-channel devices to also have
attached to either the primary or secondary winding and their sources connected to a single, DC node.
designed to impose a negative Voltage across the transformer As shown in FIG. 3, the gates of the synchronous rectifier
during its operative half cycle. Techniques to recover the MOSFETs are cross-coupled to the opposite transformers.
energy delivered to this clamp circuit, Such as the one in With this connection, the Voltage across one transformer
which a transistor is placed in anti-parallel with a clamping 45 determines the gate Voltage, and therefore the conduction
diode so that energy can flow from the clamping circuitry state (on or off) of the MOSFET connected to the other
back into the magnetizing inductance, could also be used. transformer, and vice versa. These connections therefore
Notice that because the isolation stage of FIG. 2 is fed by provide properly timed drives to the gates of the MOSFETs
an inductor (L), it is important to make Sure there is at least without the need for special secondary side control circuitry.
one path through which the current in this inductor can flow. 50 For instance, during the half cycle in which transistor Q1
At the transitions between each half cycle, it is therefore is turned on and transistor Q2 is off, the current of inductor
typical to turn on the new primary side transistor (say Q2) L flows into the primary of T1 and out its secondary. This
before turning off the old primary side transistor (say Q1). secondary side current will flow through transistor Q3 (note
The time when both transistors are on will be referred to as that even if Q3’s channel is not turned on, the secondary side
an overlap interval. 55 current will flow through the transistor's internal anti
In a conventional current-fed push-pull topology where parallel body diode). The voltage across transformer T1's
all the transformer windings are coupled on a single core, secondary winding is therefore positive, and equal to the
turning on both primary-side transistors will cause the output voltage V plus the Voltage drop across Q3. The
Voltage across the transformer windings to drop to Zero, the Voltage across T2's secondary winding is negative during
output diodes to turn off, and the power to stop flowing 60 this time, with a magnitude approximately equal to the
through the isolation stage. output voltage if the magnetizing inductance reset circuitry
Here, however, since two separate, uncoupled transform takes approximately the whole half cycle to finish its reset
ers are used, the Voltage across the transformer windings function. (The negative secondary winding Voltage may be
does not have to collapse to zero when both Q1 and Q2 are made greater than the positive Voltage so that the core will
on. Instead, both of the output diodes D1 and D2 turn on, 65 finish its reset before the next half cycle begins. This could
both transformers have a voltage across them determined by be accomplished, for example, by using less turns on the
the output voltage, and the current of inductor L splits (not tertiary winding.)
 US 7,072,190 B2
7 8
Referring to FIG. 3, the voltage at node A during this state Switching cycle in many prior art power circuits where
of operation is nearly zero with respect to the indicated diodes are replaced with synchronous rectifiers. Here, how
secondary-side ground node (actually the Voltage is slightly ever, the energy stored in these parasitic components is
negative due to the drop across Q3). The voltage at node B, nearly losslessly delivered to and recovered from them. By
on the other hand, is, following our example, approximately nearly lossless it is meant that no more than approximately
twice the output voltage (say 10 volts for a 5 volt output). 30% of the energy is dissipated. With one implementation of
Given the way these nodes are connected to the Synchronous the present invention, less than 10% dissipation is obtained.
rectifier transistors, Q3 is turned on and Q4 is turned off. The nearly lossless delivery and recovery of energy is
These respective conduction states are consistent with trans achieved because the circuit topology permits the synchro
former T1 delivering the power and transformer T2 being 10 nous rectifier Switch transitions to proceed as oscillations
reset. between inductors and capacitors. These transitions are short
In the second half-cycle when Q2 is on and Q1 is off, the compared to the overall on-state and off-state portions of the
voltage at node B will be nearly Zero (causing Q3 to be off) Switching cycle (e.g. less than 20% of the time is taken up
and the voltage at node A will be approximately twice the by the transition). This characteristic of nearly lossless and
output voltage (causing Q4 to be on). 15 relatively short transitions, which we will call soft switch
During the transition from one half-cycle to the next, the ing, is distinct from that used in full resonant, quasi
sequence of operation is as follows. Start with Q1 and Q3 resonant, or multi-resonant converters where the oscillations
on, Q2 and Q4 off. (The clamp circuit’s diode D4 may still last for a large portion, if not all, of the on-state and/or
be on, or it may have stopped conducting at this point if the off-state time.
magnetizing inductance has finished resetting to Zero.) First, The way in which the soft-switching characteristic is
Q2 is turned on. If we ignore the effects of parasitic achieved can be understood in the following manner. Start
capacitances and inductances, the Voltage across T2 steps with transistors Q1 and Q3 on, Q2 and Q4 off. The voltage
from a negative value to a positive value. The current at node A, and therefore the Voltage across C4, is nearly Zero
flowing through inductor L splits between the two primary and the Voltage at node B (and across C3) is approximately
windings, causing current to flow out of both secondary 25
twice the output voltage. The current flowing through induc
windings. These secondary currents flow through Q3 and tor L., I, is flowing into the primary winding of T1. The
Q4. Since the voltages at both node A and node B are now current flowing out of the secondary winding of T1 is I,
nearly Zero, Q3, which was on, will now be off, and Q4 will minus the current flowing in TI's magnetizing inductance,
remain off (or more precisely, the channels of these two I, both referenced to the secondary side. The magnetizing
devices are off). The secondary side currents therefore flow 30
current is increasing towards its maximum value, Ik.
through the body diodes of Q3 and Q4. which it reaches at the end of the half cycle.
At the end of the overlap interval, Q1 is turned off. The When Q2 is turned on at the end of the half cycle, the
current stops flowing through transformer T1, the body Voltage across both windings of both transformers steps to
diode of Q3 turns off, and the voltage at node A rises from Zero volts in the circuit model depicted in FIG. 5. An L-C
nearly Zero to approximately twice the output voltage as T1 35
oscillatory ring ensues between capacitor C3 and the series
begins its reset half-cycle. With node A voltage high, the combination of the two parasitic inductances, L, and L.
channel of transistor Q4 turns on, and the secondary side If we assume the parasitic capacitances and inductances are
current of transformer T2 commutates from the body diode linear, the Voltage across C3 decreases cosinusoidally
of Q4 to its channel. toward Zero while the current flowing out of the dotted end
Notice that during the overlap interval, the secondary side 40
of T2's secondary winding, I, builds up sinusoidally
currents flow through the body diodes of transistors Q3 and toward a peak determined by the initial voltage across C3
Q4, not their channels. Since these diodes have a high divided by the characteristic impedance
on-state voltage (about 0.9V) compared to the on-state
Voltage of the channel when the gate-source Voltage is high,
a much higher power dissipation occurs during this interval. 45
It is therefore desirable to keep the overlap interval short Lipi + Lp2
compared to the period of the cycle. C
Notice also the benefit of using two, uncoupled trans
formers. The Voltage across a first transformer can be Note that the current flowing out of the dotted end of T1's
changed, causing the channel of the MOSFET synchronous 50
rectifier transistor connected to a second transformer to be secondary winding, I, decreases by the same amount that
turned off, before the voltage across the second transformer I, increases Such that the Sum of the two currents is
is made to change. This could not be done if both primary (I-I), referenced to the secondary side. Also note that
and both secondary windings were tightly coupled in the during this part of the transition, the Voltages across both
same transformer, since the Voltages across all the windings 55 transformers’ secondary windings will be approximately the
would have to change together. output voltage minus half the Voltage across C3. As the
FIG. 5 shows the same topology as FIG. 3, but with oscillation ensues, therefore, the transformer winding Volt
several important parasitic capacitances and inductances ages, which started at Zero, build up toward the output
indicated Schematically. Each indicated capacitor (C3 and Voltage.
C4) represents the combined effect of one synchronous 60 The oscillation described above will continue until either
rectifiers input capacitance and the other rectifiers output the current I reaches (I-I) or the Voltages across C3
capacitance, as well as other parasitic capacitances. Each reaches zero. The first scenario occurs for lower values of
indicated inductor (L, and L) represents the combined (I-I) and the second occurs for higher values of this
effect of a transformer leakage inductance and the parasitic Current.
inductance associated with the loops formed by the primary 65 If I reaches (I-I) first (and assuming the Voltage
side components and the secondary side components. These across C3 has fallen below the threshold voltage of Q3 so
elements store significant energy that is dissipated each that I, is flowing through the body diode of Q3), the
 US 7,072,190 B2
9 10
oscillation stops because the body diode will not let I go the secondary currents are flowing through the body diodes
negative. I and I will hold constant at (I-I) and of Q3 and Q4. It is also desirable to allow the energy
Zero, respectively. Whatever voltage remains across C3 will recovering transitions just described to reach completion.
then discharge linearly due to the current I until the body These two competing desires can be traded off to determine
diode of Q4 turns on. The body diode will then carry I, an optimum overlap duration. In general, it is desirable to
until the overlap interval is over and Q1 is turned off. make sure the new primary switch is turned on before the old
When Q1 is turned off the magnetizing current I will one is turned off, and that the portion of the half-cycle during
charge the parallel capacitance of C4 and C1, the parasitic which the uncontrolled rectifiers are conducting should, for
output capacitance of Q1, until the Voltage across them is efficiency sake, be less than 20%. Note that due to delays in
high enough to forward bias the clamping diode D3. At this 10 the gate drive circuitry it is possible for the overlap interval
point the reset portion of T1's cycle commences. to appear negative at Some point in the control circuit.
Notice that for this first scenario, the complete transition The size of the output filter required to achieve a given
is accomplished with portions of oscillatory rings that, to output voltage ripple is affected by the AC ripple in the
first order, are lossless. (Some loss does occur due to current of inductor L. This ripple current is largely caused by
parasitic series resistance, but this is generally less than 20% 15 the Switching action of the preregulation stage. A larger
of the total energy and typically around 5%.) It could be said inductance, or a higher order filter for the output of the
that the energy that had been stored in L. has been regulation stage, as shown in FIG. 6 where inductor L and
transferred to Le, and that the energy that had been stored capacitor C have been added, will reduce this ripple cur
in C3 has been transferred to C4. rent.
If, on the other hand, the voltage across C3 reaches zero The required size of the output filter is also affected by the
(or, more precisely, a diode drop negative) first, then the AC ripple currents flowing in the magnetizing inductances
body diode of Q4 will turn on and prevent this voltage from of the transformers. Making these inductances as large as
ringing further negative. The currents I, and I (which possible to reduce their ripple currents is therefore desirable.
are flowing through the body diodes of Q3 and Q4) will hold It is also beneficial to connect the tertiary reset windings
constant until the overlap interval is over and Q1 is turned 25 back to a suitable point on the primary side as shown in FIG.
off. 6A where they are connected to capacitor C, rather than to
Once Q1 is turned off, an oscillation ensues between L, connect them to the output filter, as shown in FIG. 3. This
and C1. This oscillation is driven by the current remaining alternative connection reduces by a factor of two the ripple
in L, when Q1 was turned off. Given typical parameter current seen by the output filter due to the magnetizing
values, this oscillation will continue until I reaches Zero. 30 inductance currents, compared to the connection shown in
at which point the body diode of Q3 will turn off. Finally, the FIG. 3, since these magnetizing currents no longer flow to
magnetizing current I charges up the parallel combina the output capacitor during their respective reset half cycles.
tion of C4 and C1 until the clamping diode D3 turns on to The power converter circuits described so far have all had
start the reset half-cycle. an isolation stage that is current fed. It is also possible to
Notice that for this second scenario, the transition is 35 incorporate the invention with an isolation stage that is
almost accomplished in a (to first order) lossless manner. voltage fed. By “voltage fed it is meant that the voltage
Some loss does occur because in the final portion of the across the primary side of the isolation stage is held rela
transition the Voltages across C4 and C1 do not start out tively constant over the time frame of the switching cycle.
equal. C1 has already been partially charged whereas C4 is Such a converter circuit is shown in FIG. 6B where two
still at Zero volts. As these capacitor Voltages equalize, an 40 uncoupled transformers are used.
energy will be lost. This lost energy is a small fraction The operation of the Voltage-fed isolation stage is slightly
(typically less than one third) of the energy stored in C1 different than for a current-fed isolation stage. Each primary
before the equalization occurs. The energy stored in C1 transistor is still turned on for approximately one half the
equals the energy stored in I, when Q1 was turned off. cycle, but instead of providing a brief overlap period during
which itself is a small fraction (typically less than one third) 45 which both primary transistors, Q1 and Q2, are turned on
of the energy that was stored in this parasitic inductance together, here the primary transistors are both turned off for
when it was carrying the full load current, (I-I). As such, a brief overlap period.
the energy lost in this second scenario is a very small During each half cycle, the current flowing into one
fraction (typically less than one ninth) of the total energy primary winding and out its respective secondary winding
originally stored in (or delivered to) L. L., C3 and C4. In 50 can be determined as follows. Say transistors Q1 and Q3
other words, most of the parasitic energy is recovered. have just been turned on to begin a new half cycle. At the
Note that since the second scenario has a small amount of completion of their switch transition they will be carrying
loss, it may be desirable to avoid this scenario by adjusting some initial current (to be discussed in more detail below).
component values. One approach would be to make C3 and There is also a difference between the Voltage across capaci
C4 bigger by augmenting the parasitic capacitors with 55 tor C and the Voltage across capacitor C, both reflected
explicit capacitors placed in parallel. With large enough to the secondary side. This voltage differential will be called
values it is possible to ensure that the first scenario described AV. It appears across the series circuit composed of the
above holds true for the full range of load currents expected. leakage/parasitic inductances and resistances of the primary
The descriptions given above for both scenarios must be and secondary windings, T1 and Tse, the transistors Q1
modified to account for the nonlinear nature of capacitors 60 and Q3, and the capacitors C, and C. The current
C3, C4, and C1, and also to account for the reverse recovery flowing through this series L-R circuit responds to the
charge of the body diodes of Q3 and Q4. The details of the Voltage across it, AV, in accordance with the component
nonlinear waveforms are too complex to be described here, values, all referenced to the secondary side.
but the goal of recovering most of the parasitic energy is still Since C, and Co., are charged and discharged through
achieved. 65 out the half cycle, AV will vary. But if we assume AV is
As mentioned previously, it is desirable to keep the relatively constant, then the current flowing through the
overlap period as short as possible to minimize the time that series L-R circuit will change exponentially with an L/R
 US 7,072,190 B2
11 12
time constant. If this time constant is long compared to the might be slowed down. For instance, in a well known
duration of the half cycle, then the current will have a manner a resistor could be placed in series with the gate of
linearly ramping shape. If the time constant is short, that the the primary side transistor Q1 (or Q2) in FIG. 5 so that its
current will quickly reach a steady value determined by the gate Voltage would change more slowly. Similarly, a resistor
resistance. could be placed in series with the gate of a synchronous
To understand the Switch transitions that occur between rectifier Q3 or (Q4). In either case an RC circuit is created
each half cycle, consider the leakage/parasitic inductances, by the added resistor, R, and the capacitance, C, associated
Le, and L2, and the capacitances associated with the with the transistor. If this RC product is long compared to the
controlled rectifiers, C3 and C4, to be modeled in the same normal length of the oscillatory transitions described above,
way as was shown in FIG. 5. Assume Q2 and Q4 have been 10 the switch transitions will be slowed down.
on and are carrying a final current level, I, at the end of the If the length of the switch transitions are on the order of
half cycle. Transistor Q1 is then turned on, causing the v(LC) or longer, where L is the leakage/parasitic inductance
Voltage V to be applied across primary winding Ti, and (L and/or L) that oscillates with the capacitor C4 (or
its reflected value across secondary winding Ts. An C3), then the nearly lossless transitions described above will
oscillation between C4 and L, will ensue, with the Voltage 15 not be achieved. The more the Switch transitions are slowed
across C4 starting at approximately twice the output Voltage. down, the more the energy delivered to and/or recovered
After approximately one quarter of a cycle of this oscilla from the capacitors associated with the controlled rectifiers
tion, the Voltage across C4 will attempt to go negative and will be dissipated. As such, there is a tradeoff between the
be clamped by the body diode of Q3. At this point the current power converter's efficiency and its other attributes, such as
flowing through L, will have reached a peak value. Is output ripple content. This tradeoff might result in slower
determined by approximately twice the output voltage Switch transitions in situations where high efficiency is not
divided by the characteristic impedance, VL/C4. This required or if better synchronous rectifiers in the future have
transition discharges capacitor C4 and builds up the current much Smaller capacitances.
in L, to the value Is in a nearly lossless manner. As discussed above, the synchronous rectifier MOSFETs
During the quarter cycle of oscillation the Voltage across 25 Q3 and Q4 in the circuit of FIG. 3 are driven with a
the gate of transistor Q4 will drop below the threshold value gate-source Voltage equal to approximately twice the output
for the device, and the channel of Q4 will turn off. The voltage. For a 5 volt output, the 10 volt drive that results is
current that had been flowing through the channel will appropriate for common MOSFETs. If the output voltage is
commutate to the body diode of Q4. Such that the gate drive voltage is too large for the ratings of
At this point current if flowing through both transformers 30 the MOSFET, however, steps must be taken to reduce the
secondary windings and through the body diodes of Q3 and drive voltage. For example, if the output voltage is 15 volts,
Q4. Q3 is carrying the current Is and Q4 is carrying the a 30 voltgate drive will result, and it is typically desired that
current I. Now transistor Q2 is turned off and its voltage the gate be driven to only 10 volts. Also, some MOSFETs
rises as parasitic capacitors are losslessly charged until the are designed to be driven with only 5 volts, or less, at their
voltage is clamped by the diode in series with the tertiary 35 gates.
windings, T2. Inductor L2 now has a negative Voltage FIG. 7 shows one way to reduce the drive voltage while
across it and its current I will therefore linearly ramp maintaining the energy recovery feature. The Voltage wave
down to zero as its energy is recovered back to CB through form at node B (or at node A) is capacitively divided down
the clamping circuit. Once this current reaches Zero, the by the series combination of capacitors Cs and C3 (or by C6
body diode of Q4 will turn off and the current will become 40 and C4). The values of these capacitors are chosen to
negative, but only to the point where it equals the second provide the division of the AC voltage provided at node B
transforms magnetizing current, I (reflected to the sec (or node A) as desired. For example, if node B has a 30 volt
ondary side). This current will linearly charge capacitor C3 step change and a 10 volt step change is desired at the gate
nearly losslessly as energy is delivered to the capacitor from of Q3, then C5 should have one half the capacitance of C3.
the magnetizing inductance of the second transformer (re 45 Since C3 may be comprised of the parasitic capacitance of
flected to the secondary side). This current will linearly Q3, it is likely to be nonlinear. In this case, an effective value
charge capacitor C3 nearly losslessly as energy is delivered of capacitance that relates the large scale change in charge
to the capacitor from the magnetizing inductance of the to the large scale change in Voltage should be used in the
second transformer. calculation to determine C5.
As the voltage across C3 rises above the threshold value, 50 Since a capacitor divider only divides the AC components
transistor Q3 will turn on and the current that had been of a waveform, additional components need to be added to
flowing through the body diode of Q3 will commutate to the determine the DC component of the voltage applied to the
channel of Q3. The new half cycle will then proceed as gates of Q3 and Q4. FIG. 7 shows one way to do this in
discussed above, with Is being the initial value of current which two resistors, R1 and R2 (or R3 and R4), provide the
mentioned in that discussion. 55 correct division of the DC component of the voltage at node
As with the current-fed isolation stage, the transition B (or node A). These resistors should have values large
between the two half cycles has a period of time when the enough to keep their dissipation reasonably Small. On the
two body diodes are conducting. This condition is highly other hand, the resistors should be Small enough Such that
dissipative and should be kept short by keeping the overlap the time constant of the combined capacitor/resistor divider
period that both primary side transistors, Q1 and Q2, are off 60 is short enough to respond to transients such as start-up.
short. Other techniques employing diodes or Zener diodes that
In all of the power converter circuits described above, it are known in the art could be used instead of the resistor
might be desirable to slow down the switch transitions in the technique shown in FIG. 7.
isolation stage for many reasons. For instance, slower tran One variation of the invention described herein would be
sitions might reduce the high frequency differential-mode 65 to create a power Supply with multiple outputs by having
and common-mode ripple components in the output voltage more than one secondary winding on each transformer in the
waveform. There are several ways the switch transitions isolation stage. For example, by using two secondary wind
 US 7,072,190 B2
13 14
ings with the same number of turns it would be possible to Voltage will be driven toward Zero. Z and Z, are imped
create a positive 12 volt output and a negative 12 volt output. ances that should be chosen, with well established tech
If the two secondary windings have a different number of niques, to ensure stability of this feedback loop while
turns it would be possible to create two output voltages of providing the gain desired.
different magnitudes (e.g., 5 volts and 3.3 volts). Another 5 The range of Voltage required at the output of the op-amp
approach for creating multiple outputs would be to have depends on the particular application, and it may include
multiple isolation stages, each with a turns-ratio appropriate negative values. This range influences the Supply Voltage
for their respective output Voltages. requirements for the op-amp. Also, if the op-amps output
When multiple outputs are provided in this manner, a Voltage gets too high, the synchronous rectifiers may not
phenomenon commonly called cross-regulation occurs. A 10 turn off when they are Supposed to. Some means of limiting
single regulation stage cannot control the various output this Voltage. Such as a clamp circuit, may therefore be
Voltages independently, and these output voltages depend desirable.
not just on the relative turns ratios, but also on the Voltage One way to accomplish the second technique, that of
drops that result as the various output currents flow through controlling the portion of the half cycle in which the
the impedances of their various output paths. A change in 15 MOSFET is gated on, is to place a low power switch
any one or more output currents therefore causes a change network between the gate of Q3 (or Q4), node B (or node A),
in the Voltages of those outputs that are not used for and ground. This network (composed, say, of analog
feedback to the regulation stage. If this variation due to Switches operated with digital control signals) might be used
changes in output currents is a problem, then various to keep the gate Voltage grounded for Some period of time
approaches for providing regulation of the uncontrolled after the node Voltage increases, and to then connect the gate
outputs can be provided. For example, a linear regulator to node B (or A) for the remainder of the half cycle with a
might be added to each output that is not otherwise regu switch capable of bidirectional current flow. The length of
lated. the delay would be based on a signal derived from the error
One advantageous approach to providing linear regulation in the output voltage. With this approach, the energy recov
with the power circuits described here is to control how 25 ery feature associated with discharging each synchronous
much the synchronous rectifier MOSFETs are turned on rectifiers gate capacitance is preserved, but the charging
during their conduction state. This can be done by adding transition will become lossy. Alternatively, the switch net
circuitry to limit the peak voltage to which their gates will work could be controlled to start out the half cycle with the
be driven so that their on-state resistances can be made gate connected to node B (or A), and then after some delay
larger than their minimum values. It can also be done by 30 to connect the gate to ground.
controlling the portion of operative half cycle during which Using a synchronous rectifier to provide regulation as
a MOSFETs gate voltage is allowed to be high so that the well as rectification, as described above, is not limited to
MOSFET's body diode conducts for the rest of the time. multiple-output situations. It can also be used in single
With both techniques, the amount to which the output output situations either as the total regulation stage or as an
voltage can be regulated is the difference between the 35
additional regulation stage to augment the first one.
Voltage drop of the synchronous rectifiers when their chan It is also possible to use DC-DC Switching regulators on
nels are fully on (i.e., when they are at their minimum the secondary side to achieve the additional regulation
resistance) and when only their body diodes are carrying the desired, or to create more than one output Voltage from any
Current.
One way to accomplish the first technique, that of con 40
of the outputs of the isolation stage.
trolling the peak gate Voltage, is to use the basic capacitor With multiple outputs it is not necessary for the gate of
divider circuit that was shown in FIG. 7. All that is needed each controlled rectifier to be connected to secondary wind
is to make the resistor divider ratio, (or, alternatively, the ing of the other transformer which corresponds to the same
diode clamping Voltage if Such an approach is chosen) output. For instance, if the two outputs are 5 volts and 3.3
dependent on a control signal derived from the error in the 45 volts, the gates of the 3.3 volts output controlled rectifiers
output voltage compared to its desired value. The goal is to could be connected to the 5 Volt output secondary windings.
shift the DC component of the gate Voltage in response to the Doing so would give these controlled rectifiers a 10 voltgate
error signal Such that the peak voltage applied to the gate, drive, resulting in a lower on-state resistance than if they had
and therefore the on-state resistance and Voltage of the a 6.6 volt gate drive.
synchronous rectifier, helps to minimize this error. Various 50 In some situations, it may be desirable to place the
control circuitry Schemes that might be used to achieve this isolation stage first in the power flow, and to have the
goal will be obvious to one skilled in the art. Note that this regulation stage follow. For example, when there are many
approach preserves the energy recovery feature of the gate outputs sharing the total power, the circuit might be config
drive. Note also that if the voltages at nodes A and B are such ured as one isolation/step-down (or step-up) stage followed
that no AC division is desired, then C5 and C6 should be 55 by several DC-DC switching or linear regulators.
made large compared to C3 and C4. No matter where the isolation stage is situated, if it is to
FIG. 8 shows an alternative method to control the DC be current fed this requirement could be met with active
component of the gate Voltage waveform. The output Volt circuitry as well as by a passive component such as an
age (or a scaled version of it) is Subtracted from a reference inductor. For instance, if the current fed isolation stage
Voltage and the error is multiplied by the gain of an op-amp 60 follows a regulation stage that is achieved with a linear
circuit. The output of the op-amp (node C) is then connected regulator, then this linear regulator could be designed to
to the synchronous rectifier gates through resistors that are have a large AC output impedance to achieve the input
large enough to not significantly alter the AC waveforms at requirement of the current fed isolation stage.
the gates. With this connection, the DC components of the When the regulation stage precedes the isolation stage, it
gate Voltages will equal the output voltage of the op-amp at 65 is not necessary to sense the isolated output Voltage to
node C. If the gain of the op-amp circuit is large enough, control the regulation. An alternative approach is to sense
Such as when an integrator is used, the error in the output the Voltage on the primary side of the isolation stage, which
 US 7,072,190 B2
15 16
may eliminate the need for secondary side circuitry and the When two or more power supplies are connected in
need to bridge the feedback control signal across the isola parallel, diodes are sometimes placed in series with each
tion barrier. Supply’s output to avoid a situation where one Supply’s
For example, in FIG. 6 the Voltage across C, the capaci failure, seen as a short at its output, takes down the entire
tor of the third-order output filter of the down converter, output bus. These “ORing diodes typically dissipate a
could be used. This voltage nearly represents the isolated significant amount of energy. One way to reduce this dissi
output voltage (corrected for the turns-ratio). It differs only pation is to replace the diode with a MOSFET having a
due to the resistive (and parasitic inductance commutation) lower on-state voltage. This “ORing synchronous rectifier
drops between C and the output. Since these drops are small MOSFET can be placed in either output lead, with its body
and proportional to the current flowing through the isolation 10 diode pointing in the direction of the output current flow.
stage, the error in output Voltage they create can either be With the invention described here, the voltage for driving
tolerated or corrected. the gate of this MOSFET, Q5, can be derived by connecting
To correct the error, the current on the primary side could diodes to node A and/or node B (or to nodes of capacitor
be sensed, multiplied by an appropriate gain, and the result dividers connected to these nodes), as shown in FIG. 10.
used to modify the reference voltage to which the voltage 15 These diodes rectify the switching waveforms at node A
across C is compared. Since these resistive drops vary with and/or node B to give a constant Voltage Suitable for turning
temperature, it might also be desirable to include tempera on the ORing MOSFET at node D. A filter capacitor, C.
ture compensation in the control circuitry. Note that this might be added to the circuit as shown in the figure, or the
approach could also be used to correct for resistive drops parasitic input capacitance of the ORing MOSFET might be
along the leads connecting the Supply’s output to its load. used alone. A resistor RF ensures the gate Voltage discharges
The embodiments of the invention described above have when the drive is removed.
used two uncoupled transformers for the isolation stage. It is If the power Supply fails in a way that creates a short at
also possible, as shown in FIG.9, to use a single transformer its output, Such as when a synchronous rectifier shorts, the
T in which, for example, there are two primary windings voltages at nodes A and B will also be shorted after the
Terri, Terr and two secondary windings, Tsic, Tsec2. 25 transient is complete. With its gate drive no longer Supplied,
While the two primary windings may be tightly coupled, the ORing MOSFET will turn off, and the failed supply will
either the two secondaries should be loosely coupled to each be disconnected from the output bus.
other or the connections to the output capacitors and Syn When two (or more) power supplies of the type described
chronous rectifier transistors should provide adequate para here are placed in parallel, a problem can arise. If one power
sitic inductance. The resulting leakage and parasitic induc 30 supply is turned on while another is left off (i.e. not
tance on the secondary side can then be modeled as is shown Switching), the output bus Voltage generated by the first
in FIG. 9. supply will appear at the gates of the second supply’s
With this inductance present in the secondary side loops, synchronous rectifiers. Once this voltage rises above the
the operation of the coupled isolation stage during the threshold value, these synchronous rectifiers will turn on and
overlap period is similar to what was described above for the 35 draw current. At the least this will result in extra dissipation,
uncoupled case. With Q1 and Q3 on, turn Q2 on. The voltage but it could result in a shorted output bus. This problem can
across the transformer windings, as modeled in FIG. 9, drops occur even if both supplies are turned on and off together if
to zero, which is consistent with what must happen if the one supply’s transition “gets ahead of the other.
primary windings are tightly coupled. A nearly-lossless There are several approaches to solving this problem. One
energy saving transition involving inductor/capacitor oscil 40 is to make Sure both Supplies have matched transitions.
lations and linear discharges then ensues. Another is to connect the supplies together with ORing
What is different here is that the overlap period during diodes so that no supply can draw current from the combined
which both Q1 and Q2 are on cannot last too long. If the output bus. If an ORing MOSFET is used instead of an
overlap lasts too long, the transient waveforms will settle ORing diode, however, this second approach can still fail to
into a state where the voltages at nodes A and B rise to the 45 solve the problem. For instance, consider the case where a
output Voltage. If this Voltage is higher than the gates supply drives its ORing MOSFET with the technique shown
threshold levels, transistors Q3 and Q4 will partially turn on. in FIG. 10. Assume the bus voltage is already high due to
A large amount of energy will then be dissipated while this another Supply, and the first Supply is then turned on in a way
state persists, and it is possible for the output capacitor to be that causes its output voltage to rise slowly toward its
significantly discharged. 50 desired value. If the ORing MOSFETs gate voltage rises
These problems can be avoided by making sure the high enough to turn it on before the newly rising output
overlap period when both Q1 and Q2 are on does not last too Voltage approximately matches the existing bus Voltage,
long. For a given converter, an overlap period can be found then there will be at least a momentary large current flow as
which will give the highest converter efficiency. The more the two voltages equalize. To avoid this problem additional
leakage/parasitic inductance there is, the longer an overlap 55 circuitry can be added to make sure an ORing MOSFET is
period that can be tolerated. Based on the overlap time not turned on until its Supply’s output voltage has approxi
provided by a given control circuit, it may become necessary mately reached the bus voltage. This might be done by
to add additional inductance by increasing the leakage or sensing the two Voltages and taking appropriate action, or it
parasitic inductance. might be done by providing a delay between when the
With a coupled transformer it is not necessary to provide 60 ORing MOSFETs gate drive is made available and when it
a separate reset circuit (whether it uses a tertiary winding or is actually applied to the gate. Such a delay should only
not) since the magnetizing current always has a path through affect the turn-on, however; the turn-off of the ORing
which it can flow. With a coupled transformer it is necessary MOSFET should have minimal delay so that the protective
to keep the lengths of the two halves of the cycle well function of the transistor can be provided.
balanced to avoid imposing an average Voltage across the 65 While this invention has been particularly shown and
core and driving it into Saturation. Several techniques for described with references to preferred embodiments thereof,
balancing the two half cycles are well known in the art. it will be understood by those skilled in the art that various
 US 7,072,190 B2
17 18
changes in form and details may be made therein without 11. A power converter system as claimed in claim 1
departing from the spirit and scope of the invention as wherein energy is nearly losslessly delivered to and recov
defined by the appended claims. Those skilled in the art will ered from capacitors associated with the controlled rectifi
recognize or be able to ascertain using no more than routine CS.
experimentation, many equivalents to the specific embodi 12. A power converter system as claimed in claim 1
ments of the invention described specifically herein. Such wherein each controlled rectifier is turned on and off by a
equivalents are intended to be encompassed in the scope of signal applied to a control terminal relative to a reference
the claims. For instance, the regulation stage could be terminal of the controlled rectifier and the reference termi
composed of an up-converter. The ideas that have been nals of the controlled rectifiers are connected to a common
presented in terms of the N-channel implementation of the 10 node.
synchronous rectifier MOSFET can be modified to apply to 13. A power converter system as claimed in claim 1
the P-channel implementation, as well. The components wherein the isolation stage is a step down stage.
shown in the schematics of the figures (such as Q3 in FIG. 14. A power converter system as claimed in claim 1
3) could be implemented with several discrete parts con wherein the regulation stage output is of a Voltage level to
nected in parallel. In addition, certain aspects of the inven 15 drive logic circuitry.
tion could be applied to a power converter having only one 15. A power converter system as claimed in claim 14
primary transformer winding and/or one secondary trans wherein the regulation stage output is about 5 volts or less.
former winding. 16. A power converter system as claimed in claim 14
wherein the regulation stage output is about 3.3 volts.
What is claimed is: 17. A power converter system as claimed in claim 1
1. A power converter system comprising: wherein the DC power source provides a voltage that varies
a DC power source: over the range of 36 to 75 volts.
a non-regulating isolation stage comprising: 18. A power converter system as claimed in claim 1
wherein the DC power source provides a voltage within the
a primary transformer winding circuit having at least 25 range of 36 to 75 volts.
one primary winding connected to the Source; and 19. A power converter system as claimed in claim 18
a secondary transformer winding circuit having at least wherein the regulation stage output is of a Voltage level to
one secondary winding coupled to the at least one drive logic circuitry.
primary winding and having plural controlled recti 20. A power converter system comprising:
fiers, each having a parallel uncontrolled rectifier and 30 a DC power source:
each connected to a secondary winding, each con a non-regulating isolation stage comprising:
trolled rectifier being turned on and off in synchro a primary transformer winding circuit having at least
nization with the Voltage waveform across a primary one primary winding connected to the Source; and
winding to provide an output, each primary winding a secondary transformer winding circuit having at least
having a Voltage waveform with a fixed duty cycle 35 one secondary winding coupled to the at least one
and transition times which are short relative to the primary winding and having plural controlled recti
on-state and off-state times of the controlled rectifi fiers, each having a parallel uncontrolled rectifier and
ers; and each connected to a secondary winding, each con
a plurality of non-isolating regulation stages, each receiv trolled rectifier being turned on and off in synchro
ing the output of the isolation stage and regulating a 40 nization with the Voltage waveform across a primary
regulation stage output while the fixed duty cycle of the winding to provide an output; and
isolation stage is maintained. a plurality of non-isolating regulation stages, each receiv
2. A power converter system as claimed in claim 1 ing the output of the isolation stage and regulating a
wherein the regulation stages are Switching regulators. regulation stage output.
3. A power converter system as claimed in claim 2 45 21. A power converter system as claimed in claim 20
wherein the regulation stages are down converters. wherein the regulation stages are down converters.
4. A power converter system as claimed in claim 2 22. A power converter system as claimed in claim 20
wherein a Switch in the Switching regulator is a controlled wherein the signal controlling a controlled rectifier is pro
rectifier. vided by a transformer winding.
5. A power converter system as claimed in claim 1 50 23. A power converter system as claimed in claim 20
wherein the first and second controlled rectifiers are voltage wherein the isolation stage is a step down stage.
controlled field effect transistors. 24. A power converter system as claimed in claim 20
6. A power converter system as claimed in claim 1 wherein the DC power source provides a voltage within the
wherein the DC power source has a voltage-fed output range of 36 to 75 volts.
characteristic. 55 25. A power converter system as claimed in claim 20
7. A power converter system as claimed in claim 2 wherein the output of the isolation stage is about 12 volts.
wherein the voltage fed output characteristic of the DC 26. A power converter system as claimed in claim 25
power source is provided by a capacitor. wherein a regulation stage output is of a Voltage level to
drive logic circuitry.
8. A power converter system as claimed in claim 1 60 27. A power converter system comprising:
wherein the signal controlling a controlled rectifier is pro a DC power source:
vided by a transformer winding. an isolation stage comprising:
9. A power converter system as claimed in claim 1 a primary transformer winding circuit having at least
wherein the output of the isolation stage is about 12 volts. one primary winding connected to the Source; and
10. A power converter system as claimed in claim 9 65 a secondary transformer winding circuit having at least
wherein the regulation stage output is of a Voltage level to one secondary winding coupled to the at least one
drive logic circuitry. primary winding; and plural controlled rectifiers,
 US 7,072,190 B2
19 20
each having a parallel uncontrolled rectifier and each from the isolated output, providing plural regulated out
connected to a secondary winding, each controlled puts without further isolation.
rectifier being turned on and off in Synchronization 31. A method as claimed in claim 30 wherein each
with the Voltage waveform across a primary winding primary winding has a Voltage waveform with a fixed duty
to provide an output voltage whose value drops with 5
increasing current flow through the isolation stage; cycle and transition times which are short relative to the
and on-state and off-state times of the controlled rectifiers.
a plurality of non-isolating regulation stages, each receiv 32. A method as claimed in claim 30 wherein the isolated
ing the output of the isolation stage and regulating a output is a Voltage whose value drops with increasing
regulation stage output. 10 current flow.
28. A power converter system as claimed in claim 27 33. A method of providing multiple DC outputs compris
wherein each primary winding has a Voltage waveform with ing:
a fixed duty cycle and transition times which are short
relative to the on-state and off-state times of the controlled from a DC power Source providing an isolated output by
rectifiers. 15 applying power through at least one primary winding
29. A power converter system as claimed in claim 27 connected to the source and at least one secondary
wherein the isolation stage is non-regulating. winding coupled to the at least one primary winding,
30. A method of providing multiple DC outputs compris the at least one secondary winding being in a secondary
ing: transformer winding circuit having plural controlled
from a DC power source providing an isolated output rectifiers, each having a parallel uncontrolled rectifier
without regulation by applying power through at least and each connected to a secondary winding, each
one primary winding connected to the Source and at controlled rectifier being turned on and off in synchro
least one secondary winding coupled to the at least one nization with the Voltage waveform across a primary
primary winding, the at least one secondary winding winding to provide an isolated output, the isolated
being in a secondary transformer winding circuit hav 25
output being a Voltage whose value drops with increas
ing plural controlled rectifiers, each having a parallel ing current flow; and
uncontrolled rectifier and each connected to a second
ary winding, each controlled rectifier being turned on from the isolated output, providing plural regulated out
and off in synchronization with the voltage waveform puts without further isolation.
across a primary winding to provide an isolated output; 30
and
 UNITED STATES PATENT AND TRADEMARK OFFICE
CERTIFICATE OF CORRECTION

PATENT NO. : 7,072,190 B2 Page 1 of 1

APPLICATIONNO. : 10/812314
DATED : July 4, 2006
INVENTOR(S) : Martin F. Schlecht
It is certified that error appears in the above-identified patent and that said Letters Patent is
hereby corrected as shown below:

Column 17
Claim 7, line 57, delete “2 and insert --6--.

Signed and Sealed this

Twenty-first Day of November, 2006

WDJ
JON. W. DUDAS
Director of the United States Patent and Trademark Office
 UNITED STATES PATENT AND TRADEMARK OFFICE
CERTIFICATE OF CORRECTION
PATENT NO. : 7,072,190 C1 Page 1 of 1
APPLICATIONNO. : 95/001207
DATED : September 15, 2014
INVENTOR(S) : Martin F. Schlecht

It is certified that error appears in the above-identified patent and that said Letters Patent is hereby corrected as shown below:

On the title page of the above-referenced U.S. Reexamination Certificate in the Assignee section,
please delete “Bank of America N.A. and insert -- SynOor, Inc. --.

Signed and Sealed this

Seventh Day of October, 2014
74-4-04- 2% 4 Michelle K. Lee
Deputy Director of the United States Patent and Trademark Office
 US007072190C1

(12) INTERPARTES REEXAMINATION CERTIFICATE (961st)

United States Patent (10) Number: US 7,072,190 C1
Schlecht (45) Certificate Issued: Sep. 15, 2014
(54) HIGH EFFICIENCY POWER CONVERTER (51) Int. Cl.
HO2M3/335 (2006.01)
(75) Inventor: Martin F. Schlecht, Lexington, MA (52) U.S. Cl.
(US) USPC ....................................................... 363/21.06
(73) Assignee: Bank America, N.A., New York, NY (58) Field of Classification Search
None
(US) See application file for complete search history.
Reexamination Request: (56) References Cited
No. 95/001207, Aug. 19, 2009
Reexamination Certificate for: To view the complete listing of prior art documents cited
Patent No.: 7,072,190 during the proceeding for Reexamination Control Number
Issued: Jul. 4, 2006 95/001207, please refer to the USPTO's public Patent
Appl. No.: 10/812,314 Application Information Retrieval (PAIR) system under the
Filed: Mar. 29, 2004 Display References tab.
Certificate of Correction issued Nov. 21, 2006 Primary Examiner — My Trang Nu Ton
Related U.S. Application Data (57) ABSTRACT
(60) Continuation of application No. 10/359.457, filed on A power converter nearly losslessly delivers energy and
Feb. 5, 2003, now Pat. No. 6,731,520, which is a recovers energy from capacitors associated with controlled
continuation of application No. 09/821,655, filed on rectifiers in a secondary winding circuit, each controlled rec
Mar. 29, 2001, now Pat. No. 6,594,159, which is a tifier having a parallel uncontrolled rectifier. First and second
division of application No. 09/417,867, filed on Oct. primary Switches in series with first and second primary
13, 1999, now Pat. No. 6,222,742, which is a division windings, respectively, are turned on for a fixed duty cycle,
of application No. 09/012,475, filed on Jan. 23, 1998, each for approximately one half of the Switching cycle.
Switched transition times are short relative to the on-state and
now Pat. No. 5,999,417. off-state times of the controlled rectifiers. The control inputs
(60) Provisional application No. 60/036.245, filed on Jan. to the controlled rectifiers are cross-coupled from opposite
24, 1997. secondary transformer windings.
 US 7,072,190 C1
1.
INTERPARTES
REEXAMINATION CERTIFICATE
ISSUED UNDER 35 U.S.C. 316
NO AMENDMENTS HAVE BEEN MADE TO
THE PATENT

AS A RESULT OF REEXAMINATION, IT HAS BEEN

DETERMINED THAT: 10

The patentability of claims 1-33 is confirmed.

k k k k k