Electronic CKT and Dig Lab Manual

EASWARI ENGINEERING COLLEGE
(An Autonomous institution)
DEPARTMENT OF ROBOTICS AND AUTOMATION ENGINEERING
(REGULATION 2019)
LABORATORY MANUAL
ACADEMIC YEAR 2022-2023
LAB NAME : ELECTRONIC CIRCUITS AND DIGITAL LABORATORY
LAB CODE : 191ECS332L

SEMESTER : III
YEAR : II
Prepared by Approved by
S.R.SRIRAM, AP/ECE HOD /ECE
1
SYLLABUS
Course Code Course Title Periods per week

Credits
ELECTRONIC CIRCUITS AND DIGITAL L T P R
191ECS332L
LABORATORY 0 0 2 0 1
PREREQUISITES:
NIL
COURSE OBJECTIVES:
1. To practically train the students to study the characteristics of electronic components and circuits
LIST OF EXPERIMENTS
1. Characteristics of diode and clipper circuits
2. Characteristics of Zener diode and Zener voltage regulator.
3. Characteristics of BJT.
4. Characteristics of JFET.
5. Application of BJT as an amplifier and switch.
6. Study of Basic Digital IC’s.
7. Implementation of Adder and subtractor circuits.
8. Design of Code converters.
9. Study of Multiplexer and Demultiplexer.
10 Design and implementation of counters and registers
TOTAL PERIODS: 30
COURSE OUTCOMES:
Upon completion of this course, student will be able to:
CO1: Obtain the characteristics of PN Diode, Zener diode.
CO2: Obtain the characteristics of BJT, JFET.
CO3: Perform the operation with digital IC’s.
CO4: Design and Implement combinational circuits.
CO5: Design and Implement Sequential circuits.
2
List of Experiments
Cycle I
1. Characteristics of PN diode and clipper circuit

3. Characteristics of BJT – CE configuration
Cycle II

5. Design and implementation of counters and registers
EXPERIMENT BEYOND SYLLABUS
1. Design of RC Phase shift Oscillator
3
INDEX
EXPT. PAGE STAFF

DATE NAME OF THE EXPERIMENT MARKS
NO. NO. INITIAL
Characteristics of PN diode and clipper

1.
circuit
Characteristics of Zener diode and Zener

2.
voltage regulator.
Application of BJT as an amplifier and

5.
switch.
Implementation of Adder and subtractor

7.
circuits.
Design and implementation of counters and

10.
registers
4
Format no. LP-01
Issue No.02
Issue Date: 28-01-2012
EASWARI ENGINEERING COLLEGE
(AUTONOMOUS)
DEPARTMENT OF ROBOTICS AND AUTOMATION ENGINEERING
COURSE PLAN
(Regulation 2019)
Subject Code : 191ECS332L Total no. of hours given in syllabus

Title : ELECTRONIC CIRCUITS Lecture : --
AND DIGITAL
LABORATORY
Course/Branch : B.E / RAE Practical : 30
Year/Semester : II/III Tutorial : --
Academic Year : 2022-2023 TOTAL : 30
Faculty Name : Dr.S.R.Sriram, AP/ECE
COURSE OBJECTIVES:
To practically train the students to study the characteristics of electronic components and circuits
No. of
S. No. Topic
Hours
1. 3
Characteristics of PN diode and clipper circuit
3
3
3
3
3
3
3
3
3
10. Design and implementation of counters and registers

3
5
PROGRAM OUTCOMES:
Engineering Graduates will be able to:
Engineering knowledge: Apply the knowledge of mathematics, science, engineering

PO1 fundamentals, and an engineering specialization to the solution of complex engineering
problems.
Problem analysis: Identify, formulate, review research literature, and analyze complex
PO2 engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
PO3
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
Conduct investigations of complex problems: Use research-based knowledge and research
PO4 methods including design of experiments, analysis and interpretation of data, and synthesis of
the information to provide valid conclusions.
Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
PO5 engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the contextual knowledge to assess
PO6 societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
Environment and sustainability: Understand the impact of the professional engineering
PO7 solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
PO8
norms of the engineering practice.
Individual and team work: Function effectively as an individual, and as a member or leader
PO9
in diverse teams, and in multidisciplinary settings.
Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
PO10
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
Project management and finance: Demonstrate knowledge and understanding of the
PO11 engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
Life-long learning: Recognize the need for, and have the preparation and ability to engage in
PO12
independent and life-long learning in the broadest context of technological change.
PROGRAM SPECIFIC OUTCOMES:
To design and construct analog and digital circuits and to simulate the integrated circuits with
PSO1
software tools which lead to the development of electronic gadgets.
To design and analyze various signal & image processing blocks for communication areas and
PSO2 to implement their professional skills and techniques in network fields which are applicable to
industrial and societal needs.
6
COURSE OUTCOMES:
Students will be able to
191ECS332L.1 Obtain the characteristics of PN Diode, Zener diode.
191ECS332L.2 Obtain the characteristics of BJT, JFET.
191ECS332L.3 Perform the operation with digital IC’s.
191ECS332L.4 Design and Implement combinational circuits.
191ECS332L.5 Design and Implement Sequential circuits.
MAPPING OF COURSE OUTCOMES WITH THE PROGRAM OBJECTIVES:

CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
191ECS332L.1 3 3 2 - 2 - - - 2 1 - -
191ECS332L.2 3 3 2 - 2 - - - 2 1 - -
191ECS332L.3 3 3 - - - - - - 2 1 - -
191ECS332L.4 3 3 2 - 2 - - - 2 1 - -
191ECS332L.5 3 3 2 - 2 - - - 2 1 - -
191ECS332L 3 3 2 - 2 - - - 2 1 - -
JUSTIFICATION OF THE MAPPING:

191ECS332L.1 Strong knowledge in component, design, construction of circuits with diodes (PO1) and
mathematics principles and engineering sciences are used (PO2). The ability to analyze
and develop solutions for engineering problems with designed and implemented circuits
(PO3), Usage of modern tools for implementation of the designed circuits for verification
(PO5). Students function as a team (PO9) and effective communication is needed to bring
out the application of circuits (PO10).
191ECS332L.2 Strong knowledge in component, design, construction of circuits of BJT, FET (PO1) and
mathematics principles and engineering sciences are used(PO2) with the ability to analyze
(PO5). Students function as a team ( PO9) and effective communication is needed to bring
out the application of circuits (PO10)
191ECS332L.3 Simplification of Boolean expression to design a combinational circuit requires a

fundamental knowledge in mathematics (PO1) and an analytical approach to digital Logic
circuits (PO2)Students function as a team ( PO9) and effective communication is needed
to bring out the application of circuits (PO10)
7
191ECS332L.4 Strong knowledge in component, design, construction of combinational circuits (PO1) and
191ECS332L.5 Strong knowledge in component, design, construction of sequential circuits (PO1) and
(PO3). Usage of modern tools for implementation of the designed circuits for verification
MAPPING OF COURSE OUTCOMES WITH THE PROGRAM SPECIFIC OUTCOMES:
CO/PSO PSO1 PSO2
191ECS332L.1 3 1
191ECS332L.2 3 1
191ECS332L.3 3 1
191ECS332L.4 3 1
191ECS332L.5 3 1
191ECS332L 3 1
JUSTIFICATION OF THE MAPPING:
Basic design of circuits with electronic components help to design (PS01) and develop
191ECS332L.1
industrial products using modern machines in the field of manufacturing (PSO2)
Design of electronic circuits help to design and develop industrial products using
191ECS332L.2 modern machines in the field of manufacturing (PS01) and good knowledge in
analyzing the performance characteristics of various devices (PSO2).
Design of digital electronic circuits help to design (PS01) and develop industrial
191ECS332L.3
products using modern machines in the field of manufacturing (PSO2)
Design of Combinational circuits help to design and develop industrial products using
191ECS332L.4
modern machines in the field of manufacturing (PS01)
Implementation of Sequential circuits help to design and develop industrial products

191ECS332L.5
using modern machines in the field of manufacturing (PS01)
8
EXPT. NO: 1
Characteristics of PN diode and clipper circuit
DATE:
Aim:
i) To study and plot the V-I characteristics of PN junction diode
ii) To obtain the waveform of clipper circuit
Apparatus Required:
S. No. COMPONENT SPECIFICATION QUANTITY

1. Diode IN 4001/4007/BY127 - 1
2. Resistors 1KΩ,100Ω Each 1
3. Regulated Power Supply (0-30)V DC 1
Ammeter (0-200)μA/(0- 1
4. 200)mA
5. Voltmeter (0-20)V DC 1
CRO (0–30)MHz 1
6.
Function Generator (1-3)MHz 1
7.
8. Bread Board, Wire cutter - 1
9. Connecting wires - As required
Theory:
A p-n junction diode conducts only in one direction. The V-I characteristics of the diode are curve
between voltage across the diode and current through the diode. When external voltage is zero, circuit is
open and the potential barrier does not allow the current to flow. Therefore, the circuit current is zero. When
P-type (Anode is connected to +ve terminal and n- type (cathode) is connected to –ve terminal of the supply
voltage, is known as forward bias. The potential barrier is reduced when diode is in the forward biased
condition. At some forward voltage, the potential barrier altogether eliminated and current starts flowing
through the diode and also in the circuit.
The diode is said to be in ON state. The current increases with increasing forward voltage. When N-
type (cathode) is connected to +ve terminal and P-type (Anode) is connected to –ve terminal of the supply
voltage is known as reverse bias and the potential barrier across the junction increases. Therefore, the
9
junction resistance becomes very high and a very small current (reverse saturation current) flows in the
circuit. The diode is said to be in OFF state. The reverse bias current due to minority charge carriers.
APPLICATIONS:
Clippers:
1. Excessive noise spikes above a certain level can be limited or clipped in FM transmitter by using
series clippers
2. For the generation of new waveforms or shaping the existing waveforms, clippers are used.
3. Used to protect the diode form transients which are connected across the inductive load.
4. In power supply kits, in Half-wave rectifiers, Clippers are used to clip either positive or negative half
wave of the input.
5. Used as amplitude selectors and voltage limiters.
Used for separation of synchronizing signals from the composite picture signals.
1N 4001 Physical View
10
CIRCUIT DIAGRAM:
PN JUNCTION DIODE -FORWARD BIAS:
PN JUNCTION DIODE -REVERSE BIAS:
PROCEDURE:
FORWARD BIAS:
i) Make the connections as per the circuit diagram.
ii) Switch on the power supply.
iii) Increase the forward voltage Vf gradually and tabulate the readings.
iv) Draw the graph for Vf vs If.
v) Find the forward resistance from forward characteristics.
REVERSE BIAS:
i) Make the connections as per the circuit diagram.
ii) Switch on the power supply.
iii) Gradually vary the reverse bias voltage and tabulate the
iv) As the reverse bias voltage reaches the breakdown voltage, the current through the diode
increases rapidly.
11
v) Draw the graph for Vr vs Ir .
V-I CHARACTERISTICS TABULATION:
S. PN Junction Diode
No. FORWARD BIAS REVERSE BIAS
Voltage V Voltage V Current I
Current I (mA)
(volts) (volts) (A)
MODEL GRAPH:
PN Junction Diode :
12
CIRCUIT DIAGRAM:
Clippers
Negative Clipper Positive Clipper
D
D1
1 2 2 1
V7 V7
V in V in
1k CRO 1k CRO
Fig.(1) Fig. (2)
PROCEDURE:
1. Construct the circuit as shown in Fig 1 and Fig.2.

2. Apply the specified AC input voltage using Function generator and observe the output voltage using
CRO.
3. Plot the input and output voltage waveforms on the graph.
TABULATION:
13
S. No. PN Junction Diode as CLIPPER
Positive Clipper Negative clipper
Amplitude (volts) Time period (ms) Amplitude (volts) Time period (ms)
INPUT
OUTPUT
MODEL GRAPH :
VIVA QUESTIONS:
1. Define depletion region of a diode?

2. What is meant by transition & space charge capacitance of a diode?
3. Is the V-I relationship of a diode Linear or Exponential?
4. Define cut-in voltage of a diode and specify the values for Si and Ge diodes?
5. What are the applications of a p-n diode?
6. Define barrier potential.
7. What is the relationship between the clipping level and the DC voltage?
8. If the variable DC source is reversed, how does this affect the clipping?
14
RESULT:
Thus, the characteristics of PN diode was obtained and studied the operation of clipper circuit.
EXPT. NO: 2
Characteristics of Zener diode and Zener voltage regulator
DATE:
Aim:
i) To study and plot the V-I characteristics of Zener diode
ii) To find the Zener Break down voltage in reverse biased condition.
Apparatus Required:

Zener Diode (IN 4735A)/Z6.8 1
1.
2. Resistors 1KΩ,10 KΩ Each 1
3. Regulated Power Supply (0-30)V DC 1
4. Ammeter (0-30)mA 1
5. Voltmeter (0-20)/(0-1)V DC 1
6. Bread Board, Wire cutter - 1
15
Theory:
A zener diode is heavily doped p-n junction diode, specially made to operate in the break down
region. A p-n junction diode normally does not conduct when reverse biased. But if the reverse bias is
increased, at a particular voltage it starts conducting heavily. This voltage is called Break down Voltage.
High current through the diode can permanently damage the device To avoid high current, we connect a
resistor in series with zener diode. Once the diode starts conducting it maintains almost constant voltage
across the terminals whatever may be the current through it, i.e., it has very low dynamic resistance. It is
used in voltage regulators.
Symbol
CIRCUIT DIAGRAM:
ZENER DIODE-FORWARD BIAS:
ZENER DIODE-REVERSE BIAS:
16
PROCEDURE:
FORWARD BIAS:
vi) Make the connections as per the circuit diagram.
vii) Switch on the power supply.
viii) Increase the forward voltage Vf gradually and tabulate the readings.
ix) Draw the graph for Vf vs If.
x) Find the forward resistance from forward characteristics.
REVERSE BIAS:
vi) Make the connections as per the circuit diagram.
vii) Switch on the power supply.
viii) Gradually vary the reverse bias voltage and tabulate the
ix) As the reverse bias voltage reaches the breakdown voltage, the current through the diode
increases rapidly.
x) Draw the graph for Vr vs Ir .
MODEL GRAPH
17
TABULATION
S. ZENER Diode
No. FORWARD BIAS REVERSE BIAS
Voltage V Voltage V Current I
Current I (mA)
(volts) (volts) (A)
VIVA QUESTIONS:
18
1. What type of temperature Coefficient does the zener diode have?
2. If the impurity concentration is increased, how the depletion width effected?
3. Does the dynamic impendence of a zener diode vary?
4. Explain briefly about avalanche and zener breakdowns?
5. Draw the zener equivalent circuit.
6. In which region zener diode can be used as a regulator?
7. How the breakdown voltage of a particular diode can be controlled?
RESULT:
Thus the characteristics of Zener diode with Zener breakdown voltage for voltage regulator was
obtained.
EXPT. NO: 3 CHARACTERISTICS OF BJT-CE configuration
19
DATE:
Aim:
To obtain the input and output characteristics of BJT in CE mode of configuration.
Apparatus Required:

Transistor BC 107 1
1.
5 KΩ 1
Resistors
2.
1 KΩ 1
RPS Dual (0-30) V 1

3.
MC (0-1) V 1
Voltmeters
4.
MC (0-30) V 1
MC (0-10mA) 1
Ammeters
5.
MC (0-250µA) 1
Theory:
A transistor is a three-terminal device. The terminals are emitter, base, collector. In common emitter
configuration, input voltage is applied between base and emitter terminals and output is taken across the
collector and emitter terminals. Therefore, the emitter terminal is common to both input and output.
The input characteristics resemble that of a forward biased diode curve. This is expected since the
Base-Emitter junction of the transistor is forward biased. As compared to CB arrangement IB increases less
rapidly with VBE. Hence input resistance of CE circuit is higher than that of CB circuit.
The output characteristics are drawn between Ic and VCE at constant IB. the collector current varies
with VCE unto few volts only. After this the collector current becomes almost constant, and independent of
VCE. The value of VCE up to which the collector current changes with V CE is known as Knee voltage. The
transistor always operated in the region above Knee voltage, IC is always constant and is approximately
equal to IB. The current amplification factor of CE configuration is given by β = ΔIC/ΔIB
20
CIRCUIT
DIAGRAM
PROCEDURE :
INPUT CHARACTERISTICS:
1. Connections are made as per the circuit diagram.

2. VCE is kept constant (say 5V), VBE is varied insteps of 0.1V and the corresponding IB values are tabulated.
The above procedure is repeated for different constant values.
3. Graph is plotted between VBE and IB for a constant VCE.
OUTPUT CHARACTERISTICS:
2. IB is kept constant, VCE is varied in step of 1V the corresponding IC values are tabulated. The above
procedure is repeated for different constant values.
3. Graph is plotted between VCE and IC for a constant IB.
MODEL GRAPH:
INPUT CHARACTERISTICS OUTPUT CHARACTERISTICS
21
TABULATION:
INPUT CHARATERISTICS
VCE =_____V VCE = ____V
VBE (V) IB (A) VBE (V) IB (A)
OUTPUT CHARACTERISTICS
IB = ____ A IB = ____A IB = ___A
VCE (V) IC (mA) VCE (V) IC (mA) VCE (V) IC (mA)
22
VIVA QUESTIONS:
1. NPN transistors are more preferable for amplification purpose than PNP transistors. Why?
2. At what region of the output characteristics, a transistor can act as an amplifier?
3. What happens when we change the biasing condition of the transistors?
4. Why the output is phase shifted by 180◦ only in CE configuration?
5. What effect does temperature have on current gain?
6. Mention the applications of CE amplifier.
RESULT:
Thus the input and output characteristics are obtained and graph is plotted for the BJT in CE mode of
configuration.
23
EXPT. NO: 4
CHARACTERISTICS OF JFET
DATE:
Aim:
To plot the drain and transfer characteristics of JFET and also to find the drain resistance, trans-
conductance, pinch off voltage and IDSS for the given JFET.
Apparatus Required:

FET BFW10 1
1.
Resistors 1KΩ 2
2.
Regulated dual power supply MC (0-30) V 1
3.
Voltmeters MC (0-30V) and MC (0-10V) Each 1
4.
Ammeters MC (0-30) mA 1
5.
THEORY:
The features of FET and its advantages over conventional transistor.

1. In a conventional transistor, the operation depends upon the flow of majority and minority carriers. That
is why it is called bipolar transistor. In FET the operation depends upon the flow of majority carriers
only. It is called unipolar device.
2. The input to conventional transistor amplifier involves a forward biased PN junction with its inherently
low dynamic impedance. The input to FET involves a reverse biased PN junction hence the high input
impedance of the order of M-ohm.
3. It is less noisy than a bipolar transistor.
4. It exhibits no offset voltage at zero drain current.
5. It has thermal stability.
6. It is relatively immune to radiation.
7. The main disadvantage is its relatively small gain bandwidth product in comparison with conventional
transistor.
PIN DIAGRAM:
24
CIRCUIT DIAGRAM:
PROCEDURE:
DRAIN CHARACTERISTICS

2. Gate –source voltage VGS is kept constant (say –1V), drain voltage VDS is varied insteps of 1V
and the corresponding drain current ID values are tabulated.
3. The above procedure is repeated for VGS= -2V, 0V.
4. The graph is plotted VDS and ID for a constant VGS.
5. The drain resistance is found from the graph rd = VDS/ ID.
TRANSFER CHARACTERISTICS:

2. Drain –source voltage VDS is kept constant (say 5V), the gate – source voltage VGS is varied
insteps of 1V (-VE voltage) and the corresponding drain current ID values are tabulated.
3. The above procedure is repeated for VDS = 10V, 15V,
4. Graph is plotted between VGS and ID for a constant VDS.
5. The transconductance is found from the graph gm =  ID/ VGS.
MODEL GRAPH:
Transfer Characteristics Drain Characteristics
25
TABULATION:
Drain Characteristics Transfer Characteristics
VGS = ____V VGS = ___V VGS = ____V VDS=_____ V
VGS (V) ID (mA)

VDS ID VDS ID VDS ID
(V) (mA) (V) (mA) (V) (mA)
FORMULA USED:
Amplification factor = gm rd
CALCULATIONS:
Calculation of rd:
Construct a Triangle on one of the O/P Characteristic for a particular VGS in the active region and Find ∆VDS
and ∆ID Now, rd = ∆VDS /∆ID (VGS =Constant)
Calculation of gm:
Construct a Triangle on one of the transfer characteristics for a particular VDS find ∆VGS and ∆ID
Now, gm= ∆ID/ ∆VGS (VDS = Constant)
26
VIVA QUESTIONS:
1. How can you tell whether an FET is operating in the ohmic region or the active region?
2. FET is a voltage-controlled device. Justify?
3. What is Tran conductance?
4. Why current gain is important parameter in BJT whereas conductance is important parameter in
FET?
5. How can avalanche breakdown be avoided in FET?
6. Why does FET produce less electrical noise than BJT?
7. How can the JFET be used as a static electricity switch?
RESULT:
Thus the drain and transfer characteristics of the given JFET are drawn, the following parameters are
calculated.
1. Drain Resistance = ____________ Ω

2. Transconductance = ____________mho
3. Amplification factor () = ______________
4. Pinch off voltage = _____________V
5. IDSS = ______________mA
27
EXPT. NO: 5
APPLICATION OF BJT- SWITCH
DATE:
Aim:
To observe the action of a Transistor as an electronic switch and to measure the voltage across the
transistor when it is ON and when it is OFF.
Apparatus Required:

Regulated D.C Power 0–30 Volts 1
1.
Transistor BC – 107 1
2.
Resistors 4.7K Ω, 2.2K Ω Each 1
3.
LED CQY24 1
4.
5. Bread Board and connecting wires - 1 Set
THEORY:
Bipolar junction transistors (also known as BJTs) can be used as an amplifier, filter, rectifier,
oscillator, or even a switch. The transistor will operate as an amplifier or other linear circuit if the transistor
is biased into the linear region. The transistor can be used as a switch if biased in the saturation and cut-off
regions. This allows current to flow (or not) in other parts of a circuit.
Because a transistor’s collector current is proportionally limited by its base current, it can be used as
a sort of current-controlled switch. A relatively small flow of electrons sent through the base of the
transistor has the ability to exert control over a much larger flow of electrons through the collector.
Transistors may be used as switching elements to control DC power to a load. The switched
(controlled) current goes between emitter and collector; the controlling current goes between emitter and
base. When a transistor has zero current through it, it is said to be in a state of cutoff (fully non conducting).
When a transistor has maximum current through it, it is said to be in a state of saturation (fully conducting).
28
CIRCUIT DIAGRAM
PROCEDURE:
1. Construct the circuit as shown in figure.

2. Connect ‘0’ volts to the input terminals.
3. Measure the voltage across collector to emitter(VCE), collector to base(VCB) and base to
emitter(VBE).
4. Connect ‘5’ volts to the input terminals. Measure the voltage across collector to
emitter(VCE), collector to base(VCB) and base to emitter(VBE).
5. Observe that the LED glows when the input terminals are supplied with ‘0’ volts. and the
LED will not glow when the input is ‘5’ volts.
TABULATION:
Input voltage (V)

VCE (V) VCB (V) VBE (V) Mode of LED
0V
5V
29
VIVA QUESTIONS:
1. In which region of the characteristics transistor acts as a switch?

2. What is the typical value of the collector current on ON state?
3. How the junctions of Transistor are biased in ON state and OFF state?
4. State biasing modes for amplifier applications.
RESULT:
Thus the action of transistor as a switch is observed and.
30
CYCLE II
DIGITAL CIRCUITS EXPERIMENTS
31
EXPT. NO: 6
STUDY OF BASIC IC’s – LOGIC GATES
DATE:
Aim:
To study about logic gates and verify their truth tables using the specified logic gate IC’s.
Apparatus Required:

1. NAND GATE IC 7400 1
2. NOR GATE IC 7402 1
3. NOT GATE IC 7404 1
4. AND GATE IC 7408 1
5. OR GATE IC 7432 1
6. EX-OR GATE IC 7486 1
7. IC TRAINER KIT - 1
8. CONNECTING WIRES - few
Theory:
Logic gates are the basic elements that make up a digital system. A logic gate is a used to perform a
logical operation on one or more logic inputs and produces a single logic output. By connecting the different
gates in different ways, we can build circuits that perform arithmetic and other functions. The operation of a
logic gate can be easily understood with the help of “truth table”. A truth table is a table that shows all the
input-output possibilities of a logic circuit i.e., the truth table indicates the outputs for different possibilities
of the inputs.
AND Gate: The AND gate performs a logical multiplication commonly known as AND function. The
output is HIGH (1), when both the inputs are 1; otherwise the output from the gate is LOW (0). The output
from the AND gate is written as A.B.
OR Gate: The OR gate performs a logical addition commonly known as OR function. The output is
HIGH (1), if any of the inputs are 1; the output is LOW (0) if and only if all the inputs are 0. The output
from the AND gate is written as A+B.
NAND Gate: The NAND gate is a contraction of AND-NOT. It has two or more inputs. The output is
HIGH (1), when any of the inputs are 0; the output is LOW (0), if and only if all the inputs are 1. The output
from the AND gate is written as (A.B)’. It is a universal gate.
NOR Gate: The NOR gate is a contraction of OR-NOT. It has two or more inputs. The output is HIGH (1),
when all inputs are 0; the output is LOW (0), when any of the inputs are 1. The output from the AND gate is
written as (A+B)’. It is a universal gate.
NOT Gate: The NOT gate has only one input. It performs a basic logic function called inversion. The
output is HIGH (1), when the input is 0; the output is LOW (0) when the input is 1. The output from the
NOT gate is written as A’.
EX-OR Gate: The EX-OR gate has two or more inputs. The output is HIGH(1) when odd number of input
is 1. The output from the AND gate is written as (A B).
32
AND Gate:
OR GATE:
33
NAND GATE:
NOR GATE:
34
NOT GATE:
EX-OR GATE:
Procedure:
1. Place the ICs on IC trainer kit
2. Connect the Vcc and ground to respective pins of IC trainer kit
3. Connections are given as per the designed logic diagram.
4. Connect the inputs to the input switches provided in the IC trainer kit
5. Connect the outputs to the pins output LED’s
6. Apply various combinations of input according to the truth table
7. Observe the condition of output LED’s and verify the truth table
35
VERIFICATION OF LOGIC GATES :
36
Viva Questions:
1. What is meant by propagation delay?
2. What are the applications of Logic Gates?
3. Apply De-Morgan’s theorem to [(A+B) +C]’
4. Which gates are called as universal gates? What are its advantages?
5. Implement OR gate using NAND gate.
Result:
Thus studied about logic gates and verified their truth tables using the specified logic gate IC’s.
37
EXPT. NO: 7 IMPLEMENTATION OF HALF/FULL ADDER & HALF/FULL
DATE: SUBTRACTOR
Aim:
To design and implement Half Adder, Full Adder, Half subtractor and full subtractor using basic
gates.
Apparatus Required:
S. No. COMPONENTS SPECIFICATION QUANTITY
1. AND GATE IC 7408 2
6. CONNECTING WIRES - As Required
Theory:
An adder is a digital logic circuit in electronics that implements addition of numbers. In many
computers and other types of processors, adders are used to calculate addresses, similar operations and table
indices in the ALU and also in other parts of the processors. These can be built for many numerical
representations like excess-3 or binary coded decimal. Adders are classified into two types: half adder and
full adder.
Half Adder:
The half adder adds two binary digits called as augend and addend and produces two outputs as sum
and carry; XOR is applied to both inputs to produce sum and AND gate is applied to both inputs to produce
carry. The full adder adds 3 one bit numbers, where two can be referred to as operands and one can be
referred to as bit carried in. And produces 2-bit output, and these can be referred to as output carry and sum.
Full Adder:
Full adder is difficult to implement than a half-adder. The difference between a half-adder and a full-
adder is that the full-adder has three inputs and two outputs, whereas half adder has only two inputs and two
outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The full adder circuit
has three inputs and generate a carry and sum. When a full-adder logic is designed, you string eight of them
together to create a byte-wide adder and cascade the carry bit from one adder to the next.
38
Half Adder:
Logic Diagram: Truth Table:
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Full Adder:
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
PROCEDURE:
1. Place the IC on IC trainer kit
3. Connections are given as per logic diagram
5. Connect the outputs to the switches of output LED’s
39
Half Subtractor:
The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has
two inputs, the minuend (A) and subtrahend (B) and two outputs the difference (D) and borrow (B0). The
borrow signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction.
That is, B=1 when A<B.
Full Subtractor:
A full subtractor is a combinational circuit that performs subtraction of two bits, one is minuend and
other is subtrahend, taking into account borrow of the previous adjacent lower minuend bit. This circuit has
three inputs and two outputs. The three inputs A, B and Bin, denote the minuend, subtrahend, and previous
borrow, respectively. The two outputs, D and Bout represent the difference and output borrow, respectively.
Half Subtractor:
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Full Subtractor:
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
40
Viva Questions:
1. Implement a full adder with two half adders and an OR gate.
2. Write the design procedure of combinational circuit.
3. Enumerate some of the combinational circuits.
4. Write the logic expressions for the sum and carry output of a full adder.
RESULT:
Thus Half Adder, Full Adder, Half subtractor and Full subtractor are designed and implemented
using basic gates.
41
EXPT. NO: 8
DESIGN OF CODE CONVERTERS
DATE:
Aim:
To design and implement 4-bit
1. Binary to gray code converter
2. Gray to binary code converter
Apparatus Required:
S. No. COMPONENTS SPECIFICATION QUANTITY
3. CONNECTING WIRES - As Required
Theory:
A code converter is a circuit that makes the two systems compatible even though each uses a
different binary code. To convert from one binary code A to binary code B, the input lines must provide the
bit combination of elements as specified by A+ and the output lines must generate the corresponding bit
combinations of code B. A combinational circuit consisting of logic gates performs this transformation
operation.
BINARY TO GRAY CODE CONVERTER:
Gray code is a non-weighted code. Gray code belongs to a class of code known as minimum change
code, in which a number changes by only one bit as it proceeds from one number to the next. Hence this
code is not useful for arithmetic operations. This code finds extensive use for shaft encoders, in some types
of analog-to-digital converters, etc.
The input variable are designated as B3, B2, B1, B0 and the output variables are designated as G3,
G2, G1, Go. From the truth table, combinational circuit is designed. The Boolean functions are obtained
from K-Map for each output variable. Any binary number can be converted into equivalent Gray code by
the following steps:
1. The MSB of the Gray code is the same as the MSB of the binary number;
2. The second bit next to the MSB of the Gray code equals the Ex-OR of the MSB and second bit of
binary number; it will be 0 if there are same binary bits or it will be 1 for different binary bits;
3. The third bit for Gray code equals the exclusive-OR of the second and third bits of the binary
number, and similarly all the next lower order bits follow the same mechanism.
42
Truth Table:
BINARY CODE GRAY CODE

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Logic Diagram:
GRAY TO BINARY CODE CONVERTER:

To convert from gray code to binary code, the input lines must supply the bit combination of
elements as specified by code and the output lines generate the corresponding bit combination of code. Each
one of the four maps represents one of the four outputs of the circuit as a function of the four input
variables.
A two-level logic diagram may be obtained directly from the Boolean expressions derived by the
maps. These are various other possibilities for a logic diagram that implements this circuit. Any Gray code
can be converted into an equivalent binary number by the following steps:
1. The MSB of the binary number is the same as the MSB of the Gray code;
43
2. The second bit next to the MSB of the binary number equals the Ex-OR of the MSB of the binary
number and second bit of the Gray code; it will be 0 if there are same binary bits or it will be 1 for
different binary bits;
3. The third bit for the binary number equals the exclusive-OR of the second bit of the binary number
and third bit of the Gray code, and similarly all the next lower order bits follow the same
mechanism.
Truth Table:
GRAY CODE BINARY CODE

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
Logic Diagram:
44
Procedure:
Viva Questions:
1. What is a code converter?
2. What is the difference between binary code and BCD code?
3. Distinguish between weighted code and non-weighted code.
4. Explain the uses of Excess-3 code.
5. What is gray code?
Result:
Thus designed and implemented 4-bit, Binary to gray code converter and Gray to binary code
converter.
45
EXPT. NO: 9
STUDY OF MULTIPLEXER AND DEMULTIPLEXER
DATE:
Aim:
To design and implement multiplexer and demultiplexer using logic gates.
Apparatus Required:
SPECIFICATIO
S. NO. COMPONENTS QUANTITY
N
2. 3-INPUT AND GATE IC 7411 2
Theory:
Multiplexer:
A digital multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is controlled by a set
of selection lines. Normally there are 2n input line and n selection lines whose bit combination determine
which input is selected.
4:1 Multiplexer:
Block Diagram:
46
Demultiplexer:
The function of Demultiplexer is in contrast to multiplexer function. It takes information from one
line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a
data distributor. Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select
lines enable only one gate at a time and the data on the data input line will pass through the selected gate to
the associated data output line.
1: 4 Demultiplexer:
Block Diagram:
4:1 MULTIPLEXER:
LOGIC DIAGRAM:
Output, Y= D0 S1’S0’ +D1 S1’S0+ D2 S1S0’ +D3 S1S0
47
TRUTH TABLE:
S1 S0 OUTPUT (Y)
0 0 D0
0 1 D1
1 0 D2
1 1 D3
1: 4 DEMULTIPLEXER:
LOGIC DIAGRAM:
TRUTH TABLE:
INPUTS OUTPUTS
S1 S0 INPUT D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
48
PROCEDURE:
Viva Questions:
1. What is a multiplexer?
2. Implement the following with a multiplexer
F(A, B, C) = ∑m (1, 2, 4, 5)
3. Mention any two applications of multiplexers
4. Write down the differences between de-multiplexer and decoder .
5. Write the logic equation and draw the internal logic diagram for a 2 to 1 multiplexer
Result:
Thus designed and implemented the multiplexer and demultiplexer using logic gates.
49
EXPT. NO: 10
DESIGN AND IMPLEMENTATION Of COUNTERS AND SHIFT REGISTERS
DATE:
Aim:
To design and verify 4 bit asynchronous counter and SISO register.
Apparatus Required:
S. NO. COMPONENTS SPECIFICATION QUANTITY

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. D-FLIP FLOP IC 7474 2
Theory
4-Bit Asynchronous Counter:
A ripple counter also called an asynchronous counter or a serial counter is a cascaded arrangement of
flip-flops where the output of one flip-flop drives the clock input of the following flip-flop. In a ripple
counter the clock input is applied only to the first flip-flop, also called the input flip-flop, in the cascaded
arrangement. The clock input to any subsequent flip-flop comes from the output of its immediately
preceding flip-flop. For instance, the output of the first flip-flop acts as the clock input to the second flip-
flop, the output of the second flip-flop feeds the clock input of the third flip-flop and so on.
A four-bit ripple counter is implemented with negative edge-triggered J-K flip-flops wired as toggle
flip-flops. The output of the first flip-flop feeds the clock input of the second, and the output of the second
flip-flop feeds the clock input of the third, the output of which in turn feeds the clock input of the fourth
flip-flop. The outputs of the four flip-flops are designated as Q0 (LSB flip-flop), Q1, Q2 and Q3 (MSB flip-
flop).
SERIAL IN SERIAL OUT (SISO):
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input which determines what enters the left hand flip-flop, the serial output which is
taken from the output of the right hand flip-flop and the sequencing clock signal (Clk). Well this type of
Shift Register also acts as a temporary storage device or as a time delay device for the data, with the amount
of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying the
application of the clock pulses.
50
PIN DIAGRAM (D-FLIP-FLOP):
SERIAL IN SERIAL OUT:

LOGIC DIAGRAM:
TRUTH TABLE:
CLK SERIAL IN SERIAL OUT
51
Logic Diagram (4-Bit Ripple Counter):
Truth Table:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1
Procedure:
52
Viva Questions
1. How synchronous counter differ from asynchronous counters ?
2. What is a Ring counter?
3. Define registers?
4. What is shift registers? List its types?
5. What are the applications of shift registers?
Result:
Thus designed and implemented the 4bit asynchronous counter and SISO shift registers using logic
gates.
53
EXPT. NO: 11
DESIGN of RC PHASE SHIFT OSCILLATOR
DATE:
Aim:
To construct RC Phase shift oscillator and obtain its waveform.
Apparatus Required:
S. NO. COMPONENTS SPECIFICATION QUANTITY

1. Transistor BC 107 1
2. Resistor 10k ohm, 1 Kohm 3 each
3. Capacitor 0.1 micro Farad 5
4. CRO ( 0 – 30 ) MHz 1
5. RPS (0-30) V 1
Function
6. (0-1 )MHz 1
Generator
Theory:
The Transistor Phase Shift Oscillator produces a sine wave of desired designed frequency. The RC
combination will give a 60degree phase shift totally three combination will give a 180 degree phase shift..
The BC107 is in the common emitter configuration. Therefore that will give a 180 degree phase shift totally
a 360 degree phase shift output is produced. The capacitor value is designed in order to get the desired
output frequency. Initially the C and R are connected as a feedback with respect to input and output and this
will maintain constant sine wave output. CRO is connected at the output.
CIRCUIT DIAGRAM:
54
MODEL GRAPH
Observation:
Amplitude =
Time period t =
Frequency fp = 1/T =
Theoretical frequency, fT =
Practical frequency, fP =
Viva Ques:
1.Define oscillator.
2. What is the frequency of oscillation?
3. State Barkhausen criterion.
RESULT:
Thus, the RC Phase shift oscillator is constructed and output waveform is obtained.
55

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EASWARI ENGINEERING COLLEGE

(An Autonomous institution)

DEPARTMENT OF ROBOTICS AND AUTOMATION ENGINEERING

LAB NAME : ELECTRONIC CIRCUITS AND DIGITAL LABORATORY

LAB CODE : 191ECS332L

S.R.SRIRAM, AP/ECE HOD /ECE

Course Code Course Title Periods per week

1. Characteristics of PN diode and clipper circuit

1. Study of Basic Digital IC’s.

EXPERIMENT BEYOND SYLLABUS

1. Design of RC Phase shift Oscillator

EXPT. PAGE STAFF

Characteristics of PN diode and clipper

Characteristics of Zener diode and Zener

3. Characteristics of BJT – CE configuration

Application of BJT as an amplifier and

6. Study of Basic Digital IC’s.

Implementation of Adder and subtractor

8. Design of Code converters.

9. Study of Multiplexer and Demultiplexer.

Design and implementation of counters and

EXPERIMENT BEYOND SYLLABUS

11. Design of RC Phase shift Oscillator

Subject Code : 191ECS332L Total no. of hours given in syllabus

EXPERIMENT BEYOND SYLLABUS

Engineering Graduates will be able to:

Engineering knowledge: Apply the knowledge of mathematics, science, engineering

PROGRAM SPECIFIC OUTCOMES:

191ECS332L.2 Obtain the characteristics of BJT, JFET.

191ECS332L.3 Perform the operation with digital IC’s.

191ECS332L.4 Design and Implement combinational circuits.

191ECS332L.5 Design and Implement Sequential circuits.

MAPPING OF COURSE OUTCOMES WITH THE PROGRAM OBJECTIVES:

JUSTIFICATION OF THE MAPPING:

191ECS332L.3 Simplification of Boolean expression to design a combinational circuit requires a

MAPPING OF COURSE OUTCOMES WITH THE PROGRAM SPECIFIC OUTCOMES:

CO/PSO PSO1 PSO2

JUSTIFICATION OF THE MAPPING:

Implementation of Sequential circuits help to design and develop industrial products

S. No. COMPONENT SPECIFICATION QUANTITY

2. Resistors 1KΩ,100Ω Each 1

3. Regulated Power Supply (0-30)V DC 1

8. Bread Board, Wire cutter - 1

9. Connecting wires - As required

1N 4001 Physical View

PN JUNCTION DIODE -FORWARD BIAS:

PN JUNCTION DIODE -REVERSE BIAS:

V-I CHARACTERISTICS TABULATION:

Negative Clipper Positive Clipper

Fig.(1) Fig. (2)

1. Construct the circuit as shown in Fig 1 and Fig.2.

1. Define depletion region of a diode?

S. No. COMPONENT SPECIFICATION QUANTITY

2. Resistors 1KΩ,10 KΩ Each 1

3. Regulated Power Supply (0-30)V DC 1

6. Bread Board, Wire cutter - 1

7. Connecting wires - As required

ZENER DIODE-REVERSE BIAS:

S. No. COMPONENT SPECIFICATION QUANTITY

VCE =_V VCE = V

IB = __ A IB = A IB = _A

VGS = __V VGS = _V VGS = V VDS=_ V