ST6252C ST6262B

ST6262C
8-bit MCUs with A/D converter,
safe reset, auto-reload timer and EEPROM

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Features
■ 3.0 to 6.0 V supply operating range
■ 8 MHz maximum clock frequency

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■ -40 to +125°C operating temperature range
■

■
Run, Wait and Stop Modes
5 Interrupt vectors
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■

■
Look-up table capability in Program Memory
Data storage in Program Memory:
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■
User selectable size
Data RAM: 128 bytes
PDIP16

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■

■
Data EEPROM: 64 bytes (not in ST6252C devices)
User programmable options
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■ 9 I/O pins, fully programmable as:
– Input with pull-up resistor
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– Input without pull-up resistor
– Input with interrupt generation
) - PSO16
– Open-drain or push-pull output
– Analog Input

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■ 5 I/O lines can sink up to 30 mA to drive LEDs or
TRIACs directly
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■ 8-bit Timer / Counter with 7-bit programmable
prescaler
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■
prescaler (AR Timer)
Digital watchdog P r
8-bit Auto-reload Timer with 7-bit programmable

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■

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Oscillator Safe Guard (not in ST6262B devices)
Low Voltage Detector for safe Reset (not in

■
ST6262B devices)

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8-bit A/D converter with 4 analog inputs
■

■
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On-chip Clock oscillator can be driven by quartz
crystal ceramic resonator or RC network
User configurable Power-on Reset
CDIP16W
(See end of Datasheet for Ordering Information)

■ One external Non-Maskable Interrupt

■ ST626x-EMU2 emulation and development
system (connects to an MS-DOS PC via a Table 1. Device summary
parallel port)
Program memory EEPROM
DEVICE
(Bytes) (Bytes)

ST6252C 1836 -
ST6262C 1836 64
ST6262B 1836 64

March 2009 Rev. 4 1/75

 Table of Contents Document
Page
ST6252C ST6262B
ST6262C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

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1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 16
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 RESETS (CONT’D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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3.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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3.6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

) -
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.4
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4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.1 OTP/EPROM VERSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.2 FASTROM VERSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.3 ROM VERSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
. . . . 71
9 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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 ST6252C ST6262B ST6262C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST6252C and ST6262C devices are low cost fined in the programmable option byte of the
members of the ST62xx 8-bit HCMOS family of mi- OTP/EPROM versions.
crocontrollers, which is targeted at low to medium
complexity applications. All ST62xx devices are
based on a building block approach: a common
OTP devices offer all the advantages of user pro-
grammability at low cost, which make them the
s )
core is surrounded by a number of on-chip periph-
erals.
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
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The ST62E62C is the erasable EPROM version of
the ST62T62C device, which may be used to em- These compact low-cost devices feature a Timer
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ulate the ST62T52C and ST62T62C devices as
well as the ST6252C and ST6262B ROM devices.
comprising an 8-bit counter and a 7-bit program-
mable prescaler, an 8-bit Auto-Reload Timer,
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OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
EEPROM data capability (except ST6252C), an 8-
bit A/D Converter with 4 analog inputs and a Digit-

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al Watchdog timer, making them well suited for a P
tionality selecting as ROM options the options de-
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wide range of automotive, appliance and industrial
applications.
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Figure 1. Block Diagram

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b
-O
8-BIT
PORT A PA4..PA5 / Ain
A/D CONVERTER
TEST/VPP

(s)
TEST
PB0, PB2..PB3 / 30 mA Sink
PORT B PB6 / ARTimin / 20 mA Sink

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PB7 / ARTimout / 20 mA Sink
NMI INTERRUPT
DATA ROM

PROGRAM
USER
SELECTABLE

u c PORT C PC2..PC3 / Ain

MEMORY
DATA RAM

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r
AUTORELOAD
1836 bytes OTP 128 Bytes
(ST62T52C, T62C) TIMER
1836 bytes EPROM
(ST62E62C)

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DATA EEPROM

t 64 Bytes TIMER

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(ST62T62C/E62C)

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bs
PC

STACK LEVEL 1

O STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
8 BIT CORE
DIGITAL
WATCHDOG

STACK LEVEL 5
STACK LEVEL 6

POWER OSCILLATOR RESET

SUPPLY

VDD VSS OSCin OSCout RESET

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ST6252C ST6262B ST6262C

1.2 PIN DESCRIPTIONS

VDD and VSS. Power is supplied to the MCU via Mout are either Port B I/O bits or the Input and
these two pins. VDD is the power connection and Output pins of the ARTimer.
VSS is the ground connection. Reset state of PB2-PB3 pins can be defined by op-
tion either with pull-up or high impedance.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz PB0, PB2-PB3, PB6-PB7 scan also sink 30mA for
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
direct LED driving.

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The OSCin pin is the input pin, the OSCout pin is PC2-PC3. These 2 lines are organized as one I/O
port (C). Each line may be configured under soft-

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the output pin.
ware control as input with or without internal pull-
RESET. The active-low RESET pin is used to re-
start the microcontroller.
up resistor, interrupt generating input with pull-up
resistor, analog input for the A/D converter, open-
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TEST/VPP. The TEST must be held at VSS for nor-
mal operation. If TEST pin is connected to a
drain or push-pull output.

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Figure 2. ST62T52C, E62C and T62C Pin
+12.5V level during the reset phase, the
Configuration

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EPROM/OTP programming Mode is entered.
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non PB0 1 16
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PC2/Ain

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maskable interrupt to the MCU. The NMI input is
falling edge sensitive. It is provided with an on-chip VPP/TEST 2 15 PC3/Ain

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pullup resistor (if option has been enabled), and
Schmitt trigger characteristics. PB2 3 14 NMI

PA4-PA5. These 2 lines are organized as one I/O PB3 4 13 RESET

)-
port (A). Each line may be configured under soft-
ware control as inputs with or without internal pull- ARTIMin/PB6 5 12 OSCout
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs, ana-
t ( s
ARTIMout/PB7 6 11 OSCin

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log inputs for the A/D converter. VDD
7 PA5/Ain
10

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PB0, PB2-PB3, PB6-PB7. These 5 lines are or- VSS 8 9 PA4/Ain
ganized as one I/O port (B). Each line may be con-

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figured under software control as inputs with or
without internal pull-up resistors, interrupt generat-

P
ing inputs with pull-up resistors, open-drain or
push-pull outputs. PB6/ARTIMin and PB7/ARTI-

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 ST6252C ST6262B ST6262C

1.3 MEMORY MAP

1.3.1 Introduction Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
The MCU operates in three separate memory tains user data in RAM and in OTP, and Stack
spaces: Program space, Data space, and Stack space accommodates six levels of stack for sub-
space. Operation in these three memory spaces is routine and interrupt service routine nesting.
described in the following paragraphs.
Figure 3. Memory Addressing Diagram
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PROGRAM SPACE DATA SPACE

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0000h
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000h

RAM / EEPROM
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BANKING AREA

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0-63 03Fh
040h

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-
DATA READ-ONLY
MEMORY WINDOW

)
PROGRAM
MEMORY

t ( s07Fh
080h X REGISTER

c
081h Y REGISTER
082h

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V REGISTER
083h

d
W REGISTER
084h

o RAM

Pr 0C0h DATA READ-ONLY

MEMORY
0FF0h

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WINDOW SELECT
INTERRUPT &

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BANK SELECT

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RESET VECTORS
0FFFh 0FFh ACCUMULATOR

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O

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ST6252C ST6262B ST6262C

MEMORY MAP (Cont’d)

1.3.2 Program Space
Program Space comprises the instructions to be Figure 4. ST62T52C/T62C Program
executed, the data required for immediate ad- Memory Map
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is 0000h

)
addressed via the 12-bit Program Counter register
(PC register).
1.3.2.1 Program Memory Protection
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The Program Memory in OTP or EPROM devices
can be protected against external readout of mem-
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d
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
In the EPROM parts, READOUT PROTECTION
RESERVED*

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option can be disactivated only by U.V. erasure
that also results into the whole EPROM context

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erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned 087Fh
o le
parts with a protection set can therefore not be ac-
cepted.
0880h

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- O USER
PROGRAM MEMORY

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1836 BYTES
(OTP/EPROM)

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d 0F9Fh

ro
0FA0h
0FEFh
RESERVED*

e P 0FF0h
0FF7h
0FF8h
INTERRUPT VECTORS

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RESERVED
0FFBh

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0FFDh
0FFEh
NMI VECTOR
USER RESET VECTOR

b s 0FFFh

(*) Reserved areas should be filled with 0FFh

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 ST6252C ST6262B ST6262C

MEMORY MAP (Cont’d)

1.3.3 Data Space Table 2. ST62T52C, T62C and ST62E62C Data
Memory Space
Data Space accommodates all the data necessary
for processing the user program. This space com- 000h
RAM / EEPROM banks
prises the RAM resource, the processor core and 03Fh
peripheral registers, as well as read-only data 040h

)
such as constants and look-up tables in DATA ROM WINDOW AREA
OTP/EPROM.
1.3.3.1 Data ROM X REGISTER
07Fh
080h

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All read-only data is physically stored in program
memory, which also accommodates the Program
Y REGISTER
V REGISTER
W REGISTER
081h
082h
083h
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Space. The program memory consequently con-
tains the program code to be executed, as well as DATA RAM 60 BYTES
084h
0BFh
od
the constants and look-up tables required by the
application.
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
0C0h
0C1h
0C2h
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The Data Space locations in which the different

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RESERVED 0C3h
constants and look-up tables are addressed by the
PORT A DIRECTION REGISTER 0C4h

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processor core may be thought of as a 64-byte
PORT B DIRECTION REGISTER 0C5h
window through which it is possible to access the
read-only data stored in OTP/EPROM.
1.3.3.2 Data RAM/EEPROM
PORT C DIRECTION REGISTER
RESERVED

s o 0C6h
0C7h

b
INTERRUPT OPTION REGISTER 0C8h*
In ST62T52C, T62C and ST62E62C devices, the DATA ROM WINDOW REGISTER 0C9h*
data space includes 60 bytes of RAM, the accu-
mulator (A), the indirect registers (X), (Y), the short
direct registers (V), (W), the I/O port registers, the O
RESERVED

-
PORT A OPTION REGISTER
0CAh
0CBh
0CCh
peripheral data and control registers, the interrupt
option register and the Data ROM Window register
( s )
PORT B OPTION REGISTER
PORT C OPTION REGISTER
0CDh
0CEh
(DRW register).
Additional RAM and EEPROM pages can also be
c t RESERVED
A/D DATA REGISTER
0CFh
0D0h

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A/D CONTROL REGISTER 0D1h
addressed using banks of 64 bytes located be- TIMER PRESCALER REGISTER 0D2h
tween addresses 00h and 3Fh.

o d TIMER COUNTER REGISTER

TIMER STATUS CONTROL REGISTER
0D3h
0D4h
1.3.4 Stack Space

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Stack space consists of six 12-bit registers which
AR TIMER MODE CONTROL REGISTER
AR TIMER STATUS/CONTROL REGISTER1
AR TIMER STATUS/CONTROL REGISTER2
0D5h
0D6h
0D7h

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are used to stack subroutine and interrupt return

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WATCHDOG REGISTER 0D8h
addresses, as well as the current program counter AR TIMER RELOAD/CAPTURE REGISTER 0D9h
contents.

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Table 1. Additional RAM / EEPROM Banks
AR TIMER COMPARE REGISTER
AR TIMER LOAD REGISTER
0DAh
0DBh

bs
0DCh
Device RAM EEPROM 0DDh
RESERVED
ST62T52C 1 x 64 bytes - 0DEh

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ST62T62C 1 x 64 bytes 1 x 64 bytes DATA RAM/EEPROM REGISTER
RESERVED
EEPROM CONTROL REGISTER
0E7h
0E8h*
0E9h
0EAh
0EBh
RESERVED
0FEh
ACCUMULATOR 0FFh
* WRITE ONLY REGISTER

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ST6252C ST6262B ST6262C

MEMORY MAP (Cont’d)

1.3.5 Data Window Register (DWR) Data Window Register (DWR)
The Data read-only memory window is located from Address: 0C9h — Write Only
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat- 7 0
ed anywhere in program memory, between ad-
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

)
dress 0000h and 0FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window Bits 6, 7 = Not used.
t( s
can be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the Bit 5-0 = DWR5-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
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Data Window Register (DWR).
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
od
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The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operations. This register is used to position the
Caution: This register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
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64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
le
Note: Care is required when handling the DWR t
register as it is write only. For this reason, the
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
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DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service

b
bits of the register address given in the instruction routine cannot save and then restore the register’s
(as least significant bits) and the content of the previous contents. If it is impossible to avoid writ-
DWR register (as most significant bits), as illustrat-
ed in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space, with 0 load-
- O
ing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
ed in the DWR register, the physical location ad-
dressed in program memory is 00h. The DWR reg-
s )
location, and each time the program writes to the
DWR, it must also write to the image register. The

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image register must be written first so that, if an in-
ister is not cleared on reset, therefore it must be
written to prior to the first access to the Data read-
c t
terrupt occurs between the two instructions, the
DWR is not affected.
only memory window area.

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Figure 5. Data read-only memory Window Memory Addressing

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DATA ROM 13 12
WINDOW REGISTER 7 6 5

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11 10 9

4 3
8

2
7

1
6

0
5 4 3 2 1 0 PROGRAM SPACE ADDRESS
READ

let
CONTENTS
5 4 3 2 1 0 DATA SPACE ADDRESS
(DWR) :
0 1 40h-7Fh

s o IN INSTRUCTION

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Example:

DWR=28h 1 0 1 0 0
0
0
1 0 1 1 0 0 1
DATA SPACE ADDRESS
59h
:

ROM
1 0 1 0 0 0 0 1 1 0 0 1
ADDRESS:A19h
VR01573C

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 ST6252C ST6262B ST6262C

MEMORY MAP (Cont’d)

1.3.6 Data RAM/EEPROM Bank Register tion. The DRBR register is not modified when an
(DRBR) interrupt or a subroutine occurs.
Address: E8h — Write only Notes :
Care is required when handling the DRBR register
7 0
as it is write only. For this reason, it is not allowed

)
- - -
DRBR
- - -
DRBR to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-

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4 0

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not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
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Page 2.
Bit 3-1. Not used
the program writes to DRBR it must write also to
the image register. The image register must be

od
Bit 0. DRBR0. This bit, when set, selects EEP-
ROM page 0.
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
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The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
wise two or more pages are enabled in parallel,
producing errors.
t e
le
ter) located at address E8h of the Data Space ac-
cording to Table 1. No more than one bank should Care must also be taken not to change the
be set at a time.
The DRBR register can be addressed like a RAM
s o
E²PROM page (when available) when the parallel
writing mode is set for the E²PROM, as defined in
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to select
EECTL register.

O b
Table 3. Data RAM Bank Register Set-up
the desired 64-byte RAM bank of the Data Space.
The bank number has to be loaded in the DRBR
DRBR
00
) - ST62T52C
None
ST62T62C
None
register and the instruction has to point to the se-
lected location as if it was in bank 0 (from 00h ad-
t (
01
02 s Not available
Not Available
EEPROM page 0
Not Available
dress to 3Fh address).
This register is not cleared during the MCU initiali-
u c 08 Not available Not available

d
zation, therefore it must be written before the first 10h RAM Page 2 RAM Page 2
access to the Data Space bank region. Refer to

o
other Reserved Reserved

r
the Data Space description for additional informa-

P
e t e
o l
b s
O

9/75
ST6252C ST6262B ST6262C

MEMORY MAP (Cont’d)

1.3.7 EEPROM Description (PMODE). In BMODE, one byte is accessed at a
EEPROM memory is located in 64-byte pages in time, while in PMODE up to 8 bytes in the same
data space. This memory may be used by the user row are programmed simultaneously (with conse-
program for non-volatile data storage. quent speed and power consumption advantages,
the latter being particularly important in battery
Data space from 00h to 3Fh is paged as described powered circuits).
in Table 4 . EEPROM locations are accessed di-
rectly by addressing these paged sections of data General Notes:

s )
t(
space. Data should be written directly to the intended ad-

c
The EEPROM does not require dedicated instruc- dress in EEPROM space. There is no buffer mem-
ory between data RAM and the EEPROM space.
tions for read or write access. Once selected via the
Data RAM Bank Register, the active EEPROM When the EEPROM is busy (E2BUSY = “1”)
d u
o
page is controlled by the EEPROM Control Regis- EECTL cannot be accessed in write mode, it is
ter (EECTL), which is described below.
Bit E20FF of the EECTL register must be reset prior
to any write or read access to the EEPROM. If no
only possible to read the status of E2BUSY. This
implies that as long as the EEPROM is busy, it is
not possible to change the status of the EEPROM
P r
bank has been selected, or if E2OFF is set, any ac-
cess is meaningless. and must never be set.
e
Control Register. EECTL bits 4 and 5 are reserved

t
Programming must be enabled by setting the
E2ENA bit of the EECTL register.
o le
Care is required when dealing with the EECTL reg-
ister, as some bits are write only. For this reason,
The E2BUSY bit of the EECTL register is set when
the EEPROM is performing a programming cycle.
b s
the EECTL contents must not be altered while ex-
ecuting an interrupt service routine.

O
Any access to the EEPROM when E2BUSY is set If it is impossible to avoid writing to this register
within an interrupt service routine, an image of the
is meaningless.
Provided E2OFF and E2BUSY are reset, an EEP-
) -
register must be saved in a RAM location, and
each time the program writes to EECTL it must
ROM location is read just like any other data loca-
tion, also in terms of access time.
t ( s
also write to the image register. The image register
must be written to first so that, if an interrupt oc-
Writing to the EEPROM may be carried out in two
modes: Byte Mode (BMODE) and Parallel Mode
u c
curs between the two instructions, the EECTL will
not be affected.

d
Table 4. Row Arrangement for Parallel Writing of EEPROM Locations

o
Pr
Dataspace
addresses.

Byte 0

e t1e 2 3 4 5 6 7
Banks 0 and 1.

ol
ROW7 38h-3Fh
ROW6 30h-37h
ROW5
ROW4
b s 28h-2Fh
20h-27h
ROW3
ROW2
ROW1
O 18h-1Fh
10h-17h
08h-0Fh
ROW0 00h-07h

Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.

The number of available 64-byte banks (1 or 2) is device dependent.

Note: The EEPROM is disabled as soon as STOP instruction is executed in order to achieve the lowest
power-consumption.

10/75
 ST6252C ST6262B ST6262C

MEMORY MAP (Cont’d)

Additional Notes on Parallel Mode: EEPROM Control Register (EECTL)
If the user wishes to perform parallel program- Address: EAh — Read/Write
ming, the first step should be to set the E2PAR2 Reset status: 00h
bit. From this time on, the EEPROM will be ad-
dressed in write mode, the ROW address and the 7 0
data will be latched and it will be possible to
change them only at the end of the programming D7
E2O
FF
D5 D4
E2PA
R1
E2PA
R2
E2BU E2E
SY NA
s )
t(
cycle or by resetting E2PAR2 without program-
ming the EEPROM. After the ROW address is
latched, the MCU can only “see” the selected
EEPROM row and any attempt to write or read
Bit 7 = D7: Unused.
Bit 6 = E2OFF: Stand-by Enable Bit. WRITE ONLY.
u c
other rows will produce errors. If this bit is set the EEPROM is disabled (any access
will be meaningless) and the power consumption of
od
r
The EEPROM should not be read while E2PAR2
is set. the EEPROM is reduced to its lowest value.
As soon as the E2PAR2 bit is set, the 8 volatile
ROW latches are cleared. From this moment on,
Bit 5-4 = D5-D4: Reserved. MUST be kept reset.
Bit 3 = E2PAR1: Parallel Start Bit. WRITE ONLY.
e P
the user can load data in all or in part of the ROW.
Setting E2PAR1 will modify the EEPROM regis-
le t
Once in Parallel Mode, as soon as the user software
sets the E2PAR1 bit, parallel writing of the 8 adja-

o
ters corresponding to the ROW latches accessed cent registers will start. This bit is internally reset at

s
after E2PAR2. For example, if the software sets the end of the programming procedure. Note that
E2PAR2 and accesses the EEPROM by writing to

b
less than 8 bytes can be written if required, the un-
addresses 18h, 1Ah and 1Bh, and then sets defined bytes being unaffected by the parallel pro-
E2PAR1, these three registers will be modified si-
multaneously; the remaining bytes in the row will
be unaffected.
- O
gramming cycle; this is explained in greater detail in
the Additional Notes on Parallel Mode overleaf.

Note that E2PAR2 is internally reset at the end of

)
Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE

s
ONLY. This bit must be set by the user program in

(
t
the programming cycle. This implies that the user order to perform parallel programming. If E2PAR2

c
must set the E2PAR2 bit between two parallel pro- is set and the parallel start bit (E2PAR1) is reset,
gramming cycles. Note that if the user tries to set up to 8 adjacent bytes can be written simultane-
E2PAR1 while E2PAR2 is not set, there will be no
programming cycle and the E2PAR1 bit will be un-
d u ously. These 8 adjacent bytes are considered as a
row, whose address lines A7, A6, A5, A4, A3 are

o
affected. Consequently, the E2PAR1 bit cannot be

r
set if E2ENA is low. The E2PAR1 bit can be set by
fixed while A2, A1 and A0 are the changing bits, as
illustrated in Table 4. E2PAR2 is automatically re-

also set.

e P
the user, only if the E2ENA and E2PAR2 bits are set at the end of any parallel programming proce-
dure. It can be reset by the user software before

l e t
Notes: The EEPROM page shall not be changed
through the DRBR register when the E2PAR2 bit
starting the programming procedure, thus leaving
the EEPROM registers unchanged.

o
is set. Bit 1 = E2BUSY: EEPROM Busy Bit. READ ON-

s
LY. This bit is automatically set by the EEPROM
control logic when the EEPROM is in program-

O b ming mode. The user program should test it before

any EEPROM read or write operation; any attempt
to access the EEPROM while the busy bit is set
will be aborted and the writing procedure in
progress will be completed.
Bit 0 = E2ENA: EEPROM Enable Bit. WRITE ON-
LY. This bit enables programming of the EEPROM
cells. It must be set before any write to the EEP-
ROM register. Any attempt to write to the EEP-
ROM when E2ENA is low is meaningless and will
not trigger a write cycle.

11/75
ST6252C ST6262B ST6262C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes EXTCNTL is low, STOP mode is not available with
The two Option Bytes allow configuration capabili- the watchdog active.
ty to the MCUs. Option byte’s content is automati- PB2-3 PULL. When set this bit removes pull-up at
cally read, and the selected options enabled, when reset on PB2-PB3 pins. When cleared PB2-PB3
the chip reset is activated. pins have an internal pull-up resistor at reset.
It can only be accessed during the programming
mode. This access is made either automatically
D4. Reserved. Must be cleared to 0.

s )
t(
WDACT. This bit controls the watchdog activation.
(copy from a master device) or by selecting the When it is high, hardware activation is selected.
OPTION BYTE PROGRAMMING mode of the pro-
grammer.
The software activation is selected when WDACT
is low.
u c
The option bytes are located in a non-user map.
No address has to be specified.
DELAY. This bit enables the selection of the delay

od
r
internally generated after the internal reset (exter-
nal pin, LVD, or watchdog activated) is released.
EPROM Code Option Byte (LSB) When DELAY is low, the delay is 2048 cycles of
the oscillator, it is of 32768 cycles when DELAY is
e P
7

PRO- EXTC- PB2-3

- WDACT
DE-
0

OSCIL OSGEN
high.

le t
OSCIL. Oscillator selection. When this bit is low,

o
the oscillator must be controlled by a quartz crys-
TECT NTL PULL LAY

EPROM Code Option Byte (MSB) b s

tal, a ceramic resonator or an external frequency.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be

15 8 O
externally provided.

-
OSGEN. Oscillator Safe Guard. This bit must be
- - -
ADC
SYNCHRO
- -
NMI
PULL
LVD

s )
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.

(
D15-D13. Reserved. Must be cleared.
c t
The Option byte is written during programming ei-
ther by using the PC menu (PC driven Mode) or
ADC SYNCHRO. When set, an A/D conversion is
started upon WAIT instruction execution, in order
d u automatically (stand-alone mode).
1.4.2 Program Memory
to reduce supply noise. When this bit is low, an
o
Pr
A/D conversion is started as soon as the STA bit of EPROM/OTP programming mode is set by a
the A/D Converter Control Register is set. +12.5V voltage applied to the TEST/VPP pin. The
programming flow of the ST62T62C is described
D11. Reserved, must be cleared.

t
D10. Reserved, must be set to one.

e e in the User Manual of the EPROM Programming

Board.

ol
NMI PULL. NMI Pull-Up. This bit must be set high The MCUs can be programmed with the
to configure the NMI pin with a pull-up resistor. ST62E6xB EPROM programming tools available

b s
When it is low, no pull-up is provided.
LVD. LVD RESET enable.When this bit is set, safe
RESET is performed by MCU when the supply
from STMicroelectronics.
Table 5. ST62T52C/T62C Program Memory Map

O
voltage is too low. When this bit is cleared, only
power-on reset or external RESET are active.
PROTECT. Readout Protection. This bit allows the
Device Address
0000h-087Fh
0880h-0F9Fh
Description
Reserved
User ROM
protection of the software contents against piracy. 0FA0h-0FEFh Reserved
When the bit PROTECT is set high, readout of the 0FF0h-0FF7h Interrupt Vectors
OTP contents is prevented by hardware.. When 0FF8h-0FFBh Reserved
this bit is low, the user program can be read. 0FFCh-0FFDh NMI Interrupt Vector
0FFEh-0FFFh Reset Vector
EXTCNTL. External STOP MODE control.. When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one. When Note: OTP/EPROM devices can be programmed
with the development tools available from STMi-
croelectronics (ST62E6X-EPB or ST626X-KIT).

12/75
 ST6252C ST6262B ST6262C

PROGRAMMING MODES (Cont’d)

1.4.3 . EEPROM Data Memory ternal programmer. Any STMicroelectronics tool
used for the program memory (OTP/EPROM) can
EEPROM data pages are supplied in the virgin also be used to program the EEPROM data mem-
state FFh. Partial or total programming of EEP- ory.
ROM data memory can be performed either
through the application software or through an ex-

s )
ct(
d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

13/75
ST6252C ST6262B ST6262C

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the Indirect Registers (X, Y). These two indirect reg-
I/O or Memory configuration. As such, it may be isters are used as pointers to memory locations in
thought of as an independent central processor Data space. They are used in the register-indirect
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
s )
t(
buses. In-core communication is arranged as dresses 80h (X) and 81h (Y). They can also be ac-
shown in Figure 6; the controller being externally cessed with the direct, short direct, or bit direct ad-
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
u c
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
ister of the data space.

od
2.2 CPU REGISTERS
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
P r
e
The ST6 Family CPU core features six registers and space as RAM locations at addresses 82h (V) and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
le t
83h (W). They can also be accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
s o
ters as any other register of the data space.

b
Program Counter (PC). The program counter is a
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data 12-bit register which contains the address of the
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
- O
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
other register in Data space.

s )
length allows the direct addressing of 4096 bytes
in Program space.

(
Figure 6ST6 Core Block Diagram

c t
RESET
OSCin
u
0,01 TO 8MHz

d OSCout

o
Pr
INTERRUPTS
CONTROLLER

e
DATA SPACE

e t
ol
CONTROL
FLAG SIGNALS DATA

bs
OPCODE VALUES ADDRESS/READ LINE
2 RAM/EEPROM

O
PROGRAM
ROM/EPROM ADDRESS
DECODER
256
DATA
ROM/EPROM

A-DATA B-DATA
DEDICATIONS

ACCUMULATOR
Program Counter
12 and FLAGS
6 LAYER STACK ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811

14/75
 ST6252C ST6262B ST6262C

CPU REGISTERS (Cont’d)

However, if the program space contains more than a RETI instructions occurs. As the NMI mode is
4096 bytes, the additional memory in program automatically selected after the reset of the MCU,
space can be addressed by using the Program the ST6 core uses at first the NMI flags.
Bank Switch register.
Stack. The ST6 CPU includes a true LIFO hard-
The PC value is incremented after reading the ad- ware stack which eliminates the need for a stack
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
s )
t(
the ALU, where they are added; the result is then space RAM area. When a subroutine call (or inter-
shifted back into the PC. The program counter can rupt request) occurs, the contents of each level are
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
u c
- CALL instructionPC= Call address
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
od
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt PC=Interrupt vector
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumula-
P r
- ResetPC= Reset vector

t
is not stored in this stack, management of these
e
tor, in common with all other data space registers,

le
- RET & RETI instructionsPC= Pop (stack) registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position

o
- Normal instructionPC= PC + 1
if more than 6 nested calls or interrupts are execut-
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
s
ed, and consequently the last return address will

b
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY O
In this case the next instruction will be executed.

-
)
flag and a ZERO flag. One pair (CN, ZN) is used Figure 7ST6 CPU Programming Mode
during Normal operation, another pair is used dur-
s
l

ing Interrupt mode (CI, ZI), and a third pair is used

in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
c t (
INDEX
REGISTER
b7 X REG. POINTER b0
SHORT

u b7 Y REG. POINTER b0 DIRECT

ADDRESSING
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or

o d b7 V REGISTER b0 MODE

r
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)

P
instead of the Normal flags. When the RETI in-
b7

b7
W REGISTER

ACCUMULATOR
b0

b0

e
struction is executed, the previously used set of

e t
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non

l
Maskable Interrupt, Normal Interrupt or Main rou-
b11 PROGRAM COUNTER b0

o
tine). The flags are not cleared during context

bs
switching and thus retain their status. SIX LEVELS
STACK REGISTER
The Carry flag is set when a carry or a borrow oc-

O
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
pates in the rotate left instruction. NORMAL FLAGS C Z

The Zero flag is set if the result of the last arithme-

INTERRUPT FLAGS C Z
tic or logical operation was equal to zero; other-
wise it is cleared.
NMI FLAGS C Z
Switching between the three sets of flags is per- VA000423
formed automatically when an NMI, an interrupt or

15/75
ST6252C ST6262B ST6262C

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

The MCU features a Main Oscillator which can be Figure 8. Oscillator Configurations
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita-

)
CRYSTAL/RESONATOR CLOCK
ble ceramic resonator, or with an external resistor CRYSTAL/RESONATOR option
(RNET). In addition, a Low Frequency Auxiliary Os-
cillator (LFAO) can be switched in for security rea-
t( s
sons, to reduce power consumption, or to offer the
c
ST6xxx

u
benefits of a back-up clock system.
The Oscillator Safeguard (OSG) option filters
spikes from the oscillator lines, provides access to
OSCin OSCout

od
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automati-
cally limits the internal clock frequency (fINT) as a
P r
function of VDD, in order to guarantee correct oper-
ation. These functions are illustrated in Figure 9.,
CL1n CL2

t e
Figure 10., Figure 11. and Figure 12..
Figure 8. illustrates various possible oscillator con- EXTERNAL CLOCK
o le
figurations using an external crystal or ceramic res-
onator, an external clock input, an external resistor
(RNET), or the lowest cost solution using only the b s
CRYSTAL/RESONATOR option

LFAO. CL1 an CL2 should have a capacitance in the

range 12 tclkadcosgo 22 pF for an oscillator fre-
- O ST6xxx

quency in the 4-8 MHz range.

The internal MCU clock frequency (fINT) is divided
( s ) OSCin OSCout

by 12 to drive the Timer, the A/D converter and the

Watchdog timer, and by 13 to drive the CPU core,
c t NC

as may be seen in Figure 11..

d
With an 8 MHz oscillator frequency, the fastest ma- u RC NETWORK

o
RC NETWORK option
chine cycle is therefore 1.625µs.

P r
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment ST6xxx

e
the Program Counter). An instruction may require

let
two, four, or five machine cycles for execution. OSCin OSCout
3.1.1 Main Oscillator

so
NC
The oscillator configuration may be specified by se-
lecting the appropriate option. When the CRYS- RNET

Ob
TAL/RESONATOR option is selected, it must be
used with a quartz crystal, a ceramic resonator or an
external signal provided on the OSCin pin. When the
RC NETWORK option is selected, the system clock INTEGRATED CLOCK
is generated by an external resistor. CRYSTAL/RESONATOR option
OSG ENABLED option
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The ST6xxx
Low Frequency Auxiliary Oscillator is automatical-
ly started. OSCin OSCout

NC

16/75
 ST6252C ST6262B ST6262C

CLOCK SYSTEM (Cont’d)

Turning on the main oscillator is achieved by re- tions: it filters spikes from the oscillator lines which
setting the OSCOFF bit of the A/D Converter Con- would result in over frequency to the ST62 CPU; it
trol Register or by resetting the MCU. Restarting gives access to the Low Frequency Auxiliary Os-
the main oscillator implies a delay comprising the cillator (LFAO), used to ensure minimum process-
oscillator start up delay period plus the duration of ing in case of main oscillator failure, to offer re-
the software instruction at fLFAO clock frequency. duced power consumption or to provide a fixed fre-
3.1.2 Low Frequency Auxiliary Oscillator quency low cost oscillator; finally, it automatically
limits the internal clock frequency as a function of
s )
t(
(LFAO)
supply voltage, in order to ensure correct opera-

c
The Low Frequency Auxiliary Oscillator has three tion even if the power supply should drop.
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
The OSG is enabled or disabled by choosing the
relevant OSG option. It may be viewed as a filter
d u
without any external components. Lastly, it acts as
a safety oscillator in case of main oscillator failure.
whose cross-over frequency is device dependent.
Spikes on the oscillator lines result in an effectively
r o
This oscillator is available when the OSG ENA-
BLED option is selected. In this case, it automati-
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre-
e P
cally starts one of its periods after the first missing
edge from the main oscillator, whatever the reason
quency for a given power supply voltage. The

le t
OSG filters out such spikes (as illustrated in Figure
9.). In all cases, when the OSG is active, the max-

o
(main oscillator defective, no clock circuitry provid-
imum internal clock frequency, fINT, is limited to

s
ed, main oscillator switched off...).
fOSG, which is supply voltage dependent. This re-
User code, normal interrupts, WAIT and STOP in-
structions, are processed as normal, at the re-
duced fLFAO frequency. The A/D converter accura-
O b
lationship is illustrated in Figure 12..
When the OSG is enabled, the Low Frequency
cy is decreased, since the internal frequency is be-
low 1MHz. -
Auxiliary Oscillator may be accessed. This oscilla-
tor starts operating after the first missing edge of

)
the main oscillator (see Figure 10.).
At power on, the Low Frequency Auxiliary Oscilla-
tor starts faster than the Main Oscillator. It there-
t ( s
Over-frequency, at a given power supply level, is

c
fore feeds the on-chip counter generating the POR seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock fre-
delay until the Main Oscillator runs.
The Low Frequency Auxiliary Oscillator is auto-
d u quency of the device is kept within the range the
particular device can stand (depending on VDD),
tor starts.
r o
matically switched off as soon as the main oscilla- and below fOSG: the maximum authorised frequen-
cy with OSG enabled.
ADCR
Address: 0D1h — Read/Write
e P Note. The OSG should be used wherever possible
as it provides maximum safety. Care must be tak-
7

l e t 0
en, however, as it can increase power consump-
tion and reduce the maximum operating frequency

o
ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR to fOSG.
7 6

b s
5 4 3 OFF

Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:

1 0 Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and is not accu-

O
ADC Control Register. These bits are not used.
Bit 2 = OSCOFF. When low, this bit enables main
oscillator to run. The main oscillator is switched off
rate.
For precise timing measurements, it is not recom-
mended to use the OSG and it should not be ena-
when OSCOFF is high. bled in applications that use the SPI or the UART.
3.1.3 Oscillator Safe Guard It should also be noted that power consumption in
The Oscillator Safe Guard (OSG) affords drastical- Stop mode is higher when the OSG is enabled
ly increased operational integrity in ST62xx devic- (around 50µA at nominal conditions and room
es. The OSG circuit provides three basic func- temperature).

17/75
ST6252C ST6262B ST6262C

CLOCK SYSTEM (Cont’d)

Figure 9. OSG Filtering Principle

(1)

s )
ct(
(2)

d u
r o
(3)

e P
le t
(4)
s o
Ob
(1) Maximum Frequency for the device to work correctly
) -
(2) Actual Quartz Crystal Frequency at OSCin pin

t ( s
c
(3) Noise from OSCin
VR001932

u
(4) Resulting Internal Frequency

o d
r
Figure 10. OSG Emergency Oscillator Principle

P
e t e
Main
Oscillator
o l
b s
O
Emergency
Oscillator

Internal
Frequency

VR001933

18/75
 ST6252C ST6262B ST6262C

CLOCK SYSTEM (Cont’d)

Figure 11. Clock Circuit Block Diagram

POR

)
: 13 Core

s
OSG

TIMER 1

ct(
MAIN
OSCILLATOR
M
U
X
fINT
: 12
Watchdog

d u
r o
LFAO

e P
:1

le t
Main Oscillator off

s o
Figure 12. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)

O b
Maximum FREQUENCY (MHz)

) -
8

4
t ( s
c
7
FUNCTIONALITY IS NOT

du
3
6
fOSG
GUARANTEED
IN THIS AREA

r o fOSG Min (at 85°C)

4

e P 2

t
3
fOSG Min (at 125°C)
2

l e
so
1
1
2.5 3 3.6 4 4.5 5 5.5 6

Ob
SUPPLY VOLTAGE (VDD)
VR01807J

Notes:
1. In this area, operation is guaranteed at the area is guaranteed at the quartz crystal frequency.
quartz crystal frequency. When the OSG is enabled, access to this area is
2. When the OSG is disabled, operation in this prevented. The internal frequency is kept a fOSG.
area is guaranteed at the crystal frequency. When 4. When the OSG is disabled, operation in this
the OSG is enabled, operation in this area is guar- area is not guaranteed
anteed at a frequency of at least fOSG Min. When the OSG is enabled, access to this area is
3. When the OSG is disabled, operation in this prevented. The internal frequency is kept at fOSG.

19/75
ST6252C ST6262B ST6262C

3.2 RESETS
The MCU can be reset in four ways: is executed immediately following the internal de-
– by the external Reset input being pulled low; lay.
– by Power-on Reset; To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi-
– by the digital Watchdog peripheral timing out. cient level for the chosen frequency (see recom-
– by Low Voltage Detection (LVD)
3.2.1 RESET Input
mended operation) before the reset signal is re-
leased. In addition, supply rising must start from
s )
t(
0V.
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
As a consequence, the POR does not allow to su-
pervise static, slowly rising, or falling, or noisy
u c
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
(presenting oscillation) VDD supplies.
An external RC network connected to the RESET
od
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
pin, or the LVD reset can be used instead to get
the best performances.
P r
external signal. Therefore even short pulses on
the RESET pin are acceptable, provided VDD has
Figure 13. Reset and Interrupt Processing

t e
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
RESET

o le
The MCU is kept in the Reset state as long as the
RESET pin is held low.
If RESET activation occurs in the RUN or WAIT b s
NMI MASK SET

O
INT LATCH CLEARED
( IF PRESENT )
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
) -
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization se-
t ( s SELECT
NMI MODE FLAGS

quence is executed following expiry of the internal

delay period.
u c
If RESET pin activation occurs in the STOP mode,

o d
the oscillator starts up and all Inputs and Outputs
PUT FFEH
ON ADDRESS BUS

P r
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following

e
expiry of the internal delay period.

let
YES
IS RESET STILL
3.2.2 Power-on Reset PRESENT?

The function of the POR circuit consists in waking

so
up the MCU by detecting around 2V a dynamic NO
(rising edge) variation of the VDD Supply. At the

Ob
beginning of this sequence, the MCU is configured LOAD PC
FROM RESET LOCATIONS
in the Reset state: all I/O ports are configured as FFE/FFF
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to FETCH INSTRUCTION
allow the oscillator to fully stabilize before execut-
ing the first instruction. The initialization sequence VA000427

20/75
 ST6252C ST6262B ST6262C

RESETS (Cont’d)
3.2.3 Watchdog Reset ues, allowing hysteresis effect. Reference value in
The MCU provides a Watchdog timer function in case of voltage drop has been set lower than the
order to ensure graceful recovery from software reference value for power-on in order to avoid any
upsets. If the Watchdog register is not refreshed parasitic Reset when MCU start's running and
before an end-of-count condition is reached, the sinking current on the supply.
internal reset will be activated. This, amongst oth- As long as the supply voltage is below the refer-
er things, resets the watchdog counter. ence value, there is a internal and static RESET

s )
t(
command. The MCU can start only when the sup-
The MCU restarts just as though the Reset had ply voltage rises over the reference value. There-
been generated by the RESET pin, including the
built-in stabilisation delay period.
fore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
u c
3.2.4 LVD Reset running mode over the voltage reference as
shown on the Figure 14., that represents a power-
od
The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a reference value. Thanks to this
up, power-down sequence.
Note: When the RESET state is controlled by one
of the internal RESET sources (Low Voltage De- P r
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
t
tector, Watchdog, Power on Reset), the RESET
e
le
RESET is effective as well in Power-on phase as pin is tied to low logic level.
in power supply drop with different reference val-
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
s o
O b
) -
s
VDD

c t (
d u
r o
VUp

e P
Vdn

l e t
s o
RESET
RESET

O b time
VR02106A

3.2.5 Application Notes

No external resistor is required between VDD and Direct external connection of the pin RESET to
the Reset pin, thanks to the built-in pull-up device. VDD must be avoided in order to ensure safe be-
haviour of the internal reset sources (AND.Wired
structure).

21/75
ST6252C ST6262B ST6262C

RESETS (Cont’d)
3.2.6 MCU Initialization Sequence Figure 15. Reset and Interrupt Processing
When a reset occurs the stack is reset, the PC is
RESET
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is RESET
JP JP:2 BYTES/4 CYCLES

s )
t(
in Non Maskable Interrupt mode; this prevents the VECTOR
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
u c
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
od
r
INITIALIZATION
MCU will continue by processing the instruction ROUTINE RETI: 1 BYTE/2 CYCLES
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
RETI

e P
t
iced. VA00181

o le
Figure 16. Reset Block Diagram
b s
- O
( s )
VDD
fOSC

c t CK
ST6
INTERNAL

d u RESET

o
RPU COUNTER

RESET
RESD 1)

P r AND. Wired

RESET
RESET

t
POWER ON RESET

e e
l
WATCHDOG RESET

s o
LVD RESET

O b VR02107A

1) Resistive ESD protection. Value not guaranteed.

22/75
 ST6252C ST6262B ST6262C

3.3 RESETS (Cont’d)

Table 6. Register Reset Status

Register Address(es) Status Comment
EEPROM Control Register 0EAh EEPROM enabled (if available)
Port Data Registers 0C0h to 0C2h I/O are Input with pull-up
Port Direction Register 0C4h to 0C6h I/O are Input with pull-up

s )
t(
Port Option Register 0CCh to 0CEh I/O are Input with pull-up
Interrupt Option Register 0C8h Interrupt disabled
TIMER Status/Control 0D4h 00h TIMER disabled

u c
AR TIMER Mode Control Register 0D5h AR TIMER stopped

od
AR TIMER Status/Control 1 Register
AR TIMER Status/Control 2Register
0D6h
0D7h
P r
e
AR TIMER Compare Register 0DAh
X, Y, V, W, Register
Accumulator
080H TO 083H
0FFh
le t
Data RAM
Data RAM Page REgister
084h to 0BFh
0E8h
s o
Data ROM Window Register
EEPROM
0C9h
00h to F3h
Undefined

O b
As written if programmed
A/D Result Register
AR TIMER Load Register
0D0h
0DBh
) -
AR TIMER Reload/Capture Register
TIMER Counter Register
0D9h
0D3h
t ( s
FFh
TIMER Prescaler Register 0D2h

uc 7Fh Max count loaded

d
Watchdog Counter Register 0D8h FEh

o
A/D Control Register 0D1h 40h A/D in Standby

P r
e t e
o l
b s
O

23/75
ST6252C ST6262B ST6262C

3.4 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable When the Watchdog is disabled, low power Stop
downcounter timer which can be used to provide mode is available. Once activated, the Watchdog
controlled recovery from software upsets. cannot be disabled, except by resetting the MCU.
The Watchdog circuit generates a Reset when the In the HARDWARE option, the Watchdog is per-
downcounter reaches zero. User software can manently enabled. Since the oscillator will run con-
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc-
s )
t(
regularly reloaded while the user program runs tion, and the Watchdog continues to countdown.
correctly. In the event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no longer behave in its usual
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
u c
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then gov-
od
decrement down to 00h and reset the MCU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
P r
concept in mind.
t e
as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
Watchdog behaviour is governed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
ters STOP mode.
o le
the Watchdog counter is frozen and the CPU en-

STOP MODE CONTROL” (see Table 7 ).

In the SOFTWARE option, the Watchdog is disa-
b s
When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its

O
activity.
bled until bit C of the DWDR register has been set.

) -
Table 7. Recommended Option Choices
Functions Required
t ( s Recommended Options
Stop Mode & Watchdog

u c
“EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”

d
Stop Mode “SOFTWARE WATCHDOG”

o
Watchdog “HARDWARE WATCHDOG”

P r
e t e
o l
b s
O

24/75
 ST6252C ST6262B ST6262C

DIGITAL WATCHDOG (Cont’d)

The Watchdog is associated with a Data space Figure 17. Watchdog Counter Control
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.4.1 Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the D0

)
C
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to the D1 SR
t( s

WATCHDOG CONTROL REGISTER

user’s requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR
u c

WATCHDOG COUNTER
RESET

d
bit must be set to “1”, since it is this bit which gen- D2 T5
erates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re-
set. D3
r o
It should be noted that the order of the bits in the
T4

e P
t
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the D4 T3
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
o le
s
these bits are inverted and shifted with respect to D5 T2
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
b
-O
bits and the physical implementation of the Watch- D6 T1
dog timer downcounter is illustrated in Figure 17..

(s)
Only the 6 most significant bits may be used to de- D7 T0
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
c t ÷28 OSC ÷12
3,072 to 196,608 clock cycles (with an oscillator
u
od
frequency of 8 MHz, this is equivalent to timer peri-
ods ranging from 384 µs to 24.576 ms). VR02068A

P r
e t e
o l
b s
O

25/75
ST6252C ST6262B ST6262C

DIGITAL WATCHDOG (Cont’d)

3.4.1 Digital Watchdog Register (DWDR) 3.4.2 Application Notes
Address: 0D8h — Read/Write The Watchdog plays an important supporting role
Reset status: 1111 1110 b in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
7 0 lated options should be selected on the basis of a
trade-off between application security and STOP
T0 T1 T2 T3 T4 T5 SR C mode availability.

s )
t(
When STOP mode is not required, hardware acti-

c
Bit 0 = C: Watchdog Control bit vation without EXTERNAL STOP MODE CON-
TROL should be preferred, as it provides maxi-
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog mum security, especially during power-on.

d u
o
is always active). When the software option is se- When STOP mode is required, hardware activa-
lected, the Watchdog function is activated by set-
ting bit C to 1, and cannot then be disabled (save
by resetting the MCU).
tion and EXTERNAL STOP MODE CONTROL
should be chosen. NMI should be high by default,
to allow STOP mode to be entered when the MCU
P r
When C is kept low the counter can be used as a is idle.

t e
le
7-bit timer. The NMI pin can be connected to an I/O line (see
This bit is cleared to “0” on Reset. Figure 18.) to allow its state to be controlled by
Bit 1 = SR: Software Reset bit
s o
software. The I/O line can then be used to keep
NMI low while Watchdog protection is required, or
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of b
to avoid noise or key bounce. When no more
processing is required, the I/O line is released and

O
the device placed in STOP mode for lowest power

-
the 7-bit timer. consumption.
This bit is set to “1” on Reset.
Bits 2-7 = T5-T0: Downcounter bits
s )
When software activation is selected and the
Watchdog is not activated, the downcounter may

(
It should be noted that the register bits are re-
versed and shifted with respect to the physical
c t
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.
d u The software activation option should be chosen
only when the Watchdog counter is to be used as
These bits are set to “1” on Reset.
r o a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions

e P should be executed within the first 27 instructions:

jrr 0, WD, #+3

l e t ldi WD, 0FDH

s o
O b

26/75
 ST6252C ST6262B ST6262C

DIGITAL WATCHDOG (Cont’d)

These instructions test the C bit and Reset the Figure 18. A typical circuit making use of the
MCU (i.e. disable the Watchdog) if the bit is set EXERNAL STOP MODE CONTROL feature
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
SWITCH

s )
t(
should load the watchdog counter within the first NMI
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
u c
It should be noted that when the GEN bit is low (in-
I/O

od
r
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.

e P
le t
VR02002

Figure 19. Digital Watchdog Block Diagram

s o
RESET
O b
) -
t ( s
u c
Q
RSFF -2
7

o d -2 8 -12

r
S R DB1.7 LOAD SET SET

e P
t
OSCILLATOR

e 8 CLOCK

o l DB0

b s WRITE

O
RESET
DATA BUS
VA00010

27/75
ST6252C ST6262B ST6262C

3.5 INTERRUPTS
The CPU can manage four Maskable Interrupt ically reset by the core at the beginning of the non-
sources, in addition to a Non Maskable Interrupt maskable interrupt service routine.
source (top priority interrupt). Each source is asso- Interrupt request from source #1 can be config-
ciated with a specific Interrupt Vector which con- ured either as edge or level sensitive by setting ac-
tains a Jump instruction to the associated interrupt cordingly the LES bit of the Interrupt Option Regis-
service routine. These vectors are located in Pro-
gram space (see Table 8 ).
ter (IOR).
Interrupt request from source #2 are always edge
s )
t(
When an interrupt source generates an interrupt sensitive. The edge polarity can be configured by
request, and interrupt processing is enabled, the
PC register is loaded with the address of the inter-
rupt vector (i.e. of the Jump instruction), which
setting accordingly the ESB bit of the Interrupt Op-
tion Register (IOR).
u c
then causes a Jump to the relevant interrupt serv-
ice routine, thus servicing the interrupt.
Interrupt request from sources #3 & #4 are level
sensitive.
od
Interrupt sources are linked to events either on ex-
ternal pins, or on chip peripherals. Several events
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started. P r
can be ORed on the same interrupt source, and
relevant flags are available to determine which
t e
So, the occurrence of an interrupt can be stored,

le
event triggered the interrupt. until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt routine
s o
occurs before completion of the running interrupt
routine, only the first request is stored.
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request
is pending, these are processed by the processor
O b
Storage of interrupt requests is not available in lev-
el sensitive mode. To be taken into account, the
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The -
low level must be present on the interrupt pin when
the MCU samples the line after instruction execu-
tion.
)
priority of each interrupt source is fixed.
Table 8. Interrupt Vector Map
t ( s
At the end of every instruction, the MCU tests the

c
interrupt lines: if there is an interrupt request the
next instruction is not executed and the appropri-
Interrupt Source
Interrupt source #0
Priority
1
Vector Address
(FFCh-FFDh)
d u ate interrupt service routine is executed instead.
Interrupt source #1 2 (FF6h-FF7h)
o Table 9. Interrupt Option Register Description

Pr
Interrupt source #2 3 (FF4h-FF5h)
SET Enable all interrupts
Interrupt source #3 4 (FF2h-FF3h) GEN
CLEARED Disable all interrupts
Interrupt source #4 5

e t e (FF0h-FF1h)
SET
Rising edge mode on inter-
rupt source #2
3.5.1 Interrupt request
l ESB
Falling edge mode on inter-

so
CLEARED
All interrupt sources but the Non Maskable Inter- rupt source #2
rupt source can be disabled by setting accordingly Level-sensitive mode on in-

Ob
SET
the GEN bit of the Interrupt Option Register (IOR). terrupt source #1
This GEN bit also defines if an interrupt source, in- LES
Falling edge mode on inter-
cluding the Non Maskable Interrupt source, can re- CLEARED
rupt source #1
start the MCU from STOP/WAIT modes. OTHERS NOT USED
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-

28/75
 ST6252C ST6262B ST6262C

INTERRUPTS (Cont’d)
3.5.2 Interrupt Procedure MCU
The interrupt procedure is very similar to a call pro- – Automatically the MCU switches back to the nor-
cedure, indeed the user can consider the interrupt mal flag set (or the interrupt flag set) and pops
as an asynchronous call procedure. As this is an the previous PC value from the stack.
asynchronous event, the user cannot know the The interrupt routine usually begins by the identify-
context and the time at which it occurred. As a re-
sult, the user should save all Data space registers
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
s )
t(
which may be used within the interrupt routines. ters which are used within the interrupt routine in a
There are separate sets of processor flags for nor- software stack. After the RETI instruction is exe-
mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
cuted, the MCU returns to the main routine.

u c
need to be saved. Figure 20. Interrupt Processing Flow Chart

od
r
The following list summarizes the interrupt proce- INSTRUCTION
dure:
MCU
FETCH

e P
t
– The interrupt is detected. INSTRUCTION

le
– The C and Z flags are replaced by the interrupt
flags (or by the NMI flags).
– The PC contents are stored in the first level of
the stack.
EXECUTE
INSTRUCTION

s o
– The normal interrupt lines are inhibited (NMI still
b
-O
LOAD PC FROM
active). WAS
NO INTERRUPT VECTOR
THE INSTRUCTION (FFC/FFD)
– The first internal latch is cleared. A RETI ?

(s)
– The associated interrupt vector is loaded in the PC. YES

WARNING: In some circumstances, when a YES

IS THE CORE SET

t
ALREADY IN INTERRUPT MASK
?
maskable interrupt occurs while the ST6 core is in NORMAL MODE?

NORMAL mode and especially during the execu-

tion of an "ldi IOR, 00h" instruction (disabling all
u c CLEAR
NO

d
PUSH THE
maskable interrupts): if the interrupt arrives during INTERRUPT MASK
PC INTO THE STACK

o
the first 3 cycles of the "ldi" instruction (which is a

the interrupt pair CI and ZI.

P r
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to SELECT
PROGRAM FLAGS
SELECT

e
INTERNAL MODE FLAG

let
User
– User selected registers are saved within the in- "POP"
THE STACKED PC
terrupt service routine (normally on a software
stack).

s o
– The source of the interrupt is found by polling the CHECK IF THERE IS

b
NO
? AN INTERRUPT REQUEST
interrupt flags (if more than one source is associ- AND INTERRUPT MASK

O
ated with the same vector).
– The interrupt is serviced.
– Return from interrupt (RETI)
YES
VA000014

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ST6252C ST6262B ST6262C

INTERRUPTS (Cont’d)
3.5.3 Interrupt Option Register (IOR) Bit 5 = ESB: Edge Selection bit.
The Interrupt Option Register (IOR) is used to en- The bit ESB selects the polarity of the interrupt
able/disable the individual interrupt sources and to source #2.
select the operating mode of the external interrupt Bit 4 = GEN: Global Enable Interrupt. When this bit
inputs. This register is write-only and cannot be is set to one, all interrupts are enabled. When this
accessed by single-bit operations.
Address: 0C8h — Write Only
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
s )
Reset status: 00h When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
ct(
u
7 0 modes.
- LES ESB GEN - - - - This register is cleared on reset.

od
Bit 7, Bits 3-0 = Unused.
3.5.4 Interrupt Sources
Interrupt sources available on
ST62E62C/T62C are summarized in the Table 10
the
P r
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
t e
with associated mask bit to enable/disable the in-
terrupt request.
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
o le
Table 10. Interrupt Requests and Mask Bits
Address
b s Interrupt

O
Peripheral Register Mask bit Masked Interrupt Source
Register vector
GENERAL
TIMER
IOR
TSCR1
C8h
D4h
GEN
ETI
) -
All Interrupts, excluding NMI
TMZ: TIMER Overflow Vector 4
A/D CONVERTER ADCR D1h EAI
OVIE
t ( s EOC: End of Conversion
OVF: AR TIMER Overflow
Vector 4

AR TIMER ARMC D5h

u
CPIE
EIE c CPF: Successful compare
EF: Active edge on ARTIMin
Vector 3

Port PAn
Port PBn
ORPA-DRPA
ORPB-DRPB
C0h-C4h
C1h-C5h
o d ORPAn-DRPAn
ORPBn-DRPBn
PAn pin
PBn pin
Vector 1
Vector 1
Port PCn ORPC-DRPC

P rC2h-C6h ORPCn-DRPCn PCn pin Vector 2

e t e
o l
b s
O

30/75
 ST6252C ST6262B ST6262C

INTERRUPTS (Cont’d)
Figure 21. Interrupt Block Diagram

FROM REGISTER PORT A,B,C

SINGLE BIT ENABLE

s )
t(
PBE

V DD
u c
od
PORT A
PORT B PBE
FF
CLK Q
CLR
0

P r
e
Bits

t
INT #1 (FF6,7)
I Start MUX

le
1

s o
IOR REG. C8H, bit 6

O b RESTART FROM
STOP/WAIT

PORT C PBE
FF
CLK Q
) - INT #2 (FF4,5)

s
Bits
CLR
SPIDIV Register
SPINT bit IOR REG. C8H, bit 5
c t (I 2 Start

SPIE bit
OVF

d u
o
SPIMOD Register OVIE

Pr
CPF INT #3 (FF2,3)
AR TIMER CPIE

EF

e t e
TIMER1
EIE
TMZ

l ETI INT #4 (FF0,1)

VDD

so
EOC
ADC EAI

Ob
FF NMI (FFC,D)
NMI CLK Q
CLR

I0 Start

Bit GEN (IOR Register)

VA0426K

31/75
ST6252C ST6262B ST6262C

3.6 POWER SAVING MODES

The WAIT and STOP modes have been imple- of the processor core prior to the WAIT instruction,
mented in the ST62xx family of MCUs in order to but also on the kind of interrupt request which is
reduce the product’s electrical consumption during generated. This is described in the following para-
idle periods. These two power saving modes are graphs. The processor core does not generate a
described in the following paragraphs. delay following the occurrence of the interrupt, be-
cause the oscillator clock is still available and no
3.6.1 WAIT Mode
stabilisation period is necessary.

s )
t(
The MCU goes into WAIT mode as soon as the 3.6.2 STOP Mode
WAIT instruction is executed. The microcontroller
can be considered as being in a “software frozen”
state where the core stops processing the pro-
If the Watchdog is disabled, STOP mode is availa-
ble. When in STOP mode, the MCU is placed in
u c
gram instructions, the RAM contents and peripher-
al registers are preserved as long as the power
the lowest power consumption mode. In this oper-
ating mode, the microcontroller can be considered

od
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still ac-
tive.
as being “frozen”, no instruction is executed, the
oscillator is stopped, the RAM contents and pe-
ripheral registers are preserved as long as the
P r
e
power supply voltage is higher than the RAM re-
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
periods, while not losing track of time or the capa- Reset to exit the STOP state.
le t
tention voltage, and the ST62xx core waits for the
occurrence of an external interrupt request or a
bility of monitoring external events. The active os-
cillator is not stopped in order to provide a clock
s o
If the STOP state is exited due to a Reset (by acti-

b
signal to the peripherals. Timer counting may be vating the external pin) the MCU will enter a nor-
enabled as well as the Timer interrupt, before en- mal reset procedure. Behaviour in response to in-
tering the WAIT mode: this allows the WAIT mode
to be exited when a Timer interrupt occurs. The
same applies to other peripherals which use the O
terrupts depends on the state of the processor

-
core prior to issuing the STOP instruction, and
also on the kind of interrupt request that is gener-
clock signal. ated.

( s )
t
If the WAIT mode is exited due to a Reset (either This case will be described in the following para-
by activating the external pin or generated by the graphs. The processor core generates a delay af-
Watchdog), the MCU enters a normal reset proce-
dure. If an interrupt is generated during WAIT
u c
ter occurrence of the interrupt request, in order to
wait for complete stabilisation of the oscillator, be-
mode, the MCU’s behaviour depends on the state

o d fore executing the first instruction.

P r
e t e
o l
b s
O

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 ST6252C ST6262B ST6262C

POWER SAVING MODE (Cont’d)

3.6.3 Exit from WAIT and STOP Modes tered will be completed, starting with the
execution of the instruction which follows the
The following paragraphs describe how the MCU STOP or the WAIT instruction, and the MCU is
exits from WAIT and STOP modes, when an inter- still in the interrupt mode. At the end of this rou-
rupt occurs (not a Reset). It should be noted that tine pending interrupts will be serviced in accord-
the restart sequence depends on the original state
ance with their priority.

)
of the MCU (normal, interrupt or non-maskable in-
terrupt mode) prior to entering WAIT or STOP – In the event of a non-maskable interrupt, the
mode, as well as on the interrupt type. non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
t( s
Interrupts do not affect the oscillator selection.
3.6.3.1 Normal Mode
STOP mode was entered will be completed by
executing the instruction following the STOP or
u c
If the MCU was in the main routine when the WAIT
WAIT instruction. The MCU remains in normal
interrupt mode.
od
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt oc-
curs; the related interrupt routine is executed and,
Notes:
To achieve the lowest power consumption during P r
e
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, pro-
viding no other interrupts are pending.
3.6.3.2 Non Maskable Interrupt Mode
care of:

le t
RUN or WAIT modes, the user program must take

– configuring unused I/Os as inputs without pull-up

If the STOP or WAIT instruction has been execut- logic levels);
s o
(these should be externally tied to well defined
ed during execution of the non-maskable interrupt
routine, the MCU exits from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
O b
– placing all peripherals in their power down
modes before entering STOP mode;
which follows the STOP or WAIT instruction is ex-
ecuted, and the MCU remains in non-maskable in-
) -
When the hardware activated Watchdog is select-
ed, or when the software Watchdog is enabled, the
terrupt mode, even if another interrupt has been
generated.

t ( s
STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
3.6.3.3 Normal Interrupt Mode
If the MCU was in interrupt mode before the STOP
u c
If all interrupt sources are disabled (GEN low), the
MCU can only be restarted by a Reset. Although
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an interrupt oc-
o d setting GEN low does not mask the NMI as an in-
terrupt, it will stop it generating a wake-up signal.

Pr
curs. Nevertheless, two cases must be consid-
ered: The WAIT and STOP instructions are not execut-
– If the interrupt is a normal one, the interrupt rou- ed if an enabled interrupt request is pending.

t e
tine in which the WAIT or STOP mode was en-

e
s ol
O b

33/75
ST6252C ST6262B ST6262C

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

The MCU features Input/Output lines which may be also written by user software, in conjunction
be individually programmed as any of the following with the related option registers, to select the dif-
input or output configurations: ferent input mode options.
– Input without pull-up or interrupt Single-bit operations on I/O registers are possible

s )
t(
– Input with pull-up and interrupt but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
– Input with pull-up, but without interrupt
– Analog input
ly affect the Port data register causing an unde-
sired change of the input configuration.
u c
– Push-pull output The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
od
– Open drain output
The lines are organised as bytewise Ports.
set.
The Option registers (ORx) are used to select the
P r
e
Each port is associated with 3 registers in Data different port options available both in input and in
space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associat-
output mode.

le t
All I/O registers can be read or written to just as
ed with the PA0 line of Port A).

s o
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and

b
The DATA registers (DRx), are used to read the manipulation. During MCU initialization, all I/O reg-
voltage level values of the lines which have been isters are cleared and the input mode with pull-ups
configured as inputs, or to write the logic value of
the signal to be output on the lines configured as
outputs. The port data registers can be read to get
- O
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
the effective logic levels of the pins, but they can

( s )
Figure 22. I/O Port Block Diagram

c t
du
RESET VDD
SIN CONTROLS

r
DATA o VDD

e P
DIRECTION
REGISTER

l e t DATA
INPUT/OUTPUT

SHIFT
s o REGISTER

REGISTER

O b OPTION
REGISTER

SOUT
TO INTERRUPT

TO ADC
VA00413

34/75
 ST6252C ST6262B ST6262C

I/O PORTS (Cont’d)

4.1.1 Operating Modes 4.1.1.2 Interrupt Options
Each pin may be individually programmed as input All input lines can be individually connected by
or output with various configurations. software to the interrupt system by programming
This is achieved by writing the relevant bit in the the OR and DR registers accordingly. The inter-
Data (DR), Data Direction (DDR) and Option reg- rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
isters (OR). Table 11 illustrates the various port
configurations which can be selected by user soft- scribed in the Interrupt Chapter for each port.

s )
t(
ware. 4.1.1.3 Analog Input Options
4.1.1.1 Input Options
Pull-up, High Impedance Option. All input lines
Some pins can be configured as analog inputs by
programming the OR and DR registers according-
u c
can be individually programmed with or without an
internal pull-up by programming the OR and DR
ly. These analog inputs are connected to the on-
chip 8-bit Analog to Digital Converter. ONLY ONE
od
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped-
ance state.
pin should be programmed as an analog input at
any time, since by selecting more than one input
simultaneously their pins will be effectively short-
P r
ed.

t e
le
Table 11. I/O Port Option Selection
DDR
0
OR
0
DR
0
Mode
Input With pull-up, no interrupt
Option

s o
0
0
0
1
1
0
Input
Input
No pull-up, no interrupt
With pull-up and with interrupt
O b
0
1
1
0
1
X
Input
Output
Analog input (when available)

) -
Open-drain output (20mA sink when available)
1 1 X Output

t ( s
Push-pull output (20mA sink when available)

Note: X = Don’t care

u c
o d
P r
e t e
o l
b s
O

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ST6252C ST6262B ST6262C

I/O PORTS (Cont’d)

4.1.2 Safe I/O State Switching Sequence outputs, it is advisable to keep a copy of the data
Switching the I/O ports from one state to another register in RAM. Single bit instructions may then
should be done in a sequence which ensures that be used on the RAM copy, after which the whole
no unwanted side effects can occur. The recom- copy register can be written to the port data regis-
mended safe transitions are illustrated in Figure ter:
23.. All other transitions are potentially risky and

)
SET bit, datacopy
should be avoided when changing the I/O operat- LD a, datacopy
ing mode, as it is most likely that undesirable side-
effects will be experienced, such as spurious inter-
LD DRA, a

t( s
rupt generation or two pins shorted together by the
analog multiplexer.
Warning: Care must also be taken to not use in-
structions that act on a whole port register (INC,
u c
Single bit instructions (SET, RES, INC and DEC) DEC, or read operations) when all 8 bits are not
available on the device. Unavailable bits must be
od
r
should be used with great caution on Ports Data
registers, since these instructions make an implicit masked by software (AND instruction).
read and write back of the entire register. In port
input mode, however, the data register reads from
The WAIT and STOP instructions allow the
e P
the input pins directly, and not from the data regis-
ter latches. Since data register information in input
mode is used to set the characteristics of the input
le t
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
s o
sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
O b
The user must take care not to switch outputs with
heavy loads during the conversion of one of the
analog inputs in order to avoid any disturbance to
mode. In the case of inputs or of mixed inputs and the conversion.

) -
Figure 23. Diagram showing Safe I/O State Transitions

t ( s
Interrupt
pull-up 010*

u c 011
Input
Analog

Input
o d
Pr
pull-up (Reset 000 001 Input
state)

ete
Output 100 101
Output
Open Drain Open Drain

o l
s Output 110 111
Output

Ob
Push-pull Push-pull
Note *. xxx = DDR, OR, DR Bits respectively

36/75
 ST6252C ST6262B ST6262C

I/O PORTS (Cont’d)

Table 12. I/O Port Option Selections

MODE AVAILABLE ON(1) SCHEMATIC

Input
PA4-PA5
Reset state(
PB0, PB6-PB7

s )
t(
PC2-PC3
Data in
Reset state if PULL-UP PB2-PB3,
option disabled Interrupt
u c
Input PA4-PA5
od
Reset state PB0,,PB6-PB7
PC2-PC3
Data in P r
Reset state if PULL-UP
option enabled
t e
le
PB2-PB3 Interrupt

s o
Input
with pull up
PA4-PA5
PB0, PB2-PB3,PB6-PB7 b
-O
Data in
with interrupt PC2-PC3

)
Interrupt

( s
PA4-PA5
uct
d
Analog Input
PC2-PC3 ADC

r o
e P
Open drain output
5mA
l e t
PA4-PA5
PC2-PC3

s
Open drain output o Data out

b
30mA

O
PB0, PB2-PB3,PB6-PB7

PA4-PA5
Push-pull output
PC2-PC3
5mA
Data out
Push-pull output
PB0, PB2-PB3,PB6-PB7
30mA

Note 1. Provided the correct configuration has been selected.

37/75
ST6252C ST6262B ST6262C

I/O PORTS (Cont’d)

4.1.3 ARTimer alternate functions ARTIMin/PB6 is connected to the AR Timer input.
It is configured through the port registers as any
When bit PWMOE of register ARMC is low, pin standard pin of port B. To use ARTIMin/PB6 as AR
ARTIMout/PB7 is configured as any standard pin Timer input, it must be configured as input through
of port B through the port registers. When PW- DDRB.
MOE is high, ARTMout/PB7 is the PWM output, in-

)
dependently of the port registers configuration.
Figure 24. Peripheral Interface Configuration of AR Timer

t( s
PID
u c
od
r
ARTIMin

ARTIMin DR
AR TIMER

e P
PID

OR
le t
1
PWMOE

ARTIMout
s o
ARTIMout MUX
0 DR

O b
) - VR01661G

t ( s
u c
o d
P r
e t e
o l
b s
O

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 ST6252C ST6262B ST6262C

4.2 TIMER
The MCU features an on-chip Timer peripheral, The prescaler input is the internal frequency (fINT)
consisting of an 8-bit counter with a 7-bit program- divided by 12. The prescaler decrements on the
mable prescaler, giving a maximum count of 215. rising edge. Depending on the division factor pro-
Figure 25. shows the Timer Block Diagram. The grammed by PS2, PS1 and PS0 bits in the TSCR
content of the 8-bit counter can be read/written in (see Table 13.), the clock input of the timer/coun-
ter register is multiplexed to different sources. For
the Timer/Counter register, TCR, which can be ad-
dressed in Data space as a RAM location at ad- division factor 1, the clock input of the prescaler is

s )
t(
dress 0D3h. The state of the 7-bit prescaler can be also that of timer/counter; for factor 2, bit 0 of the
read in the PSC register at address 0D2h. The prescaler register is connected to the clock input of
control logic device is managed in the TSCR reg-
ister as described in the following paragraphs.
TCR. This bit changes its state at half the frequen-
cy of the prescaler input clock. For factor 4, bit 1 of
u c
The 8-bit counter is decrement by the output (ris-
the PSC is connected to the clock input of TCR,
and so forth. The prescaler initialize bit, PSI, in the
od
ing edge) coming from the 7-bit prescaler and can
be loaded and read under program control. When
it decrements to zero then the TMZ (Timer Zero)bit
TSCR register must be set to allow the prescaler
(and hence the counter) to start. If it is cleared, all
the prescaler bits are set and the counter is inhib-
P r
in the TSCR is set. If the ETI (Enable Timer Inter-
rupt) bit in the TSCR is also set, an interrupt re-
ited from counting. The prescaler can be loaded

t e
with any value between 0 and 7Fh, if bit PSI is set.
quest is generated. The Timer interrupt can be
used to exit the MCU from WAIT mode.
o
PS2/PS1/PS0 bits in the control register. le
The prescaler tap is selected by means of the

Figure 25. Timer Block Diagram

b s
Figure 26. illustrates the Timer’s working principle.

- O
DATA BUS

( s )
8 8

c t 8

du
6 8-BIT b7 b6 b5 b4 b3 b2 b1 b0
5
COUNTER
4 STATUS/CONTROL

fINT
PSC 3
2
r o
SELECT
1 OF 7
REGISTER

P
1 TMZ ETI D5 D4 PSI PS2 PS1 PS0
12
0

e
3

e t
ol
bs
INTERRUPT
LINE

O VR02070A

39/75
ST6252C ST6262B ST6262C

TIMER (Cont’d)
4.2.1 Timer Operation zero, the TMZ bit in the TSCR register is set to
The Timer prescaler is clocked by the prescaler one.
clock input (fINT ÷ 12). 4.2.3 Application Notes
The user can select the desired prescaler division TMZ is set when the counter reaches zero; howev-
ratio through the PS2, PS1, PS0 bits. When the er, it may also be set by writing 00h in the TCR
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
s )
t(
control to perform a timer function whenever it when servicing the timer interrupt to avoid unde-

c
goes high. sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
4.2.2 Timer Interrupt
When the counter register decrements to zero with
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
d u
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request associated with Interrupt Vector
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
r o
#4 is generated. When the counter decrements to
Figure 26. Timer Working Principle
e P
le t
CLOCK BIT0 BIT1 BIT2
7-BIT PRESCALER

BIT3 BIT4 BIT5

s
BIT6o
b
-O
0 1 2 3 4 5 6 7 PS0

(s)
8-1 MULTIPLEXER PS1
PS2

BIT0 BIT1 BIT2 BIT3

c t BIT4 BIT5 BIT7

u
BIT6

d
8-BIT COUNTER

o
r
VA00186

e P
l e t
s o
O b

40/75
 ST6252C ST6262B ST6262C

TIMER (Cont’d)
A write to the TCR register will predominate over PSI=“0” both counter and prescaler are not run-
the 8-bit counter decrement to 00h function, i.e. if a ning.
write and a TCR register decrement to 00h occur Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
simultaneously, the write will take precedence, lect. These bits select the division ratio of the pres-
and the TMZ bit is not set until the 8-bit counter caler register.
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time. Table 13. Prescaler Division Factors

s )
4.2.4 Timer Registers
PS2
0
PS1
0
PS0
0
Divided by
1
ct(
Timer Status Control Register (TSCR)
Address: 0D4h — Read/Write
0
0
0
1
1
0
2
4
d u
7 0
0
1
1
0
1
0
8
16
r o
TMZ ETI D5 D4 PSI PS2 PS1 PS0 1
1
0
1
1
0
32

e
64 P
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
1 1 1

le t128

count register has decrement to zero. This bit

must be cleared by user software before starting a
Timer Counter Register (TCR)
Address: 0D3h — Read/Write
s o
new count.
Bit 6 = ETI: Enable Timer Interrup
7

O b 0

When set, enables the timer interrupt request

(vector #4). If ETI=0 the timer interrupt is disabled.
D7 D6

) -
D5 D4 D3 D2 D1 D0

If ETI=1 and TMZ=1 an interrupt request is gener-

ated.
( s
Bit 7-0 = D7-D0: Counter Bits.

t
Bit 5 = D5: Reserved
c
du
Must be set to “1”. Prescaler Register PSC
Bit 4 = D4 Address: 0D2h — Read/Write
Do not care.
r o 7 0
Bit 3 = PSI: Prescaler Initialize Bit

e P
Used to initialize the prescaler and inhibit its count-
D7 D6 D5 D4 D3 D2 D1 D0

t
ing. When PSI=“0” the prescaler is set to 7Fh and

e
ol
the counter is inhibited. When PSI=“1” the prescal- Bit 7 = D7: Always read as "0".
er is enabled to count downwards. As long as Bit 6-0 = D6-D0: Prescaler Bits.

b s
O

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ST6252C ST6262B ST6262C

4.3 AUTO-RELOAD TIMER

The Auto-Reload Timer (AR Timer) on-chip pe- the prescaler and counter contents are frozen.
ripheral consists of an 8-bit timer/counter with When TEN is set, the AR counter runs at the rate
compare and capture/reload capabilities and of a of the selected clock source. The counter is
7-bit prescaler with a clock multiplexer, enabling cleared on system reset.
the clock input to be selected as fINT, fINT/3 or an The AR counter may also be initialized by writing
external clock source. A Mode Control Register,
ARMC, two Status Control Registers, ARSC0 and
to the ARLR load register, which also causes an
immediate copy of the value to be placed in the AR
s )
t(
ARSC1, an output pin, ARTIMout, and an input counter, regardless of whether the counter is run-
pin, ARTIMin, allow the Auto-Reload Timer to be ning or not. Initialization of the counter, by either
used in 4 modes:
– Auto-reload (PWM generation),
method, will also clear the ARPSC register, where-
upon counting will start from a known value.
u c
– Output compare and reload on external event 4.3.2 Timer Operating Modes

od
(PLL),
– Input capture and output compare for time meas-
urement.
Four different operating modes are available for
the AR Timer:
Auto-reload Mode with PWM Generation. This P r
– Input capture and output compare for period
t e
mode allows a Pulse Width Modulated signal to be

le
measurement. generated on the ARTIMout pin with minimum
Core processing overhead.
The AR Timer can be used to wake the MCU from
WAIT mode either with an internal or with an exter-
nal clock. It also can be used to wake the MCU
s o
The free running 8-bit counter is fed by the pres-
caler’s output, and is incremented on every rising
from STOP mode, if used with an external clock
signal connected to the ARTIMin pin. A Load reg-
edge of the clock signal.

O b
When a counter overflow occurs, the counter is
ister allows the program to read and write the
counter on the fly.

) -
automatically reloaded with the contents of the Re-
load/Capture Register, ARCC, and ARTIMout is
4.3.1 AR Timer Description
The AR COUNTER is an 8-bit up-counter incre-
t ( s
set. When the counter reaches the value con-
tained in the compare register (ARCP), ARTIMout

c
mented on the input clock’s rising edge. The coun- is reset.
ter is loaded from the ReLoad/Capture Register,
ARRC, for auto-reload or capture operations, as
d u On overflow, the OVF flag of the ARSC0 register is
set and an overflow interrupt request is generated

o
well as for initialization. Direct access to the AR if the overflow interrupt enable bit, OVIE, in the

P r
counter is not possible; however, by reading or
writing the ARLR load register, it is possible to
read or write the counter’s contents on the fly.
Mode Control Register (ARMC), is set. The OVF
flag must be reset by the user software.
When the counter reaches the compare value, the

e t e
The AR Timer’s input clock can be either the inter-
nal clock (from the Oscillator Divider), the internal
CPF flag of the ARSC0 register is set and a com-
pare interrupt request is generated, if the Compare

o l
clock divided by 3, or the clock signal connected to
the ARTIMin pin. Selection between these clock
Interrupt enable bit, CPIE, in the Mode Control
Register (ARMC), is set. The interrupt service rou-

b s
sources is effected by suitably programming bits
CC0-CC1 of the ARSC1 register. The output of the
AR Multiplexer feeds the 7-bit programmable AR
tine may then adjust the PWM period by loading a
new value into ARCP. The CPF flag must be reset
by user software.

O
Prescaler, ARPSC, which selects one of the 8
available taps of the prescaler, as defined by
PSC0-PSC2 in the AR Mode Control Register.
The PWM signal is generated on the ARTIMout
pin (refer to the Block Diagram). The frequency of
this signal is controlled by the prescaler setting
Thus the division factor of the prescaler can be set and by the auto-reload value present in the Re-
to 2n (where n = 0, 1,..7). load/Capture register, ARRC. The duty cycle of
The clock input to the AR counter is enabled by the the PWM signal is controlled by the Compare Reg-
TEN (Timer Enable) bit in the ARMC register. ister, ARCP.
When TEN is reset, the AR counter is stopped and

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 ST6252C ST6262B ST6262C

AUTO-RELOAD TIMER (Cont’d)

Figure 27. AR Timer Block Diagram
DATA BUS
DDRB7

8
DRB7

s )
AR COMPARE

ct(
REGISTER

d u
8
r o
PB7/
ARTIMout

e P
t
CPF
COMPARE R

o le
s
8
PWMOE

f INT OVF OVF

b
-O
M
8-Bit OVIE
f INT /3 U
7-Bit
AR PRESCALER AR COUNTER LOAD

)
X TCLD

( s
ct
CC0-CC1 PS0-PS2 EIE

du
EF
AR TIMER
8
INTERRUPT

o
CPF

P r CPIE

e t e 8 8

PB6/
o l
ARTIMin

b s
SL0-SL1
AR AR

O SYNCHRO
EF
RELOAD/CAPTURE
REGISTER
LOAD
REGISTER

8 8

DATA BUS

VR01660A

43/75
ST6252C ST6262B ST6262C

AUTO-RELOAD TIMER (Cont’d)

It should be noted that the reload values will also The ARTC counter is initialized by writing to the
affect the value and the resolution of the duty cycle ARRC register and by then setting the TCLD (Tim-
of PWM output signal. To obtain a signal on ARTI- er Load) and the TEN (Timer Clock Enable) bits in
Mout, the contents of the ARCP register must be the Mode Control register, ARMC.
greater than the contents of the ARRC register. Enabling and selection of the clock source is con-
The maximum available resolution for the ARTI- trolled by the CC0, CC1, SL0 and SL1 bits in the
Mout duty cycle is: Status Control Register, ARSC1. The prescaler di-

s )
t(
Resolution = 1/[256-(ARRC)] vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
Where ARRC is the content of the Reload/Capture
register. The compare value loaded in the Com- In Auto-reload Mode, any of the three available
clock sources can be selected: Internal Clock, In-
u c
pare Register, ARCP, must be in the range from
(ARRC) to 255. ternal Clock divided by 3 or the clock signal

od
r
present on the ARTIMin pin.
Figure 28. Auto-reload Timer PWM Function

e P
COUNTER

le t
255
COMPARE
VALUE
s o
O b
RELOAD

) -
REGISTER
000

t ( s t

PWM OUTPUT tHIGH

u c
o d
Pr
t
tLOW
VR001852

e t e
s ol
O b

44/75
 ST6252C ST6262B ST6262C

AUTO-RELOAD TIMER (Cont’d)

Capture Mode with PWM Generation. In this Load on External Input. The counter operates as
mode, the AR counter operates as a free running a free running 8-bit counter fed by the prescaler.
8-bit counter fed by the prescaler output. The the count is incremented on every clock rising
counter is incremented on every clock rising edge. edge.
An 8-bit capture operation from the counter to the Each counter overflow sets the ARTIMout pin. A
ARRC register is performed on every active edge match between the counter and ARCP (Compare
on the ARTIMin pin, when enabled by Edge Con- Register) resets the ARTIMout pin and sets the

s )
t(
trol bits SL0, SL1 in the ARSC1 register. At the compare flag, CPF. A compare interrupt request is
same time, the External Flag, EF, in the ARSC0 generated if the related compare interrupt enable
register is set and an external interrupt request is
generated if the External Interrupt Enable bit, EIE,
bit, CPIE, is set. A PWM signal is generated on
ARTIMout. The CPF flag must be reset by user
u c
in the ARMC register, is set. The EF flag must be
reset by user software.
software.

od
r
Initialization of the counter is as described in the
Each ARTC overflow sets ARTIMout, while a previous paragraph. In addition, if the external AR-
match between the counter and ARCP (Compare
Register) resets ARTIMout and sets the compare
TIMin input is enabled, an active edge on the input
pin will copy the contents of the ARRC register into
e P
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit,
CPIE, is set. A PWM signal is generated on ARTI-
Notes:
le t
the counter, whether the counter is running or not.

Mout. The CPF flag must be reset by user soft-

ware. lowing:
s o
The allowed AR Timer clock sources are the fol-

The frequency of the generated signal is deter-

mined by the prescaler setting. The duty cycle is
AR Timer Mode
Auto-reload mode
O b Clock Sources
fINT, fINT/3, ARTIMin
determined by the ARCP register.
Initialization and reading of the counter are identi-
Capture mode

) -
Capture/Reset mode
fINT, fINT/3
fINT, fINT/3
cal to the auto-reload mode (see previous descrip-
tion).
t ( s
External Load mode fINT, fINT/3

Enabling and selection of clock sources is control-

led by the CC0 and CC1 bits in the AR Status Con-
u c
The clock frequency should not be modified while
the counter is counting, since the counter may be

d
trol Register, ARSC1. set to an unpredictable value. For instance, the
multiplexer setting should not be modified while

r
gramming the PS0, PS1 and PS2 bits in the
o
The prescaler division ratio is selected by pro-
the counter is counting.
ARSC1 Register.

e P
In Capture mode, the allowed clock sources are
Loading of the counter by any means (by auto-re-
load, through ARLR, ARRC or by the Core) resets

t
the internal clock and the internal clock divided by the prescaler at the same time.

used as a clock source.

o e
3; the external ARTIMin input pin should not be

l
Care should be taken when both the Capture inter-
rupt and the Overflow interrupt are used. Capture
and overflow are asynchronous. If the capture oc-

b s
Capture Mode with Reset of counter and pres-
caler, and PWM Generation. This mode is identi-
cal to the previous one, with the difference that a
curs when the Overflow Interrupt Flag, OVF, is
high (between counter overflow and the flag being
reset by software, in the interrupt routine), the Ex-
O
capture condition also resets the counter and the
prescaler, thus allowing easy measurement of the
time between two captures (for input period meas-
urement on the ARTIMin pin).
ternal Interrupt Flag, EF, may be cleared simul-
taneusly without the interrupt being taken into ac-
count.
Note: In this mode it is recommended not to The solution consists in resetting the OVF flag by
change the ARTimer counter value from FFH to writing 06h in the ARSC0 register. The value of EF
any other value by writing this value in the ARRC is not affected by this operation. If an interrupt has
register and setting the TLCD bit in the ARMC reg- occured, it will be processed when the MCU exits
ister. from the interrupt routine (the second interrupt is
latched).

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ST6252C ST6262B ST6262C

AUTO-RELOAD TIMER (Cont’d)

4.3.3 AR Timer Registers Bit 2 = OVIE: Overflow Interrupt. This bit, when
AR Mode Control Register (ARMC) set, enables the overflow interrupt request. If OVIE
is reset, the compare interrupt request is masked.
Address: D5h — Read/Write If OVIE is set and the related flag, OVF in the
Reset status: 00h ARSC0 register is also set, an interrupt request is
generated.
7 0
Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0.

s )
t(
TCLD TEN PWMOE EIE CPIE OVIE ARMC1 ARMC0 These are the operating mode control bits. The fol-
lowing bit combinations will select the various op-
The AR Mode Control Register ARMC is used to
erating modes:

u c
d
program the different operating modes of the AR ARMC1 ARMC0 Operating Mode
Timer, to enable the clock and to initialize the
o
0 0 Auto-reload Mode
counter. It can be read and written to by the Core
and it is cleared on system reset (the AR Timer is
disabled).
0

1
1

0
Capture Mode
Capture Mode with Reset
of ARTC and ARPSC
P r
Note: Care should be taken when writing to the
1 1
t e
Load on External Edge

le
ARMC register while AR Timer is running: if a Mode
PWM signal is being output while the ARMC regis-
ter is overwritten with its previous value, ARTIMout
pin remains at its previous state for a programmed
s o
AR Timer Status/Control Registers ARSC0 &
time equal to tHIGH (refer to Figure 28.). Then, a
new count starts.

O b
ARSC1. These registers contain the AR Timer sta-
tus information bits and also allow the program-

-
ming of clock sources, active edge and prescaler
multiplexer setting.

)
Bit 7 = TLCD: Timer Load Bit. This bit, when set,

s
will cause the contents of ARRC register to be ARSC0 register bits 0,1 and 2 contain the interrupt
loaded into the counter and the contents of the
prescaler register, ARPSC, are cleared in order to
initialize the timer before starting to count. This bit
(
flags of the AR Timer. These bits are read normal-

t
ly. Each one may be reset by software. Writing a

c
one does not affect the bit value.
is write-only and any attempt to read it will yield a
logical zero.
d u AR Status Control Register 0 (ARSC0)

o Address: D6h — Read/Clear

Pr
Bit 6 = TEN: Timer Clock Enable. This bit, when
set, allows the timer to count. When cleared, it will 7 0
stop the timer and freeze ARPSC and ARTSC.

e
Bit 5 = PWMOE: PWM Output Enable. This bit,

t
when set, enables the PWM output on the ARTI-

e
D7 D6 D5 D4 D3 EF CPF OVF

ol
Mout pin. When reset, the PWM output is disabled. Bits 7-3 = D7-D3: Unused
Bit 4 = EIE: External Interrupt Enable. This bit, Bit 2 = EF: External Interrupt Flag. This bit is set by

b s
when set, enables the external interrupt request.
When reset, the external interrupt request is
masked. If EIE is set and the related flag, EF, in
any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.

O
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 3 = CPIE: Compare Interrupt Enable. This bit,
Bit 1 = CPF: Compare Interrupt Flag. This bit is set
if the contents of the counter and the ARCP regis-
ter are equal. The flag is cleared by writing a zero
to the CPF bit.
when set, enables the compare interrupt request.
If CPIE is reset, the compare interrupt request is Bit 0 = OVF: Overflow Interrupt Flag. This bit is set
masked. If CPIE is set and the related flag, CPF, in by a transition of the counter from FFh to 00h
the ARSC0 register is also set, an interrupt re- (overflow). The flag is cleared by writing a zero to
quest is generated. the OVF bit.

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 ST6252C ST6262B ST6262C

AUTO-RELOAD TIMER (Cont’d)

AR Status Control Register 1(ARSC1) AR Load Register ARLR. The ARLR load register
Address: D7h — Read/Write is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
7 0 ter is not affected by system reset.
AR Load Register (ARLR)
PS2 PS1 PS0 D4 SL1 SL0 CC1 CC0
Address: DBh — Read/Write

s )
t(
Bist 7-5 = PS2-PS0: Prescaler Division Selection 7 0
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
D7 D6 D5 D4 D3 D2 D1 D0

u c
following table: Bit 7-0 = D7-D0: Load Register Data Bits. These

od
Table 14. Prescaler Division Ratio Selection
PS2 PS1 PS0 ARPSC Division Ratio
are the load register data bits.

AR Reload/Capture Register. The ARRC re- P r

0 0 0 1

t e
load/capture register is used to hold the auto-re-

le
0 0 1 2 load value which is automatically loaded into the
0 1 0 4 counter when overflow occurs.
0 1 1 8 AR Reload/Capture (ARRC)

s o
b
1 0 0 16 Address: D9h — Read/Write
1 0 1 32

-O
7 0
1 1 0 64
1 1 1 128 D7 D6 D5 D4 D3 D2 D1 D0

Bit 4 = D4: Reserved. Must be kept reset.

( s )
Bit 7-0 = D7-D0: Reload/Capture Data Bits. These

ct
Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1-
0. These bits control the edge function of the Timer are the Reload/Capture register data bits.
input pin for external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
d u AR Compare Register. The CP compare register

r
is rising edge sensitive; if set, it is falling edge sen-
sitive. o is used to hold the compare value for the compare
function.

SL1 SL0
P
Edge Detection

e
AR Compare Register (ARCP)
Address: DAh — Read/Write
X
0
0
1

l e t
Disabled
Rising Edge 7 0

o
1 1 Falling Edge
D7 D6 D5 D4 D3 D2 D1 D0

b s
Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer Bit 7-0 = D7-D0: Compare Data Bits. These are

O
through the AR Multiplexer. The programming of
the clock sources is explained in the following Table
15 :
the Compare register data bits.

Table 15. Clock Source Selection.

CC1 CC0 Clock Source
0 0 Fint
0 1 Fint Divided by 3
1 0 ARTIMin Input Clock
1 1 Reserved

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ST6252C ST6262B ST6262C

4.4 A/D CONVERTER (ADC)

The A/D converter peripheral is an 8-bit analog to sion to allow stabilisation of the A/D converter.
digital converter with analog inputs as alternate I/O This action is also needed before entering WAIT
functions (the number of which is device depend- mode, since the A/D comparator is not automati-
ent), offering 8-bit resolution with a typical conver- cally disabled in WAIT mode.
sion time of 70us (at an oscillator clock frequency During Reset, any conversion in progress is
of 8MHz).
The ADC converts the input voltage by a process
stopped, the control register is reset to 40h and the
ADC interrupt is masked (EAI=0).
s )
t(
of successive approximations, using a clock fre-
quency derived from the oscillator with a division Figure 29. ADC Block Diagram
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
u c
creased. INTERRUPT
CLOCK

od
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tion and Data registers (refer to I/O ports descrip-
Ain CONVERTER RESET
AVSS
AVDD
P r
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
t e
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si-
multaneously, to avoid device malfunction.
CONTROL REGISTER

o le
RESULT REGISTER

The ADC uses two registers in the data space: the

ADC data conversion register, ADR, which stores
8

b s 8

-O
CORE CORE
the conversion result, and the ADC control regis- CONTROL SIGNALS VA00418
ter, ADCR, used to program the ADC functions.
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
s )
4.4.1 Application Notes

(
ct
matically clears (resets to “0”) the End Of Conver- The A/D converter does not feature a sample and
sion Bit (EOC). When a conversion is complete, hold circuit. The analog voltage to be measured
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and that the data
in the ADC data conversion register is valid. Each
d u should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed

r o
conversion has to be separately initiated by writing
to the STA bit.
±1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input

P
The STA bit is continuously scanned so that, if the

e
pins to reduce input voltage variation during con-
version.

t
user sets it to “1” while a previous conversion is in When selected as an analog channel, the input pin
progress, a new conversion is started before com-

o l e
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
is internally connected to a capacitor Cad of typi-
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver-
ical “0”.

b s
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,

O
rupt is associated with interrupt vector #4 and oc-
curs when the EOC bit is set (i.e. when a conver-
sion is completed). The interrupt is masked using
ASI, of the analog voltage source is calculated us-
ing the following formula:
6.5µs = 9 x Cad x ASI
the EAI (interrupt mask) bit in the control register.
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
The power consumption of the device can be re- cluding a 50% guardband. ASI can be higher if Cad
duced by turning off the ADC peripheral. This is has been charged for a longer period by adding in-
done by setting the PDS bit in the ADC control reg- structions before the start of conversion (adding
ister to “0”. If PDS=“1”, the A/D is powered and en- more than 26 CPU cycles is pointless).
abled for conversion. This bit must be set at least
one instruction before the beginning of the conver-

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 ST6252C ST6262B ST6262C

A/D CONVERTER (Cont’d)

Since the ADC is on the same chip as the micro- the noise during the conversion. But the first con-
processor, the user should not switch heavily load- version step is performed before the execution of
ed output signals during conversion, if high preci- the WAIT when most of clocks signals are still en-
sion is required. Such switching will affect the sup- abled . The key is to synchronize the ADC start
ply voltages used as analog references. with the effective execution of the WAIT. This is
The accuracy of the conversion depends on the achieved by setting ADC SYNC option. This way,
quality of the power supplies (VDD and VSS). The ADC conversion starts in effective WAIT for maxi-
mum accuracy.
s )
t(
user must take special care to ensure a well regu-
lated reference voltage is present on the VDD and Note: With this extra option, it is mandatory to ex-
VSS pins (power supply voltage variations must be
less than 5V/ms). This implies, in particular, that a
ecute WAIT instruction just after ADC start instruc-
tion. Insertion of any extra instruction may cause
u c
suitable decoupling capacitor is used at the VDD
pin.
spurious interrupt request at ADC interrupt vector.

od
r
A/D Converter Control Register (ADCR)
The converter resolution is given by::

P
Address: 0D1h — Read/Write

V DD – V SS
---------------------------
- EAI
7

EOC STA PDS D3 D2

e
D1
t e 0

D0
256

o l
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and interrupt is disabled.
b s
Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to
“1” the A/D interrupt is enabled, when EAI=0 the

O
remain constant during conversion.
Bit 6 = EOC: End of conversion. Read Only. This
Conversion resolution can be improved if the pow-
er supply voltage (VDD) to the microcontroller is
lowered.
) -
read only bit indicates when a conversion has
been completed. This bit is automatically reset to

s
“0” when the STA bit is written. If the user is using

(
ct
In order to optimise conversion resolution, the user the interrupt option then this bit can be used as an
can configure the microcontroller in WAIT mode, interrupt pending bit. Data in the data conversion
because this mode minimises noise disturbances register are valid only when this bit is set to “1”.
and power supply variations due to output switch-
ing. Nevertheless, the WAIT instruction should be
d u
Bit 5 = STA: Start of Conversion. Write Only. Writ-
executed as soon as possible after the beginning
of the conversion, because execution of the WAIT
ro ing a “1” to this bit will start a conversion on the se-
lected channel and automatically reset to “0” the

P
EOC bit. If the bit is set again when a conversion is
instruction may cause a small variation of the VDD in progress, the present conversion is stopped and
voltage. The negative effect of this variation is min-

t
imized at the beginning of the conversion when the

e e
converter is less sensitive, rather than at the end
a new one will take place. This bit is write only, any
attempt to read it will show a logical zero.

determined.
o l
of conversion, when the less significant bits are Bit 4 = PDS: Power Down Selection. This bit acti-
vates the A/D converter if set to “1”. Writing a “0” to

b s
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In-
this bit will put the ADC in power down mode (idle
mode).

O
deed, only the ADC peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking
Bit 3-0 = D3-D0. Not used

A/D Converter Data Register (ADR)

up the microcontroller could also be done using Address: 0D0h — Read only
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect 7 0
conversion accuracy.
D7 D6 D5 D4 D3 D2 D1 D0
One extra feature is available in the ADC to get a
better accuracy. In fact, each ADC conversion has
to be followed by a WAIT instruction to minimize Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result.

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ST6252C ST6262B ST6262C

5 SOFTWARE

5.1 ST6 ARCHITECTURE

The ST6 software has been designed to fully use bits of the opcode with the byte following the op-
the hardware in the most efficient way possible code. The instructions (JP, CALL) which use the
while keeping byte usage to a minimum; in short, extended addressing mode are able to branch to
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
any address of the 4K bytes Program space.

s )
t(
register or RAM location bit of the Data space with An extended addressing mode instruction is two-
byte long.

c
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
Program Counter Relative. The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
d u
or RES instruction is processed.
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
r o
5.2 ADDRESSING MODES ative instruction. If the condition is not true, the in-

e
struction which follows the relative instruction is P
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro- t
executed. The relative addressing mode instruc-

le
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
gram space, Data space, and Stack space. Pro-
gram space contains the instructions which are to
s o
acterize the kind of the test, one bit which deter-
mines whether the branch is a forward (when it is
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and In- b
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the

O
branch (0h to Fh) which must be added or sub-
put/Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
) -
tracted to the address of the relative instruction to
obtain the address of the branch.

used to stack the return addresses for subroutines

and interrupts.
t s
Bit Direct. In the bit direct addressing mode, the

(
bit to be set or cleared is part of the opcode, and

Immediate. In the immediate addressing mode,

the operand of the instruction follows the opcode
u c
the byte following the opcode points to the ad-
dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
location. As the operand is a ROM byte, the imme-
diate addressing mode is used to access con-
o d Data space memory can be set or cleared.

Pr
stants which do not change during program execu- Bit Test & Branch. The bit test and branch ad-
tion (e.g., a constant used to initialize a loop coun- dressing mode is a combination of direct address-
ter). ing and relative addressing. The bit test and

t e
Direct. In the direct addressing mode, the address

e
branch instruction is three-byte long. The bit iden-
tification and the tested condition are included in

ol
of the byte which is processed by the instruction is the opcode byte. The address of the byte to be
stored in the location which follows the opcode. Di- tested follows immediately the opcode in the Pro-
rect addressing allows the user to directly address gram space. The third byte is the jump displace-

b s
the 256 bytes in Data Space memory with a single
two-byte instruction.
ment, which is in the range of -127 to +128. This
displacement can be determined using a label,

O
which is converted by the assembler.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in Indirect. In the indirect addressing mode, the byte
the short-direct addressing mode. In this case, the processed by the register-indirect instruction is at
instruction is only one byte and the selection of the the address pointed by the content of one of the in-
location to be processed is contained in the op- direct registers, X or Y (80h,81h). The indirect reg-
code. Short direct addressing is a subset of the di- ister is selected by the bit 4 of the opcode. A regis-
rect addressing mode. (Note that 80h and 81h are ter indirect instruction is one byte long.
also indirect registers).
Inherent. In the inherent addressing mode, all the
Extended. In the extended addressing mode, the information necessary to execute the instruction is
12-bit address needed to define the instruction is contained in the opcode. These instructions are
obtained by concatenating the four less significant one byte long.

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 ST6252C ST6262B ST6262C

5.3 INSTRUCTION SET

The ST6 core offers a set of 40 basic instructions Load & Store. These instructions use one, two or
which, when combined with nine addressing three bytes in relation with the addressing mode.
modes, yield 244 usable opcodes. They can be di- One operand is the Accumulator for LOAD and the
vided into six different types: load/store, arithme- other operand is obtained from data memory using
tic/logic, conditional branch, control instructions, one of the addressing modes.
jump/call, and bit manipulation. The following par-
agraphs describe the different types. For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
s )
All the instructions belonging to a given type are
presented in individual tables.
immediate data.

ct(
Table 16. Load & Store Instructions

d u
o
Flags

r
Instruction Addressing Mode Bytes Cycles
Z C
LD A, X
LD A, Y
Short Direct
Short Direct
1
1
4
4
Δ
Δ

e
*
* P
LD A, V
LD A, W
Short Direct
Short Direct
1
1
4
4
Δ
Δ

le t *
*
LD X, A
LD Y, A
Short Direct
Short Direct
1
1
4
4
s o Δ
Δ
*
*
LD V, A
LD W, A
LD A, rr
Short Direct
Short Direct
Direct
1
1
2
O
4
4
4
b Δ
Δ
Δ
*
*
*
LD rr, A Direct 2

) - 4 Δ
Δ
*

s
LD A, (X) Indirect 1 4 *
LD A, (Y)
LD (X), A
Indirect
Indirect

c t (
1
1
4
4
Δ
Δ
*
*
LD (Y), A
LDI A, #N
Indirect
Immediate

d u 1
2
4
4
Δ
Δ
*
*
LDI rr, #N Immediate

r o 3 4 * *

P
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
Δ. Affected
e t e
* . Not Affected

o l
b s
O

51/75
ST6252C ST6262B ST6262C

INSTRUCTION SET (Cont’d)

Arithmetic and Logic. These instructions are tent or an immediate value in relation with the ad-
used to perform the arithmetic calculations and dressing mode. In CLR, DEC, INC instructions the
logic operations. In AND, ADD, CP, SUB instruc- operand can be any of the 256 data space ad-
tions one operand is always the accumulator while dresses. In COM, RLC, SLA the operand is always
the other can be either a data space memory con- the accumulator.
Table 17. Arithmetic & Logic Instructions

s )
t(
Flags
Instruction Addressing Mode Bytes Cycles

c
Z C
Δ Δ

u
ADD A, (X) Indirect 1 4
Δ Δ

d
ADD A, (Y) Indirect 1 4
Δ Δ

o
ADD A, rr Direct 2 4
ADDI A, #N
AND A, (X)
AND A, (Y)
Immediate
Indirect
Indirect
2
1
1
4
4
4
Δ
Δ
Δ
Δ
Δ
Δ P r
AND A, rr Direct 2 4 Δ Δ
t e
ANDI A, #N
CLR A
Immediate
Short Direct
2
2
4
4
Δ
Δ

o le
Δ
Δ
CLR r
COM A
Direct
Inherent
3
1
4
4
*
Δ
Δ b s *
Δ
Δ

O
CP A, (X) Indirect 1 4
Δ Δ

-
CP A, (Y) Indirect 1 4
CP A, rr Direct 2 4 Δ Δ
CPI A, #N Immediate 2

( s
4
) Δ
Δ
Δ

t
DEC X Short Direct 1 4 *
DEC Y
DEC V
Short Direct
Short Direct

u
1
1
c 4
4
Δ
Δ
*
*
DEC W
DEC A
Short Direct
Direct
o d 1
2
4
4
Δ
Δ
*
*
DEC rr
DEC (X)
Direct
Indirect
P r 2
1
4
4
Δ
Δ
*
*
DEC (Y)
INC X
Indirect

e t
Short Direct
e 1
1
4
4
Δ
Δ
*
*
INC Y
INC V
o l
Short Direct
Short Direct
1
1
4
4
Δ
Δ
*
*
INC W
INC A
b s Short Direct
Direct
1
2
4
4
Δ
Δ
*
*
INC rr
INC (X)
INC (Y)
O Direct
Indirect
Indirect
2
1
1
4
4
4
Δ
Δ
Δ
*
*
*
RLC A Inherent 1 4 Δ Δ
SLA A Inherent 2 4 Δ Δ
SUB A, (X) Indirect 1 4 Δ Δ
D

SUB A, (Y) Indirect 1 4 Δ

SUB A, rr Direct 2 4 Δ Δ
SUBI A, #N Immediate 2 4 Δ Δ
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data space register

52/75
 ST6252C ST6262B ST6262C

INSTRUCTION SET (Cont’d)

Conditional Branch. The branch instructions Control Instructions. The control instructions
achieve a branch in the program when the select- control the MCU operations during program exe-
ed condition is met. cution.
Bit Manipulation Instructions. These instruc- Jump and Call. These two instructions are used
tions can handle any bit in data space memory. to perform long (12-bit) jumps or subroutines call
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
inside the whole program space.

s )
t(
branch operations.
Table 18. Conditional Branch Instructions
Flags
u c
d
Instruction Branch If Bytes Cycles
Z C
JRC e
JRNC e
C=1
C=0
1
1
2
2
*
*
*
*
r o
JRZ e Z=1 1 2 * *

e P
t
JRNZ e Z=0 1 2 * *
Δ

le
JRR b, rr, ee Bit = 0 3 5 *
JRS b, rr, ee Bit = 1 3 5 * Δ
Notes:
b. 3-bit address rr. Data space register
s o
e. 5 bit signed displacement in the range -15 to +16<F128M>
ee. 8 bit signed displacement in the range -126 to +129

Table 19. Bit Manipulation Instructions

* . Not Affected

O b
Δ . Affected. The tested bit is shifted into carry.

Instruction Addressing Mode Bytes Cycles

) - Flags

s
Z C
SET b,rr
RES b,rr
Bit Direct
Bit Direct
2
2

c t ( 4
4
*
*
*
*

du
Notes:
b. 3-bit address; * . Not<M> Affected
rr. Data space register;

Table 20. Control Instructions

r o
Instruction Addressing Mode

e P Bytes Cycles
Z
Flags
C
NOP

e t
Inherent 1 2 * *

ol
RET Inherent 1 2 * *
RETI Inherent 1 2 Δ Δ
STOP (1)
WAIT
b s Inherent
Inherent
1
1
2
2
*
*
*
*
Notes:
1.

*.
O
This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
Δ . Affected
Not Affected

Table 21. Jump & Call Instructions

Instruction Flags
Addressing Mode Bytes Cycles
Z C
CALL abc Extended 2 4 * *
JP abc Extended 2 4 * *
Notes:
abc. 12-bit address;
* . Not Affected

53/75
ST6252C ST6262B ST6262C

Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW LOW
0 1 2 3 4 5 6 7
0000 0001 0010 0011 0100 0101 0110 0111
HI HI
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD
0 0
e abc e b0,rr,ee e # e a,(x)
0000 0000
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

)
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI
1 1
e abc e b0,rr,ee e x e a,nn
0001
1
2
pcr
JRNZ
2
4
ext
CALL
1
2
pcr
JRNC
3
5
bt
JRR
1
2
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
CP
0001

t( s
c
2 2
e abc e b4,rr,ee e # e a,(x)
0010 0010

3
1
2
pcr
JRNZ
2
4
ext
CALL
1
2
pcr
JRNC
3
5
bt
JRS
1
2
pcr
JRZ 4
1
LD 2
prc 1
JRC 4
ind
CPI
3
d u
o
e abc e b4,rr,ee e a,x e a,nn
0011 0011

4
0100
1
2
e
pcr
JRNZ
2
4
abc
ext
CALL
1
2
e
pcr
JRNC
3
5
bt
JRR
b2,rr,ee
1
2
e
pcr 1
JRZ
#
sd 1
2
e
prc 2
JRC 4
a,(x)
imm
ADD
4
0100
P r
e
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

5
0101
2

1
e
JRNZ

pcr
4

2
CALL
abc
ext
2

1
e
JRNC

pcr
5

3
JRS
b2,rr,ee
bt
2

1
e
JRZ 4

pcr 1
y
INC 2

sd 1
e
JRC 4

prc 2
a,nn
ADDI

imm
le t 5
0101

so
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC
6 6
e abc e b6,rr,ee e # e (x)
0110 0110

Ob
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC
7 7
e abc e b6,rr,ee e a,y e #
0111 0111

)-
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD
8 8
e abc e b1,rr,ee e # e (x),a
1000
1
2 RNZ
pcr 2
4
ext
CALL
1
2
pcr
JRNC
3
5
bt
JRS
1
2

t ( s
pcr
JRZ 4
1
INC 2
prc 1
JRC
ind
1000

c
9 9
e abc e b1,rr,ee e v e #
1001 1001

du
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND
A A
e abc e b5,rr,ee e # e a,(x)
1010
1
2
pcr
JRNZ
2
4
ext
CALL
1
2
r
pcr
JRNC o 3
5
bt
JRS
1
2
pcr
JRZ 4
1
LD 2
prc 1
JRC 4
ind
ANDI
1010

B
1011
1
e
pcr 2
abc

e
ext 1
e
Ppcr 3
b5,rr,ee
bt 1
e
pcr 1
a,v
sd 1
e
prc 2
a,nn
imm
B
1011

C
1100
2

1
e
JRNZ

pcr
4

2
l e
abc
t
CALL

ext
2

1
e
JRNC

pcr
5

3
JRR
b3,rr,ee
bt
2

1
e
JRZ

pcr
#
2

1
e
JRC 4

prc 1
a,(x)
SUB

ind
C
1100

so
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI
D D
e abc e b3,rr,ee e w e a,nn
1101 1101

Ob
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC
E E
e abc e b7,rr,ee e # e (x)
1110 1110
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC
F F
e abc e b7,rr,ee e a,w e #
1111 1111
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates Illegal Instructions Cycle
sd Short Direct e 5 Bit Displacement 2 JRC Mnemonic
imm Immediate b 3 Bit Address Operand e
inh Inherent rr 1byte dataspace address
Bytes 1 prc
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
Addressing Mode
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect

54/75
 ST6252C ST6262B ST6262C

Opcode Map Summary (Continued)

LOW LOW
8 9 A B C D E F
1000 1001 1010 1011 1100 1101 1110 1111
HI HI
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD
0 0
e abc e b0,rr e rr,nn e a,(y)
0000 0000
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind

)
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD
1 1
e abc e b0,rr e x e a,rr
0001
1
2
pcr
JRNZ
2
4
ext 1
JP 2
pcr
JRNC
2
4
b.d
RES
1
2
pcr 1
JRZ 4 COM
sd 1
2
prc 2
JRC 4
dir
CP
0001

t( s
c
2 2
e abc e b4,rr e a e a,(y)
0010 0010

3
1
2
pcr
JRNZ
2
4
ext 1
JP 2
pcr
JRNC
2
4
b.d
SET
1
2
pcr
JRZ 4
1
LD 2
prc 1
JRC 4
ind
CP
3
d u
o
e abc e b4,rr e x,a e a,rr
0011 0011

4
0100
1
2
e
pcr
JRNZ
2
4
abc
ext 1
JP 2
e
pcr
JRNC
2
4
b.d
RES
b2,rr
1
2
e
pcr 1
JRZ 2
sd 1
RETI 2
e
prc 2
JRC 4
a,(y)
ADD
dir

4
0100
P r
e
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

5
0101
2

1
e
JRNZ

pcr
4

2
abc
JP 2

ext 1
e
JRNC

pcr
4

2
b2,rr
SET

b.d
2

1
e
JRZ 4

pcr 1
y
DEC 2

sd 1
e
JRC 4

prc 2
a,rr
ADD

le
dir t 5
0101

so
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC
6 6
e abc e b6,rr e e (y)
0110 0110

Ob
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC
7 7
e abc e b6,rr e y,a e rr
0111 0111

)-
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD
8 8
e abc e b1,rr e # e (y),a
1000
1
2 RNZ
pcr 2
4
ext 1
JP 2
pcr
JRNC
2
4
b.d
SET
1
2

t ( s
pcr
JRZ 4
1
DEC 2
prc 1
JRC 4
ind
LD
1000

c
9 9
e abc e b1,rr e v e rr,a
1001 1001

A
1
2
e
pcr
JRNZ
2
4
abc
ext 1
JP 2
e
pcr
JRNC
2
4

d u b.d
RES
b5,rr
1
2
e
pcr 1
JRZ 4
a
sd 1
RCL 2
e
prc 2
JRC 4
a,(y)
AND
dir

A
1010

o 1010

Pr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND
B B
e abc e b5,rr e v,a e a,rr
1011 1011

e
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

C
1100
2

1
e
JRNZ

pcr
4

2
l e
abc
t JP 2

ext 1
e
JRNC

pcr
4

2
RES
b3,rr
b.d
2

1
e
JRZ 2

pcr 1
RET 2

inh 1
e
JRC 4

prc 1
a,(y)
SUB

ind
C
1100

so
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB
D D
e abc e b3,rr e w e a,rr
1101 1101

Ob
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC
E E
e abc e b7,rr e e (y)
1110 1110
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC
F F
e abc e b7,rr e w,a e rr
1111 1111
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates Illegal Instructions Cycle
sd Short Direct e 5 Bit Displacement 2 JRC Mnemonic
imm Immediate b 3 Bit Address Operand e
inh Inherent rr 1byte dataspace address
Bytes 1 prc
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
Addressing Mode
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect

55/75
ST6252C ST6262B ST6262C

6 ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices to protect the inputs Power Considerations.The average chip-junc-
against damage due to high static voltages, how- tion temperature, Tj, in Celsius can be obtained
ever it is advisable to take normal precaution to from:
avoid application of any voltage higher than the
specified maximum rated voltages.
Tj=TA + PD x RthJA

s )
t(
Where:TA = Ambient Temperature.
For proper operation it is recommended that VI
and VO be higher than VSS and lower than VDD.
Reliability is enhanced if unused inputs are con-
RthJA =Package thermal resistance (junc-
tion-to ambient).
u c
nected to an appropriate logic voltage level (VDD
or VSS).
PD = Pint + Pport.

od
r
Pint =IDD x VDD (chip internal power).

P
Pport =Port power dissipation (determined
by the user).

Symbol Parameter Value

t eUnit
VDD Supply Voltage -0.3 to 7.0
le V

so
VI Input Voltage VSS - 0.3 to VDD + 0.3(1) V
VO Output Voltage VSS - 0.3 to VDD + 0.3(1) V
IVDD
IVSS
Total Current into VDD (source)
Total Current out of VSS (sink)
O b 80
100
mA
mA
Tj Junction Temperature
- 150 °C

(s)
TSTG Storage Temperature -60 to 150 °C

Notes:

c t
- Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and

u
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

current is kept within the specification.

o d
- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection

P r
e t e
o l
b s
O

56/75
 ST6252C ST6262B ST6262C

6.2 RECOMMENDED OPERATING CONDITIONS

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
6 Suffix Version -40 85
TA Operating Temperature 1 Suffix Version 0 70 °C
3 Suffix Version -40 125

Operating Supply Voltage

fOSC = 4MHz, 1 & 6 Suffix
fOSC = 4MHz, 3 Suffix
3.0
3.0
6.0
6.0
s )
t(
V
(Except ST626xB ROM devices) fosc= 8MHz , 1 & 6 Suffix 3.6 6.0

c
fosc= 8MHz , 3 Suffix 4.5 6.0
VDD
Operating Supply Voltage
fOSC = 4MHz, 1 & 6 Suffix
fOSC = 4MHz, 3 Suffix
fosc= 8MHz , 1 & 6 Suffix
3.0
3.0
4.0
6.0
6.0
6.0
V
d u
o
(ST626xB ROM devices)

r
fosc= 8MHz , 3 Suffix 4.5 6.0

P
VDD = 3.0V, 1 & 6 Suffix 0 4.0
Oscillator Frequency2) VDD = 3.0V , 3 Suffix 0 4.0
MHz
(Except ST626xB ROM devices) VDD = 3.6V , 1 & 6 Suffix
VDD = 3.6V , 3 Suffix
0
0
8.0
4.0
t e
le
fOSC
VDD = 3.0V, 1 & 6 Suffix 0 4.0
Oscillator Frequency2)

so
VDD = 3.0V , 3 Suffix 0 4.0
MHz
(ST626xB ROM devices) VDD = 4.0V , 1 & 6 Suffix 0 8.0
VDD = 4.0V , 3 Suffix 0 4.0

Ob
IINJ+ Pin Injection Current (positive) VDD = 4.5 to 5.5V +5 mA
IINJ- Pin Injection Current (negative) VDD = 4.5 to 5.5V -5 mA
Notes:

) -
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the

(s
A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommended.

t
2.An oscillator frequency above 1MHz is recommended for reliable A/D results

c
Figure 30. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)

u
Maximum FREQUENCY (MHz)

o d
8
P
FUNCTIONALITY IS NOT
r
1 & 6 Suffix version

e 1 & 6 Suffix 3 Suffix version

t
7 GUARANTEED IN
version

e
THIS AREA
6

o l
s
5

O b 4

3
3 Suffix version

1
2.5 3 3.6 4 4.5 5 5.5 6

SUPPLY VOLTAGE (VDD)

All devices except ST626xB ROM devices

ST626xB ROM devices

The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.

57/75
ST6252C ST6262B ST6262C

6.3 DC ELECTRICAL CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VIL Input Low Level Voltage
VDD x 0.3 V
VIH
All Input pins
Input High Level Voltage
s )
t(
VDD x 0.7 V
All Input pins

VHys
Hysteresis Voltage (1)
All Input pins
VDD= 5V
VDD= 3V
0.2
0.2
V

u c
Vup LVD Threshold in power-on 4.1 4.3

od
Vdn LVD threshold in powerdown
Low Level Output Voltage
All Output pins
VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = + 3mA
3.5 3.8
0.1
0.8
P r
VOL
Low Level Output Voltage
VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = +7mA
0.1
0.8
t
V
e
le
30 mA Sink I/O pins
VDD= 5.0V; IOL = +15mA 1.3

so
High Level Output Voltage VDD= 5.0V; IOH = -10µA 4.9
VOH V
All Output pins VDD= 5.0V; IOH = -3.0mA 3.5

Ob
All Input pins 40 100 350
RPU Pull-up Resistance ΚΩ
RESET pin 150 350 900
Input Leakage Current VIN = VSS (No Pull-Up configured)

)-
0.1 1.0
IIL All Input pins but RESET VIN = VDD
μA
IIH Input Leakage Current VIN = VSS -8 -16 -30
RESET pin
Supply Current in RESET
VIN = VDD
VRESET=VSS
t ( s 10
7 mA
Mode fOSC=8MHz
c
du
Supply Current in
VDD=5.0V fINT=8MHz 7 mA
RUN Mode (2)

ro
Supply Current in WAIT
IDD VDD=5.0V fINT=8MHz 2.5 mA
Mode (3)
Supply Current in STOP
P
ILOAD=0mA
Mode, with LVD disabled(3) VDD=5.0V

e
20 μA

let
Supply Current in STOP ILOAD=0mA
500
Mode, with LVD enabled(3) VDD=5.0V
Retention EPROM Data Retention TA = 55°C 10 years

Notes:
s o
O b
(1) Hysteresis voltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by

58/75
 ST6252C ST6262B ST6262C

DC ELECTRICAL CHARACTERISTICS (Cont’d)

(TA = -40 to +85°C unless otherwise specified))

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
Vup LVD Threshold in power-on Vdn +50 mV 4.1 4.3 V

)
Vdn LVD threshold in powerdown 3.6 3.8 Vup -50 mV V
Low Level Output Voltage
All Output pins
VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = + 5mA
VDD= 5.0V; IOL = + 10mAv
0.1
0.8
1.2
t( s
VOL
Low Level Output Voltage
VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = +10mA
0.1
0.8
V

u c
30 mA Sink I/O pins VDD= 5.0V; IOL = +20mA
VDD= 5.0V; IOL = +30mA
1.3
2.0
od
VOH
High Level Output Voltage
All Output pins
Supply Current in STOP
VDD= 5.0V; IOH = -10µA
VDD= 5.0V; IOH = -5.0mA
ILOAD=0mA
4.9
3.5
V

P r
IDD
Mode, with LVD disabled(*) VDD=5.0V
10

t e
μA

Note:
(*) All Peripherals in stand-by.
o le
6.4 AC ELECTRICAL CHARACTERISTICS
b s
(TA = -40 to +125°C unless otherwise specified)

- O Value
Symbol Parameter

Supply Recovery Time (1)

Test Conditions

( s ) Min. Typ. Max.

Unit

t
tREC 100 ms

TWEE EEPROM Write Time

TA = 25°C

u
TA = 85°C
TA = 125°C c 5
10
20
10
20
30
ms

Endurance
EEPROM WRITE/ERASE Cycle
o d
QA LOT Acceptance (25°C) 300,000 1 million cycles

Pr
(2)

Retention EEPROM Data Retention TA = 55°C 10 years

fLFAO Internal frequency with LFAO active 200 400 800 kHz

e t e VDD = 3V 1

ol
Internal Frequency with OSG VDD = 3.6V 1
fOSG fOSC MHz
enabled2) VDD = 4.5V 2
VDD = 6V 2

bs
VDD=5.0V (Except 626xB ROM)
R=47kΩ 4 5 5.8 MHz

fRC O Internal frequency with RC oscilla-

tor and OSG disabled2) 3)
R=100kΩ
R=470kΩ
VDD=5.0V (626xB ROM)
R=10kΩ
2.7
800

6.3
3.2
850

8.2
3.5
900

9.8
MHz
kHz

MHz
R=27kΩ 4.7 5.9 7 MHz
R=67kΩ 2.8 3.6 4.3 MHz
R=100kΩ 2.2 2.8 3.4 MHz
CIN Input Capacitance All Inputs Pins 10 pF
COUT Output Capacitance All Outputs Pins 10 pF

Notes:
1. Period for which VDD has to be connected at 0V to allow internal Reset function at next power-up.
2 An oscillator frequency above 1MHz is recommended for reliable A/D results.
3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.

59/75
ST6252C ST6262B ST6262C

6.5 A/D CONVERTER CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
Res Resolution 8 Bit
ATOT Total Accuracy (1) (2) fOSC > 1.2MHz
fOSC > 32kHz
±2
±4
LSB

s )
t(
fOSC = 8MHz (TA < 85°C) 70
tC Conversion Time μs

c
fOSC = 4 MHz 140

u
Conversion result when
ZIR Zero Input Reading 00 Hex
VIN = VSS
FSR Full Scale Reading
Conversion result when
FF Hex
od
r
VIN = VDD
Analog Input Current During
ADI
ACIN
Conversion
Analog Input Capacitance
VDD= 4.5V
2
1.0
5
μA
pF
e P
Notes:

le t
o
1. Noise at VDD, VSS <10mV
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.

6.6 TIMER CHARACTERISTICS

b s
(TA = -40 to +125°C unless otherwise specified)

- O
Symbol Parameter Test Conditions

( s )Min.
Value
Typ. Max.
Unit

fIN Input Frequency on TIMER Pin

c t f INT-
--------- MHz

tW Pulse Width at TIMER Pin

d u VDD = 3.0V 1
4
μs

r o VDD >4.5V 125 ns

6.7 SPI CHARACTERISTICS

e P
Symbol
l e t
(TA = -40 to +125°C unless otherwise specified)

Parameter Test Conditions

Value
Unit

o Min. Typ. Max.

bs
FCL Clock Frequency Applied on Scl 500 kHz
tSU Set-up Time Applied on Sin 250 ns

O
th Hold Time Applied onSin 50 ns

6.8 ARTIMER ELECTRICAL CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min Typ Max

RUN and WAIT Modes

fIN Input Frequency on ARTIMin Pin MHz

STOP mode 2

60/75
 ST6252C ST6262B ST6262C

Figure 31. Vol versus Iol on all I/O port at Vdd=5V

6 T = -40°C
Vol (V)

T = 25°C
4
T = 95°C

s )
t(
2 T = 125°C

0
u c
0 10 20
Iol (mA)
30 40

od
This curves represents typical variations and is given for guidance only
P r
Figure 32. Vol versus Iol on all I/O port at T=25°C
t e
o le
8
6
b s Vdd = 3.0V

O
Vol (V)

Vdd = 4.0V
4

) - Vdd = 5.0V
2
0
t ( s Vdd = 6.0V

0 10 20

u
Iol (mA) c 30 40

o d
r
This curves represents typical variations and is given for guidance only

P
Figure 33. Vol versus Iol for High sink (30mA) I/Oports at T=25°C

e
5
l e t
4
s o
b Vdd = 3.0V
Vol (V)

O
2
1
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V

0
0 10 20 30 40
Iol (mA)
This curves represents typical variations and is given for guidance only

61/75
ST6252C ST6262B ST6262C

Figure 34. Vol versus Iol for High sink (30mA) I/O ports at Vdd=5V

5
4
T = -40°C
Vol (V)

3 T = 25°C
2 T = 95°C

s )
t(
T = 125°C
1
0
u c
0 10 20
Iol (mA)
30 40

od
This curves represents typical variations and is given for guidance only
P r
Figure 35. Voh versus Ioh on all I/O port at 25°C
t e
o le
6
4
b s
Vdd = 3.0V

O
Voh (V)

Vdd = 4.0V
2

) - Vdd = 5.0V

s
0 Vdd = 6.0V
-2
0 10 20
c t ( 30 40

d
Ioh (mA)
u
r o
This curves represents typical variations and is given for guidance only

P
Figure 36. Voh versus Ioh on all I/O port at Vdd=5V

e
6

l e t
4

s o T = -40°C
Voh (V)

T = 25°C

O b2

0
T = 95°C
T = 125°C

-2
0 10 20 30 40
Ioh (mA)

This curves represents typical variations and is given for guidance only

62/75
 ST6252C ST6262B ST6262C

Figure 37. Idd WAIT versus VDD at 8 Mhz for OTP devices

2.5
Idd WAIT (mA)

2 T = -40°C
1.5 T = 25°C
1 T = 95°C
T = 125°C
s )
t(
0.5

c
0
3V 4V
Vdd
5V 6V

d u
This curves represents typical variations and is given for guidance only
r o
Figure 38. Idd STOP versus VDD for OTP devices

e P
8
le t
Idd STOP (µA)

6
4
s o
T = -40°C
T = 25°C
2

O b T = 95°C

-
0 T = 125°C
-2
)
t(s
3V 4V 5V 6V
Vdd

u c
This curves represents typical variations and is given for guidance only

Figure 39. Idd STOP versus VDD for ROM devices

o d
2
P r
1.5

e t e
Idd STOP (µA)

ol
T = -40°C
1
T = 25°C

b s
0.5 T = 95°C
T = 125°C
O 0

-0.5
3V 4V 5V 6V
Vdd
This curves represents typical variations and is given for guidance only

63/75
ST6252C ST6262B ST6262C

Figure 40. Idd WAIT versus VDD at 8Mhz for ROM devices

2.5
Idd WAIT (mA)

2 T = -40°C
1.5 T = 25°C
1 T = 95°C

s )
t(
0.5 T = 125°C
0
3V 4V 5V 6V
u c
Vdd

od
This curves represents typical variations and is given for guidance only

Figure 41. Idd RUN versus VDD at 8 Mhz for ROM and OTP devices
P r
t e
le
8

6
s o
Idd RUN (mA)

T = -40°C
b T = 25°C

-O
4
T = 95°C

( s ) T = 125°C

0
ct
du
3V 4V 5V 6V
Vdd
This curves represents typical variations and is given for guidance only
r o
Figure 42. LVD thresholds versus temperature

e P
4.2

e t
s ol
4.1

O b
Vthresh.

4
Vup
Vdn
3.9

3.8

3.7
-40°C 25°C 95°C 125°C
Temp
This curves represents typical variations and is given for guidance only

64/75
 ST6252C ST6262B ST6262C

Figure 43. RC frequency versus VDD for ROM ST626xB only

10

R=1OK

R=27K
)
Frequency

s
MHz

R=67K

ct(
R=100K

d u
1
r o
3 4 5 6

e P
VDD (volts)]

This curves represents typical variations and is given for guidance only
le t
Figure 44. RC frequency versus VDD (Except for ST626xB ROM devices)
s o
10
O b
) -
t ( s
Frequency

R=47K

c
MHz

R=100K

u
1

o d R=470K

P r
e
let
0.1
3 3.5 4 4.5 5 5.5 6
VDD (volts)

s o
This curves represents typical variations and is given for guidance only

O b

65/75
ST6252C ST6262B ST6262C

7 PACKAGE MECHANICAL DATA

In order to meet environmental requirements, ST tions, grade definitions and product status are
offers these devices in different grades of ECO- available at: www.st.com. ECOPACK® is an ST
PACK® packages, depending on their level of en- trademark.
vironmental compliance. ECOPACK® specifica-
Figure 45. 16-Pin Plastic Dual In-Line Package, 300-mil Width

s )
t(
mm inches
Dim.

c
E
Min Typ Max Min Typ Max

A1
A2 A
A
A1 0.38
5.33
0.015
0.210

d u
A2
b
2.92
0.36
3.30
0.46
4.95 0.115 0.130 0.195
0.56 0.014 0.018 0.022
r o
P
L c
E1 b2 1.14 1.52 1.78 0.045 0.060 0.070

e
b2 b eB
b3 0.76 0.99 1.14 0.030 0.039 0.045

t
D1 b3 e
c 0.20 0.25 0.36 0.008 0.010 0.014
D D

le
18.67 19.18 19.69 0.735 0.755 0.775

so
D1 0.13 0.005
e 2.54 0.100

Ob
E 7.62 7.87 8.26 0.300 0.310 0.325
E1 6.10 6.35 7.11 0.240 0.250 0.280

)-
L 2.92 3.30 3.81 0.115 0.130 0.150
eB 10.92 0.430

t ( s N
Number of Pins
16

u
Figure 46. 16-Pin Ceramic Side-Brazed Dual In-Line Package c
o d
Pr
mm inches
Dim.
Min Typ Max Min Typ Max

e
A 3.78 0.149

e t A1 0.38 0.015

ol
B 0.36 0.46 0.56 0.014 0.018 0.022
B1 1.14 1.37 1.78 0.045 0.054 0.070

b s C
D
0.20 0.25 0.36 0.008 0.010 0.014
19.86 20.32 20.78 0.782 0.800 0.818

O
D1 17.78 0.700
E1 7.04 7.49 7.95 0.277 0.295 0.313
e 2.54 0.100
G 6.35 6.60 6.86 0.250 0.260 0.270
G1 9.47 9.73 9.98 0.373 0.383 0.393
G2 1.02 0.040
L 2.92 3.30 3.81 0.115 0.130 0.150
S 1.27 0.050
CDIP16W
Ø 4.22 0.166
Number of Pins
N 16

66/75
 ST6252C ST6262B ST6262C

PACKAGE MECHANICAL DATA (Cont’d)

Figure 47. 16-Pin Plastic Small Outline Package, 300-mil Width

D h x 45× mm inches
Dim.
Min Typ Max Min Typ Max

)
L

A1
A

a
C
A
A1
2.35
0.10
2.65 0.093
0.30 0.004
0.104
0.012

t( s
B e B
C
0.33
0.23
0.51 0.013
0.32 0.009
0.020
0.013
u c
D 10.10 10.50 0.398 0.413

od
r
E 7.40 7.60 0.291 0.299
H 10.00 10.65 0.394 0.419
e
h 0.25
1.27
0.75 0.010
0.050

e 0.030 P
E H α
L
0°
0.40
8°
1.27 0.016
0°

le t 8°
0.050

N
s o
Number of Pins
16

O b
) -
Figure 48. 16-Pin Plastic Shrink Small Outline Package
t ( s
uc
o d mm inches

Pr
D Dim.
L Min Typ Max Min Typ Max

A2
A 2.00 0.079
A c
A1

e
A1 0.05 0.002
b
e

e t h A2 1.65 1.75 1.85 0.065 0.069 0.073

ol
b 0.22 0.38 0.009 0.015
c 0.09 0.25 0.004 0.010

b s D
E
5.90
7.40
6.20
7.80
6.50 0.232 0.244 0.256
8.20 0.291 0.307 0.323

O
E1 5.00 5.30 5.60 0.197 0.209 0.220
e 0.65 0.026
E1 E
θ 0° 4° 8° 0° 4° 8°
L 0.55 0.75 0.95 0.022 0.030 0.037
Number of Pins
N 16

67/75
ST6252C ST6262B ST6262C

THERMAL CHARACTERISTICS
Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
PDIP16 55
RthJA Thermal Resistance °C/W
PSO16 75

s )
ct(
d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

68/75
 ST6252C ST6262B ST6262C

8 ORDERING INFORMATION

8.1 OTP/EPROM versions

Table 22. OTP/EPROM version ordering information

Program
Sales Type EEPROM (Bytes) Temperature range Package

ST62E62CF1
Memory (Bytes)
1836 EPROM 64 0 to +70°C CDIP16W
s )
ST62T52CM6
ST62T52CM3
1836 OTP None
-40 to + 85°C
-40 to + 125°C
PSO16

ct(
ST62T62CM6
ST62T62CM3
1836 OTP 64
-40 to + 85°C
-40 to + 125°C
PSO16

d u
ST62T52CB6
ST62T52CB3
1836 OTP None
-40 to + 85°C
-40 to + 125°C
PDIP16
r o
ST62T62CB6
ST62T62CB3
1836 OTP 64
-40 to + 85°C
-40 to + 125°C
PDIP16

e P
ST62T52CN6
ST62T52CN3
1836 OTP None
-40 to + 85°C
-40 to + 125°C t
SSOP16

le
so
ST62T62CN6 -40 to + 85°C
1836 OTP 64 SSOP16
ST62T62CN3 -40 to + 125°C

8.1.1 IMPORTANT NOTE

O b
For OTP devices, data retention and programmability must be guaranteed by a screening procedure. Re-
fer to Application Note AN886.

) -
8.2 FASTROM versions

( s
Table 23. FASTROM version ordering information
ct
du
Sales Type ROM EEPROM (Bytes) Temperature range Package
ST62P52CM1/XXX 0 to +70°C

ro
ST62P52CM6/XXX 1836 Bytes None -40 to + 85°C
ST62P52CM3/XXX (*) -40 to + 125°C
ST62P62CM1/XXX
ST62P62CM6/XXX

e P
1836 Bytes 64
0 to +70°C
-40 to + 85°C
PSO16

ST62P62CM3/XXX (*)
ST62P52CB1/XXX

l e t -40 to + 125°C
0 to +70°C

o
ST62P52CB6/XXX 1836 Bytes None -40 to + 85°C

bs
ST62P52CB3/XXX (*) -40 to + 125°C
PDIP16
ST62P62CB1/XXX 0 to +70°C
ST62P62CB6/XXX 1836 Bytes 64 -40 to + 85°C

O
ST62P62CB3/XXX (*)
ST62P52CN1/XXX
ST62P52CN6/XXX
ST62P52CN3/XXX (*)
1836 Bytes None
-40 to + 125°C
0 to +70°C
-40 to + 85°C
-40 to + 125°C
SSOP16
ST62P62CN1/XXX 0 to +70°C
ST62P62CN6/XXX 1836 Bytes 64 -40 to + 85°C
ST62P62CN3/XXX (*) -40 to + 125°C

(*) Advanced information

The ST62P52C and ST62P62C are the Factory They offer the same functionality as OTP devices,
Advanced Service Technique ROM (FASTROM) selecting as FASTROM options the options de-
version of ST62T52C and ST62T62C OTP devic- fined in the programmable option byte of the OTP
es. version.

69/75
ST6252C ST6262B ST6262C

The following section deals with the procedure for the customer who must thoroughly check, com-
transfer of customer codes to STMicroelectronics. plete, sign and return it to STMicroelectronics. The
8.2.1 Transfer of Customer Code signed listing forms a part of the contractual agree-
ment for the production of the specific customer
Customer code is made up of the ROM contents MCU.
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
by electronic means, with the hexadecimal file
generated by the development tool. All unused tractual points.

s )
t(
bytes must be set to FFh. Table 24. ROM Memory Map ST62P52C/P62C
The selected options are communicated to STMi-
croelectronics using the correctly filled OPTION
Device Address Description

u c
LIST appended. See page 73. 0000h-087Fh
0880h-0F9Fh
Reserved
User ROM

od
r
8.2.2 Listing Generation and Verification 0FA0h-0FEFh Reserved
0FF0h-0FF7h Interrupt Vectors
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
0FF8h-0FFBh
0FFCh-0FFDh
Reserved

e
NMI Interrupt Vector P
from it. This listing refers exactly to the ROM con-
tents and options which will be used to produce
the specified MCU. The listing is then returned to
0FFEh-0FFFh
t
Reset Vector

le
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

70/75
 ST6252C ST6262B ST6262C

8.3 ROM versions

Table 25. ROM version ordering information

Sales Type ROM EEPROM (Bytes) Temperature Range Package
ST6252CB1/XXX 0 to +70°C
ST6252CB6/XXX -40 to + 85°C PDIP16

)
ST6252CB3/XXX -40 to + 125°C
ST6252CM1/XXX
ST6252CM6/XXX
ST6252CM3/XXX
1836 Bytes None
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PSO16

t( s
ST6252CN1/XXX
ST6252CN6/XXX
0 to +70°C
-40 to + 85°C SSOP16
u c
ST6252CN3/XXX -40 to + 125°C

od
ST6262BB1/XXX
ST6262BB6/XXX
ST6262BB3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PDIP16

P r
ST6262BM1/XXX
ST6262BM6/XXX 1836 Bytes 64
0 to +70°C
-40 to + 85°C PSO16
t e
ST6262BM3/XXX -40 to + 125°C

le
so
ST6262BN1/XXX 0 to +70°C
ST6262BN6/XXX -40 to + 85°C SSOP16

b
ST6262BN3/XXX -40 to + 125°C

The ST6252C and ST6262B are mask pro-

- O
Figure 1. Programming Waveform

(s)
grammed ROM versions of ST62T52C and 0.5s min
ST62T62C OTP devices. TEST

They offer the same functionality as OTP devices,

selecting as ROM options the options defined in
c t
u
the programmable option byte of the OTP version, 15
14V typ

d
except the LVD & OSG options that are not availa-
ble on the ST6262B ROM device. 10

r o 5

e P
l e t TEST
150 µs typ

s o
O b 100mA
max

4mA typ
t
VR02001

8.3.1 ROM READOUT PROTECTION

If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to pre-
vent any access to the program memory content.

71/75
ST6252C ST6262B ST6262C

In case the user wants to blow this fuse, high volt- 8.3.3 Listing Generation and Verification
age must be applied on the TEST pin.
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
Figure 50. Programming Circuit from it. This listing refers exactly to the mask which
will be used to produce the specified MCU. The
listing is then returned to the customer who must
5V 47mF thoroughly check, complete, sign and return it to
STMicroelectronics. The signed listing forms a

s )
t(
part of the contractual agreement for the creation
100nF of the specific customer mask.
The STMicroelectronics Sales Organization will be
u c
d
VSS pleased to provide detailed information on con-
tractual points.
VDD Table 26. ROM Memory Map for ST6252C/62B
r o
PROTECT
Device Address Description

e P
TEST 14V
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
Reserved

le
User ROM
Reserved t
100nF
ZPD15
15V
0FF0h-0FF7h
0FF8h-0FFBh
s o
Interrupt Vectors
Reserved

VR02003
0FFCh-0FFDh
0FFEh-0FFFh

O bNMI Interrupt Vector

Reset Vector

Note: ZPD15 is used for overvoltage protection

) -
The following section deals with the procedure for
t ( s
transfer of customer codes to STMicroelectronics.

u c
d
8.3.2 Transfer of Customer Code
Customer code is made up of the ROM contents
and the list of the selected mask options. The
r o
P
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-

e
must be set to FFh.

l e t
ated by the development tool. All unused bytes

s o
The selected mask options are communicated to
STMicroelectronics using the correctly filled OP-

b
TION LIST appended. See page 73.

72/75
 ST6252C ST6262B ST6262C

ST6252C/62B/P52C/P62C MICROCONTROLLER OPTION LIST

Customer: ..........................................................................
Address: ..........................................................................
..........................................................................
Contact: ..........................................................................
Phone: ..........................................................................
Reference: ..........................................................................

s )
STMicroelectronics references:

Device: [ ] ST6252C (2 KB) [ ] ST6262B (2 KB)

ct(
[ ] ST62P52C (2 KB) [ ] ST62P62C (2 KB)

d u
Package: [ ] Dual in Line Plastic
[ ] Small Outline Plastic with conditioning
r o
P
[ ] Shrink Small Outline Plastic with conditioning
Conditioning option: [ ] Standard (Tube) [ ] Tape & Reel
Temperature Range: [ ] 0°C to + 70°C
[ ] - 40°C to + 125°C
[ ] - 40°C to + 85°C

t e
Marking: [ ] Standard marking
[ ] Special marking (ROM only):
o le
PSO16 (6 char. max): _ _ _ _ _ _
s
PDIP16 (9 char. max): _ _ _ _ _ _ _ _ _

b
SSOP16 (10 char. max): _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Oscillator Safeguard*: [ ] Enabled

- O
[ ] Disabled
Oscillator Selection:
[ ] RC network

( s )
[ ] Quartz crystal / Ceramic resonator

t
Reset Delay: [ ] 32768 cycle delay [ ] 2048 cycle delay
Watchdog Selection:
PB3:PB2 pull-up at RESET*:

u
[ ] Enabled
c
[ ] Software Activation [ ] Hardware Activation
[ ] Disabled

d
External STOP Mode Control: [ ] Enabled [ ] Disabled

Readout Protection:
r
FASTROM:
o
P
[ ] Enabled [ ] Disabled
ROM:

e t e [ ] Enabled:
[ ] Fuse is blown by STMicroelectronics

o l [ ] Fuse can be blown by the customer

[ ] Disabled

b s
Low Voltage Detector*:
NMI pull-up*:
[ ] Enabled
[ ] Enabled
[ ] Disabled
[ ] Disabled

O
ADC Synchro*:
*except on ST6262B
[ ] Enabled [ ] Disabled

Comments:

Oscillator Frequency in the application: .............................................

Supply Operating Range in the application: .............................................
Notes: ..........................................................................
Date: ..........................................................................
Signature: ..........................................................................

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9 REVISION HISTORY
Table 27. Document revision history
Date Rev. Main Changes

Modification of “Additional Notes for EEPROM Parallel Mode” (p.13)

Changed fRC values in section 6.4 on page 61

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In section 4.2 on page 41: vector #4 instead of vector #3 for the timer interrupt request.
Jul-2001 2.9
Changed Figure 43 on page 67.
Changed Figure 45. on page 68 and Figure 47.and Figure 48. on page 69.
Changed option list on page 76
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Swapped D11 and D10 description on page 14:

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Feb-2002 3 D11. Reserved, must be cleared.
D10. Reserved, must be set to one.
Updated part numbers on page 1 and “ORDERING INFORMATION” on page 69 P r
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Replaced 255 by 256 in the formula for max resolution ARTIMout duty cycle in section 4.3.2 on

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page 42
Altered note in “Capture Mode With Reset Of Counter And Prescaler, and PWM generation” par-

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30-Mar-2009 4
agraph on page 45

Added ECOPACK information in section 7 on page 66

Added Section 8.1.1 IMPORTANT NOTE on page 69
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Added a note in the description of ARMC register in section 4.3.3 on page 46

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 ST6252C ST6262B ST6262C

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