IMX6DQRM

i.
MX 6Dual/6Quad Applications
Processor Reference Manual
Document Number: IMX6DQRM

Rev. 6, 05/2020
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 6, 05/2020
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Introduction
1.1 About This Document...................................................................................................................................................23
1.2 Introduction...................................................................................................................................................................31
1.3 Target Applications.......................................................................................................................................................31
1.4 Features......................................................................................................................................................................... 32
1.5 Architectural Overview.................................................................................................................................................35
Chapter 2
Memory Maps
2.1 Memory system overview.............................................................................................................................................41
2.2 Arm Platform Memory Map......................................................................................................................................... 41
2.3 DDR mapping to MMDC controller ports....................................................................................................................46
2.4 DMA memory map....................................................................................................................................................... 47
Chapter 3
Interrupts and DMA Events
3.1 Overview.......................................................................................................................................................................49
3.2 Cortex A9 interrupts..................................................................................................................................................... 49
3.3 SDMA event mapping.................................................................................................................................................. 53
Chapter 4
External Signals and Pin Multiplexing
4.1 Overview.......................................................................................................................................................................57
Chapter 5
Fusemap
5.1 Fusemap........................................................................................................................................................................ 163
5.2 Fusemap Description Table.......................................................................................................................................... 173
Chapter 6
External Memory Controllers
6.1 Overview.......................................................................................................................................................................181
6.2 Multi-mode DDR controller (MMDC) overview and feature summary...................................................................... 181

NXP Semiconductors 3
6.3 Raw NAND flash controller overview......................................................................................................................... 183
6.4 EIM-PSRAM/NOR flash controller overview..............................................................................................................186
Chapter 7
System Debug
7.1 Overview.......................................................................................................................................................................189
7.2 Chip and Arm Platform Debug Architecture................................................................................................................ 189
7.3 Smart DMA (SDMA) core............................................................................................................................................199
7.4 Miscellaneous............................................................................................................................................................... 201
7.5 Supported tools............................................................................................................................................................. 202
Chapter 8
System Boot
8.1 Overview.......................................................................................................................................................................203
8.2 Boot modes................................................................................................................................................................... 205
8.3 Device configuration.....................................................................................................................................................210
8.4 Device initialization...................................................................................................................................................... 214
8.5 Boot devices (internal boot)..........................................................................................................................................220
8.6 Program image.............................................................................................................................................................. 259
8.7 Plugin image................................................................................................................................................................. 267
8.8 Serial Downloader........................................................................................................................................................ 267
8.9 Recovery devices.......................................................................................................................................................... 276
8.10 USB low-power boot.................................................................................................................................................... 276
8.11 High-Assurance Boot (HAB)........................................................................................................................................278
Chapter 9
Multimedia
9.1 Video Graphics Sub System......................................................................................................................................... 281
9.2 Image Processing Unit (IPU)........................................................................................................................................ 289
9.3 LVDS Display Bridge (LDB)....................................................................................................................................... 300
9.4 Video Data Order Adapter (VDOA).............................................................................................................................302
9.5 Display Content Integrity Checker (DCIC).................................................................................................................. 304
9.6 Video Processing Unit (VPUv6)...................................................................................................................................306

9.7 OpenGL ES 3D Graphics Processing Unit (GPU3Dv4)...............................................................................................310
9.8 2D Graphics Processing Unit (GPU2Dv2)................................................................................................................... 312
9.9 Vector Graphics Processing Unit (GPUVGv2)............................................................................................................ 314
9.10 HDMI TX - HD Multimedia Interface transmitter....................................................................................................... 315
9.11 Display / Sensor MIPI interfaces.................................................................................................................................. 318
9.12 Audio subsystem...........................................................................................................................................................322
Chapter 10
Clock and Power Management
10.1 Introduction...................................................................................................................................................................335
10.2 Device Power Management Architecture Components................................................................................................335
10.3 Clock Management....................................................................................................................................................... 338
10.4 Power management.......................................................................................................................................................347
10.5 ONOFF (Button)...........................................................................................................................................................369
Chapter 11
System Security
11.1 Overview.......................................................................................................................................................................371
11.2 Central Security Unit (CSU).........................................................................................................................................372
11.3 Cryptographic Acceleration and Assurance Module (CAAM).................................................................................... 374
11.4 Secure Non-Volatile Storage (SNVS).......................................................................................................................... 375
11.5 Data Co-Processor (DCP)............................................................................................................................................. 376
11.6 High-Assurance Boot (HAB)........................................................................................................................................377
11.7 System JTAG Controller (SJC).................................................................................................................................... 377
Chapter 12
ARM Cortex A9 MPCore Platform (ARM)
12.1 Overview.......................................................................................................................................................................379
12.2 External Signals............................................................................................................................................................ 379
12.3 Platform configuration.................................................................................................................................................. 380
12.4 Performance and Power................................................................................................................................................ 382
12.5 Core Platform Sub-Blocks details.................................................................................................................................384
12.6 Debug and Trace Sub-blocks (CoreSight components)................................................................................................387

Chapter 13
AHB to IP Bridge (AIPSTZ)
13.1 Overview.......................................................................................................................................................................391
13.2 Clocks........................................................................................................................................................................... 391
13.3 Functional Description..................................................................................................................................................392
13.4 Access Protections........................................................................................................................................................ 393
13.5 Access Support..............................................................................................................................................................393
13.6 Initialization Information.............................................................................................................................................. 394
13.7 Off-Platform Peripherals Index.....................................................................................................................................395
13.8 AIPSTZ Memory Map/Register Definition.................................................................................................................. 398
Chapter 14
AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
14.1 Overview.......................................................................................................................................................................415
14.2 Clocks........................................................................................................................................................................... 416
14.3 APBH DMA..................................................................................................................................................................417
14.4 NAND Read Status Polling Example........................................................................................................................... 422
14.5 APBH Memory Map/Register Definition.....................................................................................................................424
Chapter 15
Asynchronous Sample Rate Converter (ASRC)
15.1 Overview.......................................................................................................................................................................455
15.2 Clocks........................................................................................................................................................................... 462
15.3 Interrupts....................................................................................................................................................................... 462
15.4 DMA requests............................................................................................................................................................... 463
15.6 Startup Procedure..........................................................................................................................................................469
15.7 ASRC Memory Map/Register Definition..................................................................................................................... 473
Chapter 16
Digital Audio Multiplexer (AUDMUX)
16.1 Overview.......................................................................................................................................................................513

16.3 Clocks........................................................................................................................................................................... 516
16.4 Default Register Configuration.....................................................................................................................................518
16.6 AUDMUX Memory Map/Register Definition..............................................................................................................538
Chapter 17
40-BIT Correcting ECC Accelerator (BCH)
17.1 Overview.......................................................................................................................................................................561
17.2 Operation.......................................................................................................................................................................563
17.3 Memory to Memory (Loopback) Operation................................................................................................................. 570
17.4 Programming the BCH/GPMI Interfaces......................................................................................................................571
17.5 Behavior During Reset..................................................................................................................................................590
17.6 BCH Memory Map/Register Definition....................................................................................................................... 591
Chapter 18
Clock Controller Module (CCM)
18.1 Overview.......................................................................................................................................................................621
18.3 CCM Clock Tree...........................................................................................................................................................624
18.4 System Clocks...............................................................................................................................................................628
18.6 CCM Memory Map/Register Definition.......................................................................................................................666
18.7 CCM Analog Memory Map/Register Definition..........................................................................................................726
Chapter 19
MIPI CSI to IPU Gasket (CSI2IPU)
19.1 Overview.......................................................................................................................................................................767
19.2 CSI2IPU signals............................................................................................................................................................769
19.3 Timing interface............................................................................................................................................................770
19.4 Payload data output formats..........................................................................................................................................771
19.5 CSI2IPU Memory Map/Register Definition.................................................................................................................778
Chapter 20
Display Content Integrity Checker (DCIC)

20.1 Overview.......................................................................................................................................................................781
20.3 DCIC Memory Map/Register Definition...................................................................................................................... 787
Chapter 21
Enhanced Configurable SPI (ECSPI)
21.1 Overview.......................................................................................................................................................................795
21.3 Clocks........................................................................................................................................................................... 800
21.5 Initialization.................................................................................................................................................................. 811
21.6 Applications.................................................................................................................................................................. 811
21.7 ECSPI Memory Map/Register Definition.....................................................................................................................812
Chapter 22
External Interface Module (EIM)
22.1 Overview.......................................................................................................................................................................829
22.3 Clocks........................................................................................................................................................................... 840
22.4 Chip Select Memory Map.............................................................................................................................................841
22.7 Typical Application...................................................................................................................................................... 853
22.8 External Bus Timing Diagrams.................................................................................................................................... 861
22.9 EIM Memory Map/Register Definition........................................................................................................................ 880
Chapter 23
10/100/1000-Mbps Ethernet MAC (ENET)
23.1 Introduction...................................................................................................................................................................899
23.2 Overview.......................................................................................................................................................................899
23.4 Clocks........................................................................................................................................................................... 908
23.5 Memory map/register definition................................................................................................................................... 909

23.6 Functional description...................................................................................................................................................981
Chapter 24
Enhanced Periodic Interrupt Timer (EPIT)
24.1 Overview.......................................................................................................................................................................1041
24.2 External signals.............................................................................................................................................................1042
24.3 Clocks........................................................................................................................................................................... 1042
24.5 Initialization/ Application Information......................................................................................................................... 1047
24.6 EPIT Memory Map/Register Definition....................................................................................................................... 1048
Chapter 25
Enhanced Serial Audio Interface (ESAI)
25.1 Overview.......................................................................................................................................................................1053
25.3 Clocks........................................................................................................................................................................... 1067
25.6 ESAI Memory Map/Register Definition.......................................................................................................................1076
Chapter 26
Flexible Controller Area Network (FLEXCAN)
26.1 Overview.......................................................................................................................................................................1121
26.3 Clocks........................................................................................................................................................................... 1126
26.4 Message Buffer Structure............................................................................................................................................. 1126
26.5 Rx FIFO Structure.........................................................................................................................................................1130
26.7 Initialization/Application Information.......................................................................................................................... 1160
26.8 FLEXCAN Memory Map/Register Definition............................................................................................................. 1162
Chapter 27
General Power Controller (GPC)
27.1 Overview.......................................................................................................................................................................1201

27.2 Clocks........................................................................................................................................................................... 1202
27.3 Power Gating Control (PGC)........................................................................................................................................1202
27.4 GPC Interrupt Controller (INTC)................................................................................................................................. 1204
27.5 GPC Memory Map/Register Definition........................................................................................................................1205
27.6 PGC Memory Map/Register Definition........................................................................................................................1210
Chapter 28
General Purpose Input/Output (GPIO)
28.1 Overview.......................................................................................................................................................................1217
28.3 Clocks........................................................................................................................................................................... 1226
28.4 GPIO Functional Description....................................................................................................................................... 1227
28.5 GPIO Memory Map/Register Definition...................................................................................................................... 1235
Chapter 29
General Purpose Media Interface (GPMI)
29.1 Overview.......................................................................................................................................................................1249
29.3 Clocks........................................................................................................................................................................... 1251
29.4 GPMI NAND Mode......................................................................................................................................................1252
29.5 Behavior During Reset..................................................................................................................................................1272
29.6 GPMI Memory Map/Register Definition......................................................................................................................1272
Chapter 30
General Purpose Timer (GPT)
30.1 Overview.......................................................................................................................................................................1301
30.3 Clocks........................................................................................................................................................................... 1305
30.5 Initialization/ Application Information ........................................................................................................................ 1311
30.6 GPT Memory Map/Register Definition........................................................................................................................ 1312
Chapter 31
2D Graphics Processing Unit (GPU2D)

31.1 Overview.......................................................................................................................................................................1325
31.2 GPU2D Block Diagram................................................................................................................................................ 1325
31.3 GPU2D Features........................................................................................................................................................... 1326
31.4 GPU2D OPERATIONS................................................................................................................................................1327
Chapter 32
32.1 Overview.......................................................................................................................................................................1337
32.2 GPU3D Block Diagram................................................................................................................................................ 1337
32.3 GPU3D Hardware Features.......................................................................................................................................... 1339
32.4 Usage Mode.................................................................................................................................................................. 1346
Chapter 33
HDMI Transmitter (HDMI)
33.1 Overview.......................................................................................................................................................................1347
33.3 Clocks........................................................................................................................................................................... 1351
33.5 HDMI Memory Map/Register Definition.....................................................................................................................1378
Chapter 34
HDMI 3D Tx PHY (HDMI_PHY)
34.1 Overview.......................................................................................................................................................................1607
34.4 System-Level Implementation...................................................................................................................................... 1633
34.5 Reference Clock............................................................................................................................................................1635
34.6 Control Registers.......................................................................................................................................................... 1636
34.7 HDMI_PHY Memory Map/Register Definition...........................................................................................................1636
34.8 Appendix A: Driver Voltage Level Configuration....................................................................................................... 1683
34.9 Appendix B................................................................................................................................................................... 1684
34.10 Appendix C: 3D Video Formats................................................................................................................................... 1691

Chapter 35
I2C Controller (I2C)
35.1 Overview.......................................................................................................................................................................1695
35.3 Clocks........................................................................................................................................................................... 1699
35.5 Initialization.................................................................................................................................................................. 1703
35.6 Software restriction.......................................................................................................................................................1711
35.7 I2C Memory Map/Register Definition..........................................................................................................................1712
Chapter 36
IOMUX Controller (IOMUXC)
36.1 Overview.......................................................................................................................................................................1719
36.2 Clocks........................................................................................................................................................................... 1721
36.4 IOMUXC Memory Map/Register Definition............................................................................................................... 1724
Chapter 37
Image Processing Unit (IPU)
37.1 Overview.......................................................................................................................................................................2515
37.3 Clocks........................................................................................................................................................................... 2540
37.5 IPU Memory Map/Register Definition......................................................................................................................... 2709
Chapter 38
Keypad Port (KPP)
38.1 Overview ......................................................................................................................................................................3327
38.2 Clocks........................................................................................................................................................................... 3329
38.6 KPP Memory Map/Register Definition........................................................................................................................ 3340

Chapter 39
LVDS Display Bridge (LDB)
39.1 Overview.......................................................................................................................................................................3347
39.3 Clocks........................................................................................................................................................................... 3350
39.4 Input and Output Ports.................................................................................................................................................. 3350
39.5 Processing..................................................................................................................................................................... 3351
39.6 LDB Memory Map/Register Definition........................................................................................................................3353
Chapter 40
MIPI - Camera Serial Interface Host Controller (MIPI_CSI)
40.1 Overview.......................................................................................................................................................................3357
40.2 Features......................................................................................................................................................................... 3357
40.3 Architecture...................................................................................................................................................................3358
40.4 Timing Interfaces.......................................................................................................................................................... 3363
40.5 Payload Data Output Format........................................................................................................................................ 3368
40.6 MIPI_CSI Memory Map/Register Definition...............................................................................................................3383
Chapter 41
MIPI DSI Host Controller (MIPI_DSI)
41.1 Overview.......................................................................................................................................................................3407
41.2 Features......................................................................................................................................................................... 3407
41.3 Clocks........................................................................................................................................................................... 3408
41.4 Architecture...................................................................................................................................................................3409
41.5 Programming.................................................................................................................................................................3433
41.6 MIPI_DSI Memory Map/Register Definition...............................................................................................................3434
Chapter 42
MIPI HSI Host Controller (MIPI_HSI)
42.1 Overview.......................................................................................................................................................................3463
42.3 Clocks........................................................................................................................................................................... 3465

42.5 HSI Memory Map/Register Definition......................................................................................................................... 3469
Chapter 43
MediaLB (MLB)
43.1 Overview.......................................................................................................................................................................3563
43.3 Clocks........................................................................................................................................................................... 3565
43.5 Software Flow...............................................................................................................................................................3588
43.6 MLB150 Memory Map/Register Definition.................................................................................................................3594
Chapter 44
Multi Mode DDR Controller (MMDC)
44.1 Overview.......................................................................................................................................................................3619
44.3 Clocks........................................................................................................................................................................... 3623
44.5 Performance.................................................................................................................................................................. 3644
44.6 MMDC Debug ............................................................................................................................................................. 3647
44.7 MMDC Profiling...........................................................................................................................................................3649
44.8 LPDDR2 Refresh Rate Update and Timing Derating...................................................................................................3651
44.9 Changing MMDC SDCLK Frequency......................................................................................................................... 3652
44.10 ODT Configuration ......................................................................................................................................................3658
44.11 Calibration Process....................................................................................................................................................... 3659
44.12 MMDC Memory Map/Register Definition...................................................................................................................3683
Chapter 45
Network Interconnect Bus System (NIC-301)
45.1 Overview ......................................................................................................................................................................3813
45.3 Memory Map and Register Definition..........................................................................................................................3815
Chapter 46
On-Chip OTP Controller (OCOTP_CTRL)

46.1 Overview.......................................................................................................................................................................3821
46.2 Clocks........................................................................................................................................................................... 3821
46.3 Top-Level Symbol and Functional Overview...............................................................................................................3822
46.4 Fuse Map.......................................................................................................................................................................3829
46.5 OCOTP Memory Map/Register Definition.................................................................................................................. 3829
Chapter 47
On-Chip RAM Memory Controller (OCRAM)
47.1 Overview.......................................................................................................................................................................3859
47.2 Basic Functions.............................................................................................................................................................3860
47.3 Advanced Features........................................................................................................................................................3861
47.4 Programmable Registers............................................................................................................................................... 3863
Chapter 48
PCI Express (PCIe)
48.1 Overview.......................................................................................................................................................................3865
48.2 Architecture...................................................................................................................................................................3867
48.3 Core Operations............................................................................................................................................................ 3883
48.4 AXI Bridge Module...................................................................................................................................................... 3960
48.5 App Note: Order Enforcement Using the PCIe Core....................................................................................................3986
48.6 App Note: Calculating Gen1 PCI Express and AXI Bridge Throughput..................................................................... 3992
48.7 PCIe Registers (EP mode)............................................................................................................................................ 3996
48.8 PCIe Registers (RC mode)............................................................................................................................................4005
48.9 PCIe Registers: Port Logic............................................................................................................................................4012
48.10 PCIe CTRL EP Mode Memory Map/Register Definition............................................................................................ 4014
48.11 PCIe CTRL RC Mode Memory Map/Register Definition............................................................................................4053
48.12 PCIe CTRL Port Logic Memory Map/Register Definition.......................................................................................... 4130
Chapter 49
PCI Express PHY (PCIe_PHY)
49.1 Overview.......................................................................................................................................................................4189
49.2 Applications.................................................................................................................................................................. 4189
49.3 PCIe2 PHY Features..................................................................................................................................................... 4189

49.6 System Operation..........................................................................................................................................................4193
49.7 Control Memory Map/Register Definition................................................................................................................... 4195
Chapter 50
Power Management Unit (PMU)
50.1 Overview.......................................................................................................................................................................4253
50.2 Digital LDO Regulators................................................................................................................................................4255
50.3 Analog LDO Regulators............................................................................................................................................... 4256
50.4 USB LDO Regulator.....................................................................................................................................................4258
50.5 SNVS Regulator............................................................................................................................................................4258
50.6 Power Modes................................................................................................................................................................ 4258
50.7 PMU Memory Map/Register Definition.......................................................................................................................4259
Chapter 51
Pulse Width Modulation (PWM)
51.1 Overview.......................................................................................................................................................................4281
51.3 Clocks........................................................................................................................................................................... 4283
51.5 Enable Sequence for the PWM..................................................................................................................................... 4286
51.6 Disable Sequence for the PWM....................................................................................................................................4287
51.7 PWM Memory Map/Register Definition...................................................................................................................... 4287
Chapter 52
ROM Controller with Patch (ROMC)
52.1 Overview.......................................................................................................................................................................4297
52.2 Clocks........................................................................................................................................................................... 4299
52.3 Memory Map................................................................................................................................................................ 4299
52.5 ROMCP Memory Map/Register Definition..................................................................................................................4305

Chapter 53
Serial Advanced Technology Attachment Controller (SATA)
53.1 Introduction...................................................................................................................................................................4313
53.2 Block Overview............................................................................................................................................................ 4314
53.3 Architecture...................................................................................................................................................................4317
53.4 Programming.................................................................................................................................................................4366
53.5 Software Manipulation of Port DMA........................................................................................................................... 4369
53.6 Register Descriptions.................................................................................................................................................... 4370
53.7 SATA Memory Map/Register Definition..................................................................................................................... 4371
Chapter 54
Serial Advanced Technology Attachment PHY (SATA PHY)
54.1 Overview.......................................................................................................................................................................4419
54.4 Control Registers.......................................................................................................................................................... 4442
54.5 Timing and Specifications............................................................................................................................................ 4445
54.6 clock Memory Map/Register Definition.......................................................................................................................4470
54.7 lane0 Memory Map/Register Definition.......................................................................................................................4493
Chapter 55
Smart Direct Memory Access Controller (SDMA)
55.1 Overview.......................................................................................................................................................................4519
55.3 Clocks........................................................................................................................................................................... 4523
55.5 Instruction Set............................................................................................................................................................... 4637
55.6 Software Restrictions.................................................................................................................................................... 4693
55.7 Application Notes......................................................................................................................................................... 4694
55.8 Arm Platform Memory Map and Control Register Definitions....................................................................................4709
55.9 BP Memory Map and Control Register Definitions..................................................................................................... 4733
55.10 SDMA Internal (Core) Memory Map and Internal Register Definitions..................................................................... 4736

55.11 SDMA Peripheral Registers..........................................................................................................................................4752
Chapter 56
System JTAG Controller (SJC)
56.1 Overview.......................................................................................................................................................................4753
56.3 TAP Selection Block (TSB)..........................................................................................................................................4763
56.4 Boundary Scan Register (BSR) ................................................................................................................................... 4765
56.5 SJC Instruction Register (SJIR) ................................................................................................................................... 4765
56.6 Security......................................................................................................................................................................... 4771
56.9 SJC Memory Map/Register Definition......................................................................................................................... 4778
Chapter 57
Secure Non-Volatile Storage (SNVS)
57.1 SNVS overview............................................................................................................................................................ 4791
57.3 Clocks........................................................................................................................................................................... 4792
57.4 SNVS structure............................................................................................................................................................. 4793
57.5 SNVS_LP (low-power domain)....................................................................................................................................4796
57.6 SNVS reset and system powerup..................................................................................................................................4797
57.7 SNVS interrupts and alarms..........................................................................................................................................4799
57.8 Programming guidelines............................................................................................................................................... 4800
57.9 SNVS Memory Map/Register Definition..................................................................................................................... 4801
Chapter 58
Shared Peripheral Bus Arbiter (SPBA)
58.1 Overview.......................................................................................................................................................................4827
58.2 Clocks........................................................................................................................................................................... 4830
58.4 Resource ownership control..........................................................................................................................................4834
58.5 SPBA Memory Map/Register Definition......................................................................................................................4837

Chapter 59
Sony/Philips Digital Interface (SPDIF)
59.1 Overview ......................................................................................................................................................................4841
59.3 Clocks........................................................................................................................................................................... 4843
59.5 SPDIF Memory Map/Register Definition.....................................................................................................................4854
Chapter 60
System Reset Controller (SRC)
60.1 SRC Overview.............................................................................................................................................................. 4873
60.3 Clocks........................................................................................................................................................................... 4875
60.4 Top-level resets, power-up sequence and external supply integration......................................................................... 4875
60.5 Power-On Reset and power sequencing....................................................................................................................... 4880
60.7 SRC Memory Map/Register Definition........................................................................................................................ 4889
Chapter 61
Synchronous Serial Interface (SSI)
61.1 Overview.......................................................................................................................................................................4909
61.2 External Signal Description.......................................................................................................................................... 4911
61.3 Clocks........................................................................................................................................................................... 4915
61.4 SSI Transmit FIFO 0 & 1 Registers..............................................................................................................................4915
61.5 SSI Transmit Shift Register (TXSR)............................................................................................................................ 4916
61.6 SSI Receive FIFO 0 and 1 Registers.............................................................................................................................4918
61.7 SSI Receive Shift Register (RXSR)..............................................................................................................................4919
61.9 SSI Memory Map/Register Definition..........................................................................................................................4949
Chapter 62
Temperature Monitor (TEMPMON)
62.1 Overview.......................................................................................................................................................................4981

62.2 Software Usage Guidelines...........................................................................................................................................4982
62.3 TEMPMON Memory Map/Register Definition............................................................................................................4983
Chapter 63
TrustZone Address Space Controller (TZASC)
63.1 Overview.......................................................................................................................................................................4987
63.2 Clocks........................................................................................................................................................................... 4988
63.3 i.MX 6Dual/6Quad Specific Configuration .................................................................................................................4988
63.4 Address Mapping in various memory mapping modes................................................................................................ 4989
Chapter 64
Universal Asynchronous Receiver/Transmitter (UART)
64.1 Overview.......................................................................................................................................................................4991
64.3 Clocks........................................................................................................................................................................... 4999
64.5 Binary Rate Multiplier (BRM)......................................................................................................................................5021
64.6 Infrared Interface.......................................................................................................................................................... 5023
64.7 9-bit RS-485 Mode....................................................................................................................................................... 5028
64.8 Low Power Modes........................................................................................................................................................ 5030
64.9 UART Operation in System Debug State..................................................................................................................... 5032
64.10 Reset..............................................................................................................................................................................5033
64.11 Transfer Error................................................................................................................................................................5033
64.12 Functional Timing.........................................................................................................................................................5034
64.13 Initialization.................................................................................................................................................................. 5034
64.14 References.....................................................................................................................................................................5037
64.15 UART Memory Map/Register Definition.....................................................................................................................5038
Chapter 65
Universal Serial Bus Controller (USB)
65.1 Overview.......................................................................................................................................................................5069

65.4 USB Operation Model.................................................................................................................................................. 5078
65.5 USB Non-Core Memory Map/Register Definition.......................................................................................................5245
65.6 USB Core Memory Map/Register Definition............................................................................................................... 5262
Chapter 66
Universal Serial Bus 2.0 Integrated PHY (USB-PHY)
66.1 USB PHY Overview..................................................................................................................................................... 5339
66.2 Operation.......................................................................................................................................................................5340
66.3 USB PHY Memory Map/Register Definition...............................................................................................................5350
66.4 USB Analog Memory Map/Register Definition........................................................................................................... 5367
Chapter 67
Ultra Secured Digital Host Controller (uSDHC)
67.1 Overview.......................................................................................................................................................................5385
67.3 Clocks........................................................................................................................................................................... 5393
67.5 Initialization/Application of uSDHC............................................................................................................................ 5418
67.6 Commands for MMC/SD/SDIO................................................................................................................................... 5443
67.7 Software Restrictions.................................................................................................................................................... 5448
67.8 uSDHC Memory Map/Register Definition...................................................................................................................5450
Chapter 68
Video Data Order Adapter (VDOA)
68.1 Overview.......................................................................................................................................................................5517
68.2 Clocks........................................................................................................................................................................... 5518
68.4 VDOA Memory Map/Register Definition.................................................................................................................... 5521
Chapter 69
Video Processing Unit (VPU)
69.1 Overview.......................................................................................................................................................................5533
69.2 Modes of Operation...................................................................................................................................................... 5536
69.3 External Signal Description.......................................................................................................................................... 5537

69.4 Clocks........................................................................................................................................................................... 5539
69.7 Application Information................................................................................................................................................5548
69.8 VPU Memory Map/Register Definition........................................................................................................................5567
Chapter 70
Watchdog Timer (WDOG)
70.1 Overview.......................................................................................................................................................................5575
70.3 Clocks........................................................................................................................................................................... 5577
70.4 Watchdog mechanism and system integration..............................................................................................................5577
70.6 Initialization.................................................................................................................................................................. 5587
70.7 WDOG Memory Map/Register Definition................................................................................................................... 5588
Chapter 71
Crystal Oscillator (XTALOSC)
71.1 Overview.......................................................................................................................................................................5595
71.3 Crystal Oscillator 24 MHz............................................................................................................................................ 5596
71.4 Crystal Oscillator 32 kHz..............................................................................................................................................5598
71.5 XTALOSC 24MHz Memory Map/Register Definition................................................................................................5599

Chapter 1
Introduction
1.1 About This Document

The i.MX 6Dual/6Quad application processors are NXP's latest additions to a growing
family of real-time processing products offering high-performance processing optimized
for lowest power consumption.
The i.MX 6Dual/6Quad processors feature NXP's advanced implementation of the
ARM®Cortex®-A9 core.
The processors can be interfaced with DDR3, DDR3L LPDDR2 (single and dual
channel) DRAM memory devices.
These products are suitable for applications such as:
• Automotive navigation and entertainment
• High-end Mobile Internet Devices and high-end PDAs
• Netbooks
• Nettops
• High-end portable media players with HD video capability
• Portable navigation devices
• Gaming Consoles
1.1.1 Audience
The reference manual is intended for the board-level product designers and product
software developers. This manual assumes that the reader has a background in computer
engineering and/or software engineering and understands the concepts of the digital
system design, microprocessor architecture, input/output (I/O) devices, industry standard
communication, and device interface protocols.

About This Document
1.1.2 Organization
The reference manual describes the chip at a system level and provides an architectural
overview. It also describes the system memory map, system-level interrupt events,
external pins and pin multiplexing, external memory, system debug, system boot,
multimedia subsystem, power management, and system security.
1.1.3 Suggested Reading

This section lists the additional resources that provide background for the information in
this manual, as well as general information about the architecture.
1.1.3.1 General Information

The following documentation provides useful background information about the ARM
Cortex processor.
For information about the ARM Cortex processor see:
• http://infocenter.arm.com
1.1.3.2 Related Documentation

For a current list of documentation, refer to http://www.nxp.com.
1.1.4 Conventions
The reference manual uses the following notational conventions:
cleared / set
When a bit has a value of zero, it is said to be cleared; when it has a value of one, it is
said to be set.
mnemonics
Instruction mnemonics are shown in lowercase bold.
italics
Italics indicate variable command parameters, for example, bcctrx.
The book titles in the text are set in italics.

Chapter 1 Introduction
15
An integer in decimal.
0x
the prefix to denote a hexadecimal number.
0b
The prefix to denote a binary number. Binary values of 0 and 1 are written without a
prefix.
n'H4000CA00
The n-bit hexadecimal number.
BLK_REG_NAME
The register names are all uppercase. The block mnemonic is prepended with an
underscore delimiter (_).
BLK_REG[FIELD]
The fields within registers appear in brackets. For example, ESR[RLS] refers to the
Receive Last Slot field of the ESAI Status Register.
BLK_REG[ n]
The bit number n within the BLK.REG register.
BLK_REG[ l:r]
The register bit ranges. The ranges are indicated by the left-most bit number l and the
right-most bit number r, separated by a colon (:). For example, ESR[15:0] refers to the
lower half word in the ESAI Status Register.
x, U
In some contexts, such as signal encodings, an unitalicized x indicates a "don't care" or
"uninitialized". The binary value can be 1 or 0.
x
An italicized x indicates an alphanumeric variable.
n, m
Italicized n or m represent integer variables.
!
Binary logic operator NOT.
&&
Binary logic operator AND.
||
Binary logic operator OR.
^ or <O+>
Binary logic operator XOR. For example, A <O+> B.
|
Bit-wise OR. For example, 0b0001 | 0b1000 yields the value of 0b1001.
&
Bit-wise AND. For example, 0b0001 and 0b1000 yields the value of 0b0000.
{A,B}

About This Document
Concatenation, where the n-bit value A is prepended to the m-bit value B to form an (n
+m)-bit value. For example, {0, REGm [14:0]} yeilds a 16-bit value with 0 in the most
significant bit.
- or grey fill
Indicates a reserved bit field in a register. Although these bits can be written to with
ones or zeros, they always read zeros.
>>
Shift right logical one position.
<<
Shift left logical one position.
<=
Assignment.
==
Compare equal.
!=
Compare not equal.
>
Greater than.
<
Less than.
1.1.5 Register Access
1.1.5.1 Register Diagram Field Access Type Legend

This figure provides the interpretation of the notation used in the register diagrams for a
number of common field access types:
1 0 Fld Fld rtc 0

Reserved Reserved R/W Fld Read-only Write-only Write 1 Read Self- Reserved
returns 1 returns 0 field field field Fld to clear w1c to clear Fld clear bit Fld
on read on read
Figure 1-1. Register Field Conventions
NOTE
For reserved register fields, the software should mask off the
data in the field after a read (the software can't rely on the
contents of data read from a reserved field) and always write all
zeros.

1.1.5.2 Register Macro Usage

A common operation is to update one field without disturbing the contents of the
remaining fields in the register. Normally, this requires a read-modify-write (RMW)
operation, where the CPU reads the register, modifies the target field, then writes the
results back to the register. This is an expensive operation in terms of CPU cycles,
because of the initial register read.
To address this issue, some hardware registers are implemented as a group, including
registers that can be used to either set, clear, or toggle (SCT) individual bits of the
primary register. When writing to an SCT register, all the bits set to 1 perform the
associated operation on the primary register, while the bits set to 0 are not affected. The
SCT registers always read back 0, and should be considered write-only. The SCT
registers are not implemented if the primary register is read-only.
With this architecture, it is possible to update one or more fields using only register
writes. First, all bits of the target fields are cleared by a write to the associated clear
register, then the desired value of the target fields is written to the set register. This
sequence of two writes is referred to as a clear-set (CS) operation.
A CS operation does have one potential drawback. Whenever a field is modified, the
hardware sees a value of 0 before the final value is written. For most fields, passing
through the 0 state is not a problem. Nonetheless, this behavior is something to consider
when using a CS operation.
Also, a CS operation is not required for fields that are one-bit wide. While the CS
operation works in this case, it is more efficient to simply set or clear the target bit (that
is, one write instead of two). A simple set or clear operation is also atomic, while a CS
operation is not.
Note that not all macros for set, clear, or toggle (SCT) are atomic. For registers that do
not provide hardware support for this functionality, these macros are implemented as a
sequence of read-modify-write operations. When an atomic operation is required, the
developer should pay attention to this detail, because unexpected behavior might result if
an interrupt occurs in the middle of the critical section comprising the update sequence.
A set of SCT registers is offered for registers in many modules on this device, as
described in this manual. In a module memory map table, the suffix _SET, _CLR, or
_TOG is added to the base name of the register. For example, the
CCM_ANALOG_PLL_ARM register has three other registers called
CCM_ANALOG_PLL_ARM_SET, CCM_ANALOG_PLL_ARM_CLR, and
CCM_ANALOG_PLL_ARM_TOG.

About This Document
In the sub-section that describes one of these sets of registers, a short-hand convention is
used to denote that a register has the SCT register set. There is an italicized n appended to
the end of the short register name. Using the above example, the name used for this
register is CCM_ANALOG_PLL_ARMn. When you see this designation, there is a SCT
register set associated with the register, and you can verify this by checking it in the
memory map table. The address offset for each of these registers is given in the form of
the following example:
Address: 20C_8000h base + 0h offset + (4d × i), where i=0d to 3d
In this example, the address for each of the base registers and their three SCT registers
can be calculated as:
Register Address
CCM_ANALOG_PLL_ARM 20C_8000h
CCM_ANALOG_PLL_ARM_SET 20C_8004h
CCM_ANALOG_PLL_ARM_CLR 20c_8008h
CCM_ANALOG_PLL_ARM_TOG 20C_800Ch
1.1.6 Signal Conventions

_b, _B
When appended to a signal name, this indicates that a signal is active-low.
NEG_ACTIVE
Overbar also denotes a negative active signal.
UPPERCASE
Package pin names, Block I/O signals.
lowercase
Lowercase is used to indicate internal signals.
1.1.7 Acronyms and Abbreviations

The table below contains acronyms and abbreviations used in this document.
Acronyms and Abbreviated Terms
Term Meaning
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
AIPS Arm IP Bus
ALU Arithmetic Logic Unit
Table continues on the next page...

Term Meaning
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
ASRC Asynchronous Sample Rate Converter
AXI Advanced eXtensible Interface
BIST Built-In Self Test
CA/CM Arm Cortex-A/Cortex-M
CAAM Cryptographic Acceleration and Assurance Module
CAN Controller Area Network
CCM Clock Controller Module
CPU Central Processing Unit
CSI CMOS Sensor Interface
CSU Central Security Unit
CTI Cross Trigger Interface
D-cache Data cache
DAP Debug Access Port
DDR Double data rate
DMA Direct memory access
DPLL Digital phase-locked loop
DRAM Dynamic random access memory
ECC Error correcting codes
ECSPI Enhanced Configurable SPI
EDMA Enhanced Direct Memory Access
EIM External Interface Module
ENET Ethernet
EPIT Enhanced Periodic Interrupt Timer
EPROM Erasable Programmable Read-Only Memory
ETF Embedded Trace FIFO
ETM Embedded Trace Macrocell
FIFO First-In-First-Out
GIC General Interrupt Controller
GPC General Power Controller
GPIO General-Purpose I/O
GPR General-Purpose Register
GPS Global Positioning System
GPT General-Purpose Timer
GPU Graphics Processing Unit
GPV Global Programmers View
HAB High-Assurance Boot
I-cache Instruction cache
I2C or I2C Inter-Integrated Circuit
IC Integrated Circuit

About This Document
Term Meaning
IEEE Institute of Electrical and Electronics Engineers
IOMUX Input-Output Multiplexer
IP Intellectual Property
IrDA Infrared Data Association
JTAG Joint Test Action Group (a serial bus protocol usually used for test purposes)
LCDIF Liquid Crystal Display Interface
LDO Low-Dropout
LIFO Last-In-First-Out
LRU Least-Recently Used
LSB Least-Significant Byte
LUT Look-Up Table
LVDS Low Voltage Differential Signaling
MAC Medium Access Control
MCM Miscellaneous control Module
MMC Multimedia Card
MMDC Multi Mode DDR Controller
MSB Most-Significant Byte
MT/s Mega Transfers per second
OCRAM On-Chip Random-Access Memory
OCOTP On-Chip One-Time Programmable Controller
PCI Peripheral Component Interconnect
PCIe PCI express
PCMCIA Personal Computer Memory Card International Association
PGC Power Gating Controller
PIC Programmable Interrupt Controller
PMU Power Management Unit
POR Power-On Reset
PSRAM Pseudo-Static Random Access Memory
PWM Pulse Width Modulation
PXP Pixel Pipeline
QoS Quality of Service
R2D Radians to Degrees
RISC Reduced Instruction Set Computing
ROM Read-Only Memory
ROMCP ROM Controller with Patch
RTOS Real-Time Operating System
Rx Receive
SAI Synchronous Audio Interface
SCU Snoop Control Unit
SD Secure Digital
SDIO Secure Digital Input/Output

Term Meaning
SDLC Synchronous Data Link Control
SDMA Smart DMA
SIM Subscriber Identification Module
SNVS Secure Non-Volatile Storage
SoC System-on-Chip
SPBA Shared Peripheral Bus Arbiter
SPDIF Sony Phillips Digital Interface
SPI Serial Peripheral Interface
SRAM Static Random-Access Memory
SRC System Reset Controller
TFT Thin-Film Transistor
TPIU Trace Port Interface
TSGEN Time Stamp Generator
Tx Transmit
TZASC TrustZone Address Space Controller
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
USDHC Ultra Secured Digital Host Controller
WDOG Watchdog
WLAN Wireless Local Area Network
WXGA Wide Extended Graphics Array
1.2 Introduction
This chapter introduces the architecture of the i.MX 6Dual/6Quad Multimedia
Applications Processors. The i.MX 6Dual/6Quad processors represent NXP's latest
achievement in integrated multimedia applications processors.
It is part of a growing i.MX family of multimedia-focused products, offering high-
performance processing optimized for the lowest power consumption.
1.3 Target Applications

The i.MX 6Dual/6Quad applications processor is tailored for use in multimedia-centric
smart mobile devices, driver information systems including infotainment and graphical
instrument clusters, and portable medical devices.

Features
The architecture's flexibility enables it to be used in a wide variety of general embedded

applications. The i.MX 6Dual/6Quad processor provides all interfaces necessary to
connect peripherals such as WLAN, Bluetooth™, GPS, camera sensors, and multiple
displays.
1.4 Features
The i.MX 6Dual/6Quad Application Processor (AP) is based on the ARM Cortex A9
MPCore™ Platform, which has the following features:
• ARM Cortex A9 MPCore™Dual or Quad core CPU configurations (with TrustZone)
• Symmetric CPU configuration where each CPU includes:
• 32 Kbyte L1 Instruction Cache
• 32 Kbyte L1 Data Cache
• Private Timer and Watchdog
• Cortex-A9 NEON MPE (Media Processing Engine) Co-processor.
The ARM Cortex A9 MPCore™ complex includes:
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 1 Megabyte unified L2 cache shared by all CPU cores (Dual or Quad)
• Two Master AXI (64-bit) bus interfaces output of L2 cache
• NEON MPE coprocessor
• SIMD Media Processing Architecture
• NEON register file with 32x64-bit general-purpose registers
• NEON Integer execute pipeline (ALU, Shift, MAC)
• NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
• NEON load/store and permute pipeline
• Supports single and double-precision add, subtract, multiply, divide, multiply
and accumulate, and square root operations as described in the ARM VFPv3
architecture.
• Provides conversions between 16-bit, 32-bit and 64-bit floating-point formats
and ARM integer word formats
The i.MX 6Dual/6Quad processor makes use of dedicated HW accelerators in order to
meet the targeted multimedia performance. The use of HW accelerators is a key factor in
obtaining high performance at low power consumption numbers, while keeping the CPU
core relatively free to perform other tasks.
The i.MX 6Dual/6Quad processor incorporates the following hardware accelerators:
• VPU -Video Processing Unit

• Two IPUv3H-Image Processing Unit (version 3H)
• GPU3Dv4 - 3D/2D Graphics Processing Unit (OpenGL ES 2.0), version 4
• GPU2Dv2 - 2D Graphics Processing Unit (BitBlt)
• GPU VG - OpenVG 1.1 Graphics Processing Unit
• ASRC - Asynchronous Sample Rate Converter
Security functions are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory
mapping, etc.)
• SJC- System JTAG Controller. Protecting JTAG from debug port attacks by
regulating or blocking the access to the system debug features
• CAAM - Cryptographic Acceleration and Assurance Module, incorporating 16KB
secure RAM
• SNVS - Secure Non-Volatile Storage, including Secure Real Time Clock
• CSU - Central Security Unit. Configured during boot and by e-fuses, and will
determine the security level operation mode as well as the TZ policy
• A-HAB-Advanced High Assurance Boot - HABv4 with the next embedded
enhancements: SHA-256, 2048 bit RSA key, version control mechanism, warm boot,
CSU and TZ initialization
The memory system consists of the following levels:
• Level 1 Cache - 32KB Instruction, 32KB Data cache per each core.
• Level 2 Cache - Unified instruction and data (1MByte)
• On-Chip Memory
• Boot ROM, including HAB (96 KB)
• Internal multimedia / shared, fast access RAM (256 KByte)
• Secure/non-secure RAM (16 KB)
The chip enables the following interfaces to external devices (some of them are muxed
and not available simultaneously):
• Hard Disk Drives
• SATA II, 3.0 Gbps
• Displays
• Five interfaces available. Total raw pixel rate of all interfaces is up to 532
Mpixels/sec, 24 bpp (266 Mpixels/sec per each IPU). Up to four interfaces may
be active at once.
• Two parallel 24-bit display ports - up to 220 Mpixels/sec each (e.g. WUXGA+
@ 60Hz), or dual HD1080 + WXGA @ 60Hz.
• LVDS serial ports: One port up to 170 Mpixels/sec (e.g. WUXGA at 60 Hz) or
two ports up to 85 MP/sec each

Features
• HDMI 1.4 port

• MIPI/DSI, 2 lanes @ 1 Gbps
• Camera sensors
• Up to three interfaces may be active at once
• Two parallel camera ports (up to 20-bit, up to 240MHz peak1 each).
• MIPI CSI-2 / Parallel port, supporting from 80 Mbps up to 1 Gbps speed per data
lane. The CSI-2 Receiver core can manage one clock lane and up to 4 data lanes.
There are 4 lanes in i.MX 6Dual/6Quad.
• Expansion cards
• Four SD/MMC/SDIO Controllers:
• Fully compliant with MMC command/response sets and Physical Layer as
defined in the Multimedia Card System Specification, v4.2/4.3/4.4/4.41
including high-capacity (size > 2GB) cards HC MMC. HW reset as specified for
eMMC cards is supported at ports #3 and #4 only.
• Fully compliant with SD command/response sets and Physical Layer as defined
in the SD Memory Card Specifications, v3.0 including extended-capacity SDHC
cards up to 32 GB.
• Fully compliant with SDIO command/response sets and interrupt/read-wait
mode as defined in the SDIO Card Specification, Part E1, v1.10
• Fully compliant with SD Card Specification, Part A2, SD Host Controller
Standard Specification, v2.00
• Supports:
• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to
UHS-I SDR104 mode (104MB/s max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to
52MHz in both SDR and DDR modes (104MB/s max)
• Instances #1 and #2 are primarily intended to serve as external slots or interfaces
to on-board SDIO devices
• Instances #3 and #4 are primarily intended to serve as interfaces to embedded
MMC memory or interfaces to on-board SDIO devices
• All ports can work with 1.8V and 3.3V cards. There are two completely
independent IO power domains for Ports #1 and #2.
• External memory interfaces
• 16/32/64-bit DDR3-1066, DDR3L-1066 and 1 / 2 LPDDR2-1066 channels
• 8-bit NAND-Flash, including support for Raw MLC/SLC, 2,4,8KB page size (up
to 4x devices), BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and
others. BCH ECC up to 40-bit.
• 16-bit Nor Flash. All WEIMv2 pins are muxed on other interfaces.
• 16-bit PSRAM, Cellular RAM.
1. The peak value of 240MHz is based on IPU capability and applies to internal sources such as CSI-2. Using
parallel input is subject to IO cell timing capability and board design signal timing constraints. The actual
frequency is expected to be lower. Final frequency will be determined by IC characterization.

• USB
• High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy
• Three USB 2.0 (480 Mbps) hosts:
• HS host, with integrated HS Phy.
• Two HS host, with integrated HS-IC USB (High Speed Inter-Chip USB)
Phy.
• Low Power modes
The i.MX 6Dual/6Quad integrates advanced power management unit and controllers:
• PMU, including LDO supplies for on-chip resources
• Temperature Sensor for monitoring the die temperature
• Supporting DVFS techniques for low power modes
• Uses SW State Retention, and Power Gating for ARM and MPE
• Support for various levels of system power modes
• Flexible clock gating control scheme
• Expansion PCI Express port (PCIe) v2.0 one lane
• PCI express (Gen 2.0) dual mode complex supporting Root complex operations
and Endpoint operations. x1 PHY configuration.
• Miscellaneous IPs and interfaces:
• Three SSI's that support I2S/AC97, up to 1.4 Mbps each
• Enhanced Serial Audio Interface (ESAI), up to 1.4 Mbps each channel
• Five UART, up to 4.0 Mbps each
• Providing RS232 interface
• Supporting 9-bit RS485 multidrop mode
• One of the five supports 8-wire (uart1) while the other four support 4-wire.
(Due to SoC IOMUX limitation, as all UART IP are identical).
• Five eCSPI (Enhanced CSPI). Using chip selects to support multiple peripherals.
• Three I2C, supports 400 Kbps
• Gigabit Ethernet Controller (IEEE1588 compliant), 1Gbps/10/100 Mbps
• Four Pulse Width Modulators (PWM)
• System JTAG Controller (SJC)
• GPIO with interrupt capabilities
• 8x8 Key Pad Port (KPP)
• Sony Philips Digital Interface (SPDIF), Rx and Tx
• Two Controller Area Network (FlexCAN), 1 Mbps each
• Two Watchdog timers (WDOG)
• Audio MUX (AUDMUX)
• MLB (MediaLB) provides interface to MOST Networks (MOST25，MOST50，
MOST150) with DTCP cipher accelerator

Architectural Overview
1.5 Architectural Overview

This section contains details about the chip architecture.
1.5.1 Block Diagram

A simplified block diagram is provided in the following section.
1.5.1.1 Simplified Block Diagram

A high-level block diagram is shown in the following figure. This diagram provides a
view of the chip's major sub-systems (processor domains, shared peripherals domain, and
memories) and logical connectivity.

Raw / ONFI 2.2 LP-DDR2/DDR3 NOR Flash Battery Ctrl 4x Camera 1 / 2 LVDS 1 / 2 LCD HDMI 1.4 MIPI
Nand-Flash 532MHz(DDR1066) PSRAM Device Parall/MIPI (WUXGA+) Displays Display Display
Application Processor CSI2/MIPI LDB HDMI DSI/MIPI

Domain (AP)
Digital
Audio GPMI
External
MMDC Internal Clock and Reset Crystals
Memory I/F
RAM Image Processing PLL (8) & Clock sources
EIM (272KB) Subsystem
SATA II 2x IPUv3H CCM
Boot
3.0Gbps GPC
ROM
(96KB) ARM Cortex A9 SRC
Smart DMA
(SDMA) MPCore Platform XTALOSC
Debug 4x A9-Core
2xCAN i/f OSC32K
DAP L1 I/D Cache
SPBA TPIU Timer, Wdog
AXI and AHB Switch Fabric

MMC/SD
CTIs AP Peripherals eMMC/eSD
1MB L2 cache
PCIe Bus SJC SCU, Timer uSDHC (4) MMC/SD
Shared Peripherals PTM's CTI'S SDXC
AUDMUX
Security 2
GPS SSI (3) eCSPI (5) Video I C(3)
CAAM
Proc. Unit
5xFast-UART ESAI (16KB Ram) PWM (4) Modem IC
(VPU + Cache)
SPDIF Rx/Tx ASRC SNVS OCOTP
(SRTC) 3D Graphics
Proc. Unit IOMUXC
Audio, CSU
Power (GPU3D) KPP
Mngmnt. Power Management Unit Fuse Box
2D Graphics GPIO
(PMU) LDOs Keypad
Proc. Unit CAN(2)
(GPU2D) 1-Gbps ENET
Timers/Control
WDOG (2) OpenVG 1.1 MLB 150
Proc. Unit DTCP
GPT (GPUVG)
EPIT (2) HSI/MIPI Ethernet 1-Gbit
Temp Monitor 10/100/1000
USB OTG + Mbps
OTG PHY1
2xHSIC 3 HS Ports
Host PHY2 PHY
JTAG USB OTG MLB/Most

Bluetooth WLAN (IEEE1149.6) (dev/host) Network
Figure 1-2. Simplified block diagram
1.5.2 Architectural Partitioning

Architecture supports processing-intensive tasks in the following ways:
• ARM Cortex A9 MPCore™ Platform provides hardware features for:
• Operating System
• User applications (including control over hardware accelerators and non-
accelerated functions)
• TrustZone applications

• Smart DMA enables data transfer between non-mastering peripherals and external or
internal memories
• System Control is supported via:
• Clock Control Module (CCM)
• Eight PLLs and two PFDs
• XTALOSC- 24 MHz Crystal oscillator source support
• OSC32KHz - 32.768 Hz Crystal oscillator source support
• System Reset Controller (SRC)
• General Power Controller (GPC)
• Temperature Sensor for monitoring and alarming on high temperature situations.
• Multimedia is supported with:
• Two independent Image Processing Units-IPUv3H
• Connectivity to displays and controllers (Parallel, LVDS, MIPI, HDMI),
cameras (parallel, MIPI).
• Display Processing: video/graphics combining, image enhancement
• Image conversions: resizing, rotation/inversion, color conversion, de-
interlacing
• Synchronization and control capabilities, allowing autonomous operation
• Video Processing Unit (VPU), supports various decoding/encoding formats in
HW, up to 1080p plus SD 30 fps decoding (H.264, VC1, RV10, DivX, etc.), and
up to 1080p 30 fps encoding (H.264, etc.).
• Graphics Processing Unit (GPU3Dv4) graphics processing compliant with the
following:
• OpenGL ES 1.1 and 2.0 including extensions.
• OpenVG 1.1
• Windows Direct3D
• OpenCL EP
• Graphics Processing Unit (GPU2Dv2)
• Vector graphics processing unit (GPU2Dv2):
• Real-time hardware curve tesselation of lines, quadratic and cubic Bezier
curves
• 16x Line Anti-aliasing
• OpenVG 1.1 support
• Vector Drawing functions
• Audio
• Audio codecs are provided by SW, which runs on ARM core, supporting
(but not limited to) MP3, WMA, AAC, HE-AAC and Pro10
• 3x SSIs
• ESAI
• SPDIF Tx/Rx

• Audmux
• Audio sample rate conversion accelerator (ASRC)
• Security is supported by:
• High Assurance Boot (HAB4) System
• ARM TrustZone (TZ) Trusted Execution environment
• DDR Memory secure region protection by TrustZone Address Space Controller
• On-chip RAM (OCRAM) single region TrustZone protection
• Peripheral access policy control, using Central Security Unit (CSU)
• One-Time Programmable (OTP) electrical fuse array (Total of 3840-bit e-fuses)
via the On-chip electrical fuse controller (OCOTP_CTRL)
• CAAM and SNVS security architecture, providing:
• 16 KB Secure RAM
• Secure Real Time Counters
• Security State Controller
• Encryption and Hashing functions, Random Number Generator (RNG)
• Security Violation/Tamper Detection & Reporting
• System JTAG controller (SJC)
• Secure Real Time Clock (SRTC)
• TrustZone Watchdog (TZ WDOG)
• Connectivity peripherals, timers and External Memory Interfaces:
• Embedded DMAs
• 3.3V IO voltage for seamless integration
• Four USB 2.0 ports, including four PHYs: 2x HS-USB (OTG) and 2x HS-IC
USB integrated PHYs
• Memory, 1066 MT/s per Line, supports LP-DDR2 (2x16, 2x32, 2x32 interleaved
mode - x64), DDR3 (x16/x32/x64) and DDR3L (x16/x32/x64)
• Nand-Flash (MLC up to 40-bit ECC) and NOR Flash memory interface via
GPMI Nand-Flash controller
• Timers: 2xEPIT, GPT and two Watch Dog timers (one of which is used for TZ),
in addition to the timers and watchdog timers integrated within the ARM Cortex
A9 MPCore™ platform.
• Miscellaneous connectivity support - SATA, PCIe, FLEXCAN, MLB,
MMC/SD, I2C, SPI, UART, PWM and Keypad interface
1.5.3 Endianness Support

The chip supports only the Little Endian mode.

1.5.4 Memory Interfaces

The chip DDR controller supports these memory interfaces:
• LP-DDR2-1066, 1 or 2 32-bit channels 532-MHz clock.
• DDR3/DDR3L 32/64-bit, 532-MHz clock.
NAND flash controller supports the following:
• Eight NAND flash buses
• Configurable page size of 2 KB, 4 KB, or 8 KB
• Configurable spare area per page of up to 512 B
• Supports interleaved accesses to up to eight NAND devices
• Legacy raw SLC-type and MLC-type devices
• Supports up to 40-bit ECC by the hardware BCH ECC accelerator, capable of 200
MB/s encode/decode rate
• ONFI2.2-compliant
• Timing modes 0-5 for both the asynchronous and synchronous I/F. A
synchronous clock rate of up to 100 MHz with a data rate of up to 200 MB/s.
• Vendor-specific devices: BA-NAND (Micron), PBA-NAND and LBA-NAND
(Toshiba), E2-NAND (Hynix), EF-NAND (Samsung), Samsung's "Toggle-mode"
NAND (clock rate of up to 66 MHz and 80 MHz, with a data rate of up to 133 MB/s
and 160 MB/s respectively)
The EIM block provides an interface for SRAM and PSRAM, and a 16/8-bit NOR flash.
All EIM pins are muxed on other interfaces.

Chapter 2
Memory Maps
2.1 Memory system overview

This section introduces the memory architecture of the chip.
NOTE
Accessing the reserved memory regions can result in
unpredictable behavior.
2.2 Arm Platform Memory Map

The chip memory map has been provided in the following tables. The mapping of the
DDR memory address space can be configured by software or hardware fuses, depending
on the memory device type (LPDDR2/DDR2/DDR3) and the selected interleaving/non-
interleaving scheme.
A combined memory map (of both the 2x32 and x64) is shown in this table:
Table 2-1. System memory map
Start address End address Size Description
1000_0000 FFFF_FFFF 3840 MB MMDC—DDR Controller. See DDR mapping to MMDC
controller ports.
0800_0000 0FFF_FFFF 128 MB EIM—(NOR/SRAM)
02A0_0000 02DF_FFFF 4 MB IPU-2
0260_0000 029F_FFFF 4 MB IPU-1
0220_C000 023F_FFFF 2 MB Reserved
0220_8000 0220_BFFF 16 KB MIPI_HSI
0220_4000 0220_7FFF 16 KB OpenVG (GC355)
0220_0000 0220_3FFF 16 KB SATA
0210_0000 021F_FFFF 1 MB Peripheral IPs via AIPS-2. See Table 2-3.

Arm Platform Memory Map
Table 2-1. System memory map (continued)

Start address End address Size Description
0200_0000 020F_FFFF 1 MB Peripheral IPs via AIPS-1. See Table 2-2.
01FF_C000 01FF_FFFF 16 KB PCIe registers
0100_0000 01FF_BFFF 16368 KB PCIe
00D0_0000 00FF_FFFF 3072 KB Reserved
00C0_0000 00CF_FFFF 1 MB GPV_1 PL301 (fast1)
00B0_0000 00BF_FFFF 1 MB GPV_0 PL301 (fast2) configuration port

00A0_3000 00AF_FFFF 1012 KB Reserved
00A0_2000 00A0_2FFF 4 KB PL310 (L2 cache controller)
00A0_0000 00A0_1FFF 8 KB ARM MP
0000—00FCh SCU registers
0100—01FFh Interrupt controller interfaces
0200—02FFh Global timer
0300—05FFh Reserved
0600—06FFh Private timers and watchdogs
0700—0FFFh Reserved
1000—1FFFh Interrupt distributor
0094_0000 009F_FFFF 0.75 MB OCRAM aliased
0090_0000 0093_FFFF 0.25 MB OCRAM 256 KB
0080_0000 008F_FFFF 1 MB GPV_4 PL301 (fast3) configuration port
0040_0000 007F_FFFF 4 MB Reserved
0030_0000 003F_FFFF 1 MB GPV_3 PL301 (per2) configuration port
0020_0000 002F_FFFF 1 MB GPV_2 PL301 (per1) configuration port
0013_C000 001F_FFFF 784 KB Reserved
0013_8000 0013_BFFF 16 KB DTCP
0013_4000 0013_7FFF 16 KB GPU 2D (GC320)
0013_0000 0013_3FFF 16 KB GPU 3D
0012_9000 0012_FFFF 28 KB Reserved
0012_0000 0012_8FFF 36 KB HDMI
0011_4000 0011_7FFF 16 KB BCH
0011_2000 0011_3FFF 8 KB GPMI
0011_0000 0011_1FFF 8 KB APBH-Bridge-DMA
0010_0000 0010_3FFF 16 KB CAAM (16 KB secure RAM)
0001_8000 000F_FFFF 928 KB Reserved
0000_0000 0001_7FFF 96 KB Boot ROM (ROMCP)
The table below shows the Arm IP Bus (AIPS) detailed memory map.

Chapter 2 Memory Maps
Table 2-2. AIPS-1 memory map

Start Address End Address Region NIC Port Size
020F_C000 020F_FFFF AIPS-1 Reserved 16 KB
020F_8000 020F_BFFF Reserved 16 KB
020F_4000 020F_7FFF Reserved 16 KB
020F_0000 020F_3FFF Reserved 16 KB
020E_C000 020E_FFFF SDMA 16 KB
020E_8000 020E_BFFF DCIC2 16 KB
020E_4000 020E_7FFF DCIC1 16 KB
020E_0000 020E_3FFF IOMUXC 16 KB
020D_C2C0 020D_FFFF Reserved 15680 B
020D_C2A0 020D_C2BF PGC_ARM 32 B
020D_C280 020D_C29F Reserved 32 B
020D_C260 020D_C27F PGC_PU 32 B
020D_C000 020D_C25F GPC 608 B
020D_8000 020D_BFFF SRC 16 KB
020D_4000 020D_7FFF EPIT2 16 KB
020D_0000 020D_3FFF EPIT1 16 KB
020C_C000 020C_FFFF SNVS_HP 16 KB
020C_B000 020C_BFFF Reserved 4 KB
020C_A000 020C_AFFF USBPHY2 4 KB
020C_9000 020C_9FFF USBPHY1 4 KB
020C_8000 020C_8FFF ANALOG: (PLLs, PFDs, 4 KB
Regulators, LDOs,
Temp Sensor)
020C_4000 020C_7FFF CCM 16 KB
020C_0000 020C_3FFF WDOG2 16 KB
020B_C000 020B_FFFF WDOG1 16 KB
020B_8000 020B_BFFF KPP 16 KB
020B_4000 020B_7FFF GPIO7 16 KB
020B_0000 020B_3FFF GPIO6 16 KB
020A_C000 020A_FFFF GPIO5 16 KB
020A_8000 020A_BFFF GPIO4 16 KB
020A_4000 020A_7FFF GPIO3 16 KB
020A_0000 020A_3FFF GPIO2 16 KB
0209_C000 0209_FFFF GPIO1 16 KB
0209_8000 0209_BFFF GPT 16 KB
0209_4000 0209_7FFF CAN2 16 KB
0209_0000 0209_3FFF AIPS-1 CAN1 16 KB
0208_C000 0208_FFFF PWM4 16 KB
0208_8000 0208_BFFF PWM3 16 KB
0208_4000 0208_7FFF PWM2 16 KB

Arm Platform Memory Map
Table 2-2. AIPS-1 memory map (continued)

Start Address End Address Region NIC Port Size
0208_0000 0208_3FFF PWM1 16 KB
0207_C000 0207_FFFF AIPS-1 Configuration 16 KB
0204_0000 0207_BFFF AIPS-1 VPU 240 KB
0203_C000 0203_FFFF SPBA 16 KB
0203_8000 0203_BFFF Reserved for SDMA 16 KB
internal registers
0203_4000 0203_7FFF ASRC 16 KB
0203_0000 0203_3FFF SSI3 16 KB
0202_C000 0202_FFFF SSI2 16 KB
0202_8000 0202_BFFF SSI1 16 KB
0202_4000 0202_7FFF ESAI 16 KB
0202_0000 0202_3FFF UART1 16 KB
AIPS-1 (via SPBA)
0201_C000 0201_FFFF Glob,Module ENABLE Reserved for SDMA 16 KB
internal registers
0201_8000 0201_BFFF eCSPI5 16 KB
0201_4000 0201_7FFF eCSPI4 16 KB
0201_0000 0201_3FFF eCSPI3 16 KB
0200_C000 0200_FFFF eCSPI2 16 KB
0200_8000 0200_BFFF eCSPI1 16 KB
0200_4000 0200_7FFF SPDIF 16 KB
0200_0000 0200_3FFF Reserved for SDMA 16 KB
internal registers
The table below shows the AIPS-2 detailed memory map.

Table 2-3. AIPS-2 memory map
Start Address End Address Region Allocation Size
021F_C000 021F_FFFF Reserved 16 KB
021F_8000 021F_BFFF Reserved 16 KB
021F_4000 021F_7FFF UART5 16 KB
021F_0000 021F_3FFF UART4 16 KB
021E_C000 021E_FFFF UART3 16 KB
021E_8000 021E_BFFF UART2 16 KB
021E_4000 021E_7FFF AIPS-2 VDOA 16 KB
021E_0000 021E_3FFF MIPI (DSI port) 16 KB
021D_C000 021D_FFFF MIPI (CSI port) 16 KB
021D_8000 021D_BFFF AUDMUX 16 KB
021D_4000 021D_7FFF TZASC2 16 KB
021D_0000 021D_3FFF TZASC1 16 KB
021C_C000 Reserved

Table 2-3. AIPS-2 memory map (continued)

021C_8000 Reserved
021C_4000 021C_7FFF Reserved
021C_0000 021C_3FFF CSU 16 KB
021B_C000 021B_FFFF OCOTP_CTRL 16 KB
021B_8000 021B_BFFF EIM 16 KB
021B_4000 021B_7FFF MMDC (port 1) 16 KB
021B_0000 021B_3FFF MMDC 16 KB
021A_C000 021A_FFFF ROMCP 16 KB
021A_8000 021A_BFFF I2C3 16 KB
021A_4000 021A_7FFF I2C2 16 KB
021A_0000 021A_3FFF I2C1 16 KB
0219_C000 0219_FFFF uSDHC4 16 KB
0219_8000 0219_BFFF uSDHC3 16 KB
0219_4000 0219_7FFF uSDHC2 16 KB
0219_0000 0219_3FFF uSDHC1 16 KB
0218_C000 0218_FFFF AIPS-2 MLB150 16 KB
0218_8000 0218_BFFF ENET 16 KB
0218_4000 0218_7FFF USBOH3 (USB) 16 KB
0218_0000 0218_3FFF Reserved 16 KB
0217_C000 0217_FFFF AIPS-2 configuration 16 KB
0216_1000 0217_BFFF Arm Cortex A9 MPCore 108 KB
Platform—Reserved
0214_0000 0216_0FFF Arm Cortex A9 MPCore 132 KB (See Table 2-4)
platform/DAP
0211_0000 0213_FFFF Reserved 192 KB
0210_0000 0210_FFFF CAAM 64 KB
The table below shows the Debug Access Port (DAP) detailed memory map.
Table 2-4. DAP memory map
0216_0000 0216_0FFF Platform Control 4 KB
0215_F000 0215_FFFF PTM3 4 KB
0215_E000 0215_EFFF PTM2 4 KB
0215_D000 0215_DFFF Arm Cortex A9 PTM1 4 KB
MPCore
0215_C000 0215_CFFF Platform, DAP PTM0 4 KB
0215_B000 0215_BFFF CTI3 4 KB
0215_A000 0215_AFFF CTI2 4 KB
0215_9000 0215_9FFF CTI1 4 KB

DDR mapping to MMDC controller ports
Table 2-4. DAP memory map (continued)

0215_8000 0215_8FFF CTI0 4 KB
0215_7000 0215_7FFF CPU3 PMU 4 KB
0215_6000 0215_6FFF CPU3 Debug i/f 4 KB
0215_5000 0215_5FFF CPU2 PMU 4 KB
0215_3000 0215_3FFF CPU1 PMU 4 KB
0215_1000 0215_1FFF CPU0 PMU 4 KB
0214_F000 0214_FFFF CA9-INTEG 4 KB
0214_5000 0214_EFFF Reserved 40 KB
0214_4000 0214_4FFF FUNNEL 4 KB
0214_3000 0214_3FFF TPIU 4 KB
0214_2000 0214_2FFF ext. CTI 4 KB
0214_1000 0214_1FFF ETB 4 KB
0214_0000 0214_0FFF DAP ROM Table 4 KB
NOTE
Accessing the reserved memory regions can result in
2.3 DDR mapping to MMDC controller ports

The following table lists the various DDR configuration modes and how each mode is
mapped to the DDR channels.
Memory Mapping DDR Memory Start Address End Address Total Size MMDC channel/ports
Mode Map Config[1:0]
fuse value
X32/X64-bit, fixed ‘00’ 1000_0000 FFFF_FFFF 3840 MB MMDC #0
mapping
Dual-channel (2x 32- ‘01’ 8000_0000 FFFF_FFFF 2048 MB MMDC #0
bit), Fixed mapping 1000_0000 7FFF_FFFF 1792 MB MMDC #1
(LPDDR2)
Dual channel (2x 32- ‘10’ 1000_0000 FFFF_FFFF 3840 MB MMDC #0 , MMDC #1
bit), Interleaved (interleaved data)
mapping (LPDDR2) 1
Illegal '11'
1. In the 4KB interleaving mode the system bus maps each consecutive 4KB region to a 4KB region in the other MMDC port,
such that "odd" 4KB spaces are mapped to MMDC0, and "even" 4KB regions mapped to MMDC1.

2.4 DMA memory map

The Smart DMA memory map is shown in the following table.
Table 2-5. SDMA peripheral memory map
Peripheral Base address Size
Reserved for SDMA internal memory 0x0000 4 KB
SPDIF 0x1000 4 KB
eCSPI1 0x2000 4 KB
eCSPI2 0x3000 4 KB
eCSPI3 0x4000 4 KB
eCSPI4 0x5000 4 KB
eCSPI5 0x6000 4 KB
Reserved for SDMA internal registers 0x7000 4 KB
UART1 0x8000 4 KB
ESAI 0x9000 4 KB
SSI1 0xA000 4 KB
SSI2 0xB000 4 KB
SSI3 0xC000 4 KB
ASRC 0xD000 4 KB
Reserved 0xE000 4 KB
SPBA Registers 0xF000 4 KB
NOTE
Accessing the reserved memory regions can result in an

DMA memory map

Chapter 3
Interrupts and DMA Events
3.1 Overview
This section describes the assignments of interrupts from the Arm domain in Cortex A9
interruptsand from the DMA events in SDMA event mapping.
3.2 Cortex A9 interrupts

The Global Interrupt Controller (GIC) collects up to 128 interrupt requests from all chip
sources and provides an interface to the Cortex A9 CPU cores. The first 32 interrupts are
private to the CPUs' interface. These interrupts are not included in the table below. All
interrupts besides those private to the CPU are hooked up to the GPC.
Each interrupt can be configured as a normal or a secure interrupt. Software force
registers and software priority masking are also supported. This table describes the Arm
Cortex A9 interrupt sources:
Table 3-1. Arm Cortex A9 domain interrupt summary
IRQ Interrupt Interrupt Description
Source
32 IOMUXC General-Purpose Register 1 from IOMUXC. Used to notify the cores on the exception
condition while booting.
33 DAP Debug Access Port interrupt request
34 SDMA SDMA interrupt request from all channels
35 VPU JPEG codec interrupt request
36 SNVS PMIC power off request
37 IPU IPU error interrupt request
38 IPU1 IPU1 sync interrupt request
39 IPU2 IPU2 error interrupt request
40 IPU2 IPU2 sync interrupt request

Cortex A9 interrupts
Table 3-1. Arm Cortex A9 domain interrupt summary (continued)

Source
41 GPU3D GPU3D interrupt request
42 R2D GPU2D R2D GPU2D general interrupt request
43 V2D GPU2D V2D GPU2D(OpenVG) general interrupt request
44 VPU VPU interrupt request
45 APBH-Bridge-DMA Logical OR of APBH-Bridge-DMA channels 0-3 completion and error interrupts
46 EIM EIM interrupt request
47 BCH BCH operation complete interrupt
48 GPMI GPMI operation timeout error interrupt
49 DTCP DTCP interrupt request
50 VDOA Logical OR of VDOA interrupt requests
51 SNVS SRTC consolidated interrupt
52 SNVS SRTC security interrupt
53 CSU CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were
asserted.
54 uSDHC1 uSDHC1 (Enhanced SDHC) interrupt request
58 UART1 UART1 interrupt request
63 eCSPI1 eCSPI1 interrupt request
68 I2C1 I2C1 interrupt request
71 SATA SATA interrupt request
72 USB USB Host 1 interrupt request
75 USB USB OTG interrupt request
76 USB_PHY UTMI0 interrupt request
77 USB_PHY UTMI1 interrupt request
78 SSI1 SSI1 interrupt request

Chapter 3 Interrupts and DMA Events

Source
81 Temperature Monitor Temperature Sensor (temperature greater than threshold) interrupt request
82 ASRC ASRC interrupt request
83 ESAI ESAI interrupt request
84 SPDIF SPDIF interrupt
85 MLB150 MLB error interrupt request
86 PMU Brownout of the 1.1, 2.5, and 3.0 analog regulators occurred.
87 GPT Logical OR of GPT rollover interrupt line, input capture 1 and 2 lines, output compare 1, 2,
and 3 interrupt lines
88 EPIT1 EPIT1 output compare interrupt
89 EPIT2 EPIT2 output compare interrupt
90 GPIO1 INT7 interrupt request
98 GPIO1 Combined interrupt indication for GPIO1 signals 0 - 15
112 WDOG1 WDOG1 timer reset interrupt request
113 WDOG2 WDOG2 timer reset interrupt request
114 KPP Key Pad interrupt request
115 PWM1 Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel
crossing interrupts.

Cortex A9 interrupts

Source
119 CCM CCM interrupt request 1
120 CCM CCM interrupt request 2
121 GPC GPC interrupt request 1
122 Reserved Reserved
123 SRC SRC interrupt request
124 CPU L2 interrupt request
125 CPU Parity Check error interrupt request
126 CPU Performance Unit interrupt
127 CPU CTI trigger outputs interrupt
128 SRC Combined CPU WDOG interrupts (4x) out of SRC
132 MIPI_CSI CSI interrupt request 1
133 MIPI_CSI CSI interrupt request 2
134 MIPI_DSI DSI interrupt request
135 MIPI_HSI HSI interrupt request
136 SJC SJC interrupt from the General-Purpose register
137 CAAM CAAM job ring 0 interrupt
138 CAAM CAAM job ring 1 interrupt
140 ASC1 ASC1 interrupt request
141 ASC2 ASC2 interrupt request
142 FLEXCAN1 FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor,
ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein.
Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and
ipi_int_waken
143 FLEXCAN2 FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor,
ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein.
147 HDMI HDMI video and CEC control interrupt request.
148 HDMI HDMI CEC dedicated wake-up interrupt.


Source
149 MLB150 Channels [31:0] interrupt requests. Channels [63:32] interrupt requests are available on IRQ
#158, unless the MLB150_ACTL[SMX] bit is set, in which case those channels are muxed
into this IRQ.
150 ENET MAC 0 IRQ, Logical OR of:
MAC 0 Periodic Timer Overflow
MAC 0 Time Stamp Available
MAC 0 Payload Receive Error
MAC 0 Transmit FIFO Underrun
MAC 0 Collision Retry Limit
MAC 0 Late Collision
MAC 0 Ethernet Bus Error
MAC 0 MII Data Transfer Done
MAC 0 Receive Buffer Done
MAC 0 Receive Frame Done
MAC 0 Transmit Buffer Done
MAC 0 Transmit Frame Done
MAC 0 Graceful Stop
MAC 0 Babbling Transmit Error
MAC 0 Babbling Receive Error
MAC 0 Wakeup Request [synchronous]
151 ENET MAC 0 1588 Timer interrupt [synchronous] request
152 PCIe PCIe interrupt request 1 (intd/msi_ctrl_int)
153 PCIe PCIe interrupt request 2 (intc)
154 PCIe PCIe interrupt request 3 (intb)
155 PCIe PCIe interrupt request 4 (inta)
156 DCIC1 Logical OR of DCIC1 interrupt requests
157 DCIC2 Logical OR of DCIC2 interrupt requests
158 MLB150 Logical OR of channel[63:32] interrupt requests
159 PMU Brownout of the core, GPU, and chip digital regulators occurred.
3.3 SDMA event mapping

This table shows the DMA request signals for the peripherals in the chip:

SDMA event mapping
Table 3-2. SDMA event mapping

Event DMA Source Description
Number
0 VPU VPU DMA request
1 IPU2 IPU2 DMA event
2 IPU / IOMUX IPU-1 DMA Event; Muxed with external DMA pad #1, controlled by GPR0[0]
3 eCSPI1 / I2C3 eCSPI1 Rx request; Muxed with I2C3 controlled by IOMUXC register GPR0[1]
4 eCSPI1 / I2C2 eCSPI1 Tx request; Muxed with I2C2 controlled by IOMUXC register GPR0[2]
5 eCSPI2 / I2C1 eCSPI2 Rx request; Muxed with I2C1 controlled by IOMUXC register GPR0[3]
6 eCSPI2 eCSPI2 Tx request
7 eCSPI3 eCSPI3 Rx request
9 eCSPI4 / EPIT2 eCSPI4 Rx request; Muxed with EPIT2 DMA request controlled by IOMUXC register
GPR0[5]
10 eCSPI4/ I2C1 eCSPI4 Tx request; Muxed with I2C1 controlled by IOMUXC register GPR0[4]
11 eCSPI5 eCSPI5 Rx request
13 GPT GPT counter event
14 SPDIF / IOMUX SPDIF RX DMA request; Muxed with external DMA pad #2 controlled by IOMUXC register
GPR0[7]
15 SPDIF SPDIF TX DMA request
16 EPIT1 EPIT1 request
17 ASRC ASRC DMA1 request (Pair A input Request)
18 ASRC ASRC DMA2 request (Pair B input Request)
19 ASRC ASRC DMA3 request (Pair C input Request)
20 ASRC ASRC DMA4 request (Pair A output Request)
21 ASRC ASRC DMA5 request (Pair B output Request)
22 ASRC ASRC DMA6 request (Pair C output Request)
23 ESAI / I2C3 ESAI Rx FIFO DMA request; Muxed with I2C3 controlled by IOMUXC register GPR0[6]
24 ESAI ESAI Tx FIFO DMA request
25 UART1 UART1 Rx FIFO
26 UART1 UART1 Tx FIFO
35 SSI1 SSI1 receive 1 DMA request
36 SSI1 SSI1 transmit 1 DMA request

Table 3-2. SDMA event mapping (continued)

Event DMA Source Description
Number
As shown in the table, some of the events are the output of a mux of two signals or
triggers. The selection of this mux is controlled by the general-purpose registers in
IOMUXC.

SDMA event mapping

Chapter 4
External Signals and Pin Multiplexing
4.1 Overview
The chip contains a limited number of pins, most of which have multiple signal options.
These signal-to-pin and pin-to-signal options are selected by the input-output multiplexer
called IOMUX. The IOMUX is also used to configure other pin characteristics, such as
voltage level, drive strength, and hysteresis.
Pin Assignments lists the pad names of the chip, the various signals that can be assigned
to each of the pads, and the default settings for each pad. The muxing options table lists
the external signals grouped by the module instance, the muxing options for each signal,
and the registers used to route the signal to the chosen pad.
4.1.1 Pin Assignments

Table 4-1. Pin Assignments
Pad Name Mode Signal Pad Settings Pad/Group Registers
BOOT_MODE0 SRC_BOOT_MODE0
BOOT_MODE1 SRC_BOOT_MODE1
CLK1_N XTALOSC_CLK1_N
CLK1_P XTALOSC_CLK1_P
CLK2_N XTALOSC_CLK2_N
CLK2_P XTALOSC_CLK2_P
CSI0_DAT4 ALT0 IPU1_CSI0_DATA04 HYS - ENABLED SW_PAD_CTL_PAD_CSI0_DATA04
ALT1 EIM_DATA02 PUS - 100K_OHM_PU
ALT2 ECSPI1_SCLK PUE - PULL
ALT3 KEY_COL5 PKE - ENABLED
ALT4 AUD3_TXC ODE - DISABLED
ALT5 GPIO5_IO22 SPEED - MEDIUM
ALT7 ARM_TRACE01
DSE - 40_OHM

Overview
Table 4-1. Pin Assignments (continued)

SRE - SLOW
ALT2 ECSPI1_MOSI PUE - PULL
ALT3 KEY_ROW5 PKE - ENABLED
ALT4 AUD3_TXD ODE - DISABLED
ALT7 ARM_TRACE02
DSE - 40_OHM
SRE - SLOW
ALT2 ECSPI1_MISO PUE - PULL
ALT4 AUD3_TXFS ODE - DISABLED
ALT5 GPIO5_IO24
SPEED - MEDIUM
ALT7 ARM_TRACE03
DSE - 40_OHM
SRE - SLOW
ALT2 ECSPI1_SS0 PUE - PULL
ALT4 AUD3_RXD ODE - DISABLED
ALT7 ARM_TRACE04
DSE - 40_OHM
SRE - SLOW
ALT4 I2C1_SDA ODE - DISABLED
ALT5 GPIO5_IO26
SPEED - MEDIUM
ALT7 ARM_TRACE05
DSE - 40_OHM
SRE - SLOW
ALT4 I2C1_SCL ODE - DISABLED

Chapter 4 External Signals and Pin Multiplexing

ALT7 ARM_TRACE06 DSE - 40_OHM
SRE - SLOW
ALT1 AUD3_RXC PUS - 100K_OHM_PU
ALT3 UART1_TX_DATA PKE - ENABLED
ALT5 GPIO5_IO28 ODE - DISABLED
ALT7 ARM_TRACE07 SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT1 AUD3_RXFS PUS - 100K_OHM_PU
ALT3 UART1_RX_DATA PKE - ENABLED
ALT7 ARM_TRACE08 SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 UART4_TX_DATA PUE - PULL
ALT5 GPIO5_IO30 PKE - ENABLED
ALT7 ARM_TRACE09 ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 UART4_RX_DATA PUE - PULL
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW

Overview

SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 UART4_RTS_B PUE - PULL
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 UART4_CTS_B PUE - PULL
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW


ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
CSI0_DATA_EN ALT0 IPU1_CSI0_DATA_EN HYS - ENABLED SW_PAD_CTL_PAD_CSI0_DATA_EN
ALT5 GPIO5_IO20 PUE - PULL
ALT7 ARM_TRACE_CLK PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
CSI0_MCLK ALT0 IPU1_CSI0_HSYNC HYS - ENABLED SW_PAD_CTL_PAD_CSI0_HSYNC
ALT3 CCM_CLKO1 PUS - 100K_OHM_PU
ALT7 ARM_TRACE_CTL PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
CSI0_PIXCLK ALT0 IPU1_CSI0_PIXCLK HYS - ENABLED SW_PAD_CTL_PAD_CSI0_PIXCLK
ALT5 GPIO5_IO18 PUS - 100K_OHM_PU
ALT7 ARM_EVENTO PUE - PULL
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
CSI0_VSYNC ALT0 IPU1_CSI0_VSYNC HYS - ENABLED SW_PAD_CTL_PAD_CSI0_VSYNC
ALT7 ARM_TRACE00 PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM

Overview

SRE - SLOW
CSI_CLK0M CSI_CLK0_N
CSI_CLK0P CSI_CLK0_P
CSI_D0M CSI_DATA0_N
CSI_D0P CSI_DATA0_P
CSI_D1M CSI_DATA1_N
CSI_D1P CSI_DATA1_P
CSI_D2M CSI_DATA2_N
CSI_D2P CSI_DATA2_P
CSI_D3M CSI_DATA3_N
CSI_D3P CSI_DATA3_P
DI0_DISP_CLK ALT0 IPU1_DI0_DISP_CLK HYS - ENABLED SW_PAD_CTL_PAD_DI0_DISP_CLK
ALT1 IPU2_DI0_DISP_CLK PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
DI0_PIN2 ALT0 IPU1_DI0_PIN02 HYS - ENABLED SW_PAD_CTL_PAD_DI0_PIN02
ALT1 IPU2_DI0_PIN02 PUS - 100K_OHM_PU
ALT2 AUD6_TXD PUE - PULL
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 AUD6_TXFS PUE - PULL
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 AUD6_RXD PUE - PULL


ALT3 SD1_WP PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 AUD6_TXC PUE - PULL
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
DISP0_DAT0 ALT0 IPU1_DISP0_DATA00 HYS - ENABLED SW_PAD_CTL_PAD_DISP0_DATA00
ALT1 IPU2_DISP0_DATA00 PUS - 100K_OHM_PU
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW

Overview

ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 AUD6_RXFS PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 AUD6_RXC PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 ECSPI3_RDY PUE - PULL
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM


SRE - SLOW
ALT2 PWM1_OUT PUE - PULL
ALT3 WDOG1_B PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 WDOG2_B PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED

Overview

SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 AUD5_RXFS PUE - PULL
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 AUD5_RXC PUE - PULL
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 ECSPI2_SS1 PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 AUD5_TXC PKE - ENABLED
ALT4 SDMA_EXT_EVENT0 ODE - DISABLED
DSE - 40_OHM
SRE - SLOW


ALT3 AUD5_TXD PKE - ENABLED
ALT4 SDMA_EXT_EVENT1 ODE - DISABLED
DSE - 40_OHM
SRE - SLOW
ALT3 AUD5_TXFS PKE - ENABLED
ALT4 AUD4_RXFS ODE - DISABLED
ALT7 EIM_CS2_B
DSE - 40_OHM
SRE - SLOW
ALT3 AUD5_RXD PKE - ENABLED
ALT4 AUD4_RXC ODE - DISABLED
ALT7 EIM_CS3_B
DSE - 40_OHM
SRE - SLOW
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW

Overview

SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 AUD4_RXD PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
DRAM_A0 DRAM_ADDR00 DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_ADDR00
DDR_INPUT - CMOS SW_PAD_CTL_GRP_DDR_TYPE
HYS - DISABLED SW_PAD_CTL_GRP_ADDDS
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM


ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM

Overview

ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
DRAM_CAS DRAM_CAS_B DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_CAS_B
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
DRAM_CS0 DRAM_CS0_B DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_CS0_B
HYS - DISABLED SW_PAD_CTL_GRP_CTLDS
ODT - DISABLED
DSE - 40_OHM
DRAM_CS1 DRAM_CS1_B DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_CS1_B
ODT - DISABLED
DSE - 40_OHM
DRAM_D0 DRAM_DATA00 DDR_SEL - LPDDR2 SW_PAD_CTL_GRP_DDR_TYPE
DDR_INPUT - CMOS SW_PAD_CTL_GRP_DDRMODE
HYS - DISABLED SW_PAD_CTL_GRP_DDRHYS
PUE - PULL SW_PAD_CTL_GRP_DDRPK


PKE - ENABLED SW_PAD_CTL_GRP_DDRPKE
ODT - DISABLED SW_PAD_CTL_GRP_TERM_CTL0
DSE - 40_OHM SW_PAD_CTL_GRP_B0DS

Overview

SW_PAD_CTL_GRP_DDRHYS


HYS - DISABLED SW_PAD_CTL_GRP_DDRPK
PUE - PULL SW_PAD_CTL_GRP_DDRPKE
PKE - ENABLED SW_PAD_CTL_GRP_TERM_CTL1
ODT - DISABLED SW_PAD_CTL_GRP_B1DS
DSE - 40_OHM

Overview




Overview



SW_PAD_CTL_GRP_DDRHYS

Overview

HYS - DISABLED SW_PAD_CTL_GRP_DDRPK
PUE - PULL SW_PAD_CTL_GRP_DDRPKE
PKE - ENABLED SW_PAD_CTL_GRP_TERM_CTL4
ODT - DISABLED SW_PAD_CTL_GRP_B4DS
DSE - 40_OHM



Overview




Overview

DRAM_DQM0 DRAM_DQM0 DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_DQM0
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
HYS - DISABLED
ODT - DISABLED


DSE - 40_OHM
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
DRAM_SDODT0 DRAM_ODT0 DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_ODT0
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
DRAM_SDODT1 DRAM_ODT1 DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_ODT1

Overview

HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
DRAM_RAS DRAM_RAS_B DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_RAS_B
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
DRAM_RESET DRAM_RESET DDR_SEL - SW_PAD_CTL_PAD_DRAM_RESET
RESERVED2
DDR_INPUT - CMOS
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
DRAM_SDBA0 DRAM_SDBA0 DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_SDBA0
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
ODT - DISABLED
DSE - 40_OHM
DRAM_SDCKE0 DRAM_SDCKE0 DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_SDCKE0
ODT - DISABLED
DSE - 40_OHM
DRAM_SDCKE1 DRAM_SDCKE1 DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_SDCKE1
ODT - DISABLED


DSE - 40_OHM
DRAM_SDCLK_0 DRAM_SDCLK0_N
_B
DRAM_SDCLK_0 DRAM_SDCLK0_P DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_SDCLK0_P
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
DRAM_SDCLK_1 DRAM_SDCLK1_N
_B
DRAM_SDCLK_1 DRAM_SDCLK1_P DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_SDCLK1_P
HYS - DISABLED
ODT - DISABLED
DSE - 40_OHM
DRAM_SDQS0_B DRAM_SDQS0_N
DRAM_SDQS0 DRAM_SDQS0_P DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_SDQS0_P
HYS - DISABLED SW_PAD_CTL_GRP_DDRMODE_CTL
PUS - 100K_OHM_PD SW_PAD_CTL_GRP_DDRHYS
PUE - PULL
PKE - DISABLED
ODT - DISABLED
DSE - 40_OHM
PUE - PULL
PKE - DISABLED
ODT - DISABLED
DSE - 40_OHM
PUE - PULL

Overview

PKE - DISABLED
ODT - DISABLED
DSE - 40_OHM
PUE - PULL
PKE - DISABLED
ODT - DISABLED
DSE - 40_OHM
PUE - PULL
PKE - DISABLED
ODT - DISABLED
DSE - 40_OHM
PUE - PULL
PKE - DISABLED
ODT - DISABLED
DSE - 40_OHM
PUE - PULL
PKE - DISABLED
ODT - DISABLED


DSE - 40_OHM
PUE - PULL
PKE - DISABLED
ODT - DISABLED
DSE - 40_OHM
DRAM_SDWE DRAM_SDWE_B DDR_SEL - LPDDR2 SW_PAD_CTL_PAD_DRAM_SDWE_B
ODT - DISABLED
DSE - 40_OHM
DSI_CLK0M DSI_CLK0_N
DSI_CLK0P DSI_CLK0_P
DSI_D0M DSI_DATA0_N
DSI_D0P DSI_DATA0_P
DSI_D1M DSI_DATA1_N
DSI_D1P DSI_DATA1_P
EIM_DA0 ALT0 EIM_AD00 HYS - DISABLED SW_PAD_CTL_PAD_EIM_AD00
ALT2 IPU2_CSI1_DATA09 PUE - PULL
ALT7 SRC_BOOT_CFG00 ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST

Overview

SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM


SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
ALT2 IPU2_CSI1_DATA_EN PUE - PULL
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
ALT2 IPU2_CSI1_HSYNC PUE - PULL

Overview

SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
ALT2 IPU2_CSI1_VSYNC PUE - PULL
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
ALT1 IPU1_DI1_D0_CS PUS - 100K_OHM_PU
ALT7 SRC_BOOT_CFG13 PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
ALT2 IPU1_DI1_PIN04 PUE - PULL
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
EIM_A16 ALT0 EIM_ADDR16 HYS - DISABLED SW_PAD_CTL_PAD_EIM_ADDR16
ALT1 IPU1_DI1_DISP_CLK PUS - 100K_OHM_PU
ALT2 IPU2_CSI1_PIXCLK PUE - PULL


SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST

Overview

SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
ALT3 IPU2_SISG3 PKE - ENABLED
ALT4 IPU1_SISG3 ODE - DISABLED
ALT7 SRC_BOOT_CFG23
DSE - 40_OHM
SRE - FAST
ALT3 IPU2_SISG2 PKE - ENABLED
ALT4 IPU1_SISG2 ODE - DISABLED
ALT7 SRC_BOOT_CFG24
DSE - 40_OHM
SRE - FAST
ALT1 ECSPI4_SS1 PUS - 100K_OHM_PU
ALT2 ECSPI2_RDY PUE - PULL
ALT3 IPU1_DI1_PIN12 PKE - ENABLED
ALT4 IPU1_DI0_D1_CS ODE - DISABLED
ALT6 HDMI_TX_CEC_LINE
DSE - 40_OHM


SRE - FAST
EIM_BCLK ALT0 EIM_BCLK HYS - DISABLED SW_PAD_CTL_PAD_EIM_BCLK
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
EIM_CS0 ALT0 EIM_CS0_B HYS - DISABLED SW_PAD_CTL_PAD_EIM_CS0_B
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
EIM_CS1 ALT0 EIM_CS1_B HYS - DISABLED SW_PAD_CTL_PAD_EIM_CS1_B
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
EIM_D16 ALT0 EIM_DATA16 HYS - ENABLED SW_PAD_CTL_PAD_EIM_DATA16
ALT1 ECSPI1_SCLK PUS - 100K_OHM_PU
ALT3 IPU2_CSI1_DATA18 PKE - ENABLED
ALT4 HDMI_TX_DDC_SDA ODE - DISABLED
ALT5 GPIO3_IO16
SPEED - MEDIUM
ALT6 I2C2_SDA
DSE - 40_OHM
SRE - SLOW
ALT1 ECSPI1_MISO PUS - 100K_OHM_PU
ALT3 IPU2_CSI1_PIXCLK PKE - ENABLED
ALT4 DCIC1_OUT ODE - DISABLED

Overview

ALT6 I2C3_SCL DSE - 40_OHM
SRE - SLOW
ALT1 ECSPI1_MOSI PUS - 100K_OHM_PU
ALT4 IPU1_DI1_D0_CS ODE - DISABLED
ALT6 I2C3_SDA
DSE - 40_OHM
SRE - SLOW
ALT4 UART1_CTS_B ODE - DISABLED
ALT6 EPIT1_OUT
DSE - 40_OHM
SRE - SLOW
ALT4 UART1_RTS_B ODE - DISABLED
ALT6 EPIT2_OUT
DSE - 40_OHM
SRE - SLOW
ALT4 USB_OTG_OC ODE - DISABLED
ALT6 I2C1_SCL
DSE - 40_OHM
ALT7 SPDIF_IN
SRE - SLOW


ALT4 USB_OTG_PWR ODE - DISABLED
ALT6 SPDIF_OUT DSE - 40_OHM
SRE - SLOW
ALT3 UART1_DCD_B PKE - ENABLED
ALT4 IPU2_CSI1_DATA_EN ODE - DISABLED
ALT6 IPU1_DI1_PIN02
DSE - 40_OHM
ALT7 IPU1_DI1_PIN14
SRE - SLOW
ALT4 ECSPI2_SS2 ODE - DISABLED
ALT6 AUD5_RXFS
DSE - 40_OHM
ALT7 UART1_DTR_B
SRE - SLOW
ALT4 ECSPI2_SS3 ODE - DISABLED
ALT6 AUD5_RXC
DSE - 40_OHM
ALT7 UART1_DSR_B
SRE - SLOW
ALT4 UART2_TX_DATA ODE - DISABLED
ALT6 IPU1_SISG2
DSE - 40_OHM
ALT7 IPU1_DISP1_DATA22
SRE - SLOW

Overview

ALT4 UART2_RX_DATA ODE - DISABLED
ALT6 IPU1_SISG3 DSE - 40_OHM
ALT7 IPU1_DISP1_DATA23 SRE - SLOW
ALT1 I2C1_SDA PUS - 100K_OHM_PU
ALT6 IPU1_EXT_TRIG
DSE - 40_OHM
ALT7 IPU1_DI0_PIN13
SRE - SLOW
ALT4 UART2_RTS_B PKE - ENABLED
ALT6 IPU2_CSI1_VSYNC SPEED - MEDIUM
ALT7 IPU1_DI0_PIN14
DSE - 40_OHM
SRE - SLOW
ALT6 USB_H1_OC
DSE - 40_OHM
SRE - SLOW
ALT6 USB_H1_PWR
DSE - 40_OHM


SRE - SLOW
EIM_EB0 ALT0 EIM_EB0_B HYS - DISABLED SW_PAD_CTL_PAD_EIM_EB0_B
ALT4 CCM_PMIC_READY PKE - ENABLED
ALT7 SRC_BOOT_CFG27 SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
EIM_EB1 ALT0 EIM_EB1_B HYS - DISABLED SW_PAD_CTL_PAD_EIM_EB1_B
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
EIM_EB2 ALT0 EIM_EB2_B HYS - ENABLED SW_PAD_CTL_PAD_EIM_EB2_B
ALT4 HDMI_TX_DDC_SCL PKE - ENABLED
ALT6 I2C2_SCL SPEED - MEDIUM
ALT7 SRC_BOOT_CFG30
DSE - 40_OHM
SRE - SLOW
EIM_EB3 ALT0 EIM_EB3_B HYS - ENABLED SW_PAD_CTL_PAD_EIM_EB3_B
ALT1 ECSPI4_RDY PUS - 100K_OHM_PU
ALT3 UART1_RI_B PKE - ENABLED
ALT4 IPU2_CSI1_HSYNC ODE - DISABLED
ALT5 GPIO2_IO31
SPEED - MEDIUM
ALT6 IPU1_DI1_PIN03
DSE - 40_OHM
ALT7 SRC_BOOT_CFG31
SRE - SLOW
EIM_LBA ALT0 EIM_LBA_B HYS - DISABLED SW_PAD_CTL_PAD_EIM_LBA_B

Overview

SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
EIM_OE ALT0 EIM_OE_B HYS - DISABLED SW_PAD_CTL_PAD_EIM_OE_B
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
EIM_RW ALT0 EIM_RW HYS - DISABLED SW_PAD_CTL_PAD_EIM_RW
SPEED - MEDIUM
DSE - 40_OHM
SRE - FAST
EIM_WAIT ALT0 EIM_WAIT_B HYS - DISABLED SW_PAD_CTL_PAD_EIM_WAIT_B
ALT1 EIM_DTACK_B PUS - 100K_OHM_PU
ODE - DISABLED
SPEED - MEDIUM
DSE - 60_OHM
SRE - SLOW
ENET_CRS_DV ALT1 ENET_RX_EN HYS - ENABLED SW_PAD_CTL_PAD_ENET_CRS_DV
ALT2 ESAI_TX_CLK PUS - 100K_OHM_PU
ALT3 SPDIF_EXT_CLK PUE - PULL
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ENET_MDC ALT0 MLB_DATA HYS - ENABLED SW_PAD_CTL_PAD_ENET_MDC
ALT1 ENET_MDC PUS - 100K_OHM_PU
ALT2 ESAI_TX5_RX0 PUE - PULL


ALT4 ENET_1588_EVENT1_IN PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ENET_MDIO ALT1 ENET_MDIO HYS - ENABLED SW_PAD_CTL_PAD_ENET_MDIO
ALT2 ESAI_RX_CLK PUS - 100K_OHM_PU
ALT4 ENET_1588_EVENT1_OU PUE - PULL
T
PKE - ENABLED
ALT5 GPIO1_IO22
ODE - DISABLED
ALT6 SPDIF_LOCK
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ENET_REF_CLK ALT1 ENET_TX_CLK HYS - ENABLED SW_PAD_CTL_PAD_ENET_REF_CLK
ALT2 ESAI_RX_FS PUS - 100K_OHM_PU
ALT6 SPDIF_SR_CLK PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ENET_RXD0 ALT0 XTALOSC_OSC32K_32K_ HYS - ENABLED SW_PAD_CTL_PAD_ENET_RX_DATA0
OUT
PUS - 100K_OHM_PU
ALT1 ENET_RX_DATA0
PUE - PULL
ALT2 ESAI_TX_HF_CLK
PKE - ENABLED
ALT3 SPDIF_OUT
ODE - DISABLED
ALT5 GPIO1_IO27
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ENET_RXD1 ALT0 MLB_SIG HYS - ENABLED SW_PAD_CTL_PAD_ENET_RX_DATA1
ALT1 ENET_RX_DATA1 PUS - 100K_OHM_PU
ALT2 ESAI_TX_FS PUE - PULL
ALT4 ENET_1588_EVENT3_OU PKE - ENABLED
T
ODE - DISABLED
ALT5 GPIO1_IO26
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ENET_RX_ER ALT0 USB_OTG_ID HYS - ENABLED SW_PAD_CTL_PAD_ENET_RX_ER

Overview

ALT1 ENET_RX_ER PUS - 100K_OHM_PU
ALT2 ESAI_RX_HF_CLK PUE - PULL
ALT3 SPDIF_IN PKE - ENABLED
ALT4 ENET_1588_EVENT2_OU ODE - DISABLED
T
SPEED - MEDIUM
ALT5 GPIO1_IO24
DSE - 40_OHM
SRE - SLOW
ENET_TXD0 ALT1 ENET_TX_DATA0 HYS - ENABLED SW_PAD_CTL_PAD_ENET_TX_DATA0
ALT2 ESAI_TX4_RX1 PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ENET_TXD1 ALT0 MLB_CLK HYS - ENABLED SW_PAD_CTL_PAD_ENET_TX_DATA1
ALT1 ENET_TX_DATA1 PUS - 100K_OHM_PU
ALT2 ESAI_TX2_RX3 PUE - PULL
ALT4 ENET_1588_EVENT0_IN PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ENET_TX_EN ALT1 ENET_TX_EN HYS - ENABLED SW_PAD_CTL_PAD_ENET_TX_EN
ALT2 ESAI_TX3_RX2 PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
GPIO_0 ALT0 CCM_CLKO1 HYS - ENABLED SW_PAD_CTL_PAD_GPIO00
ALT2 KEY_COL5 PUS - 100K_OHM_PU
ALT3 ASRC_EXT_CLK PUE - PULL
ALT4 EPIT1_OUT PKE - ENABLED
ALT6 USB_H1_PWR SPEED - MEDIUM
ALT7 SNVS_VIO_5
DSE - 40_OHM


SRE - SLOW
GPIO_1 ALT0 ESAI_RX_CLK HYS - ENABLED SW_PAD_CTL_PAD_GPIO01
ALT1 WDOG2_B PUS - 100K_OHM_PU
ALT2 KEY_ROW5 PUE - PULL
ALT3 USB_OTG_ID PKE - ENABLED
ALT4 PWM2_OUT ODE - DISABLED
ALT6 SD1_CD_B
DSE - 40_OHM
SRE - SLOW
GPIO_2 ALT0 ESAI_TX_FS HYS - ENABLED SW_PAD_CTL_PAD_GPIO02
ALT2 KEY_ROW6 PUS - 100K_OHM_PU
ALT6 SD2_WP PKE - ENABLED
ALT7 MLB_DATA ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
GPIO_3 ALT0 ESAI_RX_HF_CLK HYS - ENABLED SW_PAD_CTL_PAD_GPIO03
ALT2 I2C3_SCL PUS - 100K_OHM_PU
ALT3 XTALOSC_REF_CLK_24M PUE - PULL
ALT4 CCM_CLKO2 PKE - ENABLED
ALT6 USB_H1_OC SPEED - MEDIUM
ALT7 MLB_CLK
DSE - 40_OHM
SRE - SLOW
GPIO_4 ALT0 ESAI_TX_HF_CLK HYS - ENABLED SW_PAD_CTL_PAD_GPIO04
ALT2 KEY_COL7 PUS - 100K_OHM_PU
ALT6 SD2_CD_B PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
GPIO_5 ALT0 ESAI_TX2_RX3 HYS - ENABLED SW_PAD_CTL_PAD_GPIO05
ALT2 KEY_ROW7 PUS - 100K_OHM_PU
ALT3 CCM_CLKO1 PUE - PULL

Overview

ALT7 ARM_EVENTI SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
GPIO_6 ALT0 ESAI_TX_CLK HYS - ENABLED SW_PAD_CTL_PAD_GPIO06
ALT2 I2C3_SDA PUS - 100K_OHM_PU
ALT6 SD2_LCTL PKE - ENABLED
ALT7 MLB_SIG ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT1 ECSPI5_RDY PUS - 100K_OHM_PU
ALT2 EPIT1_OUT PUE - PULL
ALT3 FLEXCAN1_TX PKE - ENABLED
ALT6 SPDIF_LOCK
DSE - 40_OHM
ALT7 USB_OTG_HOST_MODE
SRE - SLOW
ALT1 XTALOSC_REF_CLK_32K PUS - 100K_OHM_PU
ALT2 EPIT2_OUT PUE - PULL
ALT3 FLEXCAN1_RX PKE - ENABLED
ALT6 SPDIF_SR_CLK
DSE - 40_OHM
ALT7 USB_OTG_PWR_CTL_WA
SRE - SLOW
KE
GPIO_9 ALT0 ESAI_RX_FS HYS - ENABLED SW_PAD_CTL_PAD_GPIO09
ALT1 WDOG1_B PUS - 100K_OHM_PU
ALT2 KEY_COL6 PUE - PULL
ALT3 CCM_REF_EN_B PKE - ENABLED
ALT4 PWM1_OUT ODE - DISABLED
ALT5 GPIO1_IO09
SPEED - MEDIUM
ALT6 SD1_WP
DSE - 40_OHM
SRE - SLOW
ALT1 ENET_1588_EVENT2_IN PUS - 100K_OHM_PU


ALT2 ENET_REF_CLK PUE - PULL
ALT3 SD1_LCTL PKE - ENABLED
ALT4 SPDIF_IN ODE - DISABLED
ALT6 I2C3_SDA DSE - 40_OHM
ALT7 JTAG_DE_B SRE - SLOW
GPIO_17 ALT0 ESAI_TX0 HYS - ENABLED SW_PAD_CTL_PAD_GPIO17
ALT1 ENET_1588_EVENT3_IN PUS - 100K_OHM_PU
ALT2 CCM_PMIC_READY PUE - PULL
ALT3 SDMA_EXT_EVENT0 PKE - ENABLED
ALT4 SPDIF_OUT ODE - DISABLED
DSE - 40_OHM
SRE - SLOW
GPIO_18 ALT0 ESAI_TX1 HYS - ENABLED SW_PAD_CTL_PAD_GPIO18
ALT1 ENET_RX_CLK PUS - 100K_OHM_PU
ALT2 SD3_VSELECT PUE - PULL
ALT3 SDMA_EXT_EVENT1 PKE - ENABLED
ALT4 ASRC_EXT_CLK ODE - DISABLED
ALT6 SNVS_VIO_5_CTL
DSE - 40_OHM
SRE - SLOW
GPIO_19 ALT0 KEY_COL5 HYS - ENABLED SW_PAD_CTL_PAD_GPIO19
ALT1 ENET_1588_EVENT0_OU PUS - 100K_OHM_PU
T
PUE - PULL
ALT2 SPDIF_OUT
PKE - ENABLED
ALT3 CCM_CLKO1
ODE - DISABLED
ALT4 ECSPI1_RDY
SPEED - MEDIUM
ALT5 GPIO4_IO05
DSE - 40_OHM
ALT6 ENET_TX_ER
SRE - SLOW
HDMI_CLKM HDMI_TX_CLK_N
HDMI_CLKP HDMI_TX_CLK_P
HDMI_D0M HDMI_TX_DATA0_N
HDMI_D0P HDMI_TX_DATA0_P

Overview

HDMI_DDCCEC HDMI_TX_DDC_CEC
HDMI_HPD HDMI_TX_HPD
JTAG_MOD JTAG_MOD HYS - DISABLED SW_PAD_CTL_PAD_JTAG_MOD
PUS - 100K_OHM_PU
PUE - PULL
PKE - ENABLED
ODE - DISABLED
SPEED - 50MHZ
DSE - 60_OHM
SRE - SLOW
JTAG_TCK JTAG_TCK HYS - DISABLED SW_PAD_CTL_PAD_JTAG_TCK
PUS - 47K_OHM_PU
PUE - PULL
PKE - ENABLED
ODE - DISABLED
SPEED - 50MHZ
DSE - 60_OHM
SRE - SLOW
JTAG_TDI JTAG_TDI HYS - DISABLED SW_PAD_CTL_PAD_JTAG_TDI
PUS - 47K_OHM_PU
PUE - PULL
PKE - ENABLED
ODE - DISABLED
SPEED - 50MHZ
DSE - 60_OHM
SRE - SLOW
JTAG_TDO JTAG_TDO HYS - DISABLED SW_PAD_CTL_PAD_JTAG_TDO
PUS - 100K_OHM_PU
PUE - KEEP
PKE - ENABLED
ODE - DISABLED
SPEED - 100MHZ
DSE - 40_OHM
SRE - FAST
JTAG_TMS JTAG_TMS HYS - DISABLED SW_PAD_CTL_PAD_JTAG_TMS
PUS - 47K_OHM_PU
PUE - PULL
PKE - ENABLED


ODE - DISABLED
SPEED - 50MHZ
DSE - 60_OHM
SRE - SLOW
JTAG_TRSTB JTAG_TRSTB HYS - DISABLED SW_PAD_CTL_PAD_JTAG_TRSTB
PUS - 47K_OHM_PU
PUE - PULL
PKE - ENABLED
ODE - DISABLED
SPEED - 50MHZ
DSE - 60_OHM
SRE - SLOW
KEY_COL0 ALT0 ECSPI1_SCLK HYS - ENABLED SW_PAD_CTL_PAD_KEY_COL0
ALT2 AUD5_TXC PUE - PULL
ALT6 DCIC1_OUT
DSE - 40_OHM
SRE - SLOW
KEY_COL1 ALT0 ECSPI1_MISO HYS - ENABLED SW_PAD_CTL_PAD_KEY_COL1
ALT1 ENET_MDIO PUS - 100K_OHM_PU
ALT2 AUD5_TXFS PUE - PULL
ALT6 SD1_VSELECT
DSE - 40_OHM
SRE - SLOW
KEY_COL2 ALT0 ECSPI1_SS1 HYS - ENABLED SW_PAD_CTL_PAD_KEY_COL2
ALT2 FLEXCAN1_TX PUE - PULL
ALT4 ENET_MDC ODE - DISABLED
ALT5 GPIO4_IO10
SPEED - MEDIUM
ALT6 USB_H1_PWR_CTL_WAK
DSE - 40_OHM
E
SRE - SLOW
KEY_COL3 ALT0 ECSPI1_SS3 HYS - ENABLED SW_PAD_CTL_PAD_KEY_COL3
ALT1 ENET_CRS PUS - 100K_OHM_PU

Overview

ALT2 HDMI_TX_DDC_SCL PUE - PULL
ALT6 SPDIF_IN DSE - 40_OHM
SRE - SLOW
KEY_COL4 ALT0 FLEXCAN2_TX HYS - ENABLED SW_PAD_CTL_PAD_KEY_COL4
ALT1 IPU1_SISG4 PUS - 100K_OHM_PU
ALT2 USB_OTG_OC PUE - PULL
DSE - 40_OHM
SRE - SLOW
KEY_ROW0 ALT0 ECSPI1_MOSI HYS - ENABLED SW_PAD_CTL_PAD_KEY_ROW0
ALT2 AUD5_TXD PUE - PULL
ALT6 DCIC2_OUT
DSE - 40_OHM
SRE - SLOW
KEY_ROW1 ALT0 ECSPI1_SS0 HYS - ENABLED SW_PAD_CTL_PAD_KEY_ROW1
ALT1 ENET_COL PUS - 100K_OHM_PU
ALT6 SD2_VSELECT
DSE - 40_OHM
SRE - SLOW
KEY_ROW2 ALT0 ECSPI1_SS2 HYS - ENABLED SW_PAD_CTL_PAD_KEY_ROW2
ALT2 FLEXCAN1_RX PUE - PULL
ALT4 SD2_VSELECT ODE - DISABLED
ALT6 HDMI_TX_CEC_LINE
DSE - 40_OHM
SRE - SLOW


KEY_ROW3 ALT0 XTALOSC_OSC32K_32K_ HYS - ENABLED SW_PAD_CTL_PAD_KEY_ROW3
OUT
PUS - 100K_OHM_PU
ALT1 ASRC_EXT_CLK
PUE - PULL
ALT2 HDMI_TX_DDC_SDA
PKE - ENABLED
ALT3 KEY_ROW3
ODE - DISABLED
ALT4 I2C2_SDA
SPEED - MEDIUM
ALT5 GPIO4_IO13
DSE - 40_OHM
ALT6 SD1_VSELECT
SRE - SLOW
KEY_ROW4 ALT0 FLEXCAN2_RX HYS - ENABLED SW_PAD_CTL_PAD_KEY_ROW4
ALT2 USB_OTG_PWR PUE - PULL
DSE - 40_OHM
SRE - SLOW
LVDS0_CLK_N LVDS0_CLK_N
LVDS0_CLK_P LVDS0_CLK_P
LVDS0_TX0_N LVDS0_DATA0_N
LVDS0_TX0_P LVDS0_DATA0_P
LVDS1_CLK_N LVDS1_CLK_N
LVDS1_CLK_P LVDS1_CLK_P
MLB_CN MLB_CLK_N
MLB_CP MLB_CLK_P
MLB_DN MLB_DATA_N

Overview

MLB_DP MLB_DATA_P
MLB_SN MLB_SIG_N
MLB_SP MLB_SIG_P
NANDF_ALE ALT0 NAND_ALE HYS - ENABLED SW_PAD_CTL_PAD_NAND_ALE
ALT1 SD4_RESET PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
NANDF_CLE ALT0 NAND_CLE HYS - ENABLED SW_PAD_CTL_PAD_NAND_CLE
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
NANDF_CS0 ALT0 NAND_CE0_B HYS - ENABLED SW_PAD_CTL_PAD_NAND_CS0_B
PUE - PULL
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT1 SD4_VSELECT PUS - 100K_OHM_PU
ALT2 SD3_VSELECT PUE - PULL
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 ESAI_TX0 PUE - PULL


ALT3 EIM_CRE PKE - ENABLED
ALT4 CCM_CLKO2 ODE - DISABLED
ALT6 IPU2_SISG0 DSE - 40_OHM
SRE - SLOW
ALT2 ESAI_TX1 PUE - PULL
ALT3 EIM_ADDR26 PKE - ENABLED
ALT6 IPU2_SISG1 SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
NANDF_D0 ALT0 NAND_DATA00 HYS - ENABLED SW_PAD_CTL_PAD_NAND_DATA00
ALT1 SD1_DATA4 PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW

Overview

PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM


SRE - SLOW
NANDF_RB0 ALT0 NAND_READY_B HYS - ENABLED SW_PAD_CTL_PAD_NAND_READY_B
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
NANDF_WP_B ALT0 NAND_WP_B HYS - ENABLED SW_PAD_CTL_PAD_NAND_WP_B
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ONOFF SRC_ONOFF
PCIE_RXM PCIE_RX_N
PCIE_RXP PCIE_RX_P
PCIE_TXM PCIE_TX_N
PCIE_TXP PCIE_TX_P
PMIC_ON_REQ SNVS_PMIC_ON_REQ
PMIC_STBY_REQ CCM_PMIC_STBY_REQ
POR_B SRC_POR_B
RGMII_RD0 ALT0 HSI_RX_READY DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_RD0
ALT1 RGMII_RD0 HYS - ENABLED SW_PAD_CTL_GRP_DDR_TYPE_RGMII
ALT5 GPIO6_IO25 PUS - 100K_OHM_PU SW_PAD_CTL_GRP_RGMII_TERM
PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_RD1 ALT0 HSI_TX_FLAG DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_RD1
PUE - PULL
PKE - ENABLED
ODT - DISABLED

Overview

DSE - 37_OHM
RGMII_RD2 ALT0 HSI_TX_DATA DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_RD2
PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_RD3 ALT0 HSI_TX_WAKE DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_RD3
PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_RXC ALT0 USB_H3_STROBE DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_RXC
ALT1 RGMII_RXC HYS - ENABLED SW_PAD_CTL_GRP_DDR_TYPE_RGMII
ALT5 GPIO6_IO30 PUS - 100K_OHM_PD SW_PAD_CTL_GRP_RGMII_TERM
PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_RX_CTL ALT0 USB_H3_DATA DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_RX_CTL
ALT1 RGMII_RX_CTL HYS - ENABLED SW_PAD_CTL_GRP_DDR_TYPE_RGMII
ALT5 GPIO6_IO24 PUS - 100K_OHM_PD SW_PAD_CTL_GRP_RGMII_TERM
PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_TD0 ALT0 HSI_TX_READY DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_TD0
ALT1 RGMII_TD0 HYS - ENABLED SW_PAD_CTL_GRP_DDR_TYPE_RGMII
PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_TD1 ALT0 HSI_RX_FLAG DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_TD1


PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_TD2 ALT0 HSI_RX_DATA DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_TD2
PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_TD3 ALT0 HSI_RX_WAKE DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_TD3
PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_TXC ALT0 USB_H2_DATA DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_TXC
ALT1 RGMII_TXC HYS - ENABLED SW_PAD_CTL_GRP_DDR_TYPE_RGMII
ALT2 SPDIF_EXT_CLK PUS - 100K_OHM_PD
ALT7 XTALOSC_REF_CLK_24M PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RGMII_TX_CTL ALT0 USB_H2_STROBE DDR_SEL - 1P2V_IO SW_PAD_CTL_PAD_RGMII_TX_CTL
ALT1 RGMII_TX_CTL HYS - ENABLED SW_PAD_CTL_GRP_DDR_TYPE_RGMII
ALT5 GPIO6_IO26 PUS - 100K_OHM_PD
ALT7 ENET_REF_CLK PUE - PULL
PKE - ENABLED
ODT - DISABLED
DSE - 37_OHM
RTC_XTALI XTALOSC_RTC_XTALI
RTC_XTALO XTALOSC_RTC_XTALO
SATA_RXM SATA_PHY_RX_N
SATA_RXP SATA_PHY_RX_P
SATA_TXM SATA_PHY_TX_N

Overview

SATA_TXP SATA_PHY_TX_P
SD1_CLK ALT0 SD1_CLK HYS - ENABLED SW_PAD_CTL_PAD_SD1_CLK
ALT2 XTALOSC_OSC32K_32K_ PUE - PULL
OUT
PKE - ENABLED
ALT3 GPT_CLKIN
ODE - DISABLED
ALT5 GPIO1_IO20
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
SD1_CMD ALT0 SD1_CMD HYS - ENABLED SW_PAD_CTL_PAD_SD1_CMD
ALT3 GPT_COMPARE1 PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
SD1_DAT0 ALT0 SD1_DATA0 HYS - ENABLED SW_PAD_CTL_PAD_SD1_DATA0
ALT3 GPT_CAPTURE1 PUE - PULL
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT3 GPT_CAPTURE2 PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 GPT_COMPARE2 PUE - PULL
ALT3 PWM2_OUT PKE - ENABLED
ALT4 WDOG1_B


ALT6 WDOG1_RESET_B_DEB SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 GPT_COMPARE3 PUE - PULL
ALT3 PWM1_OUT PKE - ENABLED
ALT4 WDOG2_B ODE - DISABLED
ALT6 WDOG2_RESET_B_DEB
DSE - 40_OHM
SRE - SLOW
ALT3 AUD4_RXFS PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 KEY_ROW5 PUE - PULL
ALT3 AUD4_RXC PKE - ENABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT6 DCIC2_OUT
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW

Overview

ALT2 EIM_CS2_B PUE - PULL
ALT4 KEY_COL7 ODE - DISABLED
DSE - 40_OHM
SRE - SLOW
ALT2 EIM_CS3_B PUE - PULL
ALT4 KEY_ROW6 ODE - DISABLED
DSE - 40_OHM
SRE - SLOW
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT1 UART2_RTS_B PUS - 100K_OHM_PU
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT1 UART2_CTS_B PUS - 100K_OHM_PU
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW


ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PUE - PULL
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT1 UART2_RX_DATA PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED

Overview

SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT1 UART2_TX_DATA PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
SD3_RST ALT0 SD3_RESET HYS - ENABLED SW_PAD_CTL_PAD_SD3_RESET
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT1 NAND_WE_B PUS - 100K_OHM_PU


ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT1 NAND_RE_B PUS - 100K_OHM_PU
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 NAND_DQS PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 PWM3_OUT PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
ALT2 PWM4_OUT PUS - 100K_OHM_PU
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW

Overview

PUE - PULL
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM
SRE - SLOW
PKE - ENABLED
ODE - DISABLED
SPEED - MEDIUM
DSE - 40_OHM


SRE - SLOW
TAMPER SNVS_TAMPER
TEST_MODE TCU_TEST_MODE
USB_H1_DN USB_H1_DN
USB_H1_DP USB_H1_DP
USB_H1_VBUS USB_H1_VBUS
USB_OTG_CHD_ USB_OTG_CHD_B
B
USB_OTG_DN USB_OTG_DN
USB_OTG_DP USB_OTG_DP
USB_OTG_VBUS USB_OTG_VBUS
XTALI XTALOSC_XTALI
XTALO XTALOSC_XTALO
4.1.2 Muxing Options

An additional view of external signals muxing is shown by the presentation of the
muxing options per block/instance.
Table 4-2. Muxing Options
Signal Pad (Mode) Mux/Input Select Registers
ARM - ARM Platform
ARM_EVENTI GPIO_5 (ALT7) IOMUXC_SW_MUX_CTL_PAD_GPIO05
ARM_EVENTO CSI0_PIXCLK (ALT7) IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK
ARM_TRACE00 CSI0_VSYNC (ALT7) IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC
ARM_TRACE01 CSI0_DAT4 (ALT7) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04

Overview
Table 4-2. Muxing Options (continued)

ARM_TRACE_CLK CSI0_DATA_EN (ALT7) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN
ARM_TRACE_CTL CSI0_MCLK (ALT7) IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC
ASRC - Asynchronous Sample Rate Converter
ASRC_EXT_CLK GPIO_0 (ALT3) IOMUXC_SW_MUX_CTL_PAD_GPIO00
IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT
GPIO_18 (ALT4) IOMUXC_SW_MUX_CTL_PAD_GPIO18
KEY_ROW3 (ALT1) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3
AUDMUX - Digital Audio Multiplexer
AUD3_RXC CSI0_DAT10 (ALT1) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10
AUD3_RXD CSI0_DAT7 (ALT4) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07
AUD3_RXFS CSI0_DAT11 (ALT1) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11
AUD3_TXC CSI0_DAT4 (ALT4) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04
AUD3_TXD CSI0_DAT5 (ALT4) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05
AUD3_TXFS CSI0_DAT6 (ALT4) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06
AUD4_RXC DISP0_DAT19 (ALT4) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19
IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT
SD2_CMD (ALT3) IOMUXC_SW_MUX_CTL_PAD_SD2_CMD
AUD4_RXD DISP0_DAT23 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23
IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT
SD2_DAT0 (ALT3) IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0
AUD4_RXFS DISP0_DAT18 (ALT4) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18
IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT
SD2_CLK (ALT3) IOMUXC_SW_MUX_CTL_PAD_SD2_CLK
AUD4_TXC DISP0_DAT20 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20
IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT
AUD4_TXD DISP0_DAT21 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21
IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT
AUD4_TXFS DISP0_DAT22 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22


IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT
EIM_D25 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25
AUD5_RXD DISP0_DAT19 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19
AUD5_TXC DISP0_DAT16 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16
KEY_COL0 (ALT2) IOMUXC_SW_MUX_CTL_PAD_KEY_COL0
AUD5_TXD DISP0_DAT17 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17
AUD5_TXFS DISP0_DAT18 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18
AUD6_RXD DI0_PIN4 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04
AUD6_TXC DI0_PIN15 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15
AUD6_TXD DI0_PIN2 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02
AUD6_TXFS DI0_PIN3 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03
CCM - Clock Controller Module
CCM_CLKO1 CSI0_MCLK (ALT3) IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC
CCM_CLKO2 GPIO_3 (ALT4) IOMUXC_SW_MUX_CTL_PAD_GPIO03

Overview

NANDF_CS2 (ALT4) IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B
CCM_PMIC_READY EIM_EB0 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B
IOMUXC_CCM_PMIC_READY_SELECT_INPUT
IOMUXC_CCM_PMIC_READY_SELECT_INPUT
CCM_PMIC_STBY_REQ PMIC_STBY_REQ Not multiplexed.
CCM_REF_EN_B GPIO_9 (ALT3) IOMUXC_SW_MUX_CTL_PAD_GPIO09
DCIC1 - Display Content Integrity Checker
DCIC1_OUT EIM_D17 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17
DCIC2 - Display Content Integrity Checker
DCIC2_OUT KEY_ROW0 (ALT6) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0
ECSPI1 - Enhanced Configurable SPI
ECSPI1_MISO CSI0_DAT6 (ALT2) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06
IOMUXC_ECSPI1_MISO_SELECT_INPUT
DISP0_DAT22 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22
ECSPI1_MOSI CSI0_DAT5 (ALT2) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05
IOMUXC_ECSPI1_MOSI_SELECT_INPUT
ECSPI1_RDY GPIO_19 (ALT4) IOMUXC_SW_MUX_CTL_PAD_GPIO19
ECSPI1_SCLK CSI0_DAT4 (ALT2) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04
IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT


ECSPI1_SS0 CSI0_DAT7 (ALT2) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07
IOMUXC_ECSPI1_SS0_SELECT_INPUT
EIM_EB2 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B
ECSPI1_SS1 DISP0_DAT15 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15
ECSPI1_SS2 EIM_D24 (ALT3) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24
ECSPI2_MISO CSI0_DAT10 (ALT2) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10
EIM_OE (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B
ECSPI2_MOSI CSI0_DAT9 (ALT2) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09
EIM_CS1 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B
ECSPI2_RDY EIM_A25 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25
ECSPI2_SCLK CSI0_DAT8 (ALT2) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08

Overview

EIM_CS0 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B
ECSPI2_SS0 CSI0_DAT11 (ALT2) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11
EIM_RW (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_RW
EIM_LBA (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B
ECSPI3_MISO DISP0_DAT2 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02
ECSPI3_MOSI DISP0_DAT1 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01
ECSPI3_RDY DISP0_DAT7 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07
ECSPI3_SCLK DISP0_DAT0 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00
ECSPI4_MISO EIM_D22 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22
ECSPI4_MOSI EIM_D28 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28
ECSPI4_RDY EIM_EB3 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B
ECSPI4_SCLK EIM_D21 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21
ECSPI4_SS1 EIM_A25 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25
ECSPI5_MISO SD1_DAT0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0


ECSPI5_MOSI SD1_CMD (ALT1) IOMUXC_SW_MUX_CTL_PAD_SD1_CMD
ECSPI5_RDY GPIO_7 (ALT1) IOMUXC_SW_MUX_CTL_PAD_GPIO07
ECSPI5_SCLK SD1_CLK (ALT1) IOMUXC_SW_MUX_CTL_PAD_SD1_CLK
ECSPI5_SS0 SD1_DAT1 (ALT1) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1
EIM - External Interface Module
EIM_AD00 EIM_DA0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_AD00

Overview

EIM_ADDR16 EIM_A16 (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16
EIM_ADDR26 NANDF_CS3 (ALT3) IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B
EIM_BCLK EIM_BCLK (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK
EIM_CRE NANDF_CS2 (ALT3) IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B
EIM_CS0_B EIM_CS0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B
EIM_CS1_B EIM_CS1 (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B
EIM_CS2_B DISP0_DAT18 (ALT7) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18
EIM_CS3_B DISP0_DAT19 (ALT7) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19
EIM_DATA00 CSI0_DATA_EN (ALT1) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN
EIM_DATA01 CSI0_VSYNC (ALT1) IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC
EIM_DATA02 CSI0_DAT4 (ALT1) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04
EIM_DATA16 EIM_D16 (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16


EIM_DTACK_B EIM_WAIT (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B
EIM_EB0_B EIM_EB0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B
EIM_LBA_B EIM_LBA (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B
EIM_OE_B EIM_OE (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B
EIM_RW EIM_RW (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_RW
EIM_WAIT_B EIM_WAIT (ALT0) IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B
ENET - 10/100/1000-Mbps Ethernet MAC
ENET_1588_EVENT0_IN ENET_TXD1 (ALT4) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1
ENET_1588_EVENT0_OUT GPIO_19 (ALT1) IOMUXC_SW_MUX_CTL_PAD_GPIO19
ENET_1588_EVENT1_IN ENET_MDC (ALT4) IOMUXC_SW_MUX_CTL_PAD_ENET_MDC
ENET_1588_EVENT1_OUT ENET_MDIO (ALT4) IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO
ENET_1588_EVENT2_IN GPIO_16 (ALT1) IOMUXC_SW_MUX_CTL_PAD_GPIO16
ENET_1588_EVENT2_OUT ENET_RX_ER (ALT4) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER
ENET_1588_EVENT3_IN GPIO_17 (ALT1) IOMUXC_SW_MUX_CTL_PAD_GPIO17
ENET_1588_EVENT3_OUT ENET_RXD1 (ALT4) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1
ENET_COL KEY_ROW1 (ALT1) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1
ENET_CRS KEY_COL3 (ALT1) IOMUXC_SW_MUX_CTL_PAD_KEY_COL3
ENET_MDC ENET_MDC (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_MDC
ENET_MDIO ENET_MDIO (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO
IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT
IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT
ENET_REF_CLK GPIO_16 (ALT2) IOMUXC_SW_MUX_CTL_PAD_GPIO16

Overview

IOMUXC_ENET_REF_CLK_SELECT_INPUT
RGMII_TX_CTL (ALT7) IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL
IOMUXC_ENET_REF_CLK_SELECT_INPUT
ENET_RX_CLK GPIO_18 (ALT1) IOMUXC_SW_MUX_CTL_PAD_GPIO18
IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT
ENET_RX_DATA0 ENET_RXD0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0
IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT
ENET_RX_DATA1 ENET_RXD1 (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1
ENET_RX_DATA2 KEY_COL2 (ALT1) IOMUXC_SW_MUX_CTL_PAD_KEY_COL2
ENET_RX_DATA3 KEY_COL0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_KEY_COL0
ENET_RX_EN ENET_CRS_DV (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV
IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT
ENET_RX_ER ENET_RX_ER (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER
ENET_TX_CLK ENET_REF_CLK (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK
ENET_TX_DATA0 ENET_TXD0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0
ENET_TX_DATA1 ENET_TXD1 (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1
ENET_TX_DATA2 KEY_ROW2 (ALT1) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2
ENET_TX_DATA3 KEY_ROW0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0
ENET_TX_EN ENET_TX_EN (ALT1) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN
ENET_TX_ER GPIO_19 (ALT6) IOMUXC_SW_MUX_CTL_PAD_GPIO19
RGMII_RD0 RGMII_RD0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0
RGMII_RXC RGMII_RXC (ALT1) IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC
IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT
RGMII_RX_CTL RGMII_RX_CTL (ALT1) IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL
IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT
RGMII_TD0 RGMII_TD0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0


RGMII_TXC RGMII_TXC (ALT1) IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC
RGMII_TX_CTL RGMII_TX_CTL (ALT1) IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL
EPIT1 - Enhanced Periodic Interrupt Timer
EPIT1_OUT EIM_D19 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19
EPIT2 - Enhanced Periodic Interrupt Timer
EPIT2_OUT EIM_D20 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20
ESAI - Enhanced Serial Audio Interface
ESAI_RX_CLK ENET_MDIO (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO
IOMUXC_ESAI_RX_CLK_SELECT_INPUT
IOMUXC_ESAI_RX_CLK_SELECT_INPUT
ESAI_RX_FS ENET_REF_CLK (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK
IOMUXC_ESAI_RX_FS_SELECT_INPUT
IOMUXC_ESAI_RX_FS_SELECT_INPUT
ESAI_RX_HF_CLK ENET_RX_ER (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER
IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT
IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT
ESAI_TX0 GPIO_17 (ALT0) IOMUXC_SW_MUX_CTL_PAD_GPIO17
IOMUXC_ESAI_SDO0_SELECT_INPUT
ESAI_TX1 GPIO_18 (ALT0) IOMUXC_SW_MUX_CTL_PAD_GPIO18
ESAI_TX2_RX3 ENET_TXD1 (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1
IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT
ESAI_TX3_RX2 ENET_TX_EN (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN
ESAI_TX4_RX1 ENET_TXD0 (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0

Overview

ESAI_TX5_RX0 ENET_MDC (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_MDC
ESAI_TX_CLK ENET_CRS_DV (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV
IOMUXC_ESAI_TX_CLK_SELECT_INPUT
IOMUXC_ESAI_TX_CLK_SELECT_INPUT
ESAI_TX_FS ENET_RXD1 (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1
IOMUXC_ESAI_TX_FS_SELECT_INPUT
IOMUXC_ESAI_TX_FS_SELECT_INPUT
ESAI_TX_HF_CLK ENET_RXD0 (ALT2) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0
IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT
IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT
FLEXCAN1 - Flexible Controller Area Network
FLEXCAN1_RX GPIO_8 (ALT3) IOMUXC_SW_MUX_CTL_PAD_GPIO08
IOMUXC_FLEXCAN1_RX_SELECT_INPUT
FLEXCAN1_TX GPIO_7 (ALT3) IOMUXC_SW_MUX_CTL_PAD_GPIO07
FLEXCAN2 - Flexible Controller Area Network
FLEXCAN2_RX KEY_ROW4 (ALT0) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4
FLEXCAN2_TX KEY_COL4 (ALT0) IOMUXC_SW_MUX_CTL_PAD_KEY_COL4
GPIO1 - General Purpose Input/Output
GPIO1_IO00 GPIO_0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_GPIO00


GPIO1_IO10 SD2_CLK (ALT5) IOMUXC_SW_MUX_CTL_PAD_SD2_CLK
GPIO1_IO11 SD2_CMD (ALT5) IOMUXC_SW_MUX_CTL_PAD_SD2_CMD
GPIO1_IO12 SD2_DAT3 (ALT5) IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3
GPIO1_IO22 ENET_MDIO (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO
GPIO1_IO23 ENET_REF_CLK (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK
GPIO1_IO24 ENET_RX_ER (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER
GPIO1_IO25 ENET_CRS_DV (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV
GPIO1_IO26 ENET_RXD1 (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1
GPIO1_IO27 ENET_RXD0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0
GPIO1_IO28 ENET_TX_EN (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN
GPIO1_IO29 ENET_TXD1 (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1
GPIO1_IO30 ENET_TXD0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0
GPIO1_IO31 ENET_MDC (ALT5) IOMUXC_SW_MUX_CTL_PAD_ENET_MDC
GPIO2_IO00 NANDF_D0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00

Overview

GPIO2_IO16 EIM_A22 (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22
GPIO2_IO23 EIM_CS0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B
GPIO2_IO24 EIM_CS1 (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B
GPIO2_IO25 EIM_OE (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B
GPIO2_IO26 EIM_RW (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_RW
GPIO2_IO27 EIM_LBA (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B
GPIO2_IO28 EIM_EB0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B
GPIO3_IO00 EIM_DA0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_AD00


GPIO3_IO16 EIM_D16 (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16
GPIO4_IO06 KEY_COL0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_KEY_COL0
GPIO4_IO07 KEY_ROW0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0
GPIO4_IO16 DI0_DISP_CLK (ALT5) IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK
GPIO4_IO17 DI0_PIN15 (ALT5) IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15
GPIO4_IO21 DISP0_DAT0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00

Overview

GPIO5_IO00 EIM_WAIT (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B
GPIO5_IO18 CSI0_PIXCLK (ALT5) IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK
GPIO5_IO19 CSI0_MCLK (ALT5) IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC
GPIO5_IO20 CSI0_DATA_EN (ALT5) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN
GPIO5_IO21 CSI0_VSYNC (ALT5) IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC
GPIO5_IO22 CSI0_DAT4 (ALT5) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04


GPIO6_IO07 NANDF_CLE (ALT5) IOMUXC_SW_MUX_CTL_PAD_NAND_CLE
GPIO6_IO08 NANDF_ALE (ALT5) IOMUXC_SW_MUX_CTL_PAD_NAND_ALE
GPIO6_IO09 NANDF_WP_B (ALT5) IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B
GPIO6_IO10 NANDF_RB0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B
GPIO6_IO11 NANDF_CS0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B
GPIO6_IO19 RGMII_TXC (ALT5) IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC
GPIO6_IO20 RGMII_TD0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0
GPIO6_IO24 RGMII_RX_CTL (ALT5) IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL
GPIO6_IO25 RGMII_RD0 (ALT5) IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0
GPIO6_IO26 RGMII_TX_CTL (ALT5) IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL
GPIO6_IO30 RGMII_RXC (ALT5) IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC
GPIO6_IO31 EIM_BCLK (ALT5) IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK

Overview

GPIO7_IO08 SD3_RST (ALT5) IOMUXC_SW_MUX_CTL_PAD_SD3_RESET
GPMI - General Purpose Media Interface
NAND_ALE NANDF_ALE (ALT0) IOMUXC_SW_MUX_CTL_PAD_NAND_ALE
NAND_CE0_B NANDF_CS0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B
NAND_CLE NANDF_CLE (ALT0) IOMUXC_SW_MUX_CTL_PAD_NAND_CLE
NAND_DATA00 NANDF_D0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00
NAND_DQS SD4_DAT0 (ALT2) IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0
NAND_READY_B NANDF_RB0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B
NAND_RE_B SD4_CMD (ALT1) IOMUXC_SW_MUX_CTL_PAD_SD4_CMD
NAND_WE_B SD4_CLK (ALT1) IOMUXC_SW_MUX_CTL_PAD_SD4_CLK
NAND_WP_B NANDF_WP_B (ALT0) IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B
GPT - General Purpose Timer
GPT_CAPTURE1 SD1_DAT0 (ALT3) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0
GPT_CAPTURE2 SD1_DAT1 (ALT3) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1
GPT_CLKIN SD1_CLK (ALT3) IOMUXC_SW_MUX_CTL_PAD_SD1_CLK
GPT_COMPARE1 SD1_CMD (ALT3) IOMUXC_SW_MUX_CTL_PAD_SD1_CMD
GPT_COMPARE2 SD1_DAT2 (ALT2) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2
GPT_COMPARE3 SD1_DAT3 (ALT2) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3
HDMI - High Definition Multimedia Interface
HDMI_TX_CEC_LINE EIM_A25 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25
IOMUXC_HDMI_ICECIN_SELECT_INPUT
IOMUXC_HDMI_ICECIN_SELECT_INPUT
HDMI_TX_CLK_N HDMI_CLKM Not multiplexed.


HDMI_TX_CLK_P HDMI_CLKP Not multiplexed.
HDMI_TX_DATA0_N HDMI_D0M Not multiplexed.
HDMI_TX_DATA0_P HDMI_D0P Not multiplexed.
HDMI_TX_DDC_CEC HDMI_DDCCEC Not multiplexed.
HDMI_TX_DDC_SCL EIM_EB2 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B
IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT
IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT
HDMI_TX_DDC_SDA EIM_D16 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16
IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT
IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT
HDMI_TX_HPD HDMI_HPD Not multiplexed.
I2C1 - I2C Controller
I2C1_SCL CSI0_DAT9 (ALT4) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09
IOMUXC_I2C1_SCL_IN_SELECT_INPUT
I2C1_SDA CSI0_DAT8 (ALT4) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08
IOMUXC_I2C1_SDA_IN_SELECT_INPUT
I2C2_SCL EIM_EB2 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B
I2C2_SDA EIM_D16 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16
I2C3_SCL EIM_D17 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17

Overview

I2C3_SDA EIM_D18 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18
IPU1 - Image Processing Unit
IPU1_CSI0_DATA00 EIM_D27 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27
IPU1_CSI0_DATA04 CSI0_DAT4 (ALT0) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04
IPU1_CSI0_DATA_EN CSI0_DATA_EN (ALT0) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN
IPU1_CSI0_HSYNC CSI0_MCLK (ALT0) IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC
IPU1_CSI0_PIXCLK CSI0_PIXCLK (ALT0) IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK
IPU1_CSI0_VSYNC CSI0_VSYNC (ALT0) IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC
IPU1_DI0_D0_CS EIM_D23 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23
IPU1_DI0_D1_CS EIM_A25 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25
IPU1_DI0_DISP_CLK DI0_DISP_CLK (ALT0) IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK
IPU1_DI0_PIN01 EIM_D22 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22
IPU1_DI0_PIN02 DI0_PIN2 (ALT0) IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02


IPU1_DI1_D0_CS EIM_DA13 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_AD13
IPU1_DI1_D1_CS EIM_DA14 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_AD14
IPU1_DI1_DISP_CLK EIM_A16 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16
IPU1_DI1_PIN01 EIM_DA15 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_AD15
IPU1_DI1_PIN05 EIM_CS0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B
IPU1_DI1_PIN06 EIM_CS1 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B
IPU1_DI1_PIN07 EIM_OE (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B
IPU1_DI1_PIN08 EIM_RW (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_RW
IPU1_DI1_PIN12 EIM_A25 (ALT3) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25
IPU1_DI1_PIN16 EIM_BCLK (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK
IPU1_DI1_PIN17 EIM_LBA (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B
IPU1_DISP0_DATA00 DISP0_DAT0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00

Overview

IPU1_DISP1_DATA00 EIM_DA9 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_AD09
IPU1_DISP1_DATA10 EIM_EB1 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B
IPU1_DISP1_DATA11 EIM_EB0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B
IPU1_DISP1_DATA12 EIM_A17 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17


IPU1_DISP1_DATA20 EIM_D31 (ALT1) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31
IPU1_EXT_TRIG EIM_D28 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28
IPU1_SISG0 NANDF_CS2 (ALT1) IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B
IPU1_SISG2 EIM_A24 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24
IPU1_SISG4 KEY_COL4 (ALT1) IOMUXC_SW_MUX_CTL_PAD_KEY_COL4
IPU1_SISG5 KEY_ROW4 (ALT1) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4
IPU2 - Image Processing Unit
IPU2_CSI1_DATA00 EIM_DA9 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_AD09
IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT
IPU2_CSI1_DATA12 EIM_A17 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17

Overview

IPU2_CSI1_DATA_EN EIM_DA10 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_AD10
IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT
IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT
IPU2_CSI1_HSYNC EIM_DA11 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_AD11
IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT
IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT
IPU2_CSI1_PIXCLK EIM_A16 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16
IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT
IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT


IPU2_CSI1_VSYNC EIM_DA12 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_AD12
IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT
IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT
IPU2_DI0_DISP_CLK DI0_DISP_CLK (ALT1) IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK
IPU2_DI0_PIN01 NANDF_RB0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B
IPU2_SISG4 NANDF_CLE (ALT1) IOMUXC_SW_MUX_CTL_PAD_NAND_CLE

Overview

IPU2_SISG5 NANDF_WP_B (ALT1) IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B
KPP - Keypad Port
KEY_COL0 KEY_COL0 (ALT3) IOMUXC_SW_MUX_CTL_PAD_KEY_COL0
KEY_COL5 CSI0_DAT4 (ALT3) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04
IOMUXC_KEY_COL5_SELECT_INPUT
KEY_ROW0 KEY_ROW0 (ALT3) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0
KEY_ROW5 CSI0_DAT5 (ALT3) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05
IOMUXC_KEY_ROW5_SELECT_INPUT


LDB - LVDS Display Bridge
LVDS0_CLK_N LVDS0_CLK_N Not multiplexed.
LVDS0_CLK_P LVDS0_CLK_P Not multiplexed.
LVDS0_DATA0_N LVDS0_TX0_N Not multiplexed.
LVDS0_DATA0_P LVDS0_TX0_P Not multiplexed.
LVDS1_CLK_N LVDS1_CLK_N Not multiplexed.
LVDS1_CLK_P LVDS1_CLK_P Not multiplexed.
MIPI_CSI - MIPI Camera Serial Interface
CSI_CLK0_N CSI_CLK0M Not multiplexed.
CSI_CLK0_P CSI_CLK0P Not multiplexed.
CSI_DATA0_N CSI_D0M Not multiplexed.
CSI_DATA0_P CSI_D0P Not multiplexed.

Overview

MIPI_DSI - MIPI Display Serial Interface
DSI_CLK0_N DSI_CLK0M Not multiplexed.
DSI_CLK0_P DSI_CLK0P Not multiplexed.
DSI_DATA0_N DSI_D0M Not multiplexed.
DSI_DATA0_P DSI_D0P Not multiplexed.
DSI_DATA1_N DSI_D1M Not multiplexed.
DSI_DATA1_P DSI_D1P Not multiplexed.
MIPI_HSI - MIPI High Speed Synchronous Interface
HSI_RX_DATA RGMII_TD2 (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2
HSI_RX_FLAG RGMII_TD1 (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1
HSI_RX_READY RGMII_RD0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0
HSI_RX_WAKE RGMII_TD3 (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3
HSI_TX_DATA RGMII_RD2 (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2
HSI_TX_FLAG RGMII_RD1 (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1
HSI_TX_READY RGMII_TD0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0
HSI_TX_WAKE RGMII_RD3 (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3
MLB - Media Local Bus
MLB_CLK ENET_TXD1 (ALT0) IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1
IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT
IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT
MLB_CLK_N MLB_CN Not multiplexed.
MLB_CLK_P MLB_CP Not multiplexed.
MLB_DATA ENET_MDC (ALT0) IOMUXC_SW_MUX_CTL_PAD_ENET_MDC
IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT
IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT
MLB_DATA_N MLB_DN Not multiplexed.
MLB_DATA_P MLB_DP Not multiplexed.
MLB_SIG ENET_RXD1 (ALT0) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1
IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT
IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT
MLB_SIG_N MLB_SN Not multiplexed.
MLB_SIG_P MLB_SP Not multiplexed.


MMDC - Multi Mode DDR Controller
DRAM_ADDR00 DRAM_A0 Not multiplexed.
DRAM_CAS_B DRAM_CAS Not multiplexed.
DRAM_CS0_B DRAM_CS0 Not multiplexed.
DRAM_CS1_B DRAM_CS1 Not multiplexed.
DRAM_DATA00 DRAM_D0 Not multiplexed.

Overview



DRAM_DQM0 DRAM_DQM0 Not multiplexed.
DRAM_ODT0 DRAM_SDODT0 Not multiplexed.
DRAM_ODT1 DRAM_SDODT1 Not multiplexed.
DRAM_RAS_B DRAM_RAS Not multiplexed.
DRAM_RESET DRAM_RESET Not multiplexed.
DRAM_SDBA0 DRAM_SDBA0 Not multiplexed.
DRAM_SDCKE0 DRAM_SDCKE0 Not multiplexed.
DRAM_SDCKE1 DRAM_SDCKE1 Not multiplexed.
DRAM_SDCLK0_N DRAM_SDCLK_0_B Not multiplexed.
DRAM_SDCLK0_P DRAM_SDCLK_0 Not multiplexed.
DRAM_SDCLK1_N DRAM_SDCLK_1_B Not multiplexed.
DRAM_SDCLK1_P DRAM_SDCLK_1 Not multiplexed.
DRAM_SDQS0_N DRAM_SDQS0_B Not multiplexed.
DRAM_SDQS0_P DRAM_SDQS0 Not multiplexed.

Overview

DRAM_SDWE_B DRAM_SDWE Not multiplexed.
PCIE - PCI Express
PCIE_RX_N PCIE_RXM Not multiplexed.
PCIE_RX_P PCIE_RXP Not multiplexed.
PCIE_TX_N PCIE_TXM Not multiplexed.
PCIE_TX_P PCIE_TXP Not multiplexed.
PMU - Power Management Unit
CSI_REXT CSI_REXT Not multiplexed.
DRAM_VREF DRAM_VREF Not multiplexed.
DRAM_ZQPAD ZQPAD Not multiplexed.
DSI_REXT DSI_REXT Not multiplexed.
GND GND Not multiplexed.
HDMI_REF HDMI_REF Not multiplexed.
HDMI_VP HDMI_VP Not multiplexed.
HDMI_VPH HDMI_VPH Not multiplexed.
NC NC Not multiplexed.
NVCC_CSI NVCC_CSI Not multiplexed.
NVCC_DRAM NVCC_DRAM Not multiplexed.
NVCC_EIM0 NVCC_EIM0 Not multiplexed.
NVCC_ENET NVCC_ENET Not multiplexed.
NVCC_GPIO NVCC_GPIO Not multiplexed.
NVCC_JTAG NVCC_JTAG Not multiplexed.
NVCC_LCD NVCC_LCD Not multiplexed.
NVCC_LVDS_2P5 NVCC_LVDS2P5 Not multiplexed.
NVCC_MIPI NVCC_MIPI Not multiplexed.
NVCC_NAND NVCC_NANDF Not multiplexed.
NVCC_PLL NVCC_PLL_OUT Not multiplexed.
NVCC_RGMII NVCC_RGMII Not multiplexed.
NVCC_SD1 NVCC_SD1 Not multiplexed.
PCIE_REXT PCIE_REXT Not multiplexed.
PCIE_VP PCIE_VP Not multiplexed.


PCIE_VPH PCIE_VPH Not multiplexed.
PCIE_VPTX PCIE_VPTX Not multiplexed.
SATA_REXT SATA_REXT Not multiplexed.
SATA_VP SATA_VP Not multiplexed.
SATA_VPH SATA_VPH Not multiplexed.
USB_H1_VBUS USB_H1_VBUS Not multiplexed.
USB_OTG_VBUS USB_OTG_VBUS Not multiplexed.
VDD_ARM23_CAP VDDARM23_CAP Not multiplexed.
VDD_ARM23_IN VDDARM23_IN Not multiplexed.
VDD_ARM_CAP VDDARM_CAP Not multiplexed.
VDD_ARM_IN VDDARM_IN Not multiplexed.
VDD_CACHE_CAP VDD_CACHE_CAP Not multiplexed.
VDD_HIGH_CAP VDDHIGH_CAP Not multiplexed.
VDD_HIGH_IN VDDHIGH_IN Not multiplexed.
VDD_PU_CAP VDDPU_CAP Not multiplexed.
VDD_SNVS_CAP VDD_SNVS_CAP Not multiplexed.
VDD_SNVS_IN VDD_SNVS_IN Not multiplexed.
VDD_SOC_CAP VDDSOC_CAP Not multiplexed.
VDD_SOC_IN VDDSOC_IN Not multiplexed.
VDD_USB_CAP VDDUSB_CAP Not multiplexed.
PWM1 - Pulse Width Modulation
PWM1_OUT DISP0_DAT8 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08
PWM2_OUT DISP0_DAT9 (ALT2) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09
PWM3_OUT SD1_DAT1 (ALT2) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1
PWM4_OUT SD1_CMD (ALT2) IOMUXC_SW_MUX_CTL_PAD_SD1_CMD
SATA_PHY - Serial Advanced Technology Attachment PHY
SATA_PHY_RX_N SATA_RXM Not multiplexed.
SATA_PHY_RX_P SATA_RXP Not multiplexed.
SATA_PHY_TX_N SATA_TXM Not multiplexed.
SATA_PHY_TX_P SATA_TXP Not multiplexed.

Overview

SDMA - Smart Direct Memory Access Controller
SDMA_EXT_EVENT0 DISP0_DAT16 (ALT4) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16
IOMUXC_SDMA_EVENTS14_SELECT_INPUT
SDMA_EXT_EVENT1 DISP0_DAT17 (ALT4) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17
SJC - System JTAG Controller
JTAG_DE_B GPIO_16 (ALT7) IOMUXC_SW_MUX_CTL_PAD_GPIO16
JTAG_MOD JTAG_MOD Not multiplexed.
JTAG_TCK JTAG_TCK Not multiplexed.
JTAG_TDI JTAG_TDI Not multiplexed.
JTAG_TDO JTAG_TDO Not multiplexed.
JTAG_TMS JTAG_TMS Not multiplexed.
JTAG_TRSTB JTAG_TRSTB Not multiplexed.
SNVS - Secure Non-Volatile Storage
SNVS_PMIC_ON_REQ PMIC_ON_REQ Not multiplexed.
SNVS_TAMPER TAMPER Not multiplexed.
SNVS_VIO_5 GPIO_0 (ALT7) IOMUXC_SW_MUX_CTL_PAD_GPIO00
SNVS_VIO_5_CTL GPIO_18 (ALT6) IOMUXC_SW_MUX_CTL_PAD_GPIO18
SPDIF - Sony/Philips Digital Interface
SPDIF_EXT_CLK ENET_CRS_DV (ALT3) IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV
IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT
RGMII_TXC (ALT2) IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC
IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT
SPDIF_IN EIM_D21 (ALT7) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21
IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT
ENET_RX_ER (ALT3) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER
SPDIF_LOCK ENET_MDIO (ALT6) IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO
SPDIF_OUT EIM_D22 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22
ENET_RXD0 (ALT3) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0


SPDIF_SR_CLK ENET_REF_CLK (ALT6) IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK
SRC - System Reset Controller
SRC_BOOT_CFG00 EIM_DA0 (ALT7) IOMUXC_SW_MUX_CTL_PAD_EIM_AD00
SRC_BOOT_CFG16 EIM_A16 (ALT7) IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16
SRC_BOOT_CFG25 EIM_WAIT (ALT7) IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B
SRC_BOOT_CFG26 EIM_LBA (ALT7) IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B
SRC_BOOT_CFG27 EIM_EB0 (ALT7) IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B
SRC_BOOT_CFG29 EIM_RW (ALT7) IOMUXC_SW_MUX_CTL_PAD_EIM_RW
SRC_BOOT_MODE0 BOOT_MODE0 Not multiplexed.
SRC_BOOT_MODE1 BOOT_MODE1 Not multiplexed.

Overview

SRC_ONOFF ONOFF Not multiplexed.
SRC_POR_B POR_B Not multiplexed.
UART1 - Universal Asynchronous Receiver/Transmitter
UART1_CTS_B EIM_D19 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19
IOMUXC_UART1_UART_RTS_B_SELECT_INPUT
UART1_DCD_B EIM_D23 (ALT3) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23
UART1_DSR_B EIM_D25 (ALT7) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25
UART1_DTR_B EIM_D24 (ALT7) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24
UART1_RI_B EIM_EB3 (ALT3) IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B
UART1_RTS_B EIM_D20 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20
UART1_RX_DATA CSI0_DAT11 (ALT3) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11
IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT
UART1_TX_DATA CSI0_DAT10 (ALT3) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10
UART2_RX_DATA EIM_D27 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27


UART2_TX_DATA EIM_D26 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26
SD3_RST (ALT1) IOMUXC_SW_MUX_CTL_PAD_SD3_RESET
UART3_RX_DATA EIM_D25 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25
UART3_TX_DATA EIM_D24 (ALT2) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24
UART4_CTS_B CSI0_DAT17 (ALT3) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17

Overview

UART4_RTS_B CSI0_DAT16 (ALT3) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16
UART5_CTS_B CSI0_DAT19 (ALT3) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19
UART5_RTS_B CSI0_DAT18 (ALT3) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18
USB - Universal Serial Bus Controller
USB_H1_DN USB_H1_DN Not multiplexed.
USB_H1_DP USB_H1_DP Not multiplexed.
USB_H1_OC EIM_D30 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30
IOMUXC_USB_H1_OC_SELECT_INPUT
IOMUXC_USB_H1_OC_SELECT_INPUT
USB_H1_PWR EIM_D31 (ALT6) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31
USB_H1_PWR_CTL_WAKE KEY_COL2 (ALT6) IOMUXC_SW_MUX_CTL_PAD_KEY_COL2
USB_H2_DATA RGMII_TXC (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC


USB_H2_STROBE RGMII_TX_CTL (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL
USB_H3_DATA RGMII_RX_CTL (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL
USB_H3_STROBE RGMII_RXC (ALT0) IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC
USB_OTG_CHD_B USB_OTG_CHD_B Not multiplexed.
USB_OTG_DN USB_OTG_DN Not multiplexed.
USB_OTG_DP USB_OTG_DP Not multiplexed.
USB_OTG_HOST_MODE GPIO_7 (ALT7) IOMUXC_SW_MUX_CTL_PAD_GPIO07
USB_OTG_ID ENET_RX_ER (ALT0) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER
USB_OTG_OC EIM_D21 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21
IOMUXC_USB_OTG_OC_SELECT_INPUT
IOMUXC_USB_OTG_OC_SELECT_INPUT
USB_OTG_PWR EIM_D22 (ALT4) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22
USB_OTG_PWR_CTL_WAKE GPIO_8 (ALT7) IOMUXC_SW_MUX_CTL_PAD_GPIO08
USDHC1 - Ultra Secured Digital Host Controller
SD1_CD_B GPIO_1 (ALT6) IOMUXC_SW_MUX_CTL_PAD_GPIO01
SD1_CLK SD1_CLK (ALT0) IOMUXC_SW_MUX_CTL_PAD_SD1_CLK
SD1_CMD SD1_CMD (ALT0) IOMUXC_SW_MUX_CTL_PAD_SD1_CMD
SD1_DATA0 SD1_DAT0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0
SD1_DATA4 NANDF_D0 (ALT1) IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00
SD1_LCTL GPIO_16 (ALT3) IOMUXC_SW_MUX_CTL_PAD_GPIO16
SD1_VSELECT KEY_COL1 (ALT6) IOMUXC_SW_MUX_CTL_PAD_KEY_COL1
SD1_WP DI0_PIN4 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04
IOMUXC_USDHC1_WP_ON_SELECT_INPUT
IOMUXC_USDHC1_WP_ON_SELECT_INPUT
SD2_CD_B GPIO_4 (ALT6) IOMUXC_SW_MUX_CTL_PAD_GPIO04

Overview

SD2_LCTL GPIO_6 (ALT6) IOMUXC_SW_MUX_CTL_PAD_GPIO06
SD2_VSELECT KEY_ROW1 (ALT6) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1
SD2_WP GPIO_2 (ALT6) IOMUXC_SW_MUX_CTL_PAD_GPIO02
SD3_RESET SD3_RST (ALT0) IOMUXC_SW_MUX_CTL_PAD_SD3_RESET
SD3_VSELECT GPIO_18 (ALT2) IOMUXC_SW_MUX_CTL_PAD_GPIO18
SD4_RESET NANDF_ALE (ALT1) IOMUXC_SW_MUX_CTL_PAD_NAND_ALE
SD4_VSELECT NANDF_CS1 (ALT1) IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B


WDOG1 - Watchdog Timer
WDOG1_B DISP0_DAT8 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08
WDOG1_RESET_B_DEB SD1_DAT2 (ALT6) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2
WDOG2 - Watchdog Timer
WDOG2_B DISP0_DAT9 (ALT3) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09
WDOG2_RESET_B_DEB SD1_DAT3 (ALT6) IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3
XTALOSC - Crystal Oscillator
XTALOSC_CLK1_N CLK1_N Not multiplexed.
XTALOSC_CLK1_P CLK1_P Not multiplexed.
XTALOSC_CLK2_N CLK2_N Not multiplexed.
XTALOSC_CLK2_P CLK2_P Not multiplexed.
XTALOSC_OSC32K_32K_OU ENET_RXD0 (ALT0) IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0
T KEY_ROW3 (ALT0) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3
XTALOSC_REF_CLK_24M GPIO_3 (ALT3) IOMUXC_SW_MUX_CTL_PAD_GPIO03
RGMII_TXC (ALT7) IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC
XTALOSC_REF_CLK_32K GPIO_8 (ALT1) IOMUXC_SW_MUX_CTL_PAD_GPIO08
XTALOSC_RTC_XTALI RTC_XTALI Not multiplexed.
XTALOSC_RTC_XTALO RTC_XTALO Not multiplexed.
XTALOSC_XTALI XTALI Not multiplexed.
XTALOSC_XTALO XTALO Not multiplexed.

Overview

Chapter 5
Fusemap
5.1 Fusemap
This section details the various modes and selection of the required boot devices. A
separate map is given for each and every boot device.
The device select is specified by BOOT_CFG1[7:3] fuses listed in the following table.
Table 5-1. Boot Device Select
Boot Device BOOT _CFG1[7] BOOT_CFG1[6] BOOT_CFG1[5] BOOT_CFG1[4] BOOT_CFG1[3]
EIM - Table 5-3 0 0 0 0 Memory Type:
0 - NOR Flash
1 - OneNAND
SATA - Table 5-4 0 0 1 0 X
Serial ROM - Table 0 0 1 1 X
5-5
SD/eSD - Table 5-6 0 1 0 X X
MMC/eMMC - 0 1 1 X X
Table 5-7
NAND Flash - 1 X X X X
Table 5-8
NOTE
Fuses marked as “Reserved” are reserved for NXP internal (and
future) use only. Customers should not attempt to burn these, as
the IC behavior may be unpredictable. The reserved fuses can
be read as either ‘0’ or ‘1’.
Table 5-2. Lock Fuses
Addr 7 6 5 4 3 2 1 0
0x400[7:0] Reserved SJC_RESP MEM_TRIM_LOCK BOOT_CFG_LOCK TESTER_LOCK
_LOCK

Fusemap
Table 5-2. Lock Fuses (continued)

Addr 7 6 5 4 3 2 1 0
WRP,OP,R 1x - OP (Locking rows: 1x - OP
DP 0x450-0x470)
x1 - WP x1 - WP
1x - OP
x1 - WP
00x400[15:8] Reserved SRK_LOCK GP2_LOCK GP1_LOCK MAC_ADDR_LOCK
RD,WR,OP 1x - OP 1x - OP 1x - OP
x1 - WP x1 - WP x1 - WP
0x400[23:16] Reserved MISC_CON Reserved ANALOG_LOCK Reserved
F_LOCK
1x - OP
1 - WP +
x1 - WP
OP of
MISC_CON
F
0x400[31:24] Reserved
Table 5-3. EIM Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x450[7:0] 0 0 0 0 Memory Reserved Reserved Reserved
Type:
(BOOT_CFG1)
0 - NOR
Flash
1-
OneNAND
0x450[15:8] Muxing Scheme: OneNand Page Size: Reserved Reserved Reserved Reserved
(BOOT_CFG2) 00 - A/D16 (HW Default 00 - 1KB
in external boot)
01 - 2KB
01 - A+DH
10 - 4KB
10 - A+DL
11 - Reserved
11 - Reserved
0x450[23:16] L1 I-Cache BT_MMU_D DDR Memory Map Reserved Boot Reserved Reserved
ISABLE default config Frequencies
(BOOT_CFG3) DISABLE
(ARM/DDR)
00 - Single DDR channel
0 - 792 /
01 - Fixed 2x32 map
528 MHz
10 - 4KB Interleaving
1 - 396 /
Enabled
352MHz
11 - Illegal
0x450[31:24] Infinite Loop EEPROM eCSPI chip select: eCSPI Port Select:
(for debug) Recovery Addressing:
(BOOT_CFG4) 00 - ECSPIx_SS0 000 - eCSPI1
Enable
0 - Disabled (default) 0 - 2-bytes
001 - eCSPI2
0 - Disabled (16-bit)
1 - Enabled 01 - ECSPIx_SS1
010 - eCSPI3
1 - 3-bytes
10 - ECSPIx_SS2
(24-bit) 011 - eCSPI4

Chapter 5 Fusemap
Table 5-3. EIM Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
1 - Enabled 11 - ECSPIx_SS3 100 - eCSPI5
Fuse is
101 - I2C1
Reserved
for 'Serial- 110 - I2C2
ROM' Boot
111 - I2C3
mode
0x460[7:0] Reserved BT_FUSE_ DIR_BT_DI SDP_READ SEC_CONF SDP_DISA
SEL S _DISABLE IG[1] BLE (Silicon
(Silicon Revision 1.6
Revision 1.6 or later
or later only)
only)
0x460[23:16] JTAG_SMODE[1:0] WDOG_EN SJC_DISAB Reserved
ABLE LE
0 - Disabled
1 - Enabled
0x460[31:24] FORCE_IN eMMC_RE SDMMC_H TZASC_EN JTAG_HEO KTE Reserved
TERNAL_B SET_EN YS_EN ABLE
OOT
(Silicon
Revision 1.6
or later
only)
0x470[7:0] NAND_READ_CMD_CODE1[7:0]
0x470[23:16] Reserved LPB_BOOT (Core / DDR- BT_LPB_P Reserved
Bus) OLARITY
00 - LPB Disable (GPIO
polarity)
01 - 1 GPIO (def freq)
0 - Active
10 - Div by2
High
11 - Div by 4
1 -Active
Low
0x470[31:24] Reserved MMC_DLL_DLY[6:0]
0x6D0[7:0] Reserved (locked by PAD_SETTINGS[5:0]
MISC_CONF_LOCK)
Table 5-4. SATA Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x450[7:0] 0 0 1 0 Reserved Reserved Reserved Reserved
(BOOT_CFG1)
0x450[15:8] Reserved Reserved Reserved Tx Spread Rx Spread SATA_SPE SATA Type:
Spectrum Spectrum ED
(BOOT_CFG2) 00 - i
0 - Disabled 0 - Enabled

Fusemap
Table 5-4. SATA Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
1 - Enabled 1 - Disabled 0 - Gen2 01 - m
(3.0Gbps)
10 - x
1 - Gen1
11 - Reserved
(1.5Gbps)
(BOOT_CFG3) DISABLE
(ARM/DDR)
0 - 792 /
01 - Fixed 2x32 map
528 MHz
1 - 396 /
Enabled
352 MHz
11 - Illegal
Enable
001 - eCSPI2
010 - eCSPI3
1 - Enabled 1 - 3-bytes
10 - ECSPIx_SS2
Fuse is (24-bit) 011 - eCSPI4
Reserved 11 - ECSPIx_SS3
100 - eCSPI5
for 'Serial-
ROM' Boot 101 - I2C1
mode
110 - I2C2
111 - I2C3
or later only)
only)
ABLE LE
0 - Disabled
1 - Enabled
OOT
(Silicon
Revision 1.6
or later
only)
Bus) OLARITY
polarity)

Chapter 5 Fusemap
Table 5-4. SATA Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
01 - 1 GPIO (def freq) 0 - Active
High
10 - Div by2
1 -Active
11 - Div by 4
Low
MISC_CONF_LOCK)
Table 5-5. Serial-ROM Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x450[7:0] 0 0 1 1 Reserved Reserved Reserved Reserved
(BOOT_CFG1)
0x450[15:8] Reserved Reserved Reserved Reserved Reserved Reserved Reserved
(BOOT_CFG2)
(BOOT_CFG3) DISABLE
(ARM/DDR)
0 - 792 /
01 - Fixed 2x32 map
528 MHz
1 - 396 /
Enabled
352MHz
11 - Illegal
Enable
001 - eCSPI2
010 - eCSPI3
10 - ECSPIx_SS2
100 - eCSPI5
for 'Serial-
ROM' Boot 101 - I2C1
mode
110 - I2C2
111 - I2C3
0x460[7:0] Reserved eMMC_RE SDMMC_H BT_FUSE_ DIR_BT_DI SDP_READ SEC_CONF SDP_DISA
SET_EN YS_EN SEL S _DISABLE IG[1] BLE (Silicon
or later only)
only)
ABLE LE
0 - Disabled
1 - Enabled

Fusemap
Table 5-5. Serial-ROM Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
0x460[31:24] FORCE_IN Reserved TZASC_EN JTAG_HEO KTE Reserved
TERNAL_B ABLE
OOT
(Silicon
Revision 1.6
or later
only)
Bus) OLARITY
polarity)
0 - Active
10 - Div by2
High
11 - Div by 4
1 -Active
Low
MISC_CONF_LOCK)
Table 5-6. SD/eSD Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x450[7:0] 0 1 0 Fast Boot: SD/SDXC Speed SD Power SD
Cycle Loopback
(BOOT_CFG1) 0 - Regular 00 - Normal/SDR12
Enable Clock
1 - Fast 01 - High/SDR25 Source Sel
0 - No
Boot
10 - SDR50 power cycle (for SDR50
and
11 - SDR104 1 - Enabled
SDR104
via
only)
USDHC_RS
T pad 0 - through
(uSDHC3 & SD pad
4 only)
1 - direct
0x450[15:8] SD Calibration Step Bus Width: Port Select: DLL Boot Override
Override: Acknowledg Pad
(BOOT_CFG2) 00 - 1 delay cell 0 - 1-bit 00 - USDHC1
e Disable / Settings
0 - Boot
01 - 1 delay cell 1 - 4-bit 01 - USDHC2 Pull-Down (using
ROM
PAD_SETTI
10 - 2 delay cell 10 - USDHC3 default 0 - Use
NGS value)
default SD
11 - 3 delay cell 11 - USDHC4 1 - Apply
pad settings
value per
during
fuse field
power cycle
MMC_DLL_
DLY[3:0] 1 - Set pull-
down on SD
pads during

Chapter 5 Fusemap
Table 5-6. SD/eSD Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
power cycle
(used only
when "SD
Power
Cycle
Enable"
enabled)
(BOOT_CFG3) DISABLE
(ARM/DDR)
0 - 792 /
01 - Fixed 2x32 map
528 MHz
1 - 396 /
Enabled
352MHz
11 - Illegal
Enable
001 - eCSPI2
010 - eCSPI3
10 - ECSPIx_SS2
100 - eCSPI5
for 'Serial-
ROM' boot 101 - I2C1
mode
110 - I2C2
111 - I2C3
or later only)
only)
ABLE LE
0 - Disabled
1 - Enabled
OOT
(Silicon
Revision 1.6
or later
only)
Bus) OLARITY

Fusemap
Table 5-6. SD/eSD Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
polarity)
0 - Active
10 - Div by2
High
11 - Div by 4
1 -Active
Low
MISC_CONF_LOCK)
Table 5-7. MMC/eMMC Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x450[7:0] 0 1 1 Fast Boot: MMC Reserved eMMC reset Reserved
Speed pin enable
(BOOT_CFG1) 0 - Regular
0 - High 0 - eMMC
1 - Fast
reset pad
Boot 1- Normal
disabled
1- eMMC
reset
enabled via
SD_RST
pad
0x450[15:8] Bus Width: Port Select: DLL Fast Boot Override
Override: Acknowledg Pad
(BOOT_CFG2) 000 - 1-bit 00 - uSDHC1
e Disable: Settings
0 - Boot
001 - 4-bit 01 - uSDHC2 (using
ROM 0 - Boot Ack
PAD_SETTI
010 - 8-bit 10 - uSDHC3 default Enabled
NGS value)
101 - 4-bit 11 - uSDHC4 1 - Apply 1 - Boot Ack
value per Disabled
DDR (MMC 4.4)
fuse field
110 - 8-bit DDR (MMC 4.4) MMC_DLL_
DLY[3:0]
Else - Reserved
(BOOT_CFG3) DISABLE
(ARM/DDR)
0 - 792 /
01 - Fixed 2x32 map
528 MHz
1 - 396 /
Enabled
352MHz
11 - Illegal
Enable
001 - eCSPI2
010 - eCSPI3

Chapter 5 Fusemap
Table 5-7. MMC/eMMC Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
1 - Enabled 10 - ECSPIx_SS2 1 - 3-bytes 011 - eCSPI4
Fuse is (24-bit)
11 - ECSPIx_SS3 100 - eCSPI5
Reserved
for 'Serial- 101 - I2C1
ROM' boot
110 - I2C2
mode
111 - I2C3
or later only)
only)
ABLE LE
0 - Disabled
1 - Enabled
OOT
(Silicon
Revision 1.6
or later
only)
Bus) OLARITY
polarity)
0 - Active
10 - Div by2
High
11 - Div by 4
1 -Active
Low
MISC_CONF_LOCK)
Table 5-8. NAND Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x450[7:0] 1 Reserved BT_TOGGL Override Nand Number Of Nand_Row_address_byte
EMODE Pad Devices: s:
(BOOT_CFG1)
Settings
0 - Raw 00 - 1 00 - 3
Nand
01 - 2 01 - 2

Fusemap
Table 5-8. NAND Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
1 - Toggle- (using 10 - 4 10 - 4
Mode PAD_SETTI
11 - Reserved 11 - 5
NAND NGS value)
0x450[15:8] Toggle Mode 33MHz Preamble Delay, BOOT_SEARCH_COUN Pages In Block: Reset time
Read Latency: T:
(BOOT_CFG2) 00 - 128 0 - 12ms
000 - 16 GPMICLK cycles 00 - 2
01 - 64 1 - 22ms
001 - 1 GPMICLK cycles 01 - 2 (LBA Nand)
10 - 32
11 - 256
100 - 4 GPMICLK cycles
(BOOT_CFG3) DISABLE
(ARM/DDR)
0 - 792 /
01 - Fixed 2x32 map
528 MHz
1 - 396 /
Enabled
352MHz
11 - Illegal
Enable
001 - eCSPI2
010 - eCSPI3
10 - ECSPIx_SS2
100 - eCSPI5
for 'Serial-
ROM' boot 101 - I2C1
mode
110 - I2C2
111 - I2C3
0x460[7:0] Reserved eMMC_RE SDMMC_H BT_FUSE_ DIR_BT_DI SDP_READ SEC_CONF SDP_DISA
SET_EN YS_EN SEL S _DISABLE IG[1] BLE (Silicon
or later only)
only)
ABLE LE
0 - Disabled
1 - Enabled
0x460[31:24] FORCE_IN Reserved TZASC_EN JTAG_HEO KTE Reserved
TERNAL_B ABLE

Chapter 5 Fusemap
Table 5-8. NAND Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
OOT
(Silicon
Revision 1.6
or later
only)
Bus) OLARITY
polarity)
0 - Active
10 - Div by2
High
11 - Div by 4
1 -Active
Low
MISC_CONF_LOCK)
5.2 Fusemap Description Table

This section covers the fusemap descriptions of the chip.
Table 5-9. Fusemap Descriptions
Fuse Fuses Name Numbe Fuses Function Settings Locked by
Address r of
Fuses
0x400[1:0] TESTER_LOCK 2 Provides Locking of various 00 - Unlock (The controlled N/A
fuse bits. field can be read, sensed,
burned or overridden in the
corresponded
1x - Override Protect (OP)
x1 - Write Protect (WP)
11 - Both OP and WP
0x400[3:2] BOOT_CFG_LOCK 2 Perform lock on BOOT 00 - Unlock (The controlled N/A
related fuses. field can be read, sensed,
corresponded
11 - Both OP and WP

Fusemap Description Table
Table 5-9. Fusemap Descriptions (continued)

Address r of
Fuses
0x400[5:4] MEM_TRIM_LOCK 2 Trimming fuses. Burned on 00 - Unlock (The controlled N/A
the tester or by customer field can be read, sensed,
before the final product burned or overridden in the
shipment. corresponded.
11 - Both OP and WP
0x400[6] SJC_RESP_LOCK 1 Lock bit for JTAG response 00 - Unlock N/A
fuses. (SJC_RESP)
1 - Read Protect + Write
Protect + Override Protect
and Program protect lock
0x400[9:8] MAC_ADDR_LOCK 2 Lock MAC_ADDR fuses. 00 - Unlock (The controlled N/A
field can be read, sensed,
corresponded.
11 - Both OP and WP
0x400[11:10] GP1_LOCK 2 Lock for General Purpose 00 - Unlock (The controlled N/A
fuse register #1 (GP1) field can be read, sensed,
corresponded.
11 - Both OP and WP
0x400[13:12] GP2_LOCK 2 Lock for General Purpose 00 - Unlock (The controlled N/A
fuse register #2 (GP2) field can be read, sensed,
corresponded.
11 - Both OP and WP
0x400[14] SRK_LOCK 1 Locking SRK_HASH[255:0] 0 - Unlock N/A
1 - Write Protect + Override
Protect
0x400[19:18] ANALOG_LOCK 2 Lock bit for various fuses 00 - Unlock (The controlled N/A
(Addresses: 0x4D0-0x4F0) field can be read, sensed,
corresponded.
11 - Both OP and WP

Chapter 5 Fusemap

Address r of
Fuses
0x400[22] MISC_CONF_LOC 1 Locking of MISC_CONFIG 0 - Unlock
N/A
K fuses (address 0x6D0)
1 - WP + OP of MISC_CONF
0x410[31:0] SJC_CHALL[31:0] / 32 Device Unique ID, also be Random, by test program. TESTER_LOCK
UNIQUE_ID[31:0] used for SJC Challenge
phrase. (bits 31-0)
0x420[31:0] SJC_CHALL/ 32 Device Unique ID, also be Random, by test program. TESTER_LOCK
UNIQUE_ID[42:32] used for SJC Challenge
phrase. (bits 63-32)
0x430[21:20] NUM_CORES 2 Indicates the type of device : 00 - 4x Cores. TESTER_LOCK
2x cores or 4x cores.
01 - Reserved
10 - 2x Cores
11 - Reserved
0x430[24] SATA_RST_SRC 1 Controls mux to select SATA_RST_SRC TESTER_LOCK
'herset' to SATA, from either
0 - Origin SATA reset
SATA reset controller, or
controller
SRC module.
1 - SRC reset
0x430[26] MLB_DISABLE 1 MLB disable 0 - enabled TESTER_LOCK
1 - disabled
0x440[15] VPU_DISABLE 1 VPU disable 0 - enabled TESTER_LOCK
1 - disabled
0x440[17:16] SoC core speed 2 SPEED_GRADING[5:4] TESTER_LOCK
00 - 800MHz (Industrial
grade)
01 - 852MHz (Automotive
grade)
10 - 1000 MHz
11 - 1200 MHZ
0x450[7:0] BOOT_CFG1 8 BOOT configuration register See Table 5-1 for details. BOOT_CFG_LO
#1, Usage varies, depending CK
on selected boot device.
0x450[15:8] BOOT_CFG2 8 BOOT configuration register Refer to the respective boot BOOT_CFG_LO
#2, Usage varies, depending fusemap tables for details. CK
on selected boot device.
#3 fusemap tables for details. CK
#4 fusemap tables for details. CK
0x460[0] SDP_DISABLE 1 Enable/disable serial 0 – Serial download BOOT_CFG_LO
download support supported (default) CK
This fuse is available only on
silicon revision 1.6 or later


Address r of
Fuses
1 – No serial download
support. Recommended for
security-enabled
applications.
0x460[1] SEC_CONFIG[1] 1 Select polarity of GPIO pin Out of Factory state: BOOT_CFG_LO
used for LPB indication. CK
0 - Open - allows any code
to be flashed and executed,
even if it has no valid
signature.
1 - Closed (Security On)
0x460[2] SDP_READ_DISAB 1 Enable/disable reads using 0 – Reads and writes BOOT_CFG_LO
LE serial download support allowed using serial CK
download (default)
This fuse is available only on
silicon revision 1.6 or later 1 – Reads using SDR
READ_REGISTER are
disabled. Writes using SDP
are still possible.
0x460[3] DIR_BT_DIS 1 Disables the NXP reserved 0 - The reserved NXP BOOT_CFG_LO
modes. modes are enabled. CK
1 - The reserved NXP
modes are disabled.
This fuse must be blown to 1
for normal operation.
0x460[4] BT_FUSE_SEL 1 Determines, whether using If BOOT_MODE[1:0] = 0b10 BOOT_CFG_LO
fuses for boot configuration, CK
0 - Bits of SBMR are
or GPIO /Serial loader.
overridden by GPIO pins.
1 - Specific bits of SBMR are
controlled by eFUSE
settings.
If BOOT_MODE[1:0] = 0b00
0 - BOOT configuration
eFuses are not yet
programmed. Boot flow
jumps to serial downloader.
1 - BOOT configuration
eFuses have been
programmed. Regular boot
flow is performed.
0x460[15:8] DDR3_CONFIG[7:0 8 TBD (DDR3 config options) BOOT_CFG_LO
] CK
0x460[16] HDCP 1 HDCP encryption disable 0 - enabled BOOT_CFG_LO
CK
1 - disabled
0x460[20] SJC_DISABLE 1 Disable/Enable the Secure 0 - Secure JTAG Controller BOOT_CFG_LO
JTAG Controller module. is enabled CK
This fuse is used to create

Chapter 5 Fusemap

Address r of
Fuses
highest JTAG security level, 1 - Secure JTAG Controller
where JTAG is totally is disabled
blocked.
0x460[21] WDOG_ENABLE 1 Watchdog Enable Used to specify whether to BOOT_CFG_LO
enable / not watchdog at CK
boot.
0 - Watch-Dog is disabled
1 - Watch-Dog is enabled
0x460[23:22] JTAG_SMODE[1:0] 2 JTAG Security Mode. 00 - JTAG enable mode BOOT_CFG_LO
Controls the security mode CK
01 - Secure JTAG mode
of the JTAG debug interface
11 - No debug mode
0x460[26] KTE 1 Kill Trace Enable. Enables 0 - Bus tracing is allowed BOOT_CFG_LO
tracing capability on ETM, CK
1 - Bus tracing is allowed in
and other modules.
case security state as
defined by Secure JTAG
allows it (for example,
JTAG_ENABLE or
NO_DEBUG)
0x460[27] JTAG_HEO 1 JTAG HAB Enable Override. 0 - HAB may enable JTAG BOOT_CFG_LO
Disallows HAB JTAG debug access CK
enabling. The HAB may
1 - HAB JTAG enable is
normally enable JTAG
overridden (HAB may not
debugging by means of the
enable JTAG debug access)
HAB_JDE-bit in the OCOTP
SCS register. The
JTAG_HEO-bit can override
this behavior.
TZASC_ENABLE 1 TZASC1,2 enable fuse. 0 - TZASC1, 2 modules left BOOT_CFG_LO
0x460[28]
in disable and bypass state. CK
1 - TZASC1, 2 modules,
associated clocks and
muxing are enabled by Boot
ROM code.
0x460[29] SDMMC_HYS_EN 1 Override HYS bit for 0 - Override HYS bit for BOOT_CFG_LO
SD/MMC pads SD/MMC pads disabled. CK
1 - After the fuse is blown,
the [HYS] bit of
IOMUXC_SW_PAD_CTL_P
AD_SDx_CLK,
IOMUXC_SW_PAD_CTL_P
AD_SDx_CMD,
IOMUXC_SW_PAD_CTL_P
AD_SDx_DAT0-n will be set.
0x460[30] eMMC_RESET_EN 1 eMMC 4.4 - RESET TO 0 - The CMD0 with argument BOOT_CFG_LO
PRE-IDLE STATE 0xf0f0f0f0 will not be sent to CK
put the eMMC card into pre-
IDLE state.


Address r of
Fuses
1 - The CMD0 with argument
0xf0f0f0f0 will be sent to put
the eMMCcard into pre-IDLE
state so that eMMC card’s
fast boot can work properly.
0x460[31] FORCE_INTERNAL 1 Enable/disable selection of 0 – Boot mode selected from BOOT_CFG_LO
_BOOT boot mode from the the BOOT_MODE[1:0] pins CK
BOOT_MODE[1:0] pins. (default).
This fuse is available only on 1 – BOOT_MODE[1:0] pins
silicon revision 1.6 or later are ignored. The boot mode
is forced to “Internal Boot”.
This prevents impact from
physical tampering with the
BOOT_MODE pins.
Recommended for security-
enabled applications.
0x470[7:0] NAND_READ_CMD 8 NAND_READ_CMD_CODE First command word to be BOOT_CFG_LO
_CODE1[7:0] 1 used for Nand read. CK
0x470[15:8] NAND_READ_CMD 8 NAND_READ_CMD_CODE Second command word to BOOT_CFG_LO
_CODE2[7:0] 2 be used for Nand read. CK
0x470[20] BT_LPB_POLARIT 1 Define GPIO3 polarity, for 0 - Active High BOOT_CFG_LO
Y determining LPB boot mode. CK
1 -Active Low
0x470[22:21] LPB_BOOT 2 Defined the LowPower Boot (Core / DDR- Bus) BOOT_CFG_LO
options CK
00 - LPB Disable
01 - 1 GPIO (default freq)
01 - Div by2
11 - Div by 4
0x470[30:24] MMC_DLL_DLY[6:0 7 eMMC 4.4/4.41 delay line Delay value required by BOOT_CFG_LO
] default value (set by boot USDHC for eMMC 4.4/4.41 CK
rom), used in conjunction to work
with "DLL Override" = 1
(BOOT_CFG3[3])
0x480[7:6] Temperature Grade 2 Indicates the device 00 - Commercial (0 to 95C) MEM_TRIM_LO
temperature grade CK
01 – Extended Commercial
(-20 to 105C)
10 - Industrial (-40 to 105C)
11 - Automotive (-40 to
125C)
0x4D0[31] Power-Gate cores 1 0 - All quad-core devices: 4 ANALOG_LOCK
2,3 cores powered on.
1 - All dual-core devices:
cores 2 and 3 power-gated.
0x4F0[15:0] USB_VID[31:0] 16 USB VID value,( to be used ANALOG_LOCK
by USB software driver).

Chapter 5 Fusemap

Address r of
Fuses
0x4F0[31:16] USB_PID[31:0] 16 USB PID value ( to be used ANALOG_LOCK
by USB software driver).
0x580-0x5F0 SRK_HASH[255:0] 256 SRK key 0x580-SRK0 SRK_LOCK
0x590-SRK1
0x5A0-SRK2
0x5B0-SRK3
0x5C0-SRK4
0x5D0-SRK5
0x5E0-SRK6
0x5F0-SRK7
0x600[31:0] SJC_RESP[31:0] 32 Response reference value Customer / OEM use. SJC_RESP_LOC
for the secure JTAG K (locks also for
controller read and explicit
sense)
0x610[23:0] SJC_RESP[55:32] 24 Response reference value Customer / OEM use. SJC_RESP_LOC
for the secure JTAG K (locks also for
controller read and explicit
sense)
0x620[31:0] MAC_ADDR[31:0] 32 Reserved for customers/ Customer / OEM use. MAC_ADDR_LO
software CK
0x630[15:0] MAC_ADDR[47:32] 16 Reserved for customers/ Customer / OEM use. MAC_ADDR_LO
software CK
0x660[31:0] GP1[31:0] 32 General Purpose fuse GP1_LOCK
register #1
0x670[31:0] GP2[31:0] 32 General Purpose fuse GP2_LOCK
register #2
0x6D0[5:0] PAD_SETTINGS 6 Used with conjunction of IO pads settings of selected MISC_CONF_LO
MMC/SD/Nand "Override boot interface, are override CK
Pad Settings" fuse value, as with this fuses, as follow:
follows:
[0] - Slew Rate
0 - Use IO default settings
[3:1] Drive Strength
for boot device IO pads
[5:4] - Speed Settings.
1 - Use "Override" value, as
set by this register Refer to IO PAD chapter for
"Settings" fields value


Chapter 6
External Memory Controllers
6.1 Overview
This chip has these external memory interfaces and controllers:
• Multi-Mode DDR Controller (MMDC)
• Raw NAND flash controller, consisting of GPMI2, BCH40 and APBH_DMA
components including the Randomizer module.
• EIM-PSRAM/NOR flash controller
6.2 Multi-mode DDR controller (MMDC) overview and feature

summary
The MMDC module is a DDR controller that supports several types of DDR memories
and two channel memory widths (x32 and x64).

Multi-mode DDR controller (MMDC) overview and feature summary
MMDC
128@533MHz
32@1066
DDR
AXI MMDC0 DDRIF_0 PHY_0
DDR
ADOPT logic
clk_0
DDR DDR
MUX IO MUX
128@533MHz
AXI MMDC1
DDR
ADOPT logic DDR 32@1066
clk_1 DDRIF_1 PHY_1
Figure 6-1. MMDC block diagram
Table 6-1. MMDC feature summary

Feature Description
Supported standards • LV-DDR3, DDR3 x16, x32, x64 (includes SODIMM)
• LPDDR2 2ch x32, in either the split map or the interleaving mode
• LPDDR2 1ch x32
DDR interface • x16, x32, x64 data bus width
• Density of 256 MB-8 GB
• Column size of 8-12 bits
• Row size of 11-16 bits
• 2 CS per channel, with a separate CS allocation for the LPDDR2-DRAM)
• Up to 4 GB address space and configurable address space per CS. For
LPDDR2 2ch x32 up to 2 GB per channel
• Interleaved accesses of LPDDR2-DRAM towards the same DDR channel.
This is supported only when using the same clock frequency for LPDDR2-
DRAM
• Supports burst length of 8 (aligned) for DDR3 and burst lengths of 4 for
LPDDR2
DDR performance • DDR3 and LPDDR2 support up to 1066 MT/s transfer rate
• Supports Real-Time priority by means of QoS the sideband priority signals
from the chip to enable different priority levels in the re-ordering mechanism
• Page hit/page miss optimizations
• Consecutive read/write access optimizations
• Supports deep read and write requests queues to enable bank prediction
• Drives back the critical word in a read transaction as soon as it is received by
the DDR device (doesn't wait until the whole data phase has been
completed)

Chapter 6 External Memory Controllers
Table 6-1. MMDC feature summary (continued)

Feature Description
• Can track open memory pages
• Supports bank interleaving
• Special optimization for non-aligned wrap accesses in burst length 8
AXI interface • AXI bus compliant with glueless interface to PL301 AXI network interconnect
• Supports bus transfers of 8,16, 32, 64, and 128 bits (single accesses and
bursts)
DDR calibration and delay-lines • All calibrations can be done automatically by hardware or manually by
software.
• ZQ calibration for an external DDR device (in DDR3 through the ZQ
calibration command and in LPDDR2 through the MRW command).
• Can be handled automatically for ZQ Short (periodically) and ZQ Long
(at exit from self-refresh).
• Can be handled manually at ZQ INIT.
DDR general • Configurable timing parameters
• Configurable refresh scheme
• Supports dynamic voltage, frequency change, and low-power mode entry
through hardware negotiation with the system (req/ack handshake)
• Suppors automatic self-refresh and power down entry and exit
• Supports the fast and slow precharge power down in DDR3
• Supports various ODT control schemes.
• Assertion/Deassertion of ODT control per read or write accesses and
for active or passive CS
• Supports MRW and MRR commands for LPDDR2
• Software control for moving to derated timing parameters and derated
refresh rate according to the temperature variation.
• Supports various debug and profiling modes
6.3 Raw NAND flash controller overview

The Raw NAND flash controller consists of three components: BCH, GPMI, and
APBH_DMA.
• BCH is a 40-bit error correction hardware engine with an AXI bus master and a
private connection to the GPMI.
• GPMI is the NAND controller pin interface.
• APBH_DMA is the DMA engine that drives the GPMI module.
This figure shows the modules' connectivity:

Raw NAND flash controller overview
DMA DMA
Chan x4 FIFO M
Memory
Access
Bridge
4 x DMA
Control
M S
CPU
Access
APBH Bus
GPMI BCH AXI Bus
Data I/F
RAWNAND (4xCE)
(ML C, SL C)
(ONFI 2.2, Toggle)
Figure 6-2. Raw NAND flash controller sub-system
6.3.1 NAND interface features

• ONFI2.2-compliant
• Timing modes 0-5 for both the asynchronous and synchronous interfaces
• Synchronous clock rate of up to 100 MHz with data rate of up to 200 MB/s
• Support for ganged ready/busy inputs
• Support allows the use of a single package pin for all ready busy/busy input
signals
• In the ganged mode (selectable by the programmable mode bit), the GPMI
expects that all NAND r/b pins are hardwired to the GPMI RDY_BUSY0
• Up to four NAND devices, supported by four chip-selects and one ganged ready/
busy
• Legacy raw SLC, MLC type device
• BA-NAND (Micron)
• PBA-NAND and LBA-NAND (Toshiba)
• E2-NAND (Hynix)
• EF-NAND (Samsung)
• Samsung's "Toggle-mode" NAND (clock rate of up to 66 Mhz and 80 Mhz, with a
data rate of up to 133 MB/s and 160 MB/s respectively)
• Configurable page size of 2 KB, 4 KB, or 8 KB
• Configurable spare area per page of up to 512 B
• Support for non-identical NAND devices is not required
6.3.2 NAND control features

The NAND control supports interleaved accesses to as many as four NAND devices
while hiding the busy period of each device. However, a fully-independent interleaving
can't be supported in the ganged ready/busy mode because that suggests a fully
independent DMA channel operation on multiple paralleled-accessed chip-enables.
It also features:
• Delay line for adjusting the latching edge in case the frequency is relatively high
while the delay is long
• Support for monitoring the external ready/busy signal and read status command
polling to compare the R/B bit.
6.3.3 Internal interface features

• The AXI Master interface can access the system memory space.
• The APBH slave port for register configuration through the APBH bridge DMA
6.3.4 APBH-DMA overview

APBH-DMA provides the APB peripheral bus system for GPMI and BCH. APBH-DMA
uses a single GPMI interface to support as many as four DMA channels for four NAND
devices (four chip-enables) in the interleaved mode.
6.3.5 ECC-BCH features

BCH supports:
• Data rate of up to 200 MB/s
• 2 KB codeword (1 KB of data + parity)

EIM-PSRAM/NOR flash controller overview
• Galois Field polynomial GF(2^14)

• Up to 40-bit ECC for 1 KB of data (2,4,6,8,10,12,14,16,
18,20,22,24,26,28,30,32,34,36,38,40 configurable)
• 1 KB codeword (1/2 KB of data + parity)
• Galois Field polynomial GF(2^13)
• Up to 40-bit ECC for 1/2 KB of data (2,4,6,8,10,12,14,16,
18,20,22,24,26,28,30,32,34,36,38,40 configurable)
6.4 EIM-PSRAM/NOR flash controller overview

EIM is an external interface module that manages the interface to external chip devices,
including the generation of chip selects, clocks, and control for external peripherals and
memory.
It provides asynchronous and synchronous access to devices with an SRAM-like
interface.
6.4.1 EIM features

• Up to four (software configurable) chip selects for external devices
• Flexible address decoding; each chip-select memory space is determined
separately according to the GPR bits in IOMUXC.
• Maximum supported density is 128 MB by default (AUS bit is cleared). When
the AUS bit is set, the maximum supported density is 32 MB.
• Selectable write protection for each chip select
• Support for multiplexed address/data bus operation (x16 and x32 port size)
• Programmable data port size for each chip select (x8, x16, and x32)
• Programmable wait-state generator for each chip select, for write and read accesses
separately
• Asynchronous accesses with programmable setup and hold times for control signals
• Supports asynchronous page mode accesses (x16 and x32 port size)
• Independent synchronous memory burst read mode support for NOR-flash and
PSRAM memories (x16 and x32 port size)
• Independent synchronous memory burst write mode support for PSRAM and NOR-
flash memories (CellularRAMTM from Micron, Infineon, and Cypress, OneNANDTM
and utRAMTM from Samsung, and COSMORAMTMfrom Toshiba)
• Supports NAND-flash devices with a NOR-flash interfaces - OneNANDTM
(Samsung)
• Independent programmable variable/fix latency support for read and write
synchronous (burst) mode
• Support for little-endian operation

• ARM AXI slave interface accesses are only handled in parallel for single AXI ID
transactions
• External interrupt support using the RDY_INT signal function as an external
interrupt pin
• Boot from external device support according to boot signals, using the RDY_INT
signal
• RDY signal support assertion after reset
• INT signal support assertion after reset for OneNANDTM (Samsung) device
• Supports little-endian mode only
6.4.2 EIM boot scenarios

EIM allows booting from NOR-flash devices. To select the NOR flash as the boot source,
use either the boot mode and configuration GPIO pins or the internal boot-related fuses.
The default setting of the EIM boot configuration is hardwired in the SoC design
(EIM_BOOT_CFG[12:0]=1001111100101b). The MUM and DSZ fields are modified by
the Boot ROM code based on the EIM Boot eFuse setting. EIM_BOOT_CFG[2] remains
logic 1b, which affects the OEA bit. See Sytem Boot for more information.
6.4.3 EIM boot configuration

This table shows the EIM boot configuration:
Table 6-2. EIM boot configuration
EIM_BOOT_CFG bus EIM affected bits EIM register
12 NUM16_BYP_GRANT CS0GCR2
11 DSZ[2] CS0GCR1
10 AUS CS0GCR1
[9:8] CSREC[2:1] CS0GCR1
[7:5] RWSC[4:2] CS0RCR1
WWSC[4:2] CS0WCR
4 ERRST WCR
3 RAL CS0RCR1
WAL CS0WCR
2 MUM CS0GCR1
OEA[1] CS0RCR1
[1:0] DSZ[1:0] CS0GCR1

EIM-PSRAM/NOR flash controller overview
6.4.4 OneNAND requirements

By default, the Ready/Busy pin is not in use, perform these steps to configure the
OneNAND:
• Poll the device to see whether it is ready; software performs a read from the device.
• Connect the Ready/Busy signal of the OneNAND device to any GPIO pin and use it
as an interrupt that indicates the OneNAND device ready state.

Chapter 7
System Debug
7.1 Overview
This section describes the hardware and software debug and application development
features and resources of the chip. It describes the following:
• Core/platform-specific resources
• Resources associated with complex IP blocks
• Chip-wide resources
• Interface to the external debug and development tools
The debug and trace architecture is designed around the following:
• Arm CoreSight architecture, adapted to i.MX 6Dual/6Quad SoC (for 2x and 4x core
debug), including a cross-trigger subsystem for cross-domain triggering of debug
resources
• JTAG port used to interact with cores under the debug by means of SJC, the system
JTAG controller port
• DAP, the debug access port that supports the interface to the Arm RealView
Debugging tools and other third-party tools
• TPIU, a trace port interface unit that efficiently accesses the program trace
information from the system
• Various chip-wide resources, such as debug features built into the IP blocks and
critical signal visibility available through alternate pin functions or observability
muxes
7.2 Chip and Arm Platform Debug Architecture

The Arm Debug architecture is based on the CoreSight architecture by Arm. The
CoreSight architecture provides a system-wide solution to real-time debug and trace.

Chip and Arm Platform Debug Architecture
The CoreSight architecture is embodied in a set of CoreSight components and compliant

processors that form the CoreSight systems. Its architecture maintains the traditional
requirements of debug and trace:
• To access the debug functionality without software interaction
• To connect to a running system without performing a reset
Full access to the processor debug capability is available by the Arm debug register map
through the Advanced Peripheral Bus (APB) slave port. The core includes a Processor
Debug Unit which stops program execution, examines and alters the processor and
coprocessor state, examines and alters the memory and input/output peripheral state, and
restarts the processor core.
7.2.1 Debug Features

• CoreSight Program Trace Macrocell (PTM): trace generator for the Arm Cortex-A9
core
• Support for a TrustZone-related 3-level debug scheme:
• Debug in Non-Secure privileged and user, and Secure user
• Debug in Non-Secure only
• EmbeddedICE-RT logic
• Support for both the monitor-mode and halt-mode debugging:
• Core run/halt control, debug status/control
• Breakpoint/watchpoint control
• Core-mapped and memory-mapped resource examination/modification
• Data communication channel between the Arm core and the host debugger via JTAG
and the Debug Access Port (DAP) module
• PMU (Performance Metrics Unit) used for system profiling and debug
• CP15 register for debugging the MMU, I and D L1 cache, and TLB
• PL310 L2 cache provides an event monitoring signal routed to pins for visibility to
help in system debug
The chip includes Arm CoreSight components for multicore debug and trace solutions.
See the following figure for the Arm debug architecture scheme.

Chapter 7 System Debug
i.MX 6Dual
JTAG DE_B
port pin
Cortex-A9 CTI0
MPCore dbg_req[3:0]
CPU0 SJC
PTM0
JTAG
Cortex-A9 CTI1 CTM0 CTM1 Bus

MPCore DAP System
CPU1 PTM1 AHB
Cortex-A9 CTI2 CTI4

MPCore
CPU2 PTM2
Cortex-A9 CTI3
MPCore ATB 16KB
CPU3 PTM3 ATB Trace Buffer
(ETB)
ATB
Replicator EVENTI
Funnel
ATB
ATB
i.MX 6Quad EVENTO
ATB
dbg_ack[3:0] ATB
IOMUX
FIFO TPIU
IOMUXC
GPR3[16:13] dbg_ack_out Routed to internal 16-bit
Mask logic and peripherals , TRACDATA
as debug indication
Figure 7-1. i.MX 6Dual/6Quad Cortex-A9 platform debug architecture
7.2.2 Debug system components

The CoreSight components include:
• Embedded Trace Buffer (ETB):16 KB RAM array to be used for on-chip capture of
trace data output from the PTM
• ATB Replicator to connect the trace data to TPIU (Trace Port Interface) and ETB
(Embedded Trace Buffer)
• ATB Funnel for capturing of trace data from either two or four cores
• Cross Triggering logic for event routing, including CTIs and CTMs
Other related IPs and functionality:

• ROMPATCH module to support modification of program/data information in the

MCU ROM
• Debug Visibility which selects critical signals routed to the I/O pads as alternate
outputs for external visibility
7.2.2.1 AMBA Trace Bus (ATB)

ATB transfers trace data though the chip CoreSight infrastructure. The trace sources are
ATB masters and the sinks are ATB slaves. The Arm (via PTM) cores are the data
generators. Link components such as the Trace Funnel and Replicator provide both the
master and slave interfaces.
The ATB protocol supports:
• Stalling of trace sources to enable the CoreSight components to funnel and combine
the sources into a single trace stream
• Association of the trace data with the generating source using trace source IDs. The
CoreSight system can trace up to 111 different items at any time
• Capture and transfer of multiple byte bus widths, currently to 32 bits
• A flushing mechanism to force the historic trace to drain from any sources, links, or
sinks up to the point that the request is initiated
7.2.2.2 ATB replicator

The ATB replicator enables two trace sinks to be wired together and to operate from the
same incoming trace stream.
There are no programmable registers. This component is invisible to the user on a
particular trace path, from source to sink.
• Incoming ATB Interface—the ATB replicator accepts the trace data from the trace
source, either directly or through a trace funnel.
• Outgoing ATB Interfaces—the ATB replicator sends identical trace data on the
outgoing master port interfaces.

7.2.2.3 Embedded Cross Triggering

The ECT is a modular component from Arm Limited that supports the interaction and
synchronization of multiple triggering events within a chip. The main function of the
ECT (CTI and CTM) is to pass debug events from one core to another. For example, the
ECT can communicate the debug state information from one core to another, so that the
program execution can be stopped on both processors at the same time (if required).
The ECT consists of these types of modules:
• Cross Trigger Interfaces (CTI)
• Cross Trigger Matrix (CTM)
The cross trigger interfaces provide the interface between the component or subsystem
and the cross trigger matrix. The system requires a CTI for each subsystem that supports
cross triggering. The CTI combines and maps the trigger requests, and broadcasts them to
all other interfaces on the ECT as channel events. When the CTI receives a channel
event, it maps it onto a trigger output. This enables the subsystems to cross trigger with
each other. The reception and transmission of triggers is performed through the trigger
interface.
The Cross Trigger Matrix (CTM) combines the trigger requests generated from the CTIs
and broadcasts them to all CTIs as channel triggers. The CTM controls the distribution of
channel events. It provides the Channel Interfaces (CIs) to connect to either the CTIs or
CTMs. This enables multiple CTIs to be linked together. The ECT is composed of three/
five CTIs (Cross Trigger Interface) and two CTMs (Cross Trigger Matrix). The ECT is
key in the multi-core and multi-IP debug strategy. The outcome is a software-controlled
debug signal matrix that receives signals from various sources (cores and peripherals) and
propagates/ routes them to the different debug resources of the SoC. These debug
resources include the time-stamping capability, profiling capabilities, real-time trace
(trace enabled or disabled), triggers, SOC level multiplexing, and debug interrupts.
NOTE
Because the ECT should only be used during the debug
sessions, it is disabled by default.
The ECT features are enabled by enabling of individual CTIs. It is only allowed in the
supervisor mode, after having presented a suitable key to the CTI CTILOCK register.
The CTI has eight inputs (trigger inputs) and eight outputs (trigger outputs) to the core/
chip and four inputs and outputs to the CTM (channel triggers).
7.2.2.3.1 Cross-Trigger Matrix (CTM)

The CTM (Cross-Trigger Matrix) is provided by Arm. A brief description is provided
below. See the Arm documentation for more details.
The CTM is a relatively simple block with no configuration options. There are two CTM
instances in i.MX6Dual/6Quad in the Arm platform.
One of them is used to route 4x Core's CTI's, while the second one is used for the
additional CoreSight CTIs. Each CTI has four channel lines, to which the CTI events are
mapped. The exact mapping is configured in the CTI logic.
7.2.2.3.2 Cross-Trigger Interface (CTI)

The Cross-Trigger Interface (CTI) component is provided by Arm. A brief description of
the CTI is provided below.
There are 5 CTIs in the chip's Arm platform. Four are of which, dedicated to each Core,
while the 5th is used for various other signals routing.
Each of these CTIs has 8 trigger inputs and 8 trigger outputs that connect to logic in the
domain to be debugged or profiled. Each CTI also includes a 4 channel interface to the
CTM (4 inputs and 4 outputs).
For more information, see Arm platform chapter.
7.2.2.4 Debug Access Port (DAP)

The DAP enables debug access to the chip modules through APB-AP (the APB access
port) and APB-Mux (the APB multiplexer).
AHB-AP provides system access. Debug tools can use JTAG to connect to the chip.
DAP has the following features:
• AMBA 3 Peripheral Bus Multiplexor access though AMBA 3 APB Access Port,
providing debug peripheral access through the APB interface.
• External JTAG access using the JTAG Debug Port (JTAG-DP).
• Internal chip module access using:
• AHB Access Port (AHB-AP)
• APB Access Port (APB-AP)
• JTAG Access Port (JTAG-AP)
APB-Mux enables system access to CoreSight components connected to the Debug APB.
The ROM table provides a list of memory locations of CoreSight components connected
to the Debug APB. This is visible from both tools and system access and one configures
it during system implementation.

External read/write access to the internal interface is provided by JTAG-DP. JTAG-DP

provides a standard interface for debug access to the chip through DAP. It interfaces to
the DAP internal bus.
Internal access to on-chip buses and other interfaces are provided by the access ports
(APs). The available APs are:
• AHB-AP which provides an AHB-Lite master for access to a system AHB bus.
• APB-AP which provides an AMBA 3 APB master for access to the Debug APB that
configures all CoreSight components.
• JTAG-AP which provides JTAG access to on-chip components and operates as a
JTAG master port to drive JTAG chains throughout the chip.
7.2.2.5 Coresight Embedded Trace Buffer (ETB)

The ETB provides on-chip storage of trace data using 32-bit RAM. The ETB accepts
trace data from any CoreSight-compliant component trace source with an ATB master
port, such as a trace source or a trace funnel. It is included in this device to remove
dependencies from the trace pin pad speed, and enable low cost trace solutions. The
TraceRAM size is 2 KB.
ATB
ATB slave port i/f Formatter
Trace RAM
interface
TraceRAM
TRIGIN Control
(from ETM Trigger out)
APB
APB Register Bank
i/f
Figure 7-2. ETB Block Diagram
The ETB contains the following blocks:

• Formatter—Inserts source ID signals into the data packet stream so that trace data
can be re-associated with its trace source after the data is read back out of the ETB.
• Control—Control registers for trace capture and flushing.
• APB interface—Read, write, and data pointers provide access to ETB registers. In
addition, the APB interface supports wait states through the use of a PREADYDBG
signal output by the ETB. The APB interface is synchronous to the ATB domain.

• Register bank—Contains the management, control, and status registers for triggers,
flushing behavior, and external control.
• Trace RAM interface—Controls reads and writes to the Trace RAM.
7.2.2.5.1 Performance Profiling with the ETB

To create a performance profile (for example, gprof) for the target application, a means to
collect trace over a long period of time is needed. The ETB buffer is too small to capture
a meaningful profile in just one take. What is needed is to collect and concatenate data
from the ETB buffer for multiple sequential runs. Using the ETB packet counter, the
trace analysis tool can capture multiple sequential runs by executing code until the ETB
is almost full, and halting or executing an interrupt handler to allow the buffer to be
emptied, and then continuing executing code. The target halts or executes an interrupt
handler when the buffer is almost full to empty the data and then the debugger runs the
target again.
7.2.2.5.2 ETB Counter Control

The ETB packet counter is controlled by the ETB counter control register, ETB reload
register, and ETB counter value register implemented in the Miscellaneous Control
Module (MCM) accessible via the Private Peripheral Bus. Via the ETB counter control
register the ETB control logic can be configured to cause an MCM Alert Interrupt, an
NMI Interrupt, or cause a Debug halt when the down counter reaches 0. Other features of
the ETB control logic include:
• Down counter to count as many as 512 x 32-bit packets.
• Reload request transfers reload value to counter.
• ATB valid and ready signals used to form counter decrement.
• The counter disarms itself when the count reaches 0.
The counter decrement enable will allow the counter to decrement at the rising edge of
ATCLK when,
• The counter enable bit is set.
• The counter is armed.
• ATVALID and ATREADY are asserted.

ATCLK
ATDATA A A B
ATSIZE
ATVALID
ATREADY
No count Enable Enable No count No count

since count count since since
ATB Stalled decrement decrement ATB Idle ATB Idle
Figure 7-3. Count Decrement Enable
7.2.3 Chip-Specific SJC Features
7.2.3.1 JTAG Disable Mode

In addition to four different JTAG security modes that are implemented internally in the
JTAG Controller, there is an option to disable the SJC functionality by e-fuse
configuration.
This creates additional JTAG mode "JTAG Disabled" with highest level of JTAG
protection. In this mode all JTAG features are disabled. Specifically, the following debug
features are disabled in addition to the features that were already disabled in "No Debug"
JTAG mode:
• Non-Secure JTAG control registers (PLL configuration, Deterministic Reset, PLL
bypass)
• Non-Secure JTAG status registers (Core status)
• Chip Identification Code (IDCODE)

7.2.3.2 JTAG ID
Table 7-1. i.MX JTAG ID
Device Silicon revision JTAG ID
i.MX 6Dual Rev 1.0 0191_E01Dh1
i.MX 6Quad Rev 1.0 0191_C01Dh2
1. In follow-on silicon revisions, the ID value is subject to change by incrementing the first nibble as follows: 1191_E01Dh for
Rev 1.1, 2191_E01Dh for Rev 1.2 , etc.
2. In follow-on silicon revisions, the ID value is subject to change by incrementing the first nibble as follows: 1191_C01Dh for
Rev 1.1, 2191_C01Dh for Rev 1.2 , etc.
7.2.4 System JTAG Controller - SJC

The SJC module is the bridge between external development and test instrumentation and
the internal JTAG-accessible debug and test resources.
It implements and manages the daisy-chained topology consisting of its own TAP and
those of the SDMA, and the Arm Debug Access Port (DAP).
The DAP itself has a JTAG serial links, which can drive the PCIe PHY and SATA PHY's
JTAG logic, used for testing of the PHYs.
NOTE
Single Wire Debug (SWD) protocol is not supported.
7.2.5 System JTAG controller main features

• IEEE P1149.1, 1149.6 (standard JTAG) interface to off-chip test and development
equipment
• Includes an SJC-only mode for true IEEE P1149.1 compliance, used primarily
for board-level implementation of boundary scan.
• Supports IEEE P1149.6 extensions to the JTAG standard for AC testing of
selected I/O signals.
• Debug-related control and status; puting selected cores into reset and/or debug mode
and monitoring individual core status signals by means of JTAG
• System status, such as the state of the PLLs (locked or not locked)
• Four levels of security, ranging from no security to no JTAG accessibility to the chip
7.2.6 TAP Port

The SJC supports the following standard JTAG pins:

• TRSTB
• TDI
• TDO
• TCK
• TMS
7.2.7 SJC main blocks

• Interface to the outside world via the standard JTAG pins
• Interface to the external Debug_Event pin
• A master TAP controller which implements the standard JTAG state machine
• Implementation of the mandatory and optional IEEE P1149.1 (JTAG) instructions
• Mandatory: "EXTEST", "SAMPLE/PRELOAD", and "BYPASS"
• Optional: "ID_CODE" (SOC JTAG ID register), "HIGHZ"
• Implementation IEEE P1149.6 (JTAG) mandatory instructions:
• "EXTEST_PULSE" and "EXTEST_TRAIN". These two instructions enable
edge-detecting behavior on the signal path containing AC pins.
• Supports the SDMA's DR-path-only JTAG architecture by implementing the
controller portion of its TAP (including "BYPASS" as the default state) within the
SJC
• The ExtraDebug registers, which implement a variety of control and status features
• Three 32-bit insecure general purpose status registers
• Two 32-bit secure status registers - one predefined, one general purpose.
• Control and status registers for debug, core, charge pump, and PLL.
• Four levels of fuse-defined security, ranging from no security to no access.
Both predefined and user-defined control and status functions are supported by the SJC.
7.3 Smart DMA (SDMA) core

SDMA is a dedicated, programmable DMA engine. It is an integration of a 32-bit RISC
core and DMA-specific hardware. It includes ports for the AP domain and a peripheral
domain, along with a burst-capable port for direct external memory access.
NOTE
The SDMA and its integration in the chip is unchanged from
previous i.MX chips.
The main SDMA debug features are:
• OnCE - On Chip Emulator, provides the following capabilities:

Smart DMA (SDMA) core
• SDMA core control - run/halt/single-step

• SDMA core register/memory-map access
• Event detection, watchpoints, and hardware breakpoints
• Real time buffer and PC trace buffer capability
• Trace buffer
• Contains information to identify the 32 last changes of flow detected during a
program execution
• Context dump
• Includes information about all the channel dump activity
• Current contents of SDMA RAM
• ROMPATCH
7.3.1 SDMA On Chip Emulation Module (OnCE) Feature

Summary
The SDMA debug features are primarily defined by the OnCE portion of its design.
They are summarized as follows:
• Memory And Register Access - dedicated logic enables user-access to SDMA
memory and register locations. These accesses are supported only when the
processor is in debug mode.
• Event Detection Unit - watches signals from the data memory bus (DMBus) which is
used by the RISC core to access its RAM, ROM, and memory-mapped registers
• Watchpoints - one output signal is available to watch event matching conditions at
the chip level. Match conditions are defined by programming memory-mapped
registers.
• Hardware Breakpoint - a counter is decremented after an event detection. A debug
request is sent to the SDMA core only when the counter reaches the value of zero. It
is possible to program the initial value of the counter or to disable the use of the
counter if a debug request must be generated after each event detection.
• Real Time Buffer - The Real Time Buffer Register (RTB) is a single 32-bit memory-
mapped register which can be accessed as a regular memory location during program
execution. It is used to store and retrieve run time information without putting the
SDMA in debug mode. Each write to this register causes an event. This register is, in
fact, located in the OnCE. Executing through JTAG, a buffer command exports the
content of this register through the JTAG port.

• Core Control (Core Status / Single Stepping) - Commands are provided to monitor
and control processor activity. The commands can halt the core, rerun the core from
another address location, and get processor status.
• Trace Buffer - a 32x32 buffer which records the last 32 changes of flow during
program execution. The buffer stores data in a modulo fashion (i.e. the 33rd
instruction change replaces the 1st). Captured trace information is retrieved via reads
to the Trace Buffer Register.
7.3.1.1 Other SDMA Debug Functionality

• Core Trace - basic core trace capability is available through debug visibility
functionality only. PTM trace capability does not exist.
• ROM Patch - can be accomplished by manipulating the CHN0ADDR register
through JTAG or via the MCU's ability to write to SDMA OnCE registers. This must
be done right after reset and before the SDMA core is enabled to begin processing
events.
• Additional debug control/status interaction with the SJC module
• SJC-controlled Debug Request
• SJC-readable Debug Acknowledge (in debug mode)
• Debug clock control - allows SJC to force clocks on for debug purposes
• Debug core state (SDMA RISC Core State) - 4 bits accessible from the SJC via
JTAG
7.3.1.2 SDMA ROM Patching

After reset, the SDMA is in its IDLE_AFTER_RESET mode. A debug request also puts
the SDMA in its DEBUG_IN_IDLE_AFTER_RESET mode. The new address boot must
be stored in CHN0ADDR register (e.g., through the SDMA OnCE via debugger).
The user must then issue the exec_core <instruction> SDMA OnCE instruction to return
to the IDLE_AFTER_RESET mode. The very first instructions of the boot code fetches
the contents of this register (which is also mapped in the SDMA memory space) and
jumps to the given address.
7.4 Miscellaneous
The Miscellaneous function described in this section provide useful general capabilities.

Supported tools
7.4.1 Clock/Reset/Power
CDBGPWRUPREQ and CDBGPWRUPACK are the handshake signals between the
DAP and the clock control module to ensure debug power and clocks are turned on. If the
debug components are always powered on, the handshake becomes a mechanism to turn
debug clocks on. Similarly, there is a register bit in the CCM which allows internal
software to turn debug clocks on as well because the CDBGPWRUPREQ is in the TCLK
domain and is inaccessible to software.
The Cortex-A9 and VSP cores can receive resets from the following sources:
• Debug Reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register of the
DAP) in the TCLK domain. This allows the debug tools to reset the debug logic.
• System POR reset
7.5 Supported tools

DS-5 Arm Debugger is supported.
The debugger is connected to the chip from the host by the DS-5 ICE protocol converter.
Other third party tools can be used via the standard JTAG interface, but may need to be
adapted for individual IC. It is important to check with tool vendors for specific tool
requirements, especially for on-chip IC.

Chapter 8
System Boot
8.1 Overview
The boot process begins at the Power-On Reset (POR) where the hardware reset logic
forces the Arm core to begin the execution starting from the on-chip boot ROM.
The boot ROM code uses the state of the internal register BOOT_MODE[1:0] as well as
the state of various eFUSEs and/or GPIO settings to determine the boot flow behavior of
the device.
The main features of the ROM include:
• Support for booting from various boot devices
• Serial downloader support (USB OTG)
• Device Configuration Data (DCD) and plugin
• Digital signature and encryption based High-Assurance Boot (HAB)
• Wake-up from the low-power modes
• Wake-up secondary core
The boot ROM supports these boot devices:
• NOR flash
• NAND flash
• OneNAND flash
• SD/MMC
• Serial ATA (SATA) HDD (only i.MX 6Dual/6Quad)
• Serial (I2C/SPI) NOR flash and EEPROM
The boot ROM uses the state of the BOOT_MODE and eFUSEs to determine the boot
device. For development purposes, the eFUSEs used to determine the boot device may be
overridden using the GPIO pin inputs.

Overview
The boot ROM code also allows to download the programs to be run on the device. The
example is a provisioning program that can make further use of the serial connection to
provide a boot device with a new image. Typically, the provisioning program is
downloaded to the internal RAM and allows to program the boot devices, such as the
SD/MMC flash. The ROM serial downloader uses a high-speed USB in a non-stream
mode connection.
The boot ROM allows waking up from the low-power modes and waking up the
secondary core of Cortex-A9. On reset, the ROM checks the Arm core ID and the power
gating status register. When waking from the low-power mode, the primary core (ID=0)
skips loading an image from the boot device and jumps to the address saved in
PERSISTENT_ENTRY0. The secondary cores (ID!=0) jump to the address in
PERSISTENT_ENTRY<X> where 0<X<4 in all power modes.
The Device Configuration Data (DCD) feature allows the boot ROM code to obtain the
SOC configuration data from an external program image residing on the boot device. As
an example, the DCD can be used to program the DDR controller for optimal settings,
improving the boot performance. The DCD is restricted to the memory areas and
peripheral addresses that are considered essential for the boot purposes (see Write data
command).
A key feature of the boot ROM is the ability to perform a secure boot, also known as a
High-Assurance Boot (HAB). This is supported by the HAB security library which is a
subcomponent of the ROM code. The HAB uses a combination of hardware and software
together with the Public Key Infrastructure (PKI) protocol to protect the system from
executing unauthorized programs. Before the HAB allows the user image to execute, the
image must be signed. The signing process is done during the image build process by the
private key holder and the signatures are then included as a part of the final program
image. If configured to do so, the ROM verifies the signatures using the public keys
included in the program image. In addition to supporting the digital signature verification
to authenticate the program images, the encrypted boot is also supported. The encrypted
boot can be used to prevent the cloning of the program image directly off the boot device.
A secure boot with HAB can be performed on all boot devices supported on the chip in
addition to the serial downloader. The HAB library in the boot ROM also provides the
API functions, allowing the additional boot chain components (bootloaders) to extend the
secure boot chain. The out-of-fab setting for the SEC_CONFIG is the open configuration,
in which the ROM/HAB performs the image authentication, but all authentication errors
are ignored and the image is still allowed to execute.
NOTE
Silicon Revision 1.6 and later supports additional fuses related
to Serial Download mode. Fuse SDP_DISABLE enables/
disables Serial Download mode support. Fuse

Chapter 8 System Boot
SDP_READ_ENABLE enables/disables reads using Serial

Download mode. For detailed information on these fuses, see
Fusemap.
8.2 Boot modes

During reset, the chip checks the ARM core ID and power gating controller status
register.
During boot, the core's behavior is defined by the boot mode pin settings, as described in
Boot mode pin settings. When waking up from the low-power boot mode, the core skips
the clock settings. The boot ROM checks that the PERSISTENT_ENTRY0 (see
Persistent bits) is a pointer to a valid address space (OCRAM, DDR, or EIM). If the
PERSISTENT_ENTRY0 is a pointer to a valid range, it starts the execution using the
entry point from the PERSISTENT_ENTRY0 register. If the PERSISTENT_ENTRY0 is
a pointer to an invalid range, the core performs the system reset.
For the secondary cores (with ID!=0), the boot ROM checks that the
PERSISTENT_ENTRY is a pointer to a valid address space (OCRAM, DDR, or EIM). If
the PERSISTENT_ENTRY is a pointer to a valid range, it starts the execution using the
entry point from the PERSISTENT_ENTRY register. If the PERSISTENT_ENTRY is a
pointer to an invalid range, it sets the error status registers (see Persistent bits), sends the
wake-up error interrupt, and performs the Wait For Interrupt instruction. The interrupt
service routine of the other core must reconfigure the system and reset the secondary core
that failed to boot.
NOTE
The code that enables the secondary cores is not a part of the
ROM, but it must be a part of the upper-level software.
8.2.1 Boot mode pin settings

The device has four boot modes (one is reserved for NXP use). The boot mode is selected
based on the binary value stored in the internal BOOT_MODE register.
The BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1
inputs on the rising edge of the POR_B. After these inputs are sampled, their subsequent
state does not affect the contents of the BOOT_MODE internal register. The state of the

Boot modes
internal BOOT_MODE register may be read from the BMOD[1:0] field of the SRC Boot
Mode Register (SRC_SBMR2). The available boot modes are: Boot From Fuses, serial
boot via USB, and Internal Boot. See this table for settings:
Table 8-1. Boot MODE pin settings
BOOT_MODE[1:0] Boot Type
00 Boot From Fuses
01 Serial Downloader
10 Internal Boot
11 Reserved
NOTE
Silicon Revision 1.6 and later, the
FORCE_INTERNAL_BOOT has been implemented. This fuse
causes the BOOT_MODE inputs to be ignored and the boot
ROM will force the boot mode to “Internal Boot”. This
prevents impact from physically tampering with the
BOOT_MODE pins and is recommended for security-enabled
application. For detailed information on this fuses, see
Fusemap.

8.2.2 High-level boot sequence

The figure found here show the high-level boot ROM code flow.
Reset
Check CPU ID 1,2,3

(using Cortex-A9 MPIDR)
Wakeup From Low

Check Reset Use wakeup handler and Check wakeup handler
Power No
Type argument From SRC registers In valid range
Mode
Normal
Check CPU ID
Check Boot Mode (using Cortex-A9
(using fuses and/or MPIDR)
GPIOs)
1,2,3
Internal
Serial
Download initial boot image
(primary or secondary Fail Update wakeup error
depending on persistent bit) status register
No
Pass Primary boot

device is I2C/
eCSPI?
Primary 0
Authenticate Image Fail
Image?
No
Yes
Yes Download And Authenticate
Image from Serial EEPROM Send Wakeup Error
Set secondary image Interrupt
Persistent bit and
perform SW reset Fail
Pass Fail
Download And Authenticate

Image via USB
End
Pass System
Wait For Reset
Execute Image Yes Reset
Figure 8-1. Boot flow
8.2.3 Boot From Fuses mode (BOOT_MODE[1:0] = 00b)

A value of 00b in the BOOT_MODE[1:0] register selects the Boot From Fuses mode.
This mode is similar to the Internal Boot mode described in Internal Boot mode
(BOOT_MODE[1:0] = 0b10) with one difference. In this mode, the GPIO boot override
pins are ignored. The boot ROM code uses the boot eFUSE settings only. This mode also
supports a secure boot using HAB.
If set to Boot From Fuses, the boot flow is controlled by the BT_FUSE_SEL eFUSE
value. If BT_FUSE_SEL = 0, indicating that the boot device (for example, flash, SD/
MMC) was not programmed yet, the boot flow jumps directly to the Serial Downloader.
If BT_FUSE_SEL = 1, the normal boot flow is followed, where the ROM attempts to
boot from the selected boot device.

Boot modes
The first time a board is used, the default eFUSEs may be configured incorrectly for the
hardware on the platform. In such case, the Boot ROM code may try to boot from a
device that does not exist. This may cause an electrical/logic violation on some pads.
Using the Boot From Fuses mode addresses this problem.
Setting the BT_FUSE_SEL=0 forces the ROM code to jump directly to the Serial
Downloader. This allows a bootloader to be downloaded which can then provision the
boot device with a program image and blow the BT_FUSE_SEL and the other boot
configuration eFUSEs. After the reset, the boot ROM code determines that the
BT_FUSE_SEL is blown (BT_FUSE_SEL = 1) and the ROM code performs an internal
boot according to the new eFUSE settings. This allows the user to set
BOOT_MODE[1:0]=00b on a production device and burn the fuses on the same device
(by forcing the entry to the Serial Downloader), without changing the value of the
BOOT_MODE[1:0] or the pullups/pulldowns on the BOOT_MODE pins.
8.2.4 Serial Downloader

The Serial Downloader provides a means to download a program image to the chip over
the USB serial connection.
In this mode, the ROM programs the WDOG1 for a 90-second time-out if the
WDOG_ENABLE eFuse is 1 and continuously polls for the USB connection. If no
activity is found on the USB OTG1 and the watchdog timer expires, the Arm core is
reset.
NOTE
After the downloaded image is loaded, it is responsible for
managing the watchdog resets properly.
This figure shows the USB boot flow:

START
Configure USBOTG1,
, program WDOG for 32 sec timer
Poll USBOTG1 No
WDOG_ENABLE
Activity
No == 1 &&
Detected
90 sec over
Yes
Yes
Complete USB HID enumeration
Ready for Serial

Reset
Download
Figure 8-2. Serial Downloader boot flow
8.2.5 Internal Boot mode (BOOT_MODE[1:0] = 0b10)

A value of 0b10 in the BOOT_MODE[1:0] register selects the Internal Boot mode. In
this mode, the processor continues to execute the boot code from the internal boot ROM.
The boot code performs the hardware initialization, loads the program image from the
chosen boot device, performs the image validation using the HAB library (see Boot
security settings), and then jumps to an address derived from the program image. If an
error occurs during the internal boot, the boot code jumps to the Serial Downloader (see
Serial Downloader). A secure boot using the HAB is possible in all the three boot modes.
When set to the Internal Boot, the boot flow may be controlled by a combination of
eFUSE settings with an option of overriding the fuse settings using the General Purpose
I/O (GPIO) pins. The GPIO Boot Select FUSE (BT_FUSE_SEL) determines whether the
ROM uses the GPIO pins for a selected number of configuration parameters or eFUSEs
in this mode.

Device configuration
• If BT_FUSE_SEL = 1, all boot options are controlled by the eFUSEs described in

Table 8-2.
• If BT_FUSE_SEL = 0, the specific boot configuration parameters may be set using
the GPIO pins rather than eFUSEs. The fuses that can be overridden when in this
mode are indicated in the GPIO column of Table 8-2. Table 8-3 provides the details
of the GPIO pins.
The use of the GPIO overrides is intended for development since these pads are used for
other purposes in the deployed products. NXP recommends controlling the boot
configuration by the eFUSEs in the deployed products and reserving the use of the GPIO
mode for the development and testing purposes only.
8.2.6 Boot security settings

The internal boot modes use one of three security configurations.
• Closed: This level is intended for use with shipping-secure products. All HAB
functions are executed and the security hardware is initialized (the Security
Controller or SNVS enters the Secure state), the DCD is processed if present, and the
program image is authenticated by the HAB before its execution. All detected errors
are logged, and the boot flow is aborted with the control being passed to the serial
downloader. At this level, the execution does not leave the internal ROM unless the
target executable image is authenticated.
• Open: This level is intended for use in non-secure products or during the
development phases of a secure product. All HAB functions are executed as for a
closed device. The security hardware is initialized (except for the SNVS which is left
in the Non-Secure state), the DCD is processed if present, and the program image is
authenticated by the HAB before its execution. All detected errors are logged, but
have no influence on the boot flow which continues as if the errors did not occur.
This configuration is useful for a secure product development because the program
image runs even if the authentication data is missing or incorrect, and the error log
can be examined to determine the cause of the authentication failure.
• Field Return: This level is intended for the parts returned from the shipped products.
8.3 Device configuration

This section describes the external inputs that control the behavior of the Boot ROM
code.

This includes the boot device selection (SPI, EIM, NOR, SD, MMC, and so on), boot
device configuration (SD bus width, speed, and so on), and other. In general, the source
for this configuration comes from the eFUSEs embedded inside the chip. However,
certain configuration parameters can be sourced from the GPIO pins, allowing further
flexibility during the development process.
8.3.1 Boot eFUSE descriptions

This table is a comprehensive list of the configuration parameters that the ROM uses.
Table 8-2. Boot eFUSE descriptions
Fuse Config Definition GPIO1 Shipped Settings2
uratio value
n
DIR_BT_DIS OEM Disables the NXP reserved NA 0 0—The reserved NXP modes are enabled.
modes.
1—The reserved NXP modes are disabled.
This fuse must be blown to 1 for normal
operation.
BT_FUSE_SEL OEM In the Internal Boot mode NA 0 If BOOT_MODE[1:0] = 0b10:
BOOT_MODE[1:0] = 10,
• 0—The bits of the SBMR are
the BT_FUSE_SEL fuse
overridden by the GPIO pins.
determines whether the
boot settings indicated by a • 1—The specific bits of the SBMR are
Yes in the GPIO column are controlled by the eFUSE settings.
controlled by the GPIO pins
or the eFUSE settings in If BOOT_MODE[1:0] = 0b00
the On-Chip OTP Controller • 0—The BOOT configuration eFuses
(OCOTP). are not programmed yet. The boot
In the Boot From Fuse flow jumps to the serial downloader.
mode BOOT_MODE[1:0] =
00, the BT_FUSE_SEL fuse • 1—The BOOT configuration eFuses
indicates whether the bit are programmed. The regular boot
configuration eFuses are flow is performed.
programmed.
SEC_CONFIG[1:0] SEC_C Security Configuration, as NA 01 00—Reserved
ONFIG[ defined in Boot security
01—Open (allows any program image,
0] - settings
even if the authentication fails)
NXP
1x—Closed (The program image executes
SEC_C
only if authenticated)
ONFIG[
1] -
OEM
FIELD_RETURN OEM Enables the NXP reserved 0—The NXP reserved modes are enabled/
modes. disabled based on the DIR_BT_DIS value.
1—The NXP reserved modes are enabled.
SRK_HASH[255:0] OEM 256-bit hash value of the NA 0 Settings vary—used by HAB
super root key
(SRK_HASH)

Device configuration

(continued)
uratio value
n
UNIQUE_ID[63:0] NXP Device Unique ID, 64-bit NA Unique Settings vary—used by HAB
UID ID
BT_MMU_DISABLE OEM The MMU/L1 D Cache/ Yes 0 0—MMU/L1 D Cache/PL310 is enabled by
(BOOT_CFG3[6]) PL310 disable bit used by the ROM during the boot.
the boot ROM for fast HAB
1—MMU/L1 D Cache/PL310 is disabled by
processing.
the ROM during the boot.
L1 I-Cache DISABLE OEM L1 I Cache disable bit used Yes 0 0—L1 I Cache is enabled by the ROM
(BOOT_CFG3[7]) by the boot during the entire during the boot.
execution.
1—L1 I Cache is disabled by the ROM
during the boot.
BT_FREQ OEM Boot frequency selection Yes 0 0—Arm—792 MHz, DDR—528 MHz, AXI—
(BOOT_CFG3[2]) 264 MHz
1—Arm—396 MHz, DDR—352 MHz, AXI—
176 MHz
BOOT_CFG1[7:0] OEM Boot configuration 1 Yes 0 Specific to the selected boot mode
BOOT_CFG2[7:0] OEM Boot configuration 2 Yes 0 Specific to the selected boot mode
BOOT_CFG4[6:0] OEM Boot configuration 4 0 Specific to the selected boot mode
BOOT_CFG4[7] OEM Infinite Loop Enable at the Yes 0 0—Disabled
start of the boot ROM. Used
1—Enabled
for debugging purposes.
Ignored if the DIR_BT_DIS
is 1 and FIELD_RETURN is
0.
LPB_BOOT OEM USB Low-Power Boot No 0 00—LPB Disable
01—1 GPIO (default frequencies)
10—Divide by 2
11—Divide by 4
BT_LPB_POLARITY OEM USB Low-Power Boot GPIO No 0 0—Low on the GPIO pad indicates the low-
polarity power condition.
1—High on the GPIO pad indicates the
low-power condition.
WDOG_ENABLE OEM Watchdog reset counter No 0 0—The watchdog reset counter is disabled
enable during the serial downloader.
1—The watchdog reset counter is enabled
during the serial downloader.
MMC_DLL_DLY[6:0] OEM uSDHC Delay Line settings No 0 uSDHC Delay Line settings
SRK_REVOKE[2:0] OEM SRK revocation mask No 0 SRK revocation mask
PAD_SETTINGS OEM Override values for the No 0 Override these IO PAD settings:
SD/MMC and NAND boot
• PAD_SETTINGS[0]—Slew Rate
modes


(continued)
uratio value
n
• PAD_SETTINGS[3:1]—Drive
Strength
• PAD_SETTINGS[5:4]—Speed
Settings
.
OVERRIDE_HYS_SD OEM Overrides the HYS bit for No 0 Override the IO PAD setting HYS to 1 for
MMC_PADS the SD pads the SD pads.
eMMC_4.4_RESET_T OEM ROM resets the boot device No 0 Applicable for booting from the eMMC 4.4
O_PRE-IDLE_STATE in the pre-idle state using spec or greater version devices. The fuse
the eMMC 4.4 feature, must not be blown for the eMMC 4.3 or
CMD0 with the argument lesser spec version devices.
value 0xf0f0f0f0.
1. This setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See GPIO Boot Overrides for
the corresponding GPIO pin.
2. 0 = intact fuse and 1= blown fuse
8.3.2 GPIO boot overrides

This table provides a list of the GPIO boot overrides:
Table 8-3. GPIO override contact assignments
Package pin Direction on reset eFuse
BOOT_MODE1 Input Boot mode selection
BOOT_MODE0 Input
EIM_DA0 Input BOOT_CFG1[0]

Device initialization
Table 8-3. GPIO override contact assignments (continued)

Package pin Direction on reset eFuse
EIM_A16 Input BOOT_CFG3[0]
EIM_WAIT Input BOOT_CFG4[1]
EIM_LBA Input BOOT_CFG4[2]
EIM_EB0 Input BOOT_CFG4[3]
EIM_RW Input BOOT_CFG4[5]
The input pins provided are sampled at boot, and can be used to override the
corresponding eFUSE values, depending on the setting of the BT_FUSE_SEL fuse.
8.3.3 Device Configuration Data (DCD)

The DCD is the configuration information contained in the program image (external to
the ROM) that the ROM interprets to configure various on-chip peripherals. See Device
Configuration Data (DCD) for more details on DCD.
8.4 Device initialization

This section describes the details of the ROM and provides the initialization details.
This includes details on:
• The ROM memory map
• The RAM memory map
• On-chip blocks that the ROM must use or change the POR register default values
• Clock initialization
• Enabling the MMU/L2 cache
• Exception handling and interrupt handling
8.4.1 Internal ROM/RAM memory map

These figures show the iROM memory map:
0x00017FFF 0x0093FFFF
RAM Exception Vector
0x0093FFB8
Stack
(8120 bytes)
0x0093E000
MMU Table
(24KB)
ROM Boot Strap 0x00938000
OCRAM Free Area

0x000000D4 (196KB)
Log Buffer Pointer
0x000000D0
ROM API Vector Table
0x000000C0
HAB API Vector Table
0x00000094
ROM Version and 0x00907000
Copyright Information
0x00000048 Reserved
(28KB)
Reset Exception Handler
0x00000000 0x00900000
ROM Memory Map RAM Memory Map
Figure 8-3. Internal ROM and RAM memory map for i.MX 6Dual/6Quad
NOTE
If no ROM/HAB APIs are being used, the entire OCRAM
region can be used freely after the boot.
8.4.2 Boot block activation

The boot ROM affects a number of different hardware blocks which are activated and
play a vital role in the boot flow.

The ROM configures and uses the following blocks (listed in an alphabetical order)
during the boot process. Note that the blocks actually used depend on the boot mode and
the boot device selection:
• APBH—the DMA engine to drive the GPMI module
• BCH—40-bit error correction hardware engine with the AXI bus master and a
private connection to the GPMI
• CCM—Clock Control Module
• ECSPI—Enhanced Configurable Serial Peripheral Interface
• EIM—External Interface Module used for the NOR and OneNAND devices
• I2C—I2C controller
• GPMI—NAND controller pin interface
• OCOTP_CTRL—On-Chip OTP Controller; the OCOTP contains the eFUSEs
• IOMUXC—I/O Multiplexer Control which allows the GPIO use to override the
eFUSE boot settings;
• IOMUXC GPR—I/O Multiplexer Control General-Purpose Registers
• CAAM—Cryptographic Acceleration and Assurance Module
• SNVS—Secure Non-Volatile Storage
• SRC—System Reset Controller
• USB—used for the serial download of a boot device provisioning program
• USDHC—Ultra-Secure Digital Host Controller
• WDOG-1—Watchdog timer
• DTCP—Digital Transmission Content Protection
• HDCP—High-bandwidth Digital Content Protection
8.4.3 Clocks at boot time

The table below show the various clocks and their sources used by the ROM.
Table 8-4. Normal frequency clocks configuration
Clock CCM signal Source Frequency (MHz) Frequency (MHz)
BT_FREQ=0 BT_FREQ=1
System PLL pll1_sw_clk 792 792
528 MHz PLL pll2_sw_clk 528 528
480 MHz PLL pll3_sw_clk 480 480
Arm core clock arm_clk_root System PLL 792 396
EIM aclk_eim_slow_cl AXI 132 132
k_root
AHB ahb_clk_root 528 MHz PLL/PFD352 132 88
IPG ipg_clk_root 528 MHz PLL/PFD352 66 44
AXI_A axi_a 528 MHz PLL/PFD352 528 352

Table 8-4. Normal frequency clocks configuration (continued)

Clock CCM signal Source Frequency (MHz) Frequency (MHz)
BT_FREQ=0 BT_FREQ=1
AXI_B axi_b 528 MHz PLL/PFD352 264 176
USB usboh3_clk_root 480 MHz PLL 60 60
USDHC usdhc1_clk_root PFD400 198 198
usdhc2_clk_root
usdhc3_clk_root
usdhc4_clk_root
ECSPI ecspi_clk_root 480 MHz PLL 60 60
I2C per_clk_root 528 MHz PLL 66 38.3
After the reset, each Arm core has access to all peripherals. The ROM code disables the
clocks listed in the following table, except for the boot devices listed in the second
column.
Table 8-5. List of disabled clocks
Clock name Enabled for boot device
CCGR0_APBHDMA
CCGR1_ECSPI1 ECSPI1
CCGR1_ECSPI2 ECSPI2
CCGR1_ECSPI3 ECSPI3
CCGR1_ECSPI4 ECSPI4
CCGR1_FEC
CCGR1_EPIT1
CCGR1_EPIT2
CCGR2_I2C1_SERIAL I2C1
CCGR3_OPENVGAXICLK
CCGR4_PWM1
CCGR4_PWM2
CCGR4_PWM3
CCGR4_PWM4
CCGR5_SDMA
CCGR5_SPDIF
CCGR5_SSI1
CCGR5_SSI2
CCGR5_SSI3
CCGR5_UART

Table 8-5. List of disabled clocks (continued)

Clock name Enabled for boot device
CCGR5_UART_SERIAL
CCGR6_USBOH3 USB
CCGR6_USDHC1 USDHC1
CCGR6_USDHC2 USDHC2
CCGR6_USDHC3 USDHC3
CCGR6_USDHC4 USDHC4
CCGR6_EIM_SLOW NOR, OneNAND
8.4.4 Enabling MMU and caches

The boot ROM includes a feature that enables the Memory Management Unit (MMU)
and the caches to improve the boot speed.
The L1 instruction cache is enabled at the start of the image download. The L1 data
cache, L2 cache, and MMU are enabled during the image authentication. When the HAB
authentication completes, the ROM disables the L1 data cache, L2 cache, and MMU.
The L1 Instruction cache, L1 data cache, L2 cache, and MMU is controlled by eFuse. By
default, these features are enabled.
Enabling the MMU when booting non-securely with SEC_CONFIG=Open and setting
the CSF pointer in the Image Vector Table to NULL has no impact on the boot
performance. With this configuration, it is recommended to blow the
BT_MMU_DISABLE fuse.
8.4.5 Exception handling

The exception vectors located at the start of the ROM are used to map all the Arm
exceptions (except the reset exception) to a duplicate exception vector table in the
internal RAM.
During the boot phase of CPU0, the RAM vectors point to the serial downloader in the
ROM.
During the boot phase of a secondary CPU, the internal RAM vectors point to a function
that sets the error status registers (see Persistent bits), sends a wakeup error interrupt, and
performs the Wait For Interrupt instruction. The interrupt service routine of the primary
CPU must reconfigure the system and reset the secondary CPU.

After the boot, the program image can overwrite the vectors as required. The code shown
below is used to map the ROM exception vector table to the duplicate exception vector
table in the RAM.
Mapping ROM Exception Vector Table
;; Define linker area for ROM exception vector table
AREA IROM_VECTORS, CODE, READONLY
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP ; Reserved vector
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
;; Define exception vector table

Reset_Addr DCD start_address
Undefined_Addr DCD iRAM_Undefined_Handler
SWI_Addr DCD iRAM_SWI_Handler
Prefetch_Addr DCD iRAM_Prefetch_Handler
Abort_Addr DCD iRAM_Abort_Handler
DCD 0 ; Reserved vector
IRQ_Addr DCD iRAM_IRQ_Handler
FIQ_Addr DCD iRAM_FIQ_Handler
start_address DCD start ;reset handler vector
8.4.6 Interrupt handling during boot

No special interrupt-handling routines are required during the boot process. The
interrupts are disabled during the boot ROM execution and may be enabled in a later boot
stage.
8.4.7 Persistent bits

Some modes of the boot ROM require the registers that keep their values after a warm
reset. The SRC General-Purpose registers are used for this purpose.
See this table for persistent bits list and description:
Table 8-6. Persistent bits
Bit name Bit location Description
PERSIST_SECONDARY_BOOT SRC_GPR10[30] This bit identifies which image must be used—
primary and secondary. Used only for the boot
modes that support redundant boot.
PERSIST_BLOCK_REWRITE SRC_GPR10[29] This bit is used as a warning. It identifies that there
are errors in the NAND blocks that hold the
application image.

Boot devices (internal boot)
Table 8-6. Persistent bits (continued)

Bit name Bit location Description
See NAND flash for more details.
PERSISTENT_ENTRY0[31:0] SRC_GPR1[31:0] Holds the entry function for the CPU0 to wake up
from the low-power mode.
PERSISTENT_ARG0[31:0] SRC_GPR2[31:0] Holds the argument of entry function for the CPU0
to wake up from the low-power mode.
PERSIST_OVERRIDE_SBMR1 SRC_GPR10[28] This bit instructs the ROM code to use the
SRC_GPR9 register as if it is the SBMR1. This
allows the software to override the fuse bits and
boot from an alternative boot source. This feature
is vaild for a WDOG time-out reset only, and can
be disabled if the DIR_BT_DIS fuse is blown.
PERSIST_SBMR1_VALUE SRC_GPR9 The value to override the SBMR1.
PERSISTENT_ENTRY1[31:0] SRC_GPR3[31:0] Holds the entry function for the CPU1 to wake up
from the low-power mode.
PERSISTENT_ARG1[31:0] SRC_GPR4[31:0] Holds the argument of the entry function for the
CPU1 to wake up from the low-power mode.
PERSISTENT_ENTRY2[31:0] SRC_GPR5[31:0] Holds the entry function for the CPU2 (i.MX 6Quad
only).
CPU2 (i.MX 6Quad only).
PERSISTENT_ENTRY3[31:0] SRC_GPR7[31:0] Holds the entry function for the CPU3 (i.MX 6Quad
only).
CPU3 (i.MX 6Quad only).
CPU3_ERROR_STATUS SRC_GPR10[27] CPU3 error status bit (i.MX 6Quad only)
CPU2_ERROR_STATUS SRC_GPR10[26] CPU2 error status bit (i.MX 6Quad only)
CPU1_ERROR_STATUS SRC_GPR10[25] CPU1 error status bit
8.5 Boot devices (internal boot)

The chip supports these boot flash devices:
• NOR flash with the External Interface Module (EIM), located on CS0, 16-bit bus
width.
• OneNAND flash with the EIM interface, located on CS0, 16-bits bus width.
• Raw NAND (MLC and SLC), and Toggle-mode NAND flash through GPMI-2
interface. Page sizes of 2 KB, 4 KB, and 8 KB. The bus widths of 8-bit with 2
through 40-bit BCH hardware ECC (Error Correction) are supported.
• SD/MMC/eSD/SDXC/eMMC4.4 via USDHC interface, supporting high capacity
cards.

• EEPROM boot via SPI (serial flash) and I2C (via ECSPI and I2C blocks
respectively).
• Serial ATA (SATA) boot via the SATA interface.
The selection of the external boot device type is controlled by the BOOT_CFG1[7:4]
eFUSEs. See this table for more details:
Table 8-7. Boot device selection
BOOT_CFG1[7:4] Boot device
0000 NOR/OneNAND (EIM)
0001 Reserved
0010 SSD/Hard Disk
(SATA)
0011 Serial ROM (I2C/SPI)
010x SD/eSD/SDXC
011x MMC/eMMC
1xxx Raw NAND
8.5.1 NOR flash/OneNAND using EIM interface

The External Interface Module (EIM) works in the asynchronous mode, and supports
either muxed, Address/Data, or non-muxed schemes, based on the fuse settings.
Table 8-8. EIM boot eFUSE descriptions
Fuse Config Definition GPIO1 Shipped Settings
value
BOOT_CFG1[7:4] OEM Boot device selection Yes 0000 0000—boot from the EIM interface
BOOT_CFG1[3] OEM NOR/OneNAND selection Yes 0 0—NOR
1—OneNAND
BOOT_CFG2[7:6] OEM Muxing scheme Yes 00 00—muxed, 16-bit data (low half)
interface
01—not muxed, 16-bit data (high half)
interface
10—not muxed, 16-bit data (low half)
interface
11—reserved
BOOT_CFG2[5:4] OEM OneNAND page size Yes 00 00—1 KB
01—2 KB
10—4 KB
11—reserved

1. This setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See GPIO Boot Overrides for
8.5.1.1 NOR flash boot operation

Booting from the NOR flash is supported via the EIM interface. The ROM reads the
Image Vector Table and Boot Data structures to determine if the image can be executed
directly from the EIM address space or copied to another memory.
The start field of the Boot Data Structure specifies the final location of the image (see
Image Vector Table and Boot Data).
8.5.1.2 OneNAND flash boot operation

At system power-up, the OneNAND device automatically copies the Initial Load Region
of 1 KB from the start of the flash array (sector 0 and sector 1, page 0, block 0) to its
Boot RAM (OneNAND's internal RAM).
NOTE
The OneNAND boot RAM memory containing the Initial 1-KB
Load Region must contain the IVT, DCD, and the Boot Data
structures.
Next, the ROM processes the DCD and then proceeds to copy the program image
contents to the application destination pointer (located in the start entry of the Boot Data
(see Image Vector Table and Boot Data). The ROM determines the size of the program
image by the length specified by the size entry in the Boot Data structure (see Image
Vector Table and Boot Data). A failure in loading data from the OneNAND device for
any reason forces the chip to enter the Serial Downloader. Otherwise, the booting from
the OneNAND device continues.
This figure illustrates the layout of the program image on the OneNAND boot device:
Initial Load Region 1 Kbyte

- Boot Data beginning at
Block-0
Remainder of Image
Figure 8-4. Program image layout on the OneNAND flash device

Before accessing the OneNAND device, the chip waits approximately 500 μs after the
Power-On Reset. This delay is required for the OneNAND device to become ready. After
this initial 500 μs delay, it can take additional 70 μs for the OneNAND device to load the
Initial Load Region of 1 KB into its boot RAM. The chip polls the OneNAND device
Interrupt Status Register to confirm that the first 1 KB was loaded to the OneNAND boot
RAM before continuing with the boot flow.
8.5.1.3 IOMUX configuration for EIM devices

The EIM interface uses the dedicated contacts on the IC.
The contacts assigned to the data signals used by the EIM are shown in this table:
Table 8-9. EIM IOMUX pin configuration
Signal A/D16 A+DH A+DL
(Muxed, 16-bit data low half (Not muxed, 16-bit data high (Not muxed, 16-bit data low
interface) half interface) half interface)
DATA0 EIM_DA0.alt0 EIM_D16.alt0 CSI0_DATA_EN.alt1
DATA1 EIM_DA1.alt0 EIM_D17.alt0 CSI0_VSYNC.alt1
DATA2 EIM_DA2.alt0 EIM_D18.alt0 CSI0_DAT4.alt1
ADDR0 EIM_DA0.alt0
ADDR1 EIM_DA1.alt0
ADDR2 EIM_DA2.alt0
ADDR3 EIM_DA3.alt0
ADDR4 EIM_DA4.alt0
ADDR5 EIM_DA5.alt0
ADDR6 EIM_DA6.alt0
ADDR7 EIM_DA7.alt0

Table 8-9. EIM IOMUX pin configuration (continued)

Signal A/D16 A+DH A+DL
(Muxed, 16-bit data low half (Not muxed, 16-bit data high (Not muxed, 16-bit data low
interface) half interface) half interface)
ADDR8 EIM_DA8.alt0
ADDR9 EIM_DA9.alt0
ADDR10 EIM_DA10.alt0
8.5.2 NAND flash

The boot ROM supports a number of MLC/SLC NAND flash devices from different
vendors and LBA NAND flash devices. The Error Correction and Control (ECC)
subblock (BCH) is used to detect the errors.
8.5.2.1 NAND eFUSE configuration

The boot ROM determines the configuration of the external NAND flash by parameters,
either provided by the eFUSE, or sampled on the GPIO pins during boot. See Table 8-10
for parameters details.
NOTE
BOOT_CFGx sampled on the GPIO pins depends on the
BT_FUSE_SEL setting. See Boot Fusemap for details.
NOTE
For BOOT_CFG[3:2], although ROM always boots from
CS0_B, for multiple chip selects, such as some NAND chips
which consist of multi CS. This fuse must be burned correctly.
The number of devices means the number of chip selects.
Table 8-10. NAND boot eFUSE descriptions
value
BOOT_CFG1[7] OEM Boot device selection Yes 0 1—boot from the NAND
Interface

Table 8-10. NAND boot eFUSE descriptions (continued)

value
BOOT_CFG1[5] OEM BT_TOGGLEMODE Yes 0 0—raw NAND
1—toggle mode NAND
BOOT_CFG1[4] OEM Override pad settings Yes 0 0—use the default values
1—use the PAD_SETTINGS
values
BOOT_CFG1[3:2] OEM Number of devices Yes 00 00—1 device
01—2 device
10—4 device
11—Reserved
BOOT_CFG1[1:0] OEM Row address cycles Yes 00 00—3
01—2
10—4
11—5
BOOT_CFG2[7:5] OEM Toggle mode 33 MHz Yes 000 000—16 GPMICLK cycles
preamble delay, read latency
001—1 GPMICLK cycles
BOOT_CFG2[4:3] OEM Boot search count Yes 00 00—2
01—2
10—4
11—8
BOOT_CFG2[2:1] OEM Pages in block Yes 00 00—128
01—64
10—32
11—256
BOOT_CFG2[0] OEM Reset time Yes 0 0—12 ms
1—22 ms (LBA NAND)
1. The setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See Table 3 for the
corresponding GPIO pin.
8.5.2.2 NAND flash boot flow and Boot Control Blocks (BCB)
There are two BCB data structures:

• FCB
• DBBT
As a part of the NAND media initialization, the ROM driver uses safe NAND timings to
search for the Firmware Configuration Block (FCB) that contains the optimum NAND
timings, the page address of the Discovered Bad Block Table (DBBT) Search Area, and
the start page address of the primary and secondary firmware.
The hardware ECC level to use is embedded inside the FCB block. The FCB data
structure is also protected using the ECC. The driver reads raw 2112 bytes of the first
sector and runs through the software ECC engine that determines whether the FCB data is
valid or not.
If the FCB is found, the optimum NAND timings are loaded for further reads. If the ECC
fails, or the fingerprints do not match, the Block Search state machine increments the
page number to the Search Stride number of pages to read for the next BCB until the
SearchCount pages have been read.
If the search fails to find a valid FCB, the NAND driver responds with an error and the
boot ROM enters the serial download mode.
The FCB contains the page address of the DBBT Search Area, and the page address for
primary and secondary boot images. The DBBT is searched in the DBBT Search Area,
just like the FCB is searched. After the FCB is read, the DBBT is loaded, and the primary
or secondary boot image is loaded using the starting page address from the FCB.
This figure shows the state diagram of the FCB search:

START
Current Page = 0,
Search Stride = Stride Size Fuse Value,
Search Count = Boot Search Count Fuse Value
Read 4K, ReadCount++
Current Page += Search

Stride
YES
Read Count <

Is Valid FCB? NO
Search Count
YES NO
Recovery Device/
NCB Found
Serial Loader
Figure 8-5. FCB search flow
When the FCB is found, the boot ROM searches for the Discovered Bad Blocks Table
(DBBT). If the DBBT Search Area is 0 in the FCB, the ROM assumes that there are no
bad blocks on the NAND device boot area. See this figure for the DBBT search flow:

START
Current Page = DBBT Start Page,

Search Stride = Stride Size Fuse Value,
Search Count = 4
Read 4K, ReadCount++
Current Page += Search

Stride
YES
Read Count <

Is Valid DBBT? NO
Search Count
YES
NO
DBBT Found, Copy to IRAM
DBBT Not Found

DBBT Found
Figure 8-6. DBBT search flow
The BCB search and load function also monitors the ECC correction threshold and sets
the PERSIST_BLOCK_REWRITE persistent bit if the threshold exceeds the maximum
ECC correction ability.
If there is a page with a number of errors higher than ECC can correct during the primary
image read, the boot ROM turns on the PERSIST_SECONDARY_BOOT bit and
performs the software reset (After the software reset, the secondary image is used).

If there is a page with number of errors higher than ECC can correct during secondary
image read, the boot ROM goes to the serial loader.
8.5.2.3 Firmware configuration block

The FCB is the first sector in the first good block. The FCB must be present at each
search stride of the search area.
The search area contains copies of the FCB at each stride distance, so, in case the first
NAND block becomes corrupted, the ROM finds its copy in the next NAND block. The
search area must span over at least two NAND blocks. The location information for the
DBBT search area, FW1, and FW2 are all specified in the FCB. This table shows the
flash control block structure:
Table 8-11. Flash control block structure
Name Start byte Size in bytes Description
Reserved 0 4 Reserved for Fingerprint #1(Checksum)
FingerPrint 4 4 32-bit word with a value of 0x20424346, in ascii
"FCB"
Version 8 4 32-bit version number; this version of FCB is
0x00000001
m_NANDTiming 12 8 8 B of data for eight NAND timing parameters
from the NAND datasheet. The eight
parameters are:
m_NandTiming[0]=data_setup,
m_NandTiming[1]=data_hold,
m_NandTiming[2]=address_setup,
m_NandTiming[3]=dsample_time,
m_NandTiming[4]=nand_timing_state,
m_NandTiming[5]=REA,
m_NandTiming[6]=RLOH,
m_NandTiming[7]=RHOH.
The ROM only uses the first four parameters,
but the FCB provides space for other four
parameters to be used by the bootloader or
other applications.
PageDataSize 20 4 The number of bytes of data in a page.
Typically, this is 2048 bytes for 2112 bytes
page size or 4096 bytes for 4314/4224 bytes
page size or 8192 for 8568 bytes page size.
TotalPageSize 24 4 The total number of bytes in a page. Typically,
2112 for 2-KB page or 4224 or 4314 for 4-KB
page or 8568 for 8-KB page.

Table 8-11. Flash control block structure (continued)

SectorsPerBlock 28 4 The number of pages per block. Typically 64 or
128 or depending on the NAND device type.
NumberOfNANDs 32 4 Not used by ROM
TotalInternalDie 36 4 Not used by ROM
CellType 40 4 Not used by ROM
EccBlockNEccType 44 4 Value from 0 to 16 is used to set the BCH Error
Corrrection level 0, 2, 4, .. or 40 for Block BN of
ECC page, used in configuring the BCH40
page layout registers.
EccBlock0Size 48 4 Size of block B0 used in configuring the BCH40
page-layout registers.
EccBlockNSize 52 4 Size of block BN used in configuring the
BCH40 page-layout registers.
EccBlock0EccType 56 4 Value from 0 to 16 used to set the BCH Error
Corrrection level 0, 2, 4, .. or 40 for Block BN of
ECC page, used in configuring the BCH40
page layout registers.
MetadataBytes 60 4 Size of metadata bytes used in configuring the
NumEccBlocksPerPage 64 4 Number of the ECC blocks BN not including
B0. This value is used in configuring the
EccBlockNEccLevelSDK 68 4 Not used by ROM
EccBlock0SizeSDK 72 4 Not used by ROM
EccBlockNSizeSDK 76 4 Not used by ROM
EccBlock0EccLevelSDK 80 4 Not used by ROM
NumEccBlocksPerPageSDK 84 4 Not used by ROM
MetadataBytesSDK 88 4 Not used by ROM
EraseThreshold 92 4 Not used by ROM
Firmware1_startingPage 104 4 Page number address where the first copy of
bootable firmware is located.
Firmware2_startingPage 108 4 Page number address where the second copy
of bootable firmware is located.
PagesInFirmware1 112 4 Size of the first copy of firmware in pages.
PagesInFirmware2 116 4 Size of the second copy of firmware in pages.
DBBTSearchAreaStartAddress 120 4 Page address for the bad block table search
area.
BadBlockMarkerByte 124 4 This is an input offset in the BCH page for the
ROM to swap with the first byte of metadata
after reading a page using the BCH40. The
ROM supports the restoration of manufacturer-
marked bad block markers in the page and this
offset is the bad block marker offset location.


BadBlockMarkerStartBit 128 4 This is an input bit offset in the
BadBlockMarkerByte for the ROM to use when
swapping eight bits with the first byte of
metadata.
BBMarkerPhysicalOffset 132 4 This is the offset where the manufacturer
leaves the bad block marker on a page.
BCHType 136 4 0 for BCH20 and 1 for BCH40. The chip is
backwards compatible to BCH20 and this field
tells the ROM to use the BCH20 or BCH40
block.
TMTiming2_ReadLatency 140 4 Toggle mode NAND timing parameter read
latency, the ROM uses this value to configure
the timing2 register of the GPMI.
TMTiming2_PreambleDelay 144 4 Toggle mode NAND timing parameter
Preamble Delay. The ROM uses this value to
configure the timing2 register of the GPMI.
TMTiming2_CEDelay 148 4 Toggle mode NAND timing parameter CE
Delay. The ROM uses this value to configure
TMTiming2_PostambleDelay 152 4 Toggle mode NAND timing parameter
Postamble Delay. The ROM uses this value to
TMTiming2_CmdAddPause 156 4 Toggle mode NAND timing parameter Cmd
Add Pause. The ROM uses this value to
TMTiming2_DataPause 160 4 Toggle mode NAND timing parameter Data
Pause. The ROM uses this value to configure
TMSpeed 164 4 This is the toggle mode speed for the ROM to
configure the gpmi clock. 0 for 33 MHz, 1 for 40
MHz, and 2 for 66 MHz.
TMTiming1_BusyTimeout 168 4 Toggle mode NAND timing parameter Busy
Timeout. The ROM uses this value to configure
DISBBM 172 4 If 0, the ROM swaps the BadBlockMarkerByte
with metadata[0] after reading a page using the
BCH40. If the value is 1, the ROM does not
swap.
BBMark_spare_offset 176 4 The offset in the metadata place which stores
the data in the bad block marker place.
Onfi_sync_enable 180 4 Enable the Onfi nand sync mode support.
Onfi_sync_speed 184 4 Speed for the Onfi nand sync mode:
0 - 24 MHz, 1 - 33 MHz, 2 - 40 MHz, 3 - 50
MHz, 4 - 66 MHz, 5 - 80 MHz, 6 - 100 MHz, 7 -
133 MHz, 8 - 160 MHz, 9 - 200 MHz


Onfi_syncNANDData 188 28 The parameters for the Onfi nand sync mode
timing. They are read latency, ce_delay,
preamble_delay, postamble_delay,
cmdadd_pause, data_pause, and
busy_timeout.
DISBB_Search 216 4 Disable the bad block search function when
reading the firmware, only using DBBT.
8.5.2.4 Discovered Bad Block Table (DBBT)

See this table for the DBBT format:
Table 8-12. DBBT structure
reserved 0 4 -
FingerPrint 4 4 32-bit word with a value of 0x44424254,in
ascii "DBBT"
Version 8 4 32-bit version number; this version of
DBBT is 0x00000001
reserved 12 4 -
DBBT_NUM_OF_PAGES 16 4 Size of the DBBT in pages
reserved 20 4*PageSize-20 -
reserved 4*PageSize 4 -
Number of Entries 4*PageSize + 4 4 Number of bad blocks
Bad Block Number 4*PageSize + 8 4 First bad block number
Bad Block Number 4*PageSize + 12 4 Second bad block number
- - - Next bad block number
- - - -
Last bad block number - - Last bad block number
8.5.2.5 Bad block handling in ROM

During the firmware boot, at the block boundary, the Bad Block table is searched for a
match to the next block.
If no match is found, the next block can be loaded. If a match is found, the block must be
skipped and the next block checked.

If the Bad Block table start page is null, check the manufactory made Bad Block marker.
The location of the Bad Block maker is at the first three or last three pages in every block
of the NAND flash. The NAND manufacturers normally use one byte in the spare area of
certain pages within a block to mark that a block is bad or not. A value of 0xFF means
good block, non-FF means bad block.
To preserve the BI (bad block information), the flash updater or gang programmer
applications must swap the Bad Block Information (BI) data to byte 0 of the metadata
area for every page before programming the NAND flash. When the ROM loads the
firmware, it copies back the value at metadata[0] to the BI offset in the page data. This
figure shows how the factory bad block marker is preserved:
Bad block information at

column address 2048
64 B
2 KB Main area spare
512 main parity 512 main parity 512 main parity 512 main parity
meta
data Bad block information at
fourth block of data area
Swap byte
Figure 8-7. Factory bad block marker preservation
In the FCB structure, there are two elements (m_u32BadBlockMarkerByte and

m_u32BadBlockMarkerStartBit) to indicate the byte and bit place in the page data that
the manufacturer marked the bad block marker.
8.5.2.6 Toggle mode DDR NAND boot

If the BT_TOGGLEMODE efuse is blown, the ROM does the following to boot from the
Samsung's toggle mode DDR NAND.
8.5.2.6.1 GPMI and BCH clocks configuration

The ROM sets the clock source and the dividers in the CCM registers.

If the BOOT_CFG1[5] is set (toggle mode), the GPMI/BCH CLK source is PLL2PFD4,
and running at 66 MHz, otherwise the GPMI/ BCH CLK souce is PLL3, running at 24
MHz. The ROM sets the default values to timing0, timing1, and timing2 gpmi registers
for 24 MHz clock speed. It uses the BOOT_CFG2[7:5] fuse to configure the GPMI
timing2 register parameters preamble delay and read latency. The default value for these
parameters is 2 when the fuses are not blown.
The default timing parameter values used by the ROM for the toggle-mode device are:
• Timing0.ADDRESS_SETUP = 5
• Timing0.DATA_SETUP = 10
• Timing0.DATA_HOLD = 10
• Timing1.DEVICE_BUSY_TIMEOUT = 0 x 500
• Timing2.READ_LATENCY = BOOT_CFG2[7:5] if blown, otherwise 2
• Timing2.CE_DELAY = 2
• Timing2.PREAMBLE_DELAY = BOOT_CFG2[7:5] if blown, otherwise 2
• Timing2.POSTAMBLE_DELAY = 3
• Timing2.CMDADD_PAUSE = 4
• Timing2.DATA_PAUSE = 6
The default timing parameters can be overriden by the TMTiming2_ReadLatency,
TMTiming2_PreambleDelay, TMTiming2_CEDelay, TMTiming2_PostambleDelay,
TMTiming2_CmdAddPause, and TMTiming2_DataPause parameters of the FCB.
8.5.2.6.2 Setup DMA for DDR transfers

In the DMA descriptors, the GPMI is configured to read the page data at a double data
rate, the word length is set to 16, and the transfer count to a half of the page size.
8.5.2.6.3 Reconfigure timing and speed using values in FCB

After reading the FCB page with the GPMI set to default timings and a speed of 33 MHz,
the ROM reconfigures the CCM dividers to run the gpmi/bch clks to a desired speed
specified in the FCB for the rest of the boot process. The GPMI timing registers are also
reconfigured to the values specified in the FCB.
The GPMI speed can be configured using the FCB parameter TMSpeed:
• 0—24 MHz
• 1—33 MHz
• 2—40 MHz
• 3—50 MHz
• 4—66 MHz
• 5—80 MHz

• 6—100 MHz
• 7—133 MHz
• 8—160 MHz
• 9—200 MHz
The GPMI timing0 register fields data_setup, data_hold, and address_setup are set to the
values specified for the data_setup and data_hold and address_setup in the FCB member
m_NANDTiming.
The GPMI timing1.DEVICE_BUSY_TIMEOUT is set to the value specified in the FCB
member TMTiming1_BusyTimeout.
The GPMI timing2 register values are set using the FCB members
TMTiming2.READ_LATENCY, CE_DELAY, PREAMBLE_DELAY,
POSTAMBLE_DELAY, CMDADD_PAUSE, and DATA_PAUSE.
8.5.2.7 Typical NAND page organization
8.5.2.7.1 BCH ECC page organization

The first data block is called block 0 and the rest of the blocks are called block N. A
separate ECC level scan is used for block 0 and block N.
The metadata bytes must be located at the beginning of a page, starting at byte 0,
followed by the data block 0, the ECC bytes for data block 0, the block 1 and its ECC
bytes, and so on, up until the N data blocks. The ECC level for the block 0 can be
different from the ECC level for the rest of the blocks.
For the NAND boot with page-size restrictions and the data block size restricted to 512
B, only few combinations of the ECC for block 0 and block N are possible.
This figure shows the valid layout for 2112-byte sized page.
Block0 Block1 Block2 Block3

M 512 bytes EccB0 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN
Figure 8-8. Valid layout for 2112-byte sized page
The example below is for 13 bits of parity (GF13). The number of ECC bits required for
a data block is calculated using the (ECC_Correction_Level * 13) bits.

In the above layout, the ECC size for EccB0 and EccBN must be selected to not exceed a
total page size of 2112 bytes. The EccB0 and EccBN can be one of the 2, 4, 6, 8, 10, 12,
14, 16, 18, and 20 bits on the ECC correction level. The total bytes are:
[M + (data_block_size x 4) + ([EccB0 + (EccBN x 3)] x 13) / 8] <= 2112;
M = metadata bytes and data_block_size is 512.
There are four data blocks of 512 bytes each in a page of 2-KB page sized NAND. The
values of EccB0 and EccBN must be such that the above calculation does not result in a
value greater than 2112 bytes.

M 512 bytes EccB0 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN

512 bytes EccBN 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN
Figure 8-9. Valid layout for 4-KB sized page
Different NAND manufacturers have different sizes for a 4-KB page; 4314 bytes is
typical.
[M + (data_block_size x 8) + ([EccB0 + (EccBN x 7)] x 13) / 8] <= 4314;
M= metadata bytes and data_block_size is 512.
There are eight data blocks of 512 bytes each in a page of a 4-KB page sized NAND. The
values of the EccB0 and EccBN must be such that the above calculation does not result in
a value greater than the size of a page in a 4-KB page NAND.
8.5.2.7.2 Metadata
The number of bytes used for the metadata is specified in the FCB. The metadata for the
BCH encoded pages is placed at the beginning of a page. The ROM only cares about the
first byte of metadata to swap it with a bad block marker byte in the page data after each
page read; it is important to have at least one byte for the metadata bytes field in the FCB
data structure.

8.5.2.8 IOMUX configuration for NAND

The following table shows the RawNAND IOMUX pin configuration. The NAND boot
is only supported on chip select 0.
Table 8-13. NAND IOMUX pin configuration
Signal Pad name
CLE NANDF_CLE.alt0
ALE NANDF_ALE.alt0
WPN NANDF_WP_B.alt0
RD_N SD4_CMD.alt1
WRN SD4_CLK.alt1
READY0 NANDF_RB0.alt0
DQS SD4_DAT0.alt2
CE0N NANDF_CS0.alt0
CE1N NANDF_CS1.alt0
CE2N NANDF_CS2.alt0
CE3N NANDF_CS3.alt0
D0 NANDF_D0.alt0
D1 NANDF_D1.alt0
D2 NANDF_D2.alt0
D3 NANDF_D3.alt0
D4 NANDF_D4.alt0
D5 NANDF_D5.alt0
D6 NANDF_D6.alt0
D7 NANDF_D7.alt0
8.5.3 Expansion device

The ROM supports booting from the MMC/eMMC and SD/eSD compliant devices.
8.5.3.1 Expansion device eFUSE configuration

The SD/MMC/eSD/eMMC/SDXC boot can be performed using either the USDHC ports,
based on the setting of the BOOT_CFG2[4:3] (Port Select) fuse or it is associated to the
GPIO input value at the boot.
All USDHC ports support the eMMC4.3 and eMMC4.4 fast boot. See this table for
details:

Table 8-14. USDHC boot eFUSE descriptions

value
BOOT_CFG1[7:6] OEM Boot device selection Yes 00 01 - Boot from the USDHC interfaces
BOOT_CFG1[5] OEM SD/MMC selection Yes 0 0 - SD/eSD/SDXC
1 - MMC/eMMC
BOOT_CFG1[4] OEM Fast boot support Yes 0 0 - Normal boot
1 - Fast boot
BOOT_CFG1[3:2] OEM SD/MMC speed mode Yes 00 MMC
0 - High-speed mode
1 - Normal-speed mode
SD
00 - Normal (SDR12)
01 - High (SDR25)
10 - SDR50
11 - SDR104
BOOT_CFG1[1] OEM SD power cycle enable/ Yes 0 MMC
eMMC reset enable
0 - eMMC reset disabled
1 - eMMC reset enabled via the
SD_RST pad (on USDHC3 and
USDHC4 only)
SD
0 - No power cycle
1 - Power cycle enabled via the
SD_RST pad (on USDHC3 and
USDHC4 only)
BOOT_CFG1[0] OEM SD loopback clock source Yes 0 0 - Through the SD pad
sel (for SDR50 and
1 - Direct
SDR104 only)
BOOT_CFG2[7:5] OEM Bus width/SD calibration Yes 000 SD/eSD/SDXC (BOOT_CFG1[5]=0)
step
Bus width
xx0 - 1-bit
xx1 - 4-bit
SD calibration step
00x - 1 delay cells
01x - 1 delay cells
10x - 2 delay cells
11x - 3 delay cells
MMC/eMMC (BOOT_CFG1[5]=1)
000 - 1-bit
001 - 4-bit
010 - 8-bit

Table 8-14. USDHC boot eFUSE descriptions

(continued)
value
101 - 4-bit DDR (MMC 4.4)
110 - 8-bit DDR (MMC 4.4)
Else - reserved
BOOT_CFG2[4:3] OEM Port select Yes 00 00 - USDHC-1
01 - USDHC-2
10 - USDHC-3
11 - USDHC-4
BOOT_CFG2[2] OEM Boot frequencies Yes 0 0 - Boot ROM default
1 - Apply value per fuse field
MMC_DLL_DLY[6:0]
BOOT_CFG2[1] OEM Boot acknowledge disable/ Yes 0 MMC
pull down during power
0 - Boot acknowledge enabled
cycle enable
1 - Boot acknowledge disabled
SD
0 - Use default SD pad settings during
the power cycle
1 - Set pull-down on SD pads during
the power cycle (used only if "SD
Power Cycle Enable" is enabled)
BOOT_CFG2[0] OEM Override pad settings Yes 0 0 - Use default values
1 - Use PAD_SETTINGS values
MMC_DLL_DLY[6:0] OEM MMC DLL value/UHSI No 0000000 MMC DLL value/UHSI calibration start
calibaration start value value
1. The setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See GPIO boot overrides for
The boot code supports these standards:

• MMCv4.4 or less
• eMMCv4.4 or less
• SDv2.0 or less
• eSDv2.10 rev-0.9, with or without FAST_BOOT
• SDXCv3.0
The MMC/SD/eSD/SDXC/eMMC can be connected to any of the USDHC blocks and
can be booted by copying 4 KB of data from the MMC/SD/eSD/eMMC device to the
internal RAM. After checking the Image Vector Table header value (0xD1) from
program image, the ROM code performs a DCD check. After a successful DCD

extraction, the ROM code extracts from the Boot Data Structure the destination pointer
and length of image to be copied to the RAM device from where the code execution
occurs.
The maximum image size to load into the SD/MMC boot is 32 MB. This is due to a
limited number of uSDHC ADMA Buffer Descriptors allocated by the ROM.
NOTE
The initial 4 KB of the program image must contain the IVT,
DCD, and the Boot Data structures.
Table 8-15. SD/MMC frequencies
SD MMC MMC (DDR mode)
Identification (KHz) 347.22
Normal-speed mode (MHz) 25 20 25
High-speed mode (MHz) 50 40 50
UHSI SDR50 (MHz) 100
UHSI SDR104 (MHz) 200
NOTE
The boot ROM code reads the application image length and the
application destination pointer from the image.
8.5.3.2 MMC and eMMC boot

This table provides the MMC and eMMC boot details.
Table 8-16. MMC and eMMC boot details
Normal boot mode During the initialization (normal boot mode), the MMC
frequency is set to 347.22 KHz. When the MMC card enters
the identification portion of the initialization, the voltage
validation is performed, and the ROM boot code checks the
high-voltage settings and the card capacity. The ROM boot
code supports both the high-capacity and low-capacity MMC/
eMMC cards. After the initialization phase is complete, the
ROM boot code switches to a higher frequency (20 MHz in
the normal boot mode or 40 MHz in the high-speed mode).
The eMMC is also interfaced via the USDHC and follows the
same flow as the MMC.
The boot partition can be selected for an MMC4.x card after
the card initialization is complete. The ROM code reads the
BOOT_PARTITION_ENABLE field in the Ext_CSD[179] to get
the boot partition to be set. If there is no boot partition
mentioned in the BOOT_PARTITION_ENABLE field or the
user partition was mentioned, the ROM boots from the user
partition.

Table 8-16. MMC and eMMC boot details (continued)

eMMC4.3 or eMMC4.4 device supporting special boot mode If using an eMMC4.3 or eMMC4.4 device that supports the
special boot mode, it can be initiated by pulling the CMD line
low. If the BOOT ACK is enabled, the eMMC4.3/eMMC4.4
device sends the BOOT ACK via the DATA lines and the
ROM can read the BOOT ACK [S010E] to identify the
eMMC4.3/eMMC4.4 device. If the BOOT ACK is enabled, the
ROM waits 50 ms to get the BOOT ACK. If BOOT ACK is
disabled ROM waits 1 second for data. If the BOOT ACK or
data was received, the eMMC4.3/eMMC4.4 is booted in the
"boot mode", otherwise the eMMC4.3/eMMC4.4 boots as a
normal MMC card from the selected boot partition. This boot
mode can be selected by the BOOT_CFG1[4] (fast boot) fuse.
The BOOT ACK is selected by the BOOT_CFG2[1] fuse.
eMMC4.4 device If using the eMMC4.4 device, the Double Data Rate (DDR)
mode can be used. This mode can be selected by the
BOOT_CFG2[7:5] (bus width) fuse.
Start
Check data bus width fuse.

. Accordingly
do the IOMUX config
eSDHC Software Reset, Set RSTA
Set Identification Frequency

(Approx 400 KHz)
Check MMC and Fast Boot Yes

6
Selection Fuse
No
Set INITA to send 80 SDCLK to card
Card SW Reset (CMD0)
No
Command Successful? 5
Yes
SD MMC
1 Check SD/MMC Selection fuse 2
Figure 8-10. Expansion device boot flow (1 of 6)

Set Strong pull-up

For CMD line
Start GPT with 1s delay MMC Boot Set MMC card CSD Set operating frequency MMC Boot
Voltage Validation (Issue CMD9) to 20 MHz Device Init
for CMD1
Set Weak pull-up Put card data Transfer
For CMD line Mode (Issue CMD7)
Issue CMD1 with HV Increment loop counter
Yes Yes
No No
Command Successful? Command Successful?
No Yes
No Send CMD13 to read
Yes Set RCA (Issue CMD3) status
Yes Loop Cntr < 3000 and Yes
Busy Bit == 1 Yes
looping period < 1s Card State ==
No 5
Command Successful? TRANS?
No
Is Response OCR for Yes Yes
Card Is HC MMC
HC Get CID from card(Issue No
Spec ver >= 4.0?
CMD2)
No Yes
Card Is LC MMC
Send CMD8 to get
Ext_CSD
No Bus width No High Speed mode Extract the boot partition

fuse <> 1? fuse == 0? to set
Yes Yes No
Send switch command Got valid partition?
Send switch command
to change bus width and
to set high frequency
DDR mode Yes
Yes Yes
No No Send switch command
4 Switch Successful? Switch Successful? to select partition
Yes Yes
Change ESDHC bus Set operating frequency
width to 40 MHz
Start MMC Boot

Switch Command
Send CMD6 with switch

argument
No
Command Successful?
Yes
Set CMD13 poll timeout
to 100ms
Send CMD13 to read

status
Command Successful?
No Yes
CMD13 Poll No Card State ==
timeout? TRANS?
Yes Yes
Switch failed Switch succeeded Switch failed
End
Figure 8-11. Expansion device (MMC) boot flow (2 of 6)

Issue CMD8 with HV

(3.3V) SD Boot
Voltage Validation
No Issue CMD8 with LV No
Command Successful? Command Successful?
(1.8V)
Yes Yes
Card is HC/LC HV SD
ver 2.x
Set ACMD41 ARG to LV Card is LC SD Card is LC SD
and HC ver 2.x ver 1.x
Set ACMD41 ARG to HV No
UHSI mode Set ACMD41 ARG bit 29
and HC selected? for FAST BOOT
Yes
Start GPT delay of1s for Set ACMD41 ARG to HV
Set ACMD41 ARG bit 24
ACMD41 and LC
for 1.8v switch
Issue CMD55
Set ACMD41 ARG bit 28
for SDXC power control
No
Command Successful?
Yes Yes
FAST_BOOT Yes
selected? No Loop Cntr < 3000 and
Issue ACMD41 2
looping period < 1s
No
No
Command Successful?
UHSI mode No Yes

Busy Bit == 1 Issue ACMD41
selected?
Yes
Bit 24 of response No
2
0 set?
Yes
No Is Response OCR for Yes

Card is LC SD Card is HC SD
HC
Figure 8-12. Expansion device (SD/eSD/SDXC) boot flow (3 of 6) part 1

8 SD Boot
Switch Voltage
Send CMD11 to switch

voltage
No
Command Successful?
Yes
No
DATA lines driven low?
Yes
switch supply voltage
to 1.8v
delay for 5ms
set DATA line voltage

high poll timeout to
1ms
No
Voltage high No DATA lines
poll timeout? driven high?
Yes Yes
Switch failed Switch succeeded
2 7
Figure 8-13. Expansion device (SD/eSD/SDXC) boot flow (3 of 6) part 2

Get CID from card(Issue

CMD2)
SD Boot
Device Initialization
Yes Yes Set operating frequency

Command Successful? Get RCA (Issue CMD3) Command Successful?
to 20 MHz
No No
Put card data Transfer
5 Mode (Issue CMD7)
No
No
Card State == Send CMD13 to read Yes
TRANS? Command Successful?
status
Yes
Yes
UHSI mode selected? 9
No
Yes Yes Send ACMD6 with bus Command Successful?

Bus width Send CMD55 Command Successful?
fuse <> 1? width argument Yes
No No
No
Change USDHC bus Yes Set CMD13 poll timeout

Success? Check Status
width to 100ms
No
High Speed mode
fuse == 0? Yes
Send CMD6 with high Yes Set operating frequency
No Command Successful?
speed argument to 40 MHz
No
Send CMD43 to select
10
partition 1
No
Yes Set CMD13 poll timeout

to 15ms
FAST_BOOT Yes
Card is eSD
selected? Set CMD13 poll timeout Check Status
No to 1s
9 SD Boot
UHSI init
Check response of
CMD7
Yes No
Card is locked?
No
No Send ACMD6 with Yes
Command Successful? Command Successful? Send CMD55
argument of 4 bit width
Yes
Set CMD13 poll timeout Yes Change USDHC bus
Check Status Success?
to 100ms width
No
No Send CMD6 with clock Get clock speed from

Command Successful?
speed argument fuse
Yes
Change USDHC clock Loopback clock Yes Set loopback clock bit in
speed fuse set? USDHC register
No
Init failed
11
Figure 8-14. Expansion device (MMCSD/eSD/SDXC) boot flow (4 of 6)

SD Boot USB Boot

Check Status
Serial Boot
Start 5
Send CMD13 to read

status USB Flow
(Serial Boot)
No
Command Successful?
Yes
CMD13 Poll No Card State ==
timeout? TRANS?
Yes
Failure Success Failure
End
4 SD/MMC Boot
Data Read
No Set block length 512

DDR Mode Selected?
bytes (Issue CMD16)
Yes
Init ADMA buffer Yes

Command Successful?
descriptors
No
Send CMD18 (multiple
block read)
Set CMD18 poll timeout

to 1s
Wait for command

completion or timeout
No
Yes
End
Figure 8-15. Expansion device (SD/eSD) boot flow (5 of 6)

6
eMMC 4.x Boot
Fast Boot
High Speed mode Set operating frequency

fuse == 0? to 40 MHz
Set operating frequency

to 20 MHz
Change ESDHC bus

width and configure DLL
Setup ADMA BD[0]

length to 2K and BD[1]
to 32 bytes
Wait for block gap or Wait for block gap or

Set CMD line low Reached block gap? timeout
timeout
Set ESDHC poll counter Analyze IVT and setup

to 50ms ADMA buffer descriptors
to final destination
Wait for acknowledge
token or timeout Continue data trasmition
Acknowledge token Set GPT poll counter to Wait for block gap or
accepted? 1s timeout
End
2
SD Boot
11 sample point tuning
Set bottom boundary to

current value
Get start point and
ramping step from fuse
Increase current value

Set the USDHC into with ramping step
tuning mode
Yes
Set the USDHC into Exceed limit?
tuning mode
No
Configure the block
Set delay cell number to
length and block number
current value
Configure the block Send CMD19 to request

length and block number the tuning block
Send CMD19 to request

the tuning block Check the tuning status
Check the tuning status Yes

Tuning passed?
No
No
Exceed limit? No
Tuning passed?
Set upper boundary to
Yes last value
Yes
Increase current value

Tuning failed with ramping step Set delay cell number to
Tuning passed average of bottom and
upper boundary value
4 10
Figure 8-16. Expansion device boot flow (6 of 6)

8.5.3.3 SD, eSD, and SDXC

After the normal boot mode initialization begins, the SD/eSD/SDXC frequency is set to
347.22 kHz. During the identification phase, the SD/eSD/SDXC card voltage validation
is performed. During the voltage validation, the boot code first checks with the high-
voltage settings; if that fails, it checks with the low-voltage settings.
The capacity of the card is also checked. The boot code supports the high-capacity and
low-capacity SD/eSD/SDXC cards after the voltage validation card initialization is done.
During the card initialization, the ROM boot code attempts to set the boot partition for all
SD, eSD, and SDXC devices. If this fails, the boot code assumes that the card is a normal
SD or SDXC card. If it does not fail, the boot code assumes it is an eSD card. After the
initialization phase is over, the boot code switches to a higher frequency (25 MHz in the
normal-speed mode or 50 MHz in the high-speed mode). The ROM also supports the
FAST_BOOT mode booting from the eSD card. This mode can be selected by the
BOOT_CFG1[4] (Fast Boot) fuse described in Table 8-14 .
For the UHSI cards, the clock speed fuses can be set to SDR50 or SDR104 on USDHC3
and USDHC4 ports. This enables the voltage switch process to set the signaling voltage
to 1.8 V during the voltage validation. The bus width is fixed at a 4-bit width and a
sampling point tuning process is needed to calibrate the number of the delay cells. If the
SD Loopback Clock eFuse is set, the feedback clock comes directly from the loopback
SD clock, instead of the card clock (by default). The SD clock speed can be selected by
the BOOT_CFG1[3:2], and the SD Loopback Clock is selected by the BOOT_CFG1[0].
NOTE
SDR50 and SDR104 boot are not supported on USDHC1 and
USDHC2, because there is no reset signal for those ports in the
IOMUXC.
The UHSI calibration start value (MMC_DLL_DLY[6:0]) and the step value
(BOOT_CFG2[7:5]) can be set to optimize the sample point tuning process.
If the SD Power Cycle Enable eFuse is 1, the ROM sets the SD_RST pad low, waits for 5
ms, and then sets the SD_RST pad high. If the SD_RST pad is connected to the SD
power supply enable logic on board, it enables the power cycle of the SD card. This may
be crucial in case the SD logic is in the 1.8 V states and must be reset to the 3.3 V states.

8.5.3.4 IOMUX configuration for SD/MMC

Table 8-17. SD/MMC IOMUX pin configuration
Signal USDHC-1 USDHC-2 USDHC-3 USDHC-4
CLK SD1_CLK.alt0 SD2_CLK.alt0 SD3_CLK.alt0 SD4_CLK.alt0
CMD SD1_CMD.alt0 SD2_CMD.alt0 SD3_CMD.alt0 SD4_CMD.alt0
DAT0 SD1_DAT0.alt0 SD2_DAT0.alt0 SD3_DAT0.alt0 SD4_DAT0.alt1
DAT4 NANDF_D0.alt1 NANDF_D4.alt1 SD3_DAT4.alt0 SD4_DAT4.alt1
VSELECT GPIO_18.alt2 NANDF_CS1.alt1
RESET 1 SD3_RESET.alt0 NANDF_ALE.alt1
CD GPIO_1.alt6 GPIO_4.alt6 - -
1. Active-low
8.5.3.5 Redundant boot support for expansion device

The ROM supports the redundant boot for an expansion device. The primary or
secondary image is selected, depending on the PERSIST_SECONDARY_BOOT setting.
(see Table 8-6).
If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address 0x400 for the
primary image.
If the PERSIST_SECONDARY_BOOT is 1, the boot ROM reads the secondary image
table from address 0x200 on the boot media and uses the address specified in the table for
the secondary image.
Table 8-18. Secondary image table format
Reserved (chipNum)
Reserved (driveType)
tag
firstSectorNumber
Reserved (sectorCount)
Where:

• The tag is used as an indication of the valid secondary image table. It must be
0x00112233.
• The firstSectorNumber is the first 512-byte sector number of the secondary image.
For the secondary image support, the primary image must reserve the space for the
secondary image table. See this figure for the typical structures layout on an expansion
device.
Reserved For MBR 0x00000000

(optional)
0x00000200
Reserved for Secondary
Image Table (optional)
0x00000400
Program Image (Starting

From IVT)
Media Partitions
Figure 8-17. Expansion device structures layout

For the Closed mode, if there are failures during primary image authentication, the boot
ROM turns on the PERSIST_SECONDARY_BOOT bit (see Table 8-6) and performs the
software reset. (After the software reset, the secondary image is used.)
8.5.4 Hard disk and SSD

The chip supports booting from the hard disk and SSD devices using the SATA interface.
8.5.4.1 Hard disk and SSD eFUSE configuration

The boot ROM code determines the type of device using the following parameters, either
provided by the eFUSE settings, or sampled on the I/O pins, during the boot.
Table 8-19. HDD eFUSE descriptions
value
BOOT_CFG1[7:4] OEM Boot device selection Yes 0000 0010 - Boot from hard disk
BOOT_CFG2[4] OEM Tx spread spectrum Yes 0 0 - Disabled
1 - Enabled
BOOT_CFG2[3] OEM Rx spread spectrum Yes 0 0 - Enabled
1 - Disabled
BOOT_CFG2[2] OEM SATA speed Yes 0 0 - Gen2 (3.0 Gbit/s)
1 - Gen1 (1.5 Gbit/s)
BOOT_CFG2[1:0] OEM SATA type Yes 00 00 - i (internal electrical specifications with a
cable length of up to 1 m, see the Serial ATA
specification)
01 - m (electrical specifications used in the
Short Backplane Application and the
External Desktop Application, see the Serial
ATA specification)
10 - x (external cabled applications or Long
Backplane Applications, see the Serial ATA
specification)
11 - Reserved
1. The setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See Table 1 for the
corresponding GPIO pin.
The boot ROM sends the IDENTIFY command to the hard disk during the initialization.
When the identification block is received, the boot ROM assumes that the device is
ready. The boot ROM sends a separate command for each sector of 512 bytes in the PIO
mode.

The boot ROM copies 4 KB of data from the hard disk or SSD device to the internal
RAM. After checking the Image Vector Table header value (0xD1) from the program
image, the ROM code performs a DCD check. After a successful DCD extraction, the
ROM code extracts the destination pointer and length of image to be copied to the RAM
device from the Boot Data Structure, where the code execution occurs.
NOTE
The Initial 4 KB of program image must contain the IVT, DCD,
and the Boot Data structures.
8.5.4.2 IOMUX and timing configuration for SATA

The interface signals of the SATA PHY are not configured in the IOMUX. The SATA
PHY interface uses dedicated contacts on the IC. See the chip data sheet for details.
The ROM reads the TX Spread Spectrum, RX Spread Spectrum, Speed and Type of
SATA, and configures the timing parameters via the IOMUX GPR register.
8.5.4.3 Redundant boot support for hard disk and SSD

The ROM supports redundant boot for the hard disk and SSD. The primary or secondary
image is selected depending on the PERSIST_SECONDARY_BOOT setting (see Table
8-6).
If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address 0x400 for the
primary image.
If the PERSIST_SECONDARY_BOOT is 1, the boot ROM reads the secondary image
table from address 0x200 on the boot media and uses the address specified in the table for
the secondary image.
Table 8-20. Secondary image table format
Reserved (chipNum)
Reserved (driveType)
tag
firstSectorNumber
Reserved (sectorCount)
Where:

• The tag is used as an indication of a valid secondary image table. It must be

0x00112233.
• The firstSectorNumber is the first 512-byte sector number of the secondary image.
For the secondary image support, the primary image must reserve the space for the
secondary image table. See this figure for typical structures layout on an expansion
device:
Reserved For MBR 0x00000000

(optional)
0x00000200
Reserved for Secondary
Image Table (optional)
0x00000400
Program Image (Starting

From IVT)
Media Partitions
Figure 8-18. Hard disk structures layout
For the Closed mode, if there are failures during the primary image authentication, the
boot ROM turns on the PERSIST_SECONDARY_BOOT bit (see Table 8-6) and
performs a software reset. (After software reset, the secondary image is used).

8.5.5 Serial ROM through SPI and I2C

The chip supports booting from serial memory devices, such as EEPROM and serial
flash, using the SPI.
These ports are available for serial boot: eCSPI (eCSPI1, eCSPI2, eCSPI3, eCSPI4,
eCSPI5) and I2C controller (I2C1, I2C2 and I2C3) interfaces.
8.5.5.1 Serial ROM eFUSE configuration

The boot ROM code determines the type of device using the following parameters, either
provided by the eFUSE settings or sampled on the I/O pins, during boot.
See this table for details:
Table 8-21. Serial ROM boot eFUSE descriptions
value
BOOT_CFG1[7:4] OEM Boot device selection Yes 0000 0011 - Boot from the serial ROM
BOOT_CFG4[6] OEM EEPROM recovery Yes 0 0 - Disabled EEPROM recovery
enable
1 - Enabled EEPROM recovery
BOOT_CFG4[5:4] OEM CS select (SPI only) Yes 00 00 - ECSPIx_SS0
01 - ECSPIx_SS1
10 - ECSPIx_SS2
11 - ECSPIx_SS3
BOOT_CFG4[3] OEM SPI addressing (SPI Yes 0 0 - 2 B (16-bit)
only)
1 - 3 B (24-bit)
BOOT_CFG4[2:0] OEM Port select Yes 00 000 - ECSPI-1
001 - ECSPI-2
010 - ECSPI-3
011 - ECSPI-4
100 - ECSPI-5
101 - I2C1
110 - I2C2
111 - I2C3
1. The setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See GPIO Boot Overrides for

The ECPSI-1/ECPSI-2/ECPSI-3/ECPSI-4/ECSPI-5 block can be used as a boot device

using the ECSPI interface for the serial ROM boot. The SPI interface is configured to
operate at 15 MHz for 3-byte addressing devices and at 3.75 MHz for 2-byte addressing
devices.
The I2C-1/I2C-2/I2C-3 block can be used as a boot device using the I2C interface for the
serial ROM boot. The I2C interface is configured to operate at 343.75 kbit/s.
The boot ROM copies 4 KB of data from the serial ROM device to the internal RAM.
After checking the Image Vector Table header value (0xD1) from the program image, the
ROM code performs a DCD check. After a successful DCD extraction, the ROM code
extracts the destination pointer and length of image from the Boot Data Structure to be
copied to the RAM device from where the code execution occurs.
NOTE
The Initial 4 KB of program image must contain the IVT, DCD,
and the Boot Data Structures.
8.5.5.2 I2C boot

The boot flow when booting from the I2C device is shown in Figure 8-19.
The boot ROM code reads the fuses BOOT_CFG1[7:4] (Boot Device Selection) and
BOOT_CFG1[7:4] (Port select) to detect the EEPROM device type. The ROM program
copies 4 KB of data from the EEPROM device to the internal RAM. The boot ROM code
then copies the initial 4 KB of data as well as the rest of the image directly to the
application destination extracted from the application image.
The chip uses the Device Select Code/Device Address in the following table to boot from
the EEPROM.
Table 8-22. EEPROM via I2C device select code
Bits Device type identifier Chip enable address1 R/W
7 6 5 4 3 2 1 0
Device 1 0 1 0 0 0 0 R/W
select code
1. These address bits must be configured at the memory device to match this '000' value.

Start
IOMUX configuration, set the

data rate, enable I2C
Set xfer mode to transmit
Send start Note:

Failure in any of these steps will abort the boot and
jump to serial boot flow.
This is very high level flow diagram of I2C.
. For more
Send slave address details please see the I2C module description
Send MSB of source address
Send LSB of source address
Send repeat start
Send slave address with read

mode enabled
Set xfer mode to receive
Read
Data
Figure 8-19. I2C flow chart
8.5.5.2.1 I2C IOMUX pin configuration

The contacts assigned to the signals used by the I2C blocks are shown in these tables:
Table 8-23. I2C IOMUX pin configuration
Signal I2C-1 I2C-2 I2c-3
SDA EIM_D28.alt1 EIM_D16.alt6 EIM_D18.alt6
SCL EIM_D21.alt6 EIM_EB2.alt6 EIM_D17.alt6

8.5.5.3 ECSPI boot

The Enhanced Configurable SPI (ECSPI) interface is configured in the master mode and
the EEPROM device is connected to the ECSPI interface as a slave.
The boot ROM code copies 4 KB of data from the EEPROM device to the internal RAM.
If the DCD verification is successful, the ROM code copies the initial 4 KB of data, as
well as the rest of the image extracted from the application image, directly to the
application destination. The ECSPI can read data from the EEPROM using 2- or 3-byte
addressing. Its burst length is 32 B.
NOTE
The Serial ROM Chip Select Number is determined by the
BOOT_CFG4[5:4] (Chip Select) fuse.
When using the SPI as a boot device, the chip supports booting from both the serial
EEPROM and serial flash devices. The boot code determines which device is being used
by reading the appropriate eFUSE/I/O values at the boot (see Table 8-21 for details).

Start
no Configure CSPI clock

END
divider==success
yes
EEPROM Read data NO
Set instruction length

address cycle according If read data length>0
to fuses
If read data length

greater than (burst Assign MSB as read
instruction (0x30)
length-instruction
and other 2/3 byte dest
length)
address in data pointer
Assign MSB as read

NO
instruction (0x30) and other Send read instruction to
2/3 byte dest address read remaining length
in data pointer of data
Send read instruction to

read burst length of data If read instruction status
is CSPI_SUCCESS
If read instruction status

is CSPI_SUCCESS yes
Read remaining length
yes of data and copy to B
Read burst length of destination pointer
data and copy to yes B
destination pointer
NO
Disable CSPI
Increment destination
pointer and reduce
length of data read
END
Figure 8-20. CSPI flow chart
8.5.5.3.1 ECSPI IOMUX pin configuration

The contacts assigned to the signals used by the CSPI blocks are shown in this table:
Table 8-24. ECSPI IOMUX pin configuration
Signal ECSPI-1 ECSPI-2 ECSPI-3 ECSPI4 ECSPI-5
MISO EIM_D17.alt1 CSI0_DAT10.alt2 DISP0_DAT2.alt2 EIM_D22.alt1 SD1_DAT0.alt1
MOSI EIM_D18.alt1 CSI0_DAT9.alt2 DISP0_DAT1.alt2 EIM_D28.alt2 SD1_CMD.alt1

Table 8-24. ECSPI IOMUX pin configuration

(continued)
RDY N/A1 N/A N/A N/A N/A
SCLK EIM_D16.alt1 CSI0_DAT8.alt2 DISP0_DAT0.alt2 EIM_D21.alt1 SD1_CLK.alt1
SS0 EIM_EB2.alt1 CSI0_DAT11.alt2 DISP0_DAT3.alt2 EIM_D20.alt1 SD1_DAT1.alt1
SS1 EIM_D19.alt1 EIM_LBA.alt1 DISP0_DAT4.alt2 EIM_A25.alt1 SD1_DAT2.alt1
SS2 EIM_D24.alt1 EIM_D24.alt4 DISP0_DAT5.alt2 EIM_D24.alt1 SD1_DAT3.alt1
SS3 EIM_D25.alt1 EIM_D25.alt4 DISP0_DAT6.alt2 EIM_D25.alt1 SD2_DAT3.alt1
1. The N/A in the ROM code indicates that the pins are not available or not used.
8.6 Program image

This section describes the data structures that are required to be included in the user's
program image. The program image consists of:
• Image vector table—a list of pointers located at a fixed address that the ROM
examines to determine where the other components of the program image are
located.
• Boot data—a table that indicates the program image location, program image size in
bytes, and the plugin flag.
• Device configuration data—IC configuration data.
• User code and data.
8.6.1 Image Vector Table and Boot Data

The Image Vector Table (IVT) is the data structure that the ROM reads from the boot
device supplying the program image containing the required data components to perform
a successful boot.
The IVT includes the program image entry point, a pointer to Device Configuration Data
(DCD) and other pointers used by the ROM during the boot process.The ROM locates
the IVT at a fixed address that is determined by the boot device connected to the Chip.
The IVT offset from the base address and initial load region size for each boot device

Program image
type is defined in the table below. The location of the IVT is the only fixed requirement
by the ROM. The remainder or the image memory map is flexible and is determined by
the contents of the IVT.
Table 8-25. Image Vector Table Offset and Initial Load Region Size
Boot Device Type Image Vector Table Offset Initial Load Region Size
NOR 4 Kbyte = 0x1000 bytes Entire Image Size
NAND 1 Kbyte = 0x400 bytes 4 Kbyte
OneNAND 256 bytes = 0x100 bytes 1 Kbyte
SD/MMC/eSD/eMMC/SDXC 1 Kbyte = 0x400 bytes 4 Kbyte
I2C/SPI EEPROM 1 Kbyte = 0x400 bytes 4 Kbyte
SATA 1 Kbyte = 0x400 bytes 4 Kbyte
Initial
Load Region
Figure 8-21. Image Vector Table
8.6.1.1 Image vector table structure

The IVT has the following format where each entry is a 32-bit word:

Table 8-26. IVT format

header
entry: Absolute address of the first instruction to execute from the image
reserved1: Reserved and should be zero
dcd: Absolute address of the image DCD. The DCD is optional so this field may be set to NULL if no DCD is required. See
Device Configuration Data (DCD) for further details on the DCD.
boot data: Absolute address of the boot data
self: Absolute address of the IVT. Used internally by the ROM.
csf: Absolute address of the Command Sequence File (CSF) used by the HAB library. See High-Assurance Boot (HAB) for
details on the secure boot using HAB. This field must be set to NULL when not performing a secure boot
reserved2: Reserved and should be zero
Figure 8-22 shows the IVT header format:
Tag Length Version
Figure 8-22. IVT header format
where:
Tag: A single byte field set to 0xD1
Length: a two byte field in big endian format containing the overall length of the IVT,
in bytes, including the header. (the length is fixed and must have a value of
32 bytes)
Version: A single byte field set to 0x40 or 0x41
8.6.1.2 Boot data structure

The boot data must follow the format defined in the table found here, each entry is a 32-
bit word.
Table 8-27. Boot data format
start Absolute address of the image
length Size of the program image
plugin Plugin flag (see Plugin image)

Program image
8.6.2 Device Configuration Data (DCD)

Upon reset, the chip uses the default register values for all peripherals in the system.
However, these settings typically are not ideal for achieving the optimal system
performance and there are even some peripherals that must be configured before they can
be used.
The DCD is a configuration information contained in the program image (external to the
ROM) that the ROM interprets to configure various peripherals on the chip.
For example, the EIM default settings allow the core to interface to a NOR flash device
immediately after the reset. This allows the chip to interface with any NOR flash device,
but has the disadvantage of slow performance. Additionally, some components (such as
DDR) require some sequence of register programming as a part of the configuration
before it is ready to be used. The DCD feature can be used to program the EIM registers
and the MMDC registers to the optimal settings.
The ROM determines the location of the DCD table based on the information located in
the Image Vector Table (IVT). See Image Vector Table and Boot Data for more details.
The DCD table shown below is a big-endian byte array of the allowable DCD commands.
The maximum size of the DCD is limited to 1768 B.
Header
[CMD]
[CMD]
...
Figure 8-23. DCD data format
The DCD header is 4 B with the following format:
Tag Length Version
Figure 8-24. DCD header format
where:

Tag: A single-byte field set to 0xD2
Length: a two-byte field in the big-endian format containing the overall length of the DCD
(in bytes) including the header
Version: A single-byte field set to 0x41
8.6.2.1 Write data command

The write data command is used to write a list of given 1-, 2- or 4-byte values (or
bitmasks) to a corresponding list of target addresses.
The format of the write data command (in a big-endian byte array) is shown in this table:
Table 8-28. Write data command format
Tag Length Parameter
Address
Value/Mask
[Address]
[Value/Mask]
...
[Address]
[Value/Mask]
where:
Tag: a single-byte field set to 0xCC
Length: a two-byte field in a big-endian format, containing the length of the Write Data
Command (in bytes) including the header
Address: the target address to which the data must be written
Value/Mask: the data value (or bitmask) to be written to the preceding address
The parameter field is a single byte divided into the bitfields, as follows:
Table 8-29. Write data command parameter field
7 6 5 4 3 2 1 0
flags bytes
where
bytes: the width of the target locations in bytes (either 1, 2, or 4)
flags: control flags for the command behavior
Data Mask = bit 3: if set, only specific bits may be overwritten at the target address
(otherwise all bits may be overwritten)
Data Set = bit 4: if set, the bits at the target address are overwritten with this flag
(otherwise it is ignored)
One or more target address and value/bitmask pairs can be specified. The same bytes' and
flags' parameters apply to all locations in the command.

Program image
When successful, this command writes to each target address in accordance with the flags
as follows:
Table 8-30. Interpretation of write data command flags
"Mask" "Set" Action Interpretation
0 0 *address = val_msk Write value
0 1 *address = val_msk Write value
1 0 *address &= ~val_msk Clear bitmask
1 1 *address |= val_msk Set bitmask
NOTE
If any of the target addresses does not have the same alignment
as the data width indicated in the parameter field, none of the
values are written.
If any of the values are larger or any of the bitmasks are wider
than permitted by the data width indicated in the parameter
field, none of the values are written.
If any of the target addresses do not lie within the allowed
region, none of the values are written. The list of allowable
blocks and target addresses for the chip are provided below.
Table 8-31. Valid DCD address ranges
Address range Start address Last address
IOMUX Control (IOMUXC) registers 0x020E0000 0x020E3FFF
CCM register set 0x020C4000 0x020C7FFF
ANADIG registers 0x020C8000 0x020C8FFF
MMDC register set 0x021B0000 0x021B7FFF
IRAM free space 0x00907000 0x00937FF0
EIM memory 0x08000000 0x0FFEFFFF
EIM registers 0x021B8000 0x021BBFFF
DDR 0x10000000 0xFFFFFFFF
8.6.2.2 Check data command

The check data command is used to test for a given 1-, 2-, or 4-byte bitmasks from a
source address.

The check data command is a big-endian byte array with the format shown in this table:
Table 8-32. Check data command format
Tag Length Parameter
Address
Mask
[Count]
where:
Tag: a single-byte field set to 0xCF
Length: a two-byte field in the big-endian format containing the length of the check data
command (in bytes) including the header
Address: the source address to test
Mask: the bit mask to test
Count: an optional poll count; If the count is not specified, this command polls
indefinitely
until the exit condition is met. If count = 0, this command behaves as for the NOP.
The parameter field is a single byte divided into bitfields, as follows:

Table 8-33. Check data command parameter field
7 6 5 4 3 2 1 0
flags bytes
where
bytes: the width of target locations in bytes (either 1, 2, or 4)
flags: control flags for the command behavior
Data Mask = bit 3: if set, only the specific bits may be overwritten at a target address
(otherwise all bits may be overwritten)
Data Set = bit 4: if set, the bits at the target address are overwritten with this flag
(otherwise it is ignored)
This command polls the source address until either the exit condition is satisfied, or the
poll count is reached. The exit condition is determined by the flags as follows:
Table 8-34. Interpretation of check data command flags
"Mask" "Set" Action Interpretation
0 0 (*address & mask) == 0 All bits clear
0 1 (*address & mask) == mask All bits set
1 0 (*address & mask)!= mask Any bit clear
1 1 (*address & mask)!= 0 Any bit set
NOTE
If the source address does not have the same alignment as the
data width indicated in the parameter field, the value is not
read.
Program image
If the bitmask is wider than permitted by the data width

indicated in the parameter field, the value is not read.
8.6.2.3 NOP command

This command has no effect.
The format of the NOP command is a big-endian four-byte array, as shown in this table:
Table 8-35. NOP command format
Tag Length Undefined
where:
Tag: a single-byte field set to 0xC0
Length: a two-byte field in big endian containing the length of the NOP command in bytes
(fixed to a
value of 4)
Undefined: this byte is ignored and can be set to any value.
8.6.2.4 Unlock command

The unlock command is used to prevent specific engine features from being locked when
exiting the ROM.
The format of the unlock command (in a big-endian byte array) is shown in this table:
Table 8-36. Unlock command format
Tag Length Eng
Value
Value
...
Value
where:
Tag: a single-byte field set to 0xB2

Eng: the engine to be left unlocked
Values: [optional] the unlock values required by the engine
NOTE
This command may not be used in the DCD structure if the
SEC_CONFIG is configured as closed.

8.7 Plugin image

The ROM supports a limited number of boot devices. When using other devices as a boot
source (for example, Ethernet, CDROM, or USB), the supported boot device must be
used (typically serial ROM) as a firmware to provide the missing boot drivers.
Additionally, the plugin can be customized to support boot drivers, which is more
flexible when performing the device initialization, such as condition judging, delay
assertion, or to apply custom settings to the boot device and memory system.
In addition to the standard images, the chip also supports plugin images. The plugin
images return the execution to the ROM whereas the standard image does not.
The boot ROM detects the image type using the plugin flag of the boot data structure (see
Boot data structure). If the plugin flag is 1, then the ROM uses the image as a plugin
function. The function must initialize the boot device and copy the program image to the
final location. At the end, the plugin function must return with the program image
parameters. (See High-level boot sequence for details about the boot flow).
The boot ROM authenticates the plugin image before running the plugin function and
then authenticates the program image.
The plugin function must follow the API described below:
typedef BOOLEAN (*plugin_download_f)(void **start, size_t *bytes, UINT32
*ivt_offset);
ARGUMENTS PASSED:
• start - the image load address on exit.
• bytes - the image size on exit.
• ivt_offset - the offset (in bytes) of the IVT from the image start address on exit.
RETURN VALUE:
• 1 - success
• 0 - failure
8.8 Serial Downloader

The Serial Downloader provides a means to download a program image to the chip over
the USB serial connection.

Serial Downloader
In this mode, the ROM programs the WDOG1 for a 90-second time-out if the
WDOG_ENABLE eFuse is 1 and continuously polls for the USB connection. If no
activity is found on the USB OTG1 and the watchdog timer expires, the Arm core is
reset.
NOTE
After the downloaded image is loaded, it is responsible for
managing the watchdog resets properly.
This figure shows the USB boot flow:
START
Configure USBOTG1,
, program WDOG for 32 sec timer
Poll USBOTG1 No
WDOG_ENABLE
Activity
No == 1 &&
Detected
90 sec over
Yes
Yes
Complete USB HID enumeration
Ready for Serial

Reset
Download
Figure 8-25. Serial Downloader boot flow
8.8.1 USB
The USB support is composed of the USBOH3 (USB OTG1 core controller, compliant
with the USB 2.0 specification) and the USBPHY (HS USB transceiver).

The ROM supports the USB OTG port for boot purposes. The other USB ports on the
chip are not supported for boot purposes.
The USB Driver is implemented as a USB HID class. A collection of four HID reports
are used to implement the SDP protocol for data transfers, as described in Table 8-37.
Table 8-37. USB HID reports
Report ID (first byte) Transfer endpoint Direction Length Description
1 control OUT Host to device 17 B SDP command from the
host to the device.
2 control OUT Host to device Up to 1025 B Data associated with
the report 1 SDP
command.
3 interrupt Device to host 5B HAB security
configuration. The
device sends
0x12343412 in the
closed mode and
0x56787856 in the
open mode.
4 interrupt Device to host Up to 65 B Data in response to the
SDP command in report
1.
8.8.1.1 USB configuration details

The USB OTG function device driver supports a high speed (HS for UTMI) non-stream
mode with a maximal packet size of 512 B and a low-level USB OTG function.
The VID/PID and strings for the USB device driver are listed in the following table.
Table 8-38. VID/PID and strings for USB device driver
Descriptor Value
VID 0x15A2
(NXP vendor ID)
PID1 0x54
String Descriptor1 (manufacturer) NXP Semiconductors
String Descriptor2 (product) S Blank
ARIK
SE Blank
ARIK
NS Blank
ARIK

Serial Downloader
Table 8-38. VID/PID and strings for USB device driver (continued)
Descriptor Value
String Descriptor4 NXP Flash
String Descriptor5 NXP Flash
1. Allocation based on the BPN (Before Part Number)
8.8.1.2 IOMUX configuration for USB

The interface signals of the UTMI PHY are not configured in the IOMUX. The UTMI
PHY interface uses the dedicated contacts on the IC. See the chip data sheet for details.
8.8.2 Serial Download Protocol (SDP)

The 16-byte SDP command from the host to device is sent using the HID report 1.
This table describes the 16-byte SDP command data structure:
Table 8-39. 16-byte SDP command data structure
BYTE offset Size Name Description
0 2 COMMAND TYPE These commands are supported for the i.MX6 Dual/
6Quad ROM:
• 0x0101 READ_REGISTER
• 0x0202 WRITE_REGISTER
• 0x0404 WRITE_FILE
• 0x0505 ERROR_STATUS
• 0x0A0A DCD_WRITE
• 0x0B0B JUMP_ADDRESS
2 4 ADDRESS Only relevant for these commands:
READ_REGISTER, WRITE_REGISTER, WRITE_FILE,
DCD_WRITE, and JUMP_ADDRESS.
For the READ_REGISTER and WRITE_REGISTER
commands, this field is the address to a register. For the
WRITE_FILE and JUMP_ADDRESS commands, this
field is an address to the internal or external memory
address.
6 1 FORMAT Format of access, 0x8 for an 8-bit access, 0x10 for a 16-
bit access, and 0x20 for a 32-bit access. Only relevant
for the READ_REGISTER and WRITE_REGISTER
commands.

Table 8-39. 16-byte SDP command data structure (continued)

BYTE offset Size Name Description
7 4 DATA COUNT Size of the data to read or write. Only relevant for the
WRITE_FILE, READ_REGISTER, WRITE_REGISTER,
and DCD_WRITE commands. For the WRITE_FILE and
DCD_WRITE commands, the DATA COUNT is in the
byte units.
11 4 DATA The value to write. Only relevant for the
WRITE_REGISTER command.
15 1 RESERVED Reserved
8.8.2.1 SDP commands

The SDP commands are described in the following sections.
8.8.2.1.1 READ_REGISTER
The transaction for the READ_REGISTER command consists of these reports: Report1
for the command, Report3 for the security configuration, and Report4 for the response or
the register value.
The register to read is specified in the ADDRESS field of the SDP command. The first
device sends Report3 with the security configuration followed by the Report4 with the
bytes read at a given address. If the count is greater than 64, multiple reports with the
report id 4 are sent until the entire data requested by the host is sent. The STATUS is
either 0x12343412 for the closed parts and 0x56787856 for the open or field return parts.
Report1, Command, Host to Device:
1 Valid values for the READ_REGISTER COMMAND, ADDRESS, FORMAT, DATA_COUNT
ID 16-byte SDP command

Report3, Response, Device to Host:
3 Four bytes indicating the security configuration
ID 4 bytes status
Report4, Response, Device to Host: first response report
4 Register value

Serial Downloader
ID 4 bytes of data containing the register value. If the number of bytes requested is less
than 4, the remaining bytes must be ignored by the host.
Multiple reports of the report id 4 are sent until the entire requested data is sent.
Report4, Response, Device to Host: last response report
4 Register value
ID 64 bytes of data containing the register value. If the number of bytes requested is less
than 64, the remaining bytes must be ignored by the host.
8.8.2.1.2 WRITE_REGISTER
The transaction for the WRITE_REGISTER command consists of these reports: Report1
for the command, Report3 for the security configuration and Report4 for the write status.
The host sends Report1 with the WRITE_REGISTER command. The register to write is
specified in the ADDRESS field of the SDP command of Report1, with the FORMAT
field set to the data type (number of bits to write, either 8, 16, or 32) and the value to
write in the DATA field of the SDP command. The device writes the DATA to the
register address and returns the WRITE_COMPLETE code using Report4 and the
security configuration using Report3 to complete the transaction.
1 Valid values for WRITE_REGISTER COMMAND, ADDRESS, FORMAT, DATA_COUNT and DATA

3 4 bytes indicating the security configuration
ID 4 bytes status
4 WRITE_COMPLETE (0x128A8A12) status
ID 64 bytes data with the first 4 bytes to indicate that the write is completed with code
0x128A8A12. On failure, the device reports the HAB error status.

8.8.2.1.3 WRITE_FILE
The transaction for the WRITE_FILE command consists of these reports: Report1 for the
command phase, Report2 for the data phase, Report3 for the HAB mode, and Report4 to
indicate that the data are received in full.
The size of each Report2 is limited to 1024 bytes (limitation of the USB HID protocol).
Hence, multiple Report2 packets are sent by the host in the data phase until the entire
data is transferred to the device. When the entire data (DATA_COUNT bytes) is
received, the device sends Report3 with the HAB mode and Report4 with 0x88888888,
indicating that the file download completed.
Report1, Host to Device:
1 Valid values for WRITE_FILE COMMAND, ADDRESS, DATA_COUNT
========================Optional Begin=================
Host sends the ERROR_STATUS command to query if the HAB rejected the address
======================== Optional End==================
2 File data
ID Max 1024 bytes data per report

2 File data
ID Max 1024 bytes data per report
Report3, Device to Host:

3 4 bytes indicating security configuration
ID 4 bytes status

Serial Downloader
4 COMPLETE (0x88888888) status
ID 64 bytes data with the first four bytes to indicate that the file download completed
with code 0x88888888. On failure, the device reports the HAB error status.
8.8.2.1.4 ERROR_STATUS
The transaction for the SDP command ERROR_STATUS consists of three reports.
Report1 is used by the host to send the command; the device sends global error status in
four bytes of Report4 after returning the security configuration in Report3. When the
device receives the ERROR_STATUS command, it returns the global error status that is
updated for each command. This command is useful to find out whether the last
command resulted in a device error or succeeded.
1 ERROR_STATUS COMMAND
ID 16-byte SDP Command

ID 4 bytes status
4 Four bytes Error status
ID first 4 bytes status in 64 bytes Report4
8.8.2.1.5 DCD_WRITE
The SDP command DCD_WRITE is used by the host to send multiple register writes in
one shot. This command is provided to speed up the process of programming the register
writes (such as to configure an external RAM device).
The command goes with Report1 from the host with COMMAND TYPE set to
DCD_WRITE, ADDRESS which is used as a temporary location of the DCD data, and
DATA_COUNT to the number of bytes sent in the data out phase. In the data phase, the

host sends the data for a number of registers using Report2. The device completes the
transaction with Report3 indicating the security configuration and Report4 with the
WRITE_COMPLETE code 0x12828212.
1 DCD_WRITE COMMAND, ADDRESS, DATA_COUNT

Report2, Data, Host to Device:
2 DCD binary data
ID Max 1024 bytes per report

ID 4 bytes status
4 WRITE_COMPLETE (0x128A8A12) status
ID 64 bytes report with the first four bytes to indicate that the write completed with the
code 0x128A8A12. On failure, the device reports the HAB error status.
See Device Configuration Data (DCD) for the DCD format description.
8.8.2.1.6 JUMP_ADDRESS
The SDP command JUMP_ADDRESS is the last command that the host can send to the
device. After this command, the device jumps to the address specified in the ADDRESS
field of the SDP command and starts to execute.
This command usually follows after the WRITE_FILE command. The command is sent
by the host in the command-phase of the transaction using Report1. There is no data
phase for this command, but the device sends the status Report3 to complete the
transaction. If the authentication fails, it also sends Report4 with the HAB error status.

Recovery devices
1 JUMP_ADDRESS COMMAND, ADDRESS

ID 4 bytes status
This report is sent by the device only in case of an error jumping to the given address, or
if the device reports error in Report4, Response, Device to Host:
4 Four bytes HAB error status
ID 4 bytes status, 64 bytes report length
8.9 Recovery devices

The chip supports recovery devices. If the primary boot device fails, the boot ROM tries
to boot from the recovery device using one of the I2C or ECSPI ports.
To enable the recovery device, the BOOT_CFG4[6] fuse must be set. Additionally, the
serial EEPROM fuses must be set as described in Serial ROM through SPI and I2C.
8.10 USB low-power boot

The ROM supports the USB low-power boot. This feature enables a device with a dead
or weak battery to power up and boot if the device is connected to a USB upstream port,
no matter if the upstream port is a USB charger or a USB host/hub.
If a USB dedicated charger or a host/hub charger are connected, as soon as the device is
connected to the upstream port, a stable current (max.1.5 A) can be supplied by the
charger. If a USB host/hub is connected, a maximal current of 100 mA is supplied to the
device and the device is able to power up to boot the image with less than 100 mA.
If the LPB_BOOT fuses are blown, the chip checks if there is a low-power condition via
the GPIO_3 pad. If there is a low-power boot condition, the USB charger detection is
activated. If there is no USB charger, the ROM initializes the USB as a device and
applies division factors on the Arm, DDR, AXI, and AHB root clocks based on the

LPB_BOOT fuses value (see the table below). The polarity of the low-power boot
condition on the GPIO_3 pad is set by the BT _LPB_POLARITY fuse (see the following
figure).
Table 8-40. USB low-power boot frequencies
LPB_BOOT Boot Frequencies=0 Boot Frequencies=1
00 ARM_CLK_ROOT=792 MHz ARM_CLK_ROOT=396 MHz
MMDC_CH0_AXI_CLK_ROOT=528 MHz MMDC_CH0_AXI_CLK_ROOT=352 MHz
AXI_CLK_ROOT=264 MHz AHB_CLK_ROOT=132 AXI_CLK_ROOT=176 MHz AHB_CLK_ROOT=88
MHz MHz
MHz MHz
MHz MHz
MHz MHz

High-Assurance Boot (HAB)
Start
LPB_BOOT fuses equal Yes

00?
No
No
GPIO_3 pad equals
LPB_POLARITY fuse?
Yes
Start USB charger detection
USB Charger Yes

Connected?
No
Initialize USB OTG as device
Setup post dividers and root

Setup post dividers and root
clock selectors according to
clock selectors according to
Boot Freqiencies and
Boot Freqiencies fuse
LPB_BOOT fuses
Enable PLLs
End
Figure 8-26. USB low-power boot flow
8.11 High-Assurance Boot (HAB)

The High Assurance Boot (HAB) component of the ROM protects against the potential
threat of attackers modifying the areas of code or data in the programmable memory to
make it behave in an incorrect manner. The HAB also prevents the attempts to gain
access to features which must not be available.
The integration of the HAB feature with the ROM code ensures that the chip does not
enter an operational state if the existing hardware security blocks detected a condition
that may be a security threat or if the areas of memory deemed to be important were
modified. The HAB uses the RSA digital signatures to enforce these policies.

CAAM
Flash
ROM
HAB
Core Processor
SNVS
RAM
Figure 8-27. Secure boot components
The figure above illustrates the components used during a secure boot using HAB. The
HAB interfaces with the SNVS to make sure that the system security state is as expected.
The HAB also uses the CAAM hardware block to accelerate the SHA-256 message
digest operations performed during the signature verifications and AES-128 operations
for the encrypted boot operations. The HAB also includes a software implementation of
SHA-256 for cases where a hardware accelerator can't be used. The RSA key sizes
supported are 1024, 2048, and 3072 bits. The RSA signature verification operations are
performed by a software implementation contained in the HAB library. The main features
supported by the HAB are:
• X.509 public key certificate support
• CMS signature format support
• Proprietary encrypted boot support. Note that the encrypted boot depends on the
CAAM hardware module. When the CAAM is disabled (when the
EXPORT_CONTROL fuse is blown), the encrypted boot is not available.
NOTE
NXP provides the reference Code Signing Tool (CST) for key
generation, certificate generation, and code signing for use with
the HAB library. The CST can be found by searching for
"IMX_CST_TOOL" at http://www.nxp.com.
NOTE
For further details on using the secure boot feature using HAB,
refer to Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7
Series using HABv4 (AN4581).

High-Assurance Boot (HAB)
8.11.1 HAB API vector table addresses

For devices that perform a secure boot, the HAB library may be called by the boot stages
that execute after the ROM code.
The RVT table contains the pointers to the HAB API functions. The address of the RVT
table is shown in the following table.
Table 8-41. RVT table addresses
HAB API vector table address ROM API vector table address
Silicon revisions before 1.3 0x00000094 0x000000C0
Silicon revision 1.3 and later 0x00000098 0x000000C4
NOTE
For additional information on the secure boot including the
HAB API, refer to HABv4 RVT Guidelines and
Recommendations (AN12263).

Chapter 9
Multimedia
9.1 Video Graphics Sub System

The chip video graphics subsystem consists of the dedicated modules found here.
• Video Processing Unit (VPU): a multi-standard high performance video/image
CODEC
• Three Graphics Processing Units (GPUs):
• 3D GPU: accelerating the generation of 3D graphics (OpenGL/ES) and vector
graphics (OpenVG)
• 2D GPU: acceleration the generation of 2D graphics (BitBLT).
• OpenVG: acceleration of vector graphics (OpenVG).
• Two (identical) Image Processing Units (IPUs): providing connectivity to cameras
and displays, related processing, synchronization and control.
• Display interface bridges: providing optional translation from the digital display
interface supported by the IPU to other interfaces:
• LVDS bridge (LDB): providing up to two LVDS interfaces
• HDMI transmitter
• MIPI/DSI transmitter
• MIPI/CSI-2 receiver
• Two (identical) Display Content Integrity Checker (DCIC) are used to authenticate
sensitive displayed data.
• A Video Data Order Adapter (VDOA): used to re-order video data from the "tiled"
order used by the VPU to the conventional raster-scan order needed by the IPU.
High level integration scheme of the i.MX 6Dual/6Quad video/graphics system is
provided by the figure below.

Video Graphics Sub System
Data i.MX 6Dual/6Quad

Control
ARM
CPU
Memory Interface
Video Sources
GPUs
Bridges
IPUs
External
Memories
DCICs VDOA
Displays
VPU
IRAM
Figure 9-1. i.MX 6Dual/6Quad Video-Graphics Subsystem
9.1.1 Display outputs

The i.MX 6Dual/6Quad implements a robust muxing logic on the four display ports (2x
per IPU), to the external interfaces, either direct, or via bridges (MIPI, LVDS, HDMI),
per description below:
• Two parallel - driven directly by each of the IPUs; pixel clock at least up to 200 MHz
(for external load of up to 10 pF).
• Parallel interface works up to 200 MHz
• HDMI interface works up to 240 MHz (IPU)
• Two LVDS channels, driven by the LDB; pixel clock up to 170 MHz.
• One HDMI port (ver. 1.4) - driven by the HDMI transmitter: pixel clock up to 264
MHz (gated by the IPU capabilities)
• One MIPI/DSI port - driven by the MIPI/DSI transmitter; 2 data lanes at 1 GHz
• Each IPU display port (DI) can be connected to each of the above ports

Chapter 9 Multimedia
• Each IPU has 2 display ports, up to four external ports can be active at any given
time. (Additional asynchronous data flows can be sent though the parallel ports
and the MIPI/DSI port.)
• Read access is supported as follows
• For the Parallel0 port: through DI00
• For the Parallel1 port: through DI10
• For the MIPI/DSI port: through DI01 or DI11
• Inputs to either of the DCICs are taken from one of the following buses
• For each of the parallel interfaces: probing the I/O loopback (essentially
equivalent to probing the external wires).
• For other integrated interfaces (e.g. LVDS): probing the DI1 output of each of
the IPUs (essentially equivalent to the inputs to the serializers)
• For the data enable signal, two control signals are probed from each of the above
buses.
For visual view of display signal routing, see the following figure. The chip MUX select
signals are driven by configuration bits as specified in the IOMUX controller (IOMUXC)
chapter in the IOMUXC_IOMUXC_GPR registers description fields.
IPU #1 IPU #2
DI0 DI1 DI0 DI1
MIPI SoC MUX SoC MUX SoC MUX SoC MUX

IOMUX
DBI
MIPI
LVDS #0 LVDS #1 HDMI
DPI
PADS PADS
Parallel #0 Parallel #1
SoC MUX SoC MUX

GPR sticky control GPR sticky control
NOTE: Read path for smart

Displays is possible via:
1. Parallel0 pads
2. MIPI DBI
DCIC #1 DCIC #2
Figure 9-2. Display port muxing scheme

9.1.2 Video input

There are 3 video input ports (e.g. from image sensors).
See the figure below for details.
Video Input Ports Connectivity
Video Sources
i.MX 6Dual/6Quad
Parallel 0
mux
CSI0
IPU #1
CSI1
CSI2IPU
MIPI/CSI-2 MIPI/CSI-2 Bridge/
Receiver gasket
CSI0
IPU #2
mux
CSI1
Parallel 1
Figure 9-3. The Video Input Ports
Two parallel ports are connected directly to an IPU input port.

One MIPI/CSI-2 port- IPU receives two components per cycle from the MIPI_CSI2
interface. The maximum bandwidth of the interface is as follows:
• 400MByte/sec for four data lanes configuration (800Mbps/lane)
• 375MByte/sec for 3 data lanes configuration (1000Mbps/lane)
• 250MByte/sec for 2 data lanes configuration (1000Mbps/lane)
• 125Mbyte/sec for 1 data lanes configuration (1000Mbps/lane)
Each IPU has two input ports, CSI0 and CSI1, which can receive data concurrently and
independently. At any given time, an IPU input port may receive data either from a
parallel external port or from the MIPI/CSI-2 receiver.
The MIPI/CSI-2 port can receive up to 4 concurrent data channels. Each data channel is
routed to a different CSI input of the IPU (2 IPUs, 2 CSIs on each IPU; a total of 4 CSI
inputs). Pixel data can be further processed by the IPU. Other data types can be
transferred through a CSI transparently as generic data to the system memory.
The IPUs, VPU, VDOA and the GPUs have master AXI ports, providing access to
system memory.
The modules are controlled (by the ARM CPU or the SDMA) as follows:

• The LDB is controlled by signals connected to top-level registers.

• All other modules have a host interface. For the VPU, VDOA and the DCIC's, this is
a slave IP port and for the MIPI bridges, GPUs, HDMI and IPUs, this is a slave AHB
port.
• The data flow between VPU, VDOA, GPUs and IPUs is through system memory and
it is normally controlled by the CPU. For spacial situations, a direct synchronization
interface is provided:
• An interface between the IPUs and VPU, for low-latency video record.
• An interface between the VDOA and IPUs, for tight pipelining of data from the
VDOA to the IPU, through the IRAM.
9.1.3 Synchronization Mechanisms

The i.MX 6Dual/6Quad provides HW synchronization mechanism between IPU and
VPU and between IPU and VDOA to reduce core intervention and enable lock-step
operation.
9.1.3.1 Synchronization between the VDOA and the IPU

The VDOA can transfer its output to the IPU through internal memory, containing a band
double buffer.
This tight double-buffering synchronization is performed without CPU involvement,
using dedicated signals between the VDOA and IPU and the same protocol as used
between two IPU DMA channels.
This synchronization is supported for each of the IPUs, with muxing between the IPUs
performed at SoC level.
Within the IPU, this synchronization is supported only for asynchronous flows .
9.1.4 Supported applications

The system described above supports a wide variety of video/graphics applications. The
following table describes the main applications.
Table 9-1. Video/graphics applications
Application Features
Display management

Table 9-1. Video/graphics applications (continued)

Screen refresh Up to two displays active simultaneously
Pixel clock rate:
• Single display - up to 264 MHz
• Two displays (the sum of the two rates) - up to 240 MHz
NOTE: The parallel interface works up to 200 MHz, and the HDMI interface
works up to 240 MHz (IPU).
Special features:
• On-the-fly image conversion: rotation, inversion, resizing, color-space conversion and
combining
• On-the-fly image quality enhancement: color adjustment (including special effects) and gamut
mapping, gamma correction and contrast stretching
• Low-light compensation, allowing back-light reduction
• Scrolling/panning
Updating the display Buffer either in system memory or in an external display controller (accessed through the display
buffer (from a port)
background buffer)
Special features:
• On-the-fly processing - as for screen refresh
• Optimized update - only modified parts are transferred
• Synchronization with screen refresh, to prevent tearing
• Scrolling (e.g. a running banner or a short animation)
Video
Camera preview Input rate (from sensor): up to 240 MHz
(displaying a view-
Additional features:
finder window)
• Window-of-interest
• On-the-fly image conversion: de-interlacing, resizing, color space conversion, rotation,
inversion
• Combining with graphics
• Synchronization, to prevent tearing
Still image capture Rate:
• Burst mode (off-line processing): up to 180 Mpixels/sec (while still leaving headroom for up to
35% blanking overhead)
• Continuous: up to 160 Mpixels/sec
• Image quality enlacement before compression - as for camera preview
• Image conversion before compression - as for camera preview; with independent parameters
• Synchronization with a flash, a mechanical shutter and a mechanical iris
Motion Video Record Resolution and rate: up to 1080p (1920x1080 at 48 fps in unit test without multimedia framework)
Image processing before compression - as for still image capture
Motion Video Playback Resolution and rate - up to 1080i/p (1920x1080) at 60 fps in unit test (without multimedia framework)
• Post-filtering: de-blocking and de-ringing

Table 9-1. Video/graphics applications (continued)

• Image conversion after decompression: de-interlacing, rotation, inversion, resizing, color-
space conversion and combining
• Quality enhancement: color adjustment (including special effects) and gamut mapping,
gamma correction and contrast stretching
Two-Way Video Resolution and rate - up to 1080p (1920x1080) at 25 fps in unit test (without multimedia framework)
Record and playback features - as above
Various display options, including:
• Two non-overlapping windows
• Picture-in-picture
The following figure provides the sample processing flow of multimedia application.

Image Sensor Display
Camera Display
Image Enhancement
Image Signal Processing
Processing
Unit (IPU) Video/Graphics
Combining
Camera Preview
Image Image Graphics
Conversions Conversions Generation
De-blocking
Graphics
Video De-ringing
Compression Processing
Processing
Units (GPUs)
Unit (VPU) De-compression
And ARM
Memory
Combining Separation
with Audio from Audio
Communication
Network
Audio Compression
ARM Audio De-compression
Figure 9-4. Processing flow for multimedia applications
• The camera preview mode-the upper part

• Video recording-the left part
• Video playback-the right part
• A video call-both sides

9.2 Image Processing Unit (IPU)

The following table shows the IPU IP parametric table.
Table 9-2. IPU IP Parametric Table
Name IPU
Function Connectivity to cameras and displays; related processing; synchronization and
control
External I/O Pins Parallel Display port:
Notes: 32 bit data, ~18 clocks and controls.
This is the pinout of the IPU module Regular CMOS IO type, 264 MHz max.
At chip level, some of the pins are muxed May be also connected to internal connectivity bridges.
and some are omitted.
Slow Serial Display port:
Additional GPIO pins are required to
2 bit data, 3 clocks and controls.
construct the connection. This is not
included in this list. Regular CMOS IO type, 120 MHz max.
Parallel Sensor port:
20 bit data inputs, 5-6 clocks and controls.
Regular CMOS IO type, 240 MHz max.
Camera strobe port:
6 camera control outputs.
Regular CMOS IO type, 120 MHz max.
SoC Buses AXI master - for accessing the memory
AHB slave - for programming, control and direct access of the MCU to the
display
Interrupts Two interrupts: functional and error
DMA Requests Includes an integral DMA controller with an AXI master port
Also one DMA request to the SDMA
Number of instantiations 2
Clock sources and range HSP_CLK - Internal high-speed processing clock: up to 264 MHz
DI_CLK0, DI_CLK1 - Display interface clocks: up to 240 MHz
The goal of the IPU is to provide comprehensive support for the flow of data from an
image sensor and/or to a display device. This support covers all aspects of these
activities:
• Connectivity to relevant devices - cameras, displays, graphics coprocessors, TV
encoders and decoders.

• Related image processing and manipulation: image enhancements and conversions,

etc.
• Synchronization and control capabilities (to avoid tearing artifacts, for example)
This integrative approach leads to several significant advantages:
• Automation: The involvement of the MCU (Main Control Unit) in image
management is minimized. In particular, display refresh/update and a camera
preview (displaying the input from an image sensor) can be performed completely
autonomously. The resulting benefits are reducing the overhead due to SW-HW
synchronization, freeing the MCU to perform other tasks and reduced power
consumption (when the MCU is idle and can be powered down).
• Optimal data path: Access to system memory is minimized. In particular, significant
processing can be performed on-the-fly while receiving data from an image sensor
and/or sending data to a display. System memory is used essentially only when a
change in pixel order or frame rate is needed. The resulting benefits are reduced load
on the system bus and further reduction of power consumption.
• Resource sharing: Maximal HW reuse for different applications, resulting with the
support of a wide range of requirements with minimal hardware
The hardware reuse mentioned above is enabled by a sophisticated configurability of
each hardware block. This configurability also allows the support of a wide range of
external devices, data formats and operation modes.
A simplified block diagram of the IPU is given in the figure below. The role of each
block is described in the table below.

CSI SMFC
(Camera Sensor I/F) (Sensor Multi FIFO Ctrl.)
VDIC
(Video De-Interlacer
IPUv3H & Combiner)
Cameras
DI
(Display I/F) IC IDMAC 64-bit
Image Converter Memory
(Image DMA Controller) AXI
DP
(Display Processor)
DC DMFC
(Display Contr.) (Display Multi FIFO Ctrl.)
Display
CM IRT
(Control Module) (Image Rotator)
32-bit AHB
MCU
Figure 9-5. IPU - Block Diagram
Table 9-3. IPU - Block Description

Block Description
CSI - Camera Sensor Interface Controls a camera port; provides interface to an image sensor or a related device.
IPUv3 includes 2 such blocks
DI - Display Interface Provides interface to displays, display controllers and related devices.
IPUv3 includes 2 such blocks
DC - Display Controller Controls the display ports.
VDIC - Video De-Interlacer and Performs de-interlacing - converting interlaced video to progressive - or combining
Combiner
IC - Image Converter Performs resizing, color conversion/correction, combining with graphics, and
horizontal inversion
DP - Display Processor Performs the processing required for data sent to display
IRT - Image Rotator Performs rotation (90 or 180 degrees) and inversion (vertical/horizontal)
IDMAC - Image DMA Controller Controls the memory port; transfers data to/from system memory
SMFC - Sensor Multi FIFO Controller Controls FIFO's for output from the CSI's to system memory
DMFC - Display Multi FIFO Controller Controls FIFO's for IDMAC channels related to the display system
CM - Control Module Provides control and synchronization.

9.2.1 IPU External Ports

The IPU has the following ports:
• Two camera ports - controlled by a CSI module - providing a connection to image
sensors and related devices.
• Two display ports - each controlled by a DI module - providing a connection to
displays and related devices.
• Memory port - AXI (AHB V3.0) master, controlled by the IDMAC - providing
connection to the system memory.
• AHB-lite slave port, providing connection to the ARM MCU (and to any other
master connected to the ARM's cross-bar switch)
9.2.1.1 Camera Ports

The role of these ports is to receive input from video sources (e.g. image sensors) and to
provide support for time-sensitive control signals to the camera. (Non-time-sensitive
controls - e.g. configuration, reset - are performed by the MCU, through an I2C I/F or
GPIO signals).
Each of the camera ports includes the following features:
• Direct connectivity to most relevant external devices.
• Parallel interface - up to 20-bit data bus
• Frame size: up to 8192 x 4096 pixels (including blanking intervals)
• Data formats supported include Raw (Bayer), RGB, YUV 4:4:4, YUV 4:2:2 and
grayscale, up to 16 bits per value (component).
• Synchronization - video mode
• The sensor is the master of the pixel clock (PIXCLK) and synchronization
signals
• Synchronization signals are received using either of the following methods:
• Dedicated control signals -VSYNC, HSYNC - with programmable pulse
width and polarity
• Controls embedded in the data stream, following loosely the BT.656
protocol, with flexibility in code values and location.
• Synchronization - still image capture
• The image capture is triggered by the MCU or by an external signal (e.g. a
mechanical shutter)
• Synchronized strobes are generated for up to 6 outputs - the sensor and camera
peripherals (flash, mechanical shutter...)
• Additional features
• Frame rate reduction, by periodic skipping of frames

• Downsizing x2, by skipping rows/columns

• Window-of-interest selection
• Pre-flash - for red-eye reduction and for measurements (e.g. focus) in low-light
conditions
Several sensors can be connected to each of the CSI's. Simultaneous functionality
(sending data) is supported as follows:
• Two streams can be received independently, each through a different CSI.
• A CSI can receive several interleaved streams (up to 4; e.g. as supported by the
MIPI/CSI-2 I/F), The CSI can de-interleave the streams according to an ID signal
received with the input.
• Unpacking capabilities are provided for a single stream in each CSI, while the other
ones are treated as generic data.
• Only one of the streams can be transferred to the VDIC or IC for on-the-fly
processing, while the other ones are sent directly to system memory.
The input rate supported by the camera port is as follows:
• Peak: up to 240 MHz (values/sec)
• Average (assuming 35% blanking overhead), for YUV 4:2:2
• Pixel in one cycle (e.g. BT.1120): up to 180 MP/sec, e.g. 12M pixels @ 15 fps
• Pixel on two cycles (e.g. BT.656): up to 90 MP/sec, e.g. 6M pixels @ 15 fps.
• On-the-fly processing may be restricted to a lower input rate - see below.
9.2.1.2 Display Ports

The role of these ports is to communicate with display devices, either directly or through
a controller (e.g. graphics accelerator) or a bridge (e.g. TV encoder or an LVDS interface
bridge).
9.2.1.2.1 Access Modes

Two access modes are supported:
• Synchronous Access
• Asynchronous Access
9.2.1.2.2 Synchronous Access

In this mode, the IPU transfers a two-dimensional block of pixels to the display device, in
synchronization with the screen refresh cycle.

This mode has a dual role:

• For a RAM-less display or a TV screen, this mode is used to perform the screen
refresh process from a display buffer in system memory.
• For a "smart" display, this mode is used to transfer a rectangular block of pixels to
the display's screen and, in some cases, also to the display buffer
In both cases, the IPU sends to the display all the synchronization signals controlling the
screen refresh and the block transfer is synchronized with these signals. This
synchronization means that tearing effects are avoided when using this mode.
9.2.1.2.3 Asynchronous Access

This is the main mode used for communicating with an external display controller
(possibly in a smart display or a graphics accelerator). In this mode, the IPU performs
random access - read/write - to the memory and registers of the controller.
The following access types are provided:
• Data transfer to the external device, after on-the-fly processing in the IPU.
• Data transfer (DMA) - read/write - between the host's system memory and the
external device, through the IPU's memory port (controlled by the IDMAC); e.g.
transfer of a rectangular block of pixels (possibly full screen).
• Host access - read/write - to an external device, through the AHB-slave port
9.2.1.2.4 Interface details

The display interface is very flexible and supports a wide variety of devices from major
manufacturers.
The following interface types are provided (in each of the two display ports):
• A parallel video interface (for synchronous access) - up to 24-bit data bus.
• Supports BT.656 (8-bit) and BT.1120 (16-bit) protocols
• Supports HDTV standards SMPTE274 (1080i/p) and SMPTE296 (720p)
• A parallel bidirectional bus interface (for asynchronous access) - up to 32-bit data
bus.
• A serial interface - 3-wire, 4-wire and 5-wire (two flavors) (for asynchronous access)
The supported formats for pixel data are: RGB and YUV 4:2:2.
For the interface clock, there are the following options (independently for each port)
• Derived from the IPU internal clock (master mode)
• Provided by an external source (slave mode)

The transfer rate supported

• When a single port is active, the pixel clock rate is up to 264 MHz
• When both ports are active
• Each pixel clock rate may be up to 220 MHz1
• The sum of pixel clock rates is up to 240 MHz
9.2.1.2.5 Connecting To Display Devices

IPU allows the connectivity to multiple display devices.
In particular, it supports the following setup:
• Primary LCD display.
• Second LCD display.
• External display; e.g. TV.
Simultaneous functionality of the above devices is possible in each of the following
ways:
• Two devices can be accessed (synchronously or asynchronously) independently, each
through a different port: each using any of the available interfaces.
• Two devices can time-share asynchronous accesses through the legacy serial and
parallel interfaces, using the CS signals.
9.2.2 Processing
The IPU processes rectangular blocks of pixels. The processing is performed in four
modules - VDIC, IC, DP and IRT.
(see Figure 9-5 and Table 9-3). Several time-shared data flows are supported, as
described in the following table.
Table 9-4. Time-Shared Data Flows Through The IPU
Name Number Type Flow Target Restrictions
Display Refresh/ 5 flows (at DS1 Fmem -> DP -> Display Synchronous Access (e.g. —
Update most two of display refresh;
them of type
controlled by the DI)
DS1)
DS2 Fmem -> DP -> Display Asynchronous Access —
(e.g. display update)
DS3 Fmem <-> Display Generic Data Transfer —
1. Specified pixel clocks frequencies are applicable for internal clocks, but may be limited by IO buffers speed
capability. Final numbers are subjected to AC characterization.

Table 9-4. Time-Shared Data Flows Through The IPU (continued)

Name Number Type Flow Target Restrictions
1 flow DS4 MCU <-> Display Direct Access —
Video Playback 1 flow PL1 Bmem -> VDIC -> IC -> Main option —
Bmem -> IRT -> Fmem
+ DSx
PL2 Fmem -> IRT -> Bmem -> Low power Progressive source
IC -> DP
(branching to DSx, as a Large enough window
video plane)
No other video flows
PL3 Fmem -> VDIC -> IC -> Low power Interlaced source
DP
(branching to DSx, as a Large enough window
video plane)
Camera Preview 2 flows VF1 Sensor -> IC -> Bmem -> main option Single progressive input
IRT -> Fmem
(VF2 may be
used also as + DSx
a playback VF2 Sensor -> Fmem -> VDIC two inputs and/or When the VDIC is used
flow) -> IC -> Bmem -> IRT -> interlaced input for de-interlacing, one of
Fmem the three input fields can
go directly from the sensor
+ DSx
to the VDIC
VF4 Sensor -> IC -> Fmem Low power Single progressive input
+ DS1 RAM-less Display Refresh rate = 2x sensor
frame rate
Single Display Buffer
Large enough window
(in internal memory)
Tearing-less
Video Record 2 flows RCx IC -> Bmem -> IRT -> (branching from VFx)
Fmem
Graphic Overlays 2 flows GF1 Fmem -> IC (combining with the main
flow
2 flows GF2 Fmem -> DP
9.2.2.1 Display Processor (DP)

The Display Processor performs all the processing required for data sent to a display.
• Combining 2 video/graphics planes
• Overlaying a simple HW cursor 32 x 32 pixels, uniform color; may be combined
logically with the background.
• Color conversion/correction - linear (multiplicative and additive) Programmable;
including:
• YUV <-> RGB, YUV<->YUV conversions where YUV stands for any one of
the color formats defined in the MPEG-4 standard

• Adjustments: brightness, contrast, color saturation...

• Special effects: gray-scale, color inversion, sephia, blue-tone...
• Hue-preserving gamut mapping - for minimal color distortion
• Applied to the output of combining or to one of the inputs
• Gamma correction and contrast stretching - programmable piecewise-linear map
The DP processes a single data flow at any given time, but it supports up to three data
flows, by time sharing, one of them may be synchronous.
The data rate is up to 264M pixels/sec
9.2.2.2 Video de-interlacer (VDIC)

VDIC, the video de-interlacer and combiner module, has two operation modes
• De-interlacing: converts an interlaced video stream to progressive order.
• Combining: combines two video/graphics planes and a background color
The input and output to/from the VDIC is as follows:
• Input for de-interlacing: three consecutive fields
• Source
• The most recent field may come from the CSI or from system memory
• The other two fields are read from memory
• Field size: Supports up to 1080p
• Pixel format: YUV 4:2:2/4:2:0, 8 bits/value
• Typical video sources - SDTV: 480i30 (720x480 at 30 fps) or 576i25 (720x576
at 25 fps) and HDTV: 1080i30 (1920x1080 at 30 fps)
• Input for combining: two progressive video/graphics planes
• Source: system memory
• Plane size: up to 1920x1200 pixels.
• Pixel format: RGB/YUV 4:2:2, 8 bits/value
• Output: progressive frame
• Destination: to system memory or to the Image Converter.
• Frame size: up to 1920x1200 pixels.
• Rate: up to 240M pixels/sec.
• Format: same as input format.
De-interlacing is performed using a high-quality 3-field filter, which is motion adaptive:
• For slow motion - retains the full resolution (of both top and bottom fields)
• For fast motion - prevents motion artifacts
VDIC supports a single video stream at any given time.

9.2.2.3 Image Converter (IC)

The Image Converter performs various operations on a video stream.
The operations performed are:
• Resizing:
• Fully flexible resizing ratio Maximal downsizing ratio: 8:1. Subject to this
limitation, any N->M resizing can be performed
• Independent horizontal and vertical resizing ratios.
• Color conversion/correction - linear (multiplicative and additive) Programmable;
including:
• YUV <-> RGB, YUV<->YUV conversions where YUV stands for any one of
the color formats defined in the MPEG-4 standard
• Adjustments: brightness, contrast, color saturation...
• Special effects: gray-scale, color inversion, sephia, blue-tone
• Combining with a graphics plane (e.g. application-specific overlay)
• Horizontal inversion
The IC supports three time-shared data flows: record, camera preview and playback (the
first two share a common input).
The frame resolution supported is up to 4096x4096 for input and up to 1024x1024 for
output. Wider frames can be processed by the IC by splitting them to vertical stripes.
Data throughput:
• For a single active task: up to 240M pixels/sec for input and up to 120M pixels/sec
for output.
• For several active tasks: up to 200M pixels/sec for input and up to 100M pixels/sec
for output.
9.2.2.4 Image Rotator (IRT)

The Image Rotator performs any combination of the following:
• 90-degree rotation
• Horizontal inversion
• Vertical inversion
The data throughput

• When a single task is active: up to 120M pixels/sec.

• When more tasks are active: up to 100M pixels/sec.
9.2.3 Automatic Procedures

The IPU is equipped with powerful control and synchronization capabilities to perform
its tasks with minimal involvement of ARM and minimal use of memory.
In particular, it includes:
• An integrated DMA controller with an AXI master port, allowing autonomous access
to the system memory.
• An integrated display controller, performing screen refresh of a RAM-less display.
• A page-flip double buffering mechanism, synchronizing read and write access to
system memory, to prevent tearing effects.
• A double/triple buffer synchronization mechanism with a video/graphics source.
• Internal synchronization, e.g., between input from sensor and output to display.
As a result, in most cases, the MCU is involved only when it also performs part of the
processing (e.g. video coding). In particular, the following procedures are performed by
the IPU completely autonomously:
• Screen refresh for RAM-less displays
• Camera preview (displaying a view finder - a video-stream from the image sensor to
the display).
NOTE
Direct camera to display flow is possible when the frame
rate of the source and the destination is the same (typically
the target display will be asynchronous display, where the
display is updated at the rate of the source).
Typically, there are extended periods of time in which there is no other activity in the
system. The MCU - being idle - can be put to a low-power mode, reducing the power
consumption and extending significantly the battery life.
The IPU supports several techniques to reduce further the power consumption of the
display system:
• Dynamic backlight control, with low-light compensation by image enhancement
Further features and capabilities of the automatic procedures include:
• Automatic display of a changing image (animation) or moving image (scrolling).

LVDS Display Bridge (LDB)
• The timing of the display update can be adjusted to avoid tearing.

• The video stream from an image sensor can be sent directly to the display buffer used
for screen refresh, while avoiding tearing.
The clock sources received by the IPU are listed in the following table.
Table 9-5. IPU Clock Sources
Name Symbol Source Rate Comments
High-Speed HSP_CLK Clock control Module Up to 264 MHz
Processing Clock
Display Interface DI_CLK0 Clock control Module Up to 220 MHz Optional; needed for synchronization with
Clocks or an external PLL interface bridges
DI_CLK1
9.2.4 Further Changes in IPUv3H vs. IPUv3M

• The sizes of the input/output FIFOs in the DMFC, SMFC and VDIC have been
increased, to support an increased data rate
• The memory address space has been reduced to 32 MB. Direct access to an external
display device is canceled, but low-level access is retained.
• Synchronization with the VDOA has been added - see Synchronization between the
VDOA and the IPU
9.3 LVDS Display Bridge (LDB)

LVDS Display Bridge (LDB) will be used to connect the IPU (Image Processing Unit) to
the External LVDS Display Interface.
9.3.1 LDB Overview

Table 9-6. IP Parametric Table
Name Description
Function Connectivity to displays with LVDS interface
External I/O Pins LVDS Display port:
Notes: 2 channels. Each channel consists of:
Those are LVDS IO pads • 1 clock pair
• 4 data pairs
Each pair contains - LVDS special differential pad (PadP, PadM).


Table 9-6. IP Parametric Table (continued)

Name Description
total of 20 IO pads.
SoC Buses None. Only configuration signals.
Interrupts None
DMA Requests None
Clock sources and range DI0_CLK, DI1_CLK - Display interface clock: 20-170 MHz
DI0_SER_CLK, DI1_SER_CLK - Serializer clock: 140-595 MHz
The purpose of the LDB is to support flow of synchronous RGB data from the IPU to
external display devices through the LVDS interface. This support covers all aspects of
these activities:
• Connectivity to relevant devices - Displays with LVDS receivers.
• Arranging the data as required by the external display receiver and by LVDS display
standards.
• Synchronization and control capabilities.
9.3.2 LDB External Ports

The LDB has the following ports:
• Two input parallel display ports.
• Two Output LVDS channels - Each channel consisting of 4 data pair, and 1 clock
pair (pair=LVDS pad contains PadP, PadM).
• Control signals - to configure LDB parameters and operations.
• Clocks from SOC PLLs.
9.3.3 Input Parallel Display Ports

One or Two (DI0, DI1) parallel RGB input ports are supported (configurable). Only
synchronous access mode is supported.
Each RGB data interface contains the following:
• RGB Data of 18 or 24 bits
• Pixel clock
• Control signals: HSYNC, VSYNC, DE, and 1 additional optional general purpose
control.

Video Data Order Adapter (VDOA)
Total of up to 28 bits per data interface are transferred per pixel clock cycle.
Rates supported:
• For dual-channel output: Up to 170 MHz pixel clock (e.g. UXGA - 1600x1200 @ 60
Hz + 35% blanking)
• For single-channel output: Up to 85 MHz per interface. (e.g. WXGA - 1366x768 @
60 Hz + 35% blanking).
9.3.3.1 Output LVDS Ports

There are 2 LVDS channels. These inputs are used to communicate RGB data and
controls to external LCD displays with LVDS interface, or through LVDS receivers.
The LVDS ports may be used as follows:
• One single-channel output
• One dual channel output: single input, split to two output channels
• Two identical outputs: single input sent to both output channels
• Two independent outputs: two inputs sent, each, to a different output channel
9.4 Video Data Order Adapter (VDOA)

The goal of the VDOA is to re-order video data from the "tiled" order used by the VPU to
the conventional raster-scan order needed by the IPU.
9.4.1 VDOA Interfaces

The VDOA has the following interfaces
• Memory interface: 64-bit AXI master port (no AXI ID output)
• Host interface: IP slave port
• Synchronization with IPU (see below)
9.4.2 VDOA Data Path
9.4.2.1 Input
• Source: a frame buffer in system memory

• Addressing: tile-based
• Order: raster-scan of tiles
• Maximal bursts (up to 64 bytes)
9.4.2.2 Output
• Destination: a frame buffer or band buffer in system memory (band = row of tiles; to
be used when the buffering is in internal memory)
• Addressing: raster-scan of rows
• Order: full bursts of 64 bytes (requires data from several tiles)
Input/output - additional aspects
• Pixel format: YUV 4:2:0 partially-interleaved
• Pixel format: YUV 4:2:2 interleaved
• Total rate: at least up to 220 MP/sec (e.g. 1080i @ 60 fps + 480i @ 60 fps, three
fields per frame)
• Frame width: even; up to 4096 pixels
• Frame height: even; up to 2048 pixels
• Addresses [bytes]
• Base address: 32-bit integer, multiple of 8
• Offset from the Y buffer to the UV buffer: 23-bit integer, multiple of 8
• Line stride (same for both buffers): 12-bit integer, multiple of 8
9.4.3 Control
Each VDOA task is activated individually by the CPU and consists of
• Reordering a single buffer of pixels;
or
• Reordering concurrently three buffers or pixels (needed for the 3 input fields used for
de-interlacing in the IPU).
When reordering concurrently three buffers
• The buffers differ only in their base addresses.
• The switching between them is performed at the end of a band (= row of tiles), in a
fixed order: buffer 0 band 0 -> buffer 1 band 0 -> buffer 2 band 0 -> buffer 0 band
1...
Multi-tasking

• All task parameters are double buffered, to allow SW-controlled frame-by-frame

task-switching without re-configuration overhead.
Synchronization with IPU - see Synchronization between the VDOA and the IPU
End-of-task interrupt
• The VDOA can issue a functional interrupt after completing the task.
• The interrupt is triggered by the acknowledgement received on the AXI bus for the
last write access.
• For this to indicate that the data indeed reached its destination, this last write access
is non-bufferable.
9.5 Display Content Integrity Checker (DCIC)

The goal of the DCIC is to verify that a safety-critical information sent to a display is not
corrupted.
Such a verification is mandatory for warning icons in the instrument cluster of a car, to
comply with the ASIL B (Automotive Safety Integrity Level B) specification. It is also
required in other safety-sensitive systems.
9.5.1 DCIC Interfaces

The DCIC has the following interfaces
• Data input port - snooping one of the display ports
• Host interface: IP slave port
9.5.2 DCIC Data Path

See Figure 9-2 for DCIC integration in i.MX 6Dual/6Quad SoC.
Input - snooped display bus
• Pixel clock signal; up to 264 MHz
• Data enable signal: marking a cycle with valid data (pixel)
• Data: 24-bit bus, assumed to contain a single full pixel
• Vsync & Hsync signals: indicating frame & row boundaries respectively
• Mask signal (see below)
Actions
• Identify pixels belonging to a ROI (Region Of Interest)

• Up to 16 ROIs are supported
• Each is confined to a rectangle, with a configurable location and size
• A refined shape of the ROI is characterized through the mask input signal, when
enabled
• Overlap between the regions is not allowed (each pixel contributes to at most
one region)
• Calculate an integrity signature - CRC32 - independently for each ROI
• Compare the calculated signature to the reference signature - provided by the host
CPU
• This check is triggered by the Vsync signal
Results
• Registered values - accessible by the CPU through the host interface
• Calculated signatures - one for each ROI - from the last frame (the intermediate
values from the current frame are stored separately)
• Match status bits - one for each ROI - from the last frame
• Interrupts - to the host CPU (maskable)
• Match results ready (functional)
• Mismatch (error)
• Both interrupts are generated immediately after completing the signature match
check
• Signal to an external CPU (through a GPIO pin)
• Continuously oscillating at a rate which is an integer division of the input clock
• When the status bit of the mismatch interrupt is set - i.e. from mismatch
detection until the CPU clears the bit: division x16
• Otherwise: division x4
9.5.3 Configuration parameters

• For each of the 16 ROIs
• Enable bit; double-buffered; changes take effect at frame boundaries.
• Rectangle offset [pixels] = location of the upper-left pixel
• Horizontal: 0 .. 2^13-1
• Vertical: 0 .. 2^12-1
• Rectangle size [pixels]
• Horizontal: 1 .. 2^13
• Vertical: 1.. 2^12
• A 32-bit "reference signature" - to be compared with the calculated signature
• Freeze bit

Video Processing Unit (VPUv6)
• "Sticky" control bit: zero at reset; can be set but cannot be reset
• Once set (typically at boot), the only parameters from the above list that are
allowed to be changed are the reference signatures
• Mask input settings: enable, polarity
• Interrupt settings
• A mask bit for each of the two interrupts
• Freeze bit: the masks can be changed only before the freeze bit is set.
9.5.4 System Considerations

• The DCIC always assumes a 24-bit pixel.
• For proper functionality with lower color depth, one must ensure that:
• When the CPU calculates the reference signature, it applies the same mapping of
a pixel to a 24-bit field as that performed by the IPU.
• The display is connected to the appropriate pins.
• The simplest mapping would be
• Map the pixel to the data bus in the same way as for 24 bpp
• Set the values at the extra LSBs to zero.
• Parameter updates
• The reference signature can be freely updated from frame to frame, in
coordination with the changing content (since it is used only once per frame, just
before the interrupt)
• Each ROI can be freely and independently enabled/disabled between frames
(since the enable bit is double buffered)
• The size and location of a ROI can be modified while it is disabled.
9.6 Video Processing Unit (VPUv6)

The VPU is a multi-standard video codec (encoder/decoder) capable of handling multiple
streams simultaneously by time multiplexing.
It is a very flexible block consisting of hardware accelerators surrounding a
programmable core. The VPU presents to the system a register mapped interface that is
controlled by the embedded processor. End users should only interface with the VPU
using the API that is provided with each BSP Programmers User Guide. This API isolates
the user from possible changes in the register level interface.

In the following table we can see a summary of the VPU specs. The VPU has its own
DMA driven AXI masters that allow it to retrieve the required data directly from system
memory (DDR and iRAM). The load in the host ARM platform is negligible because it
only needs to interact with the VPU at the frame level.
Table 9-7. VPU Spec Summary
Name VPU
Function Decode video streams including optional video processing such as rotation,
deringing and mirroring.
Supported encoders MPEG-4 SP
H.263 V2 + Annex J, K (RS=0 and ASO=0), and T
H.264 BP, CBP
MJPEG Baseline
Supported decoders MPEG-2 MP, HP
VC-1 SP, MP, AP
MPEG-4 SP, ASP
H.263 V2 + Annex J, K (RS=0 and ASO=0), and T
H.264 BP, MP, HP
H.264-MVC BP, MP, HP
DivX v3,4,5
Real Video 8, 9, 10
MJPEG Baseline
On2 VP8
AVS Jizhun
External I/O Pins (List, Type, Schmidt No external I/O pins are needed
Trigger, Speed)
SoC Buses (List, Type, Bandwidth) 64 bit AXI master for accessing the system memory and the optional secondary
AXI but to iRAM
IPBus slave for host control
Interrupts Two interrupts
DMA Requests Integrated DMA controller on the AXI master port
Endianness 64 and 32 bit BE/LE
Clock sources and range Core clock: up to 264 MHz
AXI bus clock: up to 264 MHz
IP bus clock: up to 66 MHz
NOTE
RealNetworks video codec is disabled by default on i.MX 6
series processors. Please contact your FSL sales representative
for more details.

Video Processing Unit (VPUv6)
The i.MX 6Dual/6Quad processor has a high-performance video processing unit (VPU),
which covers many standard and high definition video decoders and encoders as a multi-
standard video codec engine as well as several important video processing such as
rotation and mirroring.
9.6.1 Basic Structure

The following Figure 9-6 shows the basic structure of the VPU. The VPU is self
contained except for memory accesses. It is connected to the memory subsystem through
two AXI master ports. The ARM configures the VPU operation through the IP bus that is
converted to APB in a gasket.
A new feature is added for allowing VPU encoding a frame even the IPU writes only a
small portion of source video (from camera sensor) into the frame buffer. This feature is
called IPU-VPU sub-frame synchronization. Four additional signals are added for
implementing this feature with three of them from IPU to VPU, and one of them from
VPU to IPU, as shown in Figure 9-6 for the signal category of "IPU VPU sub-frame
sync"

Core relative CRESETn IREQ

signals CCLK
EXT_ARESETn
AXI relative ARESETn BUSY
signals
ACLK
APB relative PRESETn AXI write address

signals
PCLK channel
TESTMODE
AXI write-data AXI write
channel channel
AXI write response

APB signal
channel
AXI read address

channel
AXI read
channel
ipu_end_of_row AXI read data

IPU VPU channel
sub-frame ipu_new_frame
sync
ipu_current_buffer[2:0]
Figure 9-6. The Block Diagram of the VPU
9.6.2 Feature summary

The following table describes the VPU's encoding / decoding capabilities:
Table 9-8. VPU decoding/encoding capabilities
Dec/Enc Standard Profile Resolution Bitrate Comments
HW Decoder MPEG-2 Main-High 1080 i/p, 30fps 50 Mbps 1080p+SD at 30fps, 720p60
MPEG4/XviD SP/ASP 1080 i/p, 30fps 40 Mbps —
H.263 P0/P3 16CIF, 30 fps 20 Mbps —
H.264 BP/CBP/MP/HP 1080 i/p, 30 fps 50 Mbps 1080p+SD at 30 fps,
720p60
H.264-MVC BP/MP/HP 720p, 30 fps — —

OpenGL ES 3D Graphics Processing Unit (GPU3Dv4)
Table 9-8. VPU decoding/encoding capabilities (continued)

Dec/Enc Standard Profile Resolution Bitrate Comments
VC1 SP/MP/AP 1080 i/p, 30 fps 45 Mbps 1080p+SD at 30 fps,
720p60
RV 8/9/10 1080 p, 30 fps 40 Mbps —
DivX 3/4/5/6 1080 i/p, 30 fps 40 Mbps —
On2 VP8 — 720p, 30 fps 20 Mbps —
AVS Jizhun 1080 i/p, 30fp 40 Mbps — —
MJPEG Baseline 8192x8192 120 Mpixel/sec Perf shown at —
4:4:4 format
Hardware MPEG4 Simple 720p, 30 fps 12 Mbps VPU can generate higher
encoder bitrate than the maximum
H.263 P0/P3 4CIF, 30 fps 8 Mbps
specified by the
H.264 BP/CBP 1080p, 30 fps 14 Mbps corresponding standard.
MJPEG Baseline 8192 x 8192 160 Mpixel/sec Perf shown at 4:2:2 format
VPU can also perform the following:

• On-the-fly (90 x n) degree simultaneous rotation and mirroring (n = 0,1,2,3).
• Post-processing
• De-blocking filtering for MPEG-4
• De-ringing filtering for MPEG-4 and H.264 decoder
9.7 OpenGL ES 3D Graphics Processing Unit (GPU3Dv4)
9.7.1 OpenGL Overview
9.7.2 OpenGL Features

Summary of features in the GPU3D includes:
• OpenGL ES 2.0 compliance, including extensions; OpenGL ES 1.1; OpenVG 1.1
• IEEE 32-bit floating-point pipeline
• Ultra-threaded, unified vertex and fragment shaders
• Low bandwidth at both high and low data rates
• Low CPU loading
• Up to 12 programmable elements per vertex

• Dependent texture operation with high-performance

• Alpha blending
• Depth and stencil compare
• Support for 8 fragment shader simultaneous textures
• Support for 4 vertex shader simultaneous textures
• Point sampling, bi-linear sampling, tri-linear filtering, and cubic textures
• Resolve and fast clear
• 8k x 8k texture size and 8k x 8k rendering target
9.7.3 OpenGL Block Diagram
GPU Debug Bus

IOMUX
64b AXI Master

AHB-32 Memory Access
32b AHB Slave GPU3D AXI
X-bar
Command Bus Graphics Core ARB.
Switch 64b AXI Master
Figure 9-7. GPU System Integration Diagram
9.7.4 OpenGL Performance

• Geometry Rate: 88M Triangles/sec
• Pixel Rate: 1.066G pixels/sec
9.7.5 OpenGL Software

API / Driver Support
• OpenGL ES 1.1, 2.0
• OpenVG 1.1

2D Graphics Processing Unit (GPU2Dv2)
• EGL 1.4
• OpenGL 2.1
• OpenCL 1.1 EP
• OpenVG 1.1
Operating Systems
• Windows CE
• Linux Embedded and X11
• Android
9.8 2D Graphics Processing Unit (GPU2Dv2)
9.8.1 2D feature summary

GPU2D has the following features:
• Bit BLT and stretch BLT
• Rectangle fill and clear
• Line drawing
• High performance stretch and shrink
• Mono expansion for text rendering
• ROP2, ROP3, and ROP4
• Alpha blending including Java 2 Porter-Duff compositing blending rules
• Support rendering size of 32Kx32K
• 90/180/270 degree rotation
• Transparency by monochrome mask, chroma key, or pattern mask
• Color space conversion between YUV and RGB
• High quality image scaling, using up to 9x9 separable filter
• Bit-Blit Formats
• A1R5G5B5 (source/destination)
• X1R5G5B5 (source/destination)
• R5G6B5 (source/destination)
• 8-bit color index (source only)

• A8 (source/destination)
• 1-bit monochrome (source only)
• Filter Blit Formats
• R5G6B5 (source/destination)
• YUV (source only):
• NV12 (4:2:0, 2 planes)
• NV16 (4:2:2, 2 planes)
• UYVY (4:2:2, interleave)
• YUY2 (4:2:2, interleave)
• YV12 (4:2:0, 3 planes)
• 8-bit color index(source only)
9.8.2 2D Block Diagram

Figure 9-8 below presents the integration of the GPU2D core in i.MX 6Dual/6Quad SoC.
GPU Debug Bus

IOMUX
64b AXI Master

AHB-32 Memory Access
32b AHB Slave GPU2Dv2 AXI
X-bar
Command Bus Graphics Core ARB.
Switch 64b AXI Master
Figure 9-8. GPU2Dv2 (GPU2D) Interface Diagram

Vector Graphics Processing Unit (GPUVGv2)
9.8.3 2D Performance
• Geometry Rate: 26.6M Triangles/sec
• Pixel Rate: 256M pixels/sec
9.8.4 2D Software
• GDI/DirectDraw
• DirectFB
• X11 EXA
Operating Systems
• Windows CE
• Android
9.9 Vector Graphics Processing Unit (GPUVGv2)
9.9.1 Vector Graphics Overview

The vector graphics processing unit is based on the GC355 IP core.
9.9.2 Vector Graphics Features

Featureset Overview:
• Real-time hardware curve tesselation of lines, quadratic and cubic Bezier curves
• 16x Line Anti-aliasing
• OpenVG 1.1 support
• Vector Drawing:
• Coordinate Systems and Transformations
• Viewport Clipping, Scissoring and Alpha Masking
• Pathsand stroke generation
• Image interpolation
• Image Filters
• Paint (gradient and pattern)

• Blending
Figure 9-9 below presents the integration of OpenVG core, in i.MX 6Dual/6Quad SoC.
GPU Debug Bus

IOMUX
AHB-32 32b AHB Slave 64b AXI Master

GC355 AXI
X-bar
Command Bus Graphics Core Memory Access ARB.
Switch
Figure 9-9. GPU2Dv2 (GC355) Interface Diagram
9.9.3 Vector Graphics Performance

• GPU-VG @ 533MHz
• Full OpenVG 1.1 Khronos Conformance
• 533 M pixels / sec raw performance (1 pixel / clock)
9.9.4 Vector Graphics Software

• OpenVG 1.1
Operating Systems
• Windows CE

HDMI TX - HD Multimedia Interface transmitter
9.10 HDMI TX - HD Multimedia Interface transmitter
9.10.1 HDMI Introduction

HDMI (High-Definition Multimedia Interface) is a compact audio/video interface for
transmitting uncompressed digital video data and uncompressed/compressed digital audio
data. HDMI connects digital audio/video sources-such as set-top boxes, Blu-ray Disc
players, personal computers (PCs), video game consoles, and AV receivers to compatible
digital audio devices, computer monitors, and digital televisions.
HDMI supports, on a single cable, any TV or PC video format, including standard,
enhanced, and high-definition video, up to 8 channels of digital audio, and a Consumer
Electronics Control (CEC) connection. The CEC allows HDMI devices to control each
other when necessary and allows the user to operate multiple devices with one remote
control handset.
Because HDMI is electrically compatible with the signals used by Digital Visual
Interface (DVI), no signal conversion is necessary, nor is there a loss of video quality
when a DVI-to-HDMI adapter is used.
The HDMI Transmitter (HDMI TX) consists of two parts:
• HDMI TX Controller
• HDMI TX PHY
Figure 9-10 depicts the HDMI TX integration scheme into the i.MX 6Dual/6Quad.

HDMI
Video I/F
Image Parallel I/F TX
Processing
Unit
TMDS_DATA
Audio DMA
HDMI
External AHB master 3
TX TMDS_CLK
Memory
PHY
Interface
HDMI
TX
Controller CEC
DDC(I2C)
Control Regs
2
AHB Slave
RNDGenGasket
Clocks
Interrupts
Figure 9-10. HDMI TX integration into the i.MX 6Dual/6Quad
The video interface is parallel with 24 bit/pixel data and separate signals for vertical
(VSYNC) and horizontal (HSYNC) synchronization. The video data is supplied by the
Image Processing Unit (IPU).
The audio data is read from an external memory by the internal Audio DMA via the
master AHB interface. The HDMI TX is controlled via the AHB interface.
9.10.2 Features
The HDMI TX features are listed in Table 9-9.
Table 9-9. HDMI TX Features
Specification item Requirement
General Features
Standard Compliance HDMI 1.4a

Display / Sensor MIPI interfaces
Table 9-9. HDMI TX Features (continued)

HDMI CTS 1.4a
DVI 1.0
HDCP 1.4
Consumer Electronic Control Supported
Monitor Detection Hot plug/unplug detection and link status monitor supported
Video Features
Video Standard Compliance EIA/CEA-861D
Supported Video Resolutions Up to 1080p@120Hz HDTV display,
up to QXGA graphics display,
HDMI 1.4a 4K x 2K video formats
HDMI 1.4a 3D video modes with up to 340MHz TMDS clock
Pixel Clock Frequency From 25 MHz to 340 MHz
Input Data Formats Parallel YCbCr 4:4:4 and parallel RGB 4:4:4
and parallel YCbCr 4:2:2
Input Color Depth 24/30/36/48 bits/pixel
Input Syncs Format Separate HSYNC and VSYNC plus data enable control
Internal Video Processing Interpolation YCbCr 4:2:2 to 4:4:4
Color space conversion YCbCr to RGB and vice versa
Audio Features
Audio Standard Compliance IEC60958, IEC61937
Supported Audio Formats All audio formats as specified by the HDMI Specification Version 1.4a supported.
Audio Input Interfaces Audio DMA
Audio Sampling Rate Up to 192 kHz
9.11 Display / Sensor MIPI interfaces
9.11.1 Introduction
i.MX 6Dual/6Quad Application Processor features MIPI DSI/CSI-2 interfaces that
includes:
• MIPI DSI Host controller with associated MIPI D-PHY Tx (One clock lane, two
Data lanes)
• MIPI CSI-2 Host controller with associated MIPI D-PHY Rx (one clock lane, four
Data Lanes)

9.11.2 MIPI DSI

MIPI DSI is a high performance serial interconnect bus for mobile applications
connecting display system to the host system.
Table 9-10. DSI Parametric Table
Name DSI
Function High speed serial interface controller for MIPI Display interface
Supported standard version MIPI DSI Compliant
DSI Version 1.01
DPI Version 2.0
DBI Version 2.0
DCS Version 1.02
PPI for D-PHY
MIPI D-PHY Version 1.0
External I/O Pins (List, Type, Schmidt Analog at chip boundary:
Trigger, Speed)
DATAP[1:0]
DATAN[1:0]
CLKP
CLKN
Supplies
AVDD -2.5V general analog supply
AVDDREF - 2.5V analog supply for D-PHY reference source (low noise) should
be directly connected to package ball
VDD - 1.1V digital supply
GND
SoC Buses (List, Type, Bandwidth) Synchronous Pixel Interface (DPI)
Display Bus Interface (DBI)
IPB slave interface x 32 bit
PPI to D-PHY
Interrupts 1
DMA Requests N/A
Num of instantiations 1
Clock sources and range AHB clock (132MHz)
Reference clock for Tx D-PHY - 6 ... 27 MHz
There is one instance of DSI port in the chip. This interface support from 80 Mbps up to
1 Gbps speed per data lane. The DSI Receiver core can mange one clock lane and up to 4
data lanes through the lane management, however two data lanes are implemented in the
transmitter D-PHY, therefore the maximum throughput of display port is 2Gbps.
Display / Sensor MIPI interfaces
DSI host core is capable of supporting a variety of resolutions and formats:

• Resolution:
• QQVGA
• QCIF, QVGA
• CIF
• VGA
• WVGA
• SVGA
• XVGA
• Pixel format:
• RGB565
• LRGB565
• RGB666
• RGB888
The DSI can support both command and video modes and up to four virtual channels to
accommodate multiple displays.
• Command and video mode support (type 1, 2, 3, and 4 display architecture)
• Mode switching: low power and ultra low power
• Burst mode: dual video channel
• Non-burst mode: single video channel
• Bus turnaround
• Fault error recovery scheme
DPI and DBI could coexists in the system but only one of them could be active in a
certain time moment
9.11.3 MIPI CSI-2

MIPI CSI-2 is a high performance serial interconnect bus for mobile applications
connecting camera sensors to the host system.
Table 9-11. CSI Parametric Table
Name CSI-2
Function High speed serial interface controller for MIPI sensor interface
Supported standard version MIPI CSI-2 Version 1.0
MIPI PPI interface for D-PHY
MIPI D-PHY Version 1.0
External I/O Pins (List, Type, Schmidt Analog at chip boundary:
Trigger, Speed)

Table 9-11. CSI Parametric Table (continued)

Name CSI-2
DATAP[3:0]
DATAN[3:0]
CLKP
CLKN
Supplies
AVDD -2.5V general analog supply
AVDDREF - 2.5V analog supply for D-PHY reference source (low noise) should
be directly connected to package ball
VDD - 1.1V digital supply
GND
SoC Buses (List, Type, Bandwidth) Synchronous Pixel Interface - 32 bit, data formatting compliant to CSI-2
specification
IPS slave interface x 32 bit
Interrupts 2
DMA Requests N/A
Num of instantiations 1
Clock sources and range AHB clock (132 MHz)
There is one instance of CSI-2 port in the chip. This interface supports from 80 Mbps up
to 1 Gbps speed per data lane. The CSI-2 Receiver core can mange one clock lane and up
to four data lanes through the lane management and de-packetization, providing a
maximum throughput of 4 Gbps transfer rate.
9.11.4 D - PHY
D-PHY serves as physical layer for both MIPI DSI and CSI-2 interfaces.
D-PHY Transceiver unit is responsible for transmission and reception of data in High
speed (HS) or Low Power (LP) mode. High speed mode is used for high-speed data
transmission while the low power mode used for the control purpose. Point-to-point lane
interconnect can be used for either data or clock signal transmission. High speed receiver
is a differential line receiver while low- Power receiver is an un-terminated, single-ended
receiver circuit.
Table 9-12. D-PHY Parametric Table
Name D-PHY TX, D-PHY RX
Function MIPI D-PHY dual mode transceiver
Supported standard version D-PHY specification v1.0

Audio subsystem
Table 9-12. D-PHY Parametric Table (continued)

Name D-PHY TX, D-PHY RX
External I/O Pins (List, Type, Schmidt One differential pair per lane. See CSI-2 and DSI parametric tables
Trigger, Speed)
SoC Buses (List, Type, Bandwidth) PPI i/f
Interrupts
DMA Requests N/A
Num of instantiations 8 - 3 in DSI interface and 5 in CSI-2 interface
Clock sources and range Reference clock - 6...27MHz
A single lane module is shown in the figure below.
PPI LP-TX
(appendix)
TX
HS-TX
Dp
Clock Dn
Lane Control HS-RX RT

Data and
Interface Logic RX
Ctrl
LP-RX
LP-CD
CD
Protocol Side Line Side
Figure 9-11. Single lane D-PHY- Block Diagram.
There is one instance of D-PHY TX (hard macro; two data lanes, one clock lane, PLL)
and one instance of D-PHY RX (hard macro: four data lanes, one clock lane, no PLL) in
i.MX 6Dual/6Quad.

9.12 Audio subsystem

The audio subsystem consists of the following modules: SSI-1, SSI-2, SSI-3, AUDMUX,
ESAI, SPDIF, ASRC, and MLB. In addition, the IOMUX must be appropriately
configured to get signals in and out of the chip.
Audio Subsystem Module Overview provides an overview of each of the audio
subsystem component modules, followed by a module-specific section.
9.12.1 Audio Subsystem Module Overview

The following figure shows a high level block diagram of the audio subsystem.

Audio subsystem
AUDMUX
Dedicated Audio Hardware
Audio Clocks
ARM
IP
3 Note: SSIx, SPDIF, and ESAI
could act as either clock master or clock slave. so
multiplexors should be provided to select related
clock input or output signal in dependence on
which mode, slave, or master mode is selected.
System Bus
SDMA 3
SSI1_3
SPBA
MLB_BI SPDIF ASRC ESAI_BIFIFO
MLB ESAI
Figure 9-12. Audio subsystem block diagram
SSI1–3 are synchronous serial interfaces used to transfer audio data. SSI1–3 are on the
shared peripheral bus. Instead of connecting to the IOMUX directly, their serial lines
connect to the digital audio mux (AUDMUX).
AUDMUX provides flexible, programmable routing of the serial interfaces (SSI1, SSI2,
or SSI3) to and from off-chip devices. AUDMUX routes audio data (and even splices
together multiple time-multiplexed audio streams) but does not decode or process audio
data itself. The ARM controls AUDMUX, but AUDMUX can route data even when the
ARM is in a low-power mode.

ESAI (enhanced serial audio interface) provides a full-duplex serial port for serial
communication with a variety of serial devices, including industry-standard codecs,
SPDIF transceivers, and other processors. ESAI consists of independent transmitter and
receiver sections, and each section has its own clock generator. ESAI is connected to the
IOMUX and to the ESAI_BIFIFO module.
ESAI_BIFIFO (ESAI bus interface and FIFO) is the interface between the ESAI module
and the shared peripheral bus. It contains the FIFOs used to buffer data to and from
ESAI. It also provides the data word alignment and padding necessary to match the 24-bit
data bus of the ESAI to the 32-bit data bus of the shared peripheral bus.
The SPDIF (Sony/Philips digital interface) audio module is a stereo transceiver that
allows the processor to receive and transmit digital audio over it. The SPDIF receiver
section includes a frequency measurement block that allows the precise measurement of
an incoming sampling frequency. A recovered clock is provided by the SPDIF receiver
section and may be used to drive both internal and external components in the system.
SPDIF is connected to the shared peripheral bus.
ASRC (asynchronous sample rate converter) converts the sampling rate of a signal
associated to an input clock into a signal associated to a different output clock. ASRC
supports concurrent sample rate conversion of up to 10 channels of over 120dB THD+N.
The sample rate conversion of each channel is associated to a pair of incoming and
outgoing sampling rates. ASRC supports up to 3 sampling rate pairs. ASRC is connected
to the shared peripheral bus.
9.12.2 Synchronous Serial Interface (SSI)

The Synchronous Serial Interface (SSI) is a full-duplex serial port that allows
communication with external devices using a variety of serial protocols. The SSI supports
a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to
24 bits per word), and clock/frame sync options.
The SSI has two pairs of 15x32 FIFOs and hardware support for an external DMA
controller in order to minimize its impact on system performance. The second pair of
FIFOs provides hardware interleaving of a second audio stream which reduces CPU
overhead in use cases where two timeslots are being used simultaneously.
The three SSIs may support three audio streams (possibly at different sample rates)
simultaneously. SSI1, SSI2 and SSI3 are located on the Shared Peripheral Bus. Since the
SDMA can directly access SSI1...SSI3 (being on the Shared Peripheral Bus), they can be
used for high-bandwidth data transfers in order to optimize bus bandwidth consumption.

Audio subsystem
9.12.3 Digital Audio MUX (AUDMUX)

The Digital Audio Mux (AUDMUX) provides a programmable interconnect fabric for
voice, audio, and synchronous data routing between host serial interfaces, such as SSI,
and peripheral serial interfaces-that is, audio and voice codecs.
The AUDMUX includes two types of interfaces. Internal ports connect to the processor
serial interfaces, and External ports connect to off-chip audio devices. A desired
connectivity is achieved by configuring the appropriate host and peripheral ports.
The AUDMUX provides flexible, programmable routing of the on-chip serial interfaces
to and from off-chip audio devices. The AUDMUX routes audio data (and even splices
together multiple time-multiplexed audio streams) but does not decode or process audio
data itself.
The following figure illustrates how the AUDMUX is connected in the system.

AUDMUX IOMUX
TxCLK3 CSI0_DAT4 (ALT4)

RxCLK3 CSI0_DAT10 (ALT1)
TxFS3 CSI0_DAT6 (ALT5)
Port 3
RxFS3 CSI0_DAT11 (ALT1)
RxD3 CSI0_DAT7 (ALT4)
TxD3 CSI0_DAT5 (ALT4)
TxCLK4 DISP0_DAT20 (ALT3)

RxCLK4 DISP0_DAT19 (ALT4)
TxFS4 DISP0_DAT22 (ALT3)
Port 4
RxFS4 DISP0_DAT18 (ALT4)

SSI 1 Port 1 DISP0_DAT23 (ALT3)
RxD4
TxD4 DISP0_DAT21 (ALT3)
SSI 2 Port 2
TxCLK5 DISP0_DAT16 (ALT3)

SSI 3 Port 7
TxFS5 DISP0_DAT18 (ALT3)
Port 5

RxD5 DISP0_DAT19 (ALT3)
TxD5 DISP0_DAT17 (ALT3)
TxCLK6 DI0_PIN15 (ALT2)

TxFS6 DI0_PIN3 (ALT2)
Port 6

RxD6 DI0_PIN4 (ALT2)
TxD6 DI0_PIN2 (ALT2)
- Daisy Chain, i.e. more than one PAD is available (only one option shown above).
Figure 9-13. AUDMUX System Block Diagram

Audio subsystem
9.12.4 Enhanced Serial Audio Interface (ESAI)

The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial
SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and receiver sections, each section with its
own clock generator. All serial transfers are synchronized to a clock. Additional
synchronization signals are used to delineate the word frames. The normal mode of
operation is used to transfer data at a periodic rate, one word per period. The network
mode is also intended for periodic transfers; however, it supports up to 32 words (time
slots) per period. This mode can be used to build time division multiplexed (TDM)
networks. In contrast, the on-demand mode is intended for non-periodic transfers of data
and to transfer data serially at high speed when the data becomes available.
The ESAI has 12 pins for data and clocking connection to external devices. The ESAI is
internally connected to the ESAI_BIFIFO, and does not connect directly to the shared
peripheral bus. The ESAI interface is designed for a 24-bit data bus, while the shared
peripheral data bus is 32-bit wide. Also, the ESAI data paths are only double buffered,
not allowing efficient DMA service in the applications processor environment. The
ESAI_BIFIFO allows increasing the data buffering and data width matching to the shared
peripheral bus.
9.12.5 Sony/Philips Digital Interface (SPDIF)

The SPDIF module is a stereo that allows the processor transmit digital audio over it
using the IEC60958 standard, consumer format. The chip provides one SPDIF transmitter
with one output and one SPDIF receiver with one input.
The SPDIF allows the handling of both SPDIF channel status (CS) and User (U) data.
For the SPDIF transmitter, the audio data is provided by the processor via the
SPDIFTxLeft and SPDIFTxRight registers, and the data is stored in two 16-word-deep
FIFOs, one for the right channel, the other for the left channel. The FIFOs support
programmable watermark levels so that FIFO Empty service request can be triggered
when the combined number of empty data words locations in both FIFOs is 8, 16, 24 or
32 words. It is recommended to program the watermark level to trigger a FIFO Empty
service request when 16 word locations are empty. For optimal performance when
servicing the FIFO Empty service request, the FIFOs should be written alternately,
starting with the left channel FIFO. The Channel Status bits are also provided via the

corresponding registers. The SPDIF transmitter generates an SPDIF output bitstream in

the biphase mark format (IEC 60958), which consists of audio data, channel status and
user bits.
The data handled by the SPDIF module is 24-bit wide. The 24-bit SPDIF data is aligned
in the 24 least significant bits of the 32-bit shared peripheral bus data word. The 8 most
significant bits of the 32-bit word are ignored by the SPDIF Transmitter when data is
being stored in the Transmit FIFOs from the peripheral bus. The 8 most significant bits of
the 32-bit word are zeroed by the SPDIF Receiver module when the data is being read
from the Receiver FIFOs to the peripheral bus.
Note that 16-bit data is left-aligned in the 24-bit word format of the SPDIF. When 16-bit
data is to be transmitted, the 32-bit word to be written to the SPDIF Transmit FIFOs
should be created as follows: the 16-bit data should be located in the middle two bytes of
the 32-bit data word and the 8 bits of the LSB must be set to zero, while the 8 bits of the
MSB will be ignored.
The SPDIF Transmit clock is generated by the SPDIF internal clock generator module
and the clock sources are from outside of the SPDIF block. The ESAI and MLB clock
sources should provide a clock that is at least 64 x Fs, where Fs is the sampling
frequency. The external clock source should provide at least 128 x Fs. Clocks of higher
frequency may be provided as long as the multiplication factor is a power of 2 (for
example, 128x, 256x or 512x). Also, clock frequency precision of 100ppm or better
should be provided.

Audio subsystem
To ESAI HCKR pin
SPDIF Rcv Clock

SPDIFIN1 DPLL
To ASRC clock input
SPDIF RVCR Audio
2 x 16 words
RCVR BLCK Data FIFO
C Channel 0 - 23
C Channel 24 - 47
U Channel 0 - 23
U Channel 24 - 47
SPDIFOUT1 To ASRC clock output
Off
SPDIF
XMTR
2 x 16 words
FIFO
C Channel 0 - 23
C Channel 24 - 47
U Channel 0 - 23
[Note: ESAI, SSI, MLB Clock freq at least 64 x Fs, 110 ppm] U Channel 24 - 47
ESAI HCKT 1-128

SSI1 TXCLK
SSI2 TXCLK DIV
MLB audioclock SPDIF Xmt Clock = 64 x Fs
2-512
External Audio Clock Input DIV
[Note: Ext Clock freq at least 128 x Fs, 100ppm]
Figure 9-14. SPDIF Transceiver Clock Diagram
9.12.6 Asynchronous Sample Rate Converter (ASRC)

The incoming audio data may be received from various sources at different sampling
rates. The outgoing audio data may have different sampling rates, and it can also be
associated to output clocks that are asynchronous to the input clocks.

ASRC converts the sampling rate of a signal associated to an input clock into a signal
associated to a different output clock. ASRC supports concurrent sample rate conversion
of up to 10 channels of about -120dB THD+N. The sampling rate conversion of each
channel is associated to a pair of incoming and outgoing sampling rates. ASRC supports
up to 3 sampling rate pairs.
In the real-time audio use case, both input/output sampling rate clocks are activated. Both
sampling rate clocks are directly connected to ASRC, and the ratio estimation of the input
clocks to output clocks is used to perform the sample rate conversion in ASRC hardware.
The SSI1, SSI2, SSI3, S/PDIF, ESAI, and MLB audio modules can act as either a clock
master or a clock slave. Multiplexors are provided on a chip level to select which of the
module's clock signal, input or output, will be connected to ASRC input in dependence of
the module's operational mode as it is shown in Figure 9-15 and Table 9-13. Figure 9-15
presents the multiplexor cell used for all ASRC input clocks. Table 9-13 shows the
detailed clocks, multiplexor control and data bits for each ASRC input clock. For the
audio blocks clocks that are directly conected to ASRC (without the multiplexor scheme)
see Table 9-14.
In the non-real time streaming audio use case, the input sampling rate clock does not need
to be provided. Instead the ideal-ratio value conversion is set in the ASRC interface
registers. In this case only the output sampling rate clock must be provided, and the fixed
ratio of the input to the output in the register is used to perform the sample rate
conversion.

Audio subsystem
Clock direction control
Clock Out
Clock In Audio Block

Bit Clock
11
1
00
0
asrck_clock_x
10
ASRC
01
Multiplexor
From GPR register (in IOMUXC)
Figure 9-15. Muxing scheme template for ASRC input clocks
Table 9-13. ASRC Muxed Input Clocks

ASRC Audio MUX2:1 MUX2:1 MUX2:1 MUX4:1 MUX4:1 MUX4:1 MUX4:1 MUX4:1
Clock block Control Input 0 Input 1 Control Input 01 Input 10 Input 11
Input 00
Input source
asrck_cloc SSI-1 (Rx) SRCR[RX External InternalSR GPR0[17:1 MUX2:1 External InternalSR RX bit
k_1 DIR]1 SRCK CK 6]2 output SRCK CK clock
asrck_cloc SSI-1 (Tx) STCR[TXD External InternalST GPR0[17:1 MUX2:1 External InternalST TX bit
k_9 IR] STCK CK 6] output STCK CK clock
k_2 DIR] SRCK CK 8] output SRCK CK clock
k_a IR] STCK CK 8] output STCK CK clock
k_3 DIR] SRCK CK 0] output SRCK CK clock
k_b IR] STCK CK 0] output STCK CK clock
asrck_cloc ESAI (Rx) RCCR[RC External InternalSC GPR0[23:2 MUX2:1 External InternalSC N/A3
k_0 KD] SCKR KR 2] output SCKR KR
asrck_cloc ESAI (Tx) TCCR[TCK External InternalSC GPR0[23:2 MUX2:1 External InternalSC N/A
k_8 D] SCKT KT 2] output SCKT KT

1. Register[bit] format, SRCR is the regsiter name in the block specified in the "Audio block source" column, while RXDIR is
name field/bit in the register.
2. GPR0 is the General Register 0 in the IOMUX controller. See IOMUXC chapter for more details.
3. Not in used, the clock value is "0".
Table 9-14. ASRC Direct Clocks

ASRC Clock Input Block driving clock source Block output clock
asrck_clock_4 SPDIF (Rx) SPDIF Rx Clock
asrck_clock_c SPDIF (Tx) SPDIF Tx Clock
asrck_clock_6 External (from PAD) Via IOMUX (from PAD)
KEY_ROW3 (ALT1) [default]
GPIO_0 (ALT3)
GPIO_18 (ALT4)
asrck_clock_7 Reserved Reserved1
asrck_clock_d CCM SPDIF1 clock root
1. Not in used, the clock value is "0".

Audio subsystem

Chapter 10
Clock and Power Management
10.1 Introduction
This chapter describes the Clock and Power Management architecture of the SoC.
The chip targets applications where low power consumption, long battery life, always-on
and instant-on capabilities are paramount, and where there is no need for active cooling.
To achieve these capabilities, the primary focus of the chip's design is reducing current
consumption as much as possible, while simultaneously enabling the maximum level of
peak performance and a balanced level of sustained performance for target applications.
To achieve this, the chip architecture uses a wide range of power-management techniques
and their combinations for maximum system design flexibility.
This chapter contains information about:
• Structural components of the power and clock management systems of the chip
• Power, clock and thermal management techniques supported by the chip
All given numerical values are typical or examples. For accurate values one should refer
to the datasheet.
10.2 Device Power Management Architecture Components

To provide a clean and versatile architecture supporting a wide range of power-
management techniques, clocks, and power rails are managed resources.
For each rail, two levels of management are defined: the first level is centralized or SoC-
level resource management, and the second is a local or "module level" resource
management.
The high level architectural view of the clock, power and thermal management system of
the chip is presented in the figure below.

Device Power Management Architecture Components
PMIC_STBY_REQ
CLK1 CCM
CLK2
Clock Clock 1
Generation Clock 2
OSC Clock N
24MHz
Configuration Clock Root
and Status Generation
OSC
Registers
32.768K
PLL Enables
Power State Control and
Clock Ready
Status Logic
Root M
Root 1
Root 2
Control and
Power State Ack

PMIC_ON_REQ
Power state request

Temperature Status Logic Handshake
Sensors Logic
Configuration
ON/OFF and Status
Button
SNVS Registers
GPC LPCG
SNVS
POR Voltage
Sensors Configuration
Power
Good
and Status
SJC Registers
ON/OFF
Clock State Reauest

Clock State Ack
DEBUG RST Control and Handshake
Status Logic Logic
POR SRC
PMU
Module Clock
Clock Enable
from module
(Integrated Power Regulators and
Power State Request

Switches) Color Coding
Power State Ack

VDD_SOC_IN
VDD_ARM_IN
Digital logic
VDD_HIGH_IN
VDD_SNVS_IN Clocks
Power
Power/Clock/Voltage Domain
Figure 10-1. Power and clock management framework
10.2.1 Centralized components of clock generation and

management
Centralized components of the clock generation and management sub-system are
implemented in the following blocks:
• CCM (Clock Control Module): The CCM module provides control for primary
(source level) and secondary (root level) clock generation, division, distribution,
synchronization, and coarse-level gating. See Clock Controller Module (CCM)) for

Chapter 10 Clock and Power Management
information on the CCM architecture, functional description and programming

model.
• LPCG (Low Power Clock Gating): This module distributes the clocks to all blocks in
the SoC and handles block level software-controllable and automated clock gating.
See Clock Controller Module (CCM) for information on the LPCG architecture and
functional description.
10.2.2 Centralized components of power generation, distribution

and management
Centralized components of the power generation, distribution and management sub-
system are implemented in the following blocks:
• Power Management Unit (PMU). See Power Management Unit (PMU) for
information on the PMU architecture, functional description and programming
model.
• General Power Controller (GPC). See General Power Controller (GPC) for
information on the GPC architecture, functional description and programming model.
10.2.3 Reset generation and distribution system

Power and clock management are accompanied with an appropriate reset generation and
distribution system, centralized functions of which are implemented by the System Reset
Controller (SRC).
10.2.4 Power and clock management framework

Together, the modules listed above provide enhanced power-management features with
centralized control for the clock, reset, and power-management signals on the SoC.
The centralized management framework defines the managed components of the power-
management architecture. These components are called the clock, power, and voltage
domains.
NOTE
A domain is a group of modules or functional blocks that share
a common resource entity (for example, common clock root,
common power source, or a common power switch). The
software component managing shared resources should take

Clock Management
into account the joint constraints of all the modules belonging

to that resource domain.
10.3 Clock Management
10.3.1 Centralized components of clock management system

The clock generation and management system is built around the CCM and LPCG
blocks.
A high level block diagram of the clock management system in the SoC environment is
shown in the following figure.

MLB_IO_CLK
CLK1 CLK2
MLB SATA PCIE IOMUX
MLB_CLK
MLB_PLL_PWR_DOWN
MLB_PLL_DIV_SEL[1:0]
SATA_REF_CLK
OSC
32.768K
REF_CLK
PCI_E
OSC
24MHz
REF_CLK
ENET
Configuration and Clock Generation Clock Generation
Status Registers Control and Status logic
Enable_USB1_PLL_PFDs
Enable_SYS_PLL_PFDs
XTAL_POWER_DOWN
USB1_PLL_PFDs[3:0]
SYS_PLL_PFDs[3:0]
Enable_USB1_PLL
Enable_ENET_PLL
Enable_ARM_PLL
Enable_AUD_PLL
Enable_MLB_PLL
Enable_SYS_PLL
Enable_VID_PLL
XTAL_ENABLE
XTAL_BYPASS
global_pll_lrf
USB1_PLL
SYS_PLL
AUD_PLL
24M_CLK
32K_CLK
VID_PLL
Stop
Configuration and
CCM
Control and Status logic Clock Selection and Root Generation
Status Registers
Root_xxx_enable
WFI
Root_1_enable
Root_2_enable
Root xxx
Root 1
Root 2
ARM_CLK
ARM
Clock
enable
At Reset
LPCG
Clock Gating Logic
SRC Mod_1_CLK1_enable
Mod_1_CLK2_enable
Mod_1_CLKX_enable
Mod_1_CLKX
Mod_1_CLK1
Mod_1_CLK2
Mod_K_CLKY_enable
Mod_K_CLK1_enable
Mod_K_CLK2_enable
Mod_K_CLK1
Mod_K_CLK2
Mod_K_CLKY
Frequency change /Stop
Request (Optional)
Acknowledge (Optional)
Module1

Request (Optional)
Acknowledge (Optional) Module K
Figure 10-2. Clock Management System
A high level block diagram of the clock generation is shown in the figure below.
10.3.2 Clock generation

The clock generation section includes the components detailed in the following sections.

Clock Management
10.3.2.1 Crystal Oscillator (XTALOSC)

The Crystal Oscillator block is comprised of both the high frequency oscillator (typical
frequency is 24 MHz) and the low frequency real time clock oscillator (typical frequency
of 32.768 KHz). Each of these oscillators is implemented as a biased amplifier that, when
combined with a suitable external quartz crystal and external load capacitors, implements
an oscillator. See Crystal Oscillator (XTALOSC) for details of the XTALOSC block.
10.3.2.2 Low Voltage Differential Signaling (LVDS) I/O ports

There is two LVDS I/O ports used for clock generation. The low jitter differential I/O
portsare provided to input and output clocks. It can take input clocks from outside of the
SoC and provide them to the PLLs or to the other modules, or it can take the outputs of
the PLLs and provide them outside of the SoC as a functional or reference clock.
10.3.2.3 PLLs
Eight PLLs are included in the clock generation section. Two of these PLLs are each
equipped with four Phase Fractional Dividers (PFDs) in order to generate additional
frequencies.
NOTE
Each PFD works independently by interpolating the VCO of the
PLL to which it is connected. It effectively takes the PLL VCO
frequency and produces 18/N x Fvco at its output where N
ranges from 12 to 35. PFD is a completely digital design with
no analog components or feedback loops. The frequency switch
time is much faster than a PLL because keeping the base PLL
locked and changing the integer N only changes the logical
combination of the interpolated outputs of the VCO. Note that
the PFD not only enables faster frequency changes than a PLL,
but also allows the configuration to be safely changed "on-the-
fly" without going through the output clock disabling/enabling
process.
The eight PLLs are listed below:
• PLL1 (also referred to as ARM_PLL) - This is the PLL clocking the Arm core
complex. It is a programmable integer frequency multiplier capable of output
frequency of up to 1.3 GHz (may exceed chip capabilities, see datasheet for more
information).

• PLL2 (also referred to as System_PLL or 528_PLL) - PLL2 generally runs at a fixed

multiplier of 22, producing 528 MHz output frequency with 24 MHz reference from
XTALOSC. It has the capability to spread spectrum the generated signal. Besides the
main output, this PLL drives four PFDs (528_PFD0...528_PFD3). The main PLL
output and its PFD outputs are used as inputs for many clock roots. These do not
require exact/constant frequency and can be changed as a part of dynamic frequency
scaling procedure and/or can be spread-spectrum modulated. Typically, this PLL is a
clock source for internal system buses, internal processing logic, DDR interface,
NAND/NOR interface modules, etc.
• PLL3 (also referred to as USB1_PLL or 480 PLL) - PLL3 is used in conjunction
with the first instance of USB PHY (USB0 PHY, also known as OTG PHY). This
PLL also drives four PFDs (480_PFD0...480_PFD3) and runs at a fixed multiplier of
20. This results in a VCO frequency of 480 MHz with a 24 MHz oscillator. The main
PLL output and its PFD outputs are used as inputs for many clock roots that require
constant frequency, such as UART, CAN and other serial interfaces, audio interfaces,
etc.
• 480_PLL2 (also referred to as USB2_PLL) - This PLL provides clock exclusively to
USB2 PHY (also known as HOST PHY). It runs at a fixed multiplier of 20, resulting
in a VCO frequency of 480 MHz with a 24 MHz oscillator.
• PLL4 (also referred to as an Audio PLL) - This is a fractional multiplier PLL used
for generating a low jitter and high precision audio clock with standardized audio
frequencies. The PLLs oscillator frequency range is from 650 MHz to 1300 MHz,
and the frequency resolution is better than 1 Hz. This clock is mainly used as a clock
for serial audio interfaces and as a reference clock for external audio codecs. It is
equipped with a divider on its output and can generate divided by 1, 2 or 4 from the
PLL VCO frequency.
• PLL5 (also referred to as a Video PLL) - This is a fractional multiplier PLL used for
generating a low jitter and high precision video clock with standardized video
frequencies. The PLLs oscillator frequency range is from 650 MHz to 1300 MHz,
and the frequency resolution is better than 1 Hz. This clock is mainly used as a clock
for display and video interfaces. It is equipped with dividers on its output and can
generate clock divided by 1, 2, 4, 8 or16 from the PLL VCO frequency
• PLL6 (also referred to as PLL_ENET) - This PLL implements a fixed 20+(5/6)
multiplier. With a 24 MHz input, it has a VCO frequency of 500 MHz. This PLL is
used to generate:
• 125 MHz for the PCIe serial interface and reduced gigabit ethernet interface.
• 100 MHz for the SATA serial interface
• 50 or 25 MHz for the external ethernet interface.
• MLB_PLL - This PLL takes the Media Link Bus (MLB) interface clock, multiplies it
up by 1, 2, or 4, and delay compensates so that the MLB data stream can be captured.

Clock Management
10.3.2.3.1 General PLL Control and Status Functions

Each PLLs configuration and control functions are accessible individually through its
PFDs and global configuration and status registers.
Reference input clock for any of the PLLs could be selected individually by the
BYPASS_CLK_SRC field of the PLL control register. See CCM Analog Memory Map/
Register Definition for more information.
Each of the PLLs could be individually configured to "Bypass", "Output disabled" and
"Power Down" modes.
When configured in "Bypass" PLL pass directly its input reference clocks to the PLL
output. Bypassing the PLL is done by setting the BYPASS bit in the control register. For
the PLL equipped with PFDs the input reference clock is also bypassed to all PFDs
outputs.
When configured in output disabled mode (ENABLE=0), the PLL's output is completely
gated and there is neither a bypass clock nor PLL generated clock that propagates to PLL
output. Each PLL output has an individual "Output Enable" control bit. The PFDs are
gated by the ENABLE bit of their associated PLL. Each PFD does have an associated
clock gate bit that can be used to turn it off individually.
When configured in "Power Down mode" most of the PLL circuitry is switched off.
Neither main PLL output nor PFD outputs are available in this mode.
When the related PLL is powered up from the power down state or made to go through a
relock cycle due to PLL reprogramming, it is required that the related PFDx_CLKGATE
bit in CCM_ANALOG_PFD_480n or CCM_ANALOG_PFD_528n, be cycled on and off
(1 to 0) after PLL lock. The PFDs can be in the clock gated state during PLL relock but
must be clock un-gated only after lock is achieved. See the engineering bulletin,
Configuration of Phase Fractional Dividers (EB790) at www.nxp.com for procedure
details.
Individual PLL status is reflected in "PLL Lock" bits of the PLL control registers. PLL
enable logic which monitors the register value change is implemented to gate off the PLL
outputs during the "lock in" period.
Outputs are generated to be sent out by monitoring the individual PLL lock flags and
filtering out any random initial edges.
Individual PLL Lock ready flags are first "ORED" with "enables" and then "ANDED"
together to generate the global PLL lock ready flag that reflects status of all PLLs
enabled in certain moment.

CCM Memory Map/Register Definition and CCM Analog Memory Map/Register

Definition contains detailed descriptions of the memory mapped registers and control
functions of the clock generation sub-module.
10.3.2.4 CCM
CCM includes:
• Clock root generation logic - This sub-block provides the registers that control most
of the secondary clock source programming, including both the primary clock source
selection and the clock dividers. The clock roots are each individual clocks to the
core, system buses (AXI, AHB, IPG) and all other SoC peripherals, among those are
serial clocks, baud clocks, and special functional clocks. Most of clock roots are
specific per module.
• CCM, in coordination with GPC, PMU and SRC, manages the Power modes, namely
RUN, WAIT and STOP modes. The gating of the peripheral clocks is programmable
in RUN and WAIT modes.
CCM manages the frequency scaling procedure for:
• Arm core clock - "on the fly" without clock interruption, by either shifting between
PLL sources PLL clock change or by changing the divider ratio.
• changing of the DDR memory controller clock. See MMDC handshake and Self
refresh and Frequency change entry/exit for more details.
• Peripheral root clock - by using programmable divider. The division factor can
change on the fly without loss of clocks.
NOTE
On-the-fly frequency changing for synchronous interfaces like
serial audio interfaces, video and display interfaces, or general
purpose serial interfaces (e.g. UART, CAN) may cause
synchronization loss and should not be done.
10.3.2.5 Low Power Clock Gating unit (LPCG)

The LPCG block receives the root clocks from CCM and splits them to clock branches
for each block. The clock branches are individually gated clocks.
The enables for those gates can come from three sources:

Clock Management
• Clock enable signal from CCM - This signal is generated depending on the power
mode the system is in. For each power mode, it is defined in the software using the
configuration of the CGR bits in CCM.
• Clock enable signal from the block - This signal is generated by the block based on
its internal logic. Not every enable signal from the block is used. Each clock enable
signal from the block can be overridden based on the programmable bit in CCM.
• Clock enable signal from the reset controller (SRC) - This signal will enable the
clock during the reset procedure.
10.3.3 Peripheral components of clock management system

The figure found here shows the clock interface of a functional module in the system.
BUS_A_CLK_gated BUS_B_CLK_gated
BUS_A_CLK BUS_B_CLK
CCM LPCG
Mod_X_BUS_A_Stop/Change_Req
Optional: If functional logic works
Optional: If functional logic works

Mod_X_CFG_BUS_CLK_gated
Mod_X_Data_BUS_CLK_gated
at configuration bus clocks
Mod_X_Bus_Idle (Master)
Mod_X_CFG_BUS_CLK
Mod_X_Data_BUS_CLK
Mod_X_FUNC_CLK_N
Mod_X_FUNC_CLK_1
Mod_X_FUNC_N_Idle
Mod_X_FUNC_N_Idle
at data bus clocks

Mod_X_ACK
System Configuration Bus
(IP/APB/AHB)
System Data Bus

(AXI/AHB)
Configuration Data Bus
and Status Functional Interface Logic
Registers Logic (Master or
(Slave) Slave)
Module X
Frequency change/Stop Acknowledge (Optional)
Frequency change/Stop Acknowledge (Optional)
Interrupt
Controller
Figure 10-3. Clock interface of the functional module in the system
10.3.3.1 Interface and functional clock

Each block within the SoC has specific clock input characteristic requirements. Based on
the characteristics of the clocks delivered to modules, the clocks are divided into two
categories: bus interface clocks and functional clocks.

The bus interface clocks have the following characteristics:

• They ensure proper communication between any block/subsystem and the system
buses.
• In most cases, they supply the system interface and configuration registers of the
block.
• A typical block has one system bus clock, but blocks with multiple interface clocks
may also exist (that is, when a block is connected to multiple buses).
• The bus interface clocks are always fed by the outputs of the CCM/LPCG.
• Clock management for this type of clock is always implemented at the system level
because it requires coordinated clock management between the block and system
buses.
Functional clocks have the following characteristics:
• They supply the functional part of a block or a subsystem.
• Typically, these clocks are completely asynchronous and independent from the bus
interface clock of the same block.
• A block can have one or more functional clocks. Some functional clocks are
mandatory, while others are optional for its functioning. A block needs its mandatory
clock(s) to be operational. The optional clocks are used for specific features and can
be shut down without stopping the block activity (in the case of IPU, that could be
the clock for a display interface or a camera sensor interface).
• The functional clocks are fed either by a CCM/LPCG block functional clock output,
or by some other clock source, such as a clock output of another block or an external
signal coming from IOMUX.
10.3.3.2 Block level clock management

Each block in the system may also have specific clock requirements. Certain module
clocks must be active when operating in some specific modes, or may be gated in some
others. Generally, the activation and gating of the module clocks are managed by LPCG.
Hence, the LPCG block must be programmed properly and, in case of hardware
controllable clock gating, peripheral module should provide signals indicating when to
activate and when to gate the module clocks.
The LPCG block differentiates the clock-management behavior for device modules based
on whether the block can initiate transactions on the device interconnect (called master
module), or if it cannot initiate transactions and only responds to the transactions initiated
by the master (called slave module). Thus, two hardware-based clock-management
protocols are used:

Clock Management
• Master protocol - Clock-management protocol between the CCM/LPCG and blocks

that can be bus master
• Slave protocol - Clock-management protocol between the CCM/LPCG and slave
modules
10.3.3.2.1 Master clock protocol

This protocol is used to indicate that a master module is ready to initiate a transaction on
the device interconnect and requests specific (both functional and interface) clocks. The
CCM/LPCG block ensures that the required clocks are active when the master module
requests that the CCM/LPCG enable them. The module is said to be functional after the
required clocks are activated.
Similarly, when the master module no longer requires the clocks, it informs the
LPCG/CCM block and the LPCG/CCM can then gate the clocks to the module and all the
clock precedents that are not used by other blocks. The master module is then said to be
in clock-gated or partially clock gated mode.
Examples of modules supporting master clock protocol areGPU3D, VPU,GPU2D,
VDOA and USDHC. Please see details in chapters describing these modules and in the
CCM enable override register (CCM_CMEOR).
10.3.3.2.2 Slave clock protocol

This hardware protocol allows CCM to control the state of a slave module. CCM informs
the slave module, through assertion of a stop/change request, when its clocks (both
interface and functional) can be changed or gated. The slave acknowledges the request
and CCM is then allowed to gate or change the clocks to the block.
Similarly, a clock-gated slave module may need to be woken up because of some event or
a service request from a master module. In this situation, CCM enables the clocks to the
module and then de-asserts the stop request to signal the module to wake up.
Examples of modules supporting slave clock protocol are CAN,EPIT and GPT. Please
see details in chapters describing these modules and in the CCM Module Enable Overide
Register (CCM_CMEOR). See CCM Memory Map/Register Definition for more details.
The protocol in both "master" and "slave" cases is completely hardware-controlled, but
software should configure the clock management behavior for the module in two places:
in the CCM registers associated with the block and in the block configuration registers.

10.3.3.3 Clock Domain(s)

A clock domain is a group of blocks fed by clock signals controlled by the same clock
controls in CCM. By gating the clocks in a clock domain, the clocks to all the blocks
belonging to that clock domain can be gated/activated, either by software control or by
hardware control associated with block activity. Thus, a clock domain allows efficient
control of the dynamic power consumption of the domain.
The device is partitioned into multiple clock domains and each clock domain is
controlled by an associated group of clock gating cells within the LPCG block. This
allows the CCM/LPCG to individually activate and gate each clock domain of the
system.
Examples of clock domains are: Main AXI bus clock domain, VPU clock domain,
GPU3D clock domain, etc.
10.3.3.4 Domain level clock management

The domain clock manager can automatically (based on hardware conditions) and
manage the bus interface clocks within the clock domain. The functional clocks within
the clock domain are managed through software settings.
10.3.3.5 Domain dependencies

A domain dependency is a hierarchical relationship between two clock domains. Clock
domain "X" is said to depend on a clock domain "Y" when a block in clock domain "Y"
provides services (or even just a clock) to a block in clock domain "X". As a result, clock
domain "Y" must be active whenever clock domain "X" is active.
The dependency between two clock domains may also exist if one clock domain serves to
ensure communication between two blocks (for example, the clock domain of the device
interconnect).
10.4 Power management

Power management
10.4.1 Centralized Components of Power Management System

The power generation and management system is built around the PMU and GPC blocks.
A high level block diagram of the power management system in the SoC environment is
shown in the figure below.
PMIC_STBY_REQ
CCM
Configuration
and Status
Registers
PMIC_ON_REQ PMU
(Control and Power State Control and
PMU Status Logic ) Status Logic
(Configuration
ON / OFF and Status
Button Registers )
SNVS
Configuration GPC
Request/ACK
SNVS Voltage
Power Gate
POR and Status
Sensors GPC
Registers
Power Interrupt
Good Controller
ON/OFF Control and
Status Logic
Power
POR SRC Gating
PMU ( Regulators and Switches )
Logic
VDD_SOC_IN
VDD_ARM_IN
VDD_HIGH_IN
VDD_SNVS_IN
GPU Isolation Control

GPU Power Gating
ARM Power Gating
ARM Isolation Control
Memories ARM Logic power

SoC power domain GPU power domain
sub-domain sub-domain
Interrupt Controller
ARM power domain
Wake- up Interrupt
Figure 10-4. Power Management System
10.4.1.1 Integrated PMU

The first component of the power management system, referred to as the integrated PMU,
is designed to simplify the external power interface.

It consists of a set of secondary power supplies that enable SoC operations from just two
or three primary supplies. The high level block diagram of the power tree, utilizing the
integrated PMU, is shown below.
VDD_SNVS_IN VDD_HIGH_IN USB VBUS USB VBUS VDD_SOC_IN VDD_ARM_IN

Device 5V Host 5V
ARM
Power
LDO 2P5 SATA PHY LDO3P0 LDO_DIG LDO_DIG LDO_DIG
(SoC) (PU) (ARM)
domain
LDO 1P1 USB PHY

GPU/VPU 2/4 ARM
(VDD_PU) Cores
(VDDG)
Bandgap LVDS PHY

(Anaclk1,2) SOC Internal
(VDD) Memory
LDO_RTC HDMI PHY
MIPI PHY
OSC32K SoC voltage domain
NVCC_LVDS
ARM PLL DDR/RGMII IO
SVNS Pre Drivers
528 PLL LVDS PHY

POR, PFD,
CLKMON
NVCC_XXX
MLB PLL _group
__
_group NVCC_XXX
OSC24M IO_group
_1
NVCC_XXX
ENET PLL
TSNS
Temperature
Audio PLL
Video PLL
Efuse
Switch
EFUSE
Figure 10-5. i.MX 6Dual/6Quad Power Tree
The integrated PMU includes the following components:

• Three Digital LDO regulators
• Two Analog LDO regulators
• USB LDO
• SNVS regulator
• Reverse well biasing
Power management
See Power Management Unit (PMU) for further details on integrated PMU functional
description and programmability.
10.4.1.1.1 Digital LDO Regulators

The integrated PMU includes three digital LDO regulators: LDO_ARM, LDO_PU, and
LDO_SOC. These regulators provide power to the ARM_Core power domain, the
combined VPU, IPU, and GPU power domain, and the rest of the SoC logic (except
always-ON SNVS domain).
NOTE
The name "digital" only refers to the type of load. It is not
related to the LDO design or feature set.
The digital LDO regulators can operate in the following modes:
• Internal Bypass - The regulation pass device (FET) is switched fully on, passing the
external input voltage to the load unaltered. The analog part of the regulator is
powered down in this state, removing any loss other than the IR drop through the
power grid and the FET. Be aware that a period of time (see datasheet) is required to
switch from the internal digital bypass mode to the analog regulation mode.
Typically it takes less than 100us. Please refer to PMU for further details on bypass
and power gate configuration.
• External Bypass - The input and output of the regulator are shorted externally to the
SoC. If operating in this configuration, enable the internal bypass early in the startup
sequence before attempting high frequency/high power operation. Be aware that
internal power gating is not available in this mode.
• Power Gate - The regulation FET is switched fully off, limiting the current draw
from the supply. The analog part of the regulator is powered down, limiting the
power consumption. The output voltage will fall to a level where the residual leakage
of the power FET balances with the leakage of the load. Power gating is applicable to
Arm and PU power domains.
• Analog regulation mode - The regulation FET is controlled such that the output
voltage of the regulator equals the programmed target voltage. The target voltage is
fully programmable in 25mV steps.
These modes allow the regulators to implement voltage scaling and power gating, and
allow bypass when an external high power efficient regulator is used as a direct source
for some of the SoC loads.
These digital regulators also feature brownout detection, which is helpful to sense when
supplies are starting to collapse. Note that the core will be interrupted on a brownout.
Please see details in Miscellaneous Control Register (PMU_MISC2n).

For further details of LDO programming and configuration please refer to Digital
Regulator Core Register (PMU_REG_COREn).
The power management system is built under assumption that in typical applications the
single (and simple) shared power supply will be used for Arm core domain and SoC
domain. The combined load gains some efficiency, especially in low power modes and
saves BoM significantly.
The DVFS in a typical cost/complexity optimized application is considered by mean of
internal LDO. In"full speed" modes LDO bypass is considered in both domains. The
dynamic voltage scaling to low load workpoints for Arm domain is implemented by
programming associated LDO.
In highly power-optimized systems, it is possible to use multiple external DCDC buck
converters and bypass internal LDO for high power domains. The obvious trade-off is in
the increased complexity of the external power supply components and the associated
increase in the BoM and board design complexity.
10.4.1.1.2 Analog LDO regulators

There are two analog LDO regulators used for general system purposes:
• LDO_1P1 - The LDO_1P1 (VDD_HIGH_IN, NVCC_PLL) linearly regulates down
a higher supply voltage (2.8V-3.3V) to produce a nominal 1.1V output voltage. This
regulator supplies digital portions of USB PHYs, PLLs, and the internal 24 MHz
oscillator.
10.4.1.1.3 USB LDO

The USB_LDO linearly regulates down the USB VBUS input voltages (typically 5V) to
produce a nominal 3.0V output voltage. This regulator has a built in power-mux that
allows the user to run the regulator from either one of the VBUS supplies when both are
present. If only one of the VBUS voltages is present, the regulator automatically selects
that supply. Current limit is also included to help the system keep the in-rush current
within limits as required in USB 2.0 specification. This regulator supplies only low speed
and full speed transceivers of USB PHYs.
10.4.1.1.4 SNVS regulator

The SNVS regulator takes the SNVS_IN supply and generates the SNVS_CAP supply,
which in turn powers the real time clock and low power section of the SNVS modules. If
VDDHIGH_IN is present, then the SNVS_IN supply is internally shorted to the
VDDHIGH_IN supply to allow coin cell recharging if necessary.

Power management
10.4.1.1.5 Reverse well biasing

The reverse well biasing module on the SoC consists of a self-clocked/self-regulating
charge-pump circuit, used to generate a negative bias voltage for the floating PWELL,
and a low-power regulator. The low-power regulator is used to generate a positive bias
voltage for the NWELL of the digital logic cells on the SOC power domain. Static
leakage reduction can be achieved during SoC low-power modes through the use of these
reverse well bias voltages. Please refer to the CCM_CLPCR register in CCM Memory
Map/Register Definition and PMU_MISC0 in PMU Memory Map/Register Definition for
details about well bias control and Static " for functional description of the reverse well
biasing.
10.4.1.2 GPC - General Power Controller

The GPC block includes the sub-blocks listed here.
• Power Gating Controller (PGC) - This sub-block of GPC has the following functions:
• Provides the user with the ability to switch off power to a target subsystem.
• Generates power-up and power-down control sequences. This includes
interaction with CCM/LPCG and SRC, and control for clock and reset
generation for power domains affected by power gating.
• Provides programmable registers that adjust the timing of the power control
signals.
• Controls the CPU power domain and the combined GPU/VPU power domain.
• Wake-up interrupt controller - This controller initiates the system wake-up from low
power modes when only low frequency real time clock remains active, and thus the
Generic Interrupt Controller (GIC) can not handle synchronous interrupt signals.
Additional features are as follows:
• Supports up to 128 interrupts
• Provides an option to mask/unmask each interrupt
• Detects interrupts and generates the wake up signal
See General Power Controller (GPC) for further details on GPC, its sub-blocks, and
information on its functional description and programmability.
10.4.1.3 SRC - System reset Controller

The reset controller is responsible for the generation of all reset signals and boot
configuration decoding.

It determines the source and the type of reset, such as POR, WARM, and COLD, and
performs the necessary reset signal qualifications. SRC is capable of generating reset
sequences in the following conditions:
• in interaction with external PMIC, based on external POR_B signal and "power
ready" signals generated by the integrated PMU
• or in interaction with the integrated PMU only, based on its "power ready" signal.
Based on the type of reset, the reset logic generates the reset sequence for either the entire
SoC or for the blocks that are power-gated.
See System Reset Controller (SRC) for further details on SRC functional description and
programmability.
10.4.1.4 Power domain(s)

A power domain is a group of blocks or sub-blocks fed by power sources controlled by
the same power controls in GPC.
Some power domains can be split into a logic sub-domain and a memory sub-domain.
The memory sub-domain in such case may contain two entities:
• Memory array(s) - Powered by a dedicated voltage rail enabling memory retention
while core is OFF.
• Memory interface logic - Powered by the same voltage source as the logic sub-
domain of the power domain.
Signals crossing power domain boundaries or sub-domain boundaries are passed through
proper isolation and/or level-shifting cells to ensure robust operations of the SoC when
some of domains are power gated or working at a reduced voltage.
The following figure shows the power domain interface within the system.

Power management
GPC
PMU
CCM
Module
Power Gating
Control
Memory Module
Interface Isolation
Power Gating Memory Control
Control Sub-domain
Isolation control
Memory
Sub-domain
Power Gating
Control
Isolation Functional Isolation

Memory And And To the rest
Memory Array Logic and of SoC
Interface Logic Level Level
Shifters FlipFlops Shifters
Module X
Figure 10-6. Power domain interface
10.4.1.4.1 Power distribution

The i.MX 6Dual/6Quad power distribution tree is comprised of multiple power domains.
The main power domains are:
• Arm - The Arm domain contains the Arm Core platform (except for memory arrays
and interface logic). This domain can be supplied either from an integrated power
supply or from an external controllable regulator, preferably high efficiency DCDC
converter.
• Arm Memory array - Memory arrays are connected to a separate and dedicated
power domain (separated from the Main logic and Arm domain). In normal operation
mode (functional mode), the memory arrays domain voltage level should be kept
equal to (same as) the rest of the core logic domains (Main, Arm). Please refer to the
Datasheet for further information about voltage level difference between domains
allowed in different power modes.
• Combined GPU and VPU domain - The combined GPU/VPU domain contains all
GPU3D and GPU2D engines and VPU engine.
• SNVS/RTC low power domain - The SRTC domain contains only counter,
comparator and compared data of the on-chip RTC. This domain should be supplied
from an external single cell LiION battery and/or an external pre-regulated power
supply.
• Analog domain - The analog domain contains the PLLs, LDOs and USB PHY. The
domain supplies should be constant to allow continuous clock during any dynamic
voltage scaling techniques. The digital supply should be provided from an internal

regulator, and can be combined with the memory array supply. The analog supply
should be provided from internal low noise regulator.
• Main SoC logic - The main SoC logic domain contains the rest of the logic of the
SoC.
From a DVFS and Power Gating standpoint, the following digital logic domains are
affected:
• Cortex-A9 Core Platform - DVFS and power gating.
• Arm Cortex-A9 memories - Power gating only.
• GPU3D and VPU - Power gating only.
See table below for details of the i.MX 6Dual/6Quad system power domains layout and
dependencies.
10.4.1.4.2 Domain Memory and domain logic state retention in case of

Power Gating
The following is the list of relevant memories and logic domains with the description of
their state-retention support:
• Cortex-A9 Core Platform is sub-divided into three sub-domains listed below:
• Cortex-A9 Core Platform logic: The software state retention for all logic is
implemented in this domain. That means that the content of relevant registers should
be be stored in some memory retaining its state (L2 cache for example) while the
logic domain is power-gated. Details on how to implement the software retention can
be found in the Cortex-A9 Core Platform TRM.
• Cortex-A9 Core L1 memories - No retention. The L1 memories have a dedicated
supply on the package (VDD_CACHE_CAP) which should be connected to the
Cortex-A9 Core Platform supply. The L1 cache should be flushed prior to power
gating in order to allow powering up of the CPU at the same state as before power
gating.
• Cortex-A9 Core L2 memories - hardware state-retention since its supplies are driven
by the SoC supplies.
• GPU3D, GPU2D and VPU: These three modules can be power gated (together)
independently of Cortex-A9 power gating, because it resides on a separate power
domain. State retention is supported neither for GPU3D, GPU2D and VPU logic nor
for their internal memories.
• ANALOG PHY IPs - PCIe, SATA and HDMI - hardware state-retention since its
supplies are driven by non-gated supplies.
• SoC - hardware state-retention in Standby mode. Reverse Well Biasing is applicable
for this domain.
• SNVS_LP - hardware state-retention even when SoC supplies are removed.
Power management
10.4.1.4.3 Power Gating Domain Management

The following bullets provide the sequence required for power-gating the relevant power-
domains:
10.4.1.4.3.1 Arm Core Platform

1. Copy through software all the Core configuration registers to a powered-on memory
2. Configure the GPC/PGC CPU registers in PGC Memory Map/Register Definition as
follows to power-down the core on the next "WFI" instruction:
• Configure the GPC/PGC PGC_CPU_PDNSCR Register ISO and ISO2SW bits.
The ISO field determines the delay between the power-down request and
enabling the platform isolation. The ISO2SW field determines the delay between
the platform isolation and the actual power-off switch to the supplies.
• Configure the GPC/PGC PGC_CPU_PUPSCR Register SW and SW2ISO bits.
The SW field determines the delay between the power-up request and the actual
power-up of the supplies. The SW2ISO field determines the delay between
asserting power toggle and negating platform isolation.
• Configure the GPC PGC PGC_CPU_CTRL PCR bit to allow the power down of
the platform
• Arm Core Platform should execute a "WFI" instruction.
Isolation enable
Power on
Power sequence phase
ISO Count ISO2SW Count Power Down SW Count SW2ISO Count
Figure 10-7. Arm Core Platform isolation and power on switch flow
10.4.1.4.3.2 GPU3D, GPU2D and VPU

1. Configure the CCM CGR bits (CCM Memory Map/Register Definition) to disable
the GPU3D, GPU2D and VPU clocks.
2. Configure the GPC/PGC Registers (GPC Memory Map/Register Definition) as
follows to power-down isolate the GPU3D, GPU2D and VPU logic from the rest of
the SoC logic :
Configure the GPC/PGC PDNSCR Register ISO bits. These bits determine the delay
between the power-down request to enabling the LDO domain isolation.

Configure the GPC/PGC PUPSCR Register SW2ISO bits. These bits determine the
power-up request to the LDO domain isolation disabling.
Configure the GPC/PGC CTRL[PCR] bit to allow the power down of the block.
Configure the GPC/PGC GPC_CNTR to power down GPU3D, GPU2D and VPU
Isolation enable
Power on
Power sequence phase
ISO Count SW Gate Supply Power Down SW Enable Supply SW2ISO Count
Figure 10-8. GPUs and VPU isolation and power on switch flow
10.4.1.4.3.3 SoC
For additional power reduction it is possible to do the following:
• Power-down the internal oscillator by configuring the following bits
CCM_CCR[COSC_EN] (CCM Memory Map/Register Definition). This can be done
only in case there is no dependency on 24 MHz XTAL for wake-up.
• Enable reverse well biasing by configuring the CCM_CLPCR[WB_PER_AT_LPM]
bit (CCM Memory Map/Register Definition).
• It is possible to turn off and turn on the PMIC supplies to the SoC even when the
SoC supplies are off. Since SNVS_LP is powered through an "always on" supply,
configuring the SNVS_LP DP_EN to "1" allows changing the PMIC_ON_REQ pad
(SoC on/off supply indication to the PMIC) through the ONOFF pad.
10.4.1.4.4 Power Gating domain dependencies

There are 3 power domains that need to be isolated in different power-down cases:
• Cortex-A9 Core Platform - Isolation needs to be enabled before power-down. This is
taken care of automatically after CCM and PGC are configured and the Cortex-A9
Core Platform executes the "WFI" instruction.
• GPU3D, GPU2D and VPU - Isolation needs to be enabled before power-down. This
should be taken care through software configuration of the PGC.
• SNVS_LP - Different from the 2 domains above, the SNVS_LP isolation isolates the
signals coming from the SoC to the SNVS_LP. This is required for saving the
contents of the SNVS_LP (such as the real-time clock). The isolation is activated in 2
ways:

Power management
• Automatically through the power-fail detector in the PMU

• Through software configuration
isolation volt level isolation

GPU3D cells shifters cells SNVS_LP
isolation SoC Voltage volt level isolation

GPU2D/VG cells Domain shifters cells
Cortex-A9
VPU isolation
cells
Note: The arrows refer to the signal directions for the voltage level shifters and isolation cells
Figure 10-9. Isolation cells and Voltage level shifters placing
10.4.1.5 Voltage domains

The list found here states the different voltage domains and their scalability in regarding
to power-saving in dynamic and static scenarios.
• Arm - Cortex-A9 Core Platform including L1 cache - Scalable voltage in both
dynamic and static scenarios
• SoC and PU LDO Domains - Scalable voltage only in static scenarios
• ANALOG components including SATA, PCIe, LVDS andHDMI, MIPI, LVDS and
PLLs - Fixed voltage
• I/O - Fixed voltage
• SNVS_LP - Fixed voltage
10.4.1.6 Voltage domain management
10.4.1.6.1 Dynamic
10.4.1.6.1.1 Voltage Scaling

A simplistic way to reduce power consumption in dynamic scenarios is to scale down the
Arm, SoC and PU LDOs voltage according to the allowed voltage points and
corresponding frequencies specified in datasheet.

10.4.1.6.2 Static
10.4.1.6.2.1 Standby Leakage reduction (SLR)

Standby leakage reduction is a power-management technique utilizing:
• Reduced supply voltage for relevant domains
• Reverse well-biasing in STOP, WAIT, or Deep Sleep Mode (DSM) modes
With SLR, the device switches into low-power active system modes automatically or in
response to user requests during system Stop, Wait, or DSM modes (that is, in situations
when no application is started and no system activity is presented).
When applying SLR, the system remains in the lowest static power mode while retaining
logic and memory states. This technique trades static power consumption for wake-up
latency while maintaining fast system response time suitable for most applications.
See CCM Control Register (CCM_CCR), CCM Low Power Control Register
(CCM_CLPCR) and PMU Miscellaneous Register 0 (PMU_MISC0) for further details
on SLR programmability options.
The following describes the flow for applying standby voltage and reverse well bias to
the SoC:
• Configure the external PMIC standby voltage, refer to chip datasheet.
• Configure CCM_CCR[RBC_EN] bits to bypass and disable PMU regulators in the
next Arm "WFI" execution.
• Configure CCM_CCR[REG_BYP_COUNT] bits to allow proper voltage restoration
by the external PMIC when exiting standby.
• Arm Core Platform executes the "WFI" instruction that completes the software
sequence putting the SoC into low power mode
• After that, the reverse well bias will be applied automatically (if enabled) with
appropriate delay. Please refer to CCM_CLPCR and CCM_CCR Registers in CCM
for further information on reverse bias enabling and counters configuration.
10.4.1.6.2.2 ANALOG PHYs IPs

The PCIe, SATA and HDMI analog PHYs can also be configured to consume less power
when the are in a non-active state. Details on how to put the IPs in low power mode can
be found in each of the IP documentation. Further reduction can be achieved by settings
the ENABLE_WEAK_LINREG in the PMU PMU_REG_2P5 register.

Power management
10.4.1.7 System domains layout
The following table describes the different power modes.

NOTE
Wakeup time is the hardware perspective, and doesn't reflect
the time it takes software to resume drivers and perform system
operations.
Table 10-1. Aimed power modes
Mode Description Wake-up capability Wakeup time Applicable use
case
(Status of main power
domains)
RUN Power supplies are on, N/A N/A All
all clocks are on.
WAIT Power supplies are on. Based on interrupt from any Immediate (Arm exit IDLE process of
module WFI) operating system.
Arm executes WFI command,
Option to gate off clocks for
specific modules based on
programmable bits.
STOP Power supplies are on. Based on interrupt from modules ~50us Suspend state of
that can track operation with low operating system -
Arm executes WFI command.
frequency clock- like Keypad system is on but is
VPU and GPU are in power press, GPIO, Timer, CAN activity, waiting for
gating etc. operation.
PLLs are off, hence all system
clocks are off.
Standby - PLLs disabled Same as above ~220 us Low power standby
mode with limited
- Low voltage could be applied
reaction on external
to Arm and SoC power inputs events
- Chip regulator bypass if reduce
supply voltage,
- Well Bias could be activated
- CPU regulator disabled for
power gating
- PU regulator is disabled in
software
- xtal enabled
Deep Same as above but with Interrupts from modules those ~1400us
Sleep OSC24M disabled could generate asynchronous
interrupts (Keypad, GPIO, SNVS)
SRTC Only SNVS domain and OSC32K SRTC security alert / SRTC timer ~1700us to WARM
keep alive expire. boot
Based on each one of those,
SRTC module will generate
request to PMIC to perform POR

Table 10-1. Aimed power modes

Mode Description Wake-up capability Wakeup time Applicable use
case
(Status of main power
domains)
sequence and walk-up the system. COLD boot,
The system will go through boot depends on boot
process. procedure and boot
device
PMIC can also receive press on
"ON" button to walk-up the
system. This should be connected
directly to PMIC.
There is a single hardware signal coming into PMU which sets the PMU in either of two
"STOP" states. The STOP state is implemented is controlled by the
PMU_MISC0[STOP_MODE_CONFIG] bit (See PMU Memory Map/Register
Definition). It is recommended that the blocks be configured for safe powerdown/up
through the registers before asserting the stop_mode signal. Blocks not described in the
section below are unaffected by stop_mode.
If the stop_mode_config is set to zero, thus in the STOP mode all blocks powered down
in minimum power configuration.
If the stop_mode_config is set to one, thus in the STOP mode some of the blocks remain
powered and in different states as defined in the table below.
Table 10-2. STOP mode configuration
Block STOP_MODE_CONFIG=0 STOP_MODE_CONFIG=1
reg1p1 off on
reg2p5 off on
reg3p0 off/on depending on vbus. Uses crude off/on depending on vbus . Uses analog
local reference if vbus is present central bandgap if VBUS is present.
reg_core bypassed if not power gated. bypassed if not power gated
reg_pu bypassed if not power gated. bypassed if not power gated.
reg_soc bypassed bypassed
bandgap off functional
temp_sensor off off
well_bias hardware controlled hardware controlled
All PLLs off off
OSC24M off Controlled by CCM configuration
LVDS clock I/O CLK1 and CLK2 off off

Power management
10.4.2 Power management techniques

The device supports the power-management techniques with the features found here.
• Partitioning of the device into voltage, power, clock, and reset domains
• Domain isolation that allows flexible configurations of domains on/off states to form
use cases targeting various applications
• Clock tree with selective clock-gating conditions and almost independent clock roots
• Power, reset, and clock control hardware mechanism to manage sleep and wake-up
dependencies of power domains
• Software-controllable and hardware-controllable clock gating for functional modules
and buses
• Memory retention and state retention capability (Software State Retention for Arm
core) for preserving memory contents and device state in low-power modes
• Support for low-power device modes input/output (I/O) pad configuration for
minimum power
• Variety of operating modes to optimize device performance and wake-up times
• Thermal monitoring and thermal aware performance management
Many of the low power features are fully or partially software controllable and can be
configured for the specific requirements of a target system.
Combining these techniques, the system designer may meet tight requirements of low-
power standby and operational modes while maintaining high performance for time-
critical tasks.
10.4.2.1 Power saving techniques

The table below lists power saving techniques supported by the SoC in their connection
to different components of power consumption.
Table 10-3. Power saving design/architecture and power saving techniques
Techniques Active SoC Standby SoC System
Power Power Power
Temperature Monitoring, and active frequency throttling √
Arm Core Platform SRPG (Software) √
Arm Core Platform Power Gating √
Cortex-M4 Asymmetric multicore √ √ √
VPU and GPU3D Power Gating √1 √
Clock gating (automatic dynamic and forced) √
Integrated PMU (IR drop, efficiency, accuracy) √ √
C4 package (IR drop, thermal) √

Table 10-3. Power saving design/architecture and power saving techniques (continued)
Techniques Active SoC Standby SoC System
Power Power Power
Display Backlight optimization (IPU, SW) √
Architecture: L2 cache, Video / Audio / Graphics acceleration √
Architecture: SATA, PCIe, LVDS, HDMI, USB integration √
Low Power DDR: LPDDR2, LV-DDR3 √
1. Applicable to use cases where GPU3D and VPU operation is not required.
10.4.2.2 Thermal-aware power management

The temperature sensor block (TEMPMON) implements a temperature sensor/conversion
function. The block features an alarm function that can raise an interrupt signal if the
temperature is above a specified threshold.
Software may implement temperature aware DVFS for the Arm domain and the GPU
domain, as well as temperature aware frequency scaling for other system components to
ensure that both the frequency and voltage is lowered when the die temperature is above
the specified limit.
Software may also implement temperature aware task scheduling to ensure that non-
critical tasks are suspended when the die temperature is above the specified limit.
See Temperature Monitor (TEMPMON) for further details on temperature monitor
functions and programmability options.
10.4.2.3 Peripheral Power management
10.4.2.3.1 Main memory power management

Main system memory, DDR3, and LPDDR2 are some of the most power-hungry system
components, but the SoC provides several options to manage DDR power.
Automated power saving modes are supported by the MMDC hardware. This feature
allows the DDR memory to automatically enter self-refresh mode when there are no
DDR accesses for a configurable time. The default setting is 1024 clock cycles which can
be optimized based on the customer use case and application.
See Power Saving and Clock Frequency Change modes for further details on MMDC
power saving features and programmability options.

Power management
Software may support DDR frequency scaling. Automated frequency changing procedure
is supported by MMDC and CCM modules.
NOTE
DDR frequency changes cost extra time and power. Slowing
requestors while keeping DDR at full speed may increase total
system power. Software may also implement Cooperative
Dynamic Frequency Scaling in order to keep the system
balanced, (that is, keep the system in balance when DDR
throughput is equal or slightly higher than total amount of
requests generated by all requestors).
Reducing the DDR frequency while in DLL-ON mode may be not efficient because:
• Reduction in DDR frequency will cause bus duty cycle to increase and thus reduces
chance of automatic MMDC power saving (place memory into SR).
• Total amount of read/write operation does not change (power is per-operation).
• The termination is active longer, though, lowering frequency from 528 MHz to 400
MHz or below may enable lowering drive strengths and termination.
When possible at lower performance use cases, software may switch DDR3 to DLL-off
mode. This allows it to greatly reduce DDR3 frequency and thus disable or reduce
termination and drive strength, which significantly reduces the power consumption of the
DDR3 interface.
A good strategy for many types of workloads is to combine most activity in bursts
(natively possible, for example, for typical multimedia applications, communication, etc.)
and run this segment at maximal speed, then switch to DLL-OFF mode to support
background activity (communication, display refresh, housekeeping).
The DRAM Interface power dissipation depends on many variables, however, proper
termination and drive strength is key for power and thermal performance. Memory and
controllers provide a host of programmable options for the drive strength of the output
buffers and for the on-die termination impedance.
The ideal settings for drive strength and ODT also depend on the clock frequency to
ensure that inter-symbol interference (ISI) effects are not introduced.
DDR PHY power is proportional to the amount and type of bus activity. For more data on
ODT savings, please refer to the Application Note, AN4509 i.MX 6Dual/6Quad Power
Consumption.
In cases where the DDR is placed into self-refresh, software can configure DDR I/O to be
floated or lowered to the minimum drive allowed by JEDEC.

Modifying the DDR drive strength must be done by code that is executing from a
memory region other than DDR (for example, IRAM). No access to DDR (including
page table walks, cache misses, alternate bus master accesses, etc.) is allowed while the
DDR I/O pads are being re-configured.
10.4.2.3.2 IO power reduction

Software configures IO to low power modes:
• PHYs - make sure that all unused PHYs are placed to lowest power state. Please refer
relevant chapter for further information about different PHYs
• Digital IOs - Make sure all unnecessary PU/PD are disabled and IO are switched to
either minimal drive strength or to input mode (when applicable)
• Set DDR type IO to CMOS mode if possible, specifically RGMII segment
10.4.2.4 Examples of External Power Supply Interface

This section presents the example of external power supply interfacing to the chip.
The scenario based on integrated PMU system is presented in the following figure. This
scenario minimizes BoM and board design complexity.

Power management
DCDC1
i.MX6 Q/D
ON/OFF
VDDARM_IN
LDO_DIG VDD_ARM_CAP
(ARM0,1)
VDDARM23_IN LDO_DIG VDD_ARM2,3_CAP
STBY (ARM2,3)
ARM0,1 ARM2,3
VDD_SoC_CAP
PWR_GOOD CACHE Array
VDDSOC_IN LDO_DIG VDD_SoC_CAP
(SoC)
SoC logic
DCDC2 VDDHIGH_IN
LDO_DIG VDD_PU_CAP
ON/OFF (PU)
GPU3D
GPU2D
NVCC_LVDS_2P5 OpenVG
VPU
STBY LVDS_IO
LDO2P5 VDD_HIGH_CAP
NVCC_DRAM
PWR_GOOD
DRAM_IO
SATA PHY SATA_VPH
Digital IO supplies should be provided per application requirements. All IO group supplies at the same operating voltage,
NVCC_RGMII SATA_VP
NVCC_LVDS_2P5 RGMII_IO
should be connected
MIPI PHY NVCC_MIPI
directly to NVCC_GPIO
VDD_HIGH_CAP
GPIO_IO
NVCC_LCD
PCIe PHY PCIE_VPH
LCD_IO PCIE_VP
NVCC_CSI
CSI_IO
HDMI Tx PHY HDMI_VPH
NVCC_ENET
HDMI_VP
ENET_IO
NVCC_EIM0
EIM0_IO
NVCC_EIM1
USB OTG PHY USB_OTG_VBUS
EIM1_IO
NVCC_EIM2
except NVCC_DRAM, can be combined.
EIM2_IO
USB H1 PHY USB_H1_VBUS
NVCC_NANDF
NANDF_IO
NVCC_SD1
SD1_IO
NVCC_SD2
SD2_IO NVCC_PLL_OUT
LDO PLL
NVCC_SD3
PLLs
SD3_IO
NVCC_JTAG
Could be connected to either coincell

/ JTAG_IO
supercap in case of systems keeping real
time clock in OFF mode. Otherwise could VDD_SNVS_IN
be combined with VDDHIGH_IN
PMIC_ON_REQ VDD_SNVS_CAP
LDO_SNVS
PMIC_STBY_REQ
Optional Standby request signal to DCDC converters
POR SNVS_IO SNVS (LP)
Optional POR signal from DCDC converters
ON/OFF
Button
Figure 10-10. Supplying i.MX 6Dual/6Quad power using integrated PMU

The scenario based on external programmable regulators is presented below: This

scenario could be used in highly power optimized systems.

Power management
PMIC i.MX6 Q/D
VDDARM_IN
OUT1 (DCDC) LDO_DIG VDD_ARM_CAP
(ARM0,1)
VDDARM23_IN LDO_DIG VDD_ARM2,3_CAP
(ARM2,3)
ARM0,1 ARM2,3
VDD_SoC_CAP
CACHE Array
VDDSOC_IN LDO_DIG VDD_SoC_CAP
OUT2 (DCDC)
(SoC)
SoC logic
VDDHIGH_IN
OUT3 LDO_DIG VDD_PU_CAP
(PU)
GPU3D
GPU2D
NVCC_LVDS_2P5 OpenVG
OUT4 VPU
NVCC_LVDS_2P5 should be connected LVDS_IO

directly to VDD_HIGH_CAP LDO2P5 VDD_HIGH_CAP
OUT5
NVCC_DRAM
DRAM_IO SATA PHY SATA_VPH

Digital IO supplies should be provided per application requirements. All IO group supplies at the same operating voltage,
NVCC_RGMII SATA_VP
OUT6
RGMII_IO
MIPI PHY NVCC_MIPI

NVCC_GPIO
GPIO_IO
NVCC_LCD
PCIe PHY PCIE_VPH
LCD_IO
PCIE_VP
NVCC_CSI
CSI_IO HDMI_VPH
HDMI Tx PHY
NVCC_ENET
HDMI_VP
ENET_IO
NVCC_EIM0
EIM0_IO
NVCC_EIM1
USB OTG PHY USB_OTG_VBUS
EIM1_IO
NVCC_EIM2
except NVCC_DRAM, can be combined.
EIM2_IO USB_H1_VBUS
USB H1 PHY
NVCC_NANDF
STBY
NANDF_IO
OUT N NVCC_SD1
ON/OFF
Button SD1_IO
ON/OFF
NVCC_SD2
SD2_IO NVCC_PLL_OUT
LDO PLL
NVCC_SD3
PLLs
SD3_IO
NVCC_JTAG
POR JTAG_IO
VDD_SNVS_IN
Always_ON
PMIC_ON_REQ LDO_SNVS
VDD_SNVS_CAP
PMIC_STBY_REQ
POR SNVS_IO SNVS (LP)
Figure 10-11. Supplying i.MX 6Dual/6Quad Power Using External Programmable PMIC

10.5 ONOFF (Button)

The chip supports the use of a button input signal to request main SoC power state
changes (i.e. On or Off) from the PMU.
The button is used to power On and Off the SoC using an always-on (e.g., coincell
battery-backed) power domain.
• When the chip main power supply is Off, a button press greater in duration than 750
ms asserts an output signal to request power from a power IC to power up the SoC.
• When the chip main power supply is On, a button press between 750 ms and 5
seconds will send an interrupt to the core to request that software bring down the
SoC safely. Software may respond to the interrupt by saving the processor state and
then setting a control bit that requests to the power IC the removal of the main power
supply.
• Button presses greater than 5 seconds, when the SoC is powered, results in a direct
hardware power down request signal to the power IC without providing a software
interrupt first. This long button press initiates a hardware-enforced mode which is
applicable when software is unable to power Off the device.
The button is connected to input ONOFF and the power IC is connected the chip output
PMIC_ON_REQ. The chip must have TEST_MODE deasserted. An always-On supply
(e.g. coincell) is needed in the system for this feature.

ONOFF (Button)

Chapter 11
System Security
11.1 Overview
Security is a common requirement for platforms built using the chip, although the
specific needs vary greatly depending on the platform and market. The type and cost of
assets to be protected on a portable consumer device are very different from those to be
protected on automotive or industrial platforms, and the same applies to the kind of
attacks and level of resources threatening those assets. The platform designer must select
an appropriate set of counter measures to meet the relevant platform security needs.
The following figure shows a simplified diagram of the security subsystem.
Supervisor mode
CAAM
access indication
ARM TZ AES-128 DES 3DES

Non-secure mode
indication RC4 DMA
AES-256
To
Alarm
RNG SHA-256 MMDC
iROM Secure Secure Key Module

(HABv4.1) RAM
To OCRAM
Security State
MMU
CSU
Secure
RAM
Zeroize SNVS
ARM RAM
SW Alarm
Alarm HP
System Security Monitor
DTCP HDMI JTAG LP

Controller Controller Controller
Zeroizable Secret key
Secure Time and Monotonic Counter

Disable
JTAG
HDCP
DTCP
HAB
Keys
Keys
Param
Tamper & Power Glitch Detectors
Electrical Fuse Array (OCOTP)
Fuse Secret Key, Boot Image Version Control,
Ship Unique Identification, SRK hash, Security Configuration Fuse Unique
Secret Key
Figure 11-1. Security subsystem (simplified)

Central Security Unit (CSU)
For the platform designer to meet the requirements for each market, the chip incorporates
a range of security features which can be used individually or in concert to underpin the
platform security architecture. Most of the chip security features provide protection
against particular kinds of attack and can be configured at various levels according to the
required degree of protection. These features are designed to work together and can be
integrated with appropriate software to create defensive layers. In addition to protection
features, the chip includes a general purpose accelerator to enhance the performance of
selected industry standard cryptographic algorithms.
The following is an introduction to the chip security components.
• Cryptographic module with AES 128/256 symmetric algorithms, random number
generator entropy source and NIST-validated DRBG, cryptographic key protection,
run-time integrity checking.
• High Assurance Boot (HAB) feature in the System Boot up to RSA-4096 signature
verification
• Secure Non Volatile Storage (SNVS)
• TrustZone (TZ) Architecture in the ARM Cortex A9 Platform, TrustZone aware
Interrupt Controller (GIC) and TrustZone Watchdog Timer (WDOG-2)
• TrustZone Address Space Controller (TZC-380) - providing security address region
control functions on DDR memory space.
• On-chip RAM (OCRAM) with TrustZone protection using OCRAM controller.
• 16 Kbyte of on-chip Secure RAM
• On chip OTP (OCOTP) with on-chip electrical fuses
• Central Security Unit (CSU)
• Secure JTAG Controller (SJC)
• Locked mode in the Smart Direct Memory Access (SDMA) controller
• For DTCP (Digital Transmission Content Protection) adopters, DTCP functionality
to support DTCP-MOST and DTCP-IP.
• 12 tamper pins supported
• Hardware Cryptographic Accelerators
• Symmetric: AES-128, AES-192, AES-256, DES, 3DES, and ARC4
• Hash Message Digest and HMAC: SHA-1, SHA-224, SHA-256, and MD-5
• True and Pseudo Random Number Generator
Detailed descriptions of the components are provided in the Multimedia Applications
Processor Security Reference Manual for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite.
11.2 Central Security Unit (CSU)

Chapter 11 System Security
11.2.1 CSU Overview

The CSU manages the system security policy for peripheral access on the SoC. The CSU
allows trusted code to set individual security access privilges on each of the peripherals,
using one of eight security access privilege levels. Also, according to programmed
policy, the CSU may assign bus master security privileges during bus transactions.
11.2.2 CSU Features

The Central Security Unit (CSU) sets access control policies between bus masters and
bus slaves, allowing peripherals to be separated into distinct security domains. This
protects against unauthorized access to data e.g. when software programs a DMA bus
master to access addresses that the software itself is prohibited from accessing directly.
Configuring DMA bus master privileges in the CSU consistent with software privileges
defends against such attempted accesses.
CSU has the following security related features:
• Peripheral access policy - Appropriate bus master privileges and identity are required
to access each peripheral.
• Masters privilege policy - CSU overrides bus master privilege signals, i.e. user/
supervisor secure/non-secure, according to access control policy.
11.2.3 CSU Functional Description

The CSU enables secure software to set bus privilege security policy within the platform.
Security policies may be set, and optionally locked in the CSU registers. These privilege
values may originate in the command sequence file (CSF) which is processed by the High
Assurance Boot (HAB) itself or by an HAB authenticated image which executes after the
initial boot ROM phase.
11.2.3.1 CSU Peripheral Access Policy

According to its programmed policy, the CSU determines the bus master privileges and
the masters that are allowed to access each of the slave peripherals.

Cryptographic Acceleration and Assurance Module (CAAM)
There are four security modes of operation (i.e. bus privileges) in the system
distinguished by security (TrustZone/non-TrustZone) and privilege (Supervisor/User)
setting of the module. Below is the list of these security modes from the highest security
level to the lowest:
• TrustZone (Secure) Privilege (Supervisor) Mode - Highest Security Level
• TrustZone (Secure) non-Privilege (User) Mode - Medium Security Level
• non-TrustZone (Regular) Privilege (Supervisor) Mode - Medium Security Level
• non-TrustZone (Regular) non-Privilege (User) Mode - Lowest Security Level
This functionality is implemented as follows:
The Configure Slave Level (CSL) Register value for a specified peripheral resource
defines the output signal -- csu_sec_level for that peripheral. The value of this signal
determines by what master privileges a peripheral is accessible. The relationship between
the value of the csu_sec_level signal and security operation mode is shown in the table
below. The CSL registers reside in the CSU module. Details, describing CSL register
fields and how they are programmed to control access privileges for specific peripherals,
can be found in the Security Reference Manual.
Table 11-1. Permission Access Table
CSU_SEC_LEVEL[2: Non-Secure Non-Secure Secure (TZ) User Secure (TZ) Spvr CSL register
0] User Mode Spvr Mode Mode Mode value
(0) 000 RD+WR RD+WR RD+WR RD+WR 8'b1111_1111
(1) 001 None RD+WR RD+WR RD+WR 8'b1011_1011
(2) 010 RD RD RD+WR RD+WR 8'b0011_1111
(3) 011 None RD RD+WR RD+WR 8'b0011_1011
(4) 100 None None RD+WR RD+WR 8'b0011_0011
(5) 101 None None None RD+WR 8'b0010_0010
(6) 110 None None RD RD 8'b0000_0011
(7) 111 None None None None Any other value
11.3 Cryptographic Acceleration and Assurance Module

(CAAM)

11.3.1 CAAM Overview

CAAM is a cryptographic acceleration device that accelerates block encryption
algorithms, stream cipher algorithms, hashing algorithms, and random number
generation. It has an integral DMA engine that allows CAAM to fetch its command
programs, read input data and write the resulting output.
CAAM works with the SNVS to provide platform assurance features, including support
for High Assurance Boot, detection of and response to potential tamper events, and
shortterm and long-term protection of secret data such as public keypairs, Digital Rights
Management keys and proprietary software.
CAAM provides the following features:
• Cryptographic acceleration of hashing, encryption and decryption
• Offloading of cryptographic functions via programmable command descriptor
language
• Two independent queues for commands and results
• Register Bus Interface used for configuration, control and status
• DMA, including scatter/gather support for data
• Automatic short-term encryption/decryption of cryptographic keys
• Long-term protection of secret data via device-specific encryption keys
• Secure Memory for access-controlled protection of critical data, and automatic
zeroization in the case of tampering
• Random Number Generation using a true random number generator and a
NISTcompliant pseudo random number generator
11.4 Secure Non-Volatile Storage (SNVS)
11.4.1 SNVS Overview

SNVS is a hardware device that includes a security state machine and security violation
detection circuits that, together with High Assurance Boot software, determine whether
the chip is currently in a secure state.
When the security state machine indicates a secure state, the SNVS allows CAAM use of
special cryptographic keys to decrypt long-term secrets such as public/private keypairs,
Digital Rights Management keys and proprietary software. When the SNVS detects a

Data Co-Processor (DCP)
potential security violation, such as a tamper alert, the SNVS signals CAAM to erase
sensitive data such as cryptographic keys, and sends an interrupt to alert the Operating
System of the event. The SNVS also includes a general purpose real-time counter.
The SNVS includes the following features:
• Security State Machine driven by High Assurance Boot software and tamper
detection circuits
• Master Key Control that protects the integrity and secrecy of the Master Key
(OTPMK) stored in fuses
• Tamper detection circuits that detect JTAG events, power glitches, Master Key ECC
check failure, and software-reported and hardware-reported security violations
• 256-bit Zeroizable Master Key that can be automatically erased in the event of a
security breach
• Tamper-protected Secure Realtime Counter that continues running when the chip is
powered off
• Non-volatile Monotonic Counter used to protect against “roll-back” attacks
• Non-volatile General Purpose Register can be used to store a 32-bit value across
power cycles
• Non-Secure Real Time Counter with programmable alarm and periodic interrupt
11.4.2 Tamper Detection

Tamper Detection is a special mechanism provided through a chip pin to signal when the
device encounters unauthorized opening or tampering.
When not in use, the Tamper Detection signal is pulled-down internally. In case of use, it
should be connected to a Tamper Detection contact in a target system (Normally closed,
pulled-up to the VDD_SNVS_IN).
An always-ON power supply (coincell battery) should be present in the system. If the
tamper detection feature is enabled by software then opening of the tamper contact:
• Switches system power ON with a Tamper Detection alarm interrupt asserted (for
software reaction)
• Activate security related hardware (e.g. automatic and immediate erasure of the
Zeroizable Master Key and deny access and erase secure memory contents)

11.5 Data Co-Processor (DCP)

For security purposes, the Data Co-Processor (DCP) provides hardware acceleration for
the cryptographic algorithms. The features of DCP are:
• Encryption Algorithms: AES-128 (ECB and CBC modes)
• Hashing Algorithms: SHA-1 and SHA-256
• Key selection from the SNVS, DCP internal key storage, or general memory
• Internal Memory for storing up to four AES-128 keys—when a key is written to a
key slot it can be read only by the DCP AES-128 engine
• IP slave interface
• DMA
11.6 High-Assurance Boot (HAB)

The HAB, which is the high-assurance boot feature in the system boot ROM, detects and
prevents the execution of unauthorized software (malware) during the boot sequence.
When the unauthorized software is permitted to gain control of the boot sequence, it can
be used for a variety of goals, such as exposing stored secrets; circumventing access
controls to sensitive data, services, or networks, or for repurposing the platform. The
unauthorized software can enter the platform during upgrades or reprovisioning, or when
booting from the USB connections or removable devices.
The HAB protects against unauthorized software by:
• Using digital signatures to recognize the authentic software. This enables you to boot
the device to a known initial state and run the software signed by the device
manufacturer.
11.7 System JTAG Controller (SJC)

The JTAG port provides debug access to hardware blocks, including the Arm processor
and the system bus. This enables program control and manipulation as well as visibility
to the chip peripherals and memory.
The JTAG port must be accessible during initial platform development, manufacturing
tests, and general troubleshooting. Given its capabilities, JTAG manipulation is a known
attack vector for accessing sensitive data and gaining control over software execution.

System JTAG Controller (SJC)
The System JTAG Controller (SJC) protects against the whole range of attacks based on
unauthorized JTAG manipulation. It also provides a JTAG port that conforms to the
IEEE 1149.1 and IEEE 1149.6 (AC) standards for BSR (boundary-scan) testing.
The SJC provides these security levels:
• The JTAG Disabled-JTAG use is permanently blocked.
• The No-Debug-All security sensitive JTAG features are permanently blocked.
• The Secure JTAG-JTAG use is restricted (as in the No-Debug level) unless a secret-
key challenge/response protocol is successfully executed.
• The JTAG Enabled-JTAG use is unrestricted.
The security levels are selected via the e-fuse configuration.
NOTE
For the final production hardware, the most secure and
preferred method is to ensure that the JTAG interface is not
pinned or routed out at all. The same applies to any other trace,
diagnostic or test ports including SDP.

Chapter 12
ARM Cortex A9 MPCore Platform (ARM)
12.1 Overview
The Cortex-A9 Core Platform consists of an ARM®Cortex®-A9 MPCore processor,
which includes a NEON co-processor, a private timer and watch-dog, and 32 KB + 32
KB L1 data and instruction caches per core.
The Cortex-A9 Core Platform consists of a unified 1 MB L2 cache, SCU (Snoop Control
Unit), and Generic Interrupt Controller (GIC). In addition, the Cortex-A9 Core Platform
includes various components composing the ARM CoreSight debug/Trace system,
including PTM and a 3 / 51 x CTI, 2xCTM, and 16KB ETB.
The Cortex-A9 processor utilizes two AXI-64 master ports connected from the SCU to
the Level 2 Cache. The L2 cache also utilizes 2x AXI-64 to access the L3 memory or
other SoC peripherals in a symmetric way.
The core supports debug through real-time trace via PTM, and static debug via JTAG.
The core platform supports static debug through the debug logic to SOC. This includes
the capability of real time trace via ARM's CoreSight PTM, ETB and TPIU modules. The
CTI and CTM modules allow cross-triggering of internal and external trigger sources.
12.2 External Signals

The following table describes the external signals of ARM:
Table 12-1. ARM External Signals
Signal Description Pad Mode Direction
ARM_EVENTI Input event signal GPIO_5 ALT7 I
1. Depending on specific part: i.MX 6Dual, i.MX 6Quad.

Platform configuration
Table 12-1. ARM External Signals (continued)

ARM_EVENTO Output event signal CSI0_PIXCLK ALT7 O
ARM_TRACE00 Trace signal CSI0_VSYNC ALT7 O
ARM_TRACE01 Trace signal CSI0_DAT4 ALT7 O
ARM_TRACE_CLK Clock signal CSI0_DATA_EN ALT7 O

ARM_TRACE_CTL Control signal CSI0_MCLK ALT7 O
12.3 Platform configuration

The Bus, Cortex A9 Core, and L2 Cache configuration options are contained in the
following subsections.
Table 12-2. Cortex-A9 revision
Core MP004-BU-50000-r2p10-0rel0
NEON AT397-BU-50001- r2p0-00rel0
PL310 PL310-BU-00000-r3p1-50rel0

Chapter 12 ARM Cortex A9 MPCore Platform (ARM)
12.3.1 Platform and SCU configuration

Table 12-3. Cortex-A9 configuration
Option Selected Value Comments
MP_MODE Yes Multi-Processor mode
POWER_DOMAIN_WRAPPER No Wrappers to support power off of individual cores.
PTM_INTERFACE_PRESENT Yes Use PTM as part of Trace/Debug logic.
PARITY Yes Using RAM arrays which support parity.
CORE_NUM 4/21 Number of cores
INT_NUM 128 Number of interrupts (SPIs) in GIC
ACP_PRESENT No Accelerator Coherency Port (ACP)
MASTER_NUM 2 Number of 64-bit AXI output master ports.
1. Depending on type of part - i.MX 6Dual, i.MX 6Quad.
12.3.2 Core configuration

Table 12-4. Cortex-A9 Core configuration
DCACHESIZE 32 L1 Data cache size
ICACHESIZE 32 L1 Instruction cache size
TLBSIZE 128
JAZELLE_PRESENT Yes Providing ARM's Jazelle technology hardware
extensions.
FPU_PRESENT No The FPU functions are provided by NEON, thus
additional FPU cannot be used.
NEON_PRESENT Yes Use MPE, NEON Co-Processor and FPU
PRELOAD_ENGINE_PRESENT No May only be beneficial in Video processing.
12.3.3 PL310 L2 Cache configuration

Table 12-5. PL310 L2 Cache configuration
Cache way size 64 KB (For total of 1 MB L2 size)
Number of cache ways 16 Performance enhancement versus 8 ways
RAM latencies 4
Data RAM banking Yes Significantly improves cache throughput

Performance and Power
Table 12-5. PL310 L2 Cache configuration (continued)

Slave port 1 present Yes
Master port 1 present Yes
Parity logic Yes For military / surveillance applications, and side ease the process of
identify memory related issues.
Lockdown by master Yes Increase L2 optimization
Lockdown by line Yes Increase L2 optimization
AXI ID width 5
Address filtering No Help in timing closure, not required for symmetric AXI bus connectivity
scheme.
Speculative read Yes Performance boost, when used with CortexA9.
Size of L2 cache 1 MB Size is implied by Cache-Size times cache-ways (i.e. 1 MB)
12.3.4 Endian Modes

The Cortex-A9 Core Platform supports little endian mode only. Big Endian is not
supported even though both modes are supported by the Cortex-A9 processor.
12.3.5 Memory Parity error support

The i.MX 6Dual/6Quad ARM Cortex A9 MPCore ™ platform supports Parity Fail signals
for several of the RAM arrays.
Parity fail indication is provided by "PARITYFAILn[7:0]" and "PARITYFAILSCU[N:
0]" buses for system notification. On parity error event, these signals will be ORed
together to provide a single event (interrupt) to the core, in case of any parity fail event.
12.4 Performance and Power

This section will discuss the operational conditions and performance goals for the Cortex-
A9 Core Platform.
12.4.1 Low-Power design

The Cortex-A9 Core Platform low-power design is based on these characteristics:
• Symmetric processing and ARM design by using the same clock frequency on cores
• Low leakage of LP process

• C4 package
As a result, the proposed power modes and power management scheme is as follows:
• The same voltage level must be used for the logic part of the whole platform.
• Separate voltage for L1 memories array is required to allow DVFS.
• On-chip power switches are not utilized by gating the power of the platform directly
from the regulator.
12.4.1.1 SRPG (State Retention Power Gating)

ARM core SRPG is implemented by software save & restore of essential configuration
registers prior to the complete power-down of the entire ARM platform.
Save & restore utilizes "Dormant mode" for the primary core (L1 cache flushed, L2
preserved), and power down mode of all other cores, as follows:
Power Down flow, 2
• Power down request
• Save core's essential registers and platform registers to L2/DDR memory by Dormant
mode routines.
• Perform L1 cache clean operation on all cores
• Enter WFI state
• Power Gating of all cores' and platform logic
Power Up flow2
• Power up request to GPC external controller (interrupt)
• Supply power
• Reset
• Restore registers of platform and cores from memory by Dormant mode routines.
12.4.1.2 Dynamic Voltage and Frequency Scaling (DVFS)

The Cortex-A9 Core Platform has been designed, in conjunction with external control
logic and software, to support dynamic scaling of voltage and frequency.
12.4.2 Clocks, frequency goals

2. Dormant mode implementation information, provided by ARM, is preliminary.

Core Platform Sub-Blocks details
12.4.2.1 ARM Clock

For ARM clock please see the product data sheet.
12.4.2.2 Bus Clocks

The AXI master ports are designed to run at half the frequency of the Cortex A9 core
clock.
The on-platform debug components clock is asynchronous to the ARM core clock.
12.4.2.3 Debug Clocks

The ARM platform contains several debug components that use different internal clock
names, but are all derived from the same ahb_clk clock root. These clocks, listed with
their default values, are as follows.
• Trace buffer (ETB) clock - 133 MHz
• Trace port (TPIU) clock - 133 MHz
• AHB clock - 133 MHz
12.5 Core Platform Sub-Blocks details
12.5.1 ARM Cortex A9 MPCore ™ Processor

The information presented in this section focuses on design aspects of the ARM Cortex
A9 MPCore ™ in the AP subsystem.
The ARM Cortex A9 is a high-performance, low-power, synthesisable processor with an
L1 cache subsystem that provides full virtual memory capabilities. The Cortex A9
processor implements the ARMv7-A architecture and runs 32-bit ARM instructions, 16-
bit and 32-bit Thumb2 instructions, and 8-bit Java™ byte-codes in Jazelle state.
The ARM Cortex A9 MPCore ™ processor in the chip consists of:
• Four (4) Cortex A9 processors in a cluster and a Snoop Control Unit (SCU) that can
be used to ensure coherency within the cluster.

• A set of private memory-mapped peripherals, including a global timer and a

watchdog and private timer for each Cortex-A9 processor present in the cluster.
• An integrated Interrupt Controller is an implementation of the Generic Interrupt
Controller architecture. The integrated Interrupt Controller registers sit beside the
timers and watchdog control registers in the private memory region of the Cortex-A9
MPCore.
Individual Cortex-A9 processors in the Cortex-A9 MPCore cluster are symmetrically
implemented with hardware configurations as specified in Platform configuration.
12.5.2 Media Processing Engine (MPE - NEON)

The Media Processing Engine (MPE) implements ARM NEON technology, a media and
signal processing architecture that adds instructions targeted at audio, video, 3-D
graphics, image, and speech processing.
Advanced SIMD instructions are available in both ARM and Thumb states. The MPE
also implements a VFPv3-D32 Floating-Point Unit.
The ARM Cortex A9 MPCore ™ Platform includes MPE per core.
12.5.3 Generic Interrupt Controller (GIC)

The Cortex-A9 MPCore contains an integrated interrupt controller that shares the same
programmer's model as the PL390 (GIC), although there are implementation-specific
differences.
12.5.3.1 Interrupt Controller Features

• 128 interrupt sources
• The Cortex-A9 multiprocessor contains the following types of interrupts:
• Up to 16 Software Generated Interrupts (SGIs)
• Private Peripheral Interrupt (PPI) - an interrupt generated by a peripheral that is
specific to a single Cortex-A9 processor (there are 5 PPIs for each Cortex-A9
processor interface)

Core Platform Sub-Blocks details
• Shared Peripheral Interrupt (SPI) - an interrupt generated by a peripheral which

the Interrupt Controller can route to any or all Cortex-A9 processor interfaces.
The Interrupt Controller supports a maximum of 224 SPIs (the i.MX 6Dual/
6Quad controller is configured for 128 interrupts).
• Lockable Shared Peripheral Interrupts (LSPI) - there are 31 LSPIs, interrupts
32-62. The user can configure and then lock these interrupts against further
change using CFGSDISABLE. The LSPIs are present only if the SPIs are
present.
For more informtation, see ARM MPCORE Technical Reference Manual.
12.5.3.2 About the Interrupt Controller

The Interrupt Controller is a single functional unit that is located in a Cortex-A9
multiprocessor design.
The Interrupt Controller is memory-mapped. The Cortex-A9 processors access it by using
a private interface through the SCU.
12.5.3.3 Interrupt Controller Clock frequency

The interrupt controller's clock period is 2x multiple of the main clock period.
The watchdogs and timers use the same clock as the interrupt controller.
12.5.3.4 TrustZone support

The Interrupt Controller permits all implemented interrupts to be individually defined as
Secure or Non-secure.
The user can program Secure interrupts to use either the IRQ or FIQ interrupt mechanism
of a Cortex-A9 processor through the FIQen bit in the ICPICR Register.
Non-secure interrupts are always signalled using the IRQ mechanism of a Cortex-A9
processor.
12.5.4 Instruction and data caches (L1)

The Cortex-A9 processor is configured with a 32 Kbyte Instruction Cache and a 32 Kbyte
Data Cache.

12.5.4.1 L1 features
• Four-way set associative cache
• Virtually indexed and physically addressed
• Capable of providing two words per cycle for all requesting sources
• Eight 32-bit words per cache line
• 128 indexes per tag RAM
12.5.5 L2 Cache and controller (PL310)

The ARM Cortex A9 MPCore ™ platform includes 1MB unified (data / instruction) L2
cache unit, based on the PL310 cache controller IP by ARM.
The Cortex-A9 processor utilizes 2x AXI-64 master ports connected from the SCU to the
Level 2 Cache. The L2 cache also utilizes 2x AXI-64 to access the L3 memory or other
SoC peripherals in a symmetric way.
See Table 12-5 for more information.
12.6 Debug and Trace Sub-blocks (CoreSight components)

This section gives a brief overview of the modules that are implemented within the
Cortex-A9 Core Platform.
The Cortex-A9 Core Platform debug blocks are part of the overall CoreSight debug
system which include the 16KB ETB, 2 x CTM's, 3 / 53 x CTI's, ATB replicator, DAP,
TPIU and APB address decode.
The CoreSight™ compatible Program Flow Trace Macrocell (PTM) provides control for
ARM software tracing and debug. The Cross Trigger Interface (CTI) is included in the
Cortex-A9 platform to provide a common programming model for use by the debug
tools, control the trigger sources, and interface to the Cross Trigger Matrix (CTM). The
debug is controlled via an ARM Debug Access Port (DAP).
For details of the full CoreSight debug subsystem, see the System Debug chapter.
3. Depending on specific part: i.MX 6Dual, i.MX 6Quad.

Debug and Trace Sub-blocks (CoreSight components)
12.6.1 Debug Access Port (DAP)

The Debug Access Port (DAP) is an implementation of an ARM Debug Interface version
5.1 (ADIv5.1) comprised of a number of components supplied in a single configuration.
All the supplied components fit into the various architectural components for Debug
Ports (DPs), which are used to access the DAP from an external debugger and Access
Ports (APs), to access on-chip system resources.
The debug port and access ports together are referred to as the DAP. The DAP provides
real-time access for the debugger without halting the processor to:
• AMBA system memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains of system components, (to
non-CoreSight compliant processors, for example).
12.6.2 Program Trace Macrocell (PTM)

The PTM unit is a nonintrusive trace macrocell that filters and compresses instruction
trace for use in system debugging and system profiling.
The PTM unit has an external interface outside of the processor called the Advanced
Trace Bus (ATB) interface. The PTM is an evolvement of the ETM, designed for the
Cortex A9 cores, handling program trace only.
The Cortex A9 PTM provides real time instruction trace for the Cortex A9. It's designed
to be used with the CoreSight Design Kit.
Real time tracing is controlled by specifying a set of filtering and triggering resources
which include address and data comparators, counters and sequencers.
Two main schemes can be used for connecting PTMs:
1. Single PTM - shared by all cores and resources.
2. Nx PTMs, where N is numbers of cores in the system.
12.6.2.1 Program Flow Trace (PFT)

The CoreSight Program Flow Trace Macrocell (PTM) is based on the Program Flow
Trace (PFT) architecture. The PTM generates information that trace tools use to
reconstruct the execution of all or part of a program.

The PFT architecture assumes the trace tools can access a copy of the code being traced.
For this reason, the PTM generates trace only at certain points in program execution,
called waypoints. This reduces the amount of trace data generated by the PTM compared
to the ETM protocol. Waypoints are changes in the program flow or events, such as an
exception. The trace tools use waypoints to follow the flow of program execution.
For full reconstruction of the program flow, the PTM traces:
• Indirect branches, with target address and condition code
• Direct branches with only the condition code
• Instruction barrier instructions
• Exceptions, with indication of where the exception occurred
• Changes in processor instruction set state
• Changes in processor security state
• Context-ID changes
• Entry to and return from Debug state when Halting Debug-mode is enabled
You can also configure the PTM to trace:
• Cycle count between traced waypoints
• Global system timestamps
• Target addresses for taken direct branches
PTM components include the following main components:
• Processor Interface to monitor the behavior of the processor.
• Trace Generation to create a real-time trace stream.
• Filtering and Triggering Resources used to affect when trace is generated and to
control the capturing of trace by the trace tools.
• Main FIFO (72 bytes) flattens out any bursts in the trace stream, and signals an
overflow in the trace when it becomes full, halting trace generation until the FIFO
empties.
• ATB interface for PTM output.
• APB interface to access the PTM registers.
12.6.3 Cross Trigger Interface (CTI)

This block controls the Trigger Interface (TI). The CTI combines and maps the trigger
requests, and broadcasts them to all other interfaces on the ECT as channel events.
When the CTI receives a channel event, it maps this onto a trigger output. This enables
subsystems to cross trigger with each other. The receiving and transmitting of triggers is
performed through the TI. Each CTI has 3/5 trigger inputs.
See System Debug for more information on the CTI.

Debug and Trace Sub-blocks (CoreSight components)
12.6.4 Embedded Trace Buffer (ETB)

The ETB provides on-chip storage of trace data using 32-bit, 16KB RAM.
The ETB accepts trace data from the Cortex-A9 PTM via an ATB port (passing through a
replicator in between). Providing an on-chip buffer alleviates the pin count, bandwidth,
and pad design requirements associated with sending trace data to a debugger directly
through package pins in near real-time.
Features:
• 16 KB compiled memory for the trace buffer and can be used as general purpose
memory
• AMBA Peripheral Bus programming interface for configuration and memory access
12.6.4.1 AMBA Trace Bus (ATB) Replicator

The ATB Replicator enables two trace sinks (ETB and an off platform port generally
connected to a Trace Port Interface Unit-TPIU) to be wired together and receive ATB
trace data from the same trace source (PTM).
There are no programmable registers. It takes incoming trace data from a single source
(PTM) and replicates it as multiple masters.

Chapter 13
AHB to IP Bridge (AIPSTZ)
13.1 Overview
This section provides an overview of the AHB to IP Bridge (AIPSTZ). This particular
peripheral is designed as the bridge between AHB bus and peripherals with the lower
bandwidth IP Slave (IPS) buses.
13.1.1 Features
The following list summarizes the key features of the bridge:
• The bridge supports the IPS slave bus signals. This interface is only meant for slave
peripherals.
• The bridge supports 8-, 16-, and 32-bit IPS peripherals. (Accesses larger than the size
of a peripheral are not supported, except to 32-bit memory.)
• The bridge supports a pair of IPS accesses for 64-bit and certain misaligned AHB
transfers to 32-bit memory in 64-bit platforms.
• The bridge directly supports up to 32 16-Kbyte external IPS peripherals, and 2 global
external IPS peripheral spaces. The bridge occupies 1 MBytes of total address space.
• The bridge provides configurable per-block and per-master access protections. More
details on the protection features and configuration can be found in the Security
Reference Manual
• Peripheral read transactions require a minimum of 2 hclk clocks, and unbuffered
write transactions require a minimum of 3 hclk clocks.
• The bridge uses one single asynchronous reset and one global clock.

Functional Description
13.2 Clocks
The following table describes the clock sources for AIPSTZ. Please see Clock Controller
Module (CCM) for clock setting, configuration and gating information.
Table 13-1. AIPSTZ Clocks
Clock name Clock Root Description
hclk ahb_clk_root Module clock
13.3 Functional Description

The AIPS bridge serves as a protocol translator between the AHB system bus and the IP
bus.
Support is provided for generating a pair of 32-bit IP bus accesses when targeted by a 64-
bit system bus access, or a misaligned access which crosses a 32-bit boundary. No other
bus-sizing access support is provided.
The AHB to IP bridge is the interface between the AHB and on-chip IPS peripherals,
which are sub-blocks containing readable/writable control and status registers.
The AHB master reads and writes these registers through the AIPSTZ. The bridge
generates block enables, the block address, transfer attributes, byte enables and write data
as inputs to the IPS peripherals. The bridge captures read data from the IPS interface and
drives it on the AHB.
Each bridge that connects to the IPS (or peripherals) are referred as AIPS. The chip has
several separate AIPS modules, and peripherals are grouped and assigned under each
AIPS block. The list of peripherals are indicated as n-1, ... and n-x for AIPS-1, ... and
AIPS-x respectively.
AIPS occupies a 1-Mbyte portion of the address space. The register maps of the IPS
peripherals are located on 16-Kbyte boundaries. Each IPS peripheral is allocated one 16-
Kbyte block of the memory map, and is activated by one of the block enables from the
bridge. Up to thirty-two 16-Kbyte external IPS peripherals may be implemented,
occupying contiguous blocks of 16-Kbytes. Two global external IPS block enables are
available for the remaining address space to allow for customization and expansion of
addressed peripheral devices. In addition, a single "non-global" block enable is also
asserted whenever any of the thirty-two non-global block enables is asserted.

Chapter 13 AHB to IP Bridge (AIPSTZ)
The bridge is responsible for indicating to IPS peripherals if an access is in supervisor or

user mode. It may block user mode accesses to certain IPS peripherals or it may allow the
individual IPS peripherals to determine if user mode accesses are allowed. In addition,
peripherals may be designated as write-protected.
The bridge supports the notion of "trusted" masters for security purposes. Masters may be
individually designated as trusted for reads, trusted for writes, or trusted for both reads
and writes, as well as being forced to look as though all accesses from a master are in
user-mode privilege level. Refer to AIPSTZ Memory Map/Register Definition for more
information.
All peripheral devices are expected to only require aligned accesses equal to or smaller in
size than the peripheral size. An exception to this rule is supported for 32-bit peripherals
to allow memory to be placed on the IPS.
13.4 Access Protections

The AIPSTZ bridge provides programmable access protections for both masters and
peripherals. It allows the privilege level of a master to be overridden, forcing it to user-
mode privilege, and allows masters to be designated as trusted or untrusted.
Peripherals may require supervisor privilege level for access, may restrict access to a
trusted master only, and may be write-protected. IP bus peripherals are subject to access
control policies set in both CSU registers and AIPSTZ registers. An access is blocked if it
is denied by either policy.
13.5 Access Support

Aligned 64-bit accesses, aligned and misaligned word and half word accesses, as well as
byte accesses are supported for 32-bit peripherals. Misaligned accesses are supported to
allow memory to be placed on the IPS.
Peripheral registers must not be misaligned, although no explicit checking is performed
by the AIPS bridge. The bridge will perform two IPS transfers for 64-bit accesses, word
accesses with byte offsets of 1, 2, or 3, and for half word accesses with a byte offset of 3.
All other accesses will be performed with a single IPS transfer.
Only aligned half word and byte accesses are supported for 16-bit peripherals. All other
accesses types are unsupported, and results of such accesses are undefined. They are not
terminated with an error response.

Initialization Information
Only byte accesses are supported for 8-bit peripherals. All other accesses types are
unsupported, and results of such accesses are undefined. They are not terminated with an
error response.
13.6 Initialization Information

The AIPS bridge should be programmed before use.
The following registers should be initialized: The Master Privilege Registers
(AIPSTZ_MPRs), the Peripheral Access Control registers (AIPSTZ_PACRs), and the
Off-platform Peripheral Access Control registers (AIPSTZ_OPACRs) described in
AIPSTZ Memory Map/Register Definition.
13.6.1 Security Block

The AIPSTZ contains a security block that is connected to each off-platform peripheral.
This block filters accesses based on write/read, non-secure, and supervisor signals.
Each peripheral can be individually configured to allow or deny each of the following
transactions as described in the table below:
Table 13-2. Peripheral Access Configuration options
Config Bit Write Non-Secure Supervisor Meaning
0 0 0 0 Secure User Read
1 0 0 1 Secure Supervisor Read
2 0 1 0 Non-Secure User Read
3 0 1 1 Non-Secure Supervisor Read
4 1 0 0 Secure User Write
5 1 0 1 Secure Supervisor Write
6 1 1 0 Non-Secure User Write
7 1 1 1 Non-Secure Supervisor Write
Each peripheral has a security configuration (sec_config_X) input for determining

whether to allow or deny a given access type. These are 8-bit vectors, with each bit
corresponding to one of the transactions above as listed in the Config Bit column of
Table 13-2. If the bit is asserted (1'b1), the transaction is allowed. If the bit is negated
(1'b0), the transaction is not allowed.
For example, if peripheral 0 is configured as follows:
sec_config_0 [7:0] = 8'b0011_0011

This peripheral can only be accessed by secure transactions. Bits 0, 1, 4, and 5 are
asserted and these bits refer to the four types of secure transactions. If an insecure
transaction is attempted to this peripheral, it will result in an error.
Eight bits per peripheral across an entire system can result in a large number of
configuration bits that must be assigned and controlled, most likely in a series of registers
in another block. To reduce the number of register bits required predefined sets of
security profiles can be defined and encapsulated in an external security translation block.
The table below describes one set of security profiles that has been proposed for use with
the AIPSTZ.
Table 13-3. Security Levels
CSU_SEC_LEVEL Non-Secure User Non-Secure Secure User Secure Supervisor
Supervisor
0 RD+WR RD+WR RD+WR RD+WR
1 NOT ALLOWED RD+WR RD+WR RD+WR
2 Read Only Read Only RD+WR RD+WR
3 NOT ALLOWED Read Only RD+WR RD+WR
4 NOT ALLOWED NOT ALLOWED RD+WR RD+WR
5 NOT ALLOWED NOT ALLOWED NOT ALLOWED RD+WR
6 NOT ALLOWED NOT ALLOWED Read Only Read Only
7 NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED
Information regarding CSU is provided in the Security Reference Manual. Contact your
NXP representative for information about obtaining this document.
A 3-bit input, 8-bit output translation block can be used such that only three register bits
are required to set the security profile and the translation block will drive the correct 8-bit
configuration vector. Each peripheral connected to the AIPSTZ would require this
translation block. The top level AIPSTZ has this three bit input line `csu_sec_level[2:0]'
corresponding to each peripheral X.
13.7 Off-Platform Peripherals Index

The off-platform peripherals index allocation is shown in the following table.
Table 13-4. External IPS Peripherals
OPAC ID AIPSTZ1 AIPSTZ2
OPAC31 Reserved Reserved
OPAC30 Reserved Reserved

Off-Platform Peripherals Index
Table 13-4. External IPS Peripherals (continued)

OPAC29 Reserved UART5
OPAC28 Reserved UART4
OPAC27 SDMA UART3
OPAC26 DCIC2 UART2
OPAC25 DCIC1 VDOA
OPAC24 IOMUXC MIPI (DSI port)
OPAC23 PGC_ARM, PGC_PU, GPC MIPI (CSI port)
OPAC22 SRC AUDMUX
OPAC21 EPIT2 TZASC2
OPAC20 EPIT1 TZASC1
OPAC19 SNVS_HP Perfmon3
OPAC18 USBPHY2, USBPHY1, ANALOG: (PLLs, Perfmon2
PFDs, Regulators, LDOs, Temp Sensor)
OPAC17 CCM Perfmon1
OPAC16 WDOG2 CSU
OPAC15 WDOG1 OCOTP_CTRL
OPAC14 KPP EIM
OPAC13 GPIO7 gcr_1
OPAC12 GPIO6 gcr_0
OPAC11 GPIO5 ROMCP
OPAC10 GPIO4 I2C3
OPAC9 GPIO3 I2C2
OPAC8 GPIO2 I2C1
OPAC7 GPIO1 uSDHC4
OPAC6 GPT uSDHC3
OPAC5 CAN2 uSDHC2
OPAC4 CAN1 uSDHC1
OPAC3 PWM4 MLB150
OPAC2 PWM3 ENET
OPAC1 PWM2 USBOH3 (USB)
OPAC0 PWM1 USBOH3
Global external IPS peripheral
OPAC33 VPU ARM Cortex A9 MPCore Platform
OPAC32 SPBA Peripherals: ASRC, SSI3, SSI2, CAAM
SSI1, ESAI, UART1,eCSPI5, eCSPI4,
eCSPI3, eCSPI2, eCSPI1, SPDIF,
SDMA internal registers

Table 13-5. External IPS Peripherals

OPAC ID AIPSTZ1 AIPSTZ2 AIPSTZ3 AIPSTZ4
OPAC31 Reserved QoSC Reserved Reserved
OPAC30 CSU Reserved ENET1 PLATFORM_CTRL
OPAC29 RDC PERFMON2 SDMA Reserved
OPAC28 SEMAPHORE2 PERFMON1 Reserved Reserved
OPAC27 SEMAPHORE1 Reserved QSPI MTR
OPAC26 GPC Reserved Reserved Reserved
OPAC25 SRC Reserved Reserved Reserved
OPAC24 CCM Reserved CSI2 TZASC
OPAC23 SNVS_HP Reserved MIPI_CSI_PHY2 Reserved
OPAC22 ANA_PLL Reserved MIPI_CSI2 Reserved
OPAC21 OCOTP_CTRL Reserved uSDHC2 Reserved
OPAC20 IOMUXC_GPR Reserved uSDHC1 Reserved
OPAC19 IOMUXC Reserved Reserved Reserved
OPAC18 LCDIF Reserved Reserved Reserved
OPAC17 ROMCP Reserved Reserved Reserved
OPAC16 Reserved GPT4 Reserved Reserved
OPAC15 GPT3 GPT5 Reserved Reserved
OPAC14 GPT2 GPT6 Reserved Reserved
OPAC13 GPT1 Reserved Reserved Reserved
OPAC12 SDMA2 System Counter_CTRL SEMAPHORE-HS Reserved
OPAC11 Reserved System Counter_CMP MU-B Reserved
OPAC10 WDOG3 System Counter_RD MU-A Reserved
OPAC9 WDOG2 PWM4 CSI1 Reserved
OPAC8 WDOG1 PWM3 MIPI_CSI_PHY1 Reserved
OPAC7 ANA_OSC PWM2 MIPI_CSI1 Reserved
OPAC6 ANA_TSENSOR PWM1 UART4 Reserved
OPAC5 Reserved Reserved I2C4 Reserved
OPAC4 GPIO5 Reserved I2C3 HDMI_SEC
OPAC3 GPIO4 Reserved I2C2 DC_MST3
OPAC2 GPIO3 Reserved I2C1 DC_MST2
OPAC1 GPIO2 Reserved MIPI_DSI DC_MST1
OPAC0 GPIO1 Reserved MIPI_PHY DC_MST0
Global external IPS peripheral
OPAC ID AIPSTZ1 AIPSTZ2 AIPSTZ3 AIPSTZ4
OPAC33 Reserved Reserved CAAM Reserved
OPAC32 SPBA2: SAI4, SAI5, Reserved SPBA1: SAI3, SAI2, HDMI_CTRL
SAI6, SAI2, SAI1 SPDIF2, UART2,
UART3, UART1,
eCSPI3, eCSPI2,
eCSPI1, SPDIF1.

AIPSTZ Memory Map/Register Definition
13.8 AIPSTZ Memory Map/Register Definition
The memory map for the AIPS SW-visible registers is shown in the table below.
The MPROT and OPACR fields are 4 bits in width. Some bits may be reserved
depending on device.
AIPSTZ memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
207_C000 Master Priviledge Registers (AIPSTZ1_MPR) 32 R/W 7700_0000h 13.8.1/398
Off-Platform Peripheral Access Control Registers
207_C040 32 R/W 4444_4444h 13.8.2/401
(AIPSTZ1_OPACR)
207_C044 32 R/W 4444_4444h 13.8.3/404
(AIPSTZ1_OPACR1)
207_C048 32 R/W 4444_4444h 13.8.4/407
(AIPSTZ1_OPACR2)
207_C04C 32 R/W 4444_4444h 13.8.5/410
(AIPSTZ1_OPACR3)
207_C050 32 R/W 4444_4444h 13.8.6/413
(AIPSTZ1_OPACR4)
217_C000 Master Priviledge Registers (AIPSTZ2_MPR) 32 R/W 7700_0000h 13.8.1/398
217_C040 32 R/W 4444_4444h 13.8.2/401
(AIPSTZ2_OPACR)
217_C044 32 R/W 4444_4444h 13.8.3/404
(AIPSTZ2_OPACR1)
217_C048 32 R/W 4444_4444h 13.8.4/407
(AIPSTZ2_OPACR2)
217_C04C 32 R/W 4444_4444h 13.8.5/410
(AIPSTZ2_OPACR3)
217_C050 32 R/W 4444_4444h 13.8.6/413
(AIPSTZ2_OPACR4)
13.8.1 Master Priviledge Registers (AIPSTZx_MPR)

Each AIPSTZ_MPR specifies 16 4-bit fields defining the access privilege level
associated with a bus master in the platform, as well as specifying whether write accesses
from this master are bufferable shown in Table 13-6

The registers provide one field per bus master, where field 15 corresponds to master 15,
field 14 to master 14,... field 0 to master 0 (typically the processor core). The master
index allocation is shown in the table below.
Table 13-6. MPROT Field
Bit Field Description
3 MBW Master Buffer Writes - This bit determines whether the AIPSTZ is enabled to buffer writes
from this master.
2 MTR Master Trusted for Reads - This bit determines whether the master is trusted for read
accesses.
1 MTW Master Trusted for Writes - This bit determines whether the master is trusted for write
accesses.
0 MPL Master Privilege Level - This bit determines how the privilege level of the master is
determined.
NOTE
The reset value is set to 0000_0000_7700_0000, which makes
master 0 and master 1 (Arm CORE) the trusted masters.
Trusted software can change the settings after reset.
Table 13-7. Master Index Allocation
Master Index Master Name Comments
Master 0 All masters excluding Arm core, SDMA and CAAM Share the same number allocation.
Master 1 Arm CORE
Master 2 CAAM
Master 3 SDMA
Master 4-15 Reserved
Address: Base address + 0h offset

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
MPROT0 MPROT1 MPROT2 MPROT3 Reserved
Reset 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AIPSTZx_MPR field descriptions

Field Description
31–28 Master 0 Priviledge, Buffer, Read, Write Control
MPROT0
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.

AIPSTZx_MPR field descriptions (continued)

Field Description
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
MPROT1
MPROT2
19–16 Master 3 Priviledge, Buffer, Read, Write Control.
MPROT3
- This field is reserved.
Reserved

13.8.2 Off-Platform Peripheral Access Control Registers

(AIPSTZx_OPACR)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 13-8
Table 13-8. OPAC Field
Bit Field Description
3 BW Buffer Writes - This bit determines whether write accesses to this peripheral are allowed to
be buffered.1
2 SP Supervisor Protect - This bit determines whether the peripheral requires supervisor privilege
level for access.
1 WP Write Protect - This bit determines whether the peripheral allows write accesses.
0 TP Trusted Protect - This bit determines whether the peripheral allows accesses from an
untrusted master.
1. Buffered writes are not available for AIPSTZ. This bit should be set to '0'.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC0 OPAC1 OPAC2 OPAC3 OPAC4 OPAC5 OPAC6 OPAC7
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
AIPSTZx_OPACR field descriptions

Field Description
31–28 Off-platform Peripheral Access Control 0
OPAC0
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
OPAC1

AIPSTZx_OPACR field descriptions (continued)

Field Description
OPAC2
OPAC3
OPAC4


Field Description
OPAC5
OPAC6
OPAC7 Off-platform Peripheral Access Control 7



Field Description

(AIPSTZx_OPACR1)
block.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
AIPSTZx_OPACR1 field descriptions

Field Description
OPAC8

AIPSTZx_OPACR1 field descriptions (continued)

Field Description
OPAC9
OPAC10
OPAC11


Field Description
OPAC12
OPAC13
OPAC14


Field Description

(AIPSTZx_OPACR2)
block.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
OPAC16


Field Description
OPAC17
OPAC18
OPAC19


Field Description
OPAC20
OPAC21
OPAC22


Field Description

(AIPSTZx_OPACR3)
block.
Address: Base address + 4Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
OPAC24


Field Description
OPAC25
OPAC26
OPAC27


Field Description
OPAC28
OPAC29
OPAC30


Field Description

(AIPSTZx_OPACR4)
block.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC32 OPAC33 Reserved
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Field Description
OPAC32


Field Description
OPAC33
Reserved

Chapter 14
AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
14.1 Overview
The AHB-to-APBH bridge provides the chip with an inexpensive peripheral attachment
bus running on the AHB's HCLK. (The H in APBH denotes that the APBH is
synchronous to HCLK.)
As shown in the figure below, the AHB-to-APBH bridge includes the AHB-to-APB PIO
bridge for a memory-mapped I/O to the APB devices, as well as a central DMA facility
for devices on this bus and a vectored interrupt controller for the Arm core. Each one of
the APB peripherals, including the vectored interrupt controller, is documented in their
respective chapters.

Clocks
AHB
AHB Slave AHB Master
AHB-to-APBH DMA
APBH Master
AHB-to-APBH Bridge
GPMI1
APBH
.
.
.
.
.
GPMIn
Figure 14-1. AHB-to-APBH Bridge DMA Block Diagram
The DMA controller uses the APBH bus to transfer read and write data to and from each
peripheral. There is no separate DMA bus for these devices. Contention between the
DMA's use of the APBH bus and the AHB-to-APB bridge functions' use of the APBH is
mediated by an internal arbitration logic. For contention between these two units, the
DMA is favored and the AHB slave will report "not ready" through its HREADY output
until the bridge transfer can complete. The arbiter tracks repeated lockouts and inverts the
priority, guaranteeing the Arm platform every fourth transfer on the APB.
14.2 Clocks
The table found here describes the clock sources for APBH. Please see Clock Controller

Chapter 14 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
Table 14-1. APBH Clocks

hclk usdhc3_clk_root Module clock
14.3 APBH DMA

The DMA supports four channels of DMA services, as shown in the following table. The
shared DMA resource allows each independent channel to follow a simple chained
command list. Command chains are built up using the general structure, as shown in
Figure 14-2.
Table 14-2. APBH DMA channel assignments
APBH DMA Channel # Usage
0 GPMI0
1 GPMI1
2 GPMI2
3 GPMI3
A single command structure or channel command word specifies a number of operations

to be performed by the DMA in support of a given device. Thus, the Arm platform can
set up large units of work, chaining together many DMA channel command words, pass
them off to the DMA, and have no further concern for the device until the DMA
completion interrupt occurs. The goal is to have enough intelligence in the DMA and the
devices to keep the interrupt frequency from any device below 1 KHz (arrival intervals
longer than 1 ms).
A single command structure can issue 32-bit PIO write operations to key registers in the
associated device using the same APB bus and controls that it uses to write DMA data
bytes to the device. For example, this allows a chain of operations to be issued to the
GPMI controller to send NAND command bytes, address bytes, and data transfers where
the command and the address structure is completely under software control, but the
administration of that transfer is handled autonomously by the DMA. Each DMA
structure can have 0–15 PIO words appended to it. The CMDPIOWORDS field, if non-
zero, instructs the DMA engine to copy these words to the APB, beginning at the first
register address offset for the peripheral and incrementing the register offset each cycle.
The DMA master generates only normal read/write transfers to the APBH. It does not
generate set, clear, or toggle (SCT) transfers.

APBH DMA
After any requested PIO words have been transferred to the peripheral, the DMA
examines the two-bit command field in the channel command structure. Table 14-3
shows the four commands implemented by the DMA.
word 0 NEXTCMDADDR
CMDPIOWORDS
HALTONTERMINATE
WAIT4ENDCMD
NANDWAIT4READY
SEMAPHORE
IRQONCMPLT
NANDLOCK
COMMAND
CHAIN
XFER_COUNT
word 1
word 2 BUFFER ADDRESS
word 3-n PIOWORD
Figure 14-2. AHB-to-APBH Bridge DMA channel command structure
Table 14-3. APBH DMA commands

DMA Command Usage
00 NO_DMA_XFER. Perform any requested PIO word transfers, but terminate the command before any DMA
transfer.
01 DMA_WRITE. Perform any requested PIO word transfers, then perform a DMA transfer from the
peripheral for the specified number of bytes.
10 DMA_READ. Perform any requested PIO word transfers and then perform a DMA transfer to the
peripheral for the specified number of bytes.
11 DMA_SENSE. Perform any requested PIO word transfers, then perform a conditional branch to the next
chained device. Follow the NEXTCMD_ADDR pointer if the peripheral sense is false. Follow the
BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. This command becomes a no-
operation for any channel other than a GPMI channel.
DMA_WRITE operations copy data bytes to the system memory (on-chip RAM or
SDRAM) from the associated peripheral.
DMA_READ operations copy data bytes to the APB peripheral from the system memory.
The DMA engine contains a shared byte aligner that aligns bytes from system memory to
or from the peripherals. Peripherals always assume little-endian-aligned data arrives or
departs on their 32-bit APB. The DMA_READ transfer uses the BUFFER_ADDRESS
word in the command structure to point to the DMA data buffer to be read by the
DMA_READ command.

The NO_DMA_XFER command is used to write PIO words to a device without

performing any DMA data byte transfers. This command is useful in such applications as
activating the NAND devices CHECKSTATUS operation. The check status command
reads a status byte from the NAND device, performs an XOR and MASK against an
expected value supplied as part of the PIO transfer. Once the read check completes (see
NAND Read Status Polling Example), the NO_DMA_XFER command completes. The
result in the peripheral is that its sense line is driven by the results of the comparison. The
sense flip-flop is only updated by CHECKSTATUS for the device that is executed. At
some future point, the chain contains a DMA command structure with the fourth and final
command value, that is, the DMA_SENSE command.
As each DMA command completes, it triggers the DMA to load the next DMA command
structure in the chain. The normal flow list of DMA commands is found by following the
NEXTCMD_ADDR pointer in the DMA command structure. The DMA_SENSE
command uses the DMA buffer pointer word of the command structure to point to an
alternate DMA command structure chain or list. The DMA_SENSE command examines
the sense line of the associated peripheral. If the sense line is false, then the DMA follows
the standard list found whose next command is found from the pointer in the
NEXTCMD_ADDR word of the command structure. If the sense line is true, then the
DMA follows the alternate list whose next command is found from the pointer in the
DMA Buffer Pointer word of the DMA_SENSE command structure (see Figure 14-2).
The sense command ignores the CHAIN bit, so that both pointers must be valid when the
DMA comes to a sense command.
If the wait-for-end-command bit (WAIT4ENDCMD) is set in a command structure, the
DMA channel waits for the device to signal completion of a command by toggling the
endcmd signal before proceeding to load and execute the next command structure. Then,
if DECREMENT_SEMAPHORE is set, the semaphore is decremented after the end
command is seen.
A detailed bit-field view of the DMA command structure is shown in the following table,
which shows a field that specifies the number of bytes to be transferred by this DMA
command. The transfer-count mechanism is duplicated in the associated peripheral, either
as an implied or as a specified count in the peripheral.
Table 14-4. DMA channel command word in system memory
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
NEXT_COMMAND_ADDRESS

APBH DMA
Table 14-4. DMA channel command word in system memory (continued)
DECREMENT SEMAPHORE
HALTONTERMINATE
NANDwAIT4READY
IRQ_COMPLETE
WAIT4ENDCMD
NANDLOCK
COMMAND
Number PIO
CHAIN
Number DMA Bytes to Transfer Words to
Write
DMA Buffer or Alternate CCW

Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBH Bus
Figure 14-2 also shows the CHAIN bit in bit 2 of the second word of the command
structure. This bit is set to 1, if the NEXT_COMMAND_ADDRESS contains a pointer to
another DMA command structure. If a null pointer (0) is loaded into the
NEXT_COMMAND_ADDRESS, it is not detected by the DMA hardware. Only the
CHAIN bit indicates whether a valid list exists beyond the current structure.
If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA
before loading the next command is to set the interrupt-status bit corresponding to the
current channel. The sticky interrupt request bit in the DMA CSR remains set until
cleared by the software. It can be used to interrupt the Arm platform.
The NAND_LOCK bit is monitored by the DMA channel arbiter. Once a NAND channel
(from channel 0 to channel 3) succeeds in the arbiter with its NAND_LOCK bit set, then
the arbiter ignores the other NAND channels until a command is completed in which the
NAND_LOCK is not set. Notice that the semantic here is that the NAND_LOCK state is
to limit scheduling of a non-locked DMA. A DMA channel can go from unlocked to
locked in the arbiter at the beginning of a command when the NAND_LOCK bit is set.
When the last DMA command of an atomic sequence is completed, the lock should be
removed. To accomplish this, the last command does not have the NAND_LOCK bit. It
is still locked in the atomic state within the arbiter when the command starts, so that it is
the only NAND command that can be executed. At the end, it drops from the atomic state
within the arbiter.
The NAND_WAIT4READY bit also has a special use for GPMI channels (from channel
0 to channel 3), i.e., the NAND device channels. The GPMI peripheral supplies a sample
of the ready line from the NAND device. This ready value is used to hold off of a
command with this bit set until the ready line is asserted to 1. Once the arbiter sees a
command with a wait-for-ready set, it holds off that channel until ready is asserted.

Receiving an IRQ for HALTONTERMINATE (HOT) is a feature in the APBH DMA

descriptor that allows GPMI to signal to the DMA engine that an error has occurred. If a
command is stalled due to an error, a HOT signal is sent from the peripheral to the DMA
engine and causes an IRQ after terminating the DMA descriptor being executed.
Therefore, it is recommended that software use this signal as follows:
• Always set HALTONTERMINATE to 1 in a DMA descriptor. That way, if a
peripheral signals HOT, the transfer will end, leaving the peripheral block and the
DMA engine synchronized (but at the end of a command).
• When an IRQ from an APBH channel is received, and the IRQ is determined to be
due to an error (as opposed to an IRQONCOMPLETE interrupt) the software should:
• Reset the channel.
• Determine the error from error reporting in the peripheral block, then manage the
error in the peripheral that is attached to that channel in whatever appropriate
way exists for that device (software recovery, device reset, block reset, etc).
Each channel has an eight-bit counting semaphore that controls whether it is in the idle
state. When the semaphore is non-zero, the channel is ready to run, process commands
and perform DMA transfers. Whenever a command finishes its DMA transfer, it checks
the DECREMENT_SEMAPHORE bit. If set, it decrements the counting semaphore. If
the semaphore goes to 0 as a result, then the channel enters the idle state and remains
there until the semaphore is incremented by the software. When the semaphore goes to
non-zero and the channel is in its idle state, then it uses the value in the
APBH_CHn_NXTCMDAR register (next command address register) to fetch a pointer to
the next command to process.
NOTE
This is a double indirect case. This method allows the software
to append to a running command list under the protection of the
counting semaphore.
To start processing the first time, software creates the command list to be processed. It
writes the address of the first command into the APBH_CHn_NXTCMDAR register, and
then writes 1 to the counting semaphore in APBH_CHn_SEMA. The DMA channel loads
APBH_CHn_CURCMDAR register and then enters the normal state machine processing
for the next command. When the software writes a value to the counting semaphore, it is
added to the semaphore count by hardware, protecting the case where both hardware and
software are trying to change the semaphore on the same clock edge.
Software can examine the value of APBH_CHn_CURCMDAR at any time to determine
the location of the command structure currently being processed.

NAND Read Status Polling Example
14.4 NAND Read Status Polling Example

The following figure shows a more complicated scenario.
This subset of a NAND device workload shows that the first two command structures are
used during the data-write phase of an NAND device write operation (CLE and ALE
transfers omitted for clarity).
• After writing the data, one must wait until the NAND device status register indicates
that the write charge has been transferred. This is built into the workload using a
check status command in the NAND in a loop created from the next two DMA
command structures.
• The NO_DMA_TRANSFER command is shown here performing the read check,
followed by a DMA_SENSE command to branch the DMA command structure list,
based on the status of a bit in the external NAND device.

1 PIO, chaining, no DMA, Check

1 PIO, chaining, DMA read NAND status & set sense line
NEXTCMD_ADDR NEXTCMD_ADDR
512 1 0 0 1 10 0 1 0 0 1 00
BUFFER ADDRESS BUFFER ADDRESS
NAND0=write mode NAND0= check status
No PIO, chaining, no DMA,
conditional branch based
No PIO, chaining
on sense line
DMA read
512-Byte NEXTCMD_ADDR
NEXTCMD_ADDR
Data
Block 16 0 0 0 1 10 0 0 0 0 1 11
BUFFER ADDRESS BUFFER ADDRESS
16-Byte
Spare 1 PIO, chaining, DMA read
Area NEXTCMD_ADDR
512 1 0 0 1 10
BUFFER ADDRESS
NAND0=write mode
No PIO,IRQ,
no chaining,
DMA read
512-Byte
NEXTCMD_ADDR=0
Data
Block 16 0 0 1 0 10
BUFFER ADDRESS
16-Byte
Spare
Area
Figure 14-3. AHB-to-APBH Bridge DMA NAND Read Status Polling with DMA Sense
Command
The example in the above figure shows the workload continuing immediately to the next
NAND page transfer. However, one could perform a second sense operation to see if an
error has occurred after the write. One could then point the sense command alternate
branch at a NO_DMA_XFER command with the interrupt bit set. If the CHAIN bit is not

APBH Memory Map/Register Definition
set on this failure branch, then the Arm platform is interrupted immediately, and the
channel process is also immediately terminated in the presence of a workload-detected
NAND error bit.
Note that each word of the three-word DMA command structure corresponds to a PIO
register of the DMA that is accessible on the APBH bus. Normally, the DMA copies the
next command structure onto these registers for processing at the start of each command
by following the value of the pointer previously loaded into the NEXTCMD_ADDR
register.
To start DMA processing for the first command, initialize the PIO registers of the desired
channel, as follows:
• First, load the next command address register with a pointer to the first command to
be loaded.
• Then, write 1 to the counting semaphore register. This causes the DMA to schedule
the targeted channel for the DMA command structure load, just as if it had finished
its previous command.
14.5 APBH Memory Map/Register Definition
APBH Hardware Register Format Summary

APBH memory map
Absolute
Width Section/
(in bits) page
(hex)
AHB to APBH Bridge Control and Status Register 0
11_0000 32 R/W E000_0000h 14.5.1/430
(APBH_CTRL0)
11_0004 32 R/W E000_0000h 14.5.1/430
(APBH_CTRL0_SET)
11_0008 32 R/W E000_0000h 14.5.1/430
(APBH_CTRL0_CLR)
11_000C 32 R/W E000_0000h 14.5.1/430
(APBH_CTRL0_TOG)
11_0010 32 R/W 0000_0000h 14.5.2/431
(APBH_CTRL1)
11_0014 32 R/W 0000_0000h 14.5.2/431
(APBH_CTRL1_SET)
11_0018 32 R/W 0000_0000h 14.5.2/431
(APBH_CTRL1_CLR)

APBH memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
11_001C 32 R/W 0000_0000h 14.5.2/431
(APBH_CTRL1_TOG)
11_0020 32 R/W 0000_0000h 14.5.3/435
(APBH_CTRL2)
11_0024 32 R/W 0000_0000h 14.5.3/435
(APBH_CTRL2_SET)
11_0028 32 R/W 0000_0000h 14.5.3/435
(APBH_CTRL2_CLR)
11_002C 32 R/W 0000_0000h 14.5.3/435
(APBH_CTRL2_TOG)
AHB to APBH Bridge Channel Register
11_0030 32 R/W 0000_0000h 14.5.4/440
(APBH_CHANNEL_CTRL)
11_0034 32 R/W 0000_0000h 14.5.4/440
(APBH_CHANNEL_CTRL_SET)
11_0038 32 R/W 0000_0000h 14.5.4/440
(APBH_CHANNEL_CTRL_CLR)
11_003C 32 R/W 0000_0000h 14.5.4/440
(APBH_CHANNEL_CTRL_TOG)
AHB to APBH DMA Device Assignment Register
11_0040 32 R 0000_0000h 14.5.5/441
(APBH_DEVSEL)
11_0050 AHB to APBH DMA burst size (APBH_DMA_BURST_SIZE) 32 R/W 0055_5555h 14.5.6/442
11_0060 AHB to APBH DMA Debug Register (APBH_DEBUG) 32 R/W 0000_0000h 14.5.7/443
APBH DMA Channel n Current Command Address Register
11_0100 32 R 0000_0000h 14.5.8/444
(APBH_CH0_CURCMDAR)
APBH DMA Channel n Next Command Address Register
11_0110 32 R/W 0000_0000h 14.5.9/445
(APBH_CH0_NXTCMDAR)
APBH DMA Channel n Command Register
11_0120 32 R 0000_0000h 14.5.10/445
(APBH_CH0_CMD)
APBH DMA Channel n Buffer Address Register
11_0130 32 R 0000_0000h 14.5.11/447
(APBH_CH0_BAR)
APBH DMA Channel n Semaphore Register
11_0140 32 R/W 0000_0000h 14.5.12/448
(APBH_CH0_SEMA)
AHB to APBH DMA Channel n Debug Information
11_0150 32 R 00A0_0000h 14.5.13/449
(APBH_CH0_DEBUG1)
11_0160 32 R 0000_0000h 14.5.14/452
(APBH_CH0_DEBUG2)
11_0170 32 R 0000_0000h 14.5.8/444
(APBH_CH1_CURCMDAR)
11_0180 32 R/W 0000_0000h 14.5.9/445
(APBH_CH1_NXTCMDAR)
11_0190 32 R 0000_0000h 14.5.10/445
(APBH_CH1_CMD)
11_01A0 32 R 0000_0000h 14.5.11/447
(APBH_CH1_BAR)


Absolute
Width Section/
(in bits) page
(hex)
11_01B0 32 R/W 0000_0000h 14.5.12/448
(APBH_CH1_SEMA)
11_01C0 32 R 00A0_0000h 14.5.13/449
(APBH_CH1_DEBUG1)
11_01D0 32 R 0000_0000h 14.5.14/452
(APBH_CH1_DEBUG2)
11_01E0 32 R 0000_0000h 14.5.8/444
(APBH_CH2_CURCMDAR)
11_01F0 32 R/W 0000_0000h 14.5.9/445
(APBH_CH2_NXTCMDAR)
11_0200 32 R 0000_0000h 14.5.10/445
(APBH_CH2_CMD)
11_0210 32 R 0000_0000h 14.5.11/447
(APBH_CH2_BAR)
11_0220 32 R/W 0000_0000h 14.5.12/448
(APBH_CH2_SEMA)
11_0230 32 R 00A0_0000h 14.5.13/449
(APBH_CH2_DEBUG1)
11_0240 32 R 0000_0000h 14.5.14/452
(APBH_CH2_DEBUG2)
11_0250 32 R 0000_0000h 14.5.8/444
(APBH_CH3_CURCMDAR)
11_0260 32 R/W 0000_0000h 14.5.9/445
(APBH_CH3_NXTCMDAR)
11_0270 32 R 0000_0000h 14.5.10/445
(APBH_CH3_CMD)
11_0280 32 R 0000_0000h 14.5.11/447
(APBH_CH3_BAR)
11_0290 32 R/W 0000_0000h 14.5.12/448
(APBH_CH3_SEMA)
11_02A0 32 R 00A0_0000h 14.5.13/449
(APBH_CH3_DEBUG1)
11_02B0 32 R 0000_0000h 14.5.14/452
(APBH_CH3_DEBUG2)
11_02C0 32 R 0000_0000h 14.5.8/444
(APBH_CH4_CURCMDAR)
11_02D0 32 R/W 0000_0000h 14.5.9/445
(APBH_CH4_NXTCMDAR)
11_02E0 32 R 0000_0000h 14.5.10/445
(APBH_CH4_CMD)
11_02F0 32 R 0000_0000h 14.5.11/447
(APBH_CH4_BAR)
11_0300 32 R/W 0000_0000h 14.5.12/448
(APBH_CH4_SEMA)


Absolute
Width Section/
(in bits) page
(hex)
11_0310 32 R 00A0_0000h 14.5.13/449
(APBH_CH4_DEBUG1)
11_0320 32 R 0000_0000h 14.5.14/452
(APBH_CH4_DEBUG2)
11_0330 32 R 0000_0000h 14.5.8/444
(APBH_CH5_CURCMDAR)
11_0340 32 R/W 0000_0000h 14.5.9/445
(APBH_CH5_NXTCMDAR)
11_0350 32 R 0000_0000h 14.5.10/445
(APBH_CH5_CMD)
11_0360 32 R 0000_0000h 14.5.11/447
(APBH_CH5_BAR)
11_0370 32 R/W 0000_0000h 14.5.12/448
(APBH_CH5_SEMA)
11_0380 32 R 00A0_0000h 14.5.13/449
(APBH_CH5_DEBUG1)
11_0390 32 R 0000_0000h 14.5.14/452
(APBH_CH5_DEBUG2)
11_03A0 32 R 0000_0000h 14.5.8/444
(APBH_CH6_CURCMDAR)
11_03B0 32 R/W 0000_0000h 14.5.9/445
(APBH_CH6_NXTCMDAR)
11_03C0 32 R 0000_0000h 14.5.10/445
(APBH_CH6_CMD)
11_03D0 32 R 0000_0000h 14.5.11/447
(APBH_CH6_BAR)
11_03E0 32 R/W 0000_0000h 14.5.12/448
(APBH_CH6_SEMA)
11_03F0 32 R 00A0_0000h 14.5.13/449
(APBH_CH6_DEBUG1)
11_0400 32 R 0000_0000h 14.5.14/452
(APBH_CH6_DEBUG2)
11_0410 32 R 0000_0000h 14.5.8/444
(APBH_CH7_CURCMDAR)
11_0420 32 R/W 0000_0000h 14.5.9/445
(APBH_CH7_NXTCMDAR)
11_0430 32 R 0000_0000h 14.5.10/445
(APBH_CH7_CMD)
11_0440 32 R 0000_0000h 14.5.11/447
(APBH_CH7_BAR)
11_0450 32 R/W 0000_0000h 14.5.12/448
(APBH_CH7_SEMA)
11_0460 32 R 00A0_0000h 14.5.13/449
(APBH_CH7_DEBUG1)


Absolute
Width Section/
(in bits) page
(hex)
11_0470 32 R 0000_0000h 14.5.14/452
(APBH_CH7_DEBUG2)
11_0480 32 R 0000_0000h 14.5.8/444
(APBH_CH8_CURCMDAR)
11_0490 32 R/W 0000_0000h 14.5.9/445
(APBH_CH8_NXTCMDAR)
11_04A0 32 R 0000_0000h 14.5.10/445
(APBH_CH8_CMD)
11_04B0 32 R 0000_0000h 14.5.11/447
(APBH_CH8_BAR)
11_04C0 32 R/W 0000_0000h 14.5.12/448
(APBH_CH8_SEMA)
11_04D0 32 R 00A0_0000h 14.5.13/449
(APBH_CH8_DEBUG1)
11_04E0 32 R 0000_0000h 14.5.14/452
(APBH_CH8_DEBUG2)
11_04F0 32 R 0000_0000h 14.5.8/444
(APBH_CH9_CURCMDAR)
11_0500 32 R/W 0000_0000h 14.5.9/445
(APBH_CH9_NXTCMDAR)
11_0510 32 R 0000_0000h 14.5.10/445
(APBH_CH9_CMD)
11_0520 32 R 0000_0000h 14.5.11/447
(APBH_CH9_BAR)
11_0530 32 R/W 0000_0000h 14.5.12/448
(APBH_CH9_SEMA)
11_0540 32 R 00A0_0000h 14.5.13/449
(APBH_CH9_DEBUG1)
11_0550 32 R 0000_0000h 14.5.14/452
(APBH_CH9_DEBUG2)
11_0560 32 R 0000_0000h 14.5.8/444
(APBH_CH10_CURCMDAR)
11_0570 32 R/W 0000_0000h 14.5.9/445
(APBH_CH10_NXTCMDAR)
11_0580 32 R 0000_0000h 14.5.10/445
(APBH_CH10_CMD)
11_0590 32 R 0000_0000h 14.5.11/447
(APBH_CH10_BAR)
11_05A0 32 R/W 0000_0000h 14.5.12/448
(APBH_CH10_SEMA)
11_05B0 32 R 00A0_0000h 14.5.13/449
(APBH_CH10_DEBUG1)
11_05C0 32 R 0000_0000h 14.5.14/452
(APBH_CH10_DEBUG2)


Absolute
Width Section/
(in bits) page
(hex)
11_05D0 32 R 0000_0000h 14.5.8/444
11_05E0 32 R/W 0000_0000h 14.5.9/445
11_05F0 32 R 0000_0000h 14.5.10/445
(APBH_CH11_CMD)
11_0600 32 R 0000_0000h 14.5.11/447
(APBH_CH11_BAR)
11_0610 32 R/W 0000_0000h 14.5.12/448
(APBH_CH11_SEMA)
11_0620 32 R 00A0_0000h 14.5.13/449
(APBH_CH11_DEBUG1)
11_0630 32 R 0000_0000h 14.5.14/452
(APBH_CH11_DEBUG2)
11_0640 32 R 0000_0000h 14.5.8/444
11_0650 32 R/W 0000_0000h 14.5.9/445
11_0660 32 R 0000_0000h 14.5.10/445
(APBH_CH12_CMD)
11_0670 32 R 0000_0000h 14.5.11/447
(APBH_CH12_BAR)
11_0680 32 R/W 0000_0000h 14.5.12/448
(APBH_CH12_SEMA)
11_0690 32 R 00A0_0000h 14.5.13/449
(APBH_CH12_DEBUG1)
11_06A0 32 R 0000_0000h 14.5.14/452
(APBH_CH12_DEBUG2)
11_06B0 32 R 0000_0000h 14.5.8/444
11_06C0 32 R/W 0000_0000h 14.5.9/445
11_06D0 32 R 0000_0000h 14.5.10/445
(APBH_CH13_CMD)
11_06E0 32 R 0000_0000h 14.5.11/447
(APBH_CH13_BAR)
11_06F0 32 R/W 0000_0000h 14.5.12/448
(APBH_CH13_SEMA)
11_0700 32 R 00A0_0000h 14.5.13/449
(APBH_CH13_DEBUG1)
11_0710 32 R 0000_0000h 14.5.14/452
(APBH_CH13_DEBUG2)
11_0720 32 R 0000_0000h 14.5.8/444


Absolute
Width Section/
(in bits) page
(hex)
11_0730 32 R/W 0000_0000h 14.5.9/445
11_0740 32 R 0000_0000h 14.5.10/445
(APBH_CH14_CMD)
11_0750 32 R 0000_0000h 14.5.11/447
(APBH_CH14_BAR)
11_0760 32 R/W 0000_0000h 14.5.12/448
(APBH_CH14_SEMA)
11_0770 32 R 00A0_0000h 14.5.13/449
(APBH_CH14_DEBUG1)
11_0780 32 R 0000_0000h 14.5.14/452
(APBH_CH14_DEBUG2)
11_0790 32 R 0000_0000h 14.5.8/444
11_07A0 32 R/W 0000_0000h 14.5.9/445
11_07B0 32 R 0000_0000h 14.5.10/445
(APBH_CH15_CMD)
11_07C0 32 R 0000_0000h 14.5.11/447
(APBH_CH15_BAR)
11_07D0 32 R/W 0000_0000h 14.5.12/448
(APBH_CH15_SEMA)
11_07E0 32 R 00A0_0000h 14.5.13/449
(APBH_CH15_DEBUG1)
11_07F0 32 R 0000_0000h 14.5.14/452
(APBH_CH15_DEBUG2)
11_0800 APBH Bridge Version Register (APBH_VERSION) 32 R 0301_0000h 14.5.15/453
14.5.1 AHB to APBH Bridge Control and Status Register 0

(APBH_CTRL0n)
The APBH CTRL 0 provides overall control of the AHB to APBH bridge and DMA.
This register contains module softreset, clock gating, channel clock gating/freeze bits.
Address: 11_0000h base + 0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APB_BURST_EN
AHB_BURST8_
R
CLKGATE
SFTRST
EN
Reserved
W
Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKGATE_CHANNEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APBH_CTRL0n field descriptions

Field Description
31 Set this bit to zero to enable normal APBH DMA operation. Set this bit to one (default) to disable clocking
SFTRST with the APBH DMA and hold it in its reset (lowest power) state. This bit can be turned on and then off to
reset the APBH DMA block to its default state.
30 This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
CLKGATE
29 Set this bit to one (default) to enable AHB 8-beat burst. Set to zero to disable 8-beat burst on AHB
AHB_BURST8_ interface.
EN
28 Set this bit to one to enable apb master do a continous transfers when a device request a burst dma. Set
APB_BURST_EN to zero will treat a burst dma request as 4/8 individual requests.
27–16 This field is reserved.
RSVD0 Reserved, always set to zero.
CLKGATE_ These bits must be set to zero for normal operation of each channel. When set to one they gate off the
CHANNEL individual clocks to the channels.
0x0001 NAND0 —
0x0002 NAND1 —
0x0004 NAND2 —
0x0008 NAND3 —
0x0010 NAND4 —
0x0020 NAND5 —
0x0040 NAND6 —
0x0080 NAND7 —
0x0100 SSP —

(APBH_CTRL1n)
The APBH CTRL one provides overall control of the interrupts generated by the AHB to
APBH DMA. This register contains the per channel interrupt status bits and the per
channel interrupt enable bits. Each channel has a dedicated interrupt vector in the
vectored interrupt controller.
EXAMPLE
BF_WR(APBH_CTRL1, CH5_CMDCMPLT_IRQ, 0); // use bitfield write macro

BF_APBH_CTRL1.CH5_CMDCMPLT_IRQ = 0; // or, assign to register
struct's bitfield

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH9_CMDCMPLT_
CH8_CMDCMPLT_
CH7_CMDCMPLT_
CH6_CMDCMPLT_
CH5_CMDCMPLT_
CH4_CMDCMPLT_
CH3_CMDCMPLT_
CH2_CMDCMPLT_
CH1_CMDCMPLT_
CH0_CMDCMPLT_
CMDCMPLT_IRQ_
CMDCMPLT_IRQ_
CMDCMPLT_IRQ_
CMDCMPLT_IRQ_
CMDCMPLT_IRQ_
CMDCMPLT_IRQ_
R
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
IRQ_EN
CH15_
CH14_
CH13_
CH12_
CH11_
CH10_
EN
EN
EN
EN
EN
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH9_CMDCMPLT_
CH8_CMDCMPLT_
CH7_CMDCMPLT_
CH6_CMDCMPLT_
CH5_CMDCMPLT_
CH4_CMDCMPLT_
CH3_CMDCMPLT_
CH2_CMDCMPLT_
CH1_CMDCMPLT_
CH0_CMDCMPLT_
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
R
CH15_
CH14_
CH13_
CH12_
CH11_
CH10_
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 Setting this bit enables the generation of an interrupt request for APBH DMA channel 15.
CH15_
CMDCMPLT_
IRQ_EN
CH14_
CMDCMPLT_
IRQ_EN
CH13_
CMDCMPLT_
IRQ_EN
CH12_
CMDCMPLT_
IRQ_EN
CH11_
CMDCMPLT_
IRQ_EN
CH10_
CMDCMPLT_
IRQ_EN

APBH_CTRL1n field descriptions (continued)

Field Description
CH9_
CMDCMPLT_
IRQ_EN
CH8_
CMDCMPLT_
IRQ_EN
CH7_
CMDCMPLT_
IRQ_EN
CH6_
CMDCMPLT_
IRQ_EN
CH5_
CMDCMPLT_
IRQ_EN
CH4_
CMDCMPLT_
IRQ_EN
CH3_
CMDCMPLT_
IRQ_EN
CH2_
CMDCMPLT_
IRQ_EN
CH1_
CMDCMPLT_
IRQ_EN
CH0_
CMDCMPLT_
IRQ_EN
15 Interrupt request status bit for APBH DMA Channel 15. This sticky bit is set by DMA hardware and reset
CH15_ by software. It is ANDed with its corresponding enable bit to generate an interrupt.
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ


Field Description
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ
9 Interrupt request status bit for APBH DMA Channel 9. This sticky bit is set by DMA hardware and reset by
CH9_ software. It is ANDed with its corresponding enable bit to generate an interrupt.
CMDCMPLT_
IRQ
8 Interrupt request status bit for APBH DMA Channel 8. This sticky bit is set by DMA hardware and reset by
CMDCMPLT_
IRQ
7 Interrupt request status bit for APBH DMA channel 7. This sticky bit is set by DMA hardware and reset by
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ


Field Description
CMDCMPLT_
IRQ
CMDCMPLT_
IRQ

(APBH_CTRL2n)
The APBH CTRL 2 provides channel error interrupts generated by the AHB to APBH
DMA. This register contains the per channel interrupt status bits and the per channel
interrupt enable bits. Each channel has a dedicated interrupt vector in the vectored
interrupt controller.
EXAMPLE
BF_WR(APBH_CTRL1, CH5_CMDCMPLT_IRQ, 0); // use bitfield write macro

BF_APBH_CTRL1.CH5_CMDCMPLT_IRQ = 0; // or, assign to register
struct's bitfield


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH15_ERROR_STATUS
CH14_ERROR_STATUS
CH13_ERROR_STATUS
CH12_ERROR_STATUS
CH11_ERROR_STATUS
CH10_ERROR_STATUS
CH9_ERROR_STATUS
CH8_ERROR_STATUS
CH7_ERROR_STATUS
CH6_ERROR_STATUS
CH5_ERROR_STATUS
CH4_ERROR_STATUS
CH3_ERROR_STATUS
CH2_ERROR_STATUS
CH1_ERROR_STATUS
CH0_ERROR_STATUS
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CH15_ERROR_IRQ
CH14_ERROR_IRQ
CH13_ERROR_IRQ
CH12_ERROR_IRQ
CH11_ERROR_IRQ
CH10_ERROR_IRQ
CH9_ERROR_IRQ
CH8_ERROR_IRQ
CH7_ERROR_IRQ
CH6_ERROR_IRQ
CH5_ERROR_IRQ
CH4_ERROR_IRQ
CH3_ERROR_IRQ
CH2_ERROR_IRQ
CH1_ERROR_IRQ
CH0_ERROR_IRQ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31 Error status bit for APBH DMA Channel 15. Valid when corresponding Error IRQ is set.
CH15_ERROR_
1 - AHB bus error
STATUS

Field Description
0 - channel early termination.
0x0 TERMINATION — An early termination from the device causes error IRQ.
0x1 BUS_ERROR — An AHB bus error causes error IRQ.
CH14_ERROR_
1 - AHB bus error
STATUS
CH13_ERROR_
1 - AHB bus error
STATUS
CH12_ERROR_
1 - AHB bus error
STATUS
CH11_ERROR_
1 - AHB bus error
STATUS
CH10_ERROR_
1 - AHB bus error
STATUS
CH9_ERROR_
1 - AHB bus error
STATUS
CH8_ERROR_
1 - AHB bus error
STATUS


Field Description
23 Error status bit for APBX DMA Channel 7. Valid when corresponding Error IRQ is set.
CH7_ERROR_
1 - AHB bus error
STATUS
CH6_ERROR_
1 - AHB bus error
STATUS
CH5_ERROR_
1 - AHB bus error
STATUS
CH4_ERROR_
1 - AHB bus error
STATUS
CH3_ERROR_
1 - AHB bus error
STATUS
CH2_ERROR_
1 - AHB bus error
STATUS
CH1_ERROR_
1 - AHB bus error
STATUS


Field Description
CH0_ERROR_
1 - AHB bus error
STATUS
15 Error interrupt status bit for APBH DMA Channel 15. This sticky bit is set by DMA hardware and reset by
CH15_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to Arm.
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
7 Error interrupt status bit for APBX DMA Channel 7. This sticky bit is set by DMA hardware and reset by
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ


Field Description
IRQ
IRQ
14.5.4 AHB to APBH Bridge Channel Register

(APBH_CHANNEL_CTRLn)
The APBH CHANNEL CTRL provides reset/freeze control of each DMA channel. This
register contains individual channel reset/freeze bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
RESET_CHANNEL FREEZE_CHANNEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APBH_CHANNEL_CTRLn field descriptions

Field Description
31–16 Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset
RESET_ state. The bit is reset after the channel resources are cleared.
CHANNEL
0x0001 NAND0 —
0x0002 NAND1 —
0x0004 NAND2 —
0x0008 NAND3 —
0x0010 NAND4 —
0x0020 NAND5 —
0x0040 NAND6 —
0x0080 NAND7 —
0x0100 SSP —
FREEZE_ Setting a bit in this field will freeze the DMA channel associated with it. This field is a direct input to the
CHANNEL DMA channel arbiter. When frozen, the channel is deined access to the central DMA resources.
0x0001 NAND0 —
0x0002 NAND1 —
0x0004 NAND2 —
0x0008 NAND3 —
0x0010 NAND4 —
0x0020 NAND5 —
0x0040 NAND6 —

APBH_CHANNEL_CTRLn field descriptions (continued)

Field Description
0x0080 NAND7 —
0x0100 SSP —
14.5.5 AHB to APBH DMA Device Assignment Register

(APBH_DEVSEL)
This register allows reassignment of the APBH device connected to the DMA Channels.
In this chip, APBH DMA channel resource is enough for high speed peripherals, so this
register is of no use and reserved.
Address: 11_0000h base + 40h offset = 11_0040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APBH_DEVSEL field descriptions

Field Description
CH15 Reserved.
CH14 Reserved.
CH13 Reserved.
CH12 Reserved.
CH11 Reserved.
CH10 Reserved.
CH9 Reserved.
CH8 Reserved.
CH7 Reserved.
CH6 Reserved.

APBH_DEVSEL field descriptions (continued)

Field Description
CH5 Reserved.
CH4 Reserved.
CH3 Reserved.
CH2 Reserved.
CH1 Reserved.
CH0 This field is reserved.
Reserved.
14.5.6 AHB to APBH DMA burst size (APBH_DMA_BURST_SIZE)

This register programs the apbh burst size of the APBH DMA devices when a DMA
burst request is issued.
This register provides a mechanism for assigning the device.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved Reserved Reserved Reserved Reserved Reserved Reserved CH8
Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
Reset 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
APBH_DMA_BURST_SIZE field descriptions

Field Description
CH15 Reserved.
CH14 Reserved.
CH13 Reserved.
CH12 Reserved.
CH11 Reserved.

APBH_DMA_BURST_SIZE field descriptions (continued)

Field Description
CH10 Reserved.
CH9 Reserved.
17–16 DMA burst size for SSP.
CH8
0x0 BURST0 —
0x1 BURST4 —
0x2 BURST8 —
15–14 DMA burst size for GPMI channel 7. Do not change. GPMI only support burst size 4.
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0 DMA burst size for GPMI channel 0. Do not change. GPMI only support burst size 4.
14.5.7 AHB to APBH DMA Debug Register (APBH_DEBUG)

This register is for debug purpose.
The debug register is for internal use only. Not recommend for customer useage.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMI_ONE_
R
FIFO
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APBH_DEBUG field descriptions

Field Description
- Reserved, always set to zero.
0 Set to 0ne and the 8 GPMI channels will share the DMA FIFO, and when set to zero, the 8 GPMI channels
GPMI_ONE_ will use its own DMA FIFO.
FIFO
14.5.8 APBH DMA Channel n Current Command Address

Register (APBH_CHn_CURCMDAR)
The APBH DMA channel n current command address register points to the multiword
command that is currently being executed. Commands are threaded on the command
address.
APBH DMA Channel n is controlled by a variable sized command structure. This register
points to the command structure currently being executed.
EXAMPLE
pCurCmd = (apbh_chn_cmd_t *) APBH_CHn_CURCMDAR_RD(0); // read the whole

register, since there is only one field
pCurCmd = (apbh_chn_cmd_t *) BF_RDn(APBH_CHn_CURCMDAR, 0, CMD_ADDR); // or, use multi-
register bitfield read macro
pCurCmd = (apbh_chn_cmd_t *) APBH_CHn_CURCMDAR(0).CMD_ADDR; // or, assign from
bitfield of indexed register's struct
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMD_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APBH_CHn_CURCMDAR field descriptions

Field Description
CMD_ADDR Pointer to command structure currently being processed for channel n.

14.5.9 APBH DMA Channel n Next Command Address Register

(APBH_CHn_NXTCMDAR)
The APBH DMA Channel n Next Command Address register contains the address of the
next multiword command to be executed. Commands are threaded on the command
address. Set CHAIN to 1 in the DMA command word to process command lists.
APBH DMA Channel n is controlled by a variable sized command structure. Software
loads this register with the address of the first command structure to process and
increments the Channel n semaphore to start processing. This register points to the next
command structure to be executed when the current command is completed.
EXAMPLE
APBH_CHn_NXTCMDAR_WR(0, (reg32_t) pCommandTwoStructure); // write the entire

register, since there is only one field
BF_WRn(APBH_CHn_NXTCMDAR, 0, (reg32_t) pCommandTwoStructure); // or, use multi-
register bitfield write macro
APBH_CHn_NXTCMDAR(0).CMD_ADDR = (reg32_t) pCommandTwoStructure; // or, assign to bitfield
of indexed register's struct
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
CMD_ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APBH_CHn_NXTCMDAR field descriptions

Field Description
CMD_ADDR Pointer to next command structure for channel n.
14.5.10 APBH DMA Channel n Command Register

(APBH_CHn_CMD)
The APBH DMA Channel n command register specifies the DMA transaction to perform
for the current command chain item.
The command register controls the overall operation of each DMA command for this
channel. It includes the number of bytes to transfer to or from the device, the number of
APB PIO command words included with this command structure, whether to interrupt at
command completion, whether to chain an additional command to the end of this one and
whether this transfer is a read or write DMA transfer.

EXAMPLE
apbh_chn_cmd_t dma_cmd;
dma_cmd.XFER_COUNT = 512; // transfer 512 bytes
dma_cmd.COMMAND = BV_APBH_CHn_CMD_COMMAND__DMA_WRITE; // transfer to system memory from
peripheral device
dma_cmd.CHAIN = 1; // chain an additional command
structure on to the list
dma_cmd.IRQONCMPLT = 1; // generate an interrupt on
completion of this command structure
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HALTONTERMINATE
NANDWAIT4READY
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
NANDLOCK
CHAIN
R CMDWORDS COMMAND
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

APBH_CHn_CMD field descriptions

Field Description
31–16 This field indicates the number of bytes to transfer to or from the appropriate PIO register in the
XFER_COUNT GPMI0 device. A value of 0 indicates a 64 KBytes transfer.
15–12 This field indicates the number of command words to send to the GPMI0, starting with the base PIO
CMDWORDS address of the GPMI0 control register and incrementing from there. Zero means transfer NO
command words
8 A value of one indicates that the channel will immeditately terminate the current descriptor and halt
HALTONTERMINATE the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of
the channel if the terminate signal is set, but the channel will continue as if the count had been
exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD.
7 A value of one indicates that the channel will wait for the end of command signal to be sent from the
WAIT4ENDCMD APBH device to the DMA before starting the next DMA command.
6 A value of one indicates that the channel will decrement its semaphore at the completion of the
SEMAPHORE current command structure. If the semaphore decrements to zero, then this channel stalls until
software increments it again.
5 A value of one indicates that the NAND DMA channel will will wait until the NAND device reports
NANDWAIT4READY "ready" before executing the command. It is ignored for non-NAND DMA channels.
4 A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the
NANDLOCK expense of other NAND DMA channels. It is ignored for non-NAND DMA channels.
3 A value of one indicates that the channel will cause the interrupt status bit to be set upon
IRQONCMPLT completion of the current command, i.e. after the DMA transfer is complete.
2 A value of one indicates that another command is chained onto the end of the current command
CHAIN structure. At the completion of the current command, this channel will follow the pointer in
APBH_CHn_CMDAR to find the next command.
COMMAND This bitfield indicates the type of current command:
0x0 NO_DMA_XFER — Perform any requested PIO word transfers but terminate command
before any DMA transfer.
0x1 DMA_WRITE — Perform any requested PIO word transfers and then perform a DMA transfer
from the peripheral for the specified number of bytes.
0x2 DMA_READ — Perform any requested PIO word transfers and then perform a DMA transfer
to the peripheral for the specified number of bytes.
0x3 DMA_SENSE — Perform any requested PIO word transfers and then perform a conditional
branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense
is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
14.5.11 APBH DMA Channel n Buffer Address Register

(APBH_CHn_BAR)
The APBH DMA Channel n buffer address register contains a pointer to the data buffer
for the transfer. For immediate forms, the data is taken from this register. This is a byte
address which means transfers can start on any byte boundary.

This register holds a pointer to the data buffer in system memory. After the command
values have been read into the DMA controller and the device controlled by this channel,
then the DMA transfer will begin, to or from the buffer pointed to by this register.
EXAMPLE
apbh_chn_bar_t dma_data;
dma_data.ADDRESS = (reg32_t) pDataBuffer;
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APBH_CHn_BAR field descriptions

Field Description
ADDRESS Address of system memory buffer to be read or written over the AHB bus.
14.5.12 APBH DMA Channel n Semaphore Register

(APBH_CHn_SEMA)
The APBH DMA Channel n semaphore register is used to synchronize the Arm platform
instruction stream and the DMA chain processing state.
Each DMA channel has an 8 bit counting semaphore that is used to synchronize between
the program stream and and the DMA chain processing. DMA processing continues until
the DMA attempts to decrement a semaphore that has already reached a value of zero.
When the attempt is made, the DMA channel is stalled until software increments the
semaphore count.
EXAMPLE
BF_WR(APBH_CHn_SEMA, 0, INCREMENT_SEMA, 2); // increment semaphore by two

current_sema = BF_RD(APBH_CHn_SEMA, 0, PHORE); // get instantaneous value
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PHORE
Reserved Reserved INCREMENT_SEMA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

APBH_CHn_SEMA field descriptions

Field Description
23–16 This read-only field shows the current (instantaneous) value of the semaphore counter.
PHORE
INCREMENT_ The value written to this field is added to the semaphore count in an atomic way such that simultaneous
SEMA software adds and DMA hardware substracts happening on the same clock are protected. This bit field
reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the
DMA channel decrements the count on the same clock, then the count is incremented by a net one.
14.5.13 AHB to APBH DMA Channel n Debug Information

(APBH_CHn_DEBUG1)
This register gives debug visibility into the APBH DMA Channel n state machine and
controls.
This register allows debug visibility of the APBH DMA Channel n.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NEXTCMDADDRVALID
WR_FIFO_EMPTY
RD_FIFO_EMPTY
WR_FIFO_FULL
RD_FIFO_FULL
READY
BURST
KICK
REQ
END
R
Reserved
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R STATEMACHINE
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

APBH_CHn_DEBUG1 field descriptions

Field Description
31 This bit reflects the current state of the DMA Request Signal from the APB device
REQ
30 This bit reflects the current state of the DMA Burst Signal from the APB device
BURST
29 This bit reflects the current state of the DMA Kick Signal sent to the APB Device
KICK
28 This bit reflects the current state of the DMA End Command Signal sent from the APB Device
END
27 This field is reserved.
SENSE This bit is reserved for this DMA Channel and always reads 0.
26 This bit is reserved for this DMA Channel and always reads 0.
READY
LOCK This bit is reserved for this Channel and always reads 0.
24 This bit reflects the internal bit which indicates whether the channel's next command address is
NEXTCMDADDRVALID valid.
23 This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
RD_FIFO_EMPTY
22 This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
RD_FIFO_FULL
21 This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
WR_FIFO_EMPTY
20 This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
WR_FIFO_FULL
RSVD1 Reserved
STATEMACHINE PIO Display of the DMA Channel n state machine state.
0x00 IDLE — This is the idle state of the DMA state machine.
0x01 REQ_CMD1 — State in which the DMA is waiting to receive the first word of a command.
0x02 REQ_CMD3 — State in which the DMA is waiting to receive the third word of a command.
0x03 REQ_CMD2 — State in which the DMA is waiting to receive the second word of a
command.
0x04 XFER_DECODE — The state machine processes the descriptor command field in this
state and branches accordingly.
0x05 REQ_WAIT — The state machine waits in this state for the PIO APB cycles to complete.
0x06 REQ_CMD4 — State in which the DMA is waiting to receive the fourth word of a
command, or waiting to receive the PIO words when PIO count is greater than 1.
0x07 PIO_REQ — This state determines whether another PIO cycle needs to occur before
starting DMA transfers.
0x08 READ_FLUSH — During a read transfers, the state machine enters this state waiting for
the last bytes to be pushed out on the APB.
0x09 READ_WAIT — When an AHB read request occurs, the state machine waits in this state
for the AHB transfer to complete.
0x0C WRITE — During DMA Write transfers, the state machine waits in this state until the AHB
master arbiter accepts the request from this channel.
0x0D READ_REQ — During DMA Read transfers, the state machine waits in this state until the
AHB master arbiter accepts the request from this channel.

APBH_CHn_DEBUG1 field descriptions (continued)

Field Description
0x0E CHECK_CHAIN — Upon completion of the DMA transfers, this state checks the value of
the Chain bit and branches accordingly.
0x0F XFER_COMPLETE — The state machine goes to this state after the DMA transfers are
complete, and determines what step to take next.
0x14 TERMINATE — When a terminate signal is set, the state machine enters this state until
the current AHB transfer is completed.
0x15 WAIT_END — When the Wait for Command End bit is set, the state machine enters this
state until the DMA device indicates that the command is complete.
0x1C WRITE_WAIT — During DMA Write transfers, the state machine waits in this state until
the AHB master completes the write to the AHB memory space.
0x1D HALT_AFTER_TERM — If HALTONTERMINATE is set and a terminate signal is set, the
state machine enters this state and effectively halts. A channel reset is required to exit this
state
0x1E CHECK_WAIT — If the Chain bit is a 0, the state machine enters this state and effectively
halts.
0x1F WAIT_READY — When the NAND Wait for Ready bit is set, the state machine enters this
state until the GPMI device indicates that the external device is ready.
14.5.14 AHB to APBH DMA Channel n Debug Information

(APBH_CHn_DEBUG2)
This register gives debug visibility for the APB and AHB byte counts for DMA Channel
n.
This register allows debug visibility of the APBH DMA Channel n.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R APB_BYTES AHB_BYTES
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APBH_CHn_DEBUG2 field descriptions

Field Description
31–16 This value reflects the current number of APB bytes remaining to be transfered in the current transfer.
APB_BYTES
AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer.

14.5.15 APBH Bridge Version Register (APBH_VERSION)

This register always returns a known read value for debug purposes it indicates the
version of the block.
This register indicates the RTL version in use.
EXAMPLE
if (APBH_VERSION.B.MAJOR != 3)
Error();
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APBH_VERSION field descriptions

Field Description
31–24 Fixed read-only value reflecting the MAJOR field of the RTL version.
MAJOR
23–16 Fixed read-only value reflecting the MINOR field of the RTL version.
MINOR
STEP Fixed read-only value reflecting the stepping of the RTL version.


Chapter 15
Asynchronous Sample Rate Converter (ASRC)
15.1 Overview
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a signal
associated with an input clock into a signal associated with a different output clock.
The ASRC supports concurrent sample rate conversion of up to 10 channels of about
-120dB THD+N. The ASRC supports up to three sampling rate pairs.
The incoming audio data to this chip may be received from various sources at different
sampling rates. The outgoing audio data of this chip may have different sampling rates
and it can also be associated with output clocks that are asynchronous to the input clocks.
The ASRC is implemented as a co-processor in hardware, with minimal ARM Platform
intervention required.
The following figure is a system view of the connection between the ASRC block and
other blocks.

Overview
MLB
SPDIF
Peripheral Bus
SPDIF Tx clock
asrck_c SPDIF Rx clock
asrck_4
ASRC
MLB Bit Clock
asrck_5
asrck_6 Pad Select: KEY_ROW3 / GPIO_0 / GPIO_18 (configured by

IOMUXC_ASRC_CLOCK_6_SELECT_INPUT[DAISY])
ASRCKI (clock controlled by CCM_CDCDR Register
asrck_d
SPDIF_CLK_PODF and SPDIF1_CLK_PRED bits)
asrck_8 ESAI Tx clock

asrck_0 ESAI Rx clock
SSI-1 Tx clock
asrck_9
SSI-1 Rx clock
asrck_1
DMA reqs asrck_a SSI-2 Tx clock
SSI-2 Rx clock
asrck_2
asrck_b SSI-3 Tx clock
asrck_3 SSI-3 Rx clock
interrupt req
SSI3
SSI2
SSI1
ESAI
Figure 15-1. General System Overview
The following figure is the ASRC block diagram.

The red dotted line designates the ASRC block. Objects outside the dotted line represent
SoC-level resources.

Chapter 15 Asynchronous Sample Rate Converter (ASRC)
Clock Src
clocks
Selector &
Divider
DMA task queue task queue
DSL
reqs. gen. FIFO
Interrupt
reqs
PCU ALU
REG_IF
interrupt logic Other small Logic
FP Peripherals
AGU
MEM_IF
FIFO CTRL
Peripheral BUS
FP
ROM DP RAM PROM
Figure 15-2. ASRC block diagram
15.1.1 Features
Table 15-1. ASRC Specifications
Parameters Test Conditions Minimum Typical Maximum Unit
Channels Supported 0 1 n (0-10) 10
Pairs of Rate Conversion 1 - 3
THD+N 120 MHz < FsASRC2 -120 dB
<160 MHz
Dynamic Range 144 dB
Settling Time 40 ms
Comment:
1. When a pair has zero channels, the pair will be disabled, although the pair enable bit may be set in ASRCTR register.
2. FsASRC is the processing clock of ASRC block.

Overview
Other Features:
• Any number (0-10) of contiguous channels can be associated to one of the sampling
rate pairs.
• Support user-programmable threshold for the input/output FIFOs.
• Support flexible 8/16/24-bit width of input data, and 16/24-bit width of output data.
• Designed for rate conversion between 44.1 kHz, 32 kHz, 48 kHz, 96 kHz, and 192
kHz. The useful signal bandwidth is below 24 kHz.
• Other input sampling rates in the range of 8 kHz to 200 kHz is also supported, but
possibly with less desirable bandwidth.
• Other output sampling rates in the range of 30 kHz to 200 kHz is also supported, but
possibly with less desirable bandwidth.
• Automatic accommodation to slow variations in the incoming and outgoing sampling
rates.
• Linear phase
• Tolerant to sample clock jitter
Clock/Data Connections
• The sampling rate clocks are directly connected to the ASRC block, the ratio
estimation of the input clocks with output clocks are done in ASRC hardware when
both input/output sampling clocks are physically available.
• When both the input sampling clock and the output sampling clock are physically
available, the rate conversion can work by configuring the physical clocks.
• When the input sampling clock is not physically available, the rate conversion can
still work by setting ideal-ratio values into ASRC interface registers.
• The clock signals come from the following blocks:
• ESAI, receiving bit clock and transmitting bit clock
• SSI1, receiving bit clock and transmitting bit clock
• SSI2, receiving bit clock and transmitting bit clock
• SPDIF, receiving bit clock and transmitting bit clock
• other audio peripherals etc.
• MLB bit clock
• The exchange of audio data is done by the processor accessing ASRC block through
registers defined on shared peripheral bus.
15.1.2 Modes of Operation
See ASRC Memory Map/Register Definition for a definition of the registers and
parameters used in ASRC.

15.1.2.1 Data Transfer Schemes
15.1.2.1.1 Data Input Modes

The input mode for each of the three channel sets may be set independently. Three modes
of supplying data to the ASRC input FIFOs are available:
• Polling
• Interrupt
• DMA
In all input-data transfer schemes, the ASRC fetches data from each enabled FIFO and
processes the data sample-by-sample after each rising edge of the associated input
sampling clock until the FIFO level reaches a threshold.
After the threshold is reached, the ASRC requests data. The FIFO size for each channel
set is 64 samples and the threshold is set at 32 samples. The threshold can be defined by
interface registers ASRMCRx, x=A, B or C.
If the ASRC attempts to fetch data from an empty FIFO, an error is generated and the
ASRSTR_AOLE bit is set. If the ASRC overload interrupt is enabled (ASRIER_AOLIE
bit is set), an interrupt is generated.
When writing data to an input FIFO, you must ensure that it is in a predefined sequence.
For example, when writing to an input FIFO, the sequence should be: channel_0,
channel_1, channel_2,..., channel_n, channel_0, channel_1, channel_2, etc. Here
channel_n stands for the data intended for the n-th channel. The hardware will re-allocate
each data to its corresponding channel FIFO. The channel being re-allocated is shown by
ASRCCR_ACIx, x=A,B or C.
Mode 1 (Polling Mode)
Polling mode is the default mode following power-on or individual reset, and is selected
by clearing the associated channel set A, B, or C data-input interrupt enable bit
(ASRIER_ADIEx, where x=A, B or C). In this mode, data-input interrupts are disabled.
When the FIFO level is below the threshold, the associated status bit (ASRSTR_AIDEx,
where x=A, B, or C) is set. To clear the status bit, the FIFO must be written with enough
data to raise the level above the threshold.
Mode 2 (Interrupt Mode)

Overview
The ASRC input FIFOs can also be serviced by interrupts. To enable interrupts, the
corresponding data-input interrupt enable bits (ASRIER_ADIEx, where x=A, B, or C)
should be set. An interrupt is automatically generated any time the input FIFO level is
below the threshold. The interrupt is cleared when enough data is written to the FIFO to
raise the level above the threshold.
Mode 3 (DMA Mode)
The ASRC input FIFOs can also be filled using DMA. In this mode, the data-input
interrupt-enable bits (ASRIER_ADIEx, where x=A, B, or C) should be cleared and the
DMA controller should be configured to use the ASRC as a request source.
15.1.2.1.2 Data Output Modes

The output mode for each of the 3 channel sets (A, B, and C) may be set independently.
Three modes of retrieving data from the ASRC output FIFOs are available:
• Polling
• Interrupt
• DMA
In all output-data transfer schemes, the ASRC places a processed sample into the
associated output FIFO. After a threshold is reached, the ASRC requests that data be
transferred out of the FIFO.
The FIFO size for each channel set is 64 samples and the threshold is set at 32 samples.
The threshold can be defined by interface registers ASRMCRx, x=A, B or C.
If the ASRC attempts to place data into a FIFO that is already full, an error is generated
and the ASRSTR_AOLE bit is set. If the ASRC overload interrupt is enabled
(ASRIER_AOLIE bit is set), an interrupt is generated.
Each output FIFO is organized in the same channel order in which the associated input
FIFO was written.
Three transfer modes are supported by Interface Block.
Mode 1 (Polling Mode)
The ASRC output FIFOs can be serviced by polling. In this mode, ensure the associated
output-data interrupt enable bit (ASRIER_ADOEx, where x=A, B, or C) is cleared. In
this mode, all output-data interrupts are disabled. Any time the output FIFO exceeds the
threshold the associated status bit (ASRSTR_AODFx, where x=A, B, or C) is set. To
clear the status bit, enough data must be read from the associated output FIFO to lower
the level below the threshold.
Mode 2 (Interrupt Mode)
The ASRC output FIFOs may also be serviced using interrupts. To enable this mode, the
corresponding output-data interrupt-enable bits (ASRIER_ADOEx, where x=A, B, or C)
should be set. Any time the output FIFO level exceeds the threshold, an interrupt is
automatically generated. The interrupt is cleared when enough data is read from the FIFO
to lower the level below the threshold.
Mode 3 (DMA Mode)
The ASRC output FIFOs can also be read using DMA. In this mode, the output-data
interrupt-enable bits (ASRIER_ADOEx, where x=A, B, or C) should be cleared and the
DMA controller should be configured to use the ASRC as a request source.
15.1.2.2 Word Alignment Supported
15.1.2.2.1 Input Data Alignment Modes

The position and length of input data word to the input data FIFOs ASRDIA, ASRDIB,
ASRDIC are programmable. The control bits are defined in ASRMCR1x {x=A, B, or C}.
It supports the following modes.
Table 15-2. Input Data Alignment
Format Bit Number
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8-bit LSB 7 6 5 4 3 2 1 0
Aligned
8-bit MSB 7 6 5 4 3 2 1 0
Aligned
16-bit LSB 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned 5 4 3 2 1 0
16-bit MSB 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned 5 4 3 2 1 0
24-bit LSB 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned 3 2 1 0 9 8 7 6 5 4 3 2 1 0
24-bit MSB 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Clocks
15.1.2.2.2 Output Data Alignment Modes

The position and length of output data word from the output data FIFOs ASRDOA,
ASRDOB, ASRDOC are programmable. The control bits are defined in ASRMCR1x
{x=A, B, or C}. It supports the following modes.
Table 15-3. Output Data Alignment
Format Bit Number
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
16-bit LSB 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned 5 4 3 2 1 0
16-bit LSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned with 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 3 2 1 0
Sign Extension
16-bit MSB 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned 5 4 3 2 1 0
24-bit LSB 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned 3 2 1 0 9 8 7 6 5 4 3 2 1 0
24-bit LSB 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned with 3 3 3 3 3 3 3 3 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Sign Extension
24-bit MSB 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Aligned 3 2 1 0 9 8 7 6 5 4 3 2 1 0
15.2 Clocks
The table found here describes the clock sources for ASRC.
Please see clock control block for clock setting, configuration and gating information.
Table 15-4. ASRC Clocks
asrck_clock_d spdif1_clk_root ASRC module clock (SPDIF clock)
ipg_clk ahb_clk_root Peripheral clock
mem_clk ahb_clk_root Peripheral access clock
15.3 Interrupts
ASRC has several interrupts events.

The priorities are shown in the following table.

Table 15-5. Interrupt Priorities/Vector
Priority Offset Description
lowest 0x0 ASRC Pair A input data needed
0x2 ASRC Pair B input data needed
0x4 ASRC Pair C input data needed
0x6 ASRC Pair A output data ready
0x8 ASRC Pair B output data ready
0xA ASRC Pair C output data ready
highest 0xC ASRC Overload
15.4 DMA requests

ASRC has six DMA requests. They are directly connected to the lowest six status bits in
the ASRSTR register. For some ARM platforms, the six status bits are directly connected
to SDMA or HDMA as DMA event signals.
Table 15-6. DMA requests
Type Description
0 ASRC Pair A input data needed
1 ASRC Pair B input data needed
2 ASRC Pair C input data needed
3 ASRC Pair A output data ready
4 ASRC Pair B output data ready
5 ASRC Pair C output data ready

This section provides a complete functional description of the block.
15.5.1 Algorithm Description

15.5.1.1 Signal processing flow
General
(1)
x2
UpSampling Fs
Low-Pass Polyphase ppout
Pre-Filter Filter
11 taps
(2)
Post Up Sampling Filter

Low-pass x0.5 (3)
Half-band Down-
Sampling x2 (1)
UpSampling Low-Pass
Pre-Decimation Filter
Fs
in (2)
Post Decimation Filter
Low-pass x0.5 (3)

Half-band Down-
Sampling
Fs
out
Figure 15-3. Signal processing configurations
The figure above shows the possible configurations of the ASRC. Each configuration
consists of 2 to 4 stages.
• x2 up-sampling rate expander (zero insertion only) (input branch 1), direct
connection (input branch 2), or low-pass pre decimation filter (consisting of a low-
pass half-band FIR filter with x0.5 downsampling rate decimator) (input branch 3),
• low-pass pre-filter, the low-pass bandwidth is at most 0.25 x Fs, where Fs is the
sampling rate of the input signal to this low-pass pre-filter,
• polyphase filter,
• x2 post upsampling filter (consisting of a x2 up-sampling rate expander (zero
insertion only) with low-pass half-band FIR filter) (output branch 1), direct
connection (output branch 2), or low-pass post decimation filter (consisting of a low-
pass half-band FIR filter with x0.5 downsampling rate decimator) (output branch 3).
By flowing through different processing branches and different setups of the pre-filter,
this ASRC scheme can be used to handle different rate conversion requirements.
• Configuration (a): Input Branch 1+Output Branch 1:

The signal bandwidth observed before the polyphase filter is at most BWin = Fsin/2.
The signal sampling rate of the polyphase filter output is Fsppout = Fsout/2.
• Configuration (b): Input Branch 1+Output Branch 2:
The signal sampling rate of the polyphase filter output is Fsppout = Fsout.
• Configuration (c): Input Branch 1+Output Branch 3:
The signal sampling rate of the polyphase filter output is Fsppout = 2Fsout.
• Configuration (d): Input Branch 2+Output Branch 1:
• Configuration (e): Input Branch 2+Output Branch 2:
• Configuration (f): Input Branch 2+Output Branch 3:
• Configuration (g): Input Branch 3+Output Branch 1:
• Configuration (h): Input Branch 3+Output Branch 2:
• Configuration (i): Input Branch 3+Output Branch 3:

Table 15-7. Pre-processing, post-processing options

{Pre_Proc, Fsout (KHz)
Post_Proc}
8 12 16 24 32 44.1 48 64 88.2 96 128 192
8 {0,1} {0,1} {0,1} {0,0} {0,0} {0,0} {0,0} {0,0} {0,0} {0,0} {0,0} {0,0}
12 {0,2} {0,1} {0,1} {0,1} {0,1} {0,0} {0,0} {0,0} {0,0} {0,0} {0,0} {0,0}
16 {1,2} {0,2} {0,1} {0,1} {0,1} {0,1} {0,1} {0,0} {0,0} {0,0} {0,0} {0,0}
24 {1,2} {1,2} {0,2} {0,1} {0,1} {0,1} {0,1} {0,1} {0,0} {0,0} {0,0} {0,0}
32 {1,2} {1,2} {1,2} {0,2} {0,1} {0,1} {0,1} {0,1} {0,1} {0,0} {0,0} {0,0}
Fsin 44.1 {2,2} {1,2} {1,2} {0,2} {0,2} {0,1} {0,1} {0,1} {0,1} {0,1} {0,0} {0,0}
(KHz) 48 {2,2} {1,2} {1,2} {1,2} {0,2} {0,2} {0,1} {0,1} {0,1} {0,1} {0,1} {0,0}
64 {2,2} {2,2} {1,2} {1,2} {0,2} {0,2} {0,2} {0,1} {0,1} {0,1} {0,1} {0,0}
88.2 NA {2,2} {2,2} {1,2} {1,2} {1,2} {1,2} {1,1} {1,1} {1,1} {1,1} {1,1}
96 NA {2,2} {2,2} {1,2} {1,2} {1,2} {1,2} {1,1} {1,1} {1,1} {1,1} {1,1}
128 NA NA {2,2} {2,2} {1,2} {1,2} {1,2} {1,1} {1,1} {1,1} {1,1} {1,1}
192 NA NA NA {2,2} {2,2} {2,2} {2,2} {2,1} {2,1} {2,1} {2,1} {2,1}
NOTE: In the {Pre_Proc, Post_Proc} pair, the meaning of the values are:
Pre_Proc:
• 0 --- Pre-processing Branch 1 as shown in Figure 15-3
• 1 --- Pre-processing Branch 2 as shown in Figure 15-3
• 2 --- Pre-processing Branch 3 as shown in Figure 15-3, decimation-by-2
Post_Proc:
• 0 --- Post-processing Branch 1 as shown in Figure 15-3
The latencies of the different option can be roughly calculated as follows:

• For PreProc = 0, PostProc = 1 : min latency = constant_A / input-sample-rate +
constant_B / output-sample-rate
• For PreProc = 0, PostProc = 0 : min latency = constant_A / input-sample-rate +
constant_C / output-sample-rate
• For PreProc = 1, PostProc = 1 : min latency = constant_D / input-sample-rate +
constant_B / output-sample-rate
The constants above (e.g., constant_A means the Constant for Preproc = 0, constant_B
means the Constant for Postproc = 1, ...) are only influenced by the PreProc/PostProc and
(input/output) sampling rate to which they are connected. Input latencies have no
relationship with the output latencies, but both elements add together to form the total
latencies.
For a rough estimation, the constants can be set as:
• Constant for Preproc = 0: 39

• Constant for Preproc = 1: 78.5

• Constant for Preproc = 2: 235
• Constant for Postproc = 0: 42.5
• Constant for Postproc = 1: 8.5
• Constant for Postproc = 2: 172
The max latency can be derived from this value by using the following formula (where
32 means the input/output FIFO depth that will arouse data transfer):
• max latency = min latency + 32 / input-sample-rate + 32 / output-sample-rate
15.5.1.2 Operation of the Filter
15.5.1.2.1 Support of Physical Clocks

This design supports physical sampling clocks. The clocks can be provided by:
• Sony/Phillips digital interface (SPDIF)
• Enhanced Serial Audio Interface (ESAI),
• Standard Serial Interface (SSI-1, SSI-2, SSI-3),
• Media Local Bus controller (MLB)
• Core master clock derivative as ASRCK1

ESAI Rx clock AICDA 0 - AICDA2 AICPA 0 - AICPA2
SS 1 Rx clock
Input Clock Input

SS 2 Rx clock Prescaler A
Divider A Input clock A
SPDIF Rx clock Input Clock Input

Divider B Prescaler B
Input clock B
MLB Bit clock
ASRCK1 MUX
ESAI Tx clock AICDB0 - AICDB2 AICPB0 - AICPB2
SS 1 Tx clock
Input Clock Input
SS 2 Tx clock Divider C Prescaler C Input clock C
SPDIF Tx clock
AICDC0 - AICDC2 AICPC0 - AICPC2
AICSA0 - AICSA3
AICSB0 - AICSB3
AICSC0 - AICSC3
ESAI Tx clock AOCDA0 - AOCDA2 AOCPA0 - AOCPA2
SS 1 Tx clock
SS 2 Tx clock Input Clock Output

Divider A Prescaler A
Output clock A
SPDIF Tx clock
Input Clock Output
Divider B Prescaler B
MLB Bit clock Output clock B
ASRCK1 (768kHz) MUX
ESAI Rx clock AOCDB0 - AOCDB2 AOCPB0 - AOCPB2
SS 1 Rx clock
Input Clock Output
SS 2 Rx clock Divider C Prescaler C Output clock C
SPDIF Rx clock
AOCDC0 - AOCDC2 AOCPC0 - AOCPC2
AOCSA0 - AOCSA3
AOCSB0 - AOCSB3
AOCSC0 - AOCSC3
Figure 15-4. Clock Source Selector and Divider

Software can set the ASRC Clock Source Register (ASRCSR) and the Clock Divider
Register to select the desired clock source and divide it to the needed sample rate clock
for use by the ASRC. The clocks have the following restriction. If the prescaler is set to
1, the clock divider can only be set to 1 and the clock source must have a 50% duty cycle.
15.6 Startup Procedure

The following example shows the normal setup procedure for the ASRC block.
#include "asrc_common.h"
#include "stdio.h"
#include "soc_api.h"
int incnt=0;
int outcnt=0;
#include "wy_ideal_ratio_dataini_part.h"
WORD IdealRatio_High=0x04; //
WORD IdealRatio_Low=0x0; //
void asrc_config_alloc(WORD ASRCTR_VAL, WORD ASRIER_VAL, WORD ASRCNCR_VAL,

WORD ASRCFG_VAL, WORD ASRCDR1_VAL, WORD ASRCDR2_VAL,
WORD ASRCSR_VAL)
{ // Disable ASRC
reg32_write(ASRC_ASRCTR,0x0);
reg32_write(ASRC_ASRCTR,ASRCTR_VAL);
reg32_write(ASRC_ASRIER,ASRIER_VAL);
reg32_write(ASRC_ASRIEM,0x0);
reg32_write(ASRC_ASRCNCR,ASRCNCR_VAL);
reg32_write(ASRC_ASRCFG,ASRCFG_VAL);
reg32_write(ASRC_ASRCDR1,ASRCDR1_VAL);
reg32_write(ASRC_ASRCDR2,ASRCDR2_VAL);
reg32_write(ASRC_ASRCSR, ASRCSR_VAL);
reg32_write(ASRC_ASRPM1, 0x7fffff);
reg32_write(ASRC_ASRPM2, 0x255555);
reg32_write(ASRC_ASRPM3, 0xff7280);

Startup Procedure
reg32_write(ASRC_ASRQFIFO1,0x001f00);
reg32_write(ASRC_ASRMCRA,0x001f00);
reg32_write(ASRC_ASRMCRB,0x001f00);
reg32_write(ASRC_ASRMCRC,0x001f00);
void sim_ideal_ratio()
WORD tmp32bit;
#define ASRSTR_AIDEA_MASK 0x1
#define ASRSTR_AODFA_MASK 0x1 <<3
#define ASRSTR_AOLE_MASK 0x1<<6
#define ASRCTR_DBG_EN 1<<23
#define ASRCTR_IDRA 1<<13
#define ASRCTR_USRA 1<<14
#define ASRC_CLK_PRED_RSTRICTED 0<<28
#define ASRC_CLK_PRED_DFLT 1<<28 // default: 596MHz div by 2
#define ASRC_CLK_PRED_DIV3 2<<28 // 596MHz div by 3
#define ECSPI_CLK_PRED_DFLT 1<<25
#define ECSPI_CLK_PODF_DFLT 1<<19
#define ASRC_CLK_PODF_DIV1 0<<9 // pred output divide by 1 again
#define ASRC_CLK_PODF_DFLT 4<<9 // default: pred output divide by 5 again
#define IEEE_CLK_PRED_DFLT 1<<6 //

#define IEEE_CLK_PODF_DFLT 4 //
#define ASR_HFA_HFB 0
#define ASR_PREMODA_UP2 0<<6
#define ASR_PREMODA_DIR 1<<6
#define ASR_PREMODA_DN2 2<<6
#define ASR_PREMODA_PAS 3<<6
#define ASR_POSTMODA_UP2 0<<8
#define ASR_POSTMODA_DIR 1<<8
#define ASR_POSTMODA_DN2 2<<8
reg32_write(CCM_CSCDR2, ASRC_CLK_PRED_DIV8|ECSPI_CLK_PRED_DFLT|ECSPI_CLK_PODF_DFLT|
ASRC_CLK_PODF_DIV25|IEEE_CLK_PRED_DFLT|IEEE_CLK_PODF_DFLT);
// Disable the ASRC
reg32_write(ASRC_ASRCTR, 0x0);
// program AHB clocks
tmp32bit = reg32_read(CCM_CBCDR);
tmp32bit = tmp32bit & (~0x00001C00);
//tmp32bit = tmp32bit | (0x00000C00); // AHB 100MHz // divided-by-4
//tmp32bit = tmp32bit | (0x00001000); // AHB 80MHz // divided-by-5
tmp32bit = tmp32bit | (0x00001C00); // AHB 50MHz // divided-by-8
reg32_write(CCM_CBCDR, tmp32bit); // enable all perihperal clocks during all modes,

except stop mode
while ( (reg32_read(CCM_CDHIPR) & 0x00008) != 0);
asrc_config_alloc ( 0x002 | ASRCTR_IDRA | ASRCTR_USRA, // ASRCTR_VAL, Use

Ratio input, use ideal ratio, Enable Pair A,
0x0, //0x09, // ASRIER_VAL, Open

PairA input and output interrupt
0x002, // ASRCNCR_VAL, assign 2 channels to Pair A
ASR_PREMODA_DIR | ASR_POSTMODA_DIR | ASR_HFA_HFB, // ASRCFG_VAL,

POSTMODA=downsampling by 2 ; PREMODA=downsampling by 2
0x03b03b , // ASRCDR1_VAL, AOCPA=3(FoutA/(2^3)); AICPA=3(FinA/(2^3));

AOCDA=7(div 8); AICDA=7(div 8);
0x0 , // ASRCDR2_VAL,
0x00d00d // ASRCSR_VAL, AOCSA=d: bit clock d: ASRCK1 clk from CCM; AICSA=d:
bit clock d: ASRCK1 clock from CCM;
);

Startup Procedure
reg32_write(ASRC_ASRIDRHA, 0x04); //
reg32_write(ASRC_ASRIDRLA, 0x0); // Ideal Ratio is set to be 1.
#define OUTFIFO_THRESH_0 8<<12
#define INFIFO_THRESH_1 32
reg32_write(ASRC_ASRMCRA, OUTFIFO_THRESH_0 | INFIFO_THRESH_1);
reg32clrbit(ASRC_ASRMCRA, 23); // zeroize Pair A buffers
reg32setbit(ASRC_ASRMCRA, 21); // stall conversion in case of near full/near empty

condition
reg32clrbit(ASRC_ASRMCRA, 20); // Do not bypass polyA filter
// Set ASRC Interrupt
//CAPTURE_INTERRUPT(ASRC_INT_ROUTINE, asrc_handler);
//enable_hdler(ASRC_INT_NUM);
disable_hdler(ASRC_INT_NUM);
incnt=0;
outcnt=0;
reg32setbit(ASRC_ASRCTR,0); // enable ASRC
#define ASRCFG_INIA_FINISH 0x1<<21
while ( (reg32_read(ASRC_ASRCFG) & ASRCFG_INIA_FINISH) == 0); // wait for ini finished.
// Polling
while (outcnt < 100) <
int ii;
if ( (reg32_read(ASRC_ASRSTR) & ASRSTR_AIDEA_MASK) != 0 )
for (ii=0;ii<2;ii++)</codeblock
reg32_write(ASRC_ASRDIA,asrc_input_array[incnt]); // feed in input

data
reg32_write(ASRC_ASRDIA,asrc_input_array[incnt]); // feed in input

data
incnt=(incnt+1)%128;
if ( (reg32_read(ASRC_ASRSTR) & ASRSTR_AODFA_MASK) != 0 )

for (ii=0;ii<2;ii++)<
WORD TempRdOut;
TempRdOut=reg32_read(ASRC_ASRDOA); // get output data
TempRdOut=reg32_read(ASRC_ASRDOA); // get output data
outcnt=outcnt+1;
if ( (reg32_read(ASRC_ASRSTR) & ASRSTR_AOLE_MASK) != 0 )
reg32_write(ASRC_ASRSTR,ASRSTR_AOLE_MASK); // clear overloading

errors
reg32clrbit(ASRC_ASRCTR,0); // disable ASRC
15.7 ASRC Memory Map/Register Definition
All useful registers are listed in the memory map below. The access of undefined
registers will behave as normal registers.
All the interface registers are LSB aligned except the input FIFOs and the output FIFOs,
and each register has only 24 effective bits.
The input FIFO and output FIFO word alignment can be defined using
ASRMCR1{A,B,C} registers in 32-bit interface system.
ASRC memory map
Absolute
Width Section/
(in bits) page
(hex)
203_4000 ASRC Control Register (ASRC_ASRCTR) 32 R/W 0000_0000h 15.7.1/476
203_4004 ASRC Interrupt Enable Register (ASRC_ASRIER) 32 R/W 0000_0000h 15.7.2/479
ASRC Channel Number Configuration Register
203_400C 32 R/W 0000_0000h 15.7.3/480
(ASRC_ASRCNCR)

ASRC Memory Map/Register Definition
ASRC memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
ASRC Filter Configuration Status Register
203_4010 32 R/W 0000_0000h 15.7.4/482
(ASRC_ASRCFG)
203_4014 ASRC Clock Source Register (ASRC_ASRCSR) 32 R/W 0000_0000h 15.7.5/484
203_4018 ASRC Clock Divider Register 1 (ASRC_ASRCDR1) 32 R/W 0000_0000h 15.7.6/487
203_401C ASRC Clock Divider Register 2 (ASRC_ASRCDR2) 32 R/W 0000_0000h 15.7.7/488
203_4020 ASRC Status Register (ASRC_ASRSTR) 32 R 0000_0000h 15.7.8/490
203_4040 ASRC Parameter Register n (ASRC_ASRPMn1) 32 R/W 0000_0000h 15.7.9/493
203_404C ASRC Parameter Register n (ASRC_ASRPMn4) 32 R/W 0000_0000h 15.7.9/493
ASRC ASRC Task Queue FIFO Register 1
203_4054 32 R/W 0000_0000h 15.7.10/494
(ASRC_ASRTFR1)
203_405C ASRC Channel Counter Register (ASRC_ASRCCR) 32 R/W 0000_0000h 15.7.11/495
203_4060 ASRC Data Input Register for Pair x (ASRC_ASRDIA) 32 W 0000_0000h 15.7.12/496
203_4064 ASRC Data Output Register for Pair x (ASRC_ASRDOA) 32 R 0000_0000h 15.7.13/496
203_4068 ASRC Data Input Register for Pair x (ASRC_ASRDIB) 32 W 0000_0000h 15.7.12/496
203_406C ASRC Data Output Register for Pair x (ASRC_ASRDOB) 32 R 0000_0000h 15.7.13/496
203_4070 ASRC Data Input Register for Pair x (ASRC_ASRDIC) 32 W 0000_0000h 15.7.12/496
203_4074 ASRC Data Output Register for Pair x (ASRC_ASRDOC) 32 R 0000_0000h 15.7.13/496
203_4080 ASRC Ideal Ratio for Pair A-High Part (ASRC_ASRIDRHA) 32 R/W 0000_0000h 15.7.14/497
203_4084 ASRC Ideal Ratio for Pair A -Low Part (ASRC_ASRIDRLA) 32 R/W 0000_0000h 15.7.15/497
203_4088 ASRC Ideal Ratio for Pair B-High Part (ASRC_ASRIDRHB) 32 R/W 0000_0000h 15.7.16/498
203_408C ASRC Ideal Ratio for Pair B-Low Part (ASRC_ASRIDRLB) 32 R/W 0000_0000h 15.7.17/498
203_4090 ASRC Ideal Ratio for Pair C-High Part (ASRC_ASRIDRHC) 32 R/W 0000_0000h 15.7.18/499
203_4094 ASRC Ideal Ratio for Pair C-Low Part (ASRC_ASRIDRLC) 32 R/W 0000_0000h 15.7.19/499
ASRC 76 kHz Period in terms of ASRC processing clock
203_4098 32 R/W 0000_0A47h 15.7.20/500
(ASRC_ASR76K)
ASRC 56 kHz Period in terms of ASRC processing clock
203_409C 32 R/W 0000_0DF3h 15.7.21/501
(ASRC_ASR56K)
203_40A0 ASRC Misc Control Register for Pair A (ASRC_ASRMCRA) 32 R/W 0000_0000h 15.7.22/502
203_40A4 ASRC FIFO Status Register for Pair A (ASRC_ASRFSTA) 32 R 0000_0000h 15.7.23/504
203_40A8 ASRC Misc Control Register for Pair B (ASRC_ASRMCRB) 32 R/W 0000_0000h 15.7.24/505
203_40AC ASRC FIFO Status Register for Pair B (ASRC_ASRFSTB) 32 R 0000_0000h 15.7.25/507
203_40B0 ASRC Misc Control Register for Pair C (ASRC_ASRMCRC) 32 R/W 0000_0000h 15.7.26/508
203_40B4 ASRC FIFO Status Register for Pair C (ASRC_ASRFSTC) 32 R 0000_0000h 15.7.27/510
ASRC Misc Control Register 1 for Pair X
203_40C0 32 R/W 0000_0000h 15.7.28/511
(ASRC_ASRMCR1A)
203_40C4 32 R/W 0000_0000h 15.7.28/511
(ASRC_ASRMCR1B)

ASRC memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
203_40C8 32 R/W 0000_0000h 15.7.28/511
(ASRC_ASRMCR1C)

15.7.1 ASRC Control Register (ASRC_ASRCTR)
The ASRC control register (ASRCTR) is a read/write register that controls the ASRC
operations.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reserved
USRC
ATSC
ATSA
Reserved ATSB IDRC USRB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASRCEN
ASREC
ASREB
ASREA
USRA
IDRB IDRA Reserved

SRST
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ASRC_ASRCTR field descriptions

Field Description
- Reserved
- Reserved. Should be written as zero for compatibility.
22 ASRC Pair C Automatic Selection For Processing Options
ATSC
When this bit is 1, pair C will automatic update its pre-processing and post-processing options (ASRCFG:
PREMODC, ASRCFG:POSTMODC see ASRC Misc Control Register 1 for Pair C) based on the
frequencies it detected. To use this option, the two parameter registers(ASR76K and ASR56K) should be
set correctly (see ASRC Misc Control Register 1 for Pair C and ASRC Misc Control Register 1 for Pair C).
When this bit is 0, the user is responsible for choosing the proper processing options for pair C.
This bit should be disabled when {USRC, IDRC}={1,1}.
21 ASRC Pair B Automatic Selection For Processing Options
ATSB
When this bit is 1, pair B will automatic update its pre-processing and post-processing options (ASRCFG:
PREMODB, ASRCFG:POSTMODB see ASRC Misc Control Register 1 for Pair C) based on the
When this bit is 0, the user is responsible for choosing the proper processing options for pair B.
This bit should be disabled when {USRB, IDRB}={1,1}.
20 ASRC Pair A Automatic Selection For Processing Options
ATSA
When this bit is 1, pair A will automatic update its pre-processing and post-processing options (ASRCFG:
PREMODA, ASRCFG:POSTMODA see ASRC Misc Control Register 1 for Pair C) based on the
When this bit is 0, the user is responsible for choosing the proper processing options for pair A.
This bit should be disabled when {USRA, IDRA}={1,1}.
18 Use Ratio for Pair C
USRC
Use ratio as the input to ASRC. This bit is used in conjunction with IDRC control bit.
17 Use Ideal Ratio for Pair C
IDRC
When USRC=0, this bit has no usage.
When USRC=1 and IDRC=0, ASRC internal measured ratio will be used.
When USRC=1 and IDRC=1, the idea ratio from the interface register ASRIDRHC, ASRIDRLC will be
used. It is suggested to manually set ASRCFG:POSTMODC, ASRCFG:PREMODC according to Table
15-7 in this case.
16 Use Ratio for Pair B
USRB
Use ratio as the input to ASRC. This bit is used in conjunction with IDRB control bit.
15 Use Ideal Ratio for Pair B
IDRB
When USRB=0, this bit has no usage.
When USRB=1 and IDRB=0, ASRC internal measured ratio will be used.
When USRB=1 and IDRB=1, the idea ratio from the interface register ASRIDRHB, ASRIDRLB will be
used.It is suggested to manually set ASRCFG:POSTMODB, ASRCFG:PREMODB according to Table
15-7 in this case.

ASRC_ASRCTR field descriptions (continued)

Field Description
14 Use Ratio for Pair A
USRA
Use ratio as the input to ASRC. This bit is used in conjunction with IDRA control bit.
13 Use Ideal Ratio for Pair A
IDRA
When USRA=0, this bit has no usage.
When USRA=1 and IDRA=0, ASRC internal measured ratio will be used.
When USRA=1 and IDRA=1, the idea ratio from the interface register ASRIDRHA, ASRIDRLA will be
used. It is suggested to manually set ASRCFG:POSTMODA, ASRCFG:PREMODA according to Table
15-7 in this case.
4 Software Reset
SRST
This bit is self-clear bit. Once it is been written as 1, it will generate a software reset signal inside ASRC.
After 9 cycles of the ASRC processing clock, this reset process will stop, and this bit will be cleared
automatically.
3 ASRC Enable C
ASREC
Enable the operation of the conversion C of ASRC. When ASREC is cleared, operation of conversion C is
disabled.
2 ASRC Enable B
ASREB
Enable the operation of the conversion B of ASRC. When ASREB is cleared, operation of conversion B is
disabled.
1 ASRC Enable A
ASREA
Enable the operation of the conversion A of ASRC. When ASREA is cleared, operation of conversion A is
disabled.
0 ASRC Enable
ASRCEN
Enable the operation of ASRC.

15.7.2 ASRC Interrupt Enable Register (ASRC_ASRIER)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFPWE
ADOEC
ADOEB
ADOEA
ADIEC
ADIEB
ADIEA
AOLIE
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRIER field descriptions

Field Description
- Reserved
7 FP in Wait State Interrupt Enable
AFPWE
Enables the FP in wait state interrupt.
1 interrupt enabled
0 interrupt disabled
6 Overload Interrupt Enable
AOLIE
Enables the overload interrupt.
1 interrupt enabled
5 Data Output C Interrupt Enable
ADOEC
Enables the data output C interrupt.
1 interrupt enabled
4 Data Output B Interrupt Enable
ADOEB
Enables the data output B interrupt.
1 interrupt enabled

ASRC_ASRIER field descriptions (continued)

Field Description
3 Data Output A Interrupt Enable
ADOEA
Enables the data output A interrupt.
1 interrupt enabled
2 Data Input C Interrupt Enable
ADIEC
Enables the data input C interrupt.
1 interrupt enabled
1 Data Input B Interrupt Enable
ADIEB
Enables the data input B interrupt.
1 interrupt enabled
0 Data Input A Interrupt Enable
ADIEA
Enables the data input A Interrupt.
1 interrupt enabled
15.7.3 ASRC Channel Number Configuration Register

(ASRC_ASRCNCR)
The ASRC channel number configuration register (ASRCNCR) is a read/write register
that sets the number of channels used by each ASRC conversion pair.
There are 10 channels available for distribution among 3 conversion pairs, they are
ordered as 0,1,...,9. The bottom [0, ANCA-1] channels are used for pair A, the top [10-
ANCC, 9] channels are used for pair C, and the [ANCA, ANCA+ANCB-1] channels are
allocated for pair B. In case that ANCA=0, then the [0, ANCB-1] channels are assigned
for pair B.
Address: 203_4000h base + Ch offset = 203_400Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved ANCC ANCB ANCA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ASRC_ASRCNCR field descriptions

Field Description
- Reserved
11–8 Number of C Channels1
ANCC
0000 0 channels in C (Pair C is disabled)
0001 1 channel in C
0010 2 channels in C
1011-1111 Should not be used.
7–4 Number of B Channels
ANCB
0000 0 channels in B (Pair B is disabled)
0001 1 channel in B
0010 2 channels in B
ANCA Number of A Channels
0000 0 channels in A (Pair A is disabled)

0001 1 channel in A
0010 2 channels in A
1. ANCC+ANCB+ANCA<=10. Hardware is not checking the constraint. Programmer should take the responsibility to ensure
the constraint is satisfied.

15.7.4 ASRC Filter Configuration Status Register

(ASRC_ASRCFG)
The ASRC configuration status register (ASRCFG) is a read/write register that sets
and/or automatically senses the ASRC operations.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INIRQC
INIRQB
INIRQA
R
NDPRC
NDPRB
NDPRA
Reserved POSTMODC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREMODC POSTMODB PREMODB POSTMODA PREMODA Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRCFG field descriptions

Field Description
- Reserved
23 Initialization for Conversion Pair C is served
INIRQC
When this bit is 1, it means the initialization for conversion pair C is served. This bit is cleared by disabling
the ASRC conversion pair (ASRCTR:ASREC=0 or ASRCTR:ASRCEN=0).
22 Initialization for Conversion Pair B is served
INIRQB
When this bit is 1, it means the initialization for conversion pair B is served. This bit is cleared by disabling
the ASRC conversion pair (ASRCTR:ASREB=0 or ASRCTR:ASRCEN=0).

ASRC_ASRCFG field descriptions (continued)

Field Description
21 Initialization for Conversion Pair A is served
INIRQA
When this bit is 1, it means the initialization for conversion pair A is served. This bit is cleared by disabling
the ASRC conversion pair (ASRCTR:ASREA=0 or ASRCTR:ASRCEN=0).
20 Not Use Default Parameters for RAM-stored Parameters For Conversion Pair C
NDPRC
0 Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
1 Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
19 Not Use Default Parameters for RAM-stored Parameters For Conversion Pair B
NDPRB
1 Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
18 Not Use Default Parameters for RAM-stored Parameters For Conversion Pair A
NDPRA
1 Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
17–16 Post-Processing Configuration for Conversion Pair C
POSTMODC
These bits will be read/write by user if ASRCTR:ATSC=0, and can also be automatically updated by the
ASRC internal logic if ASRCTR:ATSC=1 (see ASRC Misc Control Register 1 for Pair C). These bits set
the selection of the post-processing configuration.
00 Select Upsampling-by-2 as defined in Signal Processing Flow.

01 Select Direct-Connection as defined in Signal Processing Flow.
10 Select Downsampling-by-2 as defined in Signal Processing Flow.
15–14 Pre-Processing Configuration for Conversion Pair C
PREMODC
These bits will be read/write by user if ASRCTR:ATSC=0, and can also be automatically updated by the
ASRC internal logic if ASRCTR:ATSC=1 (see ASRC Misc Control Register 1 for Pair C). These bits set
the selection of the pre-processing configuration.
00 Select Upsampling-by-2 as defined in Signal processing flow

01 Select Direct-Connection as defined in Signal processing flow
10 Select Downsampling-by-2 as defined in Signal processing flow
11 Select passthrough mode. In this case, POSTMODC[1-0] have no use.
13–12 Post-Processing Configuration for Conversion Pair B
POSTMODB
These bits will be read/write by user if ASRCTR:ATSB=0, and can also be automatically updated by the
ASRC internal logic if ASRCTR:ATSB=1 (see ASRC Misc Control Register 1 for Pair C). These bits set the
selection of the post-processing configuration.

11–10 Pre-Processing Configuration for Conversion Pair B
PREMODB
These bits will be read/write by user if ASRCTR:ATSB=0, and can also be automatically updated by the
ASRC internal logic if ASRCTR:ATSB=1 (see ASRC Misc Control Register 1 for Pair C). These bits set the
selection of the pre-processing configuration.


ASRC_ASRCFG field descriptions (continued)

Field Description
11 Select passthrough mode. In this case, POSTMODB[1-0] have no use.
9–8 Post-Processing Configuration for Conversion Pair A
POSTMODA
These bits will be read/write by user if ASRCTR:ATSA=0, and can also be automatically updated by the
ASRC internal logic if ASRCTR:ATSA=1 (see ASRC Misc Control Register 1 for Pair C). These bits set the
selection of the post-processing configuration.

7–6 Pre-Processing Configuration for Conversion Pair A
PREMODA
These bits will be read/write by user if ASRCTR:ATSA=0, and can also be automatically updated by the
ASRC internal logic if ASRCTR:ATSA=1 (see ASRC Misc Control Register 1 for Pair C). These bits set the
selection of the pre-processing configuration.

11 Select passthrough mode. In this case, POSTMODA[1-0] have no use.
Reserved. Should be written as zero for compatibility.
15.7.5 ASRC Clock Source Register (ASRC_ASRCSR)

The ASRC clock source register (ASRCSR) is a read/write register that controls the
sources of the input and output clocks of the ASRC.
Table 15-8. Bit Clock Definitions
Bit Clk Name Definitions
0 ESAI RX clock
1 SSI-1 RX clock
2 SSI-2 RX clock
3 SSI-3 RX clock
4 SPDIF RX clock
5 MLB Bit clock
6 bit clock 6 should connect to one of the three pads: KEY_ROW3,GPIO_0,GPIO_18, which is
configured by register IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT
7 tied to zero
8 ESAI TX clock
9 SSI-1 TX clock
a SSI-2 TX clock
b SSI-3 TX clock

Table 15-8. Bit Clock Definitions (continued)

Bit Clk Name Definitions
c SPDIF TX clock
d bit clock d is configured by spdif1_clk_pred and spdif1_clk_podf in CCM_CDCDR, but it is
better to describe it also in CCM spec.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved AOCSC AOCSB AOCSA AICSC AICSB AICSA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRCSR field descriptions

Field Description
- Reserved
23–20 Output Clock Source C
AOCSC
0000 bit clock 0
0001 bit clock 1
0010 bit clock 2
0011 bit clock 3
0100 bit clock 4
0101 bit clock 5
0110 bit clock 6
0111 bit clock 7
1000 bit clock 8
1001 bit clock 9
1010 bit clock A
1011 bit clock B
1100 bit clock C
1101 bit clock D
1110 bit clock E
1111 clock disabled, connected to zero
19–16 Output Clock Source B
AOCSB
0000 bit clock 0
0001 bit clock 1
0010 bit clock 2
0011 bit clock 3
0100 bit clock 4
0101 bit clock 5
0110 bit clock 6
0111 bit clock 7
1000 bit clock 8
1001 bit clock 9
1010 bit clock A
1011 bit clock B

ASRC_ASRCSR field descriptions (continued)

Field Description
1100 bit clock C
1101 bit clock D
1110 bit clock E
15–12 Output Clock Source A
AOCSA
0000 bit clock 0
0001 bit clock 1
0010 bit clock 2
0011 bit clock 3
0100 bit clock 4
0101 bit clock 5
0110 bit clock 6
0111 bit clock 7
1000 bit clock 8
1001 bit clock 9
1010 bit clock A
1011 bit clock B
1100 bit clock C
1101 bit clock D
1110 bit clock E
11–8 Input Clock Source C
AICSC
0000 bit clock 0
0001 bit clock 1
0010 bit clock 2
0011 bit clock 3
0100 bit clock 4
0101 bit clock 5
0110 bit clock 6
0111 bit clock 7
1000 bit clock 8
1001 bit clock 9
1010 bit clock A
1011 bit clock B
1100 bit clock C
1101 bit clock D
1110 bit clock E
7–4 Input Clock Source B
AICSB
0000 bit clock 0
0001 bit clock 1
0010 bit clock 2
0011 bit clock 3
0100 bit clock 4

ASRC_ASRCSR field descriptions (continued)

Field Description
0101 bit clock 5
0110 bit clock 6
0111 bit clock 7
1000 bit clock 8
1001 bit clock 9
1010 bit clock A
1011 bit clock B
1100 bit clock C
1101 bit clock D
1110 bit clock E
AICSA Input Clock Source A
0000 bit clock 0

0001 bit clock 1
0010 bit clock 2
0011 bit clock 3
0100 bit clock 4
0101 bit clock 5
0110 bit clock 6
0111 bit clock 7
1000 bit clock 8
1001 bit clock 9
1010 bit clock A
1011 bit clock B
1100 bit clock C
1101 bit clock D
1110 bit clock E
15.7.6 ASRC Clock Divider Register 1 (ASRC_ASRCDR1)
The ASRC clock divider register (ASRCDR1) is a read/write register that controls the
division factors of the ASRC input and output clock sources.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved AOCDB AOCPB AOCDA AOCPA AICDB AICPB AICDA AICPA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ASRC_ASRCDR1 field descriptions

Field Description
- Reserved
23–21 Output Clock Divider B
AOCDB
Specify the divide ratio of the output clock divider B. The divide ratio may range from 1 to 8 (AOCDB[2:0] =
000 to 111).
20–18 Output Clock Prescaler B
AOCPB
Specify the prescaling factor of the output prescaler B. The prescaling ratio may be any power of 2 from 1
to 128.
17–15 Output Clock Divider A
AOCDA
Specify the divide ratio of the output clock divider A. The divide ratio may range from 1 to 8 (AOCDA[2:0] =
000 to 111).
14–12 Output Clock Prescaler A
AOCPA
Specify the prescaling factor of the output prescaler A. The prescaling ratio may be any power of 2 from 1
to 128.
11–9 Input Clock Divider B
AICDB
Specify the divide ratio of the input clock divider B. The divide ratio may range from 1 to 8 (AICDB[2:0] =
000 to 111).
8–6 Input Clock Prescaler B
AICPB
Specify the prescaling factor of the input prescaler B. The prescaling ratio may be any power of 2 from 1 to
128.
5–3 Input Clock Divider A
AICDA
Specify the divide ratio of the input clock divider A. The divide ratio may range from 1 to 8 (AICDA[2:0] =
000 to 111).
AICPA Input Clock Prescaler A
Specify the prescaling factor of the input prescaler A. The prescaling ratio may be any power of 2 from 1 to
128.
15.7.7 ASRC Clock Divider Register 2 (ASRC_ASRCDR2)
The ASRC clock divider register (ASRCDR2) is a read/write register that controls the
division factors of the ASRC input and output clock sources.
Address: 203_4000h base + 1Ch offset = 203_401Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved AOCDC AOCPC AICDC AICPC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ASRC_ASRCDR2 field descriptions

Field Description
- Reserved
11–9 Output Clock Divider C
AOCDC
Specify the divide ratio of the output clock divider C. The divide ratio may range from 1 to 8 (AOCDC[2:0]
= 000 to 111).
8–6 Output Clock Prescaler C
AOCPC
Specify the prescaling factor of the output prescaler C. The prescaling ratio may be any power of 2 from 1
to 128.
5–3 Input Clock Divider C
AICDC
Specify the divide ratio of the input clock divider C. The divide ratio may range from 1 to 8 (AICDC[2:0] =
000 to 111).
AICPC Input Clock Prescaler C
Specify the prescaling factor of the input prescaler C. The prescaling ratio may be any power of 2 from 1
to 128.

15.7.8 ASRC Status Register (ASRC_ASRSTR)
The ASRC status register (ASRSTR) is a read/write register used by the processor core to
examine the status of the ASRC block and clear the overload interrupt request and AOLE
flag bit. Read the status register will return the current state of ASRC.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSLCNT
AOOLC
AOOLB
AOOLA
ATQOL
AIOLC
R
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AODOC
AODOB
AODOA
AODFC
AODFB
AODFA
AIDUC
AIDUB
AIDUA
AIDEC
AIDEB
AIDEA
AIOLB
AIOLA
FPWT
AOLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRSTR field descriptions

Field Description
- Reserved

ASRC_ASRSTR field descriptions (continued)

Field Description
21 DSL Counter Input to FIFO ready
DSLCNT
When set, this bit indicates that new DSL counter information is stored in the internal ASRC FIFO. When
clear, this bit indicates that new DSL counter information is in the process of storage into the internal
ASRC FIFO.
When ASRIER:AFPWE=1, the rising edge of this signal will propose an interrupt request.
Writing any value with this bit set will clear the interrupt request proposed by the rising edge of this bit.
20 Task Queue FIFO overload
ATQOL
When set, this bit indicates that task queue FIFO logic is oveloaded. This may help to check the reason
why overload interrupt happens.
The bit is cleared when writing ASRSTR:AOLE as 1.
19 Pair C Output Task Overload
AOOLC
When set, this bit indicates that pair C output task is oveloaded. This may help to check the reason why
overload interrupt happens.
18 Pair B Output Task Overload
AOOLB
When set, this bit indicates that pair B output task is oveloaded. This may help to check the reason why
17 Pair A Output Task Overload
AOOLA
When set, this bit indicates that pair A output task is oveloaded. This may help to check the reason why
16 Pair C Input Task Overload
AIOLC
When set, this bit indicates that pair C input task is oveloaded. This may help to check the reason why
15 Pair B Input Task Overload
AIOLB
When set, this bit indicates that pair B input task is oveloaded. This may help to check the reason why
14 Pair A Input Task Overload
AIOLA
When set, this bit indicates that pair A input task is oveloaded. This may help to check the reason why
13 Output Data Buffer C has overflowed
AODOC
When set, this bit indicates that output data buffer C has overflowed. When clear, this bit indicates that
output data buffer C has not overflowed
12 Output Data Buffer B has overflowed
AODOB
When set, this bit indicates that output data buffer B has overflowed. When clear, this bit indicates that
output data buffer B has not overflowed


Field Description
11 Output Data Buffer A has overflowed
AODOA
When set, this bit indicates that output data buffer A has overflowed. When clear, this bit indicates that
output data buffer A has not overflowed
10 Input Data Buffer C has underflowed
AIDUC
When set, this bit indicates that input data buffer C has underflowed.
When clear, this bit indicates that input data buffer C has not underflowed.
9 Input Data Buffer B has underflowed
AIDUB
When set, this bit indicates that input data buffer B has underflowed.
When clear, this bit indicates that input data buffer B has not underflowed.
8 Input Data Buffer A has underflowed
AIDUA
When set, this bit indicates that input data buffer A has underflowed.
When clear, this bit indicates that input data buffer A has not underflowed.
7 FP is in wait states
FPWT
This bit is for debug only.
When set, this bit indicates that ASRC is in wait states.
When clear, this bit indicates that ASRC is not in wait states.
6 Overload Error Flag
AOLE
When set, this bit indicates that the task rate is too high for the ASRC to handle. The reasons for overload
may be:
- too high input clock frequency,
- too high output clock frequency,
- incorrect selection of the pre-filter,
- low ASRC processing clock,
- too many channels,
- underrun,
- or any combination of the reasons above.
Since the ASRC uses the same hardware resources to perform various tasks, the real reason for the
overload is not straight forward, and it should be carefully analyzed by the programmer.
If ASRIER:AOLIE=1, an interrupt will be proposed when this bit is set.
Write any value with this bit set as one into the status register will clear this bit and the interrupt request
proposed by this bit.
5 Number of data in Output Data Buffer C is greater than threshold
AODFC


Field Description
When set, this bit indicates that number of data already existing in ASRDORC is greater than threshold
and the processor can read data from ASRDORC. When AODFC is set, the ASRC generates data output
C interrupt request to the processor, if enabled (that is, ASRIER:ADOEC = 1). A DMA request is always
generated when the AODFC bit is set, but a DMA transfer takes place only if a DMA channel is active and
triggered by this event.
4 Number of data in Output Data Buffer B is greater than threshold
AODFB
When set, this bit indicates that number of data already existing in ASRDORB is greater than threshold
and the processor can read data from ASRDORB. When AODFB is set, the ASRC generates data output
B interrupt request to the processor, if enabled (that is, ASRIER:ADOEB = 1). A DMA request is always
generated when the AODFB bit is set, but a DMA transfer takes place only if a DMA channel is active and
3 Number of data in Output Data Buffer A is greater than threshold
AODFA
When set, this bit indicates that number of data already existing in ASRDORA is greater than threshold
and the processor can read data from ASRDORA. When AODFA is set, the ASRC generates data output
A interrupt request to the processor, if enabled (that is, ASRIER:ADOEA = 1). A DMA request is always
generated when the AODFA bit is set, but a DMA transfer takes place only if a DMA channel is active and
2 Number of data in Input Data Buffer C is less than threshold
AIDEC
When set, this bit indicates that number of data still available in ASRDIRC is less than threshold and the
processor can write data to ASRDIRC. When AIDEC is set, the ASRC generates data input C interrupt
request to the processor, if enabled (that is, ASRIER:ADIEC = 1). A DMA request is always generated
when the AIDEC bit is set, but a DMA transfer takes place only if a DMA channel is active and triggered by
this event.
1 Number of data in Input Data Buffer B is less than threshold
AIDEB
When set, this bit indicates that number of data still available in ASRDIRB is less than threshold and the
processor can write data to ASRDIRB. When AIDEB is set, the ASRC generates data input B interrupt
request to the processor, if enabled (that is, ASRIER:ADIEB = 1). A DMA request is always generated
when the AIDEB bit is set, but a DMA transfer takes place only if a DMA channel is active and triggered by
this event.
0 Number of data in Input Data Buffer A is less than threshold
AIDEA
When set, this bit indicates that number of data still available in ASRDIRA is less than threshold and the
processor can write data to ASRDIRA. When AIDEA is set, the ASRC generates data input A interrupt
request to the processor, if enabled (that is, ASRIER:ADIEA = 1). A DMA request is always generated
when the AIDEA bit is set, but a DMA transfer takes place only if a DMA channel is active and triggered by
this event.
15.7.9 ASRC Parameter Register n (ASRC_ASRPMnn)

Parameter registers determine the performance of ASRC.
The parameter registers must be initialized by software before ASRC is enabled.
Recommended values are given in ASRC Misc Control Register 1 for Pair C below,

Table 15-9. ASRC Parameter Registers (ASRPM1~ASRPM5)

Register Offset Access Reset Value Recommend Value
asrcpm1 0x40 R/W 0x00_0000 0x7fffff
asrcpm2 0x44 R/W 0x00_0000 0x255555
asrcpm3 0x48 R/W 0x00_0000 0xff7280
asrcpm4 0x4C R/W 0x00_0000 0xff7280
asrcpm5 0x50 R/W 0x00_0000 0xff7280

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PARAMETER_VALUE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRPMnn field descriptions

Field Description
- Reserved
PARAMETER_ See recommended values table.
VALUE
15.7.10 ASRC ASRC Task Queue FIFO Register 1

(ASRC_ASRTFR1)
The register defines and shows the parameters for ASRC inner task queue FIFOs.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TF_FILL
Reserved Reserved TF_BASE Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRTFR1 field descriptions

Field Description
- Reserved
19–13 Current number of entries in task queue FIFO.
TF_FILL

ASRC_ASRTFR1 field descriptions (continued)

Field Description
12–6 Base address for task queue FIFO. Set to 0x7C.
TF_BASE
Reserved. Should be written as zero for compatibility.
15.7.11 ASRC Channel Counter Register (ASRC_ASRCCR)
The ASRC channel counter register (ASRCCR) is a read/write register that sets and
reflects the current specific input/output FIFO being accessed through shared peripheral
bus for each ASRC conversion pair.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved ACOC ACOB ACOA ACIC ACIB ACIA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRCCR field descriptions

Field Description
- Reserved
23–20 The channel counter for Pair C's output FIFO
ACOC
These bits stand for the current channel being accessed through shared peripheral bus for Pair C's output
FIFO's usage. The value can be any value between [0, ANCC-1]
19–16 The channel counter for Pair B's output FIFO
ACOB
These bits stand for the current channel being accessed through shared peripheral bus for Pair B's output
FIFO's usage. The value can be any value between [0, ANCB-1]
15–12 The channel counter for Pair A's output FIFO
ACOA
These bits stand for the current channel being accessed through shared peripheral bus for Pair A's output
FIFO's usage. The value can be any value between [0, ANCA-1]
11–8 The channel counter for Pair C's input FIFO
ACIC
These bits stand for the current channel being accessed through shared peripheral bus for Pair C's input
FIFO's usage. The value can be any value between [0, ANCC-1]
7–4 The channel counter for Pair B's input FIFO
ACIB
These bits stand for the current channel being accessed through shared peripheral bus for Pair B's input
FIFO's usage. The value can be any value between [0, ANCB-1]
ACIA The channel counter for Pair A's input FIFO
These bits stand for the current channel being accessed through shared peripheral bus for Pair A's input
FIFO's usage. The value can be any value between [0, ANCA-1]

15.7.12 ASRC Data Input Register for Pair x (ASRC_ASRDIn)
These registers are the interface registers for the audio data input of pair A,B,C
respectively. They are backed by FIFOs.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRDIn field descriptions

Field Description
- Reserved
DATA Audio data input
15.7.13 ASRC Data Output Register for Pair x (ASRC_ASRDOn)
These registers are the interface registers for the audio data output of pair A,B,C
respectively. They are backed by FIFOs.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DATA
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRDOn field descriptions

Field Description
- Reserved
DATA Audio data output

15.7.14 ASRC Ideal Ratio for Pair A-High Part

(ASRC_ASRIDRHA)
The ideal ratio registers (ASRIDRHA, ASRIDRLA) hold the ratio value IDRATIOA.
IDRATIOA = FsinA/FsoutA = TsoutA/TsinA is a 32-bit fixed point value with 26 fractional
bits. This value is only useful when ASRCTR:{USRA, IDRA}=2'b11.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved IDRATIOA_H
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRIDRHA field descriptions

Field Description
- Reserved
- Reserved
IDRATIOA_H IDRATIOA[31:24]. High part of ideal ratio value for pair A
15.7.15 ASRC Ideal Ratio for Pair A -Low Part

(ASRC_ASRIDRLA)
The ideal ratio registers (ASRIDRHA, ASRIDRLA) hold the ratio value IDRATIOA.
IDRATIOA = FsinA/FsoutA = TsoutA/TsinA is a 32-bit fixed point value with 26 fractional
bits. This value is only useful when ASRCTR:{USRA, IDRA}=2'b11.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved IDRATIOA_L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRIDRLA field descriptions

Field Description
- Reserved
IDRATIOA_L IDRATIOA[23:0]. Low part of ideal ratio value for pair A

15.7.16 ASRC Ideal Ratio for Pair B-High Part

(ASRC_ASRIDRHB)
The ideal ratio registers (ASRIDRHB, ASRIDRLB) hold the ratio value IDRATIOB.
IDRATIOB = FsinB/FsoutB = TsoutB/TsinB is a 32-bit fixed point value with 26 fractional
bits. This value is only useful when ASRCTR:{USRB, IDRB}=2'b11.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved IDRATIOB_H
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRIDRHB field descriptions

Field Description
- Reserved
- Reserved
IDRATIOB_H IDRATIOB[31:24]. High part of ideal ratio value for pair B.
15.7.17 ASRC Ideal Ratio for Pair B-Low Part (ASRC_ASRIDRLB)
The ideal ratio registers (ASRIDRHB, ASRIDRLB) hold the ratio value IDRATIOB.
IDRATIOB = FsinB/FsoutB = TsoutB/TsinB is a 32-bit fixed point value with 26 fractional
bits. This value is only useful when ASRCTR:{USRB, IDRB}=2'b11.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved IDRATIOB_L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRIDRLB field descriptions

Field Description
- Reserved
IDRATIOB_L IDRATIOB[23:0]. Low part of ideal ratio value for pair B.

15.7.18 ASRC Ideal Ratio for Pair C-High Part

(ASRC_ASRIDRHC)
The ideal ratio registers (ASRIDRHC, ASRIDRLC) hold the ratio value IDRATIOC.
IDRATIOC = FsinC/FsoutC = TsoutC/TsinC is a 32-bit fixed point value with 26 fractional
bits. This value is only useful when ASRCTR:{USRC, IDRC}=2'b11.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved IDRATIOC_H
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRIDRHC field descriptions

Field Description
- Reserved
- Reserved
IDRATIOC_H IDRATIOC[31:24]. High part of ideal ratio value for pair C.
15.7.19 ASRC Ideal Ratio for Pair C-Low Part (ASRC_ASRIDRLC)
The ideal ratio registers (ASRIDRHC, ASRIDRLC) hold the ratio value IDRATIOC.
IDRATIOC = FsinC/FsoutC = TsoutC/TsinC is a 32-bit fixed point value with 26 fractional
bits. This value is only useful when ASRCTR:{USRC, IDRC}=2'b11.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved IDRATIOC_L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRIDRLC field descriptions

Field Description
- Reserved
IDRATIOC_L IDRATIOC[23:0]. Low part of ideal ratio value for pair C.

15.7.20 ASRC 76 kHz Period in terms of ASRC processing clock

(ASRC_ASR76K)
The register (ASR76K) holds the period of the 76 kHz sampling clock in terms of the
ASRC processing clock with frequency FsASRC. ASR76K = FsASRC/Fs76k. Reset value is
0x0A47 which assumes that FsASRC=200 MHz. This register is used to help the ASRC
internal logic to decide the pre-processing and the post-processing options automatically
(see ASRC Misc Control Register 1 for Pair C and ASRC Misc Control Register 1 for
Pair C). In a system when FsASRC = 133 MHz, the value should be assigned explicitly as
0x06D6 in user application code.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved ASR76K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 1 1
ASRC_ASR76K field descriptions

Field Description
- Reserved
- Reserved
ASR76K Value for the period of the 76 kHz sampling clock.

15.7.21 ASRC 56 kHz Period in terms of ASRC processing clock

(ASRC_ASR56K)
The register (ASR56K) holds the period of the 56 kHz sampling clock in terms of the
ASRC processing clock with frequency FsASRC. ASR56K = FsASRC/Fs56k. Reset value is
0x0DF3 which assumes that FsASRC = 200 MHz. This register is used to help the ASRC
internal logic to decide the pre-processing and the post-processing options automatically
(see ASRC Misc Control Register 1 for Pair C and ASRC Misc Control Register 1 for
Pair C). In a system when FsASRC = 133 MHz, the value should be assigned explicitly as
0x0947 in user application code.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved ASR56K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1
ASRC_ASR56K field descriptions

Field Description
- Reserved
- Reserved
ASR56K Value for the period of the 56 kHz sampling clock

15.7.22 ASRC Misc Control Register for Pair A

(ASRC_ASRMCRA)
The register (ASRMCRA) is used to control Pair A internal logic.

Address: 203_4000h base + A0h offset = 203_40A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYPASSPOLY
EXTTHRSHA
BUFSTALLA
ZEROBUFA
R
OUTFIFO_
Reserved Reserved THRESHOL
A
W
DA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RSYNOFA
RSYNIFA
OUTFIFO_THRESHOLDA Reserved INFIFO_THRESHOLDA

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRMCRA field descriptions

Field Description
- Reserved
23 Initialize buf of Pair A when pair A is enabled. Always clear option.
ZEROBUFA
This bit is used to control whether the buffer is to be zeroized when pair A is enabled.
1 Don't zeroize the buffer

0 Zeroize the buffer
22 Use external thresholds for FIFO control of Pair A
EXTTHRSHA
This bit will determine whether the FIFO thresholds externally defined in this register is used to control
ASRC internal FIFO logic for pair A.
1 Use external defined thresholds.

0 Use default thresholds.
21 Stall Pair A conversion in case of Buffer Near Empty/Full Condition
BUFSTALLA
This bit will determine whether the near empty/full FIFO condition will stall the rate conversion for pair A.
This option can only work when external ratio is used.
Near empty condition is the condition when input FIFO has less than 4 useful samples per channel.
Near full condition is the condition when the output FIFO has less than 4 vacant sample words to fill per
channel.

ASRC_ASRMCRA field descriptions (continued)

Field Description
1 Stall Pair A conversion in case of near empty/full FIFO conditions.
0 Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
20 Bypass Polyphase Filtering for Pair A
BYPASSPOLYA
This bit will determine whether the polyphase filtering part of Pair A conversion will be bypassed.
1 Bypass polyphase filtering.

0 Don't bypass polyphase filtering.
- Reserved. Should be written as zero for future compatibility.
17–12 The threshold for Pair A's output FIFO per channel
OUTFIFO_
These bits stand for the threshold for Pair A's output FIFO per channel. Possible range is [0,63].
THRESHOLDA
When the value is n, it means that:
when the number of output FIFO fillings of the pair is greater than n samples per channel, the output data
ready flag is set;
when the number of output FIFO fillings of the pair is less than or equal to n samples per channel, the
output data ready flag is automatically cleared.
11 Re-sync Input FIFO Channel Counter
RSYNIFA
If bit set, force ASRCCR:ACIA=0. If bit clear, untouch ASRCCR:ACIA.
10 Re-sync Output FIFO Channel Counter
RSYNOFA
If bit set, force ASRCCR:ACOA=0. If bit clear, untouch ASRCCR:ACOA.
INFIFO_ The threshold for Pair A's input FIFO per channel
THRESHOLDA
These bits stand for the threshold for Pair A's input FIFO per channel. Possible range is [0,63].
when the number of input FIFO fillings of the pair is less than n samples per channel, the input data
needed flag is set;
when the number of input FIFO fillings of the pair is greater than or equal to n samples per channel, the
input data needed flag is automatically cleared.

15.7.23 ASRC FIFO Status Register for Pair A (ASRC_ASRFSTA)
The register (ASRFSTA) is used to show Pair A internal FIFO conditions.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OAFA
R OUTFIFO_FILLA
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IAEA
R OUTFIFO_FILLA INFIFO_FILLA
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRFSTA field descriptions

Field Description
- Reserved
23 Output FIFO is near Full for Pair A
OAFA
This bit is to indicate whether the output FIFO of Pair A is near full.
18–12 The fillings for Pair A's output FIFO per channel
OUTFIFO_FILLA
These bits stand for the fillings for Pair A's output FIFO per channel. Possible range is [0,64].

ASRC_ASRFSTA field descriptions (continued)

Field Description
11 Input FIFO is near Empty for Pair A
IAEA
This bit is to indicate whether the input FIFO of Pair A is near empty.
INFIFO_FILLA The fillings for Pair A's input FIFO per channel
These bits stand for the fillings for Pair A's input FIFO per channel. Possible range is [0,64].
15.7.24 ASRC Misc Control Register for Pair B

(ASRC_ASRMCRB)
The register (ASRMCRB) is used to control Pair B internal logic.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYPASSPOLY
EXTTHRSHB
BUFSTALLB
ZEROBUFB
R
OUTFIFO_
B
W
DB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RSYNOFB
RSYNIFB
OUTFIFO_THRESHOLDB Reserved INFIFO_THRESHOLDB

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRMCRB field descriptions

Field Description
- Reserved
23 Initialize buf of Pair B when pair B is enabled
ZEROBUFB
This bit is used to control whether the buffer is to be zeroized when pair B is enabled.

22 Use external thresholds for FIFO control of Pair B
EXTTHRSHB

ASRC_ASRMCRB field descriptions (continued)

Field Description
ASRC internal FIFO logic for pair B.

21 Stall Pair B conversion in case of Buffer Near Empty/Full Condition
BUFSTALLB
This bit will determine whether the near empty/full FIFO condition will stall the rate conversion for pair B.
channel.
1 Stall Pair B conversion in case of near empty/full FIFO conditions.

0 Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
20 Bypass Polyphase Filtering for Pair B
BYPASSPOLYB
This bit will determine whether the polyphase filtering part of Pair B conversion will be bypassed.

17–12 The threshold for Pair B's output FIFO per channel
OUTFIFO_
These bits stand for the threshold for Pair B's output FIFO per channel. Possible range is [0,63].
THRESHOLDB
ready flag is set;
RSYNIFB
If bit set, force ASRCCR:ACIB=0. If bit clear, untouch ASRCCR:ACIB.
RSYNOFB
If bit set, force ASRCCR:ACOB=0. If bit clear, untouch ASRCCR:ACOB.
INFIFO_ The threshold for Pair B's input FIFO per channel
THRESHOLDB
These bits stand for the threshold for Pair B's input FIFO per channel. Possible range is [0,63].
needed flag is set;

15.7.25 ASRC FIFO Status Register for Pair B (ASRC_ASRFSTB)
The register (ASRFSTB) is used to show Pair B internal FIFO conditions.

Address: 203_4000h base + ACh offset = 203_40ACh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OAFB
R OUTFIFO_FILLB
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IAEB
R OUTFIFO_FILLB INFIFO_FILLB
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRFSTB field descriptions

Field Description
- Reserved
23 Output FIFO is near Full for Pair B
OAFB
This bit is to indicate whether the output FIFO of Pair B is near full.
18–12 The fillings for Pair B's output FIFO per channel
OUTFIFO_FILLB
These bits stand for the fillings for Pair B's output FIFO per channel. Possible range is [0,64].

ASRC_ASRFSTB field descriptions (continued)

Field Description
11 Input FIFO is near Empty for Pair B
IAEB
This bit is to indicate whether the input FIFO of Pair B is near empty.
INFIFO_FILLB The fillings for Pair B's input FIFO per channel
These bits stand for the fillings for Pair B's input FIFO per channel. Possible range is [0,64].
15.7.26 ASRC Misc Control Register for Pair C

(ASRC_ASRMCRC)
The register (ASRMCRC) is used to control Pair C internal logic.

Address: 203_4000h base + B0h offset = 203_40B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYPASSPOLY
EXTTHRSHC
BUFSTALLC
ZEROBUFC
R
OUTFIFO_
C
W
DC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RSYNOFC
RSYNIFC
OUTFIFO_THRESHOLDC Reserved INFIFO_THRESHOLDC

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRMCRC field descriptions

Field Description
- Reserved
23 Initialize buf of Pair C when pair C is enabled
ZEROBUFC
This bit is used to control whether the buffer is to be zeroized when pair C is enabled.

22 Use external thresholds for FIFO control of Pair C
EXTTHRSHC

ASRC_ASRMCRC field descriptions (continued)

Field Description
ASRC internal FIFO logic for pair C.

21 Stall Pair C conversion in case of Buffer Near Empty/Full Condition
BUFSTALLC
This bit will determine whether the near empty/full FIFO condition will stall the rate conversion for pair C.
channel.
1 Stall Pair C conversion in case of near empty/full FIFO conditions.

0 Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
20 Bypass Polyphase Filtering for Pair C
BYPASSPOLYC
This bit will determine whether the polyphase filtering part of Pair C conversion will be bypassed.

17–12 The threshold for Pair C's output FIFO per channel
OUTFIFO_
These bits stand for the threshold for Pair C's output FIFO per channel. Possible range is [0,63].
THRESHOLDC
ready flag is set;
RSYNIFC
If bit set, force ASRCCR:ACIC=0. If bit clear, untouch ASRCCR:ACIC.
RSYNOFC
If bit set, force ASRCCR:ACOC=0. If bit clear, untouch ASRCCR:ACOC.
INFIFO_ The threshold for Pair C's input FIFO per channel
THRESHOLDC
These bits stand for the threshold for Pair C's input FIFO per channel. Possible range is [0,63].
needed flag is set;

15.7.27 ASRC FIFO Status Register for Pair C (ASRC_ASRFSTC)
The register (ASRFSTC) is used to show Pair C internal FIFO conditions.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OAFC
R OUTFIFO_FILLC
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IAEC
R OUTFIFO_FILLC INFIFO_FILLC
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRFSTC field descriptions

Field Description
- Reserved
23 Output FIFO is near Full for Pair C
OAFC
This bit is to indicate whether the output FIFO of Pair C is near full.
18–12 The fillings for Pair C's output FIFO per channel
OUTFIFO_FILLC
These bits stand for the fillings for Pair C's output FIFO per channel. Possible range is [0,64].

ASRC_ASRFSTC field descriptions (continued)

Field Description
11 Input FIFO is near Empty for Pair C
IAEC
This bit is to indicate whether the input FIFO of Pair C is near empty.
INFIFO_FILLC The fillings for Pair C's input FIFO per channel
These bits stand for the fillings for Pair C's input FIFO per channel. Possible range is [0,64].
15.7.28 ASRC Misc Control Register 1 for Pair X

(ASRC_ASRMCR1n)
The register (ASRMCR1x) is used to control Pair x internal logic (for data alignment
etc.).
The bit assignment for all the input data formats is the same as that supported by the SSI.
Address: 203_4000h base + C0h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OMSB
OSGN
OW16
Reserved IWD IMSB Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASRC_ASRMCR1n field descriptions

Field Description
- Reserved
11–9 Data Width of the input FIFO
IWD
These three bits will determine the bitwidth for the audio data into ASRC
All other settings not shown are reserved.
3'b000 24-bit audio data.

ASRC_ASRMCR1n field descriptions (continued)

Field Description
8 Data Alignment of the input FIFO
IMSB
This bit will determine the data alignment of the input FIFO.
1 MSB aligned.
0 LSB aligned.
2 Data Alignment of the output FIFO
OMSB
This bit will determine the data alignment of the output FIFO.
1 MSB aligned.
0 LSB aligned.
1 Sign Extension Option of the output FIFO
OSGN
This bit will determine the sign extension option of the output FIFO.
1 Sign extension.
0 No sign extension.
0 Bit Width Option of the output FIFO
OW16
This bit will determine the bit width option of the output FIFO.
1 16-bit output data

0 24-bit output data.

Chapter 16
Digital Audio Multiplexer (AUDMUX)
16.1 Overview
The Digital Audio Multiplexer (AUDMUX) provides a programmable interconnect
device for voice, audio, and synchronous data routing between Synchronous Serial
Interface Controller (SSI) and audio/voice codec’s (also known as coder-decoders)
peripheral serial interfaces.
This section includes a top level diagram that shows the functional organization of the
block, including all off-chip signals.
AUDMUX allows the users to reconfigure the audio system signal routing through
programming, as opposed to altering the PCB design. The full description of the block is
in Functional Description.
Figure 16-1 shows the block diagram.

Overview
Fsn, Clkn TxDn, RxDn
AUD6_TFS, AUD6_TXC
AUD6_TFS
AUD6_TXC
AUD6_RFS, AUD6_RXC
AUD1_TFS, AUD1_TXC
AUD6_RFS
AUD1_TFS Port 6
AUD6_RXC
AUD1_TXC
AUD1_RFS, AUD1_RXC Da6
AUD1_RFS Db6
Port 1 AUD1_RXC
AUD5_TFS, AUD5_TXC
Da1 AUD5_TFS
Db1 AUD5_TXC
AUD5_RFS, AUD5_RXC
AUD5_RFS
AUD2_TFS, AUD2_TXC AUD5_RXC Port 5
AUD2_TFS
Da5
AUD2_TXC
Db5
AUD2_RFS, AUD2_RXC
AUD2_RFS AUD4_TFS, AUD4_TXC
Port 2 AUD2_RXC AUD4_TFS
AUD4_TXC
Da2 AUD4_RFS, AUD4_RXC
Db2
AUD4_RFS
AUD4_RXC Port 4
Da4
AUD7_TFS, AUD7_TXC Db4
AUD7_TFS
AUD3_TFS, AUD3_TXC
AUD7_TXC
AUD3_TFS
AUD7_RFS, AUD7_RXC
AUD3_TXC
AUD7_RFS
AUD3_RFS, AUD3_RXC
Port 7 AUD7_RXC
AUD3_RFS
Da7 AUD3_RXC Port 3
Db7
Da3
Db3
Figure 16-1. AUDMUX Block Diagram

Chapter 16 Digital Audio Multiplexer (AUDMUX)
AUDMUX supports single source to single destination connectivity or single source to

multiple destination connectivity.
AUDMUX includes two types of interfaces: Internal ports and External ports. Internal
ports are hard wired to Synchronous Serial Interface Controller (SSI). The connection
between each SSI and AUDMUX’s Internal ports cannot be modified, however, routing
of the signals connected to each of the internal port can be routed within AUDMUX.
External ports are connected to IOMUX module where the ports connect to off-chip
audio devices and serial interfaces of other processors. The connectivity of the External
port and IOMUX cannot be configured, but the output or input of the signal can be routed
easily by setting the appropriate AUDMUX registers.
16.1.1 Features
Key features of the block include:
• Three internal ports
• Four external ports
• Full 6-wire SSI interfaces for asynchronous receive and transmit
• Configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interfaces
• Independent Tx/Rx Frame sync and clock direction selection for host or peripheral
• Each host interface's capability to connect to any other host or peripheral interface in
a point-to-point or point-to-multipoint (network mode)
16.1.2 Modes and Operations

The AUDMUX supports the modes described in Operating Modes.

The following table describes the external signals of AUDMUX:
Table 16-1. AUDMUX External Signals
AUD3_RXC (RXC) Receive clock signal CSI0_DAT10 ALT1 IO
AUD3_RXD (RXD) Data receive signal CSI0_DAT7 ALT4 IO
AUD3_RXFS (RXFS) Receive Frame sync signal CSI0_DAT11 ALT1 IO
AUD3_TXC (TXC) Transmit clock signal CSI0_DAT4 ALT4 IO

Clocks
Table 16-1. AUDMUX External Signals (continued)

AUD3_TXD (TXD) Data transmit signal CSI0_DAT5 ALT4 IO
AUD3_TXFS (TXFS) Transmit Frame sync signal CSI0_DAT6 ALT4 IO
AUD4_RXC (RXC) Receive clock signal DISP0_DAT19 ALT4 IO
SD2_CMD ALT3
AUD4_RXD (RXD) Data receive signal DISP0_DAT23 ALT3 IO
SD2_DAT0 ALT3
AUD4_RXFS (RXFS) Receive Frame sync signal DISP0_DAT18 ALT4 IO
SD2_CLK ALT3
AUD4_TXC (TXC) Transmit clock signal DISP0_DAT20 ALT3 IO
SD2_DAT3 ALT3
AUD4_TXD (TXD) Data transmit signal DISP0_DAT21 ALT3 IO
SD2_DAT2 ALT3
AUD4_TXFS (TXFS) Transmit Frame sync signal DISP0_DAT22 ALT3 IO
SD2_DAT1 ALT3
EIM_D25 ALT6
AUD5_RXD (RXD) Data receive signal DISP0_DAT19 ALT3 IO
KEY_ROW1 ALT2
EIM_D24 ALT6
AUD5_TXC (TXC) Transmit clock signal DISP0_DAT16 ALT3 IO
KEY_COL0 ALT2
AUD5_TXD (TXD) Data transmit signal DISP0_DAT17 ALT3 IO
KEY_ROW0 ALT2
AUD5_TXFS (TXFS) Transmit Frame sync signal DISP0_DAT18 ALT3 IO
KEY_COL1 ALT2
AUD6_RXD (RXD) Data receive signal DI0_PIN4 ALT2 IO
AUD6_TXC (TXC) Transmit clock signal DI0_PIN15 ALT2 IO
AUD6_TXD (TXD) Data transmit signal DI0_PIN2 ALT2 IO
AUD6_TXFS (TXFS) Transmit Frame sync signal DI0_PIN3 ALT2 IO
16.3 Clocks
This section provides information about AUDMUX clocking including clock inputs and
the clock diagram.

The following table describes the clock source for AUDMUX. Please see Clock
Controller Module (CCM) for clock setting, configuration and gating information.
Table 16-2. AUDMUX Clocks
ipg_clk_s ipg_clk_root Peripheral access clock
16.3.1 Clock Inputs

The IP Bus read/write clock-peripheral clock (ipg_clk_s) is an input to the AUDMUX. It
is used for all AUDMUX register accesses. It is driven only when there is an AUDMUX
access on the IP Bus.
16.3.2 Clock Diagram

The figure below shows the clocking used in the AUDMUX.
AIPS AUDMUX
ips_module_en_audmux
LPG
Low Power Gate
CRM
IP Interface
Clock Registers
Peripheral clock
Gating
Cell
Peripheral clock
Figure 16-2. AUDMUX Clocking Scheme

Default Register Configuration
16.3.3 Clocking Restrictions

• Since the AUDMUX requires only peripheral clock, it places no restrictions on the
bus frequency.
• All registers in the AUDMUX are control registers so their values will not change
frequently. These values will be programmed when changing between use cases (not
during operation in a particular mode).
16.4 Default Register Configuration

There are two configuration registers for each port. Each pair of configuration registers is
identical for each port; however, the default values following a reset differ as shown in
the Memory Map.
Default Port Configuration, describes the default configuration of the ports.
16.4.1 Default Port Configuration

After a reset, each port defaults to normal mode (PDCRn[MODE] = 0) with synchronous
timing mode (PTCRn[SYN] = 1) enabled.
The default port-to-port connections are as follows:
• Port 1 to Port 6
• Port 6 provides the clock and frame sync.
• Port 7 to Port 7 (in data loopback mode)
• Clock and frame syncs are inputs.

This section provides a complete functional description of the AUDMUX.

16.5.1 Operating Modes

This section describes all functional operation modes of the AUDMUX.
Figure 16-1 shows the AUDMUX block diagram.
All of the ports are essentially identical; there is no functional difference among Ports 1
through 7. The main difference is whether a port is hard wired to synchronous serial
interface (SSI) or hard wired to the chip's pads. Each of the connection is hard wired to
specific AUDMUX port. AUDMUX provides flexibility in routing the signal within the
module, but all Internal and External port connections are fixed to specific configuration.
All ports can be configured as four- or six-wire interfaces. When configured as a six-wire
interface, Receive Frame Sync (RXFS) and Receive Clock (RXC) signals of SSI
interface enable the serial interface to be used in asynchronous mode with separate
receive and transmit clocks.
AUDMUX supports both Normal mode (not to be confused with SSI’s Normal Mode),
External Network mode and Internal Network mode. The definition of each mode will be
given in the next section.
All ports have a TXRXEN bit to provide flexibility in supporting network mode
configurations. The TXRXEN bit reverses the functions of transmit and receive data lines
where the transmit line is configured as receive and transmit line to be configured as
transmit line. This function is provided so that mastership of the serial bus can be passed
among multiple external devices connected to a single port.
In addition to supporting the External Network mode (default), all ports support an
internal network mode:
• With internal network mode, single point-to-multipoint network configuration with
an arbitrary number of slaves can be supported if the external slaves are put into the
high-impedance state (as defined in the SSI network mode protocol) and have pull-up
resistors on their TxD pins. (Alternatively, this can be viewed as requiring a pull-up
resistor on the corresponding AUDMUX RxD pin.)
Bit clock direction selection enables each port to be configured as a master or slave in the
flow.
Possible scenarios include:

• SSI (hard wired to internal port) transmits data to a voice codec and a BT (Blue
tooth) codec (both on external Port 4Port 5) and the Bottom Connector (on external
Port 5Port 6) simultaneously using network mode. SSI is configured as the master.
• An external processor (external port - Port 4Port 3) drives a voice codec and a BT
codec (both on external Port 5Port 4) and the Bottom Connector (on Port 6Port 5)
simultaneously using network mode. The external processor is the master.
16.5.1.1 Port Receive Data Modes

Each port has logic to select which data lines are used to create the RXD line for the
corresponding host interface.
Figure 16-3 shows the logic used to create the RXD line for Port 1. This logic has the
following modes of operation (as determined by MODE:
• Normal (not to be confused with SSI's normal mode)
• Internal network mode
The subsequent sections describe the various modes of the port receive data logic. The
following terms are used to define the operation of the AUDMUX:
• Network mode- Time-Division Multiplexed protocol for sending unique data to
multiple devices on a serial bus or single devices with multi-channel capabilities.
• Internal network mode-Physical bus configuration where multiple serial buses are
effectively connected within the AUDMUX via digital logic to create point-to
multipoint connectivity. An arbitrary number of devices are supported. Devices must
be put into the high-impedance state as specified by the network mode protocol.
• External network mode-Physical bus configuration where multiple serial buses are
electrically connected together on a printed circuit board (that is, external to the
AUDMUX). Devices must put their TXD lines into the high-impedance state as
specified by the network mode protocol. TXD lines of devices must be pulled high.

INMMASK[7:0]
1
AUDMUX boundary
Signal selection for
internal network mode
1
RxD
(Port x)
0
TxD1_in
TxD2_in
MODE
TxD3_in
TxD4_in
TxD5_in
TxD6_in
TxD7_in
RXDSEL[2:0]
Figure 16-3. Receive Data Logic for Port x
16.5.1.1.1 Normal Mode

In normal mode (MODE = 0) , not to be confused with SSI's Normal Mode, the port is
connected in a single device point-to-single device port configuration (as a master or a
slave) and the RXDSEL[2:0] setting selects the transmit signal from any port. In normal
mode, any data format can be used (that is, SSI normal mode, SSI network mode, AC-97,
and others.
If a user wishes to transmit SSI1’s data (TXD) to port 5, PDCR5’s RXDSEL[2:0] must
be set to 000b. If the clock (TCK) and frame clock (TFS) are sent out to the external
device from SSI1, PTCR5’s TFSEL[3:0] and TCSEL[3:0] must be set to 0000b (port1)
and 0000b (port1), while setting PTCR5’s TFSDIR and TCLKDIR to 1.
If either or both of the clocks are to be received from external device to SSI1, PTCR5’s
TCLKDIR and/or TFSDIR must be set to 0 (input), and PTCR1’s TFSEL[3:0] and/or
TCLKDIR[3:0] to 0100b (port5).
Likewise, if a user wishes to receive serial data from Port 4 and send the receiving data to
SSI2’s RXD, one must set PDCR2’s RXDSEL[2:0] to 11b. If the frame (RXFS) and bit
clocks (RXC) are to be received from the external device, PTCR2’s RFSEL[3:0] and
RCSEL[3:0] must be set to 011b while PTCR4’s RFSDIR and RCLKDIR set to 0.

16.5.1.1.2 Internal Network Mode

In internal network mode (MODE = 1) , the output of the AND gate is routed (via the
output of the port) to the RXD signal of the corresponding host interface.
The INMMASK bit vector selects the transmit signals of the ports that are to be
connected in network mode. The transmit signals received at the AUDMUX ports
(TxDn_in) are ANDed together to form the output. In internal network mode, only one
device can be transmitting in its predesignated timeslot and all other transmit signals
must remain high (be in high-impedance state and pulled-up). Therefore, non-active
signals in the selection will be high and do not influence the output of the AND gate.
Network mode is a protocol where a master SSI is connected to more than one slave SSI
device and communication occurs on a time-slotted frame. Though network mode can
allow master-slave and slave-slave communication, internal network mode supports only
master-slave communication.
There are two scenarios where internal network mode can be used with external network
mode:
1. Slave-only devices are attached to an external port.
2. A master device is attached to an external port and all slave devices connected to the
same external port are disabled.
NOTE
When internal network mode is enabled at an external port,
RXDSEL[3:0] for RxDn_obe selection is ignored and RxD_obe
is always driven high (that is, asserted for all timeslots). All
slave devices connected to the same port must be disabled.
Internal Network Mode Example 1
SSI_m and SSI_n are used with Port 3 in internal network mode as shown in Figure 16-4.
No pull-up resistors are required because the interfaces combined in internal network
mode are on-chip interfaces.

AUDMUX
Port 3 Device
Port 1
Port 4
KEY
SSI_n Port 2
Internal
Port x Network Mode
Port 5 Enabled
SSI_m Port 7 Port x Active
Port 6
Port x Inactive
Figure 16-4. Block Diagram For Example 1
See Figure 16-5 for the timing diagram of Example 1. The clock and frame sync signals
show the bit and frame timing for the serial bus. The vertical dashed lines divide the
frame into four timeslots.
The data lines for SSI_m and SSI_n (as well as their output enables) are shown. Note that
the on-chip interfaces drive a logic '1' when their output enables are logic '0'. The
combined TXD line, which is the logical AND of the individual TXD lines, is used for
Port 3's TXD line.

CLK ... ... ... ...
FS
SSI_m TxD T0 (SSI_m LEFT) T1 (SSI_m RIGHT) T2 T3
SSI_m OE
SSI_n TxD T0 T1 T2 (SSI_n LEFT) T3 (SSI_n RIGHT)
SSI_n OE
Combined TxD T0 (SSI_m LEFT) T1 (SSI_m RIGHT) T2 (SSI_n LEFT) T3 (SSI_n RIGHT)
(Port 3 RxD)
Figure 16-5. Example Using Internal Ports For Transmit Data

The SSI, Port 3, and Port 4 are used with Port 5 in internal network mode, as shown in
the following figure. Note that Port 3 and Port 4 are external ports. Therefore, pull-up
resistors are required on the Port 3 RXD and Port 4 RXD pins. This example shows the
timing associated with using adjacent timeslots for the SSI, Port 3 and Port 4 .

Pull-up Resistor On
AUDMUX TxDATA Required
Port 3 Device
SSI Port 1 Pull-up Resistor On

TxDATA Required
Port 4 Device
KEY
Port 2
Internal
Port x Network Mode
Port 5 Device Enabled
Port 7 Active
Port x
Port 6
Port x Inactive
The resistance value of the pull-up resistors must be sufficiently high such that a value of
'0' can be pulled up to logic '1' within half of a period of the bitclock. The required
resistance must be no larger than:
Rmax = 1 / (2 * fbc * C) where:
• fbc is the frequency of the bitclock
• C is the total system capacitance (ICs, board traces, and so on)
The following figure shows the timing diagram for this example. The clock and frame
sync signals show the bit and frame timing for the serial bus. The vertical dashed lines
divide the frame into four timeslots.
The data lines for the SSI, Port 3 and Port 4 are shown. Note that the SSI transmits a
logic '1' when its corresponding output enable is a logic '0'. The data lines from Port 3 and
Port 4 at the pad are pulled high by pull-up resistors when they are in the high-impedance
state. The data lines from Port 3 and Port 4 at the AUDMUX are pure digital signals and
are constantly driven. The combined TXD line, which is the logical AND of the SSI, Port
3 and Port 4's TXD lines, is used for Port 5's TXD line.

Note the highlighted areas in the Figure 16-7. This shows the transition time that occurs
while a TXD line is being pulled high. In this example, this transition time is a maximum
of 1/2 the period of the serial bitclock. This prevents corruption of the first data bit of the
next timeslot. It is critical that the pull-up resistance is sufficient for the given bitclock
frequency and system capacitance.
Note that hysteresis should be enabled at Port 3's RXD pad and Port 4's RXD pad to
prevent the digital signals created by the pad from toggling rapidly during the pull-up
period. The pads typically require a transition within 25ns unless hysteresis is enabled.
Instead of using hysteresis, one could select a pull-up resistor sufficiently high to pull-up
the signal at the pad within 25 ns; however, that would result in a higher resistance value
and higher current drain.
CLK
... ... ... ...
FS
SSI TxD T0 T1 T2 T3
SSI OE
1/2 Bit
1/2 Bit
Port 3 TxD HiZ HiZ

T1 T3
(At SoC Pin)
Port 3 TxD T1 T3
(At AUDMUX)
1/2 Bit
Port 4 TxD HiZ HiZ T2 HiZ

(At SoC Pin)
Port 4 TxD T2
(At AUDMUX)
Combined TxD T0 T1 T2 T3
(Port 5 RxD)
Figure 16-7. Example Using External Ports for Transmit Data in Consecutive Timeslots

The SSI and Port 3 are used with Port 5 in internal network mode as shown in the
following figure. Note that Port 3 is an external port. Therefore, a pull-up resistor is
required on the Port 3TXD pin. This example shows the timing associated with inserting
empty timeslots after the timeslots have been used by external ports.

Pull-up Resistor On
AUDMUX TxDATA Required
Port 3 Device
SSI Port 1
Port 4
KEY
Port 2
Internal
Port x Network Mode
Port 5 Device Enabled
Port 7 Port x Active
Port 6
Port x Inactive
The resistance value of the pull-up resistors must be sufficiently high such that a value of
'0' can be pulled up to logic '1' by the time that the next occupied timeslot occurs. This
allows a much weaker pull-up to be used as compared to Example 2. The required
resistance must be no larger than:
Rmax = (4 * n + 1) / (2* fbc * C) where:
• n is the number of bits per timeslot
• fbc is the frequency of the bitclock
• C is the total system capacitance (ICs, board traces, and so on)
The figure below shows the timing diagram for this example. The clock and frame sync
signals show the bit and frame timing for the serial bus. The vertical dashed lines divide
the frame into four timeslots.
The data lines for the SSI and Port 3 are shown. Note that the SSI transmits a logic '1'
when its corresponding output enable is a logic '0'. The data line from Port 3 at the pad is
pulled high by a pull-up resistor when they are in the high-impedance state. The data line
from Port 3 at the AUDMUX is a pure digital signal and is constantly driven. The
combined TXD line, which is the logical AND of the SSI and Port 3's TXD lines, is used
for Port 5's RXD line.

Note the highlighted area in the Figure 16-9. This shows the transition time that occurs
while Port 3's TXD line is being pulled high. In this example, this transition time is a
maximum of two timeslots plus 1/2 the period of the serial bitclock. This prevents
corruption of the first data bit of the next timeslot. It is critical that the pull-up resistance
is sufficient for the given bitclock frequency and system capacitance.
Note that hysteresis must be enabled at Port 3's RXD pad to prevent the digital signal
created by the pad from toggling rapidly during the extended pull-up period. The pads
typically require a transition within 25 ns unless hysteresis is enabled.
CLK
... ... ... ...
FS
SSI TxD T0 T1 T2 T3
SSI OE
1/2 Bit
Port 3 TxD HiZ T1 HiZ HiZ

(At SoC Pin)
Port 3 TxD T1
(At AUDMUX)
Combined TxD T0 T1
(Port 5 RxD)
Figure 16-9. Example Using External Ports For Transmit Data In Nonconsecutive
Timeslots
16.5.1.1.3 Transmit Data Output Enable Assertion

The TXD line from the internal network mode master (connected at any internal port) is
put into the high-impedance state at the pad depending upon the assertion or deassertion
of TxD_obe, its corresponding output enable generated by the network mode master.
In the case of an external network mode master (connected at an external port), the
corresponding TxD_obe is always asserted after the port data register configuration.

16.5.1.2 Tx/Rx Switch and External Network Mode

External network mode is the traditional network mode connection. It is called external
network mode to differentiate from the internal network mode. In external network mode,
devices are connected to a single external port in a star or multi-drop configuration.
In network mode, there can be only one master (driving the frame sync and clock source)
with the other devices configured in normal slave mode or network slave mode. Unlike
internal network mode, both master-slave and slave-slave communication can take place
in external network mode. Codec devices transmit on a single timeslot while processor
serial interfaces (that is, SSI) can process more than one timeslot of data while in network
master or slave mode.
The following figure shows the Tx/Rx data switch. RxD_obe is the output buffer enable
signal and RxD_out is the data transmit signal from the serial interface. The TxD_in
signal is the receive data signal going towards the RXDSEL muxes of all ports.
D_TxRx is the data pin which serves as the chip-level transmit data pin when the TxRx
switch is not enabled. D_RxTx is the data pin which serves as the chip-level receive data
pin when the TxRx switch is not enabled. The roles of these pins are reversed when the
TxRx switch is enabled.
When TXRXEN is disabled (TXRXEN=0), RxD_out is routed to D_TxRx and D_RxTx
is routed to TxD_in. The output buffer enable, selected by RXDSEL[2:0], is routed to
Db_obe.
When the Tx/Rx switch is enabled (TXRXEN=1), RxD_out is routed to D_RxTx and
D_TxRx is routed to TxD_in. The output buffer enable, selected by RXDSEL[2:0], is
routed to Da_obe.
If the RXDSELn[2:0] field for any Port n is configured to select data from an internal
port, the output buffer enable is selected by RXDSELn[2:0] and is routed to Dan_obe/
Dbn_obe. In the case when the RXDSELn[2:0] field for Port n is configured to select
data from an external port, the output buffer enable is always high and routed to
Dan_obe/Dbn_obe, depending on the TXRXENn switch configuration.

AUDMUX BOUNDARY Pin Interface Boundary
TXRXEN
Db_obe
RxD_obe
IOPAD
D_TxRx
Db_out
RxD_out
Db_in
Da_obe
IOPAD
D_RxTx
Da_out
Da_in
TxD_in
TX/RX SWITCH
Figure 16-10. Tx/Rx Switch
16.5.1.3 Timing Modes

The AUDMUX ports are constructed as 6-wire interfaces. However, they can be used
either in synchronous or asynchronous modes as determined by the SYN bit.
16.5.1.3.1 Synchronous Mode (4-Wire Interface)

In Synchronous mode, each port set in SYN=1 will be a 4-wire interface (that is, RXD,
TXD, TXC, TXFS). In this setup, receive data timing is determined by TXC and TXFS..

As shown in the following figure, SSI signals interfaced to Port x signals are routed to
Port y. When SYN = 1 the 6-wire signal from SSI is reduced to 4-wire within the internal
logic.
TFS_in, RFS_in, TCLK_in, and RCLK_in are the input frame sync and bit clocks from
the serial interface (Port x) with their corresponding output buffer enable signals (_obe).
TFS_out, RFS_out, TCLK_out, and RCLK_out are the frame sync and bit clocks that are
transmitted to the serial interface from the other ports.
The TFS_out and TCLK_out are selected at Port x by the TFSEL and TCSEL mux
settings, respectively. RFS_out and RCLK_out are selected at Port x by the RFSEL and
RCSEL mux settings, respectively. Similarly, in the external direction, Port y is
configured as a 4-wire port; TFSEL selects the FS_obe and FS_out signals. In this mode,
the configuration of RFSEL and RCSEL is not used, since the RFS_out and RCLK_out
pins at Port y are not available.

AUDMUX Boundary AUDMUX Boundary Pin Boundary

RFSELx[3:0] TFSELy[3:0]
PORT x PORT y
TFS_obe
TFS_in
FS_obe
TFS_out
FS_out TXFS
RFS_obe
FS_in
RFS_in IOPAD
RFS_out
TFSELx[3:0] TFSn_obe, TFSn_in, RFSn_obe,

RFSn_in and FSn_in to/from other ports
RCSELx[3:0] TFSELy[3:0]
TCLK_obe
TCLK_in
CLK_obe
TCLK_out
TXC
CLK_out
RCLK_obe
CLK_in
RCLK_in IOPAD
RCLK_out
TCSELx[3:0] TCLKn_obe, TCLKn_in, RCLKn_obe

RCLKn_in and CLKn_in to/from other ports
Figure 16-11. Frame Sync and Clock Routing When External Port Is 4-Wire
16.5.1.3.2 Asynchronous Mode (6-Wire Interface)

In Asynchronous mode, the port has a 6-wire interface (meaning RXD, TXD, TXC,
TXFS, RXC, RXFS). This mode has additional receive clock (RXC) and frame sync
(RXFS) signals as compared to the synchronous or 4-wire interface.
As shown in the figures below, Port x signals can be routed to Port y, producing 6-wire to
6-wire port connectivity.

TFS_in, RFS_in, TCLK_in, and RCLK_in are input frame sync and bit clocks from the
serial interface (Port x) with their corresponding output buffer enable signals (_obe).
TFS_out, RFS_out, TCLK_out, and RCLK_out are the frame sync and bit clocks that are
transmitted to the serial interface from the other ports.
TFS_out and TCLK_out are selected by the TFSEL and TCSEL mux settings,
respectively. RFS_out and RCLK_out are selected by the RFSEL and RCSEL mux
settings, respectively. Similarly, in the external direction, the TFSEL selects the
TxFS_obe and TxFS_out signals and TCSEL selects the TxCLK_obe and TxClk_out
signals. The RFSEL selects the RxFS_obe and RxFS_out signals and RCSEL selects the
RxCLK_obe and RxCLK_out signals.
NOTE
Because FS_in and CLK_in from external interfaces are also
routed to the TFSEL and TCSEL muxes of the external ports,
these signals do not have corresponding buffer enable signals.
Consequently, their corresponding inputs to the TFSEL and
TCSEL mux of the external ports have to be tied high.

AUDMUX Boundary AUDMUX Boundary Pin Boundary

RFSELx[3:0] TFSELy[3:0]
PORT x PORT y
TFS_obe
TFS_in
TFS_obe
TFS_out
TFS_out TXFS
RFS_obe
TFS_in
RFS_in IOPAD
RFS_out
TFSELx[3:0] TFSn_obe, TFSn_in, RFSn_obe,

RFSELx[3:0] RFSELy[3:0]
TFS_obe
TFS_in
RFS_obe
TFS_out
RXFS
RFS_out
RFS_obe RFS_in
RFS_in IOPAD
RFS_out
TFSELx[3:0] TFSn_obe, TFSn_in, RFSKn_obe

Figure 16-12. Frame Sync Routing When External Port Is 6-Wire

AUDMUX Boundary TCSELy[3:0] AUDMUX Boundary Pin Boundary

RCSELx[3:0]
PORT x PORT y
TCLK_obe
TCLK_in
TCLK_obe
TCLK_out
TXC
TCLK_out
RCLK_obe
TCLK_in
RCLK_in IOPAD
RCLK_out
TClkn_obe, TClkn_in, RClkn_obe,

RClkn_in and Clkn_in to/from other ports
RCSELx[3:0] RCSELy[3:0]
TCLK_obe
TCLK_in
RCLK_obe
TCLK_out
RXC
RCLK_out
RCLK_obe RCLK_in
RCLK_in IOPAD
RCLK_out
TCSELx[3:0] TCLKn_obe, TCLKn_in, RCLKn_obe

RCLKn_in and CLKn_in to/from other ports
Figure 16-13. Clock Routing When External Port Is 6 Wire
16.5.2 Connectivity Between Ports

Four basic types of connections are provided by the AUDMUX:
• Internal port to external port
• External port to external port
• Internal port to internal port
• Loopback
The corresponding data connections are described in the following sections.
16.5.2.1 Internal Port to External Port Connectivity

The internal port is connected to a processor's serial interface. TxD_obe is the buffer
enable signal from the serial interface, TxD_in is the input transmit data from the serial
interface to the AUDMUX, and RxD_out is the receive data output from the AUDMUX
to the serial interface.
RXDSEL[2:0] of the external port selects the buffer enable signal (TxD_obe) and
transmit data output (TxD_out) signal from the TxD_obe and RxD_in signals.
RXDSEL[2:0] is a common signal to both selection muxes.
NOTE
Because buffer TxD_in signals from external interfaces do not
have corresponding buffer enable signals, their buffer enable
signals into the selection mux are tied high. This will ensure
that selection of TxD_in, as RxD_out will also drive the
RxD_obe output high.
Transmit Data from the serial interface goes into the RXDSEL data mux and comes out
as RxD_out. RxD_out is routed to Da_TxRx when TXRXEN is disabled and to D_RxTx
when TXRXEN is enabled. Similarly, D_RxTx is routed to TxD_in when TXRXEN is
disabled and D_TxRx is routed to TxD_in when TXRXEN is enabled. The routing of
frame syncs is shown in Figure 16-12 and the routing of interface clocks is shown in
Figure 16-10.
If internal network mode is disabled, then RXDSEL selects the TxD_in, which is sent
from the AUDMUX to the serial interface connected at Port x. When the internal network
mode is selected, RxD_out is constructed by ANDing selected TxD_in signals from the
ports (as determined by INMMASK).
If there is more than one device attached to the external port at D_TxRx and D_RxTx and
one of the devices is a network master, then two conditions must be noted:
1. When the external master is enabled in network mode, then the serial interface at
Port x must be configured as a slave (normal or network mode). No Tx/Rx switching
is required.
2. When the external master is disabled and the serial interface at Port x and other slave
devices must communicate, then the serial interface at Port x must be configured as a
network mode master and the Tx/Rx switch at Port y must be enabled (TXRXEN=1).
This will ensure that the transmit and receive paths are connected appropriately.

To communicate with more than one port, internal network mode can be enabled at Port
x. In internal network mode, it is possible to communicate with any device attached to the
other ports. Internal network mode shall be enabled at the port that is the SSI network
mode master.
16.5.2.2 External Port to External Port Connectivity

External ports can communicate with external ports directly.
External ports can communicate together in three ways:
1. Each port's receive logic is configured in normal mode (MODE = 0) . Each port's
RXDSEL[2:0] field is configured to select the other port's transmit data. Bit fields
associated with clock/frame sync selection and direction are configured for each port.
Either port can be the master.
2. One port is configured in internal network mode (MODE = 1) . All desired data lines
are combined by the AND gate as determined by INMMASK[7:0]. Since an external
port is being used as the internal network mode master, all other devices on the same
AUDMUX port as the internal network mode master must be disabled. This
configuration can be used with a combination of internal and external ports. All
external ports must have a pull-up resistor on its RXD pin. Bit fields associated with
clock/frame sync selection and direction are configured for each port. Any port can
be the master.
16.5.2.3 Internal Port to Internal Port Connectivity

Internal ports can communicate with other internal ports directly, thereby providing a
means for synchronous interprocessor communication.
Internal ports can communicate together in two ways:
1. Each port's receive logic is configured in normal mode (MODE = 0) . Each port's
RXDSEL[2:0] field is configured to select the other port's transmit data. Bit fields
associated with clock/frame sync selection and direction are configured for each port.
Either port can be the master.
2. One port is configured in internal network mode (MODE = 1) . All desired data lines
are combined by the AND gate as determined by INMMASK[7:0]. This
configuration can be used with a combination of internal and external ports. All
external ports must have a pull-up resistor on its RXD pin. Bit fields associated with
clock/frame sync selection and direction are configured for each port. Any port can
be the master.

AUDMUX Memory Map/Register Definition
16.5.2.4 Loopback Connectivity

AUDMUX ports can communicate with themselves in order to provide loopback
functionality. Port x can route its TXD signal to its own RxD_out signal by setting
RXDSELx[2:0] to its own port number. This is supported by all ports in the AUDMUX.
In addition, ports can provide loopback support in internal network mode. With internal
network mode, the internal network mode master can loop its TXD signal (combined
with those of other ports, if desired) back into its RxD_out signal. Port x's INMMASK
should be set such that bit (x - 1) is clear in order to enable the loopback.
16.6 AUDMUX Memory Map/Register Definition
This section includes the block memory map and detailed descriptions of all registers. For
the base address of a specific sub-block instantiation, see the system memory map in this
manual.
The AUDMUX memory map is shown in the following table.
AUDMUX memory map
Absolute
Width Section/
(in bits) page
(hex)
21D_8000 Port Timing Control Register 1 (AUDMUX_PTCR1) 32 R/W AD40_0800h 16.6.1/539
21D_8004 Port Data Control Register 1 (AUDMUX_PDCR1) 32 R/W 0000_A000h 16.6.2/541
21D_8008 Port Timing Control Register 2 (AUDMUX_PTCR2) 32 R/W A500_0800h 16.6.3/542
21D_800C Port Data Control Register 2 (AUDMUX_PDCR2) 32 R/W 0000_8000h 16.6.4/544
21D_8010 Port Timing Control Register 3 (AUDMUX_PTCR3) 32 R/W 9CC0_0800h 16.6.5/545
21D_8014 Port Data Control Register 3 (AUDMUX_PDCR3) 32 R/W 0000_6000h 16.6.6/547
21D_8018 Port Timing Control Register 4 (AUDMUX_PTCR4) 32 R/W 0000_0800h 16.6.7/548
21D_801C Port Data Control Register 4 (AUDMUX_PDCR4) 32 R/W 0000_4000h 16.6.8/550
21D_8020 Port Timing Control Register 5 (AUDMUX_PTCR5) 32 R/W 0000_0800h 16.6.9/551
16.6.10/
21D_8024 Port Data Control Register 5 (AUDMUX_PDCR5) 32 R/W 0000_2000h
553
16.6.11/
21D_8028 Port Timing Control Register 6 (AUDMUX_PTCR6) 32 R/W 0000_0800h
554
16.6.12/
21D_802C Port Data Control Register 6 (AUDMUX_PDCR6) 32 R/W 0000_0000h
556
16.6.13/
21D_8030 Port Timing Control Register 7 (AUDMUX_PTCR7) 32 R/W 0000_0800h
557

AUDMUX memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
16.6.14/
21D_8034 Port Data Control Register 7 (AUDMUX_PDCR7) 32 R/W 0000_C000h
559
16.6.1 Port Timing Control Register 1 (AUDMUX_PTCR1)
PTCR1 is the Port Timing Control Register for Port 1.

Address: 21D_8000h base + 0h offset = 21D_8000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCLKDIR
TCLKDIR
TFS_ RFS_
TFSEL[3:0] TCSEL[3:0] RFSEL[3:0]
DIR DIR
W
Reset 1 0 1 0 1 1 0 1 0 1 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RCSEL[3:0] SYN
W
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
AUDMUX_PTCR1 field descriptions

Field Description
31 Transmit Frame Sync Direction Control. This bit sets the direction of the TXFS pin of the interface as an
TFS_DIR output or input. When set as an input, the TFSEL settings are ignored. When set as an output, the TFSEL
settings determine the source port of the frame sync.
0 TXFS is an input.
1 TXFS is an output.
30–27 Transmit Frame Sync Select. Selects the source port from which TXFS is sourced.
TFSEL[3:0]
0xxx Selects TXFS from port.
1xxx Selects RXFS from port.
x000 Port 1
x110 Port 7
x111 Reserved
26 Transmit Clock Direction Control. This bit sets the direction of the TXC pin of the interface as an output or
TCLKDIR input. When set as an input, the TCSEL settings are ignored. When set as an output, the TCSEL settings
determine the source port of the clock.

AUDMUX_PTCR1 field descriptions (continued)

Field Description
0 TXC is an input.
1 TXC is an output.
25–22 Transmit Clock Select. Selects the source port from which TXC is sourced.
TCSEL[3:0]
0xxx Selects TXC from port.
1xxx Selects RXC from port.
x000 Port 1
x110 Port 7
x111 Reserved
21 Receive Frame Sync Direction Control. This bit sets the direction of the RXFS pin of the interface as an
RFS_DIR output or input. When set as an input, the RFSEL settings are ignored. When set as an output, the RFSEL
0 RXFS is an input.
1 RXFS is an output.
20–17 Receive Frame Sync Select. Selects the source port from which RXFS is sourced. RXFS can be sourced
RFSEL[3:0] from TXFS and RXFS from other ports.

x000 Port 1
x110 Port 7
x111 Reserved
16 Receive Clock Direction Control. This bit sets the direction of the RXC pin of the interface as an output or
RCLKDIR input. When set as an input, the RCSEL settings are ignored. When set as an output, the RCSEL settings
NOTE: RCLKDIR and SYN should not be changed at the same time.
0 RXC is an input.
1 RXC is an output.
15–12 Receive Clock Select. Selects the source port from which RXC is sourced. RXC can be sourced from TXC
RCSEL[3:0] and RXC from other ports.

x000 Port 1
x110 Port 7
x111 Reserved
11 Synchronous/Asynchronous Select. When SYN is set, synchronous mode is chosen and the transmit and
SYN receive sections use common clock and frame sync signals (that is, the port is a 4-wire interface). When
SYN is cleared, asynchronous mode is chosen and separate clock and frame sync signals are used for
the transmit and receive sections (that is, the port is a 6-wire interface).
0 Asynchronous mode
1 Synchronous mode (default)
Reserved This read-only field is reserved and always has the value 0.

16.6.2 Port Data Control Register 1 (AUDMUX_PDCR1)
PDCR1 is the Port Data Control Register for Port 1.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
TXRXEN
RXDSEL[2:0] MODE INMMASK[7:0]

W
Reset 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
AUDMUX_PDCR1 field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
15–13 Receive Data Select. Selects the source port for the RXD data. RXDSEL is ignored if MODE = 1 (that is,
RXDSEL[2:0] Internal Network Mode is enabled).
xxx Port number for RXD

000 Port 1
110 Port 7
111 Reserved
12 Transmit/Receive Switch Enable. Swaps the transmit and receive signals.
TXRXEN
0 No switch (Transmit Pin = Transmit, Receive Pin = Receive)
1 Switch (Transmit Pin = Receive, Receive Pin = Transmit)
Reserved
8 Mode Select. This field selects the mode in which the port is to operate. The modes of operation include
MODE the following:
• Normal mode, in which the RXD from the port selected by RXDSEL is routed to the port.
• Internal Network mode in which RXD from other ports are ANDed together. RXDSEL is ignored.
INMMASK determines which RXD signals are ANDed together.
0 Normal mode
1 Internal Network mode

AUDMUX_PDCR1 field descriptions (continued)

Field Description
INMMASK[7:0] Internal Network Mode Mask. Bit mask that selects the ports from which the RXD signals are to be ANDed
together for internal network mode. Bit 6 represents RXD from Port 7 and bit0 represents RXD from Port
1.
0 Includes RXDn for ANDing

1 Excludes RXDn from ANDing

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCLKDIR
TCLKDIR
TFS_ RFS_
DIR DIR
W
Reset 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RCSEL[3:0] SYN
W
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

Field Description
0 TXFS is an input.
TFSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved


Field Description
0 TXC is an input.
1 TXC is an output.
TCSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 RXFS is an input.

x000 Port 1
x110 Port 7
x111 Reserved
0 RXC is an input.
1 RXC is an output.

x000 Port 1
x110 Port 7
x111 Reserved


Field Description
0 Asynchronous mode

Address: 21D_8000h base + Ch offset = 21D_800Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
TXRXEN
MODE
RXDSEL[2:0] INMMASK[7:0]
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
Reserved

000 Port 1
110 Port 7
111 Reserved
TXRXEN
Reserved


Field Description
MODE the following:
0 Normal mode
1.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCLKDIR
TCLKDIR
TFS_ RFS_
DIR DIR
W
Reset 1 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RCSEL[3:0] SYN
W
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

Field Description
0 TXFS is an input.


Field Description
TFSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 TXC is an input.
1 TXC is an output.
TCSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 RXFS is an input.

x000 Port 1
x110 Port 7
x111 Reserved
0 RXC is an input.
1 RXC is an output.

x000 Port 1
x110 Port 7
x111 Reserved


Field Description
0 Asynchronous mode

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
TXRXEN
MODE
W
Reset 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
Reserved

000 Port 1
110 Port 7
111 Reserved


Field Description
TXRXEN
Reserved
MODE the following:
0 Normal mode
1.

Port Timing Control Register for Port 4

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCLKDIR
TCLKDIR
TFS_ RFS_
DIR DIR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RCSEL[3:0] SYN
W
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0


Field Description
0 TXFS is an input.
TFSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 TXC is an input.
1 TXC is an output.
TCSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 RXFS is an input.

x000 Port 1
x110 Port 7
x111 Reserved
0 RXC is an input.
1 RXC is an output.


Field Description
x000 Port 1
x110 Port 7
x111 Reserved
0 Asynchronous mode

Address: 21D_8000h base + 1Ch offset = 21D_801Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
TXRXEN
MODE
W
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
Reserved


Field Description
000 Port 1
110 Port 7
111 Reserved
TXRXEN
Reserved
MODE the following:
0 Normal mode
1.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RCLKDIR
TCLKDIR
TFS_ RFS_
DIR DIR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RCSEL[3:0] SYN
W
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0


Field Description
0 TXFS is an input.
TFSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 TXC is an input.
1 TXC is an output.
TCSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 RXFS is an input.

x000 Port 1
x110 Port 7
x111 Reserved
0 RXC is an input.
1 RXC is an output.


Field Description
x000 Port 1
x110 Port 7
x111 Reserved
0 Asynchronous mode

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
TXRXEN
MODE
W
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
Reserved


Field Description
000 Port 1
110 Port 7
111 Reserved
TXRXEN
Reserved
MODE the following:
0 Normal mode
1.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RCLKDIR
TCLKDIR
TFS_ RFS_
DIR DIR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RCSEL[3:0] SYN
W
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0


Field Description
0 TXFS is an input.
TFSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 TXC is an input.
1 TXC is an output.
TCSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 RXFS is an input.

x000 Port 1
x110 Port 7
x111 Reserved
0 RXC is an input.
1 RXC is an output.


Field Description
x000 Port 1
x110 Port 7
x111 Reserved
0 Asynchronous mode

Address: 21D_8000h base + 2Ch offset = 21D_802Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
TXRXEN
MODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
Reserved


Field Description
000 Port 1
110 Port 7
111 Reserved
TXRXEN
Reserved
MODE the following:
0 Normal mode
1.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RCLKDIR
TCLKDIR
TFS_ RFS_
DIR DIR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RCSEL[3:0] SYN
W
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0


Field Description
0 TXFS is an input.
TFSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 TXC is an input.
1 TXC is an output.
TCSEL[3:0]
x000 Port 1
x110 Port 7
x111 Reserved
0 RXFS is an input.

x000 Port 1
x110 Port 7
x111 Reserved
0 RXC is an input.
1 RXC is an output.


Field Description
x000 Port 1
x110 Port 7
x111 Reserved
0 Asynchronous mode

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
TXRXEN
MODE
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
Reserved


Field Description
000 Port 1
110 Port 7
111 Reserved
TXRXEN
Reserved
MODE the following:
0 Normal mode
1.


Chapter 17
40-BIT Correcting ECC Accelerator (BCH)
17.1 Overview
The hardware ECC accelerator provides a forward error-correction function for
improving the reliability of various storage media that may be attached to the device.
For example, NAND flash devices use a spare area to store ecc codes to correct some
hard bit errors in data stored within the device, allowing higher device yields and,
therefore, lower NAND device costs.
The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is
capable of correcting from 2 to 40 single bit errors within a block of data no larger than
about 1900 bytes (512 bytes or 1024 bytes are typical) in applications such as protecting
data and resources stored on modern NAND flash devices. The correction level in the
BCH block is programmable to provide flexibility for varying applications and
configurations of flash page size. The design can be programmed to encode protection of
2 to 40 bit errors when writing flash and to correct the corresponding number of errors on
decode. The correction level when decoding MUST be programmed to the same
correction level as was used during the encode phase.
BCH-codes are a type of block-code, which implies that all error-correction is performed
over a block of N-symbols. The BCH operation will be performed over GF(213 = 8192)
or GF(214 = 16384), which is the Galois Field consisting of 8191 or 16383 one-bit
symbols. BCH-encoding (or encode for any block-code) can be performed by two
algorithms: systematic encoding or multiplicative encoding. Systematic encoding is the
process of reading all the symbols which constitute a block, dividing continuously these
symbols by the generator polynomial for the GF(8192) or GF(16384) and appending the
resulting t parity symbols to the block to create a BCH codeword (where t is the number
of correctable bits).

Overview
The BCH encode process creates t*13 (or t*14)-bit parity symbols for each data block
when the data is written to the flash device. The parity symbols are written to the flash
device after the corresponding data block, and together these are collectively called the
codeword. The codeword can be used during the decode process to correct errors that
occur in either the data or parity blocks.
The BCH decoder processes code words in a 4-step fashion:
1. Syndrome Calculation (SC): This is the process of reading in all of the symbols of
the codeword and continuously dividing by the generator polynomial for the field.
2*t syndromes must be calculated for each codeword and inspection of the
syndromes determines if there are errors: a non-zero set of syndromes indicates one
or more errors. This process is implemented parallel hardware to minimize
processing time since it must be done every time the decode is performed.
2. Key Equation Solver (KES): The syndromes represent 2t-linear equations with 2t-
unknown variables. The process of solving these equations and selecting from the
numerous solutions constitutes the KES module. When the KES block completes its
operations, it generates an error locator polynomial (sigma) that is used in the
proceeding block to determine the locations and values of the errors.
3. Chien Search (CS): This block takes input from the KES block and uses the Chien
Algorithm for finding the locations of the errors based on the error locator
polynomial. The method basically involves substituting all 8191 symbols from the
GF(8192) or 16383 symbols from the GF(16383) into the locator polynomial. All
evaluations that produce a zero solution indicate locations of the various errors. Since
each located error corresponds to a single bit, the bit in the original data may be
corrected by simply flipping the polarity of the incorrect location.
4. Correction: this block has to convert the symbol index and mask information to
memory byte indexes and masks.
The BCH block, shown in the figure, was designed to operate in a pipelined fashion to
maximize throughput. Aside from the initial latency to fill the pipeline stages, the BCH
throughput is about 7/4 cycles/byte. Thus, the bottleneck in performing NAND reads and
error corrections is the BCH rate. Current GPMI read rates are approximately 1/2 cycles/
byte maximally for the current generation of NAND flash. Fortunately, BCH has a
different master clock from GPMI, this gives some flexibility to match the throughput
rate. The CPU is not directly involved in generating parity symbols, checking for errors,
or correcting them.

Chapter 17 40-BIT Correcting ECC Accelerator (BCH)
AXI
APBH APBH Bridge/DMA
BCH Engine
BCH
GPMI Programmable
Programmable Registers
Registers
Transfer Controls
Write Data Parity Write Data

Generation
GPMI
NAND synpar AXI
CONTROLLER master
Syndrome
Read Data Read Data &
Calculation
transfer
syndromes FSM
Key
Equation
Solver
error-locator polynomial
Chien corrections
Search
GPMI clock domain
Figure 17-1. Hardware BCH Accelerator
17.2 Operation
Before performing any NAND flash read or write operations, software should first
program the BCH's flash layout registers (see Flash Page Layout) to specify how data is
to be formatted on the flash device. The BCH hardware allows full programmability over
the flash page layout to enable users flexibility in balancing ECC correction levels and
ever-changing flash page sizes.
To initiate a NAND Flash write, software will program a GPMI DMA operation. The
DMA need only program the GPMI control registers (and handle the requisite flash
addressing handshakes) since the BCH will handle all data operations using its AXI bus
interface. The BCH will then send the data to the GPMI controller to be written to flash

Operation
as it computes the parity symbols. At the end of each data block the BCH will insert the
parity symbols into the data stream so that the GPMI sees only a continuous stream of
data to be written.
NAND Flash read operations operate in a similar manner. As the GPMI controller reads
the device, all data is sent to the BCH hardware for error detection/correction. The BCH
controller writes all incoming read data to system memory and in parallel computes the
syndromes used to detect bit errors. If errors are detected within a block, the BCH
hardware activates the error correction logic to determine where bit errors have occurred
and ultimately correct them in the data buffer in system memory. After an entire flash
page has been read and corrected, the BCH will signal an interrupt to the CPU.
The figure below indicates how data read from the GPMI is operated on within the BCH
hardware. As the BCH receives data from the GPMI (top row), it is written to memory by
the BCH's Bus Interface Unit (BIU) (second row). For blocks requiring correction, the
KES logic will be activated after the entire block has been received. Once the error
locator polynomial has been computed, the corrections are determined by the Chien
Search and fed back to the BIU, which performs a read, modify, write operation on the
buffer in memory to correct the data.
ECC Done
GPMI/ Read Read Read Read Read Read Read Read Interrupt
Syndrome Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7
Write Write Write Write Write Write Write Write

Block 0 Block 1 Block 2 / Block 3 / Block 4 / Block 5 / Block 6 / Block 7 /
BIU
Correct Correct Correct Correct Correct Correct Correct Correct
Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7
KES KES KES KES KES KES KES KES

KES
CS CS CS CS CS CS CS CS
Chien Search
Figure 17-2. Block Pipeline while Reading Flash
17.2.1 BCH Limitations and Assumptions

• The BCH is programmable to support 2 to 40 bit error correction. ECC0 is supported
as a pass-through, non-correcting mode.
• Data block sizes must be a multiple of 4 bytes and be aligned in system memory.
• The BCH supports a programmable number of metadata/auxiliary data bytes, from 0
to 255.

• Metadata will be written at the beginning of the flash page to facilitate fast access for
filesystem operations.
• Metadata may be treated as an independent block for ECC purposes or combined
with the first data block to conserve bits in the flash.
• The BCH does not support a partial page write (this can be accomplished by
programming the BCH layout registers such that the BCH only sees a portion of the
page).
• Flash read operations can read the entire page or the first block on the page.
• The BCH also supports a memory-to-memory mode of operation that does not
require the use of DMA or the GPMI.
17.2.2 Flash Page Layout

The BCH supports a fully programmable flash page layout. The BCH maintains four
independent layout registers that can describe four completely different NAND devices
or layouts.
When the BCH initiates an operation, it selects one of the layouts by using the chip select
as an index into the BCH_LAYOUTSELECT register that determines which layout
should be used for the operation.
Three possible (generic) flash layout schemes are supported, as indicated in the figure
below. (In each case, the metadata size may also be programmed to 0 bytes). Metadata
may either be combined with the first block of data or the size of the first data block can
be programmed to 0 to allow the metadata to be protected by its own ECC parity bits.

Operation
Separate ECC over Metadata
parity
parity
parity
parity
parity
parity
meta d0 d1 d2 dn-1 dn
10B 512B 512B 512B 512B 512B
Block 0 Block 1 Block 2

Size=10B Size=512B Size=512B
ECC=4 ECC=14 ECC=14
Combined Metadata & Block 0, unbalanced ECC coverage
parity
parity
parity
parity
parity
meta d0 d1 d2 dn-1 dn
10B 512B 512B 512B 512B 512B

ECC=16 ECC=16 ECC=16
Combined Metadata & Block 0, balanced ECC coverage
parity
parity
parity
parity
parity
meta d0 d1 d2
2 dn-1 dn
32B 484B 516B 516B 516B 516B

ECC=14 ECC=14 ECC=14
Figure 17-3. FLASH Page Layout Options
Each layout is determined by a pair of registers that define the following parameters:
• DATA0_SIZE: Indicates the number of data bytes in the first block on the page (this
should not include parity or metadata bytes). This should be set to 0 when the
metadata is to be covered separately with its own ECC. This must be a multiple of 4
bytes.
• ECC0: Indicates the ECC level to be used for the first block on the flash
(data0+metadata).
• META_SIZE: Indicates the number of bytes (from 0-255) that are stored as
metadata.
• NBLOCKS: Indicates the number of subsequent DATAN blocks on the flash, or the
number of blocks following the DATA0 block.
• DATAN_SIZE: Indicates the number of data bytes in all subsequent data blocks.
This MUST be a multiple of 4 bytes.
• ECCN: Indicates the ECC level to be used for the subsequent data blocks.

• GF0 or GFN: Indicates the Galois field the meta / data blocks are using
• PAGE_SIZE: Indicates the total number of bytes available per page on the physical
flash device. This includes the spare area and is typically 4096+128, 4096+218, or
2048+64 bytes.
17.2.3 Determining the ECC layout for a device

Since the BCH is programmable, a system can trade off ECC levels for flash size and
layout configurations.
The following examples indicate how to determine a valid layout based on the required
storage space and flash size. For all cases, the size of the parity will be 13 (or 14 for
GF(214))*ECC level bits-- so for ECC8, 13 (or 14) bytes are required (per block).
17.2.3.1 4K+218 flash, 10 bytes metadata, 512 byte data blocks,

separate metadata, Assuming GF(213)
In this case, we have 8 data blocks each consisting of 512 bytes. Since the flash has 218
spare bytes (1744 bits), first estimate an ECC level for the data blocks by first subtracting
the number of metadata bytes from the spare bytes (218 – 10 = 208 bytes = 1664 bits)
then dividing the number of bits by 8 (number of blocks) and then by 13 (bits per ECC
level).
(218 - 10) x 8 = 1664/13(8) = 16
Therefore all the data blocks could be covered by ECC16 if the metadata had no parity.
This isn't acceptable, so assume ECC14 for all the data blocks. Now calculate the number
of free bits for the metadata parity as
1664 - (14) x 13 x 8 = 208
Therefore, 208 bits remain for metadata parity. Dividing by 13 (bits/ECC) gives 16, so
the metadata can be covered with ECC16. The settings for this device would then be
Table 17-1. Settings for 4K+218 FLASH
Setting Value
PAGE_SIZE 4096+218=4314=0x10DA
META_SIZE 10=0x0A
DATA0_SIZE 0
ECC0 16=0x10

Operation
Table 17-1. Settings for 4K+218 FLASH (continued)

Setting Value
GF0 GF(213)
DATAN_SIZE 512=0x200 (in register interface, assigned as 0x80)
ECCN 14=0x0E
GFN GF(213)
NBLOCKS 8
17.2.3.2 4K+128 flash, 10 bytes metadata, 1024 byte data blocks,

separate metadata, assuming GF(213) for data and GF(214)
for metadata
This flash will have 118 bytes available for ECC (after subtracting the metadata size),
therefore, 994 bits.
Dividing by 4*14 (number of blocks * ECC level) we get 17.75, therefore we can support
ECC16 on the data blocks. The number of free spare bits becomes 944 - 16 * 4 * 14 =
944 - 896 = 48, divided by 13 = 3.69, therefore the metadata can be also covered by
ECC2.
Table 17-2. Settings for 4K+128 FLASH
Setting Value
PAGE_SIZE 4096+128=4224=0x1080
META_SIZE 10=0x0A
DATA0_SIZE 0
ECC0 2
GF0 GF(213)
DATAN_SIZE 1024=0x400 (in register interface, assigned as 0x100)
ECCN 16
GFN GF(214)
NBLOCKS 4
In this case, there will be additional unused spare bits, with the BCH will pad out with
zeros.
17.2.4 Data Buffers in System Memory

While the data on the flash is interleaved with parity symbols, the BCH assumes that the
data buffers in memory are contiguous.
Metadata read from the flash will be stored to the location pointed to by the
GPMI_AUXILIARY register and data will be written to the address specified in the
GPMI_PAYLOAD register as is shown in the following figure where the block length is
512 bytes for example. Since the number of blocks on a flash page is programmable, the
BCH also writes individual block correction status to the auxiliary pointer at the word-
aligned address following the end of the metadata. Optionally, the computed syndromes
may also be written to the auxiliary area if the DEBUGSYNDROME bit is set in the
control register.
As blocks complete processing, the bus master will accumulate the status for each block
and write it to the auxiliary data buffer following the metadata. The metadata area will be
padded with 0's until the next word boundary and the status for blocks 0-3 will be written
to the next word. The status for subsequent blocks will then be written to the buffer. The
status for the first block (metadata block) is also stored in the STATUS_BLK0 register in
the BCH_STATUS register. The completion codes for the blocks are indicated in the
Table 17-3. Note that the definition of the bytes and their ordering in the auxiliary and
payload storage areas are user defined. When this data is read back from the flash and put
into memory, it will resemble the original buffer that was written out to the flash.
Minimum System Memory Footprint:
512 byte Payload A

HW_GPMI_PAYLOAD
512 byte Payload B
512 byte Payload C
512 byte Payload D
META_SIZE bytes of auxiliary storage

(programmable – block is padded w/ 0's to word
boundary)
HW_GPMI_AUXILIARY
Status for each block.
(Optional n bytes syndromes for Payload A)

(Optional n bytes syndrome for Payload B)
(Optional n bytes syndrome for Payload C)
(Optional n bytes syndrome for Payload D)
Computed syndrome area consists of 2*t 13 (or 14)-

bit symbols written as 16-bit half word.
Figure 17-4. BCH Data Buffers in Memory

Memory to Memory (Loopback) Operation
Table 17-3. Status Block Completion Codes

Code Description
0xFF Block is erased
0xFE Block is uncorrectable
0x00 No errors found
0x01-0x28 Number of errors corrected
The following figure shows the layout of the bytes within the status field.
3 2 1 0
Metadata
0 0
Block 3 Block 2 Block 1 block 0

Status Status Status Status
Block 7 Block 6 Block 5 Block 4

Status Status Status Status
Block 8
0 0 0
Status
Status bytes are allocated based on the NBLOCKS programmed into the
flash format register. The number of status bytes are computed by NBLOCK+1.
The status area will be padded with zeros to the next word boundary.
Syndrome data written for debug purposes
follows the end of the status block.
Figure 17-5. Memory-to-Memory Operations
17.3 Memory to Memory (Loopback) Operation

The BCH supports a memory-to-memory mode of operation where both the encoded and
decoded buffers reside in system memory.
This can be useful for applications where data must be protected by ECC, but the storage
device does not reside on the GPMI bus.
The BCH operation in memory to memory mode is much simpler than in GPMI mode
since DMAs are not required to manage the operation. Instead, software simply writes the
BCH_DATAPTR and BCH_METAPTR with the addresses of the data and metadata
(auxiliary) buffers and the BCH_ENCODEPTR with the address of the buffer for
encoded data. To initiate the operation, software simply sets the M2M_ENCODE and

M2M_ENABLE bits in the control register. The BCH can be programmed to either issue
an interrupt at the end of the operation or software may poll the status bits for
completion.
Memory to memory decode operations work in a similar manner. The encoded data
address is written to the BCH_ENCODEPTR and the data and meta pointers are written
to buffers that correspond to the desired decoded data addresses. To initiate a decode,
software must set the M2M_ENCODE bit to 0 while writing the M2M_ENABLE bit.
Note that the addresses written to the BCH_DATAPTR, BCH_METAPTR and
BCH_ENCODEPTR registers should always be aligned on a 4 byte boundary. In other
words, the 2 lower bits of the address should always be written with zeros.
17.4 Programming the BCH/GPMI Interfaces

Programming the BCH for NAND operations consists largely of disabling the soft reset
and clock bits (SFTRST and CLKGATE) from the BCH_CTRL register and then
programming the flash layout registers to correspond to the format of the attached NAND
device(s).
The BCH_LAYOUTSELECT register should also be programmed to map the chip select
of each attached device into one of the four layout registers.
The bulk of the programming is actually applied to the GPMI through PIO operations
embedded in DMA command structures. The DMA will perform all the requisite
handshaking with the GPMI interface to negotiate the address portion of the transfer, then
the BCH will handle all the movement of data from memory to the GPMI (writes) or the
GPMI to memory (reads). The BCH will direct all data blocks to the buffer pointed to by
the PAYLOAD_BUFFER and the metadata will be written to the
AUXILIARY_BUFFER. Both of these registers are located in the GPMI PIO data space
and are communicated to the BCH hardware at the beginning of the transfer. Thus, the
normal multi-NAND DMA based device interleaving is preserved, that is, four NANDs
on four separate chip selects can be scheduled for read or write operations using the
BCH. Whichever channel finishes its ready wait first and enters the DMA arbiter with its
lock bit set owns the GPMI command interface and through it owns the BCH resources
for the duration of its processing.
17.4.1 BCH Encoding for NAND Writes

The BCH encoder flowchart in Figure 17-6 shows the detailed steps involved in
programming and using the BCH encoder. This flowchart shows how to use the BCH
block with the GPMI.
Programming the BCH/GPMI Interfaces
To use the BCH encoder with the GPMI's DMA, create a DMA command chain
containing ten descriptor structures, as shown in Figure 17-8 and detailed in the DMA
structure code example that follows it in DMA Structure Code Example. The ten
descriptors perform the following tasks:
1. Disable the BCH block (in case it was enabled) and issue NAND write setup
command byte (under CLE) and address bytes (under ALE).
2. Configure and enable the BCH and GPMI blocks to perform the NAND write.
3. Disable the BCH block and issue NAND write execute command byte (under CLE).
4. Wait for the NAND device to finish writing the data by watching the ready signal.
5. Check for NAND timeout through PSENSE.
6. Issue NAND status command byte (under CLE).
7. Read the status and compare against expected.
8. If status is incorrect or incomplete, branch to error handling descriptor chain.
9. Otherwise, write is complete and emit GPMI interrupt.

BCH ENCODE &

WRITE NAND
Run the prescribe initialization sequence.
Point the GPMI DMA channel 4 (or 0/1/2/3/5/6/7) at

the prescribed static DMA sequence.
Start the DMA.
Return and wait for DMA channel 4 (or 0/1/2/3/5/6/7)

command complete interrupt.
STOP
APBH DMA CH4 Command

Complete ISR Must use SCT clear
HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ = 0
Start GPMI DMA chain for next write or read transfer.
STOP
Figure 17-6. BCH Encode Flowchart

Descriptor Legend
NEXT CMD ADDR
CMD <= xfer_count cmdwords wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command
BUFFER ADDR
HW_GPMI_CTRL0 <= command_mode word_length lock_cs CS address address_increment xfer_count
HW_GPMI_COMPARE <= mask reference
HW_GPMI_ECCCTRL <= ecc_cmd enable_ecc buffer_mask
HW_GPMI_ECCCOUNT
HW_GPMI_PAYLOAD
HW_GPMI_AUXILIARY
Figure 17-7. BCH DMA Descriptor Legend

Descriptor 1: Disable BCH engine and issue NAND write set-up command and address (CLE/ALE).
NEXT CMD ADDR
CMD <= 1+5 3 1 0 0 1 0 1 DMA_READ
BUFFER ADDR 1 Byte NAND CMD
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_CLE 1 1+5
5 Byte ADDR
HW_GPMI_COMPARE <= null null
HW_GPMI_ECCCTRL <= disable
NOTE: No DMA
Descriptor 2: Enable the BCH engine and write the data payload.
data transferred to
NEXT CMD ADDR GPMI when using
CMD <= 0 4 1 0 0 1 0 1 NO_DMA_XFER BCH
BUFFER ADDR
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_DATA 0 0
HW_GPMI_ECCCTRL <= encode_8_bit enable 0x1FF
8*512 Byte Data
HW_GPMI_ECCCOUNT<= 4096+218 (flash page size)
Payload Buffer
HW_GPMI_PAYLOAD
HW_GPMI_AUXILIARY
Auxiliary Payload
Buffer
Descriptor 3: Disable BCH engine and issue NAND write execute command (CLE).
NEXT CMD ADDR
CMD <= 1 3 1 0 0 1 0 1 DMA_READ
BUFFER ADDR
1 Byte NAND CMD
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_CLE 0 1
HW_GPMI_ECCCTRL <= ---- disable ----
Descriptor 4: Wait for NAND ready.

NEXT CMD ADDR
CMD <= 0 1 1 0 1 0 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= wait_for_ready 8_bit disabled 2 NAND_DATA 0 0
Descriptor 5: PSENSE compare for time-out.

NEXT CMD ADDR
CMD <= 0 0 0 0 0 0 0 1 DMA_SENSE DMA Error
BUFFER ADDR Descriptor Chain
Descriptor 6: Disable BCH engine (if enabled by another thread) and issue NAND status command (CLE).
NEXT CMD ADDR
CMD <= 1 3 1 0 0 1 0 1 DMA_READ
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_CLE 0 1
Descriptor 7: Read the NAND status and compare against expected value.
NEXT CMD ADDR
CMD <= 0 2 1 0 0 1 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= read_and_compare 8_bit disabled 2 NAND_DATA 0 1
HW_GPMI_COMPARE <= <mask_value> <reference_value>
Descriptor 8: PSENSE compare for status comparison check.

NEXT CMD ADDR
CMD <= 0 0 0 0 0 0 0 1 DMA_SENSE
BUFFER ADDR
Descriptor 9: Emit GPMI DMA interrupt.

NEXT CMD ADDR
CMD <= 0 0 0 0 0 0 1 0 NO_DMA_XFER
BUFFER ADDR
Figure 17-8. BCH Encode DMA Descriptor Chain

17.4.1.1 DMA Structure Code Example

The following code sample illustrates the coding for one write transaction involving 4096
bytes of data payload (eight 512-byte blocks) and 10 bytes of auxiliary payload (also
referred to as metadata) to a 4K NAND page sitting on GPMI CS2.
//----------------------------------------------------------------------------
// generic DMA/GPMI/ECC descriptor struct, order sensitive!
//----------------------------------------------------------------------------
typedef struct {
// DMA related fields
unsigned int dma_nxtcmdar;
unsigned int dma_cmd;
unsigned int dma_bar;
// GPMI related fields
unsigned int gpmi_ctrl0;
unsigned int gpmi_compare;
unsigned int gpmi_eccctrl;
unsigned int gpmi_ecccount;
unsigned int gpmi_data_ptr;
unsigned int gpmi_aux_ptr;
} GENERIC_DESCRIPTOR;
//----------------------------------------------------------------------------
// allocate 10 descriptors for doing a NAND ECC Write
//----------------------------------------------------------------------------
GENERIC_DESCRIPTOR write[10];
//----------------------------------------------------------------------------
// DMA descriptor pointer to handle error conditions from psense checks
//----------------------------------------------------------------------------
unsigned int * dma_error_handler;
//----------------------------------------------------------------------------
// 8 byte NAND command and address buffer
// any alignment is ok, it is read by the GPMI DMA
// byte 0 is write setup command
// bytes 1-5 is the NAND address
// byte 6 is write execute command
// byte 7 is status command
//----------------------------------------------------------------------------
unsigned char nand_cmd_addr_buffer[8];
//----------------------------------------------------------------------------
// 4096 byte payload buffer used for reads or writes
// needs to be word aligned
//----------------------------------------------------------------------------
unsigned int write_payload_buffer[(4096/4)];
//----------------------------------------------------------------------------
// 65 byte meta-data to be written to NAND
//----------------------------------------------------------------------------
unsigned int write_aux_buffer[65];
//----------------------------------------------------------------------------
// Descriptor 1: issue NAND write setup command (CLE/ALE)
//----------------------------------------------------------------------------
write[0].dma_nxtcmdar = &write[1]; // point to the next descriptor
write[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5)| // 1 byte command, 5 byte address
BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to the GPMI
BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish
before
// continuing
BF_APBH_CHn_CMD_SEMAPHORE (0) |
BF_APBH_CHn_CMD_NANDWAIT4READY(0) |
BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels
from
// taking over
BF_APBH_CHn_CMD_IRQONCMPLT (0) |
BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command

BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // read data from DMA, write to
NAND
write[0].dma_bar = &nand_cmd_addr_buffer; // byte 0 write setup, bytes 1 - 5 NAND
address
// 3 words sent to the GPMI
write[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND
BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) |
BV_FLD(GPMI_CTRL0, LOCK_CS, ENABLED) |
BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS
used
BV_FLD(GPMI_CTRL0, ADDRESS, NAND_CLE) |
BF_GPMI_CTRL0_ADDRESS_INCREMENT (1) | // send command and
address
BF_GPMI_CTRL0_XFER_COUNT (1 + 5); // 1 byte command, 5 byte
address
write[0].gpmi_compare = NULL; // field not used but necessary to
set eccctrl
write[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block
//----------------------------------------------------------------------------
// Descriptor 2: write the data payload (DATA)
//----------------------------------------------------------------------------
write[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0)| // NOTE: No DMA data transfer
BF_APBH_CHn_CMD_CMDWORDS (4)| // send 4 words to the GPMI
BF_APBH_CHn_CMD_WAIT4ENDCMD (1)| // Wait to end
BF_APBH_CHn_CMD_SEMAPHORE (0)|
BF_APBH_CHn_CMD_NANDWAIT4READY (0)|
BF_APBH_CHn_CMD_NANDLOCK (1)| // maintain resource lock
BF_APBH_CHn_CMD_IRQONCMPLT (0)|
BF_APBH_CHn_CMD_CHAIN (1)| // follow chain to next command
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_NO_XFER); // No data transferred
write[1].dma_bar = &write_payload_buffer; // pointer for the 4K byte
data area
BF_GPMI_CTRL0_CS (2) | // must correspond to NAND
CS used
BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA)|
BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) |
BF_GPMI_CTRL0_XFER_COUNT (0); // NOTE: this field
contains
// the total amount
// DMA transferred to GPMI via DMA (0)!
write[1].gpmi_compare = NULL; // field not used but necessary
to
set eccctrl
write[1].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, ENCODE_8_BIT) | // specify t = 8
mode
BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC module
BF_GPMI_ECCCTRL_BUFFER_MASK (0x1FF); // write all 8 data
blocks
// and 1 aux block
write[1].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(4096+218); // specify number of bytes
// written to NAND
write[1].gpmi_data_pointer = &write_payload_pointer; // data buffer address
write[1].gpmi_aux_pointer = &write_aux_pointer; // metadata pointer
//----------------------------------------------------------------------------
// Descriptor 3: issue NAND write execute command (CLE)
//----------------------------------------------------------------------------
write[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte command
before
// continuing
BF_APBH_CHn_CMD_NANDLOCK (1) | // maintain resource lock

NAND
write[2].dma_bar = &nand_cmd_addr_buffer[6]; // point to byte 6, write execute
command
used
BF_GPMI_CTRL0_XFER_COUNT (1); // 1 byte command
write[2].gpmi_compare = NULL; // field not used but necessary to set
eccctrl
//----------------------------------------------------------------------------
// Descriptor 4: wait for ready (CLE)
//----------------------------------------------------------------------------
write[3].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer

BF_APBH_CHn_CMD_CMDWORDS (1) | // send 1 word to the GPMI
BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before
// continuing
BF_APBH_CHn_CMD_NANDWAIT4READY(1) | // wait for nand to be ready
BF_APBH_CHn_CMD_NANDLOCK (0) | // relinquish nand lock
BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer
write[3].dma_bar = NULL; // field not used
// 1 word sent to the GPMI
write[3].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WAIT_FOR_READY) | // wait for NAND
ready
BV_FLD(GPMI_CTRL0, LOCK_CS, DISABLED) |
used
BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) |
BF_GPMI_CTRL0_XFER_COUNT (0);
//----------------------------------------------------------------------------
// Descriptor 5: psense compare (time out check)
//----------------------------------------------------------------------------
BF_APBH_CHn_CMD_CMDWORDS (0) | // no words sent to GPMI
BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | // do not wait to continue
BF_APBH_CHn_CMD_NANDLOCK (0) |
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); // perform a sense check
write[4].dma_bar = dma_error_handler; // if sense check fails, branch to error
handler
//----------------------------------------------------------------------------
// Descriptor 6: issue NAND status command (CLE)
//----------------------------------------------------------------------------
write[5].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte command
before
continuing

BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from
taking over
NAND
write[5].dma_bar = &nand_cmd_addr_buffer[7]; // point to byte 7, status
command
write[5].gpmi_compare = NULL; // field not used but necessary to set
eccctrl
used
//----------------------------------------------------------------------------
// Descriptor 7: read status and compare (DATA)
//----------------------------------------------------------------------------
before
// continuing
BF_APBH_CHn_CMD_NANDLOCK (1) | // maintain resource lock
write[6].dma_bar = NULL; // field not used
write[6].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ_AND_COMPARE) | // read from the
// NAND and
// // compare to expect
used
write[6].gpmi_compare = <MASK_AND_REFERENCE_VALUE>; // NOTE: mask and reference values are
NAND
// SPECIFIC to evaluate the NAND
status
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
write[7].dma_bar = dma_error_handler; // if sense check fails, branch to error
handler
//----------------------------------------------------------------------------
// Descriptor 9: emit GPMI interrupt
//----------------------------------------------------------------------------
write[8].dma_nxtcmdar = NULL; // not used since this is

last
descriptor
BF_APBH_CHn_CMD_IRQONCMPLT (1) | // emit GPMI interrupt
BF_APBH_CHn_CMD_CHAIN (0) | // terminate DMA chain
processing
17.4.1.2 Using the BCH Encoder

To use the BCH encoder, first turn off the module-wide soft reset bit in both the GPMI
and BCH blocks before starting any DMA activity.
Turning off the soft reset must take place by itself, prior to programming the rest of the
control registers. Turn off the BCH bus master soft reset bit. Turn off the clock gate bits.
Program the remainder of the GPMI, BCH and APBH DMA as follows:
// bring APBH out of reset

APBH_CTRL0_CLR(BM_APBH_CTRL0_SFRST);
APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE);
// bring BCH out of reset

BCH_CTRL_CLR(BM_BCH_CTRL_SFTRST);
BCH_CTRL_CLR(BM_BCH_CTRL_CLKGATE);
// bring gpmi out of reset

GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST);
GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE);
GPMI_CTRL1_SET(BM_GPMI_CTRL1_DEV_RESET | // deassert reset
BM_GPMI_CTRL1_BCH_MODE ); // enable BCH mode
// enable pinctrl
PINCTRL_CTRL_WR(0x00000000);
// enable gpmi pins

PINCTRL_MUXSEL0_CLR(0x0000ffff); // data bits
PINCTRL_MUXSEL1_CLR(0x03ffffff); // control bits
PINCTRL_MUXSEL8_CLR(0x0003f3ff); // control bits
PINCTRL_MUXSEL8_SET(0x00015155); // control bits
Note that for writing NANDs (ECC encoding), only GPMI DMA command complete
interrupts are used. The BCH engine is used for writing to the NAND but may optionally
produces an interrupt. From the sample code in DMA Structure Code Example :
• DMA descriptor 1 prepares the NAND for data write by using the GPMI to issue a
write setup command byte under CLE, then sends a 5-byte address under ALE. The
BCH engine is disabled and not used for these commands.

• DMA descriptor 2 enables the BCH engine for encoding to begin the initial writing
of the NAND data by specifying where the data and auxiliary payload are coming
from in system memory.
• DMA descriptor 3 issues the write commit command byte under CLE to the NAND.
• DMA descriptor 4 waits for the NAND to complete the write commit/transfer by
watching the NAND's ready line status. This descriptor relinquishes the
NANDLOCK on the GPMI to enable the other DMA channels to initiate NAND
transactions on different NAND CS lines.
• DMA descriptor 6 issues a NAND status command byte under "CLE" to check the
status of the NAND device following the page write.
• DMA descriptor 7 reads back the NAND status and compares the status with an
expected value. If there are differences, then the DMA processing engine follows an
error-handling DMA descriptor path.
• DMA descriptor 8 disables the BCH engine and emits a GPMI interrupt to indicate
that the NAND write has been completed.
17.4.2 BCH Decoding for NAND Reads

When a page is read from NAND flash, BCH syndromes will be computed and, if
correctable errors are found, they will be corrected on a per block basis within the NAND
page. This decoding process is fully overlapped with other NAND data reads and with
CPU execution. The BCH decoder flowchart in the figure below shows the steps involved
in programming the decoder. The hardware flow of reading and decoding a 4096-byte
page is shown in Figure 17-10.

Read NAND &

BCH Decode
Run the prescribe initialization Sequence
Point the GPMI DMA channel 4 (or 0/1/2/3/5/6/7) at

the prescribed static DMA sequence
Start the DMA
Return and wait for DMA channel 4 ( or 0/1/2/3/5/6/7)

command complete interrupt.
STOP
APBH DMA CH4 Command

Complete ISR Must use SCT clear
HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ = 0
Start GPMI DMA chain for next write or read transfer
STOP
BCH Complete ISR
Read status regs and store for processing
Must use SCT clear
HW_BCH_CTRL_COMPLETE_IRQ = 0
STOP
Figure 17-9. BCH Decode Flowchart
Conceptually, an APHB DMA Channel (0,1,2 or 3) command chain with seven command
structures linked together is used to perform the BCH decode operation (as shown in
Figure 17-10).
Note
The GPMI's DMA command structures controls the BCH
decode operation.

To use the BCH decoder with the GPMI's DMA, create a DMA command chain
containing seven descriptor structures, as shown in the figure below and detailed in the
DMA structure code example that follows it in DMA Structure Code Example. The seven
DMA descriptors perform the following tasks:
1. Issue NAND read setup command byte (under "CLE") and address bytes (under
"ALE").
2. Issue NAND read execute command byte (under "CLE").
3. Wait for the NAND device to complete accessing the block data by watching the
ready signal.
4. Check for NAND timeout through "PSENSE".
5. Configure and enable the BCH block and read the NAND block data.
6. Disable the BCH block.
7. Descriptor NOP to allow NANDLOCK in the previous descriptor to the thread-safe.

Descriptor 1: Disable BCH engine and issue NAND read set-up command and address (CLE/ALE).
NEXT CMD ADDR

CMD <= 1+5 3 1 0 0 1 0 1 DMA_READ
HW_GPMI_CTRL0 <= write 8_bit enabled 2 NAND_CLE 1 1+5
5 Byte ADDR
Descriptor 2: NAND read execute command (CLE).
NEXT CMD ADDR

CMD <= 1 1 1 0 0 1 0 1 DMA_READ
HW_GPMI_CTRL0 <= write 8_bit disabled 2 NAND_CLE 0 1
Descriptor 3: Wait for NAND ready.
NEXT CMD ADDR

CMD <= 0 1 1 0 1 0 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= wait_for_ready 8_bit disabled 2 NAND_DATA 0 0
Descriptor 4: PSENSE compare for time-out.
NEXT CMD ADDR

DMA Error
CMD <= 0 0 0 0 0 0 0 1 DMA_SENSE Descriptor Chain
BUFFER ADDR
Descriptor 5: Enable BCH engine and read NAND data.
NEXT CMD ADDR

CMD <= 0 6 1 0 0 1 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= read 8_bit disabled 2 NAND_DATA 0 4096+218
HW_GPMI_ECCCTRL <= decode_8_bit enable 0x1FF
8*512 Byte Data
HW_GPMI_ECCCOUNT<= 4096+218 (flash page size) Payload Buffer
HW_GPMI_PAYLOAD
HW_GPMI_AUXILIARY
412 Byte Auxiliary
Payload Buffer
Descriptor 6: Disable BCH engine (wait for ready is a NOP here).
NEXT CMD ADDR

CMD <= 0 3 1 0 1 1 0 1 NO_DMA_XFER
BUFFER ADDR
HW_GPMI_CTRL0 <= wait_for_ready 8_bit
_ disabled 0 NAND_DATA 0 0
Descriptor 7: NOP to ensure NANDLOCK in previous descriptor .
NEXT CMD ADDR

CMD <= 0 0 0 0 0 0 0 0 NO_DMA_XFER
BUFFER ADDR
Figure 17-10. BCH Decode DMA Descriptor Chain

17.4.2.1 DMA Structure Code Example

The following sample code illustrates the coding for one read transaction, consisting of a
seven DMA command structure chain for reading all 4096 bytes of payload data (eight
512-byte blocks) and 65 bytes of metadata with the associative parity bytes (8 * (18) + 9)
from a 4K NAND page sitting on GPMI CS2.
//----------------------------------------------------------------------------
// generic DMA/GPMI/ECC descriptor struct, order sensitive!
//----------------------------------------------------------------------------
typedef struct {
// DMA related fields
unsigned int dma_nxtcmdar;
unsigned int dma_cmd;
unsigned int dma_bar;
// GPMI related fields
unsigned int gpmi_ctrl0;
unsigned int gpmi_compare;
unsigned int gpmi_eccctrl;
unsigned int gpmi_ecccount;
unsigned int gpmi_data_ptr;
unsigned int gpmi_aux_ptr;
} GENERIC_DESCRIPTOR;
//----------------------------------------------------------------------------
// allocate 7 descriptors for doing a NAND ECC Read
//----------------------------------------------------------------------------
GENERIC_DESCRIPTOR read[7];
//----------------------------------------------------------------------------
// DMA descriptor pointer to handle error conditions from psense checks
//----------------------------------------------------------------------------
unsigned int * dma_error_handler;
//----------------------------------------------------------------------------
// 7 byte NAND command and address buffer
// any alignment is ok, it is read by the GPMI DMA
// byte 0 is read setup command
// bytes 1-5 is the NAND address
// byte 6 is read execute command
//----------------------------------------------------------------------------
unsigned char nand_cmd_addr_buffer[7];
//----------------------------------------------------------------------------
// 4096 byte payload buffer used for reads or writes
//----------------------------------------------------------------------------
unsigned int read_payload_buffer[(4096/4)];
//----------------------------------------------------------------------------
// 412 byte auxiliary buffer used for reads
//----------------------------------------------------------------------------
unsigned int read_aux_buffer[(412/4)];
//----------------------------------------------------------------------------
// Descriptor 1: issue NAND read setup command (CLE/ALE)
//----------------------------------------------------------------------------
read[0].dma_nxtcmdar = &read[1]; // point to the next descriptor
read[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5) | // 1 byte command, 5 byte address
// before continuing
// taking over

NAND
read[0].dma_bar = &nand_cmd_addr_buffer; // byte 0 read setup, bytes 1 - 5 NAND
address
read[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND
CS used
BF_GPMI_CTRL0_ADDRESS_INCREMENT (1) | // send command and address
BF_GPMI_CTRL0_XFER_COUNT (1 + 5); // 1 byte command, 5 byte
address
read[0].gpmi_compare = NULL; // field not used but necessary to set
eccctrl
read[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block
//----------------------------------------------------------------------------
// Descriptor 2: issue NAND read execute command (CLE)
//----------------------------------------------------------------------------
read[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte read command
BF_APBH_CHn_CMD_CMDWORDS (1) | // send 1 word to GPMI
before
// continuing
// taking over
BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // read data from DMA, write
to NAND
read[1].dma_bar = &nand_cmd_addr_buffer[6]; // point to byte 6, read execute
command
read[1].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND
CS used
//----------------------------------------------------------------------------
// Descriptor 3: wait for ready (DATA)
//----------------------------------------------------------------------------
read[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer
BF_APBH_CHn_CMD_CMDWORDS (1) | // send 1 word to GPMI
before
// continuing
read[2].dma_bar = NULL; // field not used
read[2].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WAIT_FOR_READY) | // wait for NAND
ready
BF_GPMI_CTRL0_CS (2) | // must correspond
to NAND CS used

//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
read[3].dma_nxtcmdar = &read[4]; // point to the next
descriptor
BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next
command
read[3].dma_bar = dma_error_handler; // if sense check fails, branch to
error handler
//----------------------------------------------------------------------------
// Descriptor 5: read 4K page plus 65 byte meta-data Nand data
// and send it to ECC block (DATA)
//----------------------------------------------------------------------------
BF_APBH_CHn_CMD_CMDWORDS (6) | // send 6 words to GPMI
BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before
// continuing
taking over
BF_APBH_CHn_CMD_IRQONCMPLT (0) | // ECC block generates BCH interrupt
// on completion
BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no DMA transfer,
// ECC block handles
transfer
read[4].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ) | // read from the NAND
BF_GPMI_CTRL0_CS (2) | // must correspond to
NAND CS used
BF_GPMI_CTRL0_XFER_COUNT (4096+218); // eight 512 byte data
blocks
// metadata, and parity

eccctrl
// GPMI ECCCTRL PIO This launches the 4K byte transfer through BCH's
// bus master. Setting the ECC_ENABLE bit redirects the data flow
// within the GPMI so that read data flows to the BCH engine instead
// of flowing to the GPMI's DMA channel.
read[4].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, DECODE_8_BIT) | // specify t = 8
mode
BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC
module
BF_GPMI_ECCCTRL_BUFFER_MASK (0X1FF); // read all 8 data blocks
and 1 aux block
read[4].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(4096+218); // specify number of bytes
// read from NAND
read[4].gpmi_data_ptr = &read_payload_buffer; // pointer for the 4K byte
// data area
read[4].gpmi_aux_ptr = &read_aux_buffer; // pointer for the 65 byte
aux area +
// parity and syndrome

bytes for both
// data and aux blocks.
//----------------------------------------------------------------------------
// Descriptor 6: disable ECC block
//----------------------------------------------------------------------------
BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to GPMI
before
// continuing
BF_APBH_CHn_CMD_NANDLOCK (1) | // need nand lock to be
// thread safe while turn-off BCH
read[5].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ) |
BF_GPMI_CTRL0_CS (2) | // must correspond to
NAND CS used
eccctrl
read[5].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block
//----------------------------------------------------------------------------
// Descriptor 7: deassert nand lock
//----------------------------------------------------------------------------
read[6].dma_nxtcmdar = NULL; // not used since this is last
descriptor
before
// continuing
BF_APBH_CHn_CMD_IRQONCMPLT (0) | // BCH engine generates interrupt
BF_APBH_CHn_CMD_CHAIN (0) | // terminate DMA chain processing
17.4.2.2 Using the Decoder

As illustrated in Figure 17-10 and the sample code in DMA Structure Code Example :
• DMA descriptor 1 prepares the NAND for data read by using the GPMI to issue a
NAND read setup command byte under CLE, then sends a 5-byte address under
ALE. The BCH engine is not used for these commands.
• DMA descriptor 2 issues a one-byte read execute command to the NAND device that
triggers its read access. The NAND then goes not ready.

• DMA descriptor 3 performs a wait for ready operation allowing the DMA chain to
remain dormant until the NAND device completes its read access time.
• DMA descriptor 5 handles the reading and error correction of the NAND data. This
command's PIOs activate the BCH engine to write the read NAND data to system
memory and to process it for any errors that need to be corrected. This DMA
descriptor contains two PIO values that are system memory addresses pointing to the
PAYLOAD data area and to the AUXILIARY data area. These addresses are used by
the BCH engine's AHB master to move data into system memory and to correct it.
While this example is reading an entire 4K page—payload plus metadata—it is
equally possible to read just one 512-byte payload block or just the uniquely
protected metadata block in a single 7 DMA structure transfer.
• DMA descriptor 6 disables the BCH engine with the NANDLOCK asserted. This is
necessary to ensure that the GPMI resource is not arbitrated to another DMA channel
when multiple DMA channels are active concurrently.
• DMA descriptor 7 de-asserts the NANDLOCK to free up the GPMI resource to
another channel.
As the BCH block receives data from the GPMI:

• The decoder transforms the read NAND data block into a BCH code word and
computes the codeword syndrome.
• If no errors are present, then the BCH block can immediately report back to
firmware. This report is passed as the BCH_CTRL_COMPLETE_IRQ interrupt
status bit and the associated status registers in BCH_STATUS0/1 registers.
• If an error is present, then the BCH block corrects the necessary data block or parity
block bytes, if possible (not all errors are correctable).
As the BCH decoder reads the data and parity blocks, it records a special condition, i.e.,
that all of the bits of a payload data block or metadata block are one, including any
associated parity bytes. The all-ones case for both parity and data indicates an erased
block in the NAND device.
The BCH_STATUS0 register contains a 4-bit field that indicates the final status of the
auxiliary block. A value of 0x0 indicates no errors found for a block.
• A value of 1 to 20 inclusive indicates that many correctable errors were found and
fixed.
• A value of 0xFE indicates uncorrectable errors detected on the block.

• A value of 0xFF indicates that the block was in the special ALL ONES state and is
therefore considered to be an ERASED block.
• All other values are disallowed by the hardware design.
Recall that up to eight NAND devices can have DMA chains in-flight at once, i.e. they
can all be contending for access to the GPMI data bus. It is impossible to predict which
NAND device will enter the BCH engine with a transfer first, because each chain
includes a wait4ready command structure. As a result, firmware should look at the
BCH_STATUS0_COMPLETED_CE bit field to determine which block is being reported
in the status register. There is also a 16-bit HANDLE field in the GPMI_ECCCTRL
register that is passed down the pipeline with each transaction. This handle field can be
used to speed firmware's detection of which transaction is being reported.
These examples of reading and writing have focused on full page transfers of 4K page
NAND devices. Other device configurations can be specified by changing the
ECCOUNT field in the GPMI registers and reprogramming the BCH's
FLASHnLAYOUTm registers.
The BCH and GPMI blocks are designed to be very efficient at reading single 512 (or
1024)-byte pages in one transaction. With no errors, the transaction takes less than 20
HCLKs longer than the time to read the raw data from the NAND.
To summarize, the APBH DMA command chain for a BCH decode operation is shown in
Figure 17-10. Seven DMA command structures must be present for each NAND read
transaction decoded by the BCH. The seven DMA command structures for multiple
NAND read transaction blocks can be chained together to make larger units of work for
the BCH, and each will produce an appropriate error report in the BCH PIO space.
Multiple NAND devices can have such multiple chains scheduled. The results can come
back out of order with respect to the multiple chains.
17.4.3 Interrupts
There are two interrupt sources used in processing BCH protected NAND read and write
transfers.
Since all BCH operations are initiated by GPMI DMA command structures, the DMA
completion interrupt for the GPMI is an important ISR. Both of the flow charts of Figure
17-6 and Figure 17-9 show the GPMI DMA complete ISR skeleton. In both reads and
writes, the GPMI DMA completion interrupt is used to schedule work INTO the error
correction pipeline. As the front end processing completes, the DMA interrupt is

Behavior During Reset
generated and additional work, such as DMA chains, are passed to the GPMI DMA to
keep it fed. For write operations, this is the only interrupt that is generated for processing
the NAND write transfer.
For reads, however, two interrupts are needed. Every read is started by a GPMI DMA
command chain and the front end queue is fed as described above. The back end of the
read pipeline is drained by monitoring the BCH completion interrupt found int
HW_BCH_CTRL_COMPLETE_IRQ.
An BCH transaction consists of reading or writing all of the blocks requested in the
HW_GPMI_ECCCTRL_BUFFER_MASK bit field. As every read transaction completes,
it posts the status of all of the blocks to the HW_BCH_STATUS0 and
HW_BCH_STATUS1 registers and sets the completion interrupt. The five stages of the
BCH read pipeline completes, one in the GPMI and four in the BCH, are independently
stalled as they complete and try to deliver to the next stage in the data flow. Several of
these stages can be skipped if no-errors are found or once an uncorrectable error is found
in a block.
In any case, the final stage will stall if the status register is busy waiting for the CPU to
take status register results. The hardware monitors the state of the
HW_BCH_CTRL_COMPLETE_IRQ bit. If it is still set when the last pipeline stage is
ready to post data, then the stage will stall. It follows that the next previous stage will
stall when it is ready to hand off work to the final stage, and so on up the pipeline.
CAUTION
It is important that firmware read the STATUS0/1 results and
save them before clearing the interrupt request bit. Otherwise, a
transaction and its results could be completely lost.
17.5 Behavior During Reset

A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST.
The reset process gates the clocks automatically. The example code is shown below.
// A soft reset can take multiple clocks to complete, so do NOT gate the
// clock when setting soft reset. The reset process will gate the clock
// automatically. Poll until this has happened before subsequently
// preparing soft-reset and clock gate
// asserting soft-reset
BCH_CTRL_SET(BM_BCH_CTRL_SFTRST);
// waiting for confirmation of soft-reset
while (!BCH_CTRL.B.CLKGATE)

{
// busy wait
}
// Done.
17.6 BCH Memory Map/Register Definition
BCH Hardware Register Format Summary

BCH memory map
Absolute
Width Section/
(in bits) page
(hex)
Hardware BCH ECC Accelerator Control Register
11_4000 32 R/W C000_0000h 17.6.1/592
(BCH_CTRL)
11_4004 32 R/W C000_0000h 17.6.1/592
(BCH_CTRL_SET)
11_4008 32 R/W C000_0000h 17.6.1/592
(BCH_CTRL_CLR)
11_400C 32 R/W C000_0000h 17.6.1/592
(BCH_CTRL_TOG)
Hardware ECC Accelerator Status Register 0
11_4010 32 R 0000_0010h 17.6.2/595
(BCH_STATUS0)
11_4020 Hardware ECC Accelerator Mode Register (BCH_MODE) 32 R/W 0000_0000h 17.6.3/596
Hardware BCH ECC Loopback Encode Buffer Register
11_4030 32 R/W 0000_0000h 17.6.4/597
(BCH_ENCODEPTR)
Hardware BCH ECC Loopback Data Buffer Register
11_4040 32 R/W 0000_0000h 17.6.5/597
(BCH_DATAPTR)
Hardware BCH ECC Loopback Metadata Buffer Register
11_4050 32 R/W 0000_0000h 17.6.6/598
(BCH_METAPTR)
Hardware ECC Accelerator Layout Select Register
11_4070 32 R/W E4E4_E4E4h 17.6.7/598
(BCH_LAYOUTSELECT)
Hardware BCH ECC Flash 0 Layout 0 Register
11_4080 32 R/W 070A_4080h 17.6.8/600
(BCH_FLASH0LAYOUT0)
Hardware BCH ECC Flash 0 Layout 1 Register
11_4090 32 R/W 10DA_4080h 17.6.9/602
(BCH_FLASH0LAYOUT1)
Hardware BCH ECC Flash 1 Layout 0 Register 17.6.10/
11_40A0 32 R/W 070A_4080h
(BCH_FLASH1LAYOUT0) 603
11_40B0 32 R/W 10DA_4080h
11_40C0 32 R/W 070A_4080h
11_40D0 32 R/W 10DA_4080h

BCH Memory Map/Register Definition
BCH memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
11_40E0 32 R/W 070A_4080h
11_40F0 32 R/W 10DA_4080h
17.6.16/
11_4100 Hardware BCH ECC Debug Register0 (BCH_DEBUG0) 32 R/W 0000_0000h
612
Hardware BCH ECC Debug Register0 17.6.16/
11_4104 32 R/W 0000_0000h
(BCH_DEBUG0_SET) 612
11_4108 32 R/W 0000_0000h
(BCH_DEBUG0_CLR) 612
11_410C 32 R/W 0000_0000h
(BCH_DEBUG0_TOG) 612
17.6.17/
11_4110 KES Debug Read Register (BCH_DBGKESREAD) 32 R 0000_0000h
614
Chien Search Debug Read Register 17.6.18/
11_4120 32 R 0000_0000h
(BCH_DBGCSFEREAD) 615
Syndrome Generator Debug Read Register 17.6.19/
11_4130 32 R 0000_0000h
(BCH_DBGSYNDGENREAD) 615
Bus Master and ECC Controller Debug Read Register 17.6.20/
11_4140 32 R 0000_0000h
(BCH_DBGAHBMREAD) 616
17.6.21/
11_4150 Block Name Register (BCH_BLOCKNAME) 32 R 2048_4342h
616
17.6.22/
11_4160 BCH Version Register (BCH_VERSION) 32 R 0100_0000h
617
17.6.23/
11_4170 Hardware BCH ECC Debug Register 1 (BCH_DEBUG1) 32 R/W 0000_0000h
618
17.6.1 Hardware BCH ECC Accelerator Control Register

(BCH_CTRLn)
The BCH CTRL provides overall control of the hardware ECC accelerator


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD5 RSVD4
DEBUGSYNDROME
M2M_ENCODE
M2M_ENABLE
CLKGATE
SFTRST
M2M_
LAYOUT
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9
RSVD2 8 7 6 5 4 3 2 1 0
RSVD0
DEBUG_STALL_IRQ_EN
R RSVD3 RSVD1
COMPLETE_IRQ_EN
DEBUG_STALL_IRQ
BM_ERROR_IRQ
COMPLETE_IRQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_CTRLn field descriptions

Field Description
31 Set this bit to 0 to enable normal BCH operation. Set this bit to 1 (default) to disable clocking with the
SFTRST BCH and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the
BCH block to its default state. This bit resets all state machines except for the AHB master state
machine
0x0 RUN — Allow BCH to operate normally.

0x1 RESET — Hold BCH in reset.
30 This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block.
CLKGATE

BCH_CTRLn field descriptions (continued)

Field Description
0x0 RUN — Allow BCH to operate normally.
0x1 NO_CLKS — Do not clock BCH gates in order to minimize power consumption.
RSVD5
This read-only field is reserved and always has the value 0.
22 (For debug purposes only). Enable write of computed syndromes to memory on BCH decode
DEBUGSYNDROME operations. Computed syndromes will be written to the auxiliary buffer after the status block.
Syndromes will be written as padded 16-bit values.
RSVD4
This read-only field is reserved and always has the value 0
19–18 Selects the flash page format for memory-to-memory operations.
M2M_LAYOUT
17 Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations.
M2M_ENCODE
16 NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION. The BCH module
M2M_ENABLE must be inactive (not processing data from the GPMI) when this bit is set. The M2M_ENCODE and
M2M_LAYOUT bits as well as the ENCODEPTR, DATAPTR, and METAPTR registers are used for
memory-to-memory operations and must be correctly programmed before writing this bit.
RSVD3
This read-only field is reserved and always has the value 0
10 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block
DEBUG_STALL_
IRQ_EN
RSVD2
8 1 = interrupt on completion of correction is enabled.
COMPLETE_IRQ_
EN
RSVD1
3 AHB Bus interface Error Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt
BM_ERROR_IRQ status bit.
2 DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit.
DEBUG_STALL_IRQ
RSVD0
0 This bit indicates the state of the external interrupt line. Write a 1 to the SCT clear address to clear the
COMPLETE_IRQ interrupt status bit. NOTE: subsequent ECC completions will be held off as long as this bit is set. Be
sure to read the data from BCH_STATUS0, 1 before clearing this interrupt bit.

17.6.2 Hardware ECC Accelerator Status Register 0

(BCH_STATUS0)
The BCH STAT register provides visibility into the run-time status of the BCH and status
information when processing is complete. It provides overall status of the hardware ECC
accelerator.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R HANDLE COMPLETED_CE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNCORRECTABLE
CORRECTED
ALLONES
R STATUS_BLK0 RSVD1 RSVD0
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

BCH_STATUS0 field descriptions

Field Description
31–20 Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started
HANDLE the transaction. That handle passes down the pipeline and ends up here at the time the BCH interrupt is
signaled.
19–16 This is the chip enable number corresponding to the NAND device from which this data came.
COMPLETED_CE
15–8 Count of symbols in error during processing of first block of flash (metadata block). The number of
STATUS_BLK0 errors reported will be in the range of 0 to the ECC correction level for block 0.
0x00 ZERO — No errors found on block.

0x01 ERROR1 — One error found on block.
0x02 ERROR2 — One errors found on block.
0xFE UNCORRECTABLE — Block exhibited uncorrectable errors.
0xFF ERASED — Page is erased.
RSVD1
4 1 = All data bits of this transaction are ONE.
ALLONES
3 1 = At least one correctable error encountered during last processing cycle.
CORRECTED
2 1 = Uncorrectable error encountered during last processing cycle.
UNCORRECTABLE
RSVD0 This field is reserved.
17.6.3 Hardware ECC Accelerator Mode Register (BCH_MODE)

The BCH MODE register provides additional mode controls.
Contains additional global mode controls for the BCH engine.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD
ERASE_THRESHOLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_MODE field descriptions

Field Description
RSVD
BCH_MODE field descriptions (continued)

Field Description
ERASE_ This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased.
THRESHOLD For SLC NAND devices, this value should be programmed to 0 (meaning that the entire page should
consist of bytes of 0xFF. For MLC NAND devices, bit errors may occur on reads (even on blank pages),
so this threshold can be used to tune the erased page checking algorithm.
17.6.4 Hardware BCH ECC Loopback Encode Buffer Register

(BCH_ENCODEPTR)
When performing memory to memory operations, indicates the address of the encode
buffer. This register should be programmed before writing a 1 to the M2M_ENABLE bit
in the CTRL register.
For memory to memory operations, this register is used as the pointer to the encoded
data, which is an output when encoding and an input while decoding.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_ENCODEPTR field descriptions

Field Description
ADDR Address pointer to encode buffer. This is the source for decode operations and the destination for encode
operations. This value must be aligned on a 4 bytes boundary.
17.6.5 Hardware BCH ECC Loopback Data Buffer Register

(BCH_DATAPTR)
When performing memory to memory operations, indicates the address of the data buffer.
For memory to memory operations, this register is used as the pointer to the data to
encode or the destination buffer for decode operations.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BCH_DATAPTR field descriptions

Field Description
ADDR Address pointer to data buffer. This is the source for encode operations and the destination for decode
operations. This register should be programmed before writing a 1 to the M2M_ENABLE bit in the CTRL
register. This value must be aligned on a 4 byte boundary.
17.6.6 Hardware BCH ECC Loopback Metadata Buffer Register

(BCH_METAPTR)
When performing memory to memory operations, indicates the address of the metadata
buffer.
For memory to memory operations, this register is used as the pointer to the metadata to
encode or the extracted metadata for decode operations.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_METAPTR field descriptions

Field Description
ADDR Address pointer to metadata buffer. This is the source for encode metadata read operations and the
destination for metadata decode operations. This register should be programmed before writing a 1 to the
M2M_ENABLE bit in the CTRL register. This value must be aligned on a 4 bytes boundary.
17.6.7 Hardware ECC Accelerator Layout Select Register

(BCH_LAYOUTSELECT)
The BCH LAYOUTSELECT register provides a mapping of chip selects to layout
registers.
When the BCH engine receives a request to process a data block from the GPMI
interface, it will use this register to map the incoming chip select to one of the four
possible flash layout registers

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CS15_ CS14_ CS13_ CS12_ CS11_ CS10_ CS9_ CS8_
W SELECT SELECT SELECT SELECT SELECT SELECT SELECT SELECT
Reset 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CS7_ CS6_ CS5_ CS4_ CS3_ CS2_ CS1_ CS0_
W SELECT SELECT SELECT SELECT SELECT SELECT SELECT SELECT
Reset 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0
BCH_LAYOUTSELECT field descriptions

Field Description
31–30 Selects which layout is used for chip select 15.
CS15_SELECT
CS14_SELECT
CS13_SELECT
CS12_SELECT
CS11_SELECT
CS10_SELECT
CS9_SELECT
CS8_SELECT
CS7_SELECT
CS6_SELECT
CS5_SELECT
CS4_SELECT
CS3_SELECT
CS2_SELECT
CS1_SELECT
CS0_SELECT Selects which layout is used for chip select 0.

17.6.8 Hardware BCH ECC Flash 0 Layout 0 Register

(BCH_FLASH0LAYOUT0)
The flash format register contains a description of the logical layout of data on the flash
device. This register is used in conjunction with the FLASH0LAYOUT1 register to
control the format for the devices selecting layout 0 in the LAYOUTSELECT register.
Each pair of layout registers describes one of four supported flash configurations.
Software should program the LAYOUTSELECT register for each supported GPMI chip
select to select from one of the four layout values. Each pair of registers contains settings
that are used by the BCH block while reading / writing the flash page to control data,
metadata, and flash page sizes as well as the ECC correction level. The first block written
to flash can be programmed to have different ECC, metadata, and data sizes from
subsequent data blocks on the device. In addition, the number of blocks stored on a page
of flash is not fixed, but instead is determined by the number of bytes consumed by the
initial (block 0) and subsequent data blocks.
See sections Flash Page Layout and Determining the ECC layout for a device for more
detail information on setting up the flash layout registers.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLOCKS META_SIZE
W
Reset 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GF13_0_GF14_1
ECC0 DATA0_SIZE
W
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0
BCH_FLASH0LAYOUT0 field descriptions

Field Description
31–24 Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that
NBLOCKS only the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total
of 9 blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the
hardware.

BCH_FLASH0LAYOUT0 field descriptions (continued)

Field Description
23–16 Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0
META_SIZE to 255 bytes for metadata—if set to 0, no metadata will be stored. Metadata is stored before the
associated data in block 0. If the DATA0_SIZE field is programmed to a 0, then metadata effectively be
stored with its own parity. When both the metadata and data0 fields are programmed with non-zero
values, the first block will contain both portions of data and covered by a single parity block.
15–11 Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the
ECC0 associated data from the DATA0_SIZE field.
0x0 NONE — No ECC to be performed

0x1 ECC2 — ECC 2 to be performed
0xA ECC20 — ECC 20 to be performed
0xB ECC22 — ECC 22 to be performed
0xC ECC24 — ECC 24 to be performed
0xD ECC26 — ECC 26 to be performed
0xE ECC28 — ECC 28 to be performed
0xF ECC30 — ECC 30 to be performed
10 Select GF13 or GF14: 0-GF13; 1-GF14
GF13_0_GF14_1
DATA0_SIZE Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page. If set to 0,
the first block only contains metadata.


(BCH_FLASH0LAYOUT1)
control the format for the device selecting layout 0 in the LAYOUTSELECT register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAGE_SIZE
W
Reset 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GF13_0_GF14_1
ECCN DATAN_SIZE
W
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Field Description
31–16 Indicates the total size of the flash page (in bytes). This should be set to the page size including spare
PAGE_SIZE area. The page size is programmable to accomodate different flash configurations that may be available in
the future.
15–11 Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only
ECCN contain data (no metadata).



Field Description
GF13_0_GF14_1
DATAN_SIZE Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page.
The size of subsequent data blocks does not have to match the data size for block 0, which is important
when metadata is stored separately or for balancing the amount of data stored in each block.

(BCH_FLASH1LAYOUT0)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLOCKS META_SIZE
W
Reset 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GF13_0_GF14_1
R
ECC0 DATA0_SIZE
W
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Field Description
hardware.
23–16 Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design supports from
META_SIZE 0 to 255 bytes for metadata—if set to 0, no metadata will be stored. Metadata is stored before the
associated data is in block 0. If the DATA0_SIZE field is programmed to a 0, then metadata effectively be
values, the first block will contain both portions of data and covered by a single parity block.



Field Description
GF13_0_GF14_1
the first block will contains metadata.

(BCH_FLASH1LAYOUT1)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAGE_SIZE
W
Reset 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GF13_0_GF14_1
ECCN DATAN_SIZE
W
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Field Description
the future.


Field Description
GF13_0_GF14_1

(BCH_FLASH2LAYOUT0)

Address: 11_4000h base + C0h offset = 11_40C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLOCKS META_SIZE
W
Reset 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GF13_0_GF14_1
R
ECC0 DATA0_SIZE
W
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Field Description
NBLOCKS only the DATA0 block is present and a value of 8 indicates that eight subsequent blocks are present for a
total of nine blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by
the hardware.
values, the first block will contain both portions of data and will be covered by a single parity block.



Field Description
GF13_0_GF14_1
the first block will only contain metadata.

(BCH_FLASH2LAYOUT1)
Address: 11_4000h base + D0h offset = 11_40D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAGE_SIZE
W
Reset 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GF13_0_GF14_1
ECCN DATAN_SIZE
W
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0


Field Description
the future.

GF13_0_GF14_1

(BCH_FLASH3LAYOUT0)

Address: 11_4000h base + E0h offset = 11_40E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLOCKS META_SIZE
W
Reset 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GF13_0_GF14_1
ECC0 DATA0_SIZE
W
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Field Description
hardware.
values, the first block will contain both portions of data and will be covered by a single parity block.



Field Description
GF13_0_GF14_1
the first block will only contain metadata.

(BCH_FLASH3LAYOUT1)
Address: 11_4000h base + F0h offset = 11_40F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAGE_SIZE
W
Reset 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GF13_0_GF14_1
ECCN DATAN_SIZE
W
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0


Field Description
the future.

GF13_0_GF14_1
17.6.16 Hardware BCH ECC Debug Register0 (BCH_DEBUG0n)

The hardware BCH accelerator internal state machines and signals can be seen in the
ECC debug register.
The BCH_DEBUG0 register provides access to various internal state information which
might prove useful during hardware debug and validation.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD1
KES_DEBUG_SYNDROME_SYMBOL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KES_DEBUG_PAYLOAD_FLAG
KES_DEBUG_SHIFT_SYND
RSVD0
BM_KES_TEST_BYPASS
R
KES_DEBUG_MODE4K
KES_DEBUG_STALL
KES_STANDALONE
KES_DEBUG_STEP
KES_DEBUG_KICK
DEBUG_REG_SELECT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_DEBUG0n field descriptions

Field Description
RSVD1
24–16 The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine
KES_DEBUG_ whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled.
SYNDROME_
SYMBOL 0x0 NORMAL — Bus master address generator for SYND_GEN writes operates normally.
0x1 TEST_MODE — Bus master address generator always addresses last four bytes in Auxiliary block.
15 Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the
KES_DEBUG_ syndrome register array at the input to the KES engine. After shifting in 16 symbols, one can kick off both
SHIFT_SYND KES and CF cycles by toggling BCH_DEBUG0_KES_DEBUG_KICK. Make sure that set
KES_BCH_DEBUG0_KES_STANDALONE mode to 1 before kicking.

BCH_DEBUG0n field descriptions (continued)

Field Description
14 When running the stand alone debug mode on the error calculator, the state of this bit is presented to the
KES_DEBUG_ KES engine as the input payload flag.
PAYLOAD_FLAG
0x1 DATA — Payload is set for 512 bytes data block.
0x1 AUX — Payload is set for 65 or 19 bytes auxiliary block.
13 When running the stand alone debug mode on the error calculator, the state of this bit is presented to the
KES_DEBUG_ KES engine as the input mode (4K or 2K pages).
MODE4K
0x1 4k — Mode is set for 4K NAND pages.
0x1 2k — Mode is set for 2K NAND pages.
12 Toggling causes KES engine FSM to start as if kick by the Bus Master. This allows stand alone testing of
KES_DEBUG_ the KES and Chien Search engines. Be sure to set KES_BCH_DEBUG0_KES_STANDALONE mode to 1
KICK before kicking.
11 Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and
KES_ suppress toggling the CF_BM_DONE signal by the CF engine.
STANDALONE
0x0 NORMAL — Bus master address generator for SYND_GEN writes operates normally.
10 Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and
KES_DEBUG_ completed processing a block.
STEP
9 Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but
KES_DEBUG_ before notifying the bus master that the KES computation is complete. This allows a diagnostic to stall the
STALL FSM after each blocks key equations are solved. This also has the effect of stalling the CSFE search
engine so it's state can be examined after it finishes processing the KES stalled block.
0x0 NORMAL — KES FSM proceeds to next block supplied by bus master.
0x1 WAIT — KES FSM waits after current equations are solved and the search engine is started.
8 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics
BM_KES_TEST_ can preload all payload, parity bytes and computed syndrome bytes for test the KES engine.
BYPASS
0x0 NORMAL — Bus master address generator for SYND_GEN writes operates normally.
RSVD0
DEBUG_REG_ The value loaded in this bit field is used to select the internal register state view of KES engine or the
SELECT Chien search engine.
17.6.17 KES Debug Read Register (BCH_DBGKESREAD)

The hardware BCH ECC accelerator key equation solver internal state machines and
signals can be seen in the ECC debug registers.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUES
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_DBGKESREAD field descriptions

Field Description
VALUES This register returns the ROM BIST CRC value after a BIST test.
17.6.18 Chien Search Debug Read Register

(BCH_DBGCSFEREAD)
The hardware BCH ECC accelerator Chien Search internal state machines and signals
can be seen in the ECC debug registers.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUES
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_DBGCSFEREAD field descriptions

Field Description
VALUES Reserved
17.6.19 Syndrome Generator Debug Read Register

(BCH_DBGSYNDGENREAD)
The hardware BCH ECC accelerator syndrome generator internal state machines and
signals can be seen in the ECC debug registers.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUES
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BCH_DBGSYNDGENREAD field descriptions

Field Description
VALUES Reserved
17.6.20 Bus Master and ECC Controller Debug Read Register

(BCH_DBGAHBMREAD)
The hardware BCH ECC accelerator bus master, ECC controller internal state machines,
and signals can be seen in the ECC debug registers.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VALUES
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_DBGAHBMREAD field descriptions

Field Description
VALUES Reserved
17.6.21 Block Name Register (BCH_BLOCKNAME)

Read only view of the block name string BCH.
Fixed pattern read only value is for test purposes. It can be read as an ASCII string with
the zero termination coming from the first byte of the BLOCKVERSION register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R NAME
W
Reset 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0
BCH_BLOCKNAME field descriptions

Field Description
NAME The name is in the ASCII characters BCH (0x20, H, C, B).

17.6.22 BCH Version Register (BCH_VERSION)
This register always returns a known read value for debug purposes and indicates the
version of the block and RTL version in use.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_VERSION field descriptions

Field Description
31–24 Fixed read-only value indicates the MAJOR field of the RTL version.
MAJOR
23–16 Fixed read-only value indicates the MINOR field of the RTL version.
MINOR

17.6.23 Hardware BCH ECC Debug Register 1 (BCH_DEBUG1)
The BCH_DEBUG1 register provides erased zero count information and pre-erase check.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEBUG1_PREERASECHK
R RSVD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD ERASED_ZERO_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCH_DEBUG1 field descriptions

Field Description
31 Blank page enables pre-erase check.
DEBUG1_
PREERASECHK 0x0 Turn off pre-erase check
0x1 Turn on pre-erase check
RSVD

BCH_DEBUG1 field descriptions (continued)

Field Description
ERASED_ The zero counts on one page.
ZERO_COUNT


Chapter 18
Clock Controller Module (CCM)
18.1 Overview
The Clock Control Module (CCM) generates and controls clocks to the various modules
in the design and manages low power modes. This module uses the available clock
sources to generate the clock roots.
The Clock Controller Module controls the following functions:
• Uses the available clock sources to generate clock roots to various parts of the chip:
• PLL1 also referenced as ARM PLL
• PLL2 also referenced as System PLL
• PLL3 also referenced as USB1 PLL
• PLL4 also referenced as Audio PLL
• PLL5 also referenced as Video PLL
• PLL6 also referenced as ENET PLL
• PLL7 also referenced as USB2 PLL (This PLL is only used by the USB UTM
interface through a direct connection.)
• PLL8 also referenced as MLB PLL
• Uses programmable bits to control frequencies of the clock roots.
• Controls the low power mechanism.
• Provides control signals to LPCG for gating clocks.
• Provides handshake with SRC for reset performance.
• Provides handshake with GPC for support of power gating operations.
18.1.1 Features
The CCM includes these distinctive features:
• Provides root clock to SoC modules based on several source clocks.
• Arm core root clock is generated from a dedicated source clock.

Overview
• Includes separate dividers to control generation of core and bus root clocks (AXI,
AHB, IPG).
• Includes separate dividers and clock source selectors for each serial root clock.
• Optional external clocks to bypass PLL clocks.
• Selects clock signals to output on CCM_CLKO1 and CCM_CLKO2 onto the pads
for observability.
• Controllable registers are accessible via IP bus.
• Manages the Low Power Modes, namely RUN, WAIT and STOP. The gating of the
peripheral clocks is programmable in RUN and WAIT modes.
• Manages frequency scaling procedure for Arm core clock by shifting between PLL
sources, without loss of clocks.
• Manages frequency scaling procedure for peripheral root clock by programmable
divider. The division is done on the fly without loss of clocks.
• Interface for the following IPs:
• PLL - Interfaces for each PLL
• LPCG - Low Power Clock Gating unit
• SRC - System Reset Controller
• GPC - General Power Controller
18.1.2 CCM Block Diagram

Chapter 18 Clock Controller Module (CCM)
CCM_LPM CCM_CLK_LOGIC
clk
enable
signals
CCM_HND_SK
Low Power
Clock Gating
CCM_ANALOG (LPCG) System
Clocks
PLLs CCM_CLK_ CLK_ROOTS

CCM_CLK_SWITCHER ROOT_GEN
XTALOSC, PLLs CCM_CLK_IGNITION CCM_CLK_SRC_DIV CLKO1, CLKO2
PGC RESET BOOT

GENERATOR DECODER
GPC SRC
Figure 18-1. Block Diagram
CCM contains the following sub-blocks:

Table 18-1. CCM Sub-blocks
CCM_CLK_SRC_DIV Sub-block Description
CCM_CLK_IGNITION Manages the ignition process. This module starts its functionality after CCM comes out
of reset. It manages the process that begins with starting the OSC, PLLs and finishes
with creation of stable output root clocks after reset.
CCM_CLK_SWITCHER Receives the clock outputs of the PLLs, together with the bypass clocks for the PLLs,
and generates switcher clock outputs (pll1_sw_clk, pll3_sw_clk) for the
CCM_CLK_ROOT_GEN sub-module.
CCM_CLK_ROOT_GEN Receives the main clocks (PLLs / PFDs) and generates the output root clocks.
CCM_CLK_LOGIC Generates the clock enables. It generates the clock enable signals based on info from
CCM_LPM and CCM_IP. The clock enables are used in LPCG to turn off and on the
split clocks.

External Signals
Table 18-1. CCM Sub-blocks (continued)

CCM_CLK_SRC_DIV Sub-block Description
CCM_LPM Manages the low power modes of the IC.
CCM_CLK_SRC_DIV Muxes different clocks to two output clocks, CCM_CLKO1 and CCM_CLKO2, for
observability. These output clocks are connected to the pads and can provide support
for testing.
CCM_HND_SK Manages the handshake when changing certain root clock dividers that require
handshake.

The following table describes the external signals of CCM:
Table 18-2. CCM External Signals
CCM_CLKO1 Observability clock 1 output CSI0_MCLK ALT3 O
GPIO_0 ALT0
GPIO_19 ALT3
GPIO_5 ALT3
CCM_CLKO2 Observability clock 2 output GPIO_3 ALT4 O
NANDF_CS2 ALT4
CCM_PMIC_STBY_REQ Goes to PMIC_STBY_REQ PMIC_STBY_REQ No Muxing O
pin, which notifies external (ALT0)
power management IC to
move from functional voltage
to standby voltage.
CCM_REF_EN_B Enable external reference GPIO_9 ALT3 O
clock (CKIH)
CCM_PLL3_BYP PLL3 bypass clock RGMII_TD1 ALT7 I
18.3 CCM Clock Tree

The following figures (Part 1 and Part 2) show the clock tree configuration and clock
roots for CCM.
For detailed sub-block information, see:
• Clock Switcher
• Clock Root Generator

• Low Power Clock Gating module (LPCG)

• System Clocks
NOTE
The default frequency values (in MHz) for the PLLs and PFDs
are shown in the Clock Tree diagram that follows. The PLLs
and PFDs control registers may be reprogrammed according to
the speed grade of the SoC being used, but should not exceed
that maximum setting for that speed grade.

CCM Clock Tree
CLOCK SWITCHER CLOCK ROOT GEN SYSTEM

CCSR[PLL1_SW_CLK_SEL] CLOCKS
PLL1 800 ARM_CLK_ROOT
Note: Typical value OSC
/1
CACRR[ARM_PODF]
clock source goes to ARM Domain and returns to CCM
/2
ARM domain divider
CBCMR[PRE_PERIPH2_CLK_SEL] CBCDR[periph2_clk_sel] *
CCSR[STEP_SEL] CBCDR[MMDC_CH1_AXI_PODF]
CBCDR[periph2_clk2_podf]
PLL2 528 MMDC_CH1_CLK_ROOT
PFD0 352 /2 /1
CBCMR[PERIPH2_CLK2_SEL]
PFD1 594 CBCMR[PRE_PERIPH_CLK_SEL] CBCDR[MMDC_CH0_AXI_PODF]
PFD2 396 MMDC_CH0_CLK_ROOT MMDC
* OR'd with PLL Bypass (from JTAG)
cg /1 TZASC
CCSR[pll3_sw_clk_sel] * /2 CBCDR[AHB_PODF]
AHB_CLK_ROOT
cg
/4
CBCMR[PERIPH_CLK2_SEL] CBCDR[periph_clk_sel] * AIPSTZ -
CCM_PLL3_BYP AHB uSDHC
PLL3 480
OSC(24M)
pll3_sw_clk /1 CBCDR[IPG_PODF] ARM -
MMDC CH0
CBCDR[periph_clk2_podf] IPG_CLK_ROOT
PFD0 720 CSCMR1[USDHCn_CLK_SEL]
cg /2
PERCLK_CLK_ROOT
WDOG
PFD1 540 CSCDR1[USDHCn_PODF] cg /1 EPIT, GPT

I2C, PWM
PFD2 508.2 CSCMR1[PERCLK_PODF]
PFD3 454.7
cg /2
USDHC1_CLK_ROOT
USDHC1
/2
PLL_AUDIOn[POST_DIV_SELECT]
cg USDHC2
PLL4 650 /1 USDHC2_CLK_ROOT
CCM_ANALOG_MISC2n[VIDEO_DIV]
PLL5 650 /1 /1
PLL_VIDEOn[POST_DIV_SELECT]
cg /2 USDHC3_CLK_ROOT
USDHC3
APBH
cg /2 USDHC4_CLK_ROOT
USDHC4
CS1CDR[SSI1_CLK_PRED] CS1CDR[SSI1_CLK_PODF]
SSI1_CLK_ROOT
cg /4 /2 SSI
SSI2_CLK_ROOT
cg /4 /2 SSI
SSI3_CLK_ROOT
cg /4 /2 SSI
CSCMR1[SSIn_CLK_SEL] CBCMR[GPU2D_AXI_CLK_SEL]
cg GPU2D
CBCDR[AXI_ALT_SEL] GPU2D_AXI_CLK_ROOT
CBCDR[AXI_SEL] CBCMR[GPU3D_AXI_CLK_SEL]
cg GPU3D
GPU3D_AXI_CLK_ROOT
/2 CBCMR[PCIE_AXI_CLK_SEL]
CBCDR[AXI_PODF]
cg PCIE
AXI PCIE_AXI_CLK_ROOT
INDEX: CSCDR3[IPU1_HSP_CLK_SEL] VDO_AXI_CLK_ROOT cg
VDOA
CBCMR[VDO_AXI_CLK_SEL]
Static Divider AXI_CLK_ROOT DTCP
cg MLB
2-bit Divider cg
/4 cg /2
IPU1_HSP_CLK_ROOT DCIC
PLL3_120M
3-bit Divider IPU

CSCDR3[IPU1_HSP_PODF]
IPU2_HSP_CLK_ROOT DCIC
6-bit Divider cg /2 IPU
MUX CSCDR3[IPU2_HSP_CLK_SEL] CSCDR3[IPU2_HSP_PODF]

CBCMR[GPU2D_CLK_SEL]
cg LPCG Gating GPU2D_CORE_CLK_ROOT
Option cg /1 GPU2D
CBCMR[GPU2D_CORE_CLK_PODF]
MUX SELECT CSCMR1[ACLK_EIM_SLOW_SEL]
REGISTER[BIT] ACLK_EIM_SLOW_CLK_ROOT
cg /2 EIM
DIVIDER SELECT CSCMR1[ACLK_EIM_SLOW_PODF]

CSCMR1[ACLK_SEL]
MMDC CH0
REGISTER[BIT]
ACLK_CLK_ROOT
PLL3 PFD3
PLL3 PFD2
PLL3 PFD0
PLL3 PFD1
PLL2 PFD2
PLL2 PFD1
PLL2 PFD0
pll3_sw_clk
CLOCK ROOT OUT /2 MIPI_PIXEL_CLK

MIPI
CSCMR1[ACLK_PODF]
PLL5
PLL4
AXI
OF CCM continued on next page..
Figure 18-2. Clock Tree - Part 1

CLOCK ROOT GEN SYSTEM

CLOCKS
AXI
PLL5
PLL4
PLL3 PFD3
PLL3 PFD2
PLL3 PFD0
PLL3 PFD1
PLL2 PFD2
PLL2 PFD1
PLL2 PFD0
MMDC CH0
pll3_sw_clk
CS2CDR[ENFC_CLK_SEL]
CS2CDR[ENFC_CLK_PRED]
ENFC_CLK_ROOT
PLL2 (528M) /2 /1 cg IOMUX
GPMI
CBCMR[GPU3D_CORE_CLK_SEL] CS2CDR[ENFC_CLK_PODF]
CBCMR[GPU3D_CORE_PODF]
GPU3D_CORE_CLK_ROOT
cg
/1 GPU3D
CBCMR[GPU3D_SHADER_CLK_SEL]
CBCMR[GPU3D_SHADER_PODF]
GPU3D_SHADER_CLK_ROOT
cg /1 GPU3D
CBCMR[VPU_AXI_CLK_SEL]
CSCDR1[VPU_AXI_PODF]
VPU_AXI_CLK_ROOT
cg /1 VPU
CHSCCDR[IPU1_DI0_CLK_SEL]
CHSCCDR[IPU1_DI0_PRE_CLK_SEL]
CHSCCDR[IPU1_DI0_PODF] ipp_di0_clk
ipp_di1_clk IPU1_DI0_CLK_ROOT
/3
ipu1_di0_pre_clk
cg IPU
CHSCCDR[IPU1_DI1_CLK_SEL]
CHSCCDR[IPU1_DI1_PRE_CLK_SEL] ipp_di0_clk
CHSCCDR[IPU1_DI1_PODF] ipp_di1_clk IPU1_DI1_CLK_ROOT
/3 IPU
ipu1_di1_pre_clk
cg
CSCDR2[IPU2_DI0_PRE_CLK_SEL] CSCDR2[IPU2_DI0_CLK_SEL]
ipp_di0_clk
CSCDR2[IPU2_DI0_PODF] ipp_di1_clk
IPU2_DI0_CLK_ROOT
cg
/3
ipu2_di0_pre_clk
IPU
CSCDR2[IPU2_DI1_PRE_CLK_SEL] CSCDR2[IPU2_DI1_CLK_SEL]
CSCDR2[IPU2_DI1_PODF] ipp_di0_clk
ipp_di1_clk IPU2_DI1_CLK_ROOT
ipu2_di1_pre_clk
cg /3 IPU
CS2CDR[LDB_DI0_CLK_SEL] LDB_DI0_SERIAL_CLK_ROOT
cg LDB
MMDC_CH1 /7
LDB_DI0_IPU
LDB_DI1_SERIAL_CLK_ROOT
CSCMR2[LDB_DI0_IPU_DIV] cg LDB
INDEX: LDB_DI1_IPU
MMDC_CH1
/7
CDCDR[HSI_TX_CLK_SEL]
Static Divider CSCMR2[LDB_DI1_IPU_DIV] CDCDR[HSI_TX_PODF]
CS2CDR[LDB_DI1_CLK_SEL] HSI_TX_CLK_ROOT
1-bit Divider PLL3_120M
cg /2 MIPI HSI
CDCDR[SPDIF0_CLK_SEL]
2-bit Divider CDCDR[SPDIF0_CLK_PRED] CDCDR[SPDIF0_CLK_PODF]
SPDIF0_CLK_ROOT
3-bit Divider
cg
/2 /8 SPDIF
CDCDR[SPDIF1_CLK_SEL]
6-bit Divider CDCDR[SPDIF1_CLK_PRED] CDCDR[SPDIF1_CLK_PODF]
SPDIF1_CLK_ROOT
MUX
cg /2 /8 ASRC
CSCMR2[ESAI_CLK_SEL]
LPCG Gating ESAI_CLK_ROOT
cg
Option
cg /2 /8 ESAI
CS1CDR[ESAI_CLK_PRED] CS1CDR[ESAI_CLK_PODF]
MUX SELECT
REGISTER[BIT]
cg /8 cg
/2
CAN_CLK_ROOT
CSCDR2[ECSPI_CLK_PODF] FLEXCAN
CSCMR2[CAN_CLK_PODF] ECSPI_CLK_ROOT
DIVIDER SELECT cg /1 ECSPI
CSCDR1[UART_CLK_PODF]
REGISTER[BIT] UART_CLK_ROOT
CLOCK ROOT OUT
cg
/6 /1 UART
HDMI
VIDEO_27M_CLK_ROOT
OF CCM
/4 /5 cg MIPI
VPU
(no CG for VPU)
Figure 18-3. Clock Tree - Part 2

System Clocks
18.4 System Clocks

The table found here shows the CCM output clocks' system-level connectivity.
The gating option in the table can either be CGR bit or clock enable from the block itself.
Applicable override bits are also shown.
Table 18-3. System Clocks, Gating, and Override
Module Module Clock Clock Root Module Clock Gating Module Override Enable
Enable1
AIPSTZn hclk ahb_clk_root CCGR0[CG0]
(aips_tz1_clk_enable)
CCGR0[CG1]
(aips_tz2_clk_enable)
APBH hclk usdhc3_clk_root CCGR0[CG2]
(apbhdma_hclk_enable)
sec_mst_hclk usdhc3_clk_root CCGR0[CG2]
(apbhdma_hclk_enable)
Arm clk_ahb ahb_clk_root CCGR0[CG11]
(arm_dbg_clk_enable)
clk_apb_dbg ahb_clk_root CCGR0[CG11]
clk_atb ahb_clk_root CCGR0[CG11]
ipg_clk ipg_clk_root CCGR0[CG11]
trace_clk_in ahb_clk_root CCGR0[CG11]
ASRC asrck_clock_d spdif1_clk_root
ipg_clk ahb_clk_root CCGR0[CG3]
(asrc_clk_enable)
mem_clk ahb_clk_root CCGR0[CG3]
(asrc_clk_enable)
AUDMUX ipg_clk_s ipg_clk_root
CAAM sec_mem_clk ahb_clk_root CCGR0[CG4]
(caam_secure_mem_clk_ena
ble)
aclk ahb_clk_root CCGR0[CG5]
(caam_wrapper_aclk_enable)
ckil ckil_sync_clk_root
(caam_wrapper_ipg_enable)
ipg_clk_s ipg_clk_root
exsc_aclk_exsc ahb_clk_root CCGR0[CG5]
(caam_wrapper_aclk_enable)

Table 18-3. System Clocks, Gating, and Override (continued)

Enable1
CCM analog_apb_clk ipg_clk_root
ipg_clk ipg_clk_root
CSU ap_ckil_clk ckil_sync_clk_root
DBGMON clk ipg_clk_root
DCICn hsp_clk ipu1_hsp_clk_root CCGR0[CG12]
(dcic1_clk_enable)
CCGR0[CG13]
(dcic2_clk_enable)
ipg_clk_s ipu1_hsp_clk_root CCGR0[CG12]
(dcic1_clk_enable)
CCGR0[CG13]
(dcic2_clk_enable)
DTCP clk axi_clk_root CCGR0[CG14]
(dtcp_clk_enable)
ram_CLK axi_clk_root CCGR0[CG14]
(dtcp_clk_enable)
rom_CLK axi_clk_root CCGR0[CG14]
(dtcp_clk_enable)
sec_mst_hclk axi_clk_root CCGR0[CG14]
(dtcp_clk_enable)
ECSPIn ipg_clk ipg_clk_root CCGR1[CG0]
(ecspi1_clk_enable)
CCGR1[CG1]
(ecspi2_clk_enable)
CCGR1[CG2]
(ecspi3_clk_enable)
CCGR1[CG3]
(ecspi4_clk_enable)
CCGR1[CG4]
(ecspi5_clk_enable)
ipg_clk_32k ckil_sync_clk_root
ipg_clk_per ecspi_clk_root CCGR1[CG0]
(ecspi1_clk_enable)
CCGR1[CG1]
(ecspi2_clk_enable)
CCGR1[CG2]
(ecspi3_clk_enable)
CCGR1[CG3]
(ecspi4_clk_enable)
CCGR1[CG4]
(ecspi5_clk_enable)

System Clocks

Enable1
EIM aclk aclk_eim_slow_clk_root CCGR6[CG5]
(eim_slow_clk_enable)
aclk_slow aclk_eim_slow_clk_root CCGR6[CG5]
aclk_exsc aclk_eim_slow_clk_root CCGR6[CG5]
ENET ipg_clk ahb_clk_root CCGR1[CG5]
(enet_clk_enable)
ipg_clk_mac0 ahb_clk_root CCGR1[CG5]
(enet_clk_enable)
ipg_clk_mac0_s ipg_clk_root CCGR1[CG5]
(enet_clk_enable)
ipg_clk_time ipg_clk_root CCGR1[CG5]
(enet_clk_enable)
mac0_rxmem_clk ahb_clk_root CCGR1[CG5]
(enet_clk_enable)
mac0_txmem_clk ahb_clk_root CCGR1[CG5]
(enet_clk_enable)
EPITn ipg_clk ipg_clk_root CCGR1[CG6] CMEOR[mod_en_ov_epit]
(epit1_clk_enable)
CCGR1[CG7]
(epit2_clk_enable)
ipg_clk_highfreq perclk_clk_root CCGR1[CG6]
(epit1_clk_enable)
CCGR1[CG7]
(epit2_clk_enable)
ESAI extal_clk esai_clk_root CCGR1[CG8]
(esai_clk_enable)
ipg_clk_esai ahb_clk_root CCGR1[CG8]
(esai_clk_enable)
(esai_clk_enable)
FLEXCANn ipg_clk ipg_clk_root CCGR0[CG7]
(can1_clk_enable)
CCGR0[CG9]
(can2_clk_enable)
ipg_clk_chi ipg_clk_root CCGR0[CG7]
(can1_clk_enable)


Enable1
CCGR0[CG9]
(can2_clk_enable)
ipg_clk_pe can_clk_root CCGR0[CG8] CMEOR[mod_en_ov_can
(can1_serial_clk_enable) 1_cpi]
CCGR0[CG10] CMEOR[mod_en_ov_can
(can2_serial_clk_enable) 2_cpi]
ipg_clk_pe_nogate can_clk_root CCGR0[CG8]
(can1_serial_clk_enable)
CCGR0[CG10]
(can2_serial_clk_enable)
ram_CLK ipg_clk_root CCGR0[CG7]
(can1_clk_enable)
CCGR0[CG9]
(can2_clk_enable)
GPC ipg_clk ipg_clk_root
pgc_clk ipg_clk_root
sys_clk ipg_clk_root
GPIOn ipg_clk_s ipg_clk_root
GPMI u_bch_input_apb_clk usdhc3_clk_root CCGR4[CG12]
(rawnand_u_bch_input_apb_c
lk_enable)
u_gpmi_bch_input_bch_ usdhc4_clk_root CCGR4[CG13]
clk (rawnand_u_gpmi_bch_input_
bch_clk_enable)
u_gpmi_bch_input_gpmi enfc_clk_root CCGR4[CG14]
_io_clk (rawnand_u_gpmi_bch_input_
gpmi_io_clk_enable)
u_gpmi_input_apb_clk usdhc3_clk_root CCGR4[CG15]
(rawnand_u_gpmi_input_apb
_clk_enable)
GPT ipg_clk ipg_clk_root CCGR1[CG10] CMEOR[mod_en_ov_gpt]
(gpt_clk_enable)
(gpt_serial_clk_enable)
GPU2D ACLK0 gpu2d_axi_clk_root CCGR1[CG12] CMEOR[mod_en_ov_gpu
(gpu2d_clk_enable) 2d]
ACLK1 gpu2d_axi_clk_root CCGR1[CG12]
(gpu2d_clk_enable)
clk2x gpu2d_core_clk_root CCGR1[CG12] CMEOR[mod_en_ov_gpu

System Clocks

Enable1
HCLK ahb_clk_root CCGR1[CG12] CMEOR[mod_en_ov_gpu
V2D_ACLK gpu2d_axi_clk_root CCGR1[CG12]
(gpu2d_clk_enable)
V2D_clk2x gpu2d_core_clk_root CCGR1[CG12]
(gpu2d_clk_enable)
V2D_HCLK ahb_clk_root CCGR1[CG12]
(gpu2d_clk_enable)
sec_mst_hclk ahb_clk_root CCGR1[CG12] CMEOR[mod_en_ov_gpu
GPU3D ACLK0 gpu3d_axi_clk_root CCGR1[CG13] CMEOR[mod_en_ov_gpu
ACLK1 gpu3d_axi_clk_root CCGR1[CG13]
(gpu3d_clk_enable)
clk1x gpu3d_core_clk_root CCGR1[CG13] CMEOR[mod_en_ov_gpu
clkShader gpu3d_shader_clk_root CCGR1[CG13]
(gpu3d_clk_enable)
HCLK ahb_clk_root CCGR1[CG13] CMEOR[mod_en_ov_gpu
sec_mst_hclk ahb_clk_root CCGR1[CG13] CMEOR[mod_en_ov_gpu
HDMI sec_mst_hclk ahb_clk_root CCGR2[CG0]
(hdmi_tx_enable)
iahbclk ahb_clk_root CCGR2[CG0]
(hdmi_tx_enable)
icecclk ckil_sync_clk_root
ihclk ahb_clk_root CCGR2[CG0]
(hdmi_tx_enable)
isfrclk video_27m_clk_root CCGR2[CG2]
(hdmi_tx_isfrclk_enable)
vl_sms_proc_sms_hdmi ipg_clk_root
_sram_27_clk_sms
I2Cn ipg_clk_patref perclk_clk_root CCGR2[CG3]
(i2c1_serial_clk_enable)
CCGR2[CG4]
CCGR2[CG5]
IOMUXC ipt_clk_io enfc_clk_root CCGR2[CG7]
(iomux_ipt_clk_io_enable)
IPUn hsp_clk ipu1_hsp_clk_root CCGR3[CG0]
(ipu1_clk_enable)


Enable1
CCGR3[CG3]
(ipu2_clk_enable)
ipp_di_0_ext_clk ipu1_di0_clk_root CCGR3[CG1]
(ipu1_di0_clk_enable)
ipu1_di0_pre_clk ipu2_di0_clk_root
CCGR3[CG4]
ipu2_di0_pre_clk
ipp_di_1_ext_clk ipu1_di1_clk_root CCGR3[CG2]
ipu1_di1_pre_clk ipu2_di1_clk_root
CCGR3[CG5]
ipu2_di1_pre_clk
ipu_master_hclk ahb_clk_root CCGR3[CG0]
(ipu1_clk_enable)
CCGR3[CG3]
(ipu2_clk_enable)
vl_sms_proc_sms_ipu_s ipu1_hsp_clk_root CCGR3[CG0]
ram_266_clk_sms (ipu1_clk_enable)
CCGR3[CG3]
(ipu2_clk_enable)
sec_mst_hclk ipu1_hsp_clk_root CCGR3[CG0]
(ipu1_clk_enable)
CCGR3[CG3]
(ipu2_clk_enable)
KPP ipg_clk_32k ckil_sync_clk_root
LDB ch_0_serial_clk ldb_di0_serial_clk_root CCGR3[CG6]
(ldb_di0_clk_enable)
ch_1_serial_clk ldb_di1_serial_clk_root CCGR3[CG7]
di_0_clk_nc ldb_di0_serial_clk_root CCGR3[CG6]
di_1_clk_nc ldb_di1_serial_clk_root CCGR3[CG7]
MIPI ac_clk_125m ahb_clk_root CCGR3[CG8]
(mipi_core_cfg_clk_enable)
mipi_pixel_clk aclk_clk_root
cfg_clk video_27m_clk_root CCGR3[CG8]
ips_clk ipg_clk_root CCGR3[CG8]
ips_clk_s ipg_clk_root
pll_refclk video_27m_clk_root CCGR3[CG8]
vl_sms_proc_sms_mipi_ ipg_clk_root
rf_125_clk_sms

System Clocks

Enable1
MIPI_HSI h_clk ahb_clk_root CCGR3[CG8]
tx_ref_clk hsi_tx_clk_root CCGR3[CG8]
sec_mst_hclk ahb_clk_root CCGR3[CG8]
MLB hclk ahb_clk_root CCGR3[CG9]
(mlb_clk_enable)
ipg_clk_s ipg_clk_root CCGR3[CG9]
(mlb_clk_enable)
sys_clk axi_clk_root CCGR3[CG9]
(mlb_clk_enable)
mem_ct_CLK axi_clk_root CCGR3[CG9]
(mlb_clk_enable)
mem_db_CLK axi_clk_root CCGR3[CG9]
(mlb_clk_enable)
MMDC aclk_fast_core_p0 mmdc_ch0_clk_root
aclk_fast_core_p1 GND
ipg_clk_p0 ipg_clk_root CCGR3[CG12]
(mmdc_core_ipg_clk_p0_ena
ble
ipg_clk_p1 ipg_clk_root
aclk_fast_phy_p0 mmdc_ch0_clk_root CCGR3[CG10]
(mmdc_core_aclk_fast_core_
p0_enable)
aclk_fast_phy_p1 GND
OCOTP ipg_clk ipg_clk_root CCGR2[CG6]
(iim_clk_enable)
OCRAM clk ahb_clk_root CCGR3[CG14]
(ocram_clk_enable)
aclk_exsc ahb_clk_root CCGR3[CG14]
(ocram_clk_enable)
(ocram_clk_enable)
PCIE rst_aux_clk ipg_clk_root CCGR4[CG0]
(pcie_root_enable)
rst_dbi_axi_clk pcie_axi_clk_root CCGR4[CG0]
(pcie_root_enable)
rst_mstr_axi_clk pcie_axi_clk_root CCGR4[CG0]
(pcie_root_enable)
rst_slv_axi_clk pcie_axi_clk_root CCGR4[CG0]
(pcie_root_enable)
mstr_aclk pcie_axi_clk_root CCGR4[CG0]
(pcie_root_enable)


Enable1
slv_aclk pcie_axi_clk_root CCGR4[CG0]
(pcie_root_enable)
aclk_exsc pcie_axi_clk_root CCGR4[CG0]
(pcie_root_enable)
ram_mstr_axi_clk pcie_axi_clk_root CCGR4[CG0]
(pcie_root_enable)
ram_slv_axi_clk pcie_axi_clk_root CCGR4[CG0]
(pcie_root_enable)
PWMn ipg_clk ipg_clk_root CCGR4[CG8]
(pwm1_clk_enable)
CCGR4[CG9]
(pwm2_clk_enable)
CCGR4[CG10]
(pwm3_clk_enable)
CCGR4[CG11]
(pwm4_clk_enable)
(pwm1_clk_enable)
CCGR4[CG9]
(pwm2_clk_enable)
CCGR4[CG10]
(pwm3_clk_enable)
CCGR4[CG11]
(pwm4_clk_enable)
ROMCP hclk ahb_clk_root CCGR5[CG0]
(rom_clk_enable)
hclk_reg ipg_clk_root CCGR5[CG0]
(rom_clk_enable)
(rom_clk_enable)
SATA hclk ahb_clk_root CCGR5[CG2]
(sata_clk_enable)
clk_app ahb_clk_root CCGR5[CG2]
(sata_clk_enable)
hclk_sata_mem ahb_clk_root CCGR5[CG2]
(sata_clk_enable)
(sata_clk_enable)
SDMA clk_sms ipg_clk_root
ips_hostctrl_clk ipg_clk_root CCGR5[CG3]
(sdma_clk_enable)

System Clocks

Enable1
sdma_ap_ahb_clk ahb_clk_root CCGR5[CG3]
(sdma_clk_enable)
sdma_core_clk ipg_clk_root CCGR5[CG3]
(sdma_clk_enable)
tck ioring_ipp_ind_jtag_tck
clk ahb_clk_root CCGR5[CG3]
(sdma_clk_enable)
SNVS hp_ipg_clk ipg_clk_root
hp_ipg_clk_s ipg_clk_root
ipg_hp_rtc_clk ckil_sync_clk_root
lp_ipg_clk ipg_clk_root
lp_ipg_clk_s ipg_clk_root
SPBA ipg_clk ipg_clk_root CCGR5[CG6]
(spba_clk_enable)
ipg_clk_s ipg_clk_root CCGR5[CG6]
(spba_clk_enable)
SPDIF gclkw_t0 ipg_clk_root CCGR5[CG7]
(spdif_clk_enable)
tx_clk spdif0_clk_root CCGR5[CG7]
(spdif_clk_enable)
SRC ipg_clk ipg_clk_root
SSIn ccm_ssi_clk ssi1_clk_root CCGR5[CG9]
(ssi1_clk_enable)
CCGR5[CG10]
(ssi2_clk_enable)
CCGR5[CG11]
(ssi3_clk_enable)
(ssi1_clk_enable)
CCGR5[CG10]
(ssi2_clk_enable)
CCGR5[CG11]
(ssi3_clk_enable)
TZASCn aclk mmdc_ch0_clk_root CCGR2[CG11]
(ipsync_ip2apb_tzasc1_ipg_m
aster_clk_enable)
aclk mmdc_ch0_clk_root CCGR2[CG12]
(ipsync_ip2apb_tzasc2_ipg_m
aster_clk_enable)
UARTn ipg_clk ipg_clk_root CCGR5[CG12]
(uart_clk_enable)


Enable1
ipg_perclk uart_clk_root CCGR5[CG13]
(uart_serial_clk_enable)
USB ipg_ahb_clk ahb_clk_root CCGR6[CG0]
(usboh3_clk_enable)
ipg_clk_32khz ckil_sync_clk_root
ipg_clk_s_pl301 ipg_clk_root CCGR6[CG0]
(usboh3_clk_enable)
test_clk_240m ipg_clk_root CCGR6[CG0]
(usboh3_clk_enable)
(usboh3_clk_enable)
(usboh3_clk_enable)
USDHCn hclk ahb_clk_root CCGR6[CG0] CMEOR[mod_en_ov_usd
(usdhc1_clk_enable) hc]
CCGR6[CG1]
(usdhc2_clk_enable)
CCGR6[CG2]
(usdhc3_clk_enable)
CCGR6[CG3]
(usdhc4_clk_enable)
ipg_clk ipg_clk_root CCGR6[CG0] CMEOR[mod_en_ov_usd
CCGR6[CG1]
(usdhc2_clk_enable)
CCGR6[CG2]
(usdhc3_clk_enable)
CCGR6[CG3]
(usdhc4_clk_enable)
ipg_clk_perclk usdhc1_clk_root CCGR6[CG0] CMEOR[mod_en_ov_usd
CCGR6[CG1]
(usdhc2_clk_enable)
CCGR6[CG2]
(usdhc3_clk_enable)
CCGR6[CG3]
(usdhc4_clk_enable)
VDOA ipg_clk_s vdo_axi_clk_root CCGR6[CG6]
(vdoaxi_clk_enable)
vdoa_clk vdo_axi_clk_root CCGR6[CG6] CMEOR[mod_en_ov_vdo
(vdoaxi_clk_enable) a]

System Clocks

Enable1
vdoa_clk vdo_axi_clk_root CCGR6[CG6] CMEOR[mod_en_ov_vdo
(vdoaxi_clk_enable) a]
VPU aclk vpu_axi_clk_root CCGR6[CG7] CMEOR[mod_en_ov_vpu]
(vpu_clk_enable)
cclk vpu_axi_clk_root CCGR6[CG7] CMEOR[mod_en_ov_vpu]
(vpu_clk_enable)
rclk video_27m_clk_root CMEOR[mod_en_ov_vpu]
WDOGn ipg_clk_32k ckil_sync_clk_root
1. System or module clocks that cannot be clock gated by software control are shaded gray in the Module Clock Gating
Enable column.
Table 18-4. System Clock Frequency Values

Clock Root Default Frequency (MHz) Maximum Frequency (MHz)
ARM_CLK_ROOT 792
MMDC_CH0_CLK_ROOT 528 528
MMDC_CH1_CLK_ROOT 528 528
AHB_CLK_ROOT 132 133
IPG_CLK_ROOT 66 66.5
PERCLK_CLK_ROOT 66 80
USDHCn_CLK_ROOT 198 208
SSIn_CLK_ROOT 63.5 66.5
GPU2D_AXI_CLK_ROOT 270 540
GPU3D_AXI_CLK_ROOT 270 540
PCIE_AXI_CLK_ROOT 270 540
VDO_AXI_CLK_ROOT 270 540
AXI_CLK_ROOT 264 528
IPU1_HSP_CLK_ROOT 264 264
IPU2_HSP_CLK_ROOT 264 264
GPU2D_CORE_CLK_ROOT 352 532
ACLK_EIM_SLOW_CLK_ROOT 132 540
ACLK_CLK_ROOT 198 540
ENFC_CLK_ROOT 198 200
GPU3D_CORE_CLK_ROOT 270 540
GPU3D_SHADER_CLK_ROOT 270 660
VPU_AXI_CLK_ROOT 352 540
IPU1_DI0_CLK_ROOT 180 266

Table 18-4. System Clock Frequency Values (continued)

Clock Root Default Frequency (MHz) Maximum Frequency (MHz)
LDB_DI0_SERIAL_CLK_ROOT 540 595
LDB_DI0_IPU 77.1 170
LDB_DI1_SERIAL_CLK_ROOT 540 595
LDB_DI1_IPU 77.1 170
SPDIF0_CLK_ROOT 31.8 66.5
SPDIF1_CLK_ROOT 31.8 66.5
ESAI_CLK_ROOT 31.8 66.5
HSI_TX_CLK_ROOT 198 198
CAN_CLK_ROOT 30 66.5
ECSPI_CLK_ROOT 60 66.5
UART_CLK_ROOT 80 80
VIDEO_27M_CLK_ROOT 27 27

18.5.1 Clock Generation
18.5.1.1 External Low Frequency Clock - CKIL

The chip can use a 32 kHz or 32.768 kHz crystal as the external low-frequency source
(XTALOSC). Throughout this chapter, the low-frequency crystal is referred to as the 32
kHz crystal.
This clock source should always be active when the chip is powered on. The 32 kHz
entering the CCM are referred to as CKIL. CKIL is synchronized to IPG_CLK and
supplied to modules that need it.
18.5.1.1.1 CKIL synchronizing to IPG_CLK

CKIL is synchronized to ipg_clk when the system is in functional mode. When the
system is in STOP mode (when there is no IPG_CLK) the CKIL synchronizer is
bypassed, and raw CKIL is supplied to the system.
18.5.1.2 External High Frequency Clock - CKIH and internal oscillator

The chip uses an internal oscillator to generate the reference clock (OSC). The internal
oscillator is connected to the external crystal (XTALOSC) which generates the 24 MHz
reference clock.
18.5.1.3 PLL reference clock

There are several PLLs in this chip.
PLL1 - ARM PLL (typical functional frequency 1 GHz)
PLL2 - System PLL (functional frequency 528 MHz)
PLL3 - USB1 PLL (functional frequency 480 MHz)
PLL4 - Audio PLL
PLL5 - Video PLL
PLL6 - ENET PLL
PLL7 - USB2 PLL (functional frequency 480 MHz)
PLL8 - MLB PLL
Some of the PLLs are described in the sections below. See CCM Analog Memory Map/
Register Definition for register information.
18.5.1.3.1 ARM PLL (PLL1)

This PLL synthesizes a low jitter clock from a 24 MHz reference clock. The clock output
frequency for this PLL ranges from 650 MHz to 1.3 GHz. The output frequency is
selected by a 7-bit register field CCM_ANALOG_PLL_ARM[DIV_SELECT].
PLL output frequency = Fref * DIV_SEL/2
NOTE
The upper frequency range may exceed the maximum
frequency supported. Please see the datasheet for more
information.

18.5.1.3.2 System PLL (PLL2)

This PLL synthesizes a low jitter clock from the 24 MHz reference clock. The PLL has
one output clock, plus 3 PFD outputs. The System PLL supports spread spectrum
modulation for use in applications to minimize radiated emissions. The spread spectrum
PLL output clock is frequency modulated so that the energy is spread over a wider
bandwidth, thereby reducing peak radiated emissions. Due to this feature support, the
associated lock time of this PLL is longer than other PLLs in the SoC that do not support
spread spectrum modulation.
Spread spectrum operation is controlled by configuring the
CCM_ANALOG_PLL_SYS_SS register. When enabled, the PLL output frequency will
decrease by the amount defined in the STEP field, until it reaches the limiting frequency
in the STOP field. The frequency will then similarly return to the original nominal
frequency. The following equations control the spread-spectrum operation:
CCM_ANALOG_PLL_SYS_SS[STOP]
Spread spectrum range = Fref x
CCM_ANALOG_PLL_SYS_DENOM[B]
CCM_ANALOG_PLL_SYS_SS[STEP]
Modulation frequency = Fref x
2 x CCM_ANALOG_PLL_SYS_SS[STOP]
Although this PLL does have a DIV_SELECT register field, it is intended that this PLL
will only be run at the default frequency of 528 MHz.
This PLL also supports a Fractional-N synthesizer.
18.5.1.3.3 USB1 PLL (PLL3)

These PLLs synthesize a low jitter clock from the 24 MHz reference clock. USB1 PLL
has 4 frequency-programmable PFD (phase fractional divider) outputs.
The output frequency of USB1 PLL is 480 MHz. Even though USB1 PLL has a
DIV_SELECT register field, this PLL should always be set to 480 MHz in normal
operation.
18.5.1.3.4 Audio PLL (PLL4)

The audio PLL synthesize a low jitter clock from a 24 MHz reference clock. The clock
output frequency range for this PLL is from 650 MHz to 1.3 GHz. It has a Fractional-N
synthesizer.

There are /1, /2, /4 post dividers for the Audio PLL. The output frequency can be set by
programming the fields in the CCM_ANALOG_PLL_AUDIO, and
CCM_ANALOG_MISC2 register sets according to the following equation.
PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
18.5.1.3.5 Video PLL (PLL5)

The video PLL synthesize a low jitter clock from a 24 MHz reference clock. The clock
output frequency range for this PLL is from 650 MHz to 1.3 GHz. It has a Fractional-N
synthesizer.
There are /1, /2, /4, /8, /16 post dividers for the Video PLL. The output frequency can be
set by programming the fields in the CCM_ANALOG_PLL_VIDEO, and
CCM_ANALOG_MISC2 register sets according to the following equation.
PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
18.5.1.3.6 MLB PLL

The MediaLB PLL is necessary in the MediaLB 6-Pin implementation to phase align the
internal and external clock edges, effectively tuning out the delay of the differential clock
receiver. The PLL is also responsible for generating the higher speed internal clock when
the internal-to-external clock ratio is not 1:1.
18.5.1.3.7 Ethernet PLL (PLL6)

This PLL synthesizes a low jitter clock from the 24 MHz reference clock.
The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
• Ref_PCIe =125 MHz
• Ref_SATA=100 MHz
• Ref_ethernet, which is configurable based on the PLL_ENET[DIV_SELECT]
register field.
18.5.1.3.8 USB2 PLL (PLL7)

USB2 PLL is only used by the USB UTM interface through a direct connection.
18.5.1.4 Phase Fractional Dividers (PFD)

There are several PFD outputs from the System PLL and USB1 PLL.

Each PFD output generates a fractional multiplication of the associated PLL’s VCO
frequency. Where the output frequency is equal to Fvco*18/N, N can range from 12-35.
The PFDs allow for clock frequency changes without forcing the relock of the root PLL.
This feature is useful in support of dynamic voltage and frequency scaling (DVFS). See
CCM Analog Memory Map/Register Definition.
When the related PLL is powered up from the power down state or made to go through a
relock cycle due to PLL regrogramming, it is required that the related PFDx_CLKGATE
bit in CCM_ANALOG_PFD_480n or CCM_ANALOG_PFD_528n, be cycled on and off
(1 to 0) after PLL lock. The PFDs can be in the clock gated state during PLL relock but
must be un-clock gated only after lock is achieved. See the engineering bulletin,
Configuration of Phase Fractional Dividers (EB790) at www.nxp.com for procedure
details.
18.5.1.5 CCM internal clock generation

The clock generation is comprised of two sub-modules:
CCM_CLK_SWITCHER
CCM_CLK_ROOT_GEN
18.5.1.5.1 Clock Switcher

The Clock Switcher (CCM_CLK_SWITCHER) sub-module receives the PLL output
clocks and the PLL bypass clocks.
Figure 18-4 describes the generation of the three switcher clocks.
The figure also includes the Frequency Switch Control sub-module responsible for
frequency change.

CCSR: pll1_sw_clk_sel
24MHz
OSC
PLL1 pll1_main_clk 0 pll1_sw_clk

(800M)
CCSR: step_sel
1
osc_clk
0
GLITCHLESS MUX
PFD
step_clk
PFD2: 396M 1
PFD0: 352M
PFD1: 594M
PLL 2
(528M) pll2_main_clk
PFD2: 508.2M
PFD3: 454.7M
PFD0: 720M CCM

switcher
PFD1: 540M GLITCHLESS MUX
PLL3 0
pll3_sw_clk
pll3_main_clk
(480M)
CCM_PLL3_BYP
(PLL3 Bypass clock)
PLL3 Bypass (from jtag)
CCSR: pll3_sw_clk_sel
2 bit divider pll4_main_clk

PLL 4
default=1
PLL_AUDIOn: POST_DIV_SELECT
2 bit divider 2 bit divider pll5_main_clk

PLL 5
default=1 default=1
PLL_VIDEOn: POST_DIV_SELECT CCM_ANALOG_MISC2n: VIDEO_DIV
Figure 18-4. Switcher clock generation
18.5.1.5.2 PLL bypass procedure

In addition to PLL bypass options in CCM_ANALOG module, switcher and
clk_root_gen sub-modules includes capability for each of the PLL clocks to be bypassed
with an external bypass clock.

18.5.1.5.3 PLL clock change

In order to modify or stop the clock output of a specific PLL, all the clocks generated
from the current PLL must be transitioned to the new PLL whose frequency is not being
modified.
For clocks which can't be stopped (core and bus clocks), this should be done via the
glitchless mux. Before changing the PLL setting, power it down. Power up the PLL after
the change. See Disabling / Enabling PLLs for more information.
18.5.1.5.4 Clock Root Generator

The Clock Root Generator (CCM_CLK_ROOT_GEN) sub-module generates the root
clocks to be delivered to LPCG.
The following figures describe clock generation. The frequencies in parantheses are the
default typical frequencies.

PLL2 0
PFD2
PLL3 CBCDR: axi_sel

1
PFD1
CBCDR: axi_alt_sel
AXI_CLK_ROOT
1
CBCMR:
3 bit divider
periph_clk2_sel
default=2
0 NOTE: See System Clocks,

pll3_sw_clk Gating and Override table for
0 GLITCHLESS MUX
AXI_CLK_ROOT module
OSC_CLK CBCDR: axi_podf
1 gating
(24M)
CCGR3[CG10] MMDC_CH0_CLK_ROOT
burn_in_bist 2
periph_clk
3 bit divider
OSC_CLK cg
default=1
(24M) 1
pll2_bypass_clk 0 3 bit divider
default=1
CBCDR: periph_clk2_podf GLITCHLESS MUX CBCDR: mmdc_ch0_axi_podf
1
PLL2 0
PLL2 132M_CLK_ROOT
1 0 3 bit divider
PFD2 AHB_CLK_ROOT
default=4
PLL2 2
PFD0 NOTE: See System Clocks,
PLL2 3 Gating and Override table for
PFD2 /2 AHB_CLK_ROOT module
CBCDR: ahb_podf gating
CBCMR:
pre_periph_clk_sel CBCDR: IPG_CLK_ROOT
periph_clk_sel 3 bit divider
default=2
PLL_bypass_en2 (from jtag)
NOTE: See System Clocks,
Gating and Override table for
CBCMR: CBCDR: ipg_podf IPG_CLK_ROOT module
periph2_clk2_sel gating
pll3_sw_clk 0 CBCDR: periph2_clk2_podf
PLL2 1 CBCDR: mmdc_ch1_axi_podf

3 bit divider GLITCHLESS MUX
default=1
1
3 bit divider
PLL2 0 default=1
PLL2 0 MMDC_CH1_CLK_ROOT
PFD2
1
PLL2 Note: This design implementation does
2
PFD0 not use MMDC_CH1_CLK_ROOT
PLL2 as a clock source to the MMDC. Only
/2 3
PFD2 MMDC_CH0_CLK_ROOT is used.
Note: No clock gates (cg)

before glitchless muxes.
CBCMR:
pre_periph2_clk_sel CBCDR:
periph2_clk_sel PLL_bypass_en2 (from jtag)
Figure 18-5. BUS clock generation

CCGR1[CG12]
AXI_CLK_ROOT 0 (gpu2d_clk_enable)
cg GPU2D_AXI_CLK_ROOT
AHB_CLK_ROOT 1 NOTE: See System Clocks, Gating and

Override table for GPU2D_AXI_CLK_ROOT
module gating
CBCMR: gpu2d_axi_clk_sel
CCGR1[CG13]
AXI_CLK_ROOT 0 (gpu3d_clk_enable)
cg GPU3D_AXI_CLK_ROOT

Override table for GPU3D_AXI_CLK_ROOT
module gating
CBCMR: gpu3d_axi_clk_sel
CCGR4[CG0]
AXI_CLK_ROOT 0 (pcie_root_enable)
cg PCIE_AXI_CLK_ROOT

Override table for PCIE_AXI_CLK_ROOT
module gating
CBCMR: pcie_axi_clk_sel
MMDC_CH0_AXI_CLK_ROOT
0
PLL2 CCGR3[CG0]
PFD2
1 3 bit divider
cg IPU1_HSP_CLK_ROOT
default=2
PLL3 (120M) 2
PLL3
PFD1 3
CSDR3: ipu1_hsp_clk_sel CSDR3: ipu1_hsp_podf
0
PLL2 CCGR3[CG3]
1
PFD2 IPU2_HSP_CLK_ROOT
cg 3 bit divider
PLL3 (120M) 2 default=2
PLL3
PFD1 3
CSDR3: ipu2_hsp_clk_sel CSDR3: ipu2_hsp_podf
AXI_CLK_ROOT 0
VDO_AXI_CLK_ROOT
AHB_CLK_ROOT 1
CBCMR: vdo_axi_clk_sel

CCGR3[CG0] | [CG3] | [CG8] | CCGR0[CG13:12]

PLL3_120M (120Mhz)
pll3_sw_clk cg 3 bit divider (to HSI_TX_CLK_ROOT and
(480M) podf=4 IPUn_HSP_CLK_ROOTs)
Note: See System Clocks,

Gating, and Override table
for PLL3_120M module
gating.
CCGR5[CG13]
3 bit divider
cg PLL3_80M (80Mhz)
podf=6
(to UART_CLK_ROOT)
CCGR1[CG3:0] | CCGR0[CG8] | [CG10]
3 bit divider PLL3_60M (60Mhz)

cg (to ECSPI_CLK_ROOT
podf=8
and CAN_CLK_ROOT)

Gating, and Override table
for PLL3_60M module
gating.
PLL2
divider
PFD2 PLL2 198M (198Mhz)
/2
3 bit divider divider

PLL1 ARM_CLK_ROOT
default=1 /2
Note: Clock source goes to
ARM Domain after post-divider
and returns to CCM after
static divider
CACRR: ARM_podf
Figure 18-6. AXI clocks generation

CBCMR: gpu2d_core_podf
AXI_CLK_ROOT
0
CCGR1[CG12]
pll3_sw_clk 1 3 bit divider
cg
default=1
PLL2 2
PFD0
GPU2D_CORE_CLK_ROOT
PLL2 3
PFD2
CBCMR: gpu2d_clk_sel
MMDC_CH0_AXI_CLK_ROOT CBCMR: gpu3d_core_podf

0
CCGR1[CG13]
cg
default=1
PLL2 2
PFD1
GPU3D_CORE_CLK_ROOT
PLL2 3
PFD2
CBCMR: gpu3d_clk_sel
MMDC_CH0_AXI_CLK_ROOT CBCMR: gpu3d_shader_podf

0
CCGR1[CG13]
cg
default=1
PLL2
2
PFD1
GPU3D_SHADER_CLK_ROOT
PLL3 3
PFD0
CBCMR: gpu3d_shader_clk_sel
CBCDR1: vpu_axi_podf
AXI_CLK_ROOT
0 CCGR6[CG7]
PLL2 3 bit divider
1 cg VPU_AXI_CLK_ROOT
PFD2 default=1
PLL2
2
PFD0
CBCMR: vpu_axi_clk_sel

CSCDR1: usdhc1_podf
PLL2
0 CCGR6[CG0]
PFD2
3 bit divider
cg
PLL2 default=2 USDHC1_CLK_ROOT
PFD0 1
CSCMR1: usdhc1_clk_sel
CSCDR1: usdhc2_podf
PLL2
0 CCGR6[CG1]
PFD2
3 bit divider
cg
PFD0 1
CSCDR1: usdhc3_podf
PLL2 CCGR6[CG2]
0
PFD2 3 bit divider
cg
PFD0
1
CSCDR1: usdhc4_podf
PLL2 CCGR6[CG3]
PFD2 0
3 bit divider
cg
PFD0 1
Figure 18-7. Serial clock generation

CS1CDR: ssi1_clk_pred CS1CDR: ssi1_clk_podf
PLL3
PFD2
0 CCGR5[CG9]
PLL3 3 bit divider 6 bit divider
PFD3 1 cg SSI1_CLK_ROOT
default=4 default=2
PLL4 2
CSCMR1: ssi1_clk_sel
PLL3
PFD2 0 CCGR5[CG10]
1 cg SSI2_CLK_ROOT
PFD3 default=4 default=2
PLL4 2
PLL3
PFD2 0 CCGR5[CG11]
1 cg SSI3_CLK_ROOT
PFD3 default=4 default=2
PLL4 2
6 bit divider
IPG_CLK PERCLK_CLK_ROOT
default=1

Gating and Override Table
for PERCLK_CLK_ROOT
module gating
CSCMR1: perclk_podf
IPG_CLK
CKIL Sync CKIL_SYNC_CLK_ROOT (32Khz)

(32K)

CHSCCDR: ipu1_di0_pre_clk_sel
0
pll3_sw_clk 1
PLL5 2
PLL2 3
PFD0
PLL2 4
PFD2
PLL3 5
PFD1
CHSCCDR: ipu1_di0_podf
CHSCCDR: ipu1_di0_clk_sel
CCGR3[CG1]
3 bit divider
cg default=3 0
ipp_di0_clk 1
CCGR3[CG1]
ipp_di1_clk 2 cg IPU1_DI0_CLK_ROOT
ldb_di0_ipu 3
ldb_di1_ipu 4
CHSCCDR: ipu1_di1_pre_clk_sel
0
pll3_sw_clk 1
PLL5 2
PLL2 3
PFD0
PLL2 4
PFD2
PLL3 5
PFD1
CHSCCDR: ipu1_di1_podf
CHSCCDR: ipu1_di1_clk_sel
CCGR3[CG2]
3 bit divider
cg default=3 0
ipp_di0_clk 1
CCGR3[CG2]
ldb_di0_ipu 3
ldb_di1_ipu 4

CSCDR2: ipu2_di0_pre_clk_sel
0
pll3_sw_clk 1
PLL5 2
PLL2
3
PFD0
PLL2
4
PFD2 CSCDR2: ipu2_di0_podf
PLL3 5
PFD1
CSCDR2: ipu2_di0_clk_sel
CCGR3[CG4]
3 bit divider
cg default=3 0
ipp_di0_clk 1
CCGR3[CG4]
ldb_di0_ipu 3
ldb_di1_ipu 4
CSCDR2: ipu2_di1_pre_clk_sel
0
pll3_sw_clk 1
PLL5 2
PLL2
3
PFD0
PLL2 CSCDR2: ipu2_di1_podf
4
PFD2
PLL3 5
PFD1 CSCDR2: ipu2_di1_clk_sel
CCGR3[CG5]
3 bit divider
cg default=3 0
ipp_di0_clk 1
CCGR3[CG5]
ldb_di0_ipu 3
ldb_di1_ipu 4
CSCMR2: can_clk_podf
CCGR0[CG8] | [CG10]
6 bit divider
PLL3 60M cg CAN_CLK_ROOT
default=2

CS2CDR: ldb_di0_clk_sel
PLL5
0 CCGR3[CG6]
PLL2 LDB_DI0_SERIAL_CLK_ROOT
1 cg
PFD0
PLL2 2
PFD2 CSCMR2: ldb_di0_ipu_div
MMDC_CH1_AXI_CLK_ROOT 3
div 3.5 / 7 ldb_di0_ipu

pll3_sw_clk 4
NOTE: This clock path is not controlled
by a clock gate (CG). For proper clock
switching procedures refer to the Clock
Switching Multiplexers section.
CSCMR2: ldb_di1_clk_sel
PLL5
0 CCGR3[CG7]
PLL2 LDB_DI1_SERIAL_CLK_ROOT
1 cg
PFD0
PLL2 2
PFD2 CSCMR2: ldb_di1_ipu_div
MMDC_CH1_AXI_CLK_ROOT 3
div 3.5 / 7 ldb_di1_ipu

pll3_sw_clk 4
NOTE: This clock path is not controlled
by a clock gate (CG). For proper clock
switching procedures refer to the Clock
Switching Multiplexers section.
Figure 18-8. Serial clock generation

CDCDR: spdif0_clk_pred
PLL 4 0 CDCDR: spdif0_clk_podf
PLL3
PFD2 1 CCGR5[CG7]
PLL3 cg 3 bit divider 3 bit divider SPDIF0_CLK_ROOT

default=2 default=8
PFD3 2
pll3_sw_clk 3
CDCDR: spdif0_clk_sel
CDCDR: spdif1_clk_pred
PLL 4 0 CDCDR: spdif1_clk_podf
PLL3
PFD2 1
3 bit divider 3 bit divider SPDIF1_CLK_ROOT
PLL3 default=2 default=8
2
PFD3
Note: SPDIF1_CLK_ROOT
pll3_sw_clk 3 is used by ASRC.
CDCDR: spdif1_clk_sel
CS1CDR: esai_clk_pred
PLL 4 0 CS1CDR: esai_clk_podf

PLL3
1 CCGR1[CG8]
PFD2
PLL3 cg 3 bit divider 3 bit divider ESAI_CLK_ROOT
default=2 default=8
PFD3 2
pll3_sw_clk 3
CSCMR2: esai_clk_sel

CSCDR2: ecspi_clk_podf
PLL3_60M cg 6 bit divider ECSPI_CLK_ROOT

default=1
Gating and Override table
for ECSPI_CLK_ROOT
gating
AXI_CLK_ROOT 0 CSCMR1: aclk_eim_slow_podf
pll3_sw_clk 1 CCGR6[CG5]
cg 3 bit divider ACLK_EIM_SLOW_CLK_ROOT

PLL2 default=2
PFD2 2
PLL2
PFD0 3
CSCMR1: aclk_eim_slow_sel
PLL2
0 CSCMR1: aclk_podf
PFD2
pll3_sw_clk 1
3 bit divider ACLK_CLK_ROOT
default=8 (MIPI_CLK_ROOT)
AXI_CLK_ROOT 2
PLL2
PFD0 3
CSCMR1: aclk_sel
PLL2
0 CS2CDR: enfc_clk_pred CS2CDR: enfc_clk_podf
PFD0
PLL2 1
3 bit divider 6 bit divider ENFC_CLK_ROOT
pll3_sw_clk default=2 default=1
2 Note: See System Clocks,
Gating and Override table
PLL2 for ENFC_CLK_ROOT
PFD2 3
module gating
Note: ENFC_CLK_ROOT
is controlled by CG bits in
CS2CDR: enfc_clk_sel the IOMUXC and GPMI
Modules

CDCDR1: uart_clk_podf
6 bit divider
UART_CLK_ROOT
PLL3_80M
default=1
Note: See System, Clocks,
and Override table for
UART_CLK_ROOT
module gating
CDCDR: hsi_tx_podf
PLL3_120M 0 CCGR3[CG8]
cg 3 bit divider HSI_TX_CLK_ROOT

PLL2 default=2
1
PFD2
CDCDR: hsi_tx_clk_sel
PLL3 2 bit divider 3 bit divider VIDEO_27M_CLK_ROOT

PFD1 ratio=4 ratio=5
Note: See System, Clocks,
and Override table for
VIDEO_27M_CLK_ROOT
module gating
Figure 18-9. UART, HSI, Video clock generation
NOTE
All 6-bit PODF dividers found in the diagrams above can
operate on low frequency.
18.5.1.5.5 Initial values controlled by the System JTAG Controller (SJC)

The initial values of the following dividers and muxes can be controlled by SJC.
In regular functional mode, the SJC will drive the reset values stated in the CCM register
memory map. If SJC is programmed to change those values, then the reset value for those
dividers/muxes will be taken from the SJC programability.
Software can update the changed reset value after reset sequence. The control signals and
the dividers/muxes are listed below:
• [2:0] init_mmdc_ch1_axi_podf
• [2:0] init_periph2_clk2_podf
• [1:0] init_ipg_podf
• [2:0] init_ahb_podf

• [2:0] init_axi_podf
• [2:0] init_mmdc_ch0_axi_podf
• [2:0] init_periph_clk2_podf
• init_periph_clk_sel
• init_periph2_clk_sel
18.5.1.5.6 Divider change handshake

Modifying the following dividers will start the handshake with MMDC CH1 and/or CH0.
• mmdc_ch0_axi_podf
• mmdc_ch1_axi_podf
• periph_clk_sel
• periph2_clk_sel
• arm_podf
• axi_podf
• ahb_podf
The dividers listed above are designed with a handshake. For dividers without a
handshake design, the following sequence must be performed when updating PODF
value:
1. Gate the output clock off before updating PODF value.
2. Gate the output clock on after the PODF value is updated and stable.
To update the PODF value without gating the output clock off will cause unpredictable
results such as no clock output.
18.5.1.6 Disabling / Enabling PLLs

PLL disabling and enabling is done via analog module.
Before disabling a PLL using the analog registers, software should first move all the
clocks generated from that specific PLL to another source. This alternate source could be
another PLL, or a PFD driven by another PLL. Alternatively, software can bypass the
PLL and use the PLL reference clock (usually 24 MHz) as the output clock. Bypassing
the PLL is done by setting the analog BYPASS bit in the control register for that PLL.
18.5.1.7 Clock Switching Multiplexers

There are a multitude of multiplexers available throughout the clock generation logic that
provide alternate clock sources for the system clocks controlled by the CCM. The CCM
uses several synchronous glitchless clock multiplexers as well as asynchronous glitchy
clock multiplexers.
Synchronous muxes ensure there are no glitches between the transition of two
asynchronous clocks and that there will be no pulses that are of a frequency higher than
either input clock. For the synchronous multiplexer to work properly, both the current
clock and the clock to be selected must remain active during the entire selection process.
There are several glitchless (synchronous) muxes used in the CCM. The table below lists
the muxes and the respective control bits.
Table 18-5. Glitchless Multiplexers
Glitchless Mux Mux Select Bit Handshake Bit
periph_clk_mux CBCDR[periph_clk_sel] CDHIPR[periph_clk_sel_busy]
periph2_clk_mux CBCDR[periph2_clk_sel] CDHIPR[periph2_clk_sel_busy]
axi_alt_clk_mux CBCDR[ axi_sel]
pll3_sw_clk_mux CCSR[pll3_sw_clk_sel]
pll1_sw_clk_mux CCSR[pll1_sw_clk_sel]
NOTE
Any change of the periph_clk_sel and periph2_clk_sel sync
mux select will involve handshake with the MMDC. Refer to
the CCDR and CDHIPR registers for the handshake bypass and
busy bits.
Table 18-6. Multiplexers
Signal Mux Select Bit Glitchless
pll1_sw_clk CCSR[pll1_sw_clk_sel] Yes
step_clk CCSR[step_sel] No
pll3_sw_clk CCSR[pll3_sw_clk_sel] Yes
axi_alt CBCDR[axi_alt_sel] No
AXI_CLK_ROOT CBCDR[axi_sel] Yes
periph_clk2 CBCMR[periph_clk2_sel] No
periph_clk CBCDR[periph_clk_sel] Yes
pre_periph_clk CBCMR[pre_periph_clk_sel] No
periph2_clk2 CBCMR[periph2_clk2_sel] No
pre_periph2_clk CBCMR[pre_periph2_clk_sel] No
periph2_clk CBCDR[periph2_clk_sel] Yes
GPU2D_AXI_CLK_ROOT CBCMR[gpu2d_axi_clk_sel] No
GPU3D_AXI_CLK_ROOT CBCMR[gpu3d_axi_clk_sel] No

Table 18-6. Multiplexers (continued)

Signal Mux Select Bit Glitchless
PCIE_AXI_CLK_ROOT CBCMR[pcie_axi_clk_sel] No
IPU1_HSP_CLK_ROOT CSCDR3[ipu1_hsp_clk_sel] No
IPU2_HSP_CLK_ROOT CSCDR3[ipu2_hsp_clk_sel] No
VDO_AXI_CLK_ROOT CBCMR[vdo_axi_clk_sel] No
GPU2D_CORE_CLK_ROOT CBCMR[gpu2d_core_clk_sel] No
GPU3D_CORE_CLK_ROOT CBCMR[gpu3d_core_clk_sel] No
GPU3D_SHADER_CLK_ROOT CBCMR[gpu3d_shader_clk_sel] No
VPU_AXI_CLK_ROOT CBCMR[vpu_axi_clk_sel] No
USDHC1_CLK_ROOT CSCMR1[usdhc1_clk_sel] No
SSI1_CLK_ROOT CSCMR1[ssi1_clk_sel] No
IPU1_DI0_CLK_ROOT CHSCCDR[ipu1_di0_clk_sel] No
IPU1_DI1_CLK_ROOT CHSCCDR[ipu1_di1_clk_sel] No
IPU2_DI0_CLK_ROOT CSCDR2[ipu2_di0_clk_sel] No
IPU2_DI1_CLK_ROOT CSCDR2[ipu2_di1_clk_sel] No
LDB_DI0_SERIAL_CLK_ROOT CS2CDR[ldb_di0_clk_sel] No
LDB_DI1_SERIAL_CLK_ROOT CS2CDR[ldb_di1_clk_sel] No
SPDIF0_CLK_ROOT CDCDR[spdif0_clk_sel] No
SPDIF1_CLK_ROOT CDCDR[spdif1_clk_sel] No
ESAI_CLK_ROOT CSCMR2[esai_clk_sel] No
ACLK_EIM_SLOW_CLK_ROOT CSCMR1[aclk_eim_slow_sel] No
ACLK_CLK_ROOT CSCMR1[aclk_sel] No
ENFC_CLK_ROOT CS2CDR[enfc_clk_sel] No
HSI_TX_CLK_ROOT CDCDR[hsi_tx_clk_sel] No
For critical system bus clocks, changing the clock source can be done in the CCM using
the glitchless clock muxes in Figure 18-5. In the figure, the thick bar on the input side
indicates the glitchless muxes. Those without the thick bar are regular muxes (not
glitchless).
For example, before disabling PLL2, software can switch the FABRIC_CLK_ROOT
away from the PLL2 or one of its PFDs by programming
CBCMR[PERIPH2_CLK2_SEL] and CBCDR[PERIPH2_CLK2_PODF] to provide an
appropriate frequency clock, then glitchlessly switch to it by programming
CBCDR[PERIPH2_CLK_SEL].

Asynchronous multiplexers or glitchy multiplexers, allow the clock to switch

immediately after the multiplexer select changed. This immediate switch of two
asynchronous clock domains can cause the output clock to glitch. Since both clock
sources to the mux are asynchronous, switching the clocks from one source to the other
can cause a glitch to be generated, regardless of the input clock source.
The output clocks to the mux are required to be gated before switching the source clock
in the CCM clock mux. If the output clocks are not gated, clock glitches can propagate to
the logic that follows the clock mux, causing the logic to behave unpredictably.
For serial clocks, software should first disable the module, then gate its clock in the
LPCG. Then it should move the mux controlling the source of the clocks to another PLL,
and reset the module and its clocks. Only then is it safe to disable the PLL. The mux for
the serial clocks is not glitchless.
18.5.1.8 Low Power Clock Gating module (LPCG)

The LPCG module receives the root clocks and splits them to clock branches for each
module. The clock branches are gated clocks.
The enables for those gates can come from four sources:
1. Clock enable signal from CCM - this signal is generated by configuring of the CGR
bits in the CCM. It is based on the low power mode.
2. Clock enable signal from the module - this signal is generated by the module based
on internal logic of the module. Not every enable signal from the module is used. For
used clock enable signals from the module, CCM will generate an override signal
based on a programable bit in CCM (CMEOR).
3. Clock enable signal from Reset controller (SRC) - this signal will enable the clock
during the reset procedure. Please see the SRC chapter for details on the clock enable
signal during reset procedure.
4. Hard-coded enable from fuse box.
These enable signals are ANDed to generate the enable signal for the gating cell.
The enable signal for the gating cell is synchronized with the clock it needs to gate in
order to prevent glitches on the gated clock.
Notifications are generated for CCM to indicate when clock roots should be opened and
closed. All notifications that correspond to the same clock root will be ORed to generate
one notification signal to CCM for clock root gating.

The following figure describes the clock split inside the LPCG module. It describes the
case of two modules; one module is without an enable signal and one is shown with an
enable signal. SRC enable signals and sync flip flops are omitted from this figure.
CGM LPCG Module 1

enable module 1 clock
Gated clock for module 1
CGR
Module 1
clock_root
Module 2
CGR
Module 2 enable module 2 clock Gated clock for module 2
ov_clk_en clock enable from module 2

Module 2
Figure 18-10. Clock split in LPCG
18.5.1.9 MMDC handshake

CCM will assert the mmdc_freq_change_req signal.
MMDC will assert the mmdc0_freq_change_ack and mmdc1_freq_change_ack signals to
acknowledge that the frequency change request has been received and that the frequency
can now be changed safely.
CCM will commence the actual change of division ratio of mmdc0 and/or mmdc1
dividers or apply mux change on root clocks after both of the non-masked acknowledges
are asserted.

NOTE
MMDC handshakes can be masked.
18.5.2 DVFS support

When performing DVFS, the frequency shift procedure for the Arm core clock domain
can be performed by software.
CPU PLL frequency and CCM ARM clock divider is controlled by CCM and CPU power
domain supply voltage value is controlled by CCM_ANALOG module.
NOTE
The frequency should be shifted down first and then voltage
value reduced, and vice-versa, when shifting the frequency up.
NOTE
CCM_ANALOG will not control the voltage value in Bypass
mode
18.5.3 Power modes

The chip supports 3 low power modes: RUN mode, WAIT mode, STOP mode.
18.5.3.1 RUN mode

This is the normal/functional operating mode. In this mode, the CPU runs in its normal
operational mode. Clocks to the modules can be gated by configuring the corresponding
CCGRx bits.
18.5.3.2 WAIT mode

In this mode the CPU clock is gated. All other clocks are functional and can be gated by
programming their CGR bits when all Arm cores are in WFI, and L2 cache and SCU are
idle.
18.5.3.2.1 Entering WAIT mode

If the CLPCR[LPM] bit is set by software to WAIT mode, when CPU executes the next
wait for interrupt (WFI) instruction, WAIT mode sequence will start.

As part of the WFI routine, alternative interrupt controller in GPC should be updated; the
CPU platform interrupt controller will be disabled first by software and will be not
functional, due to clock gating. Interrupts during WAIT mode are monitored by
alternative interrupt controller.
After execution of the WFI routine, the CPU platform will assert idle signals for each
component of the platform and CCM will gate clock to the platform.
The next actions can be programmed during WAIT mode:
1. CCM requests an acknowledge to close clocks to MMDC if its CGR bits indicate to
close its clocks on WAIT mode, and if those clocks are not already closed in run
mode. The request will be issued if the handshake is not bypassed by programing the
CLPCR register. If the corresponding bits are set, the request signal will not be
issued to the corresponding module and CCM will not wait for its acknowledge in
the process of entering low power mode. After CCM receives all the acknowledge
signals needed, then it will enter WAIT mode.
2. Close the clocks to the modules which were defined to be shut at WAIT mode in the
CCGR bits.
3. Observability to indicate WAIT mode.
NOTE
Setting MMDC CGR bits to 01 can hang the entire system since
the MMDC clock and fabric clock share the same clock root.
Any enabled interrupt assertion will start the exit from WAIT mode.
18.5.3.2.2 Exiting WAIT mode

As soon as enabled interrupt is asserted, CPU supply will be restored if CPU SRPG was
applied and clocks are enabled to CPU and other modules.
18.5.3.3 STOP mode

In this mode all system clocks are stopped, along with the CPU, system buses and all
PLLs. Power gating can be applied for Arm platform, GPU3D, and VPU. External supply
voltage can be reduced to decrease leakage.
18.5.3.3.1 Entering STOP mode

Procedure entering STOP mode is the same, as entering WAIT mode until the moment of
disabling clocks to modules. (LPM bit should be configured to STOP mode.)

After clocks to modules are gated, the following actions will be taken:
• PLLs are disabled
• CCM_PMIC_STBY_REQ asserted, if vstby bit is set
• osc_en signal is negated
• osc_pwrdn is asserted, if sbyos bit is set
Counter will be triggered after CCM_PMIC_STBY_REQ assertion to allow to external
regulator or PMIC to decrease voltage until valid voltage range. On counter completion,
stop_mode signal will be asserted, that will trigger disabling analog elements in anatop.
CCM's low power state machine will remain in state STOP_GPC until STOP mode is
exited.
18.5.3.3.2 Exiting STOP mode

As soon as an enabled interrupt is asserted, the CCM will begin the process of exiting
STOP mode.
The following will take place:
1. If vstby bit was set, deassert PMIC_STBY_REQ to notify power management IC to
change voltage from standby voltage to functional voltage.
2. If well bias was enabled, deasserted well bias controls.
3. If sbyos was set, and CCM closed either external oscillator or on board oscillator,
then CCM will start oscillator by asserting ref_en_b signal and deasserting
cosc_pwrdown signal respectively.
4. After the number of cycles of CKILs defined in stby_count bits, wait until PMIC
functional voltage is ready. This is the notification from power management IC that
the voltage is ready at its functional value. Only then will CCM continue the steps.
5. Start osc. If oscillator was started, wait until oscnt has finished its counting to make
sure that oscillator is ready.
6. Start PLLs. Only the PLLs that were configured to be on prior to the entrance to
STOP mode will be started.
7. CCM will request GPC to restore Arm power by GPC_PUP_REQ. If power was
removed from the Arm platform, GPC will notify CCM by asserting signal
GPC_PUP_ACK that power to Arm is back on, and its safe to exit from STOP mode.
Only then will the CCM progress to the next step.
8. After assertion of notification from src that the resets for the power gated modules
has been finished, (src_power_gating_reset_done is set) negate the low power
request signals to all modules and enable all module clocks including Arm clocks
and CKIL sync, and return to run mode. (Clocks whose CCGR bits are not to be
opened in RUN mode will not be opened; they will continued to be gated.)

CCM Memory Map/Register Definition
After the system is in run mode, the ccm_ipg_stop and system_in_stop_mode signals
negate.
18.6 CCM Memory Map/Register Definition
NOTE
The register reset values for CCM change depending on the
boot configuration. See Clocks at boot time for more
information.
CCM memory map
Absolute
Width Section/
(in bits) page
(hex)
20C_4000 CCM Control Register (CCM_CCR) 32 R/W 0401_16FFh 18.6.1/668
20C_4004 CCM Control Divider Register (CCM_CCDR) 32 R/W 0000_0000h 18.6.2/670
20C_4008 CCM Status Register (CCM_CSR) 32 R 0000_0010h 18.6.3/671
20C_400C CCM Clock Switcher Register (CCM_CCSR) 32 R/W 0000_0100h 18.6.4/672
20C_4010 CCM Arm Clock Root Register (CCM_CACRR) 32 R/W 0000_0000h 18.6.5/674
20C_4014 CCM Bus Clock Divider Register (CCM_CBCDR) 32 R/W 0001_8D00h 18.6.6/675
20C_4018 CCM Bus Clock Multiplexer Register (CCM_CBCMR) 32 R/W 0002_0324h 18.6.7/678
20C_401C CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1) 32 R/W 00F0_0000h 18.6.8/681
20C_4020 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2) 32 R/W 02B9_2F06h 18.6.9/683
18.6.10/
20C_4024 CCM Serial Clock Divider Register 1 (CCM_CSCDR1) 32 R/W 0049_0B00h
685
18.6.11/
20C_4028 CCM SSI1 Clock Divider Register (CCM_CS1CDR) 32 R/W 0EC1_02C1h
687
18.6.12/
20C_402C CCM SSI2 Clock Divider Register (CCM_CS2CDR) 32 R/W 0007_36C1h
688
18.6.13/
20C_4030 CCM D1 Clock Divider Register (CCM_CDCDR) 32 R/W 33F7_1F92h
690
18.6.14/
20C_4034 CCM HSC Clock Divider Register (CCM_CHSCCDR) 32 R/W 0002_A150h
692
18.6.15/
20C_4038 CCM Serial Clock Divider Register 2 (CCM_CSCDR2) 32 R/W 0002_A150h
695
18.6.16/
20C_403C CCM Serial Clock Divider Register 3 (CCM_CSCDR3) 32 R/W 0001_0841h
697
CCM Divider Handshake In-Process Register 18.6.17/
20C_4048 32 R 0000_0000h
(CCM_CDHIPR) 699
18.6.18/
20C_4054 CCM Low Power Control Register (CCM_CLPCR) 32 R/W 0000_0079h
702

CCM memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
18.6.19/
20C_4058 CCM Interrupt Status Register (CCM_CISR) 32 w1c 0000_0000h
705
18.6.20/
20C_405C CCM Interrupt Mask Register (CCM_CIMR) 32 R/W FFFF_FFFFh
708
18.6.21/
20C_4060 CCM Clock Output Source Register (CCM_CCOSR) 32 R/W 000A_0001h
711
18.6.22/
20C_4064 CCM General Purpose Register (CCM_CGPR) 32 R/W 0000_FE62h
714
18.6.23/
20C_4068 CCM Clock Gating Register 0 (CCM_CCGR0) 32 R/W FFFF_FFFFh
715
18.6.24/
20C_406C CCM Clock Gating Register 1 (CCM_CCGR1) 32 R/W FFFF_FFFFh
717
18.6.25/
20C_4070 CCM Clock Gating Register 2 (CCM_CCGR2) 32 R/W FC3F_FFFFh
718
18.6.26/
720
18.6.27/
721
18.6.28/
20C_407C CCM Clock Gating Register 5 (CCM_CCGR5) 32 R/W FFFF_FFFFh
722
18.6.29/
724
18.6.30/
20C_4088 CCM Module Enable Overide Register (CCM_CMEOR) 32 R/W FFFF_FFFFh
725

18.6.1 CCM Control Register (CCM_CCR)
The figure below represents the CCM Control Register (CCR), which contains bits to
control general operation of CCM. The table below provides its field descriptions.
Address: 20C_4000h base + 0h offset = 20C_4000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 RBC_EN 0
REG_BYPASS_COUNT WB_COUNT
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COSC_EN
R 0 0
OSCNT
W
Reset 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1
CCM_CCR field descriptions

Field Description
Reserved
27 Enable for REG_BYPASS_COUNTER. If enabled, analog_reg_bypass signal will be asserted after
RBC_EN REG_BYPASS_COUNT clocks of CKIL, after standby voltage is requested. If standby voltage is not
requested analog_reg_bypass won't be asserted, event if counter is enabled.
1 REG_BYPASS_COUNTER enabled.
0 REG_BYPASS_COUNTER disabled
26–21 Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ.
REG_BYPASS_ Should be zeroed and reconfigured after exit from low power mode.
COUNT
REG_BYPASS_COUNT can also be used for holding off interrupts when the PGC unit is sending signals
to power gate the core.
000000 no delay
000001 1 CKIL clock period delay
111111 63 CKIL clock periods delay
Reserved
18–16 Well Bias counter. Delay, defined by this value, counted by CKIL clock will be applied till well bias is
WB_COUNT enabled at exit from wait or stop low power mode. Counter will be used if wb_core_at_lpm or
wb_per_at_lpm bits are set. Should be zeroed and reconfigured after exit from low power mode.
000 no delay

CCM_CCR field descriptions (continued)

Field Description
001 1 CKIL clock delay
111 7 CKIL clocks delay
Reserved
12 On chip oscillator enable bit - this bit value is reflected on the output cosc_en. The system will start with on
COSC_EN chip oscillator enabled to supply source for the PLLs. Software can change this bit if a transition to the
bypass PLL clocks was performed for all the PLLs. In cases that this bit is changed from '0' to '1' then
CCM will enable the on chip oscillator and after counting oscnt ckil clock cycles it will notify that on chip
oscillator is ready by an interrupt cosc_ready and by status bit cosc_ready. The cosc_en bit should be
changed only when on chip oscillator is not chosen as the clock source.
0 disable on chip oscillator

1 enable on chip oscillator
OSCNT Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for
oscillator lock time. This is used for oscillator lock time. Current estimation is ~5ms. This counter will be
used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip
oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened.
00000000 count 1 ckil

11111111 count 256 ckil's

18.6.2 CCM Control Divider Register (CCM_CCDR)
The figure below represents the CCM Control Divider Register (CCDR), which contains
bits that control the loading of the dividers that need handshake with the modules they
affect. The table below provides its field descriptions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMDC_CH0_
MMDC_CH1_
R 0
MASK
MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_CCDR field descriptions

Field Description
Reserved
17 During divider ratio mmdc_ch0_axi_podf change or sync mux periph_clk_sel change (but not jtag) or SRC
MMDC_CH0_ request during warm reset, mask handshake with mmdc_ch0 module.
MASK
This field value should be set to 1 for normal operation.
0 allow handshake with mmdc_ch0 module

1 mask handshake with mmdc_ch0. Request signal will not be generated.
16 During divider ratio mmdc_ch1_axi_podf change or sync mux periph2_clk_sel change (but not jtag) or
MMDC_CH1_ SRC request during warm reset, mask handshake with mmdc_ch1 module.
MASK
0 Allow handshake with mmdc_ch1 module.
1 Mask handshake with mmdc_ch1. Request signal will not be generated.

18.6.3 CCM Status Register (CCM_CSR)
The figure below represents the CCM status Register (CSR). The status bits are read-only
bits. The table below provides its field descriptions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COSC_READY
REF_EN_B
R 0 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
CCM_CSR field descriptions

Field Description
Reserved

CCM_CSR field descriptions (continued)

Field Description
5 Status indication of on board oscillator. This bit will be asserted if on chip oscillator is enabled and on chip
COSC_READY oscillator is not powered down, and if oscnt counter has finished counting.
0 on board oscillator is not ready.

1 on board oscillator is ready.
4 This read-only field is reserved and always has the value 1.
Reserved
Reserved
0 Status of the value of CCM_REF_EN_B output of ccm
REF_EN_B
0 value of CCM_REF_EN_B is '0'
1 value of CCM_REF_EN_B is '1'
18.6.4 CCM Clock Switcher Register (CCM_CCSR)
The figure below represents the CCM Clock Switcher register (CCSR). The CCSR
register contains bits to control the switcher sub-module dividers and multiplexers. The
table below provides its field descriptions.
Address: 20C_4000h base + Ch offset = 20C_400Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pll2_pfd1_594m_dis_mask
SECONDARY_CLK_SEL
PLL1_SW_CLK_SEL
PLL3_SW_CLK_SEL
pll3_pfd1_dis_mask
pll3_pfd0_dis_mask
pll3_pfd3_dis_mask
pll3_pfd2_dis_mask
pll2_pfd0_dis_mask
pll2_pfd2_dis_mask
R 0
STEP_SEL
Reserved
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

CCM_CCSR field descriptions

Field Description
Reserved
15 Mask of PLL3 PFD1 auto-disable.
pll3_pfd1_dis_
mask 0 - PLL3 PFD1 disable=0 (PFD always on)
1 PLL3 PFD1 disable is managed by associated dividers disable. If all PLL3 PFD1-driven dividers are
closed, PFD is disabled.
pll3_pfd0_dis_
mask 0 PLL3 PFD0 disable=0 (PFD always on)
pll3_pfd3_dis_
pll3_pfd2_dis_
pll2_pfd1_594m_
dis_mask 0 PLL2 PFD1 disable=0 (PFD always on)
pll2_pfd0_dis_
pll2_pfd2_dis_
8 Selects the option to be chosen for the step frequency when shifting Arm frequency. This will control the
STEP_SEL step_clk.
NOTE: This mux is allowed to be changed only if its output is not used, i.e. Arm uses the output of pll1,
and step_clk is not used.
0 derive clock from osc_clk (24M) - source for lp_apm.

1 derive clock from secondary_clk
Reserved
3 Select source to generate secondary_clk
SECONDARY_
CLK_SEL 0 PLL2 PFD2 (400 M)
1 PLL2 (528 M)

CCM_CCSR field descriptions (continued)

Field Description
2 Selects source to generate pll1_sw_clk.
PLL1_SW_CLK_
SEL 0 pll1_main_clk
1 step_clk
- Reserved
0 Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes.
PLL3_SW_CLK_
SEL 0 pll3_main_clk
1 pll3 bypass clock
18.6.5 CCM Arm Clock Root Register (CCM_CACRR)
The figure below represents the CCM Arm Clock Root register (CACRR). The CACRR
register contains bits to control the Arm clock root generation. The table below provides
its field descriptions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ARM_
W PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_CACRR field descriptions

Field Description
Reserved
ARM_PODF Divider for Arm clock root.
NOTE: If arm_freq_shift_divider is set to '1' then any new write to arm_podf will be held until
arm_clk_switch_req signal is asserted.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8

18.6.6 CCM Bus Clock Divider Register (CCM_CBCDR)
The figure below represents the CCM Bus Clock Divider Register (CBCDR). The
CBCDR register contains bits to control the clock generation sub module dividers. The
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIPH2_CLK_
PERIPH_CLK_
R
PERIPH_CLK2_ SEL
SEL
Reserved Reserved mmdc_ch0_axi_podf AXI_PODF
PODF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
AXI_
AXI_ PERIPH2_CLK2_
Reserved AHB_PODF IPG_PODF ALT_ mmdc_ch1_axi_podf
SEL PODF
SEL
W
Reset 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0
CCM_CBCDR field descriptions

Field Description
- Reserved
29–27 Divider for periph_clk2_podf.
PERIPH_CLK2_
PODF 000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
26
PERIPH2_CLK_ Selector for peripheral2 main clock (source of mmdc_ch1_clk_root).
SEL
NOTE: Any change of this mux select will involve handshake with the MMDC. Refer to the CCDR and
CDHIPR registers for the handshake bypass and busy bits.

CCM_CBCDR field descriptions (continued)

Field Description
0 PLL2 (pll2_main_clk)
1 derive clock from periph2_clk2_clk clock source.
25 Selector for peripheral main clock.
PERIPH_CLK_
SEL NOTE: Alternative clock source should be used when PLL is relocked. For PLL relock procedure pls refer
to the PLL chapter.
NOTE: Any change of this sync mux select will involve handshake with the MMDC. Refer to the CCDR
and CDHIPR registers for the handshake bypass and busy bits.
0 PLL2 (pll2_main_clk)
1 derive clock from periph_clk2_clk clock source.
- Reserved
21–19 Divider for mmdc_ch0_axi podf.
mmdc_ch0_axi_
podf 000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
18–16 Divider for axi podf.
AXI_PODF
NOTE: Any change of this divider might involve handshake with EMIand IPU. See CDHIPR register for
the handshake busy bits.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
- Reserved
12–10 Divider for AHB PODF.
AHB_PODF
NOTE: Any change of this divider might involve handshake with EMIand IPU. See CDHIPR register for
the handshake busy bits.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6

CCM_CBCDR field descriptions (continued)

Field Description
110 divide by 7
111 divide by 8
9–8 Divider for ipg podf.
IPG_PODF
NOTE: SDMA module will not support ratio of 1:3 and 1:4 for ahb_clk:ipg_clk. In case SDMA is used,
then those ratios should not be used.
00 divide by 1
01 divide by 2
10 divide by 3
11 divide by 4
7 AXI alternative clock select
AXI_ALT_SEL
0 PLL2 PFD2 will be selected as alternative clock for AXI root clock
1 PLL3 PFD1 will be selected as alternative clock for AXI root clock
6 AXI clock source select
AXI_SEL
0 Periph_clk output will be used as AXI clock root
1 AXI alternative clock will be used as AXI clock root
5–3 Divider for mmdc_ch1_axi podf.
mmdc_ch1_axi_ NOTE: This design implementation does not use MMDC_CH1_CLK_ROOT as a clock source to the
podf MMDC. Only MMDC_CH0_CLK_ROOT is used.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
PERIPH2_CLK2_ Divider for periph2_clk2 podf.
PODF
NOTE: Divider should be updated when output clock is gated.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8

18.6.7 CCM Bus Clock Multiplexer Register (CCM_CBCMR)

The figure below represents the CCM Bus Clock Multiplexer Register (CBCMR). The
CBCMR register contains bits to control the multiplexers that generate the bus clocks.
The table below provides its field descriptions.
NOTE
Any change on the above multiplexer will have to be done
while the module that its clock is affected is not functional and
the respective clock is gated in LPCG. If the change will be
done during operation of the module, then it is not guaranteed
that the modules operation will not be harmed.
The change for arm_clk_sel should be done through sdma so that Arm will not use this
clock during the change and the clock will be gated in LPCG.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIPH2_CLK2_
R
PRE_ PRE_
gpu2d_core_clk_ gpu2d_core_
SEL
gpu3d_shader_podf gpu3d_core_podf PERIPH2_ PERIPH_
podf clk_sel
CLK_SEL CLK_SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pcie_axi_clk_sel
gpu3d_axi_clk_
gpu2d_axi_clk_
vdoaxi_clk_sel
R
gpu3d_
VPU_AXI_ PERIPH_ gpu3d_core_
shader_clk_ Reserved Reserved
sel
sel
CLK_SEL CLK2_SEL clk_sel
sel
W
Reset 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0
CCM_CBCMR field descriptions

Field Description
31–29 Divider for gpu3d_shader clock.
gpu3d_shader_
podf NOTE: Divider should be updated when output clock is gated.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6

CCM_CBCMR field descriptions (continued)

Field Description
110 divide by 7
111 divide by 8
28–26 Divider for gpu3d_core clock.
gpu3d_core_podf
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
25–23 Divider for gpu2d_core clock.
gpu2d_core_clk_
podf NOTE: Divider should be updated when output clock is gated.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
22–21 Selector for pre_periph2 clock multiplexer
PRE_PERIPH2_
CLK_SEL 00 derive clock from PLL2
01 derive clock from PLL2 PFD2
11 derive clock from divided (/2) PLL2 PFD2
20 Selector for periph2_clk2 clock multiplexer
PERIPH2_CLK2_
SEL 0 derive clock from pll3_sw_clk
1 derive clock from PLL2 Main
19–18 Selector for pre_periph clock multiplexer
PRE_PERIPH_
CLK_SEL 00 derive clock from PLL2
11 derive clock from divided (/2) PLL2 PFD2
17–16 Selector for open vg (GPU2D Core) clock multiplexer
gpu2d_core_clk_
sel 00 derive clock from AXI
01 derive clock from pll3_sw_clk

CCM_CBCMR field descriptions (continued)

Field Description
15–14 Selector for VPU axi clock multiplexer
VPU_AXI_CLK_
SEL 00 derive clock from AXI
11 Reserved
13–12 Selector for peripheral clk2 clock multiplexer
PERIPH_CLK2_
SEL 00 derive clock from pll3_sw_clk
01 derive clock from osc_clk (pll1_ref_clk)
10 derive clock from pll2_bypass_clk
11 reserved
11 Selector for vdoaxi clock multiplexer
vdoaxi_clk_sel
0 derive clock from AXI clock
1 derive clock from AHB clock
10 Selector for pcie_axi clock multiplexer
pcie_axi_clk_sel
0 derive clock from AXI clock
1 derive clock from AHB clock
9–8 Selector for gpu3d_shader clock multiplexer
gpu3d_shader_
clk_sel 00 derive clock from mmdc_ch0 clk
- Reserved
5–4 Selector for gpu3d_core clock multiplexer
gpu3d_core_clk_
sel 00 derive clock from mmdc_ch0
- Reserved
1 Selector for gpu3d_axi clock multiplexer
gpu3d_axi_clk_
sel 0 derive clock from axi
1 derive clock from system_133M_clk
0 Selector for gpu2d_axi clock multiplexer
gpu2d_axi_clk_
sel 0 derive clock from axi
1 derive clock from system_133M_clk

18.6.8 CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1)

The figure below represents the CCM Serial Clock Multiplexer Register 1 (CSCMR1).
The CSCMR1 register contains bits to control the multiplexers that generate the serial
clocks. The table below provides its field descriptions.
NOTE
the clock is gated. If the change will be done during operation
of the module, then it is not guaranteed that the modules
operation will not be harmed.
Address: 20C_4000h base + 1Ch offset = 20C_401Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USDHC4_CLK_SEL
USDHC3_CLK_SEL
USDHC2_CLK_SEL
USDHC1_CLK_SEL
R 0
Reserved
ACLK_EIM_ ACLK_EIM_SLOW_
ACLK_SEL ACLK_PODF
SLOW_SEL PODF
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSI3_CLK_ SSI2_CLK_ SSI1_CLK_

Reserved PERCLK_PODF
SEL SEL SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_CSCMR1 field descriptions

Field Description
Reserved
30–29 Selector for aclk_eim_slow root clock multiplexer
ACLK_EIM_
SLOW_SEL 00 derive clock from AXI

CCM_CSCMR1 field descriptions (continued)

Field Description
28–27 Selector for aclk root clock multiplexer
ACLK_SEL
10 derive clock from AXI
- Reserved
25–23 Divider for aclk_eim_slow clock root.
ACLK_EIM_
SLOW_PODF 000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
22–20 Divider for aclk clock root.
ACLK_PODF
NOTE: These bits are inverted between R/W and are not sequential.
000 divide by 7 (Read value 110)

19 Selector for usdhc4 clock multiplexer
USDHC4_CLK_
SEL 0 derive clock from PLL2 PFD2
USDHC3_CLK_
USDHC2_CLK_
USDHC1_CLK_

CCM_CSCMR1 field descriptions (continued)

Field Description
15–14 Selector for ssi3 clock multiplexer
SSI3_CLK_SEL
10 derive clock from PLL4
11 Reserved
SSI2_CLK_SEL
11 Reserved
SSI1_CLK_SEL
11 Reserved
- Reserved
PERCLK_PODF Divider for perclk podf.
000000 divide by 1
000001 divide by 2
000010 divide by 3
000011 divide by 4
000100 divide by 5
000101 divide by 6
000110 divide by 7
111111 divide by 64
18.6.9 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2)

The figure below represents the CCM Serial Clock Multiplexer Register 2 (CSCMR2).
The CSCMR2 register contains bits to control the multiplexers that generate the serial
clocks. The table below provides its field descriptions.
NOTE
the clock is gated. If the change will be done during operation
of the module, then it is not guaranteed that the modules
operation will not be harmed.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ESAI_CLK_
Reserved Reserved
SEL
W
Reset 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDB_DI1_IPU_
LDB_DI0_IPU_
R
DIV
DIV
Reserved Reserved CAN_CLK_PODF Reserved
W
Reset 0 0 1 0 1 1 1 1 0 0 0 0 0 1 1 0
CCM_CSCMR2 field descriptions

Field Description
- Reserved
20–19 Selector for esai clock multiplexer
ESAI_CLK_SEL
00 derive clock from PLL4 divided clock
01 derive clock from PLL3 PFD2 clock
10 derive clock from PLL3 PFD3 clock
- Reserved
11 Control for divider of ldb clock for IPU di1
LDB_DI1_IPU_
DIV 0 divide by 3.5
1 divide by 7
10 Control for divider of ldb clock for IPU di0
LDB_DI0_IPU_
DIV 0 divide by 3.5
1 divide by 7
- Reserved
7–2 Divider for CAN clock podf.
CAN_CLK_
...
000111 divide by 8
...
111111 divide by 2^6
Reserved

18.6.10 CCM Serial Clock Divider Register 1 (CCM_CSCDR1)

The figure below represents the CCM Serial Clock Divider Register 1 (CSCDR1). The
CSCDR1 register contains bits to control the clock generation sub-module dividers. The
NOTE
Any change on the above dividers will have to be done while
the module that its clock is affected is not functional and the
affected clock is gated. If the change will be done during
operation of the module, then it is not guaranteed that the
modules operation will not be harmed.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 VPU_AXI_PODF USDHC4_PODF USDHC3_PODF USDHC2_PODF
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved USDHC1_PODF Reserved UART_CLK_PODF
Reset 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0
CCM_CSCDR1 field descriptions

Field Description
Reserved
27–25 Divider for vpu axi clock podf.
VPU_AXI_PODF
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
24–22 Divider for usdhc4 clock pred.
USDHC4_PODF
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4

CCM_CSCDR1 field descriptions (continued)

Field Description
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
21–19 Divider for usdhc3 clock podf.
USDHC3_PODF
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
18–16 Divider for usdhc2 clock.
USDHC2_PODF
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
- Reserved
13–11 Divider for usdhc1 clock podf.
USDHC1_PODF
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
- Reserved.
UART_CLK_ Divider for uart clock podf.
PODF
000000 divide by 1

18.6.11 CCM SSI1 Clock Divider Register (CCM_CS1CDR)
The figure below represents the CCM ESAI, SSI1, and SSI3 Clock Divider Register
(CS1CDR). The CS1CDR register contains bits to control the SSI1 and SSI3 clock
generation dividers. The table below provides its field descriptions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ESAI_ SSI3_ 0 ESAI_ SSI1_
CLK_ CLK_ SSI3_CLK_PODF CLK_ CLK_ SSI1_CLK_PODF
W
PODF PRED PRED PRED
Reset 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1
CCM_CS1CDR field descriptions

Field Description
Reserved
27–25 Divider for esai clock podf.
ESAI_CLK_
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
24–22 Divider for ssi3 clock pred.
SSI3_CLK_
PRED 000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
21–16 Divider for ssi3 clock podf.
SSI3_CLK_
The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
PODF
000000 divide by 1
Reserved

CCM_CS1CDR field descriptions (continued)

Field Description
11–9 Divider for esai clock pred.
ESAI_CLK_
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
8–6 Divider for ssi1 clock pred.
SSI1_CLK_
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
SSI1_CLK_ Divider for ssi1 clock podf.
PODF
The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
000000 divide by 1
18.6.12 CCM SSI2 Clock Divider Register (CCM_CS2CDR)
The figure below represents the CCM SSI2, LDB Clock Divider Register (CS2CDR).
The CS2CDR register contains bits to control the SSI2 clock generation dividers, and ldb
serial clocks select. The table below provides its field descriptions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 ENFC_CLK_
ENFC_CLK_PODF ENFC_CLK_PRED
W SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 LDB_DI1_CLK_SEL LDB_DI0_CLK_SEL SSI2_CLK_PRED SSI2_CLK_PODF
W
Reset 0 0 1 1 0 1 1 0 1 1 0 0 0 0 0 1

CCM_CS2CDR field descriptions

Field Description
Reserved
26–21 Divider for enfc clock divider.
ENFC_CLK_
000001 divide by 2
20–18
ENFC_CLK_ Divider for enfc clock pred divider.
PRED
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
17–16
ENFC_CLK_SEL Selector for enfc clock multiplexer
NOTE: Multiplexor should be updated when output clock is gated.

Reserved
14–12
LDB_DI1_CLK_ Selector for ldb_di1 clock multiplexer
SEL
NOTE: Multiplexor should be updated when both input and output clocks are gated.
000 pll5 clock

011 derive clock from mmdc_ch1 clock
101-111 Reserved
11–9
LDB_DI0_CLK_ Selector for ldb_di1 clock multiplexer
SEL
NOTE: Multiplexor should be updated when both input and output clocks are gated.
000 PLL5 clock


CCM_CS2CDR field descriptions (continued)

Field Description
101-111 Reserved
8–6
SSI2_CLK_ Divider for ssi2 clock pred.
PRED
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
SSI2_CLK_ Divider for ssi2 clock podf.
PODF The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
000000 divide by 1
18.6.13 CCM D1 Clock Divider Register (CCM_CDCDR)
The figure below represents the CCM DI Clock Divider Register (CDCDR). The table
below provides its field descriptions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSI_TX_CLK_
SPDIF0_
SEL
HSI_TX_PODF SPDIF0_CLK_PRED SPDIF0_CLK_PODF Reserved

CLK_SEL
W
Reset 0 0 1 1 0 0 1 1 1 1 1 1 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserv SPDIF1_
SPDIF1_CLK_PRED SPDIF1_CLK_PODF Reserved
ed CLK_SEL
W
Reset 0 0 0 1 1 1 1 1 1 0 0 1 0 0 1 0

CCM_CDCDR field descriptions

Field Description
31–29 Divider for hsi_tx clock podf.
HSI_TX_PODF
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
28 Selector for hsi_tx clock multiplexer
HSI_TX_CLK_
SEL 0 derive from pll3_120M clock
27–25 Divider for spdif0 clock pred.
SPDIF0_CLK_
PRED NOTE: Divider should be updated when output clock is gated.
000 divide by 1 (do not use with high input frequencies)

001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
24–22 Divider for spdif0 clock podf.
SPDIF0_CLK_
PODF NOTE: Divider should be updated when output clock is gated.
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
21–20 Selector for spdif0 clock multiplexer
SPDIF0_CLK_
SEL 00 derive clock from PLL4 divided clock
- Reserved

CCM_CDCDR field descriptions (continued)

Field Description
14–12 Divider for spdif1 clock pred.
SPDIF1_CLK_
PRED NOTE: Divider should be updated when output clock is gated.
NOTE: Used for ASRC clock, not related to SPDIF module
000 divide by 1 (do not use with high input frequencies)

001 divide by 2
010 divide by 3
111 divide by 8
11–9 Divider for spdif1 clock podf.
SPDIF1_CLK_
NOTE: Used for ASRC clock, not related to SPDIF module
000 divide by 1
111 divide by 8
8–7 Selector for spdif1 clock multiplexer
SPDIF1_CLK_
SEL NOTE: Used for ASRC clock, not related to SPDIF module
00 derive clock from PLL4 divided clock

Reserved
18.6.14 CCM HSC Clock Divider Register (CCM_CHSCCDR)
The figure below represents the CCM HSC Clock Divider Register (CHSCCDR). The
CHSCCDR register contains bits to control the ipu di clock generation dividers. The table
below provides its field descriptions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ipu1_di1_ ipu1_di0_
ipu1_di1_ ipu1_di1_ ipu1_di0_ ipu1_di0_
pre_clk_ pre_clk_
W podf clk_sel podf clk_sel
sel sel
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0

CCM_CHSCCDR field descriptions

Field Description
Reserved
17–15
ipu1_di1_pre_ Selector for ipu1 di1 root clock pre-multiplexer
clk_sel
NOTE: Multiplexor should only be updated when the output clock is gated. Please refer to System Clocks
for the respective output clock gating bits.

010 derive clock from pll5
110-111 Reserved
14–12 Divider for ipu1_di clock divider.
ipu1_di1_podf
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
11–9
ipu1_di1_clk_sel Selector for ipu1 di1 root clock multiplexer
000 derive clock from divided pre-muxed ipu1 di1 clock

001 derive clock from ipp_di0_clk
011 derive clock from ldb_di0_clk
101-111 Reserved
8–6
clk_sel


CCM_CHSCCDR field descriptions (continued)

Field Description
110-111 Reserved
5–3 Divider for ipu1_di0 clock divider.
ipu1_di0_podf
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
ipu1_di0_clk_sel
Selector for ipu1 di0 root clock multiplexer

101-111 Reserved

The figure below represents the CCM Serial Clock Divider Register 2(CSCDR2). The
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ipu2_di1_pre_clk_sel
R
Reserved
Reserved ECSPI_CLK_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ipu2_di1_podf ipu2_di1_clk_sel ipu2_di0_podf ipu2_di0_clk_sel
Reset 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0

Field Description
- Reserved
24–19 Divider for ecspi clock podf.
ECSPI_CLK_
NOTE: The input clock to this divider should be lower than 300Mhz, the predivider can be used to
achieve this.
000000 divide by 1
- Reserved


Field Description
17–15
clk_sel

110-111 Reserved
ipu2_di1_podf
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
11–9
ipu2_di1_clk_sel Selector for ipu1 di2 root clock multiplexer

101-111 Reserved
8–6
clk_sel

110-111 Reserved


Field Description
ipu2_di0_podf
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
ipu2_di0_clk_sel
Selector for ipu2 di0 root clock multiplexer
NOTE: Multiplexor should be updated only when the output clock is gated.

101-111 Reserved
The figure below represents the CCM Serial Clock Divider Register 3(CSCDR3). The
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 ipu2_hsp_podf
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ipu2_hsp_ ipu1_hsp_
ipu1_hsp_podf Reserved
W clk_sel clk_sel
Reset 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1


Field Description
Reserved
18–16 Divider for ipu2_hsp clock.
ipu2_hsp_podf
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
15–14 Selector for ipu2_hsp clock multiplexer
ipu2_hsp_clk_sel
10 derive clock from pll3_120M
13–11 Divider for ipu1_hsp clock.
ipu1_hsp_podf
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
10–9 Selector for ipu1_hsp clock multiplexer
ipu1_hsp_clk_sel
10 derive clock from pll3_120M
Reserved

18.6.17 CCM Divider Handshake In-Process Register

(CCM_CDHIPR)
The figure below represents the CCM Divider Handshake In-Process Register
(CDHIPR). The CDHIPR register contains read-only bits that indicate that CCM is in the
process of updating dividers or muxes that might need handshake with modules.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARM_PODF_BUSY
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERIPH2_CLK_SEL_BUSY
PERIPH_CLK_SEL_BUSY
mmdc_ch0_podf_busy
mmdc_ch1_podf_busy
AHB_PODF_BUSY
AXI_PODF_BUSY
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_CDHIPR field descriptions

Field Description
Reserved
16 Busy indicator for arm_podf.
ARM_PODF_
BUSY 0 divider is not busy and its value represents the actual division.
1 divider is busy with handshake process with module. The value read in the divider represents the
previous value of the division factor, and after the handshake the written value of the arm_podf will be
applied.
Reserved
5 Busy indicator for periph_clk_sel mux control.
PERIPH_CLK_
SEL_BUSY 0 mux is not busy and its value represents the actual division.
1 mux is busy with handshake process with module. The value read in the periph_clk_sel represents the
previous value of select, and after the handshake periph_clk_sel value will be applied.
4 Busy indicator for mmdc_ch0_axi_podf.
mmdc_ch0_
podf_busy

CCM_CDHIPR field descriptions (continued)

Field Description
0 divider is not busy and its value represents the actual division.
previous value of the division factor, and after the handshake the written value of the
mmdc_ch0_axi_podf will be applied.
3 Busy indicator for periph2_clk_sel mux control.
PERIPH2_CLK_
SEL_BUSY 0 mux is not busy and its value represents the actual division.
1 mux is busy with handshake process with module. The value read in the periph2_clk_sel represents
the previous value of select, and after the handshake periph2_clk_sel value will be applied.
2 Busy indicator for mmdc_ch1_axi_podf.
mmdc_ch1_
podf_busy 0 divider is not busy and its value represents the actual division.
previous value of the division factor, and after the handshake the written value of the
mmdc_ch1_axi_podf will be applied.
1 Busy indicator for ahb_podf.
AHB_PODF_
previous value of the division factor, and after the handshake the written value of the ahb_podf will be
applied.
0 Busy indicator for axi_podf.
AXI_PODF_
previous value of the division factor, and after the handshake the written value of the axi_podf will be
applied.

18.6.18 CCM Low Power Control Register (CCM_CLPCR)
The figure below represents the CCM Low Power Control Register (CLPCR). The
CLPCR register contains bits to control the low power modes operation.The table below
provides its field descriptions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYPASS_MMDC_CH1_
BYPASS_MMDC_CH0_
MASK_CORE0_WFI
MASK_L2CC_IDLE
R 0 MASK_SCU_IDLE 0 0
mask_core3_wfi
mask_core2_wfi
mask_core1_wfi
wb_per_at_lpm
Reserved
LPM_HS
LPM_HS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARM_CLK_DIS_ON_LPM
COSC_PWRDOWN
R 0
Reserved
DIS_
SBYOS
VSTBY
STBY_
REF_ Reserved LPM
COUNT
OSC
W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1
CCM_CLPCR field descriptions

Field Description
Reserved
27 Mask L2CC IDLE for entering low power mode.
MASK_L2CC_
IDLE NOTE: Assertion of all bits[27:22] will generate low power mode request
1 L2CC IDLE is masked

0 L2CC IDLE is not masked
26 Mask SCU IDLE for entering low power mode
MASK_SCU_
IDLE NOTE: Assertion of all bits[27:22] will generate low power mode request
1 SCU IDLE is masked

0 SCU IDLE is not masked

CCM_CLPCR field descriptions (continued)

Field Description
25 Mask WFI of core3 for entering low power mode
mask_core3_wfi
NOTE: Assertion of all bits[27:22] will generate low power mode request
1 WFI of core3 is masked

0 WFI of core3 is not masked
mask_core2_wfi

mask_core1_wfi

MASK_CORE0_
WFI NOTE: Assertion of all bits[27:22] will generate low power mode request

21 Bypass handshake with mmdc_ch1 on next entrance to low power mode (STOP or WAIT). CCM doesn't
BYPASS_ wait for the module's acknowledge.
MMDC_CH1_
LPM_HS 0 Handshake with mmdc_ch1 on next entrance to low power mode will be performed.
1 Handshake with mmdc_ch1 on next entrance to low power mode will be bypassed.
Reserved
19
BYPASS_ Bypass handshake with mmdc_ch0 on next entrance to low power mode (STOP or WAIT). CCM doesn't
MMDC_CH0_ wait for the module's acknowledge. Handshake will also be bypassed, if CGR3 CG10 is set to gate fast
LPM_HS mmdc_ch0 clock.
NOTE: MMDC_CH0 clock is not used. This bit should always be programmed HIGH to let CCM know not
to wait for the acknowledge from MMDC_CH0, due to no connection.
0 Handshake with mmdc_ch0 on next entrance to low power mode will be performed.
1 Handshake with mmdc_ch0 on next entrance to low power mode will be bypassed.
Reserved
- Reserved
16 Enable periphery charge pump for well biasing at low power mode (stop or wait)
wb_per_at_lpm
0 Periphery charge pump won't be enabled at STOP or WAIT low power modes
1 Periphery charge pump will be enabled at STOP or WAIT low power modes
Reserved


Field Description
11 In run mode, software can manually control powering down of on chip oscillator, i.e. generating '1' on
COSC_ cosc_pwrdown signal. If software manually powered down the on chip oscillator, then sbyos functionality
PWRDOWN for on chip oscillator will be bypassed.
The manual closing of onchip oscillator should be performed only in case the reference oscilator is not the
source of all the clocks generation.
0 On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.

1 On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
10–9 Standby counter definition. These two bits define, in the case of stop exit (if VSTBY bit was set).
STBY_COUNT
NOTE: Clock cycles ratio depends on pmic_delay_scaler, defined by CGPR[0] bit.
00 CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles

8 Voltage standby request bit. This bit defines if PMIC_STBY_REQ pin, which notifies external power
VSTBY management IC to move from functional voltage to standby voltage, will be asserted in STOP mode.
0 Voltage will not be changed to standby voltage after next entrance to STOP mode.
( PMIC_STBY_REQ will remain negated - '0')
1 Voltage will be requested to change to standby voltage after next entrance to stop mode.
( PMIC_STBY_REQ will be asserted - '1').
7 dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i.e.
DIS_REF_OSC generating '1' on CCM_REF_EN_B signal. If software closed manually the external reference clock, then
sbyos functionality will be bypassed.
The manual closing of external reference oscilator should be performed only in case the reference
oscilator is not the source of any clock generation.
NOTE: When returning from stop mode, the PMIC_STBY_REQ will be deasserted (if it was asserted
when entering stop mode). See stby_count bits.
0 external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.

1 external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
6 Standby clock oscillator bit. This bit defines if cosc_pwrdown, which power down the on chip oscillator, will
SBYOS be asserted in STOP mode. This bit is discarded if cosc_pwrdown='1' for the on chip oscillator.
0 On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B
will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0')
1 On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will
be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode,
external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after
oscnt count, CCM will continue with the exit from the STOP mode process.
5 Define if Arm clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait
ARM_CLK_DIS_ mode. This is useful for debug mode, when the user still wants to simulate entering wait mode and still
ON_LPM keep Arm clock functioning.
NOTE: Software should not enable Arm power gating in wait mode if this bit is cleared.
0 Arm clock enabled on wait mode.

1 Arm clock disabled on wait mode. .


Field Description
- Reserved
- Reserved
LPM
Setting the low power mode that system will enter on next assertion of dsm_request signal.
NOTE: Set CCM_CGPR[INT_MEM_CLK_LPM] and CCM_CGPR[1] bits to 1 when setting

CCM_CLPCR[LPM] bits to 01 (WAIT Mode) or 10 (STOP mode) without power gating.
CCM_CGPR[INT_MEM_CLK_LPM] and CCM_CGPR[1] bits do not have to be set for STOP
mode entry.
00 Remain in run mode

01 Transfer to wait mode
10 Transfer to stop mode
11 Reserved
18.6.19 CCM Interrupt Status Register (CCM_CISR)

The figure below represents the CCM Interrupt Status Register (CISR). This is a write
one to clear register. After an interrupt is generated, software should write one to clear it.
The table below provides its field descriptions.
NOTE
CCM interrupt request 1 can be masked by CCM interrupt
request 1 mask bit. CCM interrupt request 2 can be masked by
CCM interrupt request 2 mask bit.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
mmdc_ch0_podf_loaded
mmdc_ch1_podf_loaded
ARM_PODF_LOADED
AHB_PODF_LOADED
PERIPH2_CLK_SEL_
AXI_PODF_LOADED
PERIPH_CLK_SEL_
LOADED
LOADED
R 0 0 0 0
W w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COSC_READY
LRF_PLL
R 0 0
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_CISR field descriptions

Field Description
Reserved

CCM_CISR field descriptions (continued)

Field Description
26 CCM interrupt request 1 generated due to frequency change of arm_podf. The interrupt will commence
ARM_PODF_ only if arm_podf is loaded during a DVFS operation.
LOADED
0 interrupt is not generated due to frequency change of arm_podf
1 interrupt generated due to frequency change of arm_podf
Reserved
23 CCM interrupt request 1 generated due to update of mmdc_ch0_axi_podf.
mmdc_ch0_
podf_loaded 0 interrupt is not generated due to update of mmdc_ch0_axi_podf.
1 interrupt generated due to update of mmdc_ch0_axi_podf*
22 CCM interrupt request 1 generated due to update of periph_clk_sel.
PERIPH_CLK_
SEL_LOADED 0 interrupt is not generated due to update of periph_clk_sel.
1 interrupt generated due to update of periph_clk_sel.
21 CCM interrupt request 1 generated due to frequency change of mmdc_ch0_podf_ loaded
mmdc_ch1_
podf_loaded 0 interrupt is not generated due to frequency change of mmdc_ch0_podf_ loaded
1 interrupt generated due to frequency change of mmdc_ch0_podf_ loaded
20 CCM interrupt request 1 generated due to frequency change of ahb_podf
AHB_PODF_
LOADED 0 interrupt is not generated due to frequency change of ahb_podf
1 interrupt generated due to frequency change of ahb_podf
19 CCM interrupt request 1 generated due to frequency change of periph2_clk_sel
PERIPH2_CLK_
SEL_LOADED 0 interrupt is not generated due to frequency change of periph2_clk_sel
1 interrupt generated due to frequency change of periph2_clk_sel
Reserved
0 interrupt is not generated due to frequency change of mmdc_ch0_axi_podf
1 interrupt generated due to frequency change of mmdc_ch0_axi_podf
17 CCM interrupt request 1 generated due to frequency change of axi_podf
AXI_PODF_
LOADED 0 interrupt is not generated due to frequency change of axi_podf
1 interrupt generated due to frequency change of axi_podf
Reserved
6 CCM interrupt request 2 generated due to on board oscillator ready, i.e. oscnt has finished counting.
COSC_READY
0 interrupt is not generated due to on board oscillator ready
1 interrupt generated due to on board oscillator ready
Reserved
0 CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs
LRF_PLL
0 interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
1 interrupt generated due to lock ready of all enabled and not bypaseed PLLs

18.6.20 CCM Interrupt Mask Register (CCM_CIMR)
The figure below represents the CCM Interrupt Mask Register (CIMR). The table below
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
mask_mmdc_ch0_axi_podf_loaded
1 1 1
MASK_PERIPH2_CLK_SEL_LOADED
R
MASK_PERIPH_CLK_SEL_LOADED
mask_mmdc_ch0_podf_loaded
mask_mmdc_ch1_podf_loaded
MASK_AHB_PODF_LOADED
MASK_AXI_PODF_LOADED
ARM_PODF_LOADED
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 1 1
MASK_COSC_READY
MASK_LRF_PLL
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CCM_CIMR field descriptions

Field Description
Reserved
26 mask interrupt generation due to frequency change of arm_podf
ARM_PODF_
LOADED 0 don't mask interrupt due to frequency change of arm_podf - interrupt will be created
1 mask interrupt due to frequency change of arm_podf
Reserved
23 mask interrupt generation due to update of mask_mmdc_ch0_podf
mask_mmdc_
ch0_podf_loaded 0 don't mask interrupt due to update of mask_mmdc_ch0_podf - interrupt will be created
1 mask interrupt due to update of mask_mmdc_ch0_podf
22 mask interrupt generation due to update of periph_clk_sel.
MASK_PERIPH_
CLK_SEL_ 0 don't mask interrupt due to update of periph_clk_sel - interrupt will be created
LOADED 1 mask interrupt due to update of periph_clk_sel
21 mask interrupt generation due to update of mask_mmdc_ch1_podf
mask_mmdc_
ch1_podf_loaded 0 don't mask interrupt due to update of mask_mmdc_ch1_podf - interrupt will be created
1 mask interrupt due to update of mask_mmdc_ch1_podf

CCM_CIMR field descriptions (continued)

Field Description
20 mask interrupt generation due to frequency change of ahb_podf
MASK_AHB_
PODF_LOADED 0 don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
1 mask interrupt due to frequency change of ahb_podf
19 mask interrupt generation due to update of periph2_clk_sel.
MASK_
PERIPH2_CLK_ 0 don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
SEL_LOADED 1 mask interrupt due to update of periph2_clk_sel
18 mask interrupt generation due to frequency change of mmdc_ch0_axi_podf
mask_mmdc_
ch0_axi_podf_ 0 don't mask interrupt due to frequency change of mmdc_ch0_axi_podf - interrupt will be created
loaded 1 mask interrupt due to frequency change of mmdc_ch0_axi_podf
17 mask interrupt generation due to frequency change of axi_podf
MASK_AXI_
PODF_LOADED 0 don't mask interrupt due to frequency change of axi_podf - interrupt will be created
1 mask interrupt due to frequency change of axi_podf
Reserved
6 mask interrupt generation due to on board oscillator ready
MASK_COSC_
READY 0 don't mask interrupt due to on board oscillator ready - interrupt will be created
1 mask interrupt due to on board oscillator ready
Reserved
0 mask interrupt generation due to lrf of PLLs
MASK_LRF_PLL
0 don't mask interrupt due to lrf of PLLs - interrupt will be created
1 mask interrupt due to lrf of PLLs

18.6.21 CCM Clock Output Source Register (CCM_CCOSR)
The figure below represents the CCM Clock Output Source Register (CCOSR). The
CCOSR register contains bits to control the clocks that will be generated on the output
ipp_do_clko1 (CCM_CLKO1) and ipp_do_clko2 (CCM_CLKO2).The table below
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLKO2_EN
R
CLKO2_DIV CLKO2_SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
CLKO1_EN
CLK_OUT_
R
SEL
CLKO1_DIV CLKO1_SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
CCM_CCOSR field descriptions

Field Description
Reserved
24 Enable of CCM_CLKO2 clock
CLKO2_EN
0 CCM_CLKO2 disabled.
1 CCM_CLKO2 enabled.
23–21 Setting the divider of CCM_CLKO2
CLKO2_DIV
000 divide by 1
001 divide by 2
010 divide by 3
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
20–16 Selection of the clock to be generated on CCM_CLKO2
CLKO2_SEL

CCM_CCOSR field descriptions (continued)

Field Description
00000 mmdc_ch0_clk_root
00001 mmdc_ch1_clk_root
00010 usdhc4_clk_root
00100 gpu2d_axi_clk_root
00101 wrck_clk_root
00110 ecspi_clk_root
00111 gpu3d_axi_clk_root
01001 125M_clk_root
01010 arm_clk_root
01011 ipu1_hsp_clk_root
01100 ipu2_hsp_clk_root
01101 vdo_axi_clk_root
01110 osc_clk
01111 gpu2d_core_clk_root
10000 gpu3d_core_clk_root
10010 ssi1_clk_root
10011 ssi2_clk_root
10100 ssi3_clk_root
10101 gpu3d_shader_clk_root
10110 vpu_axi_clk_root
10111 can_clk_root
11000 ldb_di0_serial_clk_root
11001 ldb_di1_serial_clk_root
11010 esai_clk_root
11011 aclk_eim_slow_clk_root
11100 uart_clk_root
11101 spdif0_clk_root
11110 spdif1_clk_root
11111 hsi_tx_clk_root
Reserved
8 CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks
CLK_OUT_SEL
0 CCM_CLKO1 output drives CCM_CLKO1 clock
1 CCM_CLKO1 output drives CCM_CLKO2 clock
7 Enable of CCM_CLKO1 clock
CLKO1_EN
0 CCM_CLKO1 disabled.
1 CCM_CLKO1 enabled.
6–4 Setting the divider of CCM_CLKO1
CLKO1_DIV
000 divide by 1
001 divide by 2
010 divide by 3

CCM_CCOSR field descriptions (continued)

Field Description
011 divide by 4
100 divide by 5
101 divide by 6
110 divide by 7
111 divide by 8
CLKO1_SEL Selection of the clock to be generated on CCM_CLKO1
0000 pll3_sw_clk (this inputs has additional constant division /2)

0001 pll2_main_clk (this inputs has additional constant division /2)
0100 video_27M_clk_root
0101 axi_clk_root
0110 enfc_clk_root
0111 ipu1_di0_clk_root
1011 ahb_clk_root
1100 ipg_clk_root
1101 perclk_root
1110 ckil_sync_clk_root
1111 pll4_main_clk

18.6.22 CCM General Purpose Register (CCM_CGPR)
Fast PLL enable. Can be used to engage PLL faster after STOP mode, if 24MHz OSC
was active
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_MEM_CLK_LPM
R 0
FPL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFUSE_PROG_SUPPLY_
PMIC_DELAY_SCALER
MMDC_EXT_CLK_DIS
R 1 0 1
Reserved
GATE
W 1
Reset 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0
CCM_CGPR field descriptions

Field Description
Reserved
17
INT_MEM_CLK_ Control for the Deep Sleep signal to the Arm Platform memories with additional control logic based on the
LPM Arm WFI signal. Used to keep the Arm Platform memory clocks enabled if an interrupt is pending when
entering low power mode.
NOTE: This bit should always bet set when the CCM_CLPCR_LPM bits are set to 01(WAIT Mode) or 10
(STOP mode) without power gating. This bit does not have to be set for STOP mode entry.
0 Disable the clock to the Arm platform memories when entering Low Power Mode
1 Keep the clocks to the Arm platform memories enabled only if an interrupt is pending when entering
Low Power Modes (WAIT and STOP without power gating)
16 Fast PLL enable.
FPL

CCM_CGPR field descriptions (continued)

Field Description
0 Engage PLL enable default way.
1 Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if
24MHz OSC was active in low power mode.
Reserved
Reserved
Reserved
4 Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing
EFUSE_PROG_
SUPPLY_GATE 0 fuse programing supply voltage is gated off to the efuse module
1 allow fuse programing.
- Reserved
2 Disable external clock driver of MMDC during STOP mode
MMDC_EXT_
CLK_DIS 1 disable during stop mode
0 don't disable during stop mode.
1 Reserved. Keep default value set to '1' for proper operation.
-
0 Defines clock dividion of clock for stby_count (pmic delay counter)
PMIC_DELAY_
SCALER 0 clock is not divided
1 clock is divided /8
18.6.23 CCM Clock Gating Register 0 (CCM_CCGR0)

CG(i) bits CCGR 0-6
These bits are used to turn on/off the clock to each module independently. The following
table details the possible clock activity conditions for each module.
CGR value Clock Activity Description
00 Clock is off during all modes. Stop enter hardware handshake is disabled.
01 Clock is on in run mode, but off in WAIT and STOP modes
10 Not applicable (Reserved).
11 Clock is on during all modes, except STOP mode.
Module should be stopped, before set its bits to "0"; clocks to the module will be stopped
immediately.

The tables above show the register mappings for the different CGRs. The clock
connectivity table should be used to match the "CCM output affected" to the actual
clocks going into the modules.
The figure below represents the CCM Clock Gating Register 0 (CCM_CCGR0). The
clock gating Registers define the clock gating for power reduction of each clock (CG(i)
bits). There are 7 CGR registers. The number of registers required is according to the
number of peripherals in the system.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
CG15 CG14 CG13 CG12 CG11 CG10 CG9 CG8
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CCM_CCGR0 field descriptions

Field Description
31–30 Reserved
CG15
29–28 dtcp clocks (dtcp_clk_enable)
CG14
27–26 dcic2 clocks (dcic2_clk_enable)
CG13
25–24 dcic1 clocks (dcic1_clk_enable)
CG12
23–22 CPU debug clocks (arm_dbg_clk_enable)
CG11
21–20 can2_serial clock (can2_serial_clk_enable)
CG10
19–18 can2 clock (can2_clk_enable)
CG9
17–16 can1_serial clock (can1_serial_clk_enable)
CG8
15–14 can1 clock (can1_clk_enable)
CG7
13–12 caam_wrapper_ipg clock (caam_wrapper_ipg_enable)
CG6
11–10 caam_wrapper_aclk clock (caam_wrapper_aclk_enable)
CG5
9–8 caam_secure_mem clock (caam_secure_mem_clk_enable)
CG4
7–6 asrc clock (asrc_clk_enable)
CG3

CCM_CCGR0 field descriptions (continued)

Field Description
5–4 apbhdma hclk clock (apbhdma_hclk_enable)
CG2
3–2 aips_tz2 clocks (aips_tz2_clk_enable)
CG1
CG0 aips_tz1 clocks (aips_tz1_clk_enable)
The figure below represents the CCM Clock Gating Register 1(CCM_CCGR1). The
clock gating registers define the clock gating for power reduction of each clock (CG(i)
bits). There are 8 CGR registers. The number of registers required is determined by the
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 Reserved
CG15
29–28 Reserved
CG14
27–26 gpu3d clock (gpu3d_clk_enable)
CG13
25–24 gpu2d clock (gpu2d_clk_enable)
CG12
NOTE: GPU2D clock cannot be gated without gating OPENVG clock as well. Configure both CG bits
(CCM_CCGR1[CG12] and CCM_CCGR3[CG15]), to gate GPU2D.
23–22 gpt serial clock (gpt_serial_clk_enable)
CG11
21–20 gpt bus clock (gpt_clk_enable)
CG10
19–18 Reserved
CG9


Field Description
17–16 esai clocks (esai_clk_enable)
CG8
15–14 epit2 clocks (epit2_clk_enable)
CG7
13–12 epit1 clocks (epit1_clk_enable)
CG6
11–10 enet clock (enet_clk_enable)
CG5
9–8 ecspi5 clocks (ecspi5_clk_enable)
CG4
CG3
CG2
CG1
CG0 ecspi1 clocks (ecspi1_clk_enable)
clock gating registers define the clock gating for power reduction of each clock (CG(i)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 Reserved
CG15
29–28 Reserved
CG14


Field Description
27–26 ipsync_vdoa_ipg clocks (ipsync_vdoa_ipg_master_clk_enable)
CG13
25–24 ipsync_ip2apb_tzasc2_ipg clocks (ipsync_ip2apb_tzasc2_ipg_master_clk_enable)
CG12
23–22 ipsync_ip2apb_tzasc1_ipg clocks (ipsync_ip2apb_tzasc1_ipg_master_clk_enable)
CG11
21–20 ipmux3 clock (ipmux3_clk_enable)
CG10
CG9
CG8
15–14 iomux_ipt_clk_io clock (iomux_ipt_clk_io_enable)
CG7
13–12 OCOTP_CTRL clock (ocotp_clk_enable)
CG6
11–10 i2c3_serial clock (i2c3_serial_clk_enable)
CG5
CG4
CG3
5–4 hdmi_tx_isfrclk clock (hdmi_tx_isfrclk_enable)
CG2
3–2 Reserved
CG1
CG0 hdmi_tx_iahbclk, hdmi_tx_ihclk clock (hdmi_tx_enable)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 openvgaxiclk clock (openvgaxiclk_clk_root_enable)
CG15
NOTE: OPENVG clock cannot be gated without gating GPU2D clock as well. Configure both CG bits
(CCM_CCGR1[CG12] and CCM_CCGR3[CG15]) to gate OPENVG.
29–28 The OCRAM clock cannot be turned off when the CM cache is running on this device.
CG14
ocram clock(ocram_clk_enable)
27–26 Reserved
CG13
25–24 mmdc_core_ipg_clk_p0 clock (mmdc_core_ipg_clk_p0_enable)
CG12
23–22 Reserved
CG11
21–20 mmdc_core_aclk_fast_core_p0 clock (mmdc_core_aclk_fast_core_p0_enable)
CG10
19–18 mlb clock (mlb_clk_enable)
CG9
17–16 mipi_core_cfg clock (mipi_core_cfg_clk_enable)
CG8
15–14 ldb_di1 clock (ldb_di1_clk_enable)
CG7
13–12 ldb_di0 clock (ldb_di0_clk_enable)
CG6
11–10 ipu2_di1 clock and pre-clock (ipu2_ipu_di1_clk_enable)
CG5


Field Description
CG4
7–6 ipu2_ipu clock (ipu2_ipu_clk_enable)
CG3
CG2
CG1
CG0 ipu1_ipu clock (ipu1_ipu_clk_enable)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 rawnand_u_gpmi_input_apb clock (rawnand_u_gpmi_input_apb_clk_enable)
CG15
29–28 rawnand_u_gpmi_bch_input_gpmi_io clock (rawnand_u_gpmi_bch_input_gpmi_io_clk_enable)
CG14
27–26 rawnand_u_gpmi_bch_input_bch clock (rawnand_u_gpmi_bch_input_bch_clk_enable)
CG13
25–24 rawnand_u_bch_input_apb clock (rawnand_u_bch_input_apb_clk_enable)
CG12
23–22 pwm4 clocks (pwm4_clk_enable)
CG11
CG10


Field Description
CG9
CG8
15–14 pl301_mx6qper2_mainclk_enable (pl301_mx6qper2_mainclk_enable)
CG7
13–12
CG6 pl301_mx6qper1_bch clocks (pl301_mx6qper1_bchclk_enable)
NOTE: This gates bch_clk_root to sim_m fabric.
11–10 Reserved
CG5
9–8 pl301_mx6qfast1_s133 clock (pl301_mx6qfast1_s133clk_enable)
CG4
7–6 Reserved
CG3
5–4 Reserved.
CG2
3–2 Reserved.
CG1
CG0 pcie clock (pcie_root_enable)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


Field Description
31–30 Reserved
CG15
29–28 Reserved
CG14
27–26 uart_serial clock (uart_serial_clk_enable)
CG13
25–24 uart clock (uart_clk_enable)
CG12
23–22 ssi3 clocks (ssi3_clk_enable)
CG11
CG10
CG9
17–16 Reserved
CG8
15–14 spdif clock (spdif_clk_enable)
CG7
13–12 spba clock (spba_clk_enable)
CG6
11–10 Reserved
CG5
9–8 Reserved
CG4
7–6 sdma clock (sdma_clk_enable)
CG3
5–4 sata clock (sata_clk_enable)
CG2
3–2 Reserved
CG1
CG0 rom clock (rom_clk_enable)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
31–30 Reserved
CG15
29–28 Reserved
CG14
27–26 Reserved
CG13
25–24 Reserved
CG12
23–22 Reserved
CG11
21–20 Reserved
CG10
19–18 Reserved
CG9
17–16 Reserved
CG8
15–14 vpu clocks (vpu_clk_enable)
CG7
13–12 vdoaxiclk root clock (vdoaxiclk_clk_enable)
CG6
11–10 eim_slow clocks (eim_slow_clk_enable)
CG5
9–8 usdhc4 clocks (usdhc4_clk_enable)
CG4


Field Description
CG3
CG2
CG1
CG0 usboh3 clock (usboh3_clk_enable)
18.6.30 CCM Module Enable Overide Register (CCM_CMEOR)
The following figure represents the CCM Module Enable Override Register (CMEOR).
The CMEOR register contains bits to override the clock enable signal from the module.
This bit is applicable only for modules whose clock enable signals are used. The
following table provides its field descriptions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
mod_en_ov_can1_
mod_en_ov_can2_
R 1 1 1
cpi
cpi
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
mod_en_ov_gpu3d
mod_en_ov_gpu2d
mod_en_ov_vdoa
mod_en_ov_dap
mod_en_ov_vpu
mod_en_ov_epit
mod_en_ov_gpt
mod_en_usdhc
R 1 1
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CCM_CMEOR field descriptions

Field Description
Reserved

CCM Analog Memory Map/Register Definition
CCM_CMEOR field descriptions (continued)

Field Description
30 Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi'.
mod_en_ov_
can1_cpi 0 don't overide module enable signal
1 overide module enable signal
Reserved
28 Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi'.
mod_en_ov_
can2_cpi 0 don't override module enable signal
1 override module enable signal
Reserved
11 Overide clock enable signal from GPU3D - clock will not be gated based on GPU3D's signal.
mod_en_ov_
gpu3d 0 don't override module enable signal
10 Overide clock enable signal from GPU2D - clock will not be gated based on GPU's signal 'gpu2d_busy' .
mod_en_ov_
gpu2d 0 don't override module enable signal
9 Overide clock enable signal from VPU- clock will not be gated based on VPU's signal 'vpu_idle' .
mod_en_ov_vpu
0 don't override module enable signal
8 Overide clock enable signal from DAP- clock will not be gated based on DAP's signal 'dap_dbgen' .
mod_en_ov_dap
7 Overide clock enable signal from USDHC.
mod_en_usdhc
6 Overide clock enable signal from EPIT - clock will not be gated based on EPIT's signal 'ipg_enable_clk' .
mod_en_ov_epit
5 Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk' .
mod_en_ov_gpt
4 Overide clock enable signal from vdoa - clock will not be gated based on vdoa signal.
mod_en_ov_
vdoa 0 don't override module enable signal

18.7 CCM Analog Memory Map/Register Definition
This section describes the registers for the analog PLLs. The registers which have the
same description are grouped within {}. The register offsets for the various PLLs are:
• ARM PLL: {0h000, 0h004, 0h008, 0h00C}.
• USB1 PLL: {0h010, 0h014, 0h018, 0h01C}, {0h0F0, 0h0F4, 0h0F8, 0h0FC}.
• System PLL: {0h030, 0h034, 0h038, 0h03C}, 0h040, 0h050, 0h060, {0h100, 0h104,
0h108, 0h10C}.
• Audio / Video PLL: {0h070, 0h074, 0h078, 0h07C}, 0h080, 0h090, {0h0A0, 0h0A4,
0h0A8, 0h0AC}, 0h0B0, 0h0C0
CCM_ANALOG memory map
Absolute
Width Section/
(in bits) page
(hex)
Analog ARM PLL control Register
20C_8000 32 R/W 0001_3042h 18.7.1/730
(CCM_ANALOG_PLL_ARM)
20C_8004 32 R/W 0001_3042h 18.7.1/730
(CCM_ANALOG_PLL_ARM_SET)
20C_8008 32 R/W 0001_3042h 18.7.1/730
(CCM_ANALOG_PLL_ARM_CLR)
20C_800C 32 R/W 0001_3042h 18.7.1/730
(CCM_ANALOG_PLL_ARM_TOG)
Analog USB1 480MHz PLL Control Register
20C_8010 32 R/W 0001_2000h 18.7.2/732
(CCM_ANALOG_PLL_USB1)
20C_8014 32 R/W 0001_2000h 18.7.2/732
(CCM_ANALOG_PLL_USB1_SET)
20C_8018 32 R/W 0001_2000h 18.7.2/732
(CCM_ANALOG_PLL_USB1_CLR)
20C_801C 32 R/W 0001_2000h 18.7.2/732
(CCM_ANALOG_PLL_USB1_TOG)
20C_8020 32 R/W 0001_2000h 18.7.3/735
(CCM_ANALOG_PLL_USB2)
20C_8024 32 R/W 0001_2000h 18.7.3/735
(CCM_ANALOG_PLL_USB2_SET)
20C_8028 32 R/W 0001_2000h 18.7.3/735
(CCM_ANALOG_PLL_USB2_CLR)
20C_802C 32 R/W 0001_2000h 18.7.3/735
(CCM_ANALOG_PLL_USB2_TOG)
Analog System PLL Control Register
20C_8030 32 R/W 0001_3001h 18.7.4/737
(CCM_ANALOG_PLL_SYS)
20C_8034 32 R/W 0001_3001h 18.7.4/737
(CCM_ANALOG_PLL_SYS_SET)
20C_8038 32 R/W 0001_3001h 18.7.4/737
(CCM_ANALOG_PLL_SYS_CLR)

CCM_ANALOG memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
20C_803C 32 R/W 0001_3001h 18.7.4/737
(CCM_ANALOG_PLL_SYS_TOG)
528MHz System PLL Spread Spectrum Register
20C_8040 32 R/W 0000_0000h 18.7.5/739
(CCM_ANALOG_PLL_SYS_SS)
Numerator of 528MHz System PLL Fractional Loop Divider
20C_8050 32 R/W 0000_0000h 18.7.6/739
Register (CCM_ANALOG_PLL_SYS_NUM)
Denominator of 528MHz System PLL Fractional Loop
20C_8060 32 R/W 0000_0012h 18.7.7/740
Divider Register (CCM_ANALOG_PLL_SYS_DENOM)
Analog Audio PLL control Register
20C_8070 32 R/W 0001_1006h 18.7.8/741
(CCM_ANALOG_PLL_AUDIO)
20C_8074 32 R/W 0001_1006h 18.7.8/741
(CCM_ANALOG_PLL_AUDIO_SET)
20C_8078 32 R/W 0001_1006h 18.7.8/741
(CCM_ANALOG_PLL_AUDIO_CLR)
20C_807C 32 R/W 0001_1006h 18.7.8/741
(CCM_ANALOG_PLL_AUDIO_TOG)
Numerator of Audio PLL Fractional Loop Divider Register
20C_8080 32 R/W 05F5_E100h 18.7.9/743
(CCM_ANALOG_PLL_AUDIO_NUM)
Denominator of Audio PLL Fractional Loop Divider Register 18.7.10/
20C_8090 32 R/W 2964_619Ch
(CCM_ANALOG_PLL_AUDIO_DENOM) 743
Analog Video PLL control Register 18.7.11/
20C_80A0 32 R/W 0001_100Ch
(CCM_ANALOG_PLL_VIDEO) 745
20C_80A4 32 R/W 0001_100Ch
(CCM_ANALOG_PLL_VIDEO_SET) 745
20C_80A8 32 R/W 0001_100Ch
(CCM_ANALOG_PLL_VIDEO_CLR) 745
20C_80AC 32 R/W 0001_100Ch
(CCM_ANALOG_PLL_VIDEO_TOG) 745
Numerator of Video PLL Fractional Loop Divider Register 18.7.12/
20C_80B0 32 R/W 05F5_E100h
(CCM_ANALOG_PLL_VIDEO_NUM) 747
Denominator of Video PLL Fractional Loop Divider Register 18.7.13/
20C_80C0 32 R/W 10A2_4447h
(CCM_ANALOG_PLL_VIDEO_DENOM) 747
18.7.14/
20C_80D0 MLB PLL Control Register (CCM_ANALOG_PLL_MLB) 32 R/W 0001_0000h
748
MLB PLL Control Register 18.7.14/
20C_80D4 32 R/W 0001_0000h
(CCM_ANALOG_PLL_MLB_SET) 748
20C_80D8 32 R/W 0001_0000h
(CCM_ANALOG_PLL_MLB_CLR) 748
20C_80DC 32 R/W 0001_0000h
(CCM_ANALOG_PLL_MLB_TOG) 748
Analog ENET PLL Control Register 18.7.15/
20C_80E0 32 R/W 0001_1001h
(CCM_ANALOG_PLL_ENET) 750
20C_80E4 32 R/W 0001_1001h
(CCM_ANALOG_PLL_ENET_SET) 750

CCM_ANALOG memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
20C_80E8 32 R/W 0001_1001h
(CCM_ANALOG_PLL_ENET_CLR) 750
20C_80EC 32 R/W 0001_1001h
(CCM_ANALOG_PLL_ENET_TOG) 750
480MHz Clock (PLL3) Phase Fractional Divider Control 18.7.16/
20C_80F0 32 R/W 1311_100Ch
Register (CCM_ANALOG_PFD_480) 751
20C_80F4 32 R/W 1311_100Ch
Register (CCM_ANALOG_PFD_480_SET) 751
20C_80F8 32 R/W 1311_100Ch
Register (CCM_ANALOG_PFD_480_CLR) 751
20C_80FC 32 R/W 1311_100Ch
Register (CCM_ANALOG_PFD_480_TOG) 751
20C_8100 32 R/W 1018_101Bh
Register (CCM_ANALOG_PFD_528) 753
20C_8104 32 R/W 1018_101Bh
Register (CCM_ANALOG_PFD_528_SET) 753
20C_8108 32 R/W 1018_101Bh
Register (CCM_ANALOG_PFD_528_CLR) 753
20C_810C 32 R/W 1018_101Bh
Register (CCM_ANALOG_PFD_528_TOG) 753
18.7.18/
20C_8150 Miscellaneous Register 0 (CCM_ANALOG_MISC0) 32 R/W 0400_0000h
756
18.7.18/
20C_8154 Miscellaneous Register 0 (CCM_ANALOG_MISC0_SET) 32 R/W 0400_0000h
756
18.7.18/
20C_8158 Miscellaneous Register 0 (CCM_ANALOG_MISC0_CLR) 32 R/W 0400_0000h
756
18.7.18/
20C_815C Miscellaneous Register 0 (CCM_ANALOG_MISC0_TOG) 32 R/W 0400_0000h
756
18.7.19/
759
18.7.19/
759
18.7.19/
759
18.7.19/
759
18.7.20/
762
18.7.20/
762
18.7.20/
762
18.7.20/
762

18.7.1 Analog ARM PLL control Register

(CCM_ANALOG_PLL_ARMn)
The control register provides control for the system PLL.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
R -
LVDS_24MHZ_SEL
LVDS_SEL
PLL_SEL
BYPASS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
POWERDOWN
ENABLE
BYPASS_
Reserved DIV_SELECT
CLK_SRC
Reset 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0
CCM_ANALOG_PLL_ARMn field descriptions

Field Description
31 1 - PLL is currently locked.
LOCK
0 - PLL is not currently locked.

CCM_ANALOG_PLL_ARMn field descriptions (continued)

Field Description
30–20 Always set to zero (0).
-
19 Reserved
PLL_SEL
18 Analog Debug Bit
LVDS_24MHZ_
SEL
17 Analog Debug Bit
LVDS_SEL
16 Bypass the PLL.
BYPASS
15–14
BYPASS_CLK_ Determines the bypass source.
SRC
NOTE: Changing the Bypass clock source also changes the PLL reference clock source.
0x0 REF_CLK_24M — Select the 24MHz oscillator as source.

0x1 CLK1 — Select the CLK1_N / CLK1_P as source.
0x3 XOR — Select the XOR of CLK1_N / CLK1_P and CLK2_N / CLK2_P as source.
13 Enable the clock output.
ENABLE
12 Powers down the PLL.
POWERDOWN
- Reserved.
DIV_SELECT This field controls the PLL loop divider. Valid range for divider value: 54-108. Fout = Fin * div_select/2.0.

18.7.2 Analog USB1 480MHz PLL Control Register

(CCM_ANALOG_PLL_USB1n)
The control register provides control for USBPHY0 480MHz PLL.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
R -
BYPASS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R - -
EN_USB_CLKS
DIV_SELECT
Reserved
ENABLE
POWER
BYPASS_
CLK_SRC
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_PLL_USB1n field descriptions

Field Description
LOCK
-
16 Bypass the PLL.
BYPASS
15–14 Determines the bypass source.
BYPASS_CLK_
SRC 0x0 REF_CLK_24M — Select the 24MHz oscillator as source.
13 Enable the PLL clock output.
ENABLE
12 Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.
POWER
-
6 Powers the 9-phase PLL outputs for USBPHYn. Additionally, the UTMI clock gate must be deasserted in
EN_USB_CLKS the USBPHYn to enable USBn operation (clear CLKGATE bit in USBPHYn_CTRL). This bit will be set
automatically when USBPHYn remote wakeup event occurs.
0 PLL outputs for USBPHYn off.

1 PLL outputs for USBPHYn on.
-

CCM_ANALOG_PLL_USB1n field descriptions (continued)

Field Description
1 This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.
DIV_SELECT
- Reserved.

18.7.3 Analog USB2 480MHz PLL Control Register

(CCM_ANALOG_PLL_USB2n)
The control register provides control for USBPHY1 480MHz PLL.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
R -
BYPASS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R - -
EN_USB_CLKS
DIV_SELECT
Reserved
ENABLE
POWER
BYPASS_
CLK_SRC
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_PLL_USB2n field descriptions

Field Description
LOCK
-
16 Bypass the PLL.
BYPASS
BYPASS_CLK_
13 Enable the PLL clock output.
ENABLE
12 Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.
POWER
-
6 0: 8-phase PLL outputs for USBPHY1 are powered down. If set to 1, 8-phase PLL outputs for USBPHY1
EN_USB_CLKS are powered up. Additionally, the utmi clock gate must be deasserted in the USBPHY1 to enable USB0
operation (clear CLKGATE bit in USBPHY1_CTRL).This bit will be set automatically when USBPHY1
remote wakeup event happens.
-
DIV_SELECT

CCM_ANALOG_PLL_USB2n field descriptions (continued)

Field Description
- Reserved.
18.7.4 Analog System PLL Control Register

(CCM_ANALOG_PLL_SYSn)
The control register provides control for the 528MHz PLL.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
R -
BYPASS
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R -
POWERDOWN
DIV_SELECT
ENABLE
BYPASS_
Reserved
CLK_SRC
Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1

CCM_ANALOG_PLL_SYSn field descriptions

Field Description
31 1 - PLL is currently locked; 0 - PLL is not currently locked.
LOCK
-
- Reserved
16 Bypass the PLL.
BYPASS
BYPASS_CLK_
13 Enable PLL output
ENABLE
POWERDOWN
- Reserved.
-
DIV_SELECT

18.7.5 528MHz System PLL Spread Spectrum Register

(CCM_ANALOG_PLL_SYS_SS)
This register contains the 528MHz PLL spread spectrum controls.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ENABLE
STEP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_PLL_SYS_SS field descriptions

Field Description
31–16 Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.
STOP
15 Enable bit
ENABLE
0 — Spread spectrum modulation disabled
1 — Soread spectrum modulation enabled
STEP Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.
18.7.6 Numerator of 528MHz System PLL Fractional Loop Divider

Register (CCM_ANALOG_PLL_SYS_NUM)
This register contains the numerator of 528MHz PLL fractional loop divider (signed
number).
Absolute value should be less than denominator.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R -
A
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_PLL_SYS_NUM field descriptions

Field Description
-
A 30 bit numerator (A) of fractional loop divider (signed integer).
18.7.7 Denominator of 528MHz System PLL Fractional Loop

Divider Register (CCM_ANALOG_PLL_SYS_DENOM)
This register contains the denominator of 528MHz PLL fractional loop divider.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R -
B
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
CCM_ANALOG_PLL_SYS_DENOM field descriptions

Field Description
-
B 30 bit denominator (B) of fractional loop divider (unsigned integer).

18.7.8 Analog Audio PLL control Register

(CCM_ANALOG_PLL_AUDIOn)
The control register provides control for the audio PLL.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
R -
Reserved
BYPASS
POST_DIV_
Reserved
SELECT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POWERDOWN
ENABLE
BYPASS_
Reserved DIV_SELECT
CLK_SRC
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0
CCM_ANALOG_PLL_AUDIOn field descriptions

Field Description
LOCK
-
- Reserved
20–19 These bits implement a divider after the PLL, but before the enable and bypass mux.
POST_DIV_
SELECT 00 — Divide by 4.
01 — Divide by 2.
10 — Divide by 1.
11 — Reserved
- Revsered
16 Bypass the PLL.
BYPASS
BYPASS_CLK_
ENABLE
POWERDOWN

CCM_ANALOG_PLL_AUDIOn field descriptions (continued)

Field Description
- Reserved.
DIV_SELECT This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.
18.7.9 Numerator of Audio PLL Fractional Loop Divider Register

(CCM_ANALOG_PLL_AUDIO_NUM)
This register contains the numerator (A) of Audio PLL fractional loop divider (Signed
number).
Absolute value should be less than denominator
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R -
A
W
Reset 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0
CCM_ANALOG_PLL_AUDIO_NUM field descriptions

Field Description
-
A 30 bit numerator of fractional loop divider.
18.7.10 Denominator of Audio PLL Fractional Loop Divider

Register (CCM_ANALOG_PLL_AUDIO_DENOM)
This register contains the denominator (B) of Audio PLL fractional loop divider
(unsigned number).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R -
B
W
Reset 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0

CCM_ANALOG_PLL_AUDIO_DENOM field descriptions

Field Description
-
B 30 bit denominator of fractional loop divider.

18.7.11 Analog Video PLL control Register

(CCM_ANALOG_PLL_VIDEOn)
The control register provides control for the Video PLL.

Address: 20C_8000h base + A0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
R -
Reserved
BYPASS
POST_DIV_
Reserved
SELECT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POWERDOWN
ENABLE
BYPASS_
Reserved DIV_SELECT
CLK_SRC
Reset 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0
CCM_ANALOG_PLL_VIDEOn field descriptions

Field Description
31 1 - PLL is currently locked;
LOCK
-
- Revserved
20–19 These bits implement a divider after the PLL, but before the enable and bypass mux.
POST_DIV_
SELECT 00 — Divide by 4.
01 — Divide by 2.
10 — Divide by 1.
11 — Reserved
- Reserved
16 Bypass the PLL.
BYPASS
BYPASS_CLK_
ENABLE
POWERDOWN

CCM_ANALOG_PLL_VIDEOn field descriptions (continued)

Field Description
- Reserved.
DIV_SELECT This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.
18.7.12 Numerator of Video PLL Fractional Loop Divider Register

(CCM_ANALOG_PLL_VIDEO_NUM)
This register contains the numerator (A) of Video PLL fractional loop divider (signed
number).
Absolute value should be less than denominator
Address: 20C_8000h base + B0h offset = 20C_80B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R -
A
W
Reset 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0
CCM_ANALOG_PLL_VIDEO_NUM field descriptions

Field Description
-
A 30 bit numerator of fractional loop divider (signed number). The absolute value should be less than
denominator.
18.7.13 Denominator of Video PLL Fractional Loop Divider

Register (CCM_ANALOG_PLL_VIDEO_DENOM)
This register contains the denominator (B) of Video PLL fractional loop divider
(unsigned number).
Address: 20C_8000h base + C0h offset = 20C_80C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R -
B
W
Reset 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1

CCM_ANALOG_PLL_VIDEO_DENOM field descriptions

Field Description
-
B 30 bit denominator of fractional loop divider.
18.7.14 MLB PLL Control Register (CCM_ANALOG_PLL_MLBn)
This register defines the control bits for the MLB PLL.
Address: 20C_8000h base + D0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
BYPASS
MLB_FLT_RES_ RX_CLK_DELAY_
Reserved VDDD_DELAY_CFG VDDA_DELAY_CFG
CFG CFG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HOLD_RING_OFF
Reserved PHASE_SEL Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ANALOG_PLL_MLBn field descriptions

Field Description
31 Lock bit
LOCK
0 PLL is not currently locked
1 PLL is currently locked.
- Reserved.
28–26 Configure the filter resistor for different divider ratio of MLB PLL.
MLB_FLT_RES_
CFG
25–23 Configure the phase delay of the MLB PLL RX Clock.
RX_CLK_
DELAY_CFG
22–20 Configure the phase delay of the MLB PLL by adjusting the delay line in core Vdd poser domain.
VDDD_DELAY_
CFG
19–17 Configure the phase delay of the MLB PLL by adjusting the delay line in Vddio power domain.
VDDA_DELAY_
CFG
16 Bypass the PLL.
BYPASS
- Reserved.
13–12 Analog debut bit.
PHASE_SEL
11 Analog debug bit.
HOLD_RING_
OFF
Reserved.

18.7.15 Analog ENET PLL Control Register

(CCM_ANALOG_PLL_ENETn)
The control register provides control for the ENET PLL.

Address: 20C_8000h base + E0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
R -
ENABLE_100M
ENABLE_125M
BYPASS
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R -
POWERDOWN
DIV_SELECT
ENABLE
BYPASS_
Reserved
CLK_SRC
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
CCM_ANALOG_PLL_ENETn field descriptions

Field Description
31 1 - PLL is currently locked; 0 - PLL is not currently locked.
LOCK
-
20 Enables an offset in the phase frequency detector.
ENABLE_100M

CCM_ANALOG_PLL_ENETn field descriptions (continued)

Field Description
19 Enables an offset in the phase frequency detector.
ENABLE_125M
- Reserved
16 Bypass the PLL.
BYPASS
BYPASS_CLK_
13 Enable the ethernet clock output.
ENABLE
POWERDOWN
- Reserved.
-
DIV_SELECT Controls the frequency of the ethernet reference clock.00 - 25MHz; 01 - 50MHz; 10 - 100MHz (not 50%
duty cycle); 11 - 125MHz;
18.7.16 480MHz Clock (PLL3) Phase Fractional Divider Control

Register (CCM_ANALOG_PFD_480n)
The PFD_480 control register provides control for PFD clock generation.
This register controls the 4-phase fractional clock dividers. The fractional clock
frequencies are a product of the values in these registers.

Address: 20C_8000h base + F0h offset + (4d × i), where i=0d to 3d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFD3_STABLE
PFD2_STABLE
R
PFD3_CLKGATE
PFD2_CLKGATE
PFD3_FRAC PFD2_FRAC
Reset 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFD1_STABLE
PFD0_STABLE
R
PFD1_CLKGATE
PFD0_CLKGATE
PFD1_FRAC PFD0_FRAC
Reset 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0
CCM_ANALOG_PFD_480n field descriptions

Field Description
31 IO Clock Gate. If set to 1, the 3rd fractional divider clock (reference ref_pfd3) is off (power savings). 0:
PFD3_CLKGATE ref_pfd3 fractional divider clock is enabled.
Need to assert this bit before PLL is powered down
30 This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
PFD3_STABLE stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit,

CCM_ANALOG_PFD_480n field descriptions (continued)

Field Description
program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the
value will not invert when the fractional divider is taken out of or placed into clock-gated state.
29–24 This field controls the fractional divide value. The resulting frequency shall be 480*18/PFD3_FRAC where
PFD3_FRAC PFD3_FRAC is in the range 12-35.
23 IO Clock Gate. If set to 1, the IO fractional divider clock (reference ref_pfd2) is off (power savings). 0:
7 If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings). 0: ref_pfd0 fractional
PFD0_CLKGATE divider clock is enabled.
PFD0_FRAC This field controls the fractional divide value. The resulting frequency shall be 480*18/PFD0_FRAC where
PFD0_FRAC is in the range 12-35.
18.7.17 528MHz Clock (PLL2) Phase Fractional Divider Control

Register (CCM_ANALOG_PFD_528n)
The PFD_528 control register provides control for PFD clock generation.
This register controls the 3-phase fractional clock dividers. The fractional clock
frequencies are a product of the values in these registers.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFD2_STABLE
R
PFD2_CLKGATE
Reserved PFD2_FRAC
Reset 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFD1_STABLE
PFD0_STABLE
R
PFD1_CLKGATE
PFD0_CLKGATE
PFD1_FRAC PFD0_FRAC
Reset 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1
CCM_ANALOG_PFD_528n field descriptions

Field Description
- Reserved
Need to assert this bit before PLL powered down

CCM_ANALOG_PFD_528n field descriptions (continued)

Field Description
7 If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings). 0: ref_pfd0 fractional
PFD0_CLKGATE divider clock is enabled.
PFD0_FRAC This field controls the fractional divide value. The resulting frequency shall be 528*18/PFD0_FRAC where
PFD0_FRAC is in the range 12-35.

18.7.18 Miscellaneous Register 0 (CCM_ANALOG_MISC0n)
This register defines the control and status bits for miscellaneous analog blocks.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSC_XTALOK
WBCP_VPW_THRESH
R
OSC_XTALOK_EN
CLKGATE_CTRL
Reserved CLKGATE_DELAY Reserved
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFTOP_SELFBIASOFF
STOP_MODE_CONFIG
R
REFTOP_VBGUP
REFTOP_PWD
Reserved
OSC_I Reserved REFTOP_VBGADJ Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ANALOG_MISC0n field descriptions

Field Description
-
28–26
CLKGATE_ This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the
DELAY digital logic inside the analog block.
NOTE: Do not change the field during a low power event. This is not a field that the user would normally
need to modify.
NOTE: Not related to CCM. See Crystal Oscillator (XTALOSC)
000 0.5ms
001 1.0ms
010 2.0ms
011 3.0ms
100 4.0ms
101 5.0ms
110 6.0ms
111 7.0ms
25
CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital
logic in the analog block.
NOTE: Do not change the field during a low power event. This is not a field that the user would normally
need to modify.
0 ALLOW_AUTO_GATE — Allow the logic to automatically gate the clock when the XTAL is powered
down.
1 NO_AUTO_GATE — Prevent the logic from ever gating off the clock.
- Always set to zero.
19–18
WBCP_VPW_ This signal alters the voltage that the pwell is charged pumped to.
THRESH
NOTE: Not related to CCM. See Power Management Unit (PMU)
00 NOMINAL_BIAS — Nominal output pwell bias voltage.

01 PLUS_25MV — Increase pwell output voltage by 25mV.
10 MINUS_25MV — Decrease pwell output pwell voltage by 25mV.
11 MINUS_50MV — Decrease pwell output pwell voltage by 50mV.
17
OSC_XTALOK_ This bit enables the detector that signals when the 24MHz crystal oscillator is stable.
EN
16
OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable. Generated from a timer and
active detection of the actual frequency.

CCM_ANALOG_MISC0n field descriptions (continued)

Field Description
15–14
OSC_I This field determines the bias current in the 24MHz oscillator. The aim is to start up with the highest bias
current, which can be decreased after startup if it is determined to be acceptable.
00 NOMINAL — Nominal
01 MINUS_12_5_PERCENT — Decrease current by 12.5%
10 MINUS_25_PERCENT — Decrease current by 25.0%
11 MINUS_37_5_PERCENT — Decrease current by 37.5%
Reserved Reserved
12 Configure the analog behavior in stop mode.
STOP_MODE_
CONFIG 0x0 DEEP — Deep Stop Mode - 0x0 All analog except RTC powered down on Stop mode assertion
0x1 LIGHT — Light Stop Mode - 0x1 All the analog domain except the LDO_1P1, LDO_2P5, and PLL3
is powered down on STOP mode assertion. If required the CCM can be configured not to power
down the oscillator (XTALOSC). PLL3 can be disabled with register settings if desired.
- Reserved
7
REFTOP_ Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.
VBGUP
6–4
REFTOP_ NOTE: Not related to CCM. See Power Management Unit (PMU)
VBGADJ
000 Nominal VBG
001 VBG+0.78%
010 VBG+1.56%
011 VBG+2.34%
100 VBG-0.78%
101 VBG-1.56%
110 VBG-2.34%
111 VBG-3.12%
3
REFTOP_ Control bit to disable the self-bias circuit in the analog bandgap. The self-bias circuit is used by the
SELFBIASOFF bandgap during startup. This bit should be set after the bandgap has stabilized and is necessary for best
noise performance of analog blocks using the outputs of the bandgap.
NOTE: Value should be returned to zero before removing vddhigh_in or asserting bit 0 of this register
(REFTOP_PWD) to assure proper restart of the circuit.
0 Uses coarse bias currents for startup

1 Uses bandgap-based bias currents for best performance.
-
0
REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry.


Field Description
NOTE: A note of caution, the bandgap is necessary for correct operation of most of the LDO, PLL, and
other analog functions on the die.
This register defines the control and status bits for miscellaneous analog blocks. The
LVDS1 and LVDS2 controls below control the behavior of the anaclk1/1b and
anaclk2/2b LVDS IO's.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRQ_TEMPSENSE
IRQ_ANA_BO
IRQ_DIG_BO
Reserved
W w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LVDSCLK2_OBEN
LVDSCLK1_OBEN
LVDSCLK2_IBEN
LVDSCLK1_IBEN
Reserved LVDS2_CLK_SEL LVDS1_CLK_SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Field Description
31
IRQ_DIG_BO This status bit is set to one when when any of the digital regulator brownout interrupts assert. Check the
regulator status bits to discover which regulator interrupt asserted.

30
IRQ_ANA_BO This status bit is set to one when when any of the analog regulator brownout interrupts assert. Check the
regulator status bits to discover which regulator interrupt asserted.

29
IRQ_ This status bit is set to one when when the temperature sensor interrupt asserts.
TEMPSENSE
NOTE: Not related to CCM. See Temperature Monitor (TEMPMON)
-
13 This enables the LVDS input buffer for anaclk2/2b. Do not enable input and output buffers simultaneously.
LVDSCLK2_
IBEN
12 This enables the LVDS input buffer for anaclk1/1b. Do not enable input and output buffers simultaneously.
LVDSCLK1_
IBEN
11 This enables the LVDS output buffer for anaclk2/2b. Do not enable input and output buffers
LVDSCLK2_ simultaneously.
OBEN
10 This enables the LVDS output buffer for anaclk1/1b. Do not enable input and output buffers
LVDSCLK1_ simultaneously.
OBEN
9–5 This field selects the clk to be routed to anaclk2/2b.
LVDS2_CLK_
SEL 00000 ARM_PLL — Arm PLL
00001 SYS_PLL — System PLL
00010 PFD4 — ref_pfd4_clk == pll2_pfd0_clk
00110 AUDIO_PLL — Audio PLL
00111 VIDEO_PLL — Video PLL
01000 MLB_PLL — MLB PLL
01001 ETHERNET_REF — ethernet ref clock (ENET_PLL)
01010 PCIE_REF — PCIe ref clock (125M)
01011 SATA_REF — SATA ref clock (100M)
01100 USB1_PLL — USB1 PLL clock
10010 XTAL — xtal (24M)


Field Description
10011 LVDS1 — LVDS1 (loopback)
10100 LVDS2 — LVDS2 (not useful)
10101 to 11111 ref_pfd7_clk == pll2_pfd3_clk
LVDS1_CLK_ This field selects the clk to be routed to anaclk1/1b.
SEL
00000 ARM_PLL — Arm PLL
00001 SYS_PLL — System PLL
00110 AUDIO_PLL — Audio PLL
00111 VIDEO_PLL — Video PLL
01000 MLB_PLL — MLB PLL
01001 ETHERNET_REF — ethernet ref clock (ENET_PLL)
01010 PCIE_REF — PCIe ref clock (125M)
01011 SATA_REF — SATA ref clock (100M)
10010 XTAL — xtal (24M)
10011 LVDS1 — LVDS1 (loopback)
10100 LVDS2 — LVDS2 (not useful)
10101 to 11111 ref_pfd7_clk == pll2_pfd3_clk

This register defines the control for miscellaneous analog blocks.

NOTE
This register is shared with PMU.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REG2_BO_STATUS
REG2_OK
R REG2_BO_OFFSET
REG2_ENABLE_BO
REG2_STEP_TIME
REG1_STEP_TIME
REG0_STEP_TIME
Reserved
Reserved
VIDEO_DIV
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REG1_BO_STATUS
REG0_BO_STATUS
REG1_OK
REG0_OK
R REG1_BO_OFFSET REG0_BO_OFFSET
REG1_ENABLE_BO
REG0_ENABLE_BO
PLL3_DISABLE
Reserved
Reserved
Reserved
W
Reset 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1

Field Description
31–30 Post-divider for video. The output clock of the video PLL should be gated prior to changing this divider to
VIDEO_DIV prevent glitches. This divider is feed by PLL_VIDEOn[POST_DIV_SELECT] to achieve division ratios
of /1, /2, /4.
00 divide by 1 (Default)
01 divide by 2
10 divide by 1
11 divide by 4
29–28
REG2_STEP_ Number of clock periods (24MHz clock).
TIME
00 64_CLOCKS — 64
01 128_CLOCKS — 128
10 256_CLOCKS — 256
11 512_CLOCKS — 512
27–26
TIME


Field Description
00 64_CLOCKS — 64
01 128_CLOCKS — 128
10 256_CLOCKS — 256
11 512_CLOCKS — 512
25–24
TIME
00 64_CLOCKS — 64
01 128_CLOCKS — 128
10 256_CLOCKS — 256
11 512_CLOCKS — 512
- Reserved
22
REG2_OK Signals that the voltage is above the brownout level for the SOC supply. 1 = regulator output >
brownout_target

21
REG2_ENABLE_ Enables the brownout detection.
BO
-
19
REG2_BO_ Reg2 brownout status bit.
STATUS
18–16
REG2_BO_ This field defines the brown out voltage offset for the xPU power domain. IRQ_DIG_BO is also asserted.
OFFSET Single-bit increments reflect 25mV brownout voltage steps. The reset brown-offset is 175mV below the
programmed target code. Brownout target = OUTPUT_TRG - BO_OFFSET. Some steps may be
irrelevant because of input supply limitations or load operation.
100 Brownout offset = 0.100V

-
14
REG1_OK GPU/VPU supply

13
BO


Field Description
-
11
STATUS
1 Brownout, supply is below target minus brownout offset.

10–8
REG1_BO_ This field defines the brown out voltage offset for the xPU power domain. IRQ_DIG_BO is also asserted.
OFFSET Single-bit increments reflect 25mV brownout voltage steps. The reset brown-offset is 175mV below the
programmed target code. Brownout target = OUTPUT_TRG - BO_OFFSET. Some steps may be
irrelevant because of input supply limitations or load operation.

7 When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals
PLL3_DISABLE require the USB PLL3 clock when the SoC is not in low power mode. A user needs to set this bit if they
want to optionally disable PLL3 while the SoC is not in any low power mode to save power. When the
system does go into low power mode this bit setting would not have any affect.
NOTE: When USB is in low power suspend mode users would need to ensure PLL3 is not being used
before setting this bit in RUN mode. Please refer to the correct PLL disabling procedure in
Disabling / Enabling PLLs
0 PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
1 PLL3 can be disabled when the SoC is not in any low power mode
6
REG0_OK Arm supply

5
BO
-
3
STATUS
1 Brownout, supply is below target minus brownout offset.

REG0_BO_
OFFSET This field defines the brown out voltage offset for the CORE power domain. IRQ_DIG_BO is also
asserted. Single-bit increments reflect 25mV brownout voltage steps. Some steps may be irrelevant
because of input supply limitations or load operation.



Chapter 19
MIPI CSI to IPU Gasket (CSI2IPU)
19.1 Overview
The CSI2IPU gasket is a digital core that functions as a gasket interface between the
MIPI CSI-2 host controller and the IPU system. This facilitates communication between
a MIPI CSI-2 compliant camera sensor and IPU (the image processing unit). The gasket's
main functions are to synchronize the CSI-2 input 32-bit data bus with the 16-bit data bus
and to separate the four virtual channels.
The following block diagram shows the CSI2IPU gasket's position in the system as part
of the CSI to IPU connectivity.
Video
Sources
i.MX 6 Series
Parallel 0
mux
VC 0 CSI0
IPU1
CSI1
VC 1
MIPI/CSI-2 CSI2IPU
MIPI/CSI-2 Receiver gasket
CSI0
VC 2
IPU2
VC 3
mux
CSI1
Parallel 1
Figure 19-1. CSI2IPU gasket connectivity

Overview
19.1.1 CSI2IPU feature summary

The CSI2IPU gasket supports:
• Up to 4 virtual channels of MIPI CSI-2 host controller
• All data types of the MIPI Alliance Standard for Camera Serial Interface (CSI)
• Dynamically configurable pixel clock gating or non-gating for the IPU module
• Dynamically configurable RGB444 and YUV422 data format for the IPU module
• A software reset to reset the program during operation
19.1.2 CSI2IPU architectural description

The following figure shows the overall architecture of the CSI2IPU gasket.
Clk_data
Header_en
Virtual_channel
Csi0/1/2/3_data
Data_type [15:0]
Csi0/1/2/3_mct_di
Word_count FIFO_WR Async_FIFO FIFO_RD GST_OUT
Csi0/1/2/3_data_en
ecc
Data_en Csi0/1/2/3_pix_clk
Csi_data Csi0/1/2/3_vsync
[31:0]
Bytes_en Csi0/1/2/3_hsync
vvalid Register
Control
hvalid
dvalid
Figure 19-2. CSI2IPU gasket architecture
The main blocks are:

• FIFO WRITE—Responsible for receiving the CSI-2 host input signals and
integrating them into a wr_data[46:0] bus
• ASYNC FIFO—Used to synchronize the wr_data to the read clock domain. It also
generates FIFO full and empty signals.
• FIFO READ—Responsible for reading FIFO output and changing the 32-bit data bus
to the 16-bit data bus.

Chapter 19 MIPI CSI to IPU Gasket (CSI2IPU)
• GST OUT—Generates output data according to the format controlled by the register
bank.
• REGISTER CONTROL—register bank used to control the GST OUT block.
19.2 CSI2IPU signals

The following tables describe the CSI2IPU gasket's input and output signals.
Table 19-1. Input signals to CSI2IPU
Signal Description
clk_data Clock input for the CSI host controller
header_en Shows that the header data at the input (signals virtual_channel, data_type,
word_count, and ecc) is valid for the packet being transferred. This signal stays HIGH
during the complete packet transfer.
virtual_channel[1:0] Virtual channel identifier value
• 00— VC0
• 01—VC1
• 10—VC2
• 11—VC3
data_type[5:0] • 00h–07h—Synchronization short packet data types
• 08h–0Fh—Generic short packet data types
• 10h–17h—Generic long packet data types
• 18h–1Fh—YUV data
• 20h–27h—RGB data
• 28h–2Fh—RAW data
• 30h– 37h—User defined byte-based data
• 38h–3Fh—Reserved
word_count[15:0] 16-bit word count information from the packet header
ecc[7:0] 8-bit error correction code for the packet header
data_en Shows that new payload data is present at the input (signals csi_data and bytes_en).
This signal is only asserted when receiving long packets. Note that the signal
header_en is also asserted when data_en is asserted.
bytes_en[1:0] Shows how may bytes are in the csi_data output signal
• 00 = 1 valid byte in csi_data[7:0]
• 01 = 2 valid bytes in csi_data[15:0]
vvalid[3:0] This signal is asserted when a Frame Start is detected and de-asserted when a Frame
End is detected. Each virtual channel has one valid signal.
• vvalid[0]—vvalid for Virtual Channel 0
hvalid[3:0] This signal is asserted when a Line Start is detected and de-asserted when a Line End
is detected. Line Start and Line End are optional; when they are not available, hvalid
has the same behavior as dvalid. Each virtual channel has one valid signal.
• hvalid[0]—hvalid for Virtual Channel 0

Timing interface
Table 19-1. Input signals to CSI2IPU (continued)

Signal Description
dvalid[3:0] Used to signal when valid data is available
csi_data_out[31:0] Payload data
hw_resetn System hardware reset
sft_resetn System software reset from top module
gst_clk_sel • 0—Gating clock mode
• 1—Non-gating clock mode
gst_rgb444_fm Rgb444 output format select
• 0—{4’h0,r4g4b4}
• 1—{r4,1’b0,g4,1’b0,b4,1’b0}
gst_yuv422_8bit_fm Yuv422 output format select
• 0—output YUYV
• 1—output UYVY
ccm_pixel_clk Reading clock from CCM
Table 19-2. CSI2IPU output signals to IPU

Signal Description
csin, 1 _data[15:0] Virtual channel n1 CSI data
csin1 _mct_di[7:0] Virtual channel n1 {Channel_ID[1:0],Data type[5:0]}
csin1 _data_en virtual channel n1 data enable signal
csin1 _pix_clk virtual channel n1 pixel clock signal clock
csin1 _vsync virtual channel n1 vertical synchronism signal(Frame start)
csin1 _hsync virtual channel n1 horizontal synchronism signal
csin1 _Byte_en virtual channel n1 byte enable
• 0–[7:0] valid
• 1:[15:0] valid
1. n = 0 - 3

19.3 Timing interface

The following figure shows the timing for the image data interface.
pix_clk
data_en
vsync
hsync
csix_data
Figure 19-3. Image data interface
19.4 Payload data output formats

The following figures illustrate the formats for the payload data output.
Bytes3 Bytes2 Bytes1 Bytes0
32bits data bus

Bytes1 Bytes0
Bytes3 Bytes2
16bits data bus
Figure 19-4. General/arbitrary data reception

Payload data output formats
B1 R0 G0 B0
G2 B2 R1 G1
32bits data bus G0 B0
B1 R0
16bits data bus R1 G1
G2 B2
Figure 19-5. RGB888 data reception
R1 G1 B1 R0 G0 B0
G3 B3 R2 G2 B2 R1
32bits data bus R0 G0 B0
R1 G1 B1 R0
16bits data bus
G2 B2 R1
G3 B3 R2
R1 G1 B1 R0 G0 B0
32bits data bus

R0 G0 B0

R1 G1 B1 R0 G0 B0
0 0

0
R1 G1 B1
16bits data bus 0
R1 G1 B1 R0 G0 B0
x x x x x x x x
32bits data bus

R0 G0 B0
x x x x

x x x x
Y2 VI Y1 U1
Y4 V3 Y3 U3
32bits data bus Y1 U1
Y2 V1
Y3 U3
16bits data bus
Y4 V3
Figure 19-10. YUV422-8 data reception

Y2[9:2] V1[9:2] Y1[9:2] U1[9:2]
V3[9:2] Y3[9:2] U3[9:2] Y2[1:0],V1[1:0],Y1[1:0],U1[1:0]
32bits data bus Y1[9:2] U1[9:2]
Y2[9:2] V1[9:2]
16bits data bus

U3[9:2] Y2[1:0], V1[1:0], Y1[1:0], U1[1:O]
V3[9:2] Y3[9:2]
U1 Y1 Y2 U3
Y3 Y4 U5 Y5
32bits data bus (Odd Line) U1 Y1
Y2 U3
16bits data bus (Odd Line)
Y3 Y4
U5 Y5
V1 Y1 Y2 V3
Y3 Y4 V5 Y5
32bits data bus (Even Line)

V1 Y1
Y2 V3

Y3 Y4
V5 Y5
Figure 19-12. YUV420-8 (legacy) data reception

Y4 Y3 Y2 Y1
Y8 Y7 Y6 Y5
32bits data bus (Odd Line) Y2 Y1
Y4 Y3
Y6 Y5
Y8 Y7
Y2 V1 Y1 U1
Y4 V3 Y3 U3
32bits data bus (Even Line) Y1 U1
Y2 V1

Y3 U3
Y4 V3

Y4[9:2] Y3[9:2] Y2[9:2] Y1[9:2]
Y7[9:2] Y6[9:2] Y5[9:2] Y4[1:0],Y3[1:0],Y2[1:0],Y1[1:0]
32bits data bus (Odd Line) Y4[9:2] Y3[9:2]
Y5[9:2] Y3[9:2]

Y5[9:2] Y4[1:0], Y3[1:0], Y2[1:0], Y1[1:O]
Y7[9:2] Y6[9:2]
Y2[9:2] V1[9:2] Y1[9:2] U1[9:2]
V3[9:2] Y3[9:2] U3[9:2] Y2[1:0],V1[1:0],Y1[1:0],U1[1:0]
32bits data bus (Odd Line) Y1[9:2] U1[9:2]
Y2[9:2] V1[9:2]

U3[9:2] Y2[1:0], V1[1:0], Y1[1:0], U1[1:O]
V3[9:2] Y3[9:2]
P6 P5 P4 P3 P2 P1
P11 P10 P9 P8 P7 P6
P3 P2 P1
32bits data bus
P6 P5 P4 P3
16bits data bus P8 P7 P6
P11 P10 P9
Figure 19-15. RAW-6 data reception

P5 P4 P3 P2 P1
P10 P9 P8 P7 P6 P5
P3 P2 P1
32bits data bus
P5 P4 P3
16bits data bus P7 P6 P5
P10 P9 P8 P7
P4 P3 P2 P1
P8 P7 P6 P5
32bits data bus P2 P1
P4 P3
16bits data bus P6 P5
P8 P7
P4[9:2] P3[9:2] P2[9:2] P1[9:2]
P7[9:2] P6[9:2] P5[9:2] P4[1:0],P3[1:0],P2[1:0],P1[1:0]
32bits data bus P2[9:2] P1[9:2]
P4[9:2] P3[9:2]
16bits data bus

P5[9:2] P4[1:0], P3[1:0], P2[1:0], P1[1:O]
P7[9:2] P6[9:2]

CSI2IPU Memory Map/Register Definition
P3[11:4] P2[3:0],P1[3:0] P2[11:4] P1[11:4]
P6[11:4] P5[11:4] P4[3:0], P3[3:0] P4[11:4]
32bits data bus P2[11:4] P1[11:4]
P3[11:4] P2[11:4], P1[3:0]
16bits data bus P4[3:0], P3[3:0] P4[11:4]
P6[11:4] P5[11:4]
P4[13:6] P3[13:6] P2[13:6] P1[13:6]
P5[13:6] P4[5:0] P3[5:0] P2[5:0] P1[5:0]
32bits data bus P2[13:6] P1[13:6]
P4[13:6] P3[13:6]
16bits data bus P3[3:0] P2[5:0] P1[5:0]
P5[13:6] P4[5:0] P3[5:4]
19.5 CSI2IPU Memory Map/Register Definition

CSI2IPU memory map
Absolute
Width Section/
(in bits) page
(hex)
21D_CF00 CSI 2 IPU Gasket Software Reset (CSI2IPU_SW_RST) 32 R/W 0000_0000h 19.5.1/779

19.5.1 CSI 2 IPU Gasket Software Reset (CSI2IPU_SW_RST)
This register describes the IPU interface signals.

Address: 21D_C000h base + F00h offset = 21D_CF00h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
YUV422_8BIT_
RGB444_FM
R 0
CLK_SEL
SW_
FM
RST
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CSI2IPU_SW_RST field descriptions

Field Description
Reserved
3 rgb444 mode selection
RGB444_FM
0 {4’h0,r4b4g4}
1 {r4,1’b0,g4,2’b00,b4,1’b0}
2 YUV422 8-bit mode selection
YUV422_8BIT_
FM 0 YUYV
1 UYVY
1 Clock mode selection
CLK_SEL
0 Gated Mode
1 Non-Gated Mode
0 Software Reset
SW_RST
0 Software Reset Disable
1 Software Reset Enable

CSI2IPU Memory Map/Register Definition

Chapter 20
20.1 Overview
The goal of the DCIC is to verify that a safety-critical information sent to a display is not
corrupted.
Such a verification is mandatory for warning icons in the instrument cluster of a car, to
comply with the ASIL B (Automotive Safety Integrity Level B) specification. It is also
required in other safety-sensitive systems.
Using external muxing DCIC can monitor either one of the IPU display port outputs or
feedback signals going from IO pads of Parallel display interface. The figure below
shows DCIC integration in system with two IPU blocks.

Overview
IPU #0 IPU #1
DI0 DI1 DI0 DI1
MIPI
IOMUX
DBI
SoCMUX SoCMUX SoCMUX SoCMUX
PADS PADS MIPI

Parallel#1 Parallel#1 LVDS #0 LVDS #1 HDMI
DPI
SoCMUX SoCMUX
sticky control sticky control
DCIC #0 DCIC #1
Figure 20-1. DCIC system integration example
20.1.1 Block Diagram

The figure below shows DCIC top level block diagram.

Chapter 20 Display Content Integrity Checker (DCIC)
Display
interface
Display interface clock domain

DCF-
synchronization buffer
DCIC clock domain (HSP_CLK)
IP
bus IP Logic, Mirrored Display
Configuration & configuration ROI Comparators interface
Status registers registers parser
Interrupts logic
CRC generator
control
CRC32 generator
Figure 20-2. DCIC Block Diagram
20.1.2 Features
• Pixel clock up to 266 MHz
• Configurable polarity of Display Interface control signals
• 24-bit pixel data bus
• Up to 16 rectangular ROIs with a configurable location and size
• Independent CRC32 signature calculation for each ROI
• External controller mismatch indication signal


20.2.1 Generic synchronous parallel display interface

The figure below depicts the LCD interface timing for a generic active matrix color TFT
panel. In this figure signals are shown with negative polarity, but both polarity modes are
supported by DCIC through configuration of appropriate bits of DCICCR register.
The sequence of events for active matrix interface timing is:
• IPP_DISP_CLK latches data into the panel on its negative edge (when positive
polarity is selected). In active mode, IPP_DISP_CLK runs continuously.
• HSYNC causes the panel to start a new line.
• VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DRDY acts like an output enable signal. This output enables the data to be shifted
onto the display. When disabled, the data is invalid and the trace is off.
VSYNC
HSYNC
LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n
HSYNC
DRDY
1 2 3 m-1 m
IPP_DISP_CLK
IPP_DATA
Figure 20-3. Interface Timing Diagram for TFT (Active Matrix) Panels
20.2.2 CRC Polynomial

DCIC uses the CRC32 polynomial to calculate the data signature.
Initial value for CRC calculation is 0x00000000.

x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
CRC generator uses XOR-ed combination of input data bits and previous result bits.
20.2.3 Mode of operation

After DCIC is configured and enabled, providing IPU display interface is already
enabled, first VSYNC is being watched. VSYNC assertion zeroizes main position
counters and initializes CRC storage registers.
Each HSYNC assertion after first line in frame that holds valid pixel data (non blanking)
will signal new line, i.e. increment Y-counter and zeroize X-counter. Each valid data
cycle (DATA_EN asserted) will increment X-counter. Thus X & Y values used to
configure the module should be the coordinates on the actual visual part of the screen
without blanking intervals. X & Y position counters are constantly compared to ROIs
configuration. When current position matches one of the enabled ROIs, it triggers the
enablement of CRC generator, which will use the current pixel data and previous pixel
CRC result for this ROI. The result of the new calculation stored separately for each ROI.
Next VSYNC, apart of signalling new frame start, will cause sampling calculated CRC
values into configuration registers domain. These values then will be compared to
expected signatures and appropriate status bits / interrupts will be asserted.
20.2.4 Interrupts
There are two maskable interrupts:
• Functional - Asserted when match results ready.
• Error - Asserted when there is a signature mismatch.
Both interrupts are generated immediately after completing the signature match check.
Software should clean the interrupts by writing "1" to appropriate status bits (FI_STAT,
ROI_MATCH_STAT). EI_STAT bit is a result of OR between all ROI_MATCH_STAT
bits, hence it will be cleared automatically when these bits are clear.
Interrupt masks can be set/reset only while FREEZE_MASK bit isn't set. This bit can not
be set back to zero.

20.2.5 Software reset

Disabling and enabling the module operation (IC_EN bit, DCIC Control Register
(DCIC_DCICC)) will reset all the logic apart of configuration registers domain. Status
bits of DCICS (DCIC Status Register (DCIC_DCICS)) register will also be cleared.
20.2.6 Clock domains

Asynchronous FIFO is being used to sample raw display interface signals and transfer
them into DCIC fast clock domain (hsp_clk).
Display interface clock is always slower than DCIC fast clock.
IP registers are driven by the same fast clock and will be synchronized to system IP Bus
clock by external IP_SYNC module.
20.2.7 External controller mismatch indication signal

Besides of interrupts to SoC core, DCIC provides an additional mismatch indication for
external controller. The signal, if enabled, continuously oscillating at a rate which is an
integer division of the main clock (hsp clock).
• When the status bit of the mismatch interrupt is set - i.e. from mismatch detection
until the CPU clears the bit: division x16
• Otherwise: division x4
The indication signal is idle while integrity check is disabled.
20.2.8 Power saving

Disabling the module by clearing IC_EN bit will stop all module activities, including
sampling of input signals into the FIFO.
20.2.9 System Considerations

• The DCIC always assumes a 24-bit pixel. For proper functionality with lower color
depth, one must ensure that:
• When the CPU calculates the reference signature, it applies the same mapping of
a pixel to a 24-bit field as that performed by the IPU.

• The display is connected to the appropriate pins.

• The simplest mapping would be
• Map the pixel to the data bus in the same way as for 24 bpp
• Set the values at the extra LSBs to zero.
• Parameter updates
• The reference signature can be freely updated from frame to frame, in
coordination with the changing content (since it is used only once per frame, just
before the interrupt)
• Each ROI can be freely and independently enabled/disabled between frames
(since the enable bit is double buffered)
• The size and location of a ROI can be modified while it is disabled.
• Display interface signals polarity can be changed only when the module is
disabled.
• ROI (regions of interest) don't overlap, i.e. each pixel belongs to single ROI at most.
• DCIC operation is intended for monitoring relatively static portions of graphic
interface, otherwise it will be complicated software task to keep up with frame
synchronization and update expected signature for each frame.
• There should be no processing done at IPU on monitored ROIs, which can't be taken
in consideration by software when calculating the expected signature.
20.3 DCIC Memory Map/Register Definition
Important: All write accesses have to be full word (32-bit) accesses. No error/abort will
be responded in case of different access size, but no data will be written. Similarly, there
will be no error response in case of access to undefined memory space.
Read access will return 32-bit data, which may be truncated on system level in case it
wasn't full word acces.
DCIC memory map
Absolute
Width Section/
(in bits) page
(hex)
20E_4000 DCIC Control Register (DCIC1_DCICC) 32 R/W 0000_0070h 20.3.1/788
20E_4004 DCIC Interrupt Control Register (DCIC1_DCICIC) 32 R/W 0000_0003h 20.3.2/789
20E_4008 DCIC Status Register (DCIC1_DCICS) 32 w1c 0000_0000h 20.3.3/790
20E_4010 DCIC ROI Config Register m (DCIC1_DCICRC) 32 R/W 0000_0000h 20.3.4/791
20E_4014 DCIC ROI Size Register m (DCIC1_DCICRS) 32 R/W 0000_0000h 20.3.5/792

DCIC Memory Map/Register Definition
DCIC memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
DCIC ROI Reference Signature Register m
20E_4018 32 R/W 0000_0000h 20.3.6/793
(DCIC1_DCICRRS)
20E_401C DCIC ROI Calculated Signature m (DCIC1_DCICRCS) 32 R 0000_0000h 20.3.7/793
20E_8000 DCIC Control Register (DCIC2_DCICC) 32 R/W 0000_0070h 20.3.1/788
20E_8004 DCIC Interrupt Control Register (DCIC2_DCICIC) 32 R/W 0000_0003h 20.3.2/789
20E_8008 DCIC Status Register (DCIC2_DCICS) 32 w1c 0000_0000h 20.3.3/790
20E_8010 DCIC ROI Config Register m (DCIC2_DCICRC) 32 R/W 0000_0000h 20.3.4/791
20E_8014 DCIC ROI Size Register m (DCIC2_DCICRS) 32 R/W 0000_0000h 20.3.5/792
DCIC ROI Reference Signature Register m
20E_8018 32 R/W 0000_0000h 20.3.6/793
(DCIC2_DCICRRS)
20E_801C DCIC ROI Calculated Signature m (DCIC2_DCICRCS) 32 R 0000_0000h 20.3.7/793
20.3.1 DCIC Control Register (DCICx_DCICC)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSYNC_POL
VSYNC_POL
R 0 0
CLK_POL
IC_EN
DE_
POL
W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0
DCICx_DCICC field descriptions

Field Description
Reserved
7 DISP_CLK signal polarity.
CLK_POL
0 Not inverted (default).
1 Inverted.
6 VSYNC_IN signal polarity.
VSYNC_POL

DCICx_DCICC field descriptions (continued)

Field Description
0 Active High.
1 Active Low (default).
5 HSYNC_IN signal polarity.
HSYNC_POL
0 Active High.
4 DATA_EN_IN signal polarity.
DE_POL
0 Active High.
Reserved
0 Integrity Check enable. Main enable switch.
IC_EN
0 Disabled
1 Enabled
20.3.2 DCIC Interrupt Control Register (DCICx_DCICIC)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
EXT_
SIG_
W
EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
FREEZE_
EI_MASK
FI_MASK
MASK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
DCICx_DCICIC field descriptions

Field Description
Reserved
16 External controller mismatch indication signal.
EXT_SIG_EN
0 Disabled (default)
1 Enabled

DCICx_DCICIC field descriptions (continued)

Field Description
Reserved
3 Disable change of interrupt masks. "Sticky" bit which can be set once and cleared by reset only.
FREEZE_MASK
0 Masks change allowed (default)
1 Masks are frozen
Reserved
1 Functional Interrupt mask. Can be changed only while FREEZE_MASK = 0.
FI_MASK
0 Mask disabled - Interrupt assertion enabled
1 Mask enabled - Interrupt assertion disabled (default)
0 Error Interrupt mask. Can be changed only while FREEZE_MASK = 0.
EI_MASK
0 Mask disabled - Interrupt assertion enabled
1 Mask enabled - Interrupt assertion disabled (default)
20.3.3 DCIC Status Register (DCICx_DCICS)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EI_STAT
FI_STAT
R 0
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ROI_MATCH_STAT
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DCICx_DCICS field descriptions

Field Description
Reserved
17 Functional Interrupt status. Write "1" to clear.
FI_STAT
0 No pending Interrupt
1 Pending Interrupt
16 Error Interrupt status.
EI_STAT
Result of "OR" operation on ROI_MATCH_STAT[15:0] bits. Cleared when these bits are clear.
0 No pending Interrupt
1 Pending Interrupt
ROI_MATCH_ Each set bit of this field indicates there was a mismatch at appropriate ROIs signature during the last
STAT frame.
Valid only for active ROIs.
Write "1" to clear.
0 ROI calculated CRC matches expected signature

1 Mismatch at ROI calculated CRC
20.3.4 DCIC ROI Config Register m (DCICx_DCICRC)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ROI_FREEZE
R 0
ROI_EN
START_OFFSET_Y
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
START_OFFSET_X
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCICx_DCICRC field descriptions

Field Description
31 ROI #m tracking enable
ROI_EN
0 Disabled
1 Enabled

DCICx_DCICRC field descriptions (continued)

Field Description
30 When set, the only parameter of ROI #m that can be changed is reference signature.
ROI_FREEZE
"Sticky" bit - can be set once and cleared by reset only.
0 ROI configuration can be changed

1 ROI configuration is frozen
Reserved
27–16 Row number of ROIs upper-left corner (Y coordinate)
START_
Range: 0 to 2^12-1
OFFSET_Y
Reserved
START_ Column number of ROIs upper-left corner (X coordinate)
OFFSET_X
Range: 0 to 2^13-1
20.3.5 DCIC ROI Size Register m (DCICx_DCICRS)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
END_OFFSET_Y END_OFFSET_X
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCICx_DCICRS field descriptions

Field Description
Reserved
27–16 Row number of ROIs lower-right corner (Y coordinate)
END_OFFSET_Y
Range: 1 to 2^12-1
Reserved
END_OFFSET_X Column number of ROIs lower-right corner (X coordinate)
Range: 1 to 2^13-1

20.3.6 DCIC ROI Reference Signature Register m

(DCICx_DCICRRS)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
REFERENCE_SIGNATURE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCICx_DCICRRS field descriptions

Field Description
REFERENCE_ 32-bit expected signature (CRC calculation result) for ROI #m
SIGNATURE
20.3.7 DCIC ROI Calculated Signature m (DCICx_DCICRCS)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CALCULATED_SIGNATURE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCICx_DCICRCS field descriptions

Field Description
CALCULATED_ 32-bit actual signature (CRC calculation result) for ROI #m during the last frame.
SIGNATURE
Updated automatically at the beginning of a next frame.


Chapter 21
Enhanced Configurable SPI (ECSPI)
21.1 Overview
The Enhanced Configurable Serial Peripheral Interface (ECSPI) is a full-duplex,

synchronous, four-wire serial communication block.
The ECSPI contains a 64 x 32 receive buffer (RXFIFO) and a 64 x 32 transmit buffer
(TXFIFO). With data FIFOs, the ECSPI allows rapid data communication with fewer
software interrupts. The figure below shows a block diagram of the ECSPI.

Overview
Peripheral Bus Interface
TXDATA RXDATA STATREG INTREG DMAREG PERIODREG TESTREG CONREG
Low-Frequency
Clock Reference Clock
State Machine
Generator
Reference Clock
Interrupt Request
DMA Requests
SPI_RDY
SS[3:0]
SCLK
Shift Register MISO
MOSI
Figure 21-1. ECSPI Block Diagram
21.1.1 Features
Key features of the ECSPI include:
• Full-duplex synchronous serial interface
• Master/Slave configurable
• Four Chip Select (SS) signals to support multiple peripherals
• Transfer continuation function allows unlimited length data transfers
• 32-bit wide by 64-entry FIFO for both transmit and receive data
• Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
• Direct Memory Access (DMA) support
• Refer to the product data sheet for the maximum operating frequency

Chapter 21 Enhanced Configurable SPI (ECSPI)
21.1.2 Modes and Operations

The ECSPI supports the modes described in the indicated sections:
• Master Mode
• Slave Mode
• Low Power Modes
As described in Operations, the ECSPI supports the operations described in the indicated
sections:
• Typical Master Mode
• Master Mode with SPI_RDY
• Master Mode with Wait States
• Master Mode with SS_CTL[3:0] Control
• Master Mode with Phase Control
• Typical Slave Mode

The following table describes the external signals of ECSPI:
Table 21-1. ECSPI1 External Signals
ECSPI1_MISO (MISO) Master data in; slave data out CSI0_DAT6 ALT2 IO
DISP0_DAT22 ALT2
EIM_D17 ALT1
KEY_COL1 ALT0
ECSPI1_MOSI (MOSI) Master data out; slave data in CSI0_DAT5 ALT2 IO
DISP0_DAT21 ALT2
EIM_D18 ALT1
KEY_ROW0 ALT0
ECSPI1_RDY (RDY) SPI data ready signal GPIO_19 ALT4 I
ECSPI1_SCLK (SCLK) SPI clock signal CSI0_DAT4 ALT2 IO
DISP0_DAT20 ALT2
EIM_D16 ALT1
KEY_COL0 ALT0
ECSPI1_SS0 (SS0) Chip select signal CSI0_DAT7 ALT2 IO
DISP0_DAT23 ALT2
EIM_EB2 ALT1
KEY_ROW1 ALT0

External Signals

(continued)
ECSPI1_SS1 (SS1) Chip select signal DISP0_DAT15 ALT2 IO
EIM_D19 ALT1
KEY_COL2 ALT0
ECSPI1_SS2 (SS2) Chip select signal EIM_D24 ALT3 IO
KEY_ROW2 ALT0
KEY_COL3 ALT0

ECSPI2_MISO (MISO) Master data in; slave data out CSI0_DAT10 ALT2 IO
DISP0_DAT17 ALT2
EIM_OE ALT2
ECSPI2_MOSI (MOSI) Master data out; slave data in CSI0_DAT9 ALT2 IO
DISP0_DAT16 ALT2
EIM_CS1 ALT2
ECSPI2_RDY (RDY) SPI data ready signal EIM_A25 ALT2 I
ECSPI2_SCLK (SCLK) SPI clock signal CSI0_DAT8 ALT2 IO
DISP0_DAT19 ALT2
EIM_CS0 ALT2
ECSPI2_SS0 (SS0) Chip select signal CSI0_DAT11 ALT2 IO
DISP0_DAT18 ALT2
EIM_RW ALT2
EIM_LBA ALT2

ECSPI3_MISO (MISO) Master data in; slave data out DISP0_DAT2 ALT2 IO
ECSPI3_MOSI (MOSI) Master data out; slave data in DISP0_DAT1 ALT2 IO
ECSPI3_RDY (RDY) SPI data ready signal DISP0_DAT7 ALT2 I
ECSPI3_SCLK (SCLK) SPI clock signal DISP0_DAT0 ALT2 IO


(continued)

ECSPI4_MISO (MISO) Master data in; slave data out EIM_D22 ALT1 IO
ECSPI4_MOSI (MOSI) Master data out; slave data in EIM_D28 ALT2 IO
ECSPI4_RDY (RDY) SPI data ready signal EIM_EB3 ALT1 I
ECSPI4_SCLK (SCLK) SPI clock signal EIM_D21 ALT1 IO
EIM_D29 ALT2
ECSPI4_SS1 (SS1) Chip select signal EIM_A25 ALT1 IO

ECSPI5_MISO (MISO) Master data in; slave data out SD1_DAT0 ALT1 IO
SD2_DAT0 ALT1
ECSPI5_MOSI (MOSI) Master data out; slave data in SD1_CMD ALT1 IO
SD2_CMD ALT1
ECSPI5_RDY (RDY) SPI data ready signal GPIO_7 ALT1 I
ECSPI5_SCLK (SCLK) SPI clock signal SD1_CLK ALT1 IO
SD2_CLK ALT1
ECSPI5_SS0 (SS0) Chip select signal SD1_DAT1 ALT1 IO
SD2_DAT1 ALT1
SD2_DAT2 ALT1
Figure 21-2 shows the ECSPI in master mode connected to four external devices in a
one-way communication link.

Clocks
External External External External

Device 0 Device 1 Device 2 Device 3
ECSPI
SS[0] SS[1] SS[2] SS[3]
SS[3:0]
(Master)
SCLK
MOSI
Figure 21-2. Example Connection Diagram
21.3 Clocks
The following table describes the clock sources for eCSPI. Please see Clock Controller
Table 21-6. eCSPI Clocks
ipg_clk ipg_clk_root Peripheral clock
ipg_clk_32k ckil_sync_clk_root Low-frequency reference clock (32kHz)
ipg_clk_per ecspi_clk_root eCSPI module clock


This section provides a complete functional description of the ECSPI. The figure found
here shows the relationship of SCLK and data lines while ECSPI has been configured
with different POL and PHA settings.
(POL=1, PHA=1) SCLK
(POL=1, PHA=0) SCLK
(POL=0, PHA=1) SCLK
(POL=0, PHA=0) SCLK
MISO MSB ... ... ... ... ... ... LSB
MOSI MSB ... ... ... ... ... ... LSB
Figure 21-3. ECSPI SCLK, MISO, and MOSI Relationship
21.4.1 Master Mode

When the ECSPI is configured as a master, it uses a serial link to transfer data between
the ECSPI and an external slave device.
One of the Chip Select (SS) signals and the clock signal (SCLK) are used to transfer data
between two devices. If the external device is a transmit-only device, the ECSPI master's
output port can be ignored and used for other purposes. In order to use the internal
TXFIFO and RXFIFO, two auxiliary output signals, Chip Select (SS) and SPI_RDY, are
used for data transfer rate control. Software can also configure the sample period control
register to a fixed data transfer rate.

21.4.2 Slave Mode

When the ECSPI is configured as a slave, software can configure the ECSPI Control
register to match the external SPI master's timing.
In this configuration, Chip Select (SS) becomes an input signal, and is used to control
data transfers through the Shift register, as well as to load/store the data FIFO.
Slave mode only supports the case when ECSPIx_CONFIGREG[SS_CTL] is cleared.
The accurate burst length should always be specified using the BURST_LENGTH
parameter. ECSPIx_CONFIGREG[SS_CTL] set to 1 is not supported in slave mode.
21.4.3 Low Power Modes

The ECSPI does not operate under low power mode.
It holds its operation when its clock is gated off in master mode. In slave mode, the
ECSPI does not respond when its clock is gated off.
21.4.4 Operations
The information found here describes the ECSPI's operations.
21.4.4.1 Typical Master Mode

The ECSPI master uses the Chip Select (SS) signal to enable an external SPI device, and
uses the SCLK signal to transfer data in and out of the Shift register.
The SPI_RDY enables fast data communication with fewer software interrupts. By
programming the ECSPI_PERIODREG register accordingly, the ECSPI can be used for a
fixed data transfer rate.
When the ECSPI is in Master mode the SS, SCLK, and MOSI are output signals, and the
MISO signal is an input.

SS
SCLK
MOSI 1 1 0 1 0 0 1 0
MISO 0 1 1 0 0 1 1 0
Figure 21-4. Typical SPI Burst (8-bit Transfer)
In the above figure, the Chip Select (SS) signal enables the selected external SPI device,
and the SCLK synchronizes the data transfer. The MOSI and MISO signals change on
rising edge of SCLK and the MISO signal is latched on the falling edge of the SCLK.
The figure above shows a data of 0xD2 is shifted out, and a data of 0x66 is shifted in.
21.4.4.1.1 Master Mode with SPI_RDY

By default, the ECSPI does not use the SPI_RDY signal in master mode (MODE =1).
A SPI burst begins when the following events happen:
• The ECSPI is enabled, TXFIFO has data in it, and ECSPI_CONREG[XCH] bit or
the ECSPI_CONREG[SMC] bit is set.
• When the SPI Data Ready Control (ECSPI_CONREG[DRCTL]) bits contains either
01 or 10, the SPI_RDY signal controls when a SPI burst starts.
A SPI burst is defined as a bus transaction that starts when the slave select is asserted and
ends when the slave select is negated. The Chip Select (SS) signal will remain asserted
until all the bits in a SPI burst are shifted out.
If ECSPI_CONREG[DRCTL] is set to 01, the SPI burst can be triggered only if a falling
edge of the SPI_RDY signal has been detected.
The following figure shows the relationship between a SPI burst and the falling edge of
SPI_RDY signal.

SS
SPI_RDY
SCLK
MOSI
MISO
Figure 21-5. Relationship Between a SPI Burst and SPI_RDY: Falling-Edge Triggered
A SPI burst does not start until the falling edge of the SPI_RDY signal is detected. The
next SPI burst starts when the next SPI_RDY falling edge is detected, after the last burst
has finished.
If SPI Data Ready Control (ECSPI_CONREG[DRCTL]) is set to 10, the SPI burst can be
triggered only if the SPI_RDY signal is low.
The following figure shows the relationship between a SPI burst and the SPI_RDY
signal. The SPI burst does not begin until the SPI_RDY signal goes low. The ECSPI will
keep transmitting SPI burst if the SPI_RDY signal remains low.

SS
SPI_RDY
SCLK
MOSI
MISO
Figure 21-6. Relationship Between a SPI Burst and SPI_RDY: Low-Level Triggered
21.4.4.1.2 Master Mode with Wait States

Wait states can be inserted between SPI bursts. This provides a way for software to slow
down the SPI burst to meet the timing requirements of a slower SPI device.
The following figure shows wait states inserted between SPI bursts.
SS
Wait States
SCLK
MOSI
MISO
Figure 21-7. SPI Bursts with Wait States
In this case, the number of wait states is controlled by ECSPI_PERIODREG[SAMPLE

PERIOD] and the wait states' clock source is selected by ECSPI_PERIODREG[CSRC].
21.4.4.1.3 Master Mode with SS_CTL[3:0] Control

The SPI SS Control (SS_CTL[3:0]) controls whether the current operation is single burst
or multiple bursts.

When the SPI SS Wave Form Select (SS_CTL[3:0]) is set, the current operation is
multiple bursts transfer. When the SPI SS Wave Form Select (SS_CTL[3:0]) bit is
cleared, the current operation is single burst transfer. A SPI burst can contains multiple
words as defined in the BURST LENGTH field of the ECSPI_CONREG register.
SS Waiting for
software to
write data to
SCLK the TXFIFO
MOSI
MISO
Figure 21-8. SPI Burst While SS_CTL[3:0] is Clear
In Figure 21-8, two 8-bit bursts in the TXFIFO have been combined and transmitted in
one SPI burst. The maximum length of a single SPI burst is defined by the BURST
LENGTH and limited by the FIFO size. (Figure 21-8 corresponds to a BURST LENGTH
of 8.) This provides a way for transferring a longer SPI burst by writing data into
TXFIFO while the ECSPI is transmitting.
SS
SCLK
MOSI
MISO
Figure 21-9. SPI Bursts While SS_CTL[3:0] is Set
In Figure 21-9, two FIFO entries are transmitted, one entry with each SPI burst. The
ECSPI will continue to transmit SPI bursts until the TXFIFO is empty. When wait states
can be inserted between SPI bursts, the SS will negate between SPI bursts until the wait
states finish.
21.4.4.1.4 Master Mode with Phase Control

The Phase Control (ECSPI_CONREG[PHA]) bit controls how the transmit data shifts out
and the receive data shifts in.

When the Phase control (ECSPI_CONREG[PHA]) bit is set, the transmit data will shift
out on the rising edge of SCLK, and the receive data is latched on the falling edge of
SCLK. The most-significant bit is output on the first rising SCLK edge.
When ECSPI_CONREG[PHA] is cleared, the transmit data is shifted out on the falling
edge of SCLK and the receive data is latched on the rising edge of SCLK. The MSB is
output when the host processor loads the transmitted data.
Inverting the SCLK polarity does not impact the edge-triggered operations because they
are internal to the serial peripheral interface master. Figure 21-10 shows how SPI burst
works with different POL and PHA configuration.
SS
(POL=0, PHA=0)
(POL=1, PHA=0)
(POL=0, PHA=1)
SCLK
(POL=1, PHA=1)
MOSI
MISO
Figure 21-10. SPI Burst with Different POL and PHA Configurations
21.4.4.2 Typical Slave Mode

When the ECSPI is configured as a slave (Mode = 0), software can configure the ECSPI
Control register to match the external SPI master's timing. In this configuration, SS
becomes an input signal, and is used to latch data in and out of the internal data Shift
registers, as well as to advance the data FIFO.

The SS, SCLK, and MOSI are inputs and MISO is output. Most of the timing diagrams
are similar to the diagrams shown previously for the SPI in Master mode (Mode = 1),
because the inputs come from a SPI master device.
However, the timing is different when SS is used to advance the data FIFO. When the
SS_POL=0 is set while the ECSPI is configured in Slave mode, the data FIFO will
advance on the rising edge of the SS signal. When the polarity is reversed (SS_POL = 1),
the data FIFO will advance on the falling edge of the SS signal.
The figure below shows a SPI burst in which the data FIFO is advanced by the rising
edge of the SS signal.
SS
SCLK
MOSI
MISO
Figure 21-11. Advancing the Data FIFO on the Rising Edge of SS
In the above case, only the most significant 7 bits are loaded to the RXFIFO.
21.4.5 Reset
Whenever a device reset occurs, a reset is performed on the ECSPI, resetting all registers
to their default values.
Software can reset the block using the CONREG[EN] bit; see ECSPI.
21.4.6 Interrupts
Interrupt control provides a way to manage the ECSPI FIFOs:

• For transmitting data, software can enable the TXFIFO empty, TXFIFO data request,
and TXFIFO full interrupts to maintain the TXFIFO using an interrupt service
routine.
• For receiving data, software can enable the RXFIFO ready, RXFIFO data request,
and RXFIFO full interrupts to retrieve data from the RXFIFO using an interrupt
service routine.
Other interrupt sources can be used to control or debug the SPI bursts:
• The transfer-completed interrupt means that there is no data left in the TXFIFO and
that the data in the Shift register has been shifted out.
• The RXFIFO overflow interrupt means that the RXFIFO received more than 64
words and will not accept any other words.
Enable CSPI
Enable interrupts
Fill TXFIFO using interrupt service routine
Enable XCH
Wait until all needed data are transferred Retrieve data using interrupt service routine
TC interrupt
TC clear by writing 1
Done
Figure 21-12. Program Sequence of SPI Burst Using Interrupt Control
NOTE
The TC bit does not provide a reliable indication that the
transfer is complete. Under some conditions, the TC interrupt
can occur before the transfer is completed. If the TC bit is used
as an interrupt source, the XCH bit should be polled after the
TC interrupt occurs to accurately confirm that the transfer is
complete.
21.4.7 DMA
DMA control provides another method to utilize the FIFOs in the ECSPI. By using DMA
request and acknowledge signals, larger amounts of data can be transferred, and will
reduce interrupts and host processor loading. When the appropriate conditions are
matched, the block will send out a DMA request.
The DMA can deal with the following conditions:
• TXFIFO empty
• TXFIFO data request
• RXFIFO data request
• RXFIFO full
The figure below shows a program sequence of SPI bursts using DMA control.
Enable CSPI
Enable DMA
Fill TXFIFO using DMA
Enable XCH
Wait until all needed data is transferred Retrieve data using DMA
TC interrupt
Done
Figure 21-13. Program Sequence of SPI Burst Using DMA
NOTE


complete.
21.4.8 Byte Order

The ECSPI does not support byte re-ordering in hardware.
21.5 Initialization
This section provides initialization information for ECSPI.
To initialize the block:
1. Clear the EN bit in ECSPI_CONREG to reset the block.
2. Enable the clocks for ECSPI within the CCM.
3. Configure the Control Register and then set the EN bit in the ECSPI_CONREG to
put ECSPI out of reset.
4. Configure corresponding IOMUX for ECSPI external signals.
5. Configure registers of ECSPI properly according to the specifications of the external
SPI device.
21.6 Applications

ECSPI Memory Map/Register Definition
Master Mode Slave Mode
Configure ECSPI.CONREG, Configure ECSPI.CONREG,

ECSPI.CONFIGREG ECSPI.CONFIGREG
Configure ECSPI.INTREG (optional) Fill TXFIFO
Configure ECSPI.DMAREG (optional)

Wait for RXFIFO Interrupt
(Ready, Data Request, Full)
Configure ECSPI.PERIODREG (optional)
Read Data from RXFIFO
Fill TXFIFO
Transfer Completed
Set XCH bit
Poll XCH bit

or wait for TC interrupt
Read Data from RXFIFO
Transfer Completed
Figure 21-14. Flowchart of the ECSPI Operation
NOTE
complete.
21.7 ECSPI Memory Map/Register Definition
This section includes the block memory map and detailed descriptions of all registers. For
the base address of a particular block instantiation, see the system memory map.

ECSPI memory map

Absolute
Width Section/
(in bits) page
(hex)
200_8000 Receive Data Register (ECSPI1_RXDATA) 32 R 0000_0000h 21.7.1/814
200_8004 Transmit Data Register (ECSPI1_TXDATA) 32 W 0000_0000h 21.7.2/815
200_8008 Control Register (ECSPI1_CONREG) 32 R/W 0000_0000h 21.7.3/815
200_800C Config Register (ECSPI1_CONFIGREG) 32 R/W 0000_0000h 21.7.4/818
200_8010 Interrupt Control Register (ECSPI1_INTREG) 32 R/W 0000_0000h 21.7.5/820
200_8014 DMA Control Register (ECSPI1_DMAREG) 32 R/W 0000_0000h 21.7.6/821
200_8018 Status Register (ECSPI1_STATREG) 32 R/W 0000_0003h 21.7.7/823
200_801C Sample Period Control Register (ECSPI1_PERIODREG) 32 R/W 0000_0000h 21.7.8/824
200_8020 Test Control Register (ECSPI1_TESTREG) 32 R/W 0000_0000h 21.7.9/826
21.7.10/
200_8040 Message Data Register (ECSPI1_MSGDATA) 32 W 0000_0000h
827
200_C000 Receive Data Register (ECSPI2_RXDATA) 32 R 0000_0000h 21.7.1/814
200_C004 Transmit Data Register (ECSPI2_TXDATA) 32 W 0000_0000h 21.7.2/815
200_C008 Control Register (ECSPI2_CONREG) 32 R/W 0000_0000h 21.7.3/815
200_C00C Config Register (ECSPI2_CONFIGREG) 32 R/W 0000_0000h 21.7.4/818
200_C010 Interrupt Control Register (ECSPI2_INTREG) 32 R/W 0000_0000h 21.7.5/820
200_C014 DMA Control Register (ECSPI2_DMAREG) 32 R/W 0000_0000h 21.7.6/821
200_C018 Status Register (ECSPI2_STATREG) 32 R/W 0000_0003h 21.7.7/823
200_C01C Sample Period Control Register (ECSPI2_PERIODREG) 32 R/W 0000_0000h 21.7.8/824
200_C020 Test Control Register (ECSPI2_TESTREG) 32 R/W 0000_0000h 21.7.9/826
21.7.10/
200_C040 Message Data Register (ECSPI2_MSGDATA) 32 W 0000_0000h
827
21.7.10/
827

ECSPI memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
21.7.10/
827
21.7.10/
827
21.7.1 Receive Data Register (ECSPIx_RXDATA)
The Receive Data register (ECSPI_RXDATA) is a read-only register that forms the top
word of the 64 x 32 receive FIFO. This register holds the data received from an external
SPI device during a data transaction. Only word-sized read operations are allowed.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ECSPI_RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECSPIx_RXDATA field descriptions

Field Description
ECSPI_RXDATA Receive Data. This register holds the top word of the receive data FIFO. The FIFO is advanced for each
read of this register. The data read is undefined when the Receive Data Ready (RR) bit in the Interrupt
Control/Status register is cleared. Zeros are read when ECSPI is disabled.

21.7.2 Transmit Data Register (ECSPIx_TXDATA)
The Transmit Data (ECSPI_TXDATA) register is a write-only data register that forms
the bottom word of the 64 x 32 TXFIFO. The TXFIFO can be written to as long as it is
not full, even when the SPI Exchange bit (XCH) in ECSPI_CONREG is set. This allows
software to write to the TXFIFO during a SPI data exchange process. Writes to this
register are ignored when the ECSPI is disabled (ECSPI_CONREG[EN] bit is cleared).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W ECSPI_TXDATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECSPIx_TXDATA field descriptions

Field Description
ECSPI_TXDATA Transmit Data. This register holds the top word of data loaded into the FIFO. Data written to this register
must be a word operation. The number of bits actually transmitted is determined by the BURST_LENGTH
field of the corresponding SPI Control register. If this field contains more bits than the number specified by
BURST_LENGTH, the extra bits are ignored. For example, to transfer 10 bits of data, a 32-bit word must
be written to this register. Bits 9-0 are shifted out and bits 31-10 are ignored. When the ECSPI is operating
in Slave mode, zeros are shifted out when the FIFO is empty. Zeros are read when ECSPI is disabled.
21.7.3 Control Register (ECSPIx_CONREG)
The Control Register (ECSPI_CONREG) allows software to enable the ECSPI ,

configure its operating modes, specify the divider value, and SPI_RDY control signal,
and define the transfer length.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CHANNEL_
BURST_LENGTH DRCTL
W SELECT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
PRE_DIVIDER POST_DIVIDER CHANNEL_MODE SMC XCH HT EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ECSPIx_CONREG field descriptions

Field Description
31–20 Burst Length. This field defines the length of a SPI burst to be transferred. The Chip Select (SS) will
BURST_ remain asserted until all bits in a SPI burst are shifted out. A maximum of 2^12 bits can be transferred in a
LENGTH single SPI burst.
In master mode, it controls the number of bits per SPI burst. Since the shift register always loads 32-bit
data from transmit FIFO, only the n least-significant (n = BURST LENGTH + 1) will be shifted out. The
remaining bits will be ignored.
Number of Valid Bits in a SPI burst.
0x000 A SPI burst contains the 1 LSB in a word.

...
0x01F A SPI burst contains all 32 bits in a word.
0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
...
0xFFE A SPI burst contains the 31 LSB in first word and 2^7 -1 words.
0xFFF A SPI burst contains 2^7 words.
19–18 SPI CHANNEL SELECT bits. Select one of four external SPI Master/Slave Devices. In master mode,
CHANNEL_ these two bits select the external slave devices by asserting the Chip Select (SSn) outputs. Only the
SELECT selected Chip Select (SSn) signal can be active at a given time; the remaining three signals will be
negated.
00 Channel 0 is selected. Chip Select 0 (SS0) will be asserted.

17–16 SPI Data Ready Control. This field selects the utilization of the SPI_RDY signal in master mode. ECSPI
DRCTL checks this field before it starts an SPI burst.
00 The SPI_RDY signal is a don't care.

01 Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered).
10 Burst will be triggered by a low level of the SPI_RDY signal (level-triggered).
11 Reserved.
15–12 SPI Pre Divider. ECSPI uses a two-stage divider to generate the SPI clock. This field defines the pre-
PRE_DIVIDER divider of the reference clock.
0000 Divide by 1.
0001 Divide by 2.
0010 Divide by 3.
...
1101 Divide by 14.
1110 Divide by 15.
1111 Divide by 16.
11–8 SPI Post Divider. ECSPI uses a two-stage divider to generate the SPI clock. This field defines the post-
POST_DIVIDER divider of the reference clock using the equation: 2 n .
0000 Divide by 1.
0001 Divide by 2.

ECSPIx_CONREG field descriptions (continued)

Field Description
0010 Divide by 4.
...
1110 Divide by 2 14 .
1111 Divide by 2 15 .
7–4 SPI CHANNEL MODE selects the mode for each SPI channel.
CHANNEL_
CHANNEL MODE[3] is for SPI channel 3.
MODE
0 Slave mode.
1 Master mode.
3 Start Mode Control. This bit applies only to channels configured in Master mode (CHANNEL MODE = 1).
SMC
It controls how the ECSPI starts a SPI burst, either through the SPI exchange bit, or immediately when the
TXFIFO is written to.
0 SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst
or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and
SS_CTL descriptions.
1 Immediately starts a SPI burst when data is written in TXFIFO.
2 SPI Exchange Bit. This bit applies only to channels configured in Master mode (CHANNEL MODE = 1).
XCH
If the Start Mode Control (SMC) bit is cleared, writing a 1 to this bit starts one SPI burst or multiple SPI
bursts according to the SPI SS Wave Form Select (SS_CTL). The XCH bit remains set while either the
data exchange is in progress, or when the ECSPI is waiting for an active input if SPIRDY is enabled
through DRCTL. This bit is cleared automatically when all data in the TXFIFO and the shift register has
been shifted out.
0 Idle.
1 Initiates exchange (write) or busy (read).
1 Hardware Trigger Enable. This bit is used in master mode only. It enables hardware trigger (HT) mode.
HT Note, HT mode is not supported by this product.
0 Disable HT mode.
1 Enable HT mode.
0 SPI Block Enable Control. This bit enables the ECSPI. This bit must be set before writing to other registers
EN or initiating an exchange. Writing zero to this bit disables the block and resets the internal logic with the
exception of the ECSPI_CONREG. The block's internal clocks are gated off whenever the block is
disabled.
0 Disable the block.

1 Enable the block.

21.7.4 Config Register (ECSPIx_CONFIGREG)
The Config Register (ECSPI_CONFIGREG) allows software to configure each SPI

channel, configure its operating modes, specify the phase and polarity of the clock,
configure the Chip Select (SS), and define the HT transfer length. Note, HT mode is not
supported by this product.
Address: Base address + Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved HT_LENGTH SCLK_CTL DATA_CTL SS_POL SS_CTL SCLK_POL SCLK_PHA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECSPIx_CONFIGREG field descriptions

Field Description
- Reserved
28–24 HT LENGTH. This field defines the message length in HT Mode. Note, HT mode is not supported by this
HT_LENGTH product.
The length in bits of one message is (HT LENGTH + 1).
23–20 SCLK CTL. This field controls the inactive state of SCLK for each SPI channel.
SCLK_CTL
SCLK CTL[3] is for SPI channel 3.
0 Stay low.
1 Stay high.
19–16 DATA CTL. This field controls inactive state of the data line for each SPI channel.
DATA_CTL
DATA CTL[3] is for SPI channel 3.
0 Stay high.
1 Stay low.
15–12 SPI SS Polarity Select. In both Master and Slave modes, this field selects the polarity of the Chip Select
SS_POL (SS) signal.
SS POL[3] is for SPI channel 3.

ECSPIx_CONFIGREG field descriptions (continued)

Field Description
0 Active low.
1 Active high.
11–8 SPI SS Wave Form Select. In master mode, this field controls the output wave form of the Chip Select
SS_CTL (SS) signal when the SMC (Start Mode Control) bit is cleared. The SS_CTL bits are ignored if the SMC bit
is set.
SS CTL[3] is for SPI channel 3.
In slave mode, this bit controls when the SPI burst is completed.
An SPI burst is completed by the Chip Select (SS) signal edges. (SSPOL = 0: rising edge; SSPOL = 1:
falling edge) The RXFIFO is advanced whenever a Chip Select (SS) signal edge is detected or the shift
register contains 32-bits of valid data.
0 In master mode - only one SPI burst will be transmitted.

1 In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be
transmitted. The SPI transfer will automatically stop when the TXFIFO is empty.
0 In slave mode - an SPI burst is completed when the number of bits received in the shift register is
equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the
first received word are valid. All bits subsequent to the first received word in RXFIFO are valid.
1
Reserved
7–4 SPI Clock Polarity Control. This field controls the polarity of the SCLK signal. See Figure 21-10 for more
SCLK_POL information.
SCLK_POL[3] is for SPI channel 3.
0 Active high polarity (0 = Idle).

1 Active low polarity (1 = Idle).
SCLK_PHA SPI Clock/Data Phase Control. This field controls the clock/data phase relationship. See Figure 21-10 for
more information.
SCLK PHA[3] is for SPI channel 3.
0 Phase 0 operation.
1 Phase 1 operation.

21.7.5 Interrupt Control Register (ECSPIx_INTREG)
The Interrupt Control Register (ECSPI_INTREG) enables the generation of interrupts to

the host processor. If the ECSPI is disabled, this register reads zero.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDREN
TDREN
ROEN
TCEN
RRE
Reserved RFEN TFEN TEEN
N
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECSPIx_INTREG field descriptions

Field Description
- Reserved
7 Transfer Completed Interrupt enable. This bit enables the Transfer Completed Interrupt.
TCEN
0 Disable
1 Enable
6 RXFIFO Overflow Interrupt enable. This bit enables the RXFIFO Overflow Interrupt.
ROEN
0 Disable
1 Enable
5 RXFIFO Full Interrupt enable. This bit enables the RXFIFO Full Interrupt.
RFEN
0 Disable
1 Enable
4 RXFIFO Data Request Interrupt enable. This bit enables the RXFIFO Data Request Interrupt when the
RDREN number of data entries in the RXFIFO is greater than RX_THRESHOLD.
0 Disable
1 Enable
3 RXFIFO Ready Interrupt enable. This bit enables the RXFIFO Ready Interrupt.
RREN
0 Disable
1 Enable

ECSPIx_INTREG field descriptions (continued)

Field Description
2 TXFIFO Full Interrupt enable. This bit enables the TXFIFO Full Interrupt.
TFEN
0 Disable
1 Enable
1 TXFIFO Data Request Interrupt enable. This bit enables the TXFIFO Data Request Interrupt when the
TDREN number of data entries in the TXFIFO is less than or equal to TX_THRESHOLD.
0 Disable
1 Enable
0 TXFIFO Empty Interrupt enable. This bit enables the TXFIFO Empty Interrupt.
TEEN
0 Disable
1 Enable
21.7.6 DMA Control Register (ECSPIx_DMAREG)

The Direct Memory Access Control Register (ECSPI_DMAREG) provides software a
way to use an on-chip DMA controller for ECSPI data. Internal DMA request signals
enable direct data transfers between the ECSPI FIFOs and system memory. The ECSPI
sends out DMA requests when the appropriate FIFO conditions are matched.
If the ECSPI is disabled, this register is read as 0.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
Reserved
RXTDEN
RXDEN
RX_DMA_LENGTH RX_THRESHOLD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
TEDEN
Reserved TX_THRESHOLD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ECSPIx_DMAREG field descriptions

Field Description
31 RXFIFO TAIL DMA Request/Interrupt Enable. This bit enables an internal counter that is increased at
RXTDEN each read of the RXFIFO. This counter is cleared automatically when it reaches RX DMA LENGTH. If the
number of words remaining in the RXFIFO is greater than or equal to RX DMA LENGTH, a DMA request/
interrupt is generated even if it is less than or equal to RX_THRESHOLD.
0 Disable
1 Enable
- Reserved
29–24 RX DMA LENGTH. This field defines the burst length of a DMA operation. Applies only when RXTDEN is
RX_DMA_ set.
LENGTH
23 RXFIFO DMA Request Enable. This bit enables/disables the RXFIFO DMA Request.
RXDEN
0 Disable
1 Enable
- Reserved
21–16 RX THRESHOLD. This field defines the FIFO threshold that triggers a RX DMA/INT request.
RX_
A RX DMA/INT request is issued when the number of data entries in the RXFIFO is greater than
THRESHOLD
RX_THRESHOLD.
- Reserved
7 TXFIFO Empty DMA Request Enable. This bit enables/disables the TXFIFO Empty DMA Request.
TEDEN
0 Disable
1 Enable
- Reserved
TX_ TX THRESHOLD. This field defines the FIFO threshold that triggers a TX DMA/INT request.
THRESHOLD
A TX DMA/INT request is issued when the number of data entries in the TXFIFO is not greater than
TX_THRESHOLD.

21.7.7 Status Register (ECSPIx_STATREG)
The ECSPI Status Register (ECSPI_STATREG) reflects the status of the ECSPI's
operating condition. If the ECSPI is disabled, this register reads 0x0000_0003.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TC RO RF RDR RR TF TDR TE
Reserved
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
ECSPIx_STATREG field descriptions

Field Description
- Reserved
7
TC Transfer Completed Status bit. Writing 1 to this bit clears it.
NOTE: The TC bit does not provide a reliable indication that the transfer is complete. Under some
conditions, the TC interrupt can occur before the transfer is completed. If the TC bit is used as an
interrupt source, the XCH bit should be polled after the TC interrupt occurs to accurately confirm
that the transfer is complete.
0 Transfer in progress.
1 Transfer completed.
6 RXFIFO Overflow. When set, this bit indicates that RXFIFO has overflowed. Writing 1 to this bit clears it.
RO
0 RXFIFO has no overflow.
1 RXFIFO has overflowed.
5 RXFIFO Full. This bit is set when the RXFIFO is full.
RF
0 Not Full.
1 Full.
4 RXFIFO Data Request.
RDR
0 When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
1 When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a
DMA TAIL DMA condition exists.
0 When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
1 When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD.

ECSPIx_STATREG field descriptions (continued)

Field Description
3 RXFIFO Ready. This bit is set when one or more words are stored in the RXFIFO.
RR
0 No valid data in RXFIFO.
1 More than 1 word in RXFIFO.
2 TXFIFO Full. This bit is set when if the TXFIFO is full.
TF
0 TXFIFO is not Full.
1 TXFIFO is Full.
1 TXFIFO Data Request.
TDR
0 Number of valid data slots in TXFIFO is greater than TX_THRESHOLD.
1 Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD.
0 TXFIFO Empty. This bit is set if the TXFIFO is empty.
TE
0 TXFIFO contains one or more words.
1 TXFIFO is empty.
21.7.8 Sample Period Control Register (ECSPIx_PERIODREG)

The Sample Period Control Register (ECSPI_PERIODREG) provides software a way to
insert delays (wait states) between consecutive SPI transfers. Control bits in this register
select the clock source for the sample period counter and the delay count indicating the
number of wait states to be inserted between data transfers.
The delay counts apply only when the current channel is operating in Master mode
(ECSPI_CONREG[CHANNEL MODE] = 1).ECSPI_PERIODREG also contains the
CSD CTRL field used to insert a delay between the Chip Select's active edge and the first
SPI Clock edge.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved CSD_CTL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CSRC
SAMPLE_PERIOD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ECSPIx_PERIODREG field descriptions

Field Description
- Reserved
21–16 Chip Select Delay Control bits. This field defines how many SPI clocks will be inserted between the chip
CSD_CTL select's active edge and the first SPI clock edge. The range is from 0 to 63.
15 Clock Source Control. This bit selects the clock source for the sample period counter.
CSRC
0 SPI Clock (SCLK)
1 Low-Frequency Reference Clock (32.768 KHz)
SAMPLE_ Sample Period Control. These bits control the number of wait states to be inserted in data transfers.
PERIOD During the idle clocks, the state of the SS output will operate according to the SS_CTL control field in the
ECSPI_CONREG register.
0x0000 0 wait states inserted

0x0001 1 wait state inserted
... ...
0x7FFE 32766 wait states inserted
0x7FFF 32767 wait states inserted

21.7.9 Test Control Register (ECSPIx_TESTREG)
The Test Control Register (ECSPI_TESTREG) provides software a mechanism to

internally connect the receive and transmit devices of the ECSPI, and monitor the
contents of the receive and transmit FIFOs.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LBC Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserv
RXCNT TXCNT
ed
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECSPIx_TESTREG field descriptions

Field Description
31 Loop Back Control. This bit is used in Master mode only. When this bit is set, the ECSPI connects the
LBC transmitter and receiver sections internally, and the data shifted out from the most-significant bit of the
shift register is looped back into the least-significant bit of the Shift register. In this way, a self-test of the
complete transmit/receive path can be made. The output pins continue to operate normally, however the
input pins are ignored.
0 Not connected.
1 Transmitter and receiver sections internally connected for Loopback.
- Reserved, all bits should be ignored.
- Reserved
14–8 RXFIFO Counter. This field indicates the number of words in the RXFIFO.
RXCNT

ECSPIx_TESTREG field descriptions (continued)

Field Description
- Reserved
TXCNT TXFIFO Counter. This field indicates the number of words in the TXFIFO.
21.7.10 Message Data Register (ECSPIx_MSGDATA)
The Message Data Register (ECSPI_MSGDATA) forms the top word of the 16 x 32
MSG Data FIFO. Only word-size accesses are allowed for this register. Reading from
this register returns zero, and writing to this register stores data in the MSG Data FIFO.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W ECSPI_MSGDATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECSPIx_MSGDATA field descriptions

Field Description
ECSPI_ ECSPI_MSGDATA holds the top word of MSG Data FIFO. The MSG Data FIFO is advanced for each
MSGDATA write of this register. The data read is zero. The data written to this register is stored in the MSG Data
FIFO.


Chapter 22
External Interface Module (EIM)
22.1 Overview
The EIM handles the interface to devices external to the chip, including generation of
chip selects, clock and control for external peripherals and memory. It provides
asynchronous access to devices with SRAM-like interface and synchronous access to
devices with NOR-Flash-like or PSRAM-like interface.

Overview
IPP_DO_STROBE
AXI IPP_DO_CS_B[5:0]
controls
LPMD IPP_DO_WE_B
AXI IPP_DO_OE_B
LPACK Interface
Output
Control IPP_DO_BE_B[3:0]
EIM_GRANT
IPP_DO_ADV_B
EIM_BUSY Synchronous Asynchronous

Core Core IPP_OBE_DATA_DIR[3:0]
IPP_CBE_MADDR_DIR[1:0]
IPI_EIM_INT CONFIGURATION
EIM_BOOT[2:0] IPP_IND_RDY_INT
IPP_DO_CRE_S
Config.
Registers
IPG_CLK_S
IPP_DO_CRE
IPS
Interface
IPS CONTROLS
ACLK
IPP_DO_BCLK
GATED CLOCKS
BCLK
Clock Generation
Gating
AXI_ADDR[31:0] Addr
Path
IPP_DO_ADDR_OUT[27:0]
READ_BIGEND,WRITE_BIGEND
IPP_DO_DATA_MADDR[31:0]
IPP_MUXED_DATA_IN[15:0]
WDATA[31:0] IPP_IND_READ_DATA[31:0]
Data
Path
IPP_IND_WAIT_B
RDATA[31:0]
IPP_IND_FB_BCLK
IPP_IND_DTACK
Figure 22-1. EIM Diagram

Chapter 22 External Interface Module (EIM)
22.1.1 Features
• Four chip selects for external devices
• Flexible address decoding. Each chip select memory space determined
separately, according to VIA port configuration (see Chip Select Memory Map).
Configurable Chip Select 0 base address (by VIA)
• Individual select signal for each one of the memory space defined. Up to 6
memory spaces may be defined and programmed individually.
• 128 MByte maximum supported density by default (AUS bit is cleared). When
the AUS bit is set, maximum supported density is 32 MBytes.
• Selectable Write Protection for each Chip Select
• Support for multiplexed address / data bus operation x16 and x32 port size
• Programmable Data Port Size for each Chip Select (x8, x16 and x32)
• Programmable Wait-State generator for each Chip Select, for write and read accesses
separately
• Asynchronous accesses with programmable setup and hold times for control signals
• Support for Asynchronous page mode accesses (x16 and x32 port size)
• Independent synchronous Memory Burst Read Mode support for NOR-Flash and
PSRAM memories (x16 and x32 port size)
• Independent synchronous Memory Burst Write Mode support for PSRAM and NOR-
Flash like memories (CellularRAM™ from Micron, Infineon, and Cypress,
OneNAND™ and utRAM™ from Samsung, and COSMORAM™ from Toshiba)
• Support of NAND-Flash devices with NOR-Flash like interface - MDOC™ (M-
Systems), OneNAND™ (Samsung)
• Independent programmable variable/fix Latency support for read and write
synchronous (burst) mode
• Support for Big Endian and Little Endian operation modes per access
• Arm AXI slave interface. One ID at a time support.
• External Interrupt support, RDY_INT signal function as external interrupt
• Boot from external device support according to boot signals, using RDY_INT signal
• RDY signal support assertion after reset for MDOC™ (M-Systems) device
• INT signal support assertion after reset for OneNAND™ (Samsung) device

The EIM has the following modes of operation:
• Asynchronous Mode
• Asynchronous Page Mode
• Multiplexed Address/Data mode
Overview
• Burst Clock Mode

• Low Power Modes
• Boot Mode
See details in the EIM Operational Modes.
22.1.2.1 Asynchronous Mode

This is a non-burst mode that is used for SRAM access. In this mode, a single data is
read/written with each access (asserted address).
All controls' timings are controlled by preset values in Chip Select Configuration
Registers.
22.1.2.2 Asynchronous Page Read Mode

Setting the APR bit causes the EIM to perform memory burst accesses by emulating page
mode operation.
The external address asserts for each piece of data. The initial access timing is according
to RWSC field, and the next address assertions timing is according to PAT field. When
APR bit is set, RCSN OEN, RADVN and RBEN fields are ignored for burst access to the
external device.
The page size can be set via the BL field to 2, 4, 8, 16, or 32 words (the word size is
determined by the DSZ field).
22.1.2.3 Multiplexed Address/Data Mode

In this mode, multiplexing addresses and data bits on the same pins is supported for
synchronous/asynchronous accesses to x8/x16/x32 data width memory devices.
For more information about the pins that drive data/address in 8/16/32 non-muxed mode
and 16/32 muxed mode, see the following table.

Table 22-1. EIM multiplexing

Setup Non Multiplexed Address/Data Mode Multiplexed Address/
Data mode
8 Bit 16 Bit 32 Bit 16 Bit 32 Bit
MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 1, MUM = 1,
DSZ = 100 DSZ = 101 DSZ = 110 DSZ = 111 DSZ = 001 DSZ = 010 DSZ = 011 DSZ = 001 DSZ = 011
A[15:0] EIM_DA[1 EIM_DA[1 EIM_DA[1 EIM_DA[1 EIM_DA[1 EIM_DA[1 EIM_DA[1 EIM_DA[1 EIM_DA[1
5:0] 5:0] 5:0] 5:0] 5:0] 5:0] 5:0] 5:0] 5:0]
A[25:16] EIM_A[25: EIM_A[25: EIM_A[25: EIM_A[25: EIM_A[25: EIM_A[25: EIM_A[25: EIM_A[25: EIM_D[9:0]
16] 16] 16] 16] 16] 16] 16] 16]
D[7:0], EIM_D[7:0] - - - EIM_D[7:0] - EIM_D[7:0] EIM_DA[7: EIM_DA[7:
EIM_EB0 0] 0]
D[15:8], - EIM_D[15: - - EIM_D[15: - EIM_D[15: EIM_DA[1 EIM_DA[1
EIM_EB1 8] 8] 8] 5:8] 5:8]
D[23:16], - - EIM_D[23: - - EIM_D[23: EIM_D[23: - EIM_D[7:0]
EIM_EB2 16] 16] 16]
D[31:24], - - - EIM_D[31: - EIM_D[31: EIM_D[31: - EIM_D[15:
EIM_EB3 24] 24] 24] 8]
22.1.2.4 Burst Clock Mode

The controller has the ability to support burst synchronous operations in various
frequencies, depending on the frequency of the input clock supplied by the system (EIM
clock).
The EIM clock can be divided by one, two, three or four, and its frequency can be
changed according to the requirements. Variable and fix latency are supported for this
mode, according to the external device requirements.
• Synchronous read mode. This is a burst mode, which is used for reading from Flash/
PSRAM memory devices. In this mode, after address assertion a burst of sequential
data can be read. Data exchange is carried out according to BCLK being generated
by EIM. An access is delayed according to external WAIT_B signal assertion (signal
from the memory device).
• Synchronous write mode. A burst mode used for accessing external devices, which
support synchronous write type of access (PSRAM protocol). In this mode, after
address assertion a burst of sequential data can be written to the external device.
Access may be delayed according to WAIT_B signal assertion (signal from the
memory device) before first piece of data arrived to the external device.
NOTE
Maximum frequency of the EIM main clock is 133 MHz. It
may be reduced by the system for special cases of external

External Signals
devices, which demand a different frequency then integer

division of the 133 MHz clock.
22.1.2.5 Low Power Modes

The input clock is gated by ACT_CS bits. When all the ACT_CS are negated (all CS
disable) the internal clock is turned off; awready/wready & arready signal are de-asserted
and the master can't access the EIM.
22.1.2.6 Boot Mode

It is possible to perform a boot operation from external device located on CS0. The
configuration of the relevant bits are done with boot mode signals according to the
external device parameters (for example, port size and protocol assertion).
See System Boot for more details.

The following table describes the external signals of EIM:
Table 22-2. EIM External Signals
EIM_AD00 LSB multiplexed Address/Data Bus EIM_DA0 ALT0 IO
signal
signal
signal
signal
signal
signal
signal
signal
signal

Table 22-2. EIM External Signals (continued)

signal
signal
signal
signal
signal
signal
signal
EIM_ADDR16 MSB Address Bus signal EIM_A16 ALT0 O
EIM_ADDR26 MSB Address Bus signal NANDF_CS3 ALT3 O
EIM_BCLK Burst Clock (BCLK). This active-high EIM_BCLK ALT0 O
output signal is used to clock
external burstcapable devices to
synchronize the loading and
incrementing of addresses and
delivery of burst read and write data
to/from the EIM. Its behavior is
affected by the BCM field in the
EIM_WCR and the SWR, SRD,
BCD, and BCS fields of the
EIM_CSxGCR1.
EIM_CRE Used as CRE/PS for CellularRam NANDF_CS2 ALT3 O
memory. It is used for the Mode
Register Set command. This signal
can be configured as active low or
active high. See CRE and CREP
field descriptions of the
EIM_CSxGCR1 registers.
EIM_CS0 Chip Selects. These signals are EIM_CS0 ALT0 O
active-low. Behavior is affected by
the RCSA and RCSN fields of the

External Signals

EIM_CSxRCR1 registers and the
WCSA and WCSN fields of the
EIM_CSxWCR1registers.
EIM_CS1 Chip Selects. These signals are EIM_CS1 ALT0 O
active-low. Behavior is affected by
EIM_CS2 Chip Selects. These signals are DISP0_DAT18 ALT7 O
active-low. Behavior is affected by SD2_DAT1 ALT2
EIM_CS3 Chip Selects. These signals are DISP0_DAT19 ALT7 O
active-low. Behavior is affected by SD2_DAT2 ALT2
EIM_DATA00 MSB Data Bus signal CSI0_DATA_EN ALT1 IO
EIM_DATA01 MSB Data Bus signal CSI0_VSYNC ALT1 IO
EIM_DATA02 MSB Data Bus signal CSI0_DAT4 ALT1 IO
EIM_DATA16 MSB Data Bus signal EIM_D16 ALT0 IO


EIM_DTACK_B Data Acknowledge, asynchronous EIM_WAIT ALT1 I
access. This input is used as a data
acknowledge signal for single
asynchronous accesses.
EIM_EB0 Byte Enable. These active-low EIM_EB0 ALT0 O
output signals indicate valid data
bytes for the current access. They
may be configured to assert for write
cycles only.
EIM_EB[0] corresponds to
DATA_OUT[7:0]
For asynchronous write accesses,
behavior is affected by the WBEA
and WBEN fields of the
EIM_CS1WCR1-EIM_CS5WCR1
Registers. On synchronous or
asynchronous read accesses, these
signals are always asserted at the
start of the access and negated at
end of the access.
cycles only.
DATA_OUT[15:8]
end of the access.

External Signals

cycles only.
DATA_OUT[23:16]
end of the access.
cycles only.
DATA_OUT[31:24].
end of the access.
EIM_LBA Address Valid. This active-low EIM_LBA ALT0 O
output signal is asserted during
burst mode accesses to cause the
external burst capable device to load
a new starting burst address.
Assertion of LBA indicates that a
valid address is present on the
address bus. Its behavior is affected
by the SWR, SRD, BCD, and BCS
fields of the EIM_CSxGCR1
registers, the RADVA and RADVN
fields of the EIM_CSxRCR1
registers, and the WADVA and
WADVN fields of the
EIM_CSxWCR1 registers. In
asynchronous mode, LBA length is
affected by the RADVA, WADVA,
RADVN, and WADVN fields.
Minimum length of LBA signal in all
modes is one EIM clock cycle.


EIM_OE Output Enable. This active-low EIM_OE ALT0 O
output signal indicates the bus
access is a read and enables
external devices to drive the data
bus with read data. Its behavior is
affected by the OEA and OEN bit
fields in the Chip Select
Configuration Registers.
EIM_RW Memory Write Enable. This active- EIM_RW ALT0 O
low output signal indicates the bus
access is a write and enables
external devices to sample the data
bus. Its behavior is affected by the
WEA and WEN bit fields in the Chip
Select Configuration Registers.
EIM_WAIT Ready/Busy/Wait signal. This active- EIM_WAIT ALT0 I
low input signal is asserted by
external burst capable devices
which support fixed or variable
latency of data. It is serviced in
synchronous mode only
(EIM_CSxGCR1[SWR, SRD] =1).
WAIT will have a pull up resistor in
pad. The signal indicates whether
the External device is ready for data
transaction or not. Busy cycles (or
wait cycles) of the external device
can occur at the start of a Burst
access or at page boundary
crossover.
NOTE: For burst devices, WAIT
output should be configured
to change one cycle before
data is ready (before
delay).
NOTE: Some External devices may
not use this input signal for
ready state indication (fix
latency without WAIT signal
monitoring). For these
devices EIM should be
configured accordingly (see
RFL, WFL, and PSZ field
descriptions).
NOTE: This is same as what is
shown in IP_IND_WAIT_B

Clocks
22.2.1 Other Important Block I/O Signals Internal to the SoC

The following table provides a description of other signals internal to the chip that are
important in understanding the function of EIM.
Table 22-3. EIM Important Internal Signals
Name I/O Description
EIM_FB_BCLK Input Burst Clock Feedback. This block input is used to sample read data during high transfer
speeds. The signal provides feedback from the I/O pad of the BCLK output pin and tends
to align more closely with data from the external memory device.
EIM_BOOT Input EIM Boot Configuration. These block inputs determine the reset state of DSZ[1:0] and
MUM. A more detailed description can be found in Fusemap.
ACLK Input AXI clock, maximum frequency 133 Mhz
IPG_CLK_S Input EIM module IPG clock
RST_B Input Active low HW reset
EIM_WARM_RESET Input Warm Reset. If this signal is asserted the rst_b will reset only the internal FF and state
machine while S/W registers will keep their current state. This signal is active high signal.
22.3 Clocks
The following table describes the clock sources for EIM. Please see Clock Controller
Table 22-4. EIM Clocks
aclk aclk_eim_slow_clk_root EIM clock (main)
aclk_slow aclk_eim_slow_clk_root EIM clock (slow)
aclk_exsc aclk_eim_slow_clk_root EIM clock (external device)
• ACLK: EIM clock (main clock, AXI clock) with a Max frequency of 133 MHz. Can
be gated externally when there is no active AXI access.
• ACLK_SLOW: EIM all time running ACLK. Used for flip-flops that must be active
even when EIM is in low power down mode to provide clock for lpack/lpmd
registers, IP registers and IP to AXI sync registers.
• IPG_CLK_S: IPG clock for IP accesses. IP registers are activated by ACLK_SLOW
clock.
• ACLK_EXSC: Clock created from EIM clock for External device usage. Integer
division by 1, 2, 3 and 4 of the clock can be use with BCD bit field configuration,
according to external devices demands. EIM clock frequency may be reduced for
lower frequency support which cannot be achieved via BCD bit field.
22.4 Chip Select Memory Map

The EIM memory space is mapped into 128 MB total memory space in the processor
memory. For addresses, see the System memory map table and the CM4 memory map
table. The total 128 MB of memory can be divided among the EIM four chip selects. The
memory configuration across the chip selects is controlled by the IOMUXC_GPR1
register. The ADDRSn[10] fields control how much memory is allotted to each chip
select.
The following four configurations are supported:
• CS0 (128 MB), CS1 (0 MB), CS2 (0 MB), CS3 (0 MB) [default configuration]
• CS0 (64 MB), CS1 (64 MB), CS2 (0 MB), CS3 (0 MB)

This section provides the functional description for the EIM.
22.5.1 Bus Sizing Configuration

The EIM supports byte, half word and word operands allowing access to x8, x16, x32
ports. It can be address/data multiplexed in x16, x32 ports. The port size is programmable
via the DSZ bit field in the corresponding Chip Select Configuration Register. An 8-bit
port can reside in each one of the bytes of the data bus. A 16-bit port can reside on the
lower 16 bits of the data bus, DATA_IN/OUT[15:0] or on the higher 16 bits of the data
bus, DATA_IN/OUT[31:16].
In the case of a multi-cycle transfer, the lower two address bits (ADDR[1:0]) are
incremented appropriately. The EIM address bus is configured according to DSZ bit field
and AUS bits. There is either one bit (for x16 port size) or two bits (for x32 port size)
right shift of the address bits (only when AUS=0) and no bit shift when AUS = 1 or
DSZ[2] = 1.
The EIM has a data multiplexer which takes the four bytes of the AXI data bus and routes
them to their required positions to properly interface to memory.

NOTE
A word access to or from a x16 port requires two external bus
cycles to complete the transfer.
A word access to or from a x8 port requires four external bus
cycles to complete the transfer.
22.5.1.1 8 BIT PORT SUPPORT

EIM has limited support for mot68000 & intel 386 protocols.
22.5.1.1.1 MOTOROLA 68000

EIM has limited support for mot68000 protocol. Only basic read or write asynchronous
operations are supported.
The following operations are not supported:
• Read modify write
• Sync access
• All special accesses (Arm platform space, bus arbitration, bus control, bus error &
reset operations)
• FC outputs
22.5.1.1.2 INTEL 386

EIM has limited support for intel 386 protocol. Only basic read or write async non-
pipelined operations are supported.
The following operations are not supported:
• Other bus cycles (interrupt, halt & refresh)
• Bus lock
• M/IO, DC, LBA, NA, REFRESH & BS8 signals
22.5.2 EIM Operational Modes

Listed here are the main operational modes for EIM selected by control bit fields settings.

For details, see the bit field descriptions of SWR / SRD / MUM. All modes are supported
in with 8-, 16- or 32-bit port configuration, according to DSZ bit field.
Table 22-5. EIM Operation Modes Field Settings
Control bit fields Brief mode description
MUM SRD SWR
0 0 0 Asynchronous write / Asynchronous read for APR=0 /
Asynchronous page read for APR=1, none multiplexed
1 Synchronous write/ Asynchronous read or APR=0 /
Asynchronous page read for APR=1,none multiplexed
1 0 Asynchronous write/Synchronous read none multiplexed
1 Synchronous write/read none multiplexed
1 0 0 Asynchronous write/read multiplexed
1 Synchronous write/ Asynchronous read multiplexed
1 0 Asynchronous write/Synchronous read multiplexed
1 Synchronous write/read multiplexed
22.5.3 Burst Mode (Synchronous) Memory Operation

This mode is enabled for read or write access. Bit SWR sets the burst mode for write
operations at the corresponding chip select and bit SRD sets it for read operation.
When this mode is set, the controller attempts to translate the Master burst accesses to
memory burst accesses, being limited by the memory burst length, predefined by BL
value, or memory and Master WRAP/INCR boundary crossing non-matching. Only the
first address accessed is put by the controller on the external address bus in a memory
burst sequence.
EIM may translate from some Master sequential accesses to one or several memory
bursts, but not from two Master individual accesses to one memory burst.
For the first access in a memory burst sequence, the EIM asserts ADV, causing the
external burst device to latch the starting burst address; then toggle the burst clock
(BCLK) for a predefined number of cycles in order to latch the first unit of data.
Subsequent accessed data units can then be burst in fewer clock cycles, realizing an
overall increase in bus bandwidth.
NOTE
The BCLK signal toggles only when burst access is executed
toward the external device (BCM=1'b0 for normal mode use). It
runs with a 50% duty cycle until the end of access is reached.
When access is terminated, BCLK stops toggling.
Memory burst accesses are terminated by the EIM whenever it detects the following:
• The specific burst length has executed completely (end of access)
• Write access - missing data in write buffer (Master is delaying the data transfer
toward the EIM)
• Next sequential access crosses boundary with unequal condition (wrap/increment,
burst length) on the Master and memory
• Current memory burst length reached
22.5.4 Burst Clock Divisor (BCD)

In some cases, it may be necessary to slow the external bus in relation to the internal bus
to allow accesses to burst devices that have a maximum operating frequency less than the
operating frequency of the internal bus.
The internal bus frequency can be divided by one, two, three or four for presentation on
the external bus in burst mode operation.
BCLK can only be set to integer divisions of the incoming clock frequency. To get a
specific frequency on BCLK, configure the divider to change the incoming EIM clock
accordingly.
By programming the BCD bit field to various values, two signals on the external bus are
affected; ADV and BCLK. The ADV signal is asserted according to RADVA or
WADVA bit fields programming, and is negated according to the formula mentioned in
RADVN and WADVN bit fields description. The BCLK signal runs with a 50% duty
cycle until the end of access is reached.
If BCM = 1, the BCLK runs at frequency according to GBCD bit field settings on every
async memory access, regardless of the SWR and SRD bits configuration. Caution should
be exercised when using BCM bit; GBCD bit field should be updated once and should
not change when BCLK is toggling. The BCM bit is used mainly for system debug mode.
It has no functional use of the EIM in normal mode.
22.5.5 Burst Clock Start (BCS)

In an effort to allow greater flexibility in achieving the minimum number of wait states
on burst accesses, you can determine when you want the BCLK to start toggling after the
start of access. This allows the BCLK to be skewed from point of data capture on the
EIM clock by any number of EIM clock cycles.

Care must be exercised when setting BCS bit field in conjunction with the BCD and
RWSC/WWSC bit fields. See the external timing diagrams in Burst (Synchronous Mode)
Read Memory Accesses Timing Diagram - BCD=1 and Burst (Synchronous Mode) Read
Memory Accesses Timing Diagram - BCD=0 for examples of how to use the BCS, BCD
and RWSC/WWSC bit fields together.
22.5.6 Multiplexed Address/Data Mode Support

The control bit MUM allows support memory with multiplexed address/data bus both in
asynchronous and in synchronous modes.
Caution should be exercised for using OEA/WEA & ADH bit fields. They should be
configured according to the external device requirements, as it determines the time point
of end of address phase and start of data phase.
22.5.7 Mixed Master/Memory Burst Modes Support

To provide mixed sequential/wrap accesses with different length, EIM interprets burst
signal and generate additional ADV signals whenever there appear unequal address or
burst boundary crossing condition.
BL bit field is used to notify EIM about current memory burst and wrap condition for
properly external address generation. In case of non-matching boundaries in both the
memory and Master access, EIM starts a new memory burst access by updating address
from Master on address bus and generating ADV signal.
22.5.8 AXI (Master) Bus Cycles Support

The EIM uses an Arm AXI slave interface. It has a 32-bit bus and supports one access
(one ID) at a time. No out of order or parallel accesses are supported.
The following AXI protocol signals are not supported:
• AWLOCK
• AWCACHE
• ARLOCK
• ARCACHE
ARID bus is sampled when:

• new read access is valid on the read address channel and is reflected on the RID bus
output toward the master.
AWID bus is sampled when:
• new write access is valid on the write address channel and is reflected on the
WID/BID bus output toward the master.
ARPROT and AWPROT signal are partially used. ARPROT[0] and AWPROT[0] bits are
used for normal/privileged access detection. ARPROT[2:1] and AWPROT[2:1] are not
used.
When sampling a valid access on both of the address channels, the read access will be
performed first while write access is pending. After last data transfer completed, the
pending write will be executed.
A new access may be executed one cycle after sampling a valid access on the read or
write address channels, assuming there is no current access (back to back) which can
cause a recovery or end of access penalty cycles, for write access, also assuming data is
in write buffer for fast execution.
NOTE
• Only 32-bit word size accesses are supported for burst
mode accesses.
• Only 8-bit (1 byte), 16-bit (2 byte) and 32-bit (4 byte) word
size supported for single access.
• Maximum number of burst length is 16.
• According to AXI protocol, burst access should not cross 4
KB blocks. In case EIM gets an access that crosses the 4
KB, memory address calculation is invalid.
AXI transfers shown in the table below are also supported. These AXI cycles will be
translated into the necessary cycles on the memory side. For example, for optimal
operation in case Arm cache is configured to 8 beat burst with wrap, a synchronous flash
and cellular RAM memory should be configured in 16 word wrap burst mode when using
a 16-bit data port, and in 8 word wrap burst mode when using a 32-bit data port. EIM
uses BL bit field to support different memory configurations. The controller splits the
transaction when needed in some cases. See Table 22-7.
Table 22-6. AXI Burst Cycles Supported
Burst Length - Burst size - Bytes Burst type Description
Number of data in transfer
transfers
1 1 INCR Single transfer

Table 22-6. AXI Burst Cycles Supported (continued)

Burst Length - Burst size - Bytes Burst type Description
Number of data in transfer
transfers
2 4 WRAP 2-beat wrapping burst
2 4 INCR 2-beat incrementing burst
Table 22-7. AXI to Memory Burst Splits Number

AXI Burst Type Memory Burst # of accesses to # of accesses to # of accesses to X32
Type Config. X8 X16
Memory Port size
Memory Port size Memory Port size
INC16 WRAP4 16 8 4
Aligned Addr. Cont. 1 1 1
INC16 WRAP4 17 9 5
Unaligned Addr. Cont. 1 1 1
WRAP16 Aligned Addr. WRAP16 4 2 1
Cont. 1 1 1
WRAP16 Unaligned Addr. WRAP16 5 3 1
Cont. 2 2 2
INC8 WRAP8 4 2 1
Aligned Addr. WRAP16 2 1 1
INC8 WRAP8 4 or 5 2 or 3 2

Table 22-7. AXI to Memory Burst Splits Number (continued)

AXI Burst Type Memory Burst # of accesses to # of accesses to # of accesses to X32
Type Config. X8 X16
Memory Port size
Memory Port size Memory Port size
Unaligned Addr. WRAP16 2 or 3 2 1 or 2
WRAP8 WRAP16 2 1 1
Aligned Addr. Cont. 1 1 1
WRAP8 Unaligned Addr. WRAP16 2 or 3 1 2
Cont. 2 2 2
22.5.9 WAIT_B Signal, RWSC and WWSC bit fields Usage

Most of the external devices supporting burst mode for write or read accesses provide a
signal which indicates data is valid on the memory bus (a.k.a. handshake mode). For this
mode, RFL and WFL bits should be cleared and RWSC/ WWSC bit fields indicate when
the controller should start sampling this signal from the external device or, in other
words, how many BCLK cycles should be masked.
For devices which do not use this signal or have a fixed latency ability, the RFL and
WFL bits may be set for internal calculation regarding BCLK cycles penalty until data is
valid (memory initial access time). For this mode, RWSC/ WWSC indicates when the
data is ready for sampling by the controller (read access) or the external device (write
access). There is separation between read and write accesses wait-state control. For read
access, RWSC bit field is valid and WWSC bit field is ignored; for write access, WWSC
is valid and RWSC is ignored.
22.5.10 IPS Register Interface

Access to the registers of the EIM, read or write, is made with IPS protocol signals. The
system should avoid changing the registers while master/memory transaction is valid, as
this can cause an unknown behavior of the controller.
Register access size is 32-bit as the register size definition, other size of access (byte or
half word) is not supported.

22.5.11 MRS Set for PSRAM

Memory registers of PSRAM devices can be configured according to external signal,
which indicates whether the access is to a memory array or memory register domain.
When the CRE bit is set, the following transactions to the external device will assert the
CRE signal. The polarity of this signal is determined by the CREP bit for active low or
active high assertion of the signal.
22.5.12 EIM Access Termination

EIM is monitoring the corresponding CSx control signal every time variable latency
access or dtack access is performed toward the external device.
In variable latency accesses, the Watchdog Timer (WDOG-1) counts BCLK cycles. If it
reaches the wdog_limit (according to the WDOG_LIMIT bit field in the WCR) before
the device signals can drive/sample new data, the controller will terminate the access and
generate an error response transfer toward the Master.
In dtack access, WDOG-1 counts ACLK cycles instead of BCLK and it reaches the
wdog_limit before the device asserts the dtack signal, the controller will terminate the
access and generate an error response transfer toward the Master.
WDOG-1 can by disabled by WDOG_EN bit in the WCR.
22.5.13 Error Conditions

The following conditions cause an error (AXI error or IPS error) response signal:
• AXI errors
• Access to a disabled chip select - access to a mapped chip select address space
where the CSEN bit in the corresponding chip select Configuration Register is
clear
• Access to a non mapped address - access to an address that is not mapped to any
CS.
• User access to a supervisor-protected chip select address space (the SP bit in the
corresponding chip select Configuration Register is set)
• User access in fixed mode access
• User performs write access to write protected chip select
• First write data ID and write address ID do not match. (No data is written to the
memory.)

• First Write Data ID and write address ID match but one or more of the other
Write data IDs does not match the First Write data ID (data is written to memory
according)
• Access duration to external device from CSx signal assertion is
128/256/512/1024 cycles (access is terminated by the controller) - This error can
be disabled be software.
• IPS errors
• User read or write access to a reserved/non-valid address in the EIM
Configuration Register
22.5.14 DTACK Mode

In DTACK mode, the EIM uses DTACK signal as an indication of when to end the
access.
DTACK is an asynchronous edge/level sensitive signal. DTACK polarity is configurable
by the DAP bit in CsxGCR2 (default value is 0).
In this case, EIM begins the access and after a few cycles (according DAPS field) and
waits until DTACK (after synchronization) becomes asserted, then samples the data in
read access and completes the current data access (see Figure 22-15, Figure 22-16 &
Figure 22-17).
If more than one data is needed, CS will be negated between access (CSREC field is not
zero) and the AXI burst access will be split into single accesses (see Figure 22-19).
22.5.15 RDY_INT Signal as Interrupt

The EIM has an external interrupt support. When INTEN bit in the WCR is set, signal
RDY_INT is used as interrupt; its status is being reflected by INT bit and output signal.
It is cleared by writing one to the INT bit. When INTEN is cleared, the interrupt is
disabled. This interrupt is a level interrupt and its polarity can be configured by the
INTPOL bit in the WCR.
22.5.16 RDY_INT Signal as Ready After Reset Indication

This feature is used for boot propose from external devices based on NANDFlash array
memory with NORFlash interface.

When ERRST bit is set, RDY_INT signal is monitored to determine ready after reset of
the external device located on CS0.
The monitoring is taking place when CS0 is accessed for the first time. The access will be
pending until assertion of the signal is detected. When detection occurs, ERRST bit is
self-cleared and pending access is executed to the external device on CS0.
22.5.17 EIM_GRANT / EIM_BUSY Handshake Description

Prior to executing command to one of the external device (chip select), EIM assert
EIM_BUSY signal (1'b1) and checks the EIM_GRANT signal status.
If EIM_GRANT signal is high, it indicates external data bus is not used by other slaves
(NAND Flash Controller) and EIM may start to execute the access. If EIM_GRANT is
low, EIM waits until it is set (1'b1) before executing the access.
EIM keeps EIM_BUSY signal set until it completes the access toward the external
device.
Once EIM_GRANT signal is set, it can not be reset until EIM_BUSY signal is cleared by
EIM.
NOTE
In 16-bit Muxed EIM doesn't use the data bus, therefore there is
no sharing of the data bus with NFC. EIM doesn't wait for
EIM_GRANT signal from NFC and doesn't assert the
EIM_BUSY signal.
22.5.18 LPMD / LPACK Handshake Description

These signals are used for frequency and/or voltage change, and for entering low power
mode during normal operation of the EIM. Before any change can take place, the
controller and all the relevant external devices should be in idle state, which means no
access or data transfer is in process.
LPMD input signal is asserted once EIM detects the assertion of LPMD, all ready signals
of the AXI channels are negated, and EIM is not sampling new accesses. It finishes all
the ongoing accesses and already pending ones. When EIM is in idle state, the LPACK
output signal is asserted. EIM will stay in idle state and the LPACK signal will stay
asserted until the LPMD signal is negated.

22.5.19 Endianness
Big and Little endianness are supported by the controller according to the following table.
Table 22-8. EIM Out/in Data in Case AXI Out/in Data is 0xB3B2B1B0
Endian AXI AXI Port size and used bits
mode access address
Word port Half word port Byte port
[1:0]
[31:24] [23:16] [15:8] [7:0] External [31:24] [23:16] External [31:24]
address address
([15:8]) ([7:0]) ([23:16])
[0] [1:0]
([15:8])
([7:0])
Big Word 0 0xB3 0xB2 0xB1 0xB0 0 0xB3 0xB2 0 0xB3
1 0xB2
1 0xB1 0xB0 2 0xB1
3 0xB0
Half 0 0xB1 0xB0 0 0xB3 0xB2 0 0xB3
Word 1 0xB2
2 0xB3 0xB2 1 0xB1 0xB0 2 0xB1
3 0xB0
Byte 0 0xB0 0 0xB3 0 0xB3
1 0xB1 0xB2 1 0xB2
2 0xB2 1 0xB1 2 0xB1
3 0xB3 0xB0 3 0xB0
Little Word 0 0xB3 0xB2 0xB1 0xB0 0 0xB1 0xB0 0 0xB0
1 0xB1
1 0xB3 0xB2 2 0xB2
3 0xB3
Half 0 0xB1 0xB0 0 0xB1 0xB0 0 0xB0
Word 1 0xB1
2 0xB3 0xB2 1 0xB3 0xB2 2 0xB2
3 0xB3
Byte 0 0xB0 0 0xB0 0 0xB0
1 0xB1 0xB1 1 0xB1
2 0xB2 1 0xB2 2 0xB2
3 0xB3 0xB3 3 0xB3
22.5.20 Strobe Signal Use

The strobe signal is toggling according to address/data valid condition on the external bus
for read and write accesses, and for both synchronous and asynchronous modes.

At any time point when address/data is valid on the external bus, the strobe signal will
generate a positive edge, which can be used to sample the external data and control
signal.
NOTE
Strobe signal for read data is active (RL + 1) cycles after data
on external bus is valid.
22.6.1 Booting from EIM

EIM is ready to work with CS0 after the hardware reset, but it has been configured for
very slow access (for boot purposes), with additional setup and hold time.
Other CSs are disabled by hardware reset. Therefore, all CSs must be properly initialized
before use in writing values to the corresponding chip select configuration registers.
DSZ[1:0] and MUM fields are set according to EIM_BOOT [2:0] block inputs.
22.7 Typical Application

Application note uses following functions to illustrate EIM and memory accesses:
• WR16(address, data) is a 16 bit write access
• WR32(address, data) is a 32 bit write access
• RD16(address, data) is a 16 bit read access
• RD32(address, data) is a 32 bit read access
• WR_I(address, data, delta, counter) is a write data sequence, there data(i+1) = data(i)
+ delta
• COMMAND_SEQUENCE
• CHECK_STATUS
NOTE
COMMAND_SEQUENCE and CHECK_STATUS are
described in AMD Flash Utility, Intel Sibley Flash Utility,
MDOC Device Utility, Samsung OneNAND Utility, and
Spansion Flash Utility.

Typical Application
All addresses are byte addresses. "CS0" is a Chip Select 0 base address. "EIM_" is a
prefix of EIM's registers. 'h is a prefix of hexadecimal constant. "//" is a comment
beginning. csba[cs] is a dimension of CS base addresses. "addr" means an address offset
in current CS address space. Examples use CS0 address space, but it may apply to any CS
except for boot mode functionality.
Configuration examples were verfied with the memory models listed below and may
require some adjustments for other family members.
22.7.1 Access to Intel Sibley Flash

The following configurations are intended to Sibley family muxed and non-muxed
devices.
22.7.1.1 Intel Sibley Flash Asynchronous Mode Configuration

• WR32('EIM_CS0GCR1,'h00210081);
• WR32('EIM_CS0RCR1,'h0e020000);
• WR32('EIM_CS0RCR2,'h00000000);
• WR32('EIM_CS0WCR1,'h0704a040);
22.7.1.2 Intel Sibley Flash Synchronous Mode Configuration

Configuration used for 133 MHz synchronous access to flash:
// Set memory to synchronous read mode
WR16('CS0+('h5903<<1),'h0060);
WR16('CS0+('h5903<<1),'h0003);
WR16('CS0+('h0000<<1),'h00ff);
// Set EIM configuration to synchronous timing
WR32('EIM_CS0GCR1,'h50214225); // 133 MHz
WR32('EIM_CS0RCR1,'h0c000000); // 12 cycles on memory
Configuration used for 66 MHz synchronous access to muxed flash:

// Set memory to synchronous read mode
WR16('CS0+('h3103<<1),'h0060);
WR16('CS0+('h3103<<1),'h0003);
WR16('CS0+('h0000<<1),'h00ff);
//--------------------------------------------------------------------------
// Set EIM configuration to synchronous timing
WR32('EIM_CS0GCR1,'h5021122d); // 66 MHz
WR32('EIM_CS0RCR1,'h07000000); // 7cycles on memory

22.7.1.3 Intel Sibley Flash Utility

// Single data word programming to addr
WR16('CS0+addr,'h0060); // Unlock
WR16('CS0+addr,'h00d0);
WR16('CS0+addr, 'h0041);
WR16('CS0+addr, data);
WR16('CS0+caddr, 'h0070); // Read Status command
while('CS0+data[7] == 0) // Wait / Polling
RD16('CS0+addr, data); // Read status
WR16('CS0+'h0000,'h00ff);
// Write buffer programming
WR16('CS0+addr,'h0060); // Unlock
WR16('CS0+addr,'h00d0);
data = 0;
WR16('CS0+addr, 'h0070); // Read Status command
while(data[7] == 0) // Wait
WR16('CS0+'h0000,'h00ff);
WR16('CS0+addr,'h00e9); // Write Buffer command
WR16('CS0+addr,255); // Word counter (<256)
for(i=0; i<'h200; i = i + 'h40)
WR_I('CS0+addr+i, data+((i>2)*'h0010_0001), 'h0010_0001, 16); // Data
WR16('CS0+addr,'h00d0); // Write Confirm command
data = 0;
while(data[7] == 0) // Wait
WR16('CS0+'h0000,'h00ff);
22.7.2 Access to MDOC Device

The following configurations are intended to MDOC H3 device.
22.7.2.1 MDOC Device Boot

To boot from the MDOC device the ERRST bit should be configured to 1, so that EIM
will hold the first read access to CS0 until the MDOC asserts the RDY signal.
22.7.2.2 MDOC Device Asynchronous Mode Configuration

// Non-muxed mode
WR32('EIM_CS0GCR1,'h00410081);
WR32('EIM_CS0RCR1,'h0e121010);
WR32('EIM_CS0RCR2,'h00000000);
WR32('EIM_CS0WCR1,'h12092492);
// Muxed mode
WR32('EIM_CS0GCR1,'h00410081);
WR32('EIM_CS0RCR1,'h0e121010);
WR32('EIM_CS0RCR2,'h00000000);
WR32('EIM_CS0WCR1,'h12092492);

Typical Application
22.7.2.3 MDOC Device Utility

// Read Manufacturer ID and Device ID
RE16('CS0+'h9400,'h4833);
RE16('CS0+'h9422,'hb7cc);
22.7.3 Access to Micron PSRAM

The following configurations are intended to mt45w4mw16bfb_706.
22.7.3.1 Micron PSRAM Asynchronous Mode Configuration

// 16 bit memory
WR32('EIM_CS0GCR1,'h403104b1);
WR32('EIM_CS0RCR1,'h0b010000);
WR32('EIM_CS0RCR2,'h00000008);
WR32('EIM_CS0WCR1,'h0b040040);
// 32 bit memory
WR32('EIM_CS0RCR1,'h0f010000);
WR32('EIM_CS0RCR2,'h00000008);
WR32('EIM_CS0WCR1,'h0f040040);
22.7.3.2 Micron PSRAM Synchronous Mode Configuration

// 16 bit memory
WR16('CS0+('h85947<<1),'h0040); // memory configuration
WR32('EIM_CS0GCR1,'h4021_5487);// fixed latency memory wrap 4
WR32('EIM_CS0RCR1,'h04000000);
WR32('EIM_CS0RCR2,'h00000008);
WR32('EIM_CS0WCR1,'h04000000);
// 32 bit memory
WR32('EIM_CS0GCR1,'h6003_04f1);
WR32('EIM_CS0WCR1,'h0b04_0000);
WR32('CS0+('h85947<<2),'h0040); // memory configuration
WR32('EIM_CS0GCR1,'h4003_1487); // var latency memory inc. page size 128
WR32('EIM_CS0RCR1,'h04000000);
WR32('EIM_CS0RCR2,'h00000008);
WR32('EIM_CS0WCR1,'h04000000);
22.7.4 Access to Samsung OneNAND

Mentioned below are the configurations intended for Samsung OneNAND muxed and
non-muxed devices.

22.7.4.1 Samsung OneNAND Boot

There are two ways to boot from Samsung OneNAND. In the first way, the ERRST bit is
set to 0 and the user has to poll the interrupt status in the OneNAND interrupt register (or
set interrupt handler there). In the second way, the ERRST bit is set to 1 and the user
should enable the device interrupt output before the first read from CS0 access is issued.
Load sectors 2,3 to DataRAM, page 0 done in the next example:
• WR16('CS0+('hF241<<1),'h0); // Clear interrupt status
• WR16('CS0+('hF100<<1),'h0); // block[8:0] address
• WR16('CS0+('hF107<<1),'h2); // sector[1:0] and page[7:2] addresses
• WR16('CS0+('hF200<<1),'h802); // buffer[11:8] address and counter[1:0]
• WR16('CS0+('hF101<<1),'h0); // DDP choose
• WR16('CS0+('hF220<<1),'h0); // Set command
22.7.4.2 Samsung OneNAND Asynchronous Mode Configuration

// Non-muxed memory
WR32('EIM_CS0GCR1,'h00410081);
WR32('EIM_CS0RCR2,'h00000000);
WR32('EIM_CS0WCR1,'h0c092480);
// Muxed memory
WR32('EIM_CS0GCR1,'h00410089);
WR32('EIM_CS0RCR2,'h00000000);
WR32('EIM_CS0WCR1,'h0c092480);
22.7.4.3 Samsung OneNAND Synchronous Mode Configuration

Set memory and EIM to synchronous read mode is shown in the next example:
WR16('CS0+('hF221<<1),'hc0e0); // Synchronous read, 4 clk latency
WR32('EIM_CS0GCR1,'h50412405); // 44 MHz (non-muxed)
WR32('EIM_CS0RCR1,'h05010000);
The muxed Samsung OneNAND supports synchronous write, too:

// Set memory & EIM to synchronous read and write mode
WR16('CS0+('hF221<<1),'hc0f2); // Sync. read and write, 4 clk latency
WR32('EIM_CS0GCR1,'h5041240f); // 44 MHz
WR32('EIM_CS0RCR1,'h05010000);
WR32('EIM_CS0WCR1,'h05040000);
22.7.4.4 Samsung OneNAND Utility

The following utility algorithms are used on the Samsung OneNAND:

Typical Application
// Unlock Block command
WR16('CS0+('hF100<<1),'h0); // DFS
WR16('CS0+('hF100<<1),'h0); // DBS
WR16('CS0+('hF24c<<1),'h2); // SBA - block number (2)
WR16('CS0+('hF241<<1),'h0); // Clear interrupt status
WR16('CS0+('hF220<<1),'h23); // Unlock command
data ='h0;
while(!(data &'h0004)) // Polling
RD32('WIAR, data); // Read status
// Erase block command
WR16('CS0+('hF100<<1),'h2); // DFS and block ([8:0]) address
WR16('CS0+('hF101<<1),'h0); // DBS
WR16('CS0+('hF220<<1),'h94); // Erase command
data ='h0;
while(!(data &'h0004)) // Wait
// Program page command
WR16('CS0+('hF100<<1),'h2); // DFS and block[8:0] address
WR16('CS0+('hF107<<1),'h0); // sector[1:0] and page[7:2] addresses
WR16('CS0+('hF200<<1),'h800); // buffer[11:8] address and counter[1:0]
WR16('CS0+('hF220<<1),'h80); // Program command
data ='h0;
22.7.5 Access to Samsung UtRAM

Below mentioned configurations are intended for Samsung UtRAM.
22.7.5.1 Samsung UtRAM Asynchronous Mode Configuration

WR32('EIM_CS0RCR1,'h0a010000);
WR32('EIM_CS0RCR2,'h00000008);
22.7.5.2 Samsung UtRAM Synchronous Mode Configuration

RD16('CS0+('hff_ffff<<1),data); // command sequence
RD16('CS0+('hff_ffff<<1),data);
RD16('CS0+('hff_ffff<<1),data);
RD16('CS0+('hff_feff<<1),data);
RD16('CS0+('h00_82a0<<1),data); // memory sync. configuration
WR32('EIM_CS0GCR1,'h4021_53b7); // fixed latency memory wrap 32
WR32('EIM_CS0RCR1,'h0500_0000);
WR32('EIM_CS0WCR1,'h0300_0000);
22.7.6 Access to Spansion Flash

Below mentioned configurations are intended for Spansion Flash.

22.7.6.1 Spansion Flash Asynchronous Mode Configuration

WR32('EIM_CS0GCR1,'h00410081);
WR32('EIM_CS0RCR1,'h0a018000);
WR32('EIM_CS0RCR2,'h00000000);
WR32('EIM_CS0WCR1,'h0704a240);
WR16('CS0+('hF220<<1),'h94); // Erase command
data ='h0;
// Program page command
WR16('CS0+('hF100<<1),'h2); // DFS and block[8:0] address
WR16('CS0+('hF107<<1),'h0); // sector[1:0] and page[7:2] addresses
WR16('CS0+('hF200<<1),'h800); // buffer[11:8] address and counter[1:0]
WR16('CS0+('hF220<<1),'h80); // Program command
data ='h0;
22.7.6.2 Spansion Flash Synchronous Mode Configuration

WR16('CS0+('h0555<<1),'h00aa); // command sequence
WR16('CS0+('h02aa<<1),'h0055);
WR16('CS0+('h0555<<1),'hd0);
WR16('CS0+('h0000<<1),'h1ec4); // memory sync. configuration
WR32('EIM_CS0GCR1,'h50411325); // 66 MHz
WR32('EIM_CS0RCR1,'h05000000); // 5 cycles on memory
22.7.6.3 Spansion Flash Utility

// Single word programming
COMMAND_SEQUENCE(cs,16,'ha0); // single word programming
WR16('CS0+addr, data);
CHECK_STATUS('CS0+addr,data,16,1,errst);
// Write buffer programming
COMMAND_SEQUENCE(0,16,'h25); // write buffer programming
WR16('CS0+addr,'h001f); // counter-1
WR_I('CS0+addr, data, 'h0010_0001, 16); // data
WR16('CS0+addr,'h0029); // write buffer to flash
CHECK_STATUS('CS0+addr+'h3e,data[31:16]+'h00f0,16,1,errst);
There COMMAND_SEQUENCE and CHECK_STATUS are next functions:

task COMMAND_SEQUENCE;
input[2:0] cs;
input[7:0] port_size;
input[31:0] code;
begin
if(port_size == 16)
begin
WR16(csba[cs]+('h0555<<1),'h00aa);
WR16(csba[cs]+('h02aa<<1),'h0055);
WR16(csba[cs]+('h0555<<1),code);
end
else
begin
WR32(csba[cs]+('h0555<<2),'h00aa);

Typical Application
WR32(csba[cs]+('h02aa<<2),'h0055);
WR32(csba[cs]+('h0555<<2),code);
end
end
endtask
task CHECK_STATUS;
input[31:0] addr;
input[31:0] edata;
input[7:0] port_size;
input[7:0] opcode;
output[7:0] errst;
reg[31:0] data;
reg[31:0] data3;
begin
errst = 0;
data = 0;
data3 = 0;
while(!(data == edata) && !errst) // Wait operation
begin: BR_EN
RD16(addr, data); // Read status
if(data[7] !== edata[7])
begin
if(data[5] == 1)
begin
RD16(addr, data3);
RD16(addr, data);
if(data[6] !== data3[6])
begin
$display("CHECK_STATUS: Error timout on single data program");
errst = 1;
disable BR_EN;
end
end
else
begin
if(opcode == 2)
if(data[1] == 1)
begin
RD16(addr, data3);
if(port_size == 32)
RD32(addr, data);
else
RD16(addr, data);
if(data[1] == 1 && data !== edata)
begin
$display("CHECK_STATUS: Error on write buffer");
errst =3;
disable BR_EN;
end
end
end
end
else
begin
RD16(addr, data3);
if(port_size == 32)
RD32(addr, data);
else
begin
RD16(addr, data);
edata[31:16] = 16'h0;
end
if(data !== edata)
begin
$display("CHECK_STATUS: Error in data write on single data program");
errst =2;
disable BR_EN;
end
end
end

end
endtask
22.7.7 8 bit support

This section details the pin connections for Intel mode and Motorola mode.
Intel Mode - For intel mode use the following connection:
Table 22-9. Intel Mode pin connections
Arm platform Pin EIM Pin Notes
ADS# IPP_DO_ADV_B WAL = 1,RAL = 1
W/R IPP_DO_BE_B WBED = 1
WR# WE#
RD# OE#
Mot. Mode - For intel mode use the following connection:

Table 22-10. Motorola Mode pin connections
Arm platform Pin EIM Pin Notes
AS# IPP_DO_CS_B
R/W# WE#
LDS# BE#
22.8 External Bus Timing Diagrams

The following timing diagrams show the timing of accesses to memory or a peripheral
with different timing parameters. All examples done for CS0, but are valid for any others
chip select. BE means one from current used BE[3:0].

External Bus Timing Diagrams
22.8.1 Asynchronous Read Memory Accesses Timing Diagram
EIM clk
ARVALID
ARLEN 0
ARADDR V1
ARREADY
RDATA Last Valid Data V1
RVALID
RLSAT
ADDR Last Valid Address V1
RWSC
CSo
ADV
OE
RW
DATA_IN V1
Figure 22-2. Read Access, RWSC=2,RCSA=0,OEA=0,RCSN=0,OEN=0, RAL=1

22.8.2 Asynchronous Write Memory Accesses Timing Diagram
EIM clk
AWVALID
AWLEN 0
AWADDR V1
AWREADY
WDATA V1
WVALID
WLSAT
AWREADY
ADDR Last Valid Address Write Address 0
WWSC
CSo
WE
ADV
EB
DATA_OUT Last Valid Data Write Data 0
Figure 22-3. Write Access, WWSC=2,WCSA=0,WEA=0,WCSN=0,WEN=0,BEA=0, BEN=0,

WAL=1
22.8.3 Asynchronous Read/Write Memory Accesses Timing

Diagram

EIM CLK
BCLK
RWSC WWSC
ADDR RD Address WR Address
RCSA RCSN WCSA WCSN
CSo
WEA WEN
WE Write
Read
RADVN+RADVA+1 WADVN+WADVA+1
RADVA RADVN+1 WADVA WADVN+1
ADV
OEA OEN
OE
BEA BEN
BE
DATA_IN Read Data
DATA_OUT Last Valid Data Write Data
Figure 22-4.
RCSA=1,RADVA=2,OEA=1,RADVN=1,RCSN=1,OEN=1,WCSA=1,WEA=1,WADVA=1,BEA=
1,WADVN=1,WCSN=1,WEN=1,BEN=1

EIM CLK
BCLK
RWSC WWSC
RCSA RCSN CSREC WCSN
CSo
WEN
WE Write
Read
RADVN+RADVA+1 WADVN+WADVA+1
RADVA RADVN+1 WADVN+1
ADV
OEA OEN
OE
BEN
BE
DATA_IN Read Data
Figure 22-5.
RWSC=5,RCSA=1,RCSN=1,RADVA=1,RADVN=1,OEA=1,OEN=1,WWSC=4,WCSA=0,WCS
N=1,WEA=0,WEN=1,WADVA=1,WADVN=1,BEA=0,BEN=1,CSREC=1

22.8.4 Asynchronous Read/Write Using RAL, WAL and CSREC
EIM CLK
BCLK
RWSC WWSC
RCSA RCSN CSREC WCSA WCSN
CSo
WEN
WE Write
Read
RAL =1 WAL =1
RADVA CSREC
ADV
OEA
OE
BEA BEN
BE
DATA_IN Read Data
Figure 22-6.
RAL=1,RCSN=1,RADVA=2,OEA=1,RCSN=1,CSREC=1,WCSA=1,WEA=0,WADVA=0,BEA=
1,WAL=1,WCSN=1,WEN=1,BEN=1
22.8.5 Consecutive Asynchronous Write Memory Accesses

Timing Diagram

EIM CLK
WWSC WWSC
ADDR Addr0 Addr1
CSo
WE
ADV
BE
DATA_OUT WDo WD1
OE
BCLK
Figure 22-7.
WWSC=4,WCSA=0,WEA=0,WADVA=0,BEA=0,WCSN=0,WEN=0,WADVN=0,BEN=0,CSRE
C=0

EIM CLK
WWSC CSREC WWSC
ADDR Addr0 Addr1
CSo
WE
ADV
Write
BE
DATA_OUT WDo WD1
OE
BCLK
Figure 22-8.
WWSC=4,WCSA=0,WEA=0,WADVA=0,BEA=0,WCSN=0,WEN=0,WADVN=0,BEN=0,CSRE
C=2

EIM CLK
WWSC WWSC
ADDR Addr0 Addr1

WCSA WCSN WCSA
CSo
WEA WEN WEA
WE
WADVA+WADVN+1
ADV
BEA BEN
Write
BE BEA
DATA_OUT WD0 WD1
OE
BCLK
Figure 22-9.
WWSC=7,WCSA=1,WCSN=1,WEA=1,WEN=2,WADVA=0,WADVN=2,BEA=1,BEN=2
22.8.6 Consecutive Asynchronous Read Memory Accesses

Timing Diagram

EIM CLK
RWSC RWSC
ADDR Addr0 Addr1
CSo
OE
ADV
Read
DATA_IN RData0 RData1
BE
WE
BCLK
Figure 22-10. RWSC=4,RCSA=0,OEA=0,RADVA=0,RCSN=0,OEN=0,RADVN=0,CSREC=0
EIM CLK
RWSC CSREC RWSC
ADDR Addr 0 Addr1
CSo
OE
ADV
DATA_IN RData0 RData1
WE
BE
BCLK
Figure 22-11. RWSC=4,RCSA=0,OEA=0,RADVA=0,RCSN=0,OEN=0,RADVN=0,CSREC=2

22.8.7 Burst (Synchronous Mode) Read Memory Accesses

Timing Diagram - BCD=0
Figure 22-12. SRD=1,BCD=0,BCS=0,RWSC=1,RADVA=0,RADVN=0,RFL=0,RL=0

22.8.8 Burst (Synchronous Mode) Read Memory Accesses

Timing Diagram - BCD=1
Figure 22-13. BCD=1, RL = 3


22.8.9 Burst (Synchronous Mode) Write Memory Access Timing -

BCD=1
EIM clock
awvalid
awready
awaddr V1
awlen 1
wvalid
wready
wdata D1 D2
BCLK
CS
WR
ADV
ADDR ADDR
DATA_OUT D1 D2
WAIT

22.8.10 Asynchronous Page Mode Access
ACLK
ARVALID
ARLEN 4
ARADDR V1
ARREADY
RDATA Last Valid Data RD0 RD1 RD2 RD3
RVALID
RLSAT
RREADY
RWSC PAT PAT PAT
ADDR Last Valid Addr A0 A1 A2 A3
DATA_IN RDo RD1 RD2 RD3
CSo
ADV
OEA
OE
Figure 22-14. PAT = 2
22.8.11 DTACK Mode - AXI Single Access

ACLK
ARVALID
ARLEN 0
V1
ARADDR
ARREADY
RDATA V1 Word
RVALID
ADDR Last Valid Addr Address V1
CSo
RW
ADV
OE
DAPS Sync Time
DTACK
DATA_IN V1 Word
Figure 22-15. DAPS = 2

ACLK
ARVALID
ARLEN 0
ARADDR V1
ARREADY
RDATA V1 Word
RVALID
CSo
RW
ADV
OE
Sync Time
DTACK
DATA_IN V1 Word

ACLK
ARVALID
ARLEN 0
ARADDR V1
ARREADY
RDATA V1 Word
RVALID
CSo
RW
ADV
OE
Sync Time
DTACK
DATA_IN V1 Word

22.8.12 DTACK Mode - AXI Single Write Access
ACLK
AWVALID
AWLEN 0
AWADDR V1
AWREADY
WDATA V1 word
WVALID
CSo
OE
ADV
WE
DAPS Sync Time
DTACK
DATA_OUT V1 Word

EIM Memory Map/Register Definition
22.8.13 DTACK Mode - AXI Burst Access
ACLK
ARVALID
ARLEN 1
ARADDR V1
ARREADY
RDATA V1 Word V2 Word
RVALID
ADDR Last Valid Addr Address V1 Address V2
CSo
RW
ADV
OE
DAPS Sync Time DAPS Sync Time
DTACK
DATA_IN V1 Word V2 Word
Figure 22-19. DAPS = 2 CSREC = 2
22.9 EIM Memory Map/Register Definition

The EIM includes 33 user-accessible 32-bit registers. The the EIM Configuration
Register (EIM_WCR) contains control bits that configure the EIM for certain operation
modes.
The 160 bits used to control Individual Chip Select are divided into five registers:
• Chip Select n General Configuration Register 1 (EIM_CSnGCR1)
• Chip Select n General Configuration Register 2 (EIM_CSnGCR2)
• Chip Select n Read Configuration Register 1 (EIM_CSnRCR1)
• Chip Select n Read Configuration Register 2 (EIM_CSnRCR2)
• Chip Select n Write Configuration Register (EIM_CSnWCR)
In addition there are 3 general registers: EIM_WCR, EIM_WIAR, and EIM_EAR.
NOTE
• All EIM registers are sampled by IPG_CLK_S, therefore
IPG_CLK_S must be active when accessing through IP
bus.
• Read access from all registers (except EIM_WIAR and
EIM_EAR) will generate one IPG_XFR_WAIT cycle.
• Read access from EIM_WIAR and EIM_EAR will
generate six IPG_XFR_WAIT cycles.
• Write access to all registers (except EIM_EAR) will
generate three IPG_XFR_WAIT cycles.
• Write access to EIM_EAR will generate six
IPG_XFR_WAIT cycles.
EIM memory map
Absolute
Width Section/
(in bits) page
(hex)
Chip Select n General Configuration Register 1
21B_8000 32 R/W 0061_0088h 22.9.1/883
(EIM_CS0GCR1)
21B_8004 32 R/W 0000_1010h 22.9.2/887
(EIM_CS0GCR2)
Chip Select n Read Configuration Register 1
21B_8008 32 R/W 1C00_2000h 22.9.3/888
(EIM_CS0RCR1)
21B_800C 32 R/W 0000_0000h 22.9.4/891
(EIM_CS0RCR2)
Chip Select n Write Configuration Register 1
21B_8010 32 R/W 1C00_0000h 22.9.5/892
(EIM_CS0WCR1)
21B_8014 32 R/W 0000_0000h 22.9.6/895
(EIM_CS0WCR2)
21B_8018 32 R/W 0061_0088h 22.9.1/883
(EIM_CS1GCR1)

EIM memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
21B_801C 32 R/W 0000_1010h 22.9.2/887
(EIM_CS1GCR2)
21B_8020 32 R/W 1C00_2000h 22.9.3/888
(EIM_CS1RCR1)
21B_8024 32 R/W 0000_0000h 22.9.4/891
(EIM_CS1RCR2)
21B_8028 32 R/W 1C00_0000h 22.9.5/892
(EIM_CS1WCR1)
21B_802C 32 R/W 0000_0000h 22.9.6/895
(EIM_CS1WCR2)
21B_8030 32 R/W 0061_0088h 22.9.1/883
(EIM_CS2GCR1)
21B_8034 32 R/W 0000_1010h 22.9.2/887
(EIM_CS2GCR2)
21B_8038 32 R/W 1C00_2000h 22.9.3/888
(EIM_CS2RCR1)
21B_803C 32 R/W 0000_0000h 22.9.4/891
(EIM_CS2RCR2)
21B_8040 32 R/W 1C00_0000h 22.9.5/892
(EIM_CS2WCR1)
21B_8044 32 R/W 0000_0000h 22.9.6/895
(EIM_CS2WCR2)
21B_8048 32 R/W 0061_0088h 22.9.1/883
(EIM_CS3GCR1)
21B_804C 32 R/W 0000_1010h 22.9.2/887
(EIM_CS3GCR2)
21B_8050 32 R/W 1C00_2000h 22.9.3/888
(EIM_CS3RCR1)
21B_8054 32 R/W 0000_0000h 22.9.4/891
(EIM_CS3RCR2)
21B_8058 32 R/W 1C00_0000h 22.9.5/892
(EIM_CS3WCR1)
21B_805C 32 R/W 0000_0000h 22.9.6/895
(EIM_CS3WCR2)
21B_8090 EIM Configuration Register (EIM_WCR) 32 R/W 0000_0020h 22.9.7/896
21B_8094 EIM IP Access Register (EIM_WIAR) 32 R/W 0000_0010h 22.9.8/897
21B_8098 Error Address Register (EIM_EAR) 32 R/W 0000_0000h 22.9.9/898

22.9.1 Chip Select n General Configuration Register 1

(EIM_CSnGCR1)
Address: 21B_8000h base + 0h offset + (24d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSZ WP GBC AUS CSREC SP DSZ

W
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSEN
BCS BCD WC BL CREP CRE RFL WFL MUM SRD SWR
W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
EIM_CSnGCR1 field descriptions

Field Description
31–28 Page Size. This bit field indicates memory page size in words (word is defined by the DSZ field). PSZ is
PSZ used when fix latency mode is applied, WFL=1 for sync. write accesses, RFL=1 for sync. Read accesses.
When working in fix latency mode WAIT signal from the external device is not being monitored, PSZ is
used to determine if page boundary is reached and renewal of access is preformed. This bit field is
ignored when sync. Mode is disabled or fix latency mode is not being used for write or read access
separately.
It can be valid for both access type, read or write, or only for one type, according to configuration. PSZ is
cleared by a hardware reset.
0000 8 words page size

0111 1024 (1k) words page size
1000 2048 (2k) words page size
1001 - 1111 Reserved
27 Write Protect. This bit prevents writes to the address range defined by the corresponding chip select. WP
WP is cleared by a hardware reset.
0 Writes are allowed in the memory range defined by chip.

1 Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error
response and no assertion of the chip select output.
26–24 Gap Between Chip Selects. This bit field, according to the settings shown below, determines the minimum
GBC time between end of access to the current chip select and start of access to different chip select. GBC is

EIM_CSnGCR1 field descriptions (continued)

Field Description
Example settings:
000 minimum of 0 EIM clock cycles before next access from different chip select (async. mode only)
001 minimum of 1 EIM clock cycles before next access from different chip select
23 Address UnShifted. This bit indicates an unshifted mode for address assertion for the relevant chip select
AUS accesses. AUS bit is cleared by hardware reset.
0 Address shifted according to port size (DSZ config) (128 Mbyte maximum supported memory density).
1 Address unshifted (32 Mbyte maximum supported memory density).
22–20 CS Recovery. This bit field, according to the settings shown below, determines the minimum pulse width
CSREC of CS, OE, and WE control signals before executing a new back to back access to the same chip select.
CSREC is cleared by a hardware reset.
NOTE: The reset value for EIM_CS0GCR1, CSREC[2:0] is 0b110. For EIM_CS1GCR1 - EIM_CS5GCR,
the reset value is 0b000.
Example settings:
000 0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only)
001 1 EIM clock cycles minimum width of CS, OE and WE signals
19 Supervisor Protect. This bit prevents accesses to the address range defined by the corresponding chip
SP select when the access is attempted in the User mode. SP is cleared by a hardware reset.
0 User mode accesses are allowed in the memory range defined by chip select.
1 User mode accesses are prohibited. All attempts to access an address mapped by this chip select in
User mode results in an error response and no assertion of the chip select output.
18–16 Data Port Size. This bit field defines the width of an external device's data port as shown below.
DSZ
NOTE: Only async. access supported for 8 bit port.
NOTE: The reset value for EIM_CS0GCR1, DSZ[2] = 0, DSZ[1:0] = EIM_BOOT[1:0]. For EIM_CS1GCR1
- EIM_CS5GCR1, the reset value is 0b001.
000 Reserved.
001 16 bit port resides on DATA[15:0]
15–14 Burst Clock Start. When SRD=1 or SWR=1,this bit field determines the number of EIM clock cycles delay
BCS from start of access before the first rising edge of BCLK is generated.
When BCD=0 value of BCS=0 results in a half clock delay after the start of access. For other values of
BCD a one clock delay after the start of access is applied, not an immediate assertion. BCS is cleared by
a hardware reset.
00 0 EIM clock cycle additional delay



Field Description
13–12 Burst Clock Divisor. This bit field contains the value used to program the burst clock divisor for BCLK
BCD generation. It is used to divide the internal EIMbus frequency. BCD is cleared by a hardware reset.
NOTE: For other then the mentioned below frequency such as 104 MHz, EIM clock (input clock) should
be adjust accordingly.
00 Divide EIM clock by 1

11 Write Continuous. The WI bit indicates that write access to the memory are always continuous accesses
WC regardless of the BL field value. WI is cleared by hardware reset.
0 Write access burst length occurs according to BL value.

1 Write access burst length is continuous.
10–8 Burst Length. The BL bit field indicates memory burst length in words (word is defined by the DSZ field)
BL and should be properly initialized for mixed wrap/increment accesses support. Continuous BL value
corresponds to continuous burst length setting of the external memory device. For fix memory burst size,
type is always wrap. In case not matching wrap boundaries in both the memory (BL field) and Master
access on the current address, EIM update address on the external device address bus and regenerates
the access.
BL is cleared by a hardware reset.
When APR=1, Page Read Mode is applied, BL determine the number of words within the read page burst.
BL is cleared by a hardware reset for EIM_CS0GCR1 - EIM_CS5GCR1.
000 4 words Memory wrap burst length (read page burst size when APR = 1)
100 Continuous burst length (2 words read page burst size when APR = 1)
101 Reserved
110 Reserved
111 Reserved
7 Configuration Register Enable Polarity. This bit indicates CRE memory pin assertion state, active-low or
CREP active-high, while executing a memory register set command to the external device (PSRAM memory
type). CREP is set by a hardware reset.
NOTE: Whenever PSRAM is connected the CREP value must be correct also for accesses where CRE
is disabled.
For Non-PSRAM memory CREP value should be 1.
0 CRE signal is active low

1 CRE signal is active high
6 Configuration Register Enable. This bit indicates CRE memory pin state while executing a memory
CRE register set command to PSRAM external device. CRE is cleared by a hardware reset.


Field Description
0 CRE signal use is disable
1 CRE signal use is enable
5 Read Fix Latency. This bit field determine if the controller is monitoring the WAIT signal from the External
RFL device connected to the chip select (handshake mode - fix or variable data latency) or if it start sampling
data according to RWSC field, it only valid in synchronous mode. RFL is cleared by a hardware reset.
When RFL=1 Burst access is terminated on page boundary and resume on the following page according
to BL bit field configuration, because WAIT signal is not monitored from the external device.
0 the External device WAIT signal is being monitored, and it reflect the external data bus state
1 the state of the External devices is determined internally (Fix latency mode only)
4 Write Fix Latency. This bit field determine if the controller is monitoring the WAIT signal from the External
WFL device connected to the chip select (handshake mode - fix or variable data latency) or if it start data
transfer according to WWSC field, it only valid in synchronous mode. WFL is cleared by a hardware reset.
When WFL=1 Burst access is terminated on page boundary and resume on the following page according
to BL bit field configuration, because WAIT signal is not monitored from the external device
0 the External device WAIT signal is being monitored, and it reflect the external data bus state
1 the state of the External devices is determined internally (Fix latency mode only)
3 Multiplexed Mode. This bit determines the address/data multiplexed mode for asynchronous and
MUM synchronous accesses for 8 bit, 16 bit or 32 bit devices (DSZ config. dependent).
NOTE: The reset value for EIM_CS0GCR1[MUM] = EIM_BOOT[2]. For EIM_CS1GCR1 -

EIM_CS5GCR1 the reset value is 0.
0 Multiplexed Mode disable

1 Multiplexed Mode enable
2 Synchronous Read Data. This bit field determine the read accesses mode to the External device of the
SRD chip select. The External device should be configured to the same mode as this bit implicates. SRD is
NOTE: Sync. accesses supported only for 16/32 bit port.
0 read accesses are in Asynchronous mode

1 read accesses are in Synchronous mode
1 Synchronous Write Data. This bit field determine the write accesses mode to the External device of the
SWR chip select. The External device should be configured to the same mode as this bit implicates. SWR is
NOTE: Sync. accesses supported only for 16/32 bit port.
0 write accesses are in Asynchronous mode

1 write accesses are in Synchronous mode
0 CS Enable. This bit controls the operation of the chip select pin. CSEN is set by a hardware reset for
CSEN CSGCR0 to allow external boot operation. CSEN is cleared by a hardware reset to CSGCR1-CSGCR5.
NOTE: Reset value for EIM_CS0GCR1 for CSEN is 1. For EIM_CS1GCR1-CS1GCR5 reset value is 0.
0 Chip select function is disabled; attempts to access an address mapped by this chip select results in
an error respond and no assertion of the chip select output
1 Chip select is enabled, and is asserted when presented with a valid access.

22.9.2 Chip Select n General Configuration Register 2

(EIM_CSnGCR2)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX16_BYP_
R 0 0 0
GRANT
DAP DAE DAPS ADH

W
Reset 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
EIM_CSnGCR2 field descriptions

Field Description
Reserved
12 Muxed 16 bypass grant. This bit when asserted causes EIM to bypass the grant/ack. arbitration with NFC
MUX16_BYP_ (only for 16 bit muxed mode accesses).
GRANT
0 EIM waits for grant before driving a 16 bit muxed mode access to the memory.
1 EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory.
Reserved
9 Data Acknowledge Polarity. This bit indicates DTACK memory pin assertion state, active-low or active-
DAP high, while executing an async access using DTACK signal from the external device. DAP is cleared by a
hardware reset.
0 DTACK signal is active high

1 DTACK signal is active low
8 Data Acknowledge Enable. This bit indicates external device is using DTACK pin as strobe/terminator of
DAE an async. access. DTACK signal may be used only in asynchronous single read (APR=0) or write
accesses. DTACK poling start point is set by DAPS bit field. polarity of DTACK is set by DAP bit field. DAE
is cleared by a hardware reset.
0 DTACK signal use is disable

1 DTACK signal use is enable
7–4 Data Acknowledge Poling Start. This bit field determine the starting point of DTACK input signal polling.
DAPS DAPS is used only in asynchronous single read or write accesses.


Field Description
NOTE: Since DTACK is an async. signal the start point of DTACK signal polling is at least 3 cycles after
the start of access.
DAPS is cleared by a hardware reset.
Example settings:
0000 3 EIM clk cycle between start of access and first DTACK check
0001 4 EIM clk cycles between start of access and first DTACK check
Reserved
ADH Address hold time - This bit field determine the address hold time after ADV negation when mum = 1
(muxed mode).
When mum = 0 this bit has no effect. For read accesses the field determines when the pads direction will
be switched.
NOTE: Reset value for EIM_CS0GCR2 for ADH is 0b10. For EIM_CS1GCR2-EIM_CS5GCR2 reset
value is 0b00.
00 0 cycle after ADV negation

11 Reserved
22.9.3 Chip Select n Read Configuration Register 1

(EIM_CSnRCR1)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
RWSC RADVA RAL RADVN
W
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0
OEA OEN RCSA RCSN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
EIM_CSnRCR1 field descriptions

Field Description
Reserved

EIM_CSnRCR1 field descriptions (continued)

Field Description
29–24 Read Wait State Control. This bit field programs the number of wait-states, according to the settings
RWSC shown below, for synchronous or asynchronous read access to the external device connected to the chip
select.
When SRD=1 and RFL=0, RWSC indicates the number of burst clock (BCLK) cycles from the start of an
access, before the controller can start sample data.Since WAIT signal can be asserted one cycle before
the first data can be sampled, the controller starts evaluating the WAIT signal state one cycle before, this
is referred as handshake mode or variable latency mode.
When SRD=1 and RFL=1, RWSC indicates the number of burst clock (BCLK) cycles from the start of an
access, until the external device is ready for data transfer, this is referred as fix latency mode.
When SRD=0, RFL bit is ignored, RWSC indicates the asynchronous access length and the number of
EIM clock cycles from the start of access until the external device is ready for data transfer.
RWSC is cleared by a hardware reset.
NOTE: The reset value for EIM_CS0RCR1, RWSC[5:0] = 0b011100. For CG1RCR1 - CS1RCR5 the
reset value is 0b000000.
Example settings:
000000 Reserved
000001 RWSC value is 1
Reserved
22–20 ADV Assertion. This bit field determines when ADV signal is asserted for synchronous or asynchronous
RADVA read modes according to the settings shown below. RADVA is cleared by a hardware reset.
Example settings:
000 0 EIM clock cycles between beginning of access and ADV assertion
19 Read ADV Low. This bit field determine ADV signal negation time. When RAL=1, RADVN bit field is
RAL ignored and ADV signal will stay asserted until end of access. When RAL=0 negation of ADV signal is
according to RADVN bit field configuration.
18–16 ADV Negation. This bit field determines when ADV signal to memory is negated during read accesses.
RADVN
When SRD=1 (synchronous read mode), ADV negation occurs according to the following formula:
(RADVN + RADVA + BCD + BCS + 1) EIM clock cycles from start of access.
When asynchronous read mode is applied (SRD=0) and RAL=0 ADV negation occurs according to the
following formula: (RADVN + RADVA + 1) EIM clock cycles from start of access. RADVN is cleared by a
hardware reset.
NOTE: The reset value for EIM_CS0RCR1[RADVN] = 0b010. For EIM_CS1RCR1 - EIM_CS5RCR1, the
reset value is 0b000.
NOTE: This field should be configured so ADV negation will occur before the end of access. For ADV
negation at the same time with the end of access user should RAL bit.


Field Description
Reserved
14–12 OE Assertion. This bit field determines when OE signal are asserted during read cycles (synchronous or
OEA asynchronous mode), according to the settings shown below. OEA is cleared by a hardware reset.
In muxed mode OE assertion occurs (OEA + RADVN + RADVA + ADH +1) EIM clock cycles from start of
access.
NOTE: The reset value for EIM_CS0RCR1[OEA] is 0b000 if EIM_BOOT[2] = 0. If EIM_BOOT[2] is 1, the
reset value for EIM_CS0RCR1[OEA] is 0b010. The reset value of this field for EIM_CS1RCR1 -
EIM_CS5RCR1 is 0b000.
Example settings:
000 0 EIM clock cycles between beginning of access and OE assertion

Reserved
10–8 OE Negation. This bit field determines when OE signal is negated during read cycles in asynchronous
OEN single mode only (SRD=0 and APR = 0), according to the settings shown below. This bit field is ignored
when SRD=1. OEN is cleared by a hardware reset.
Example settings:
000 0 EIM clock cycles between end of access and OE negation

Reserved
6–4 Read CS Assertion. This bit field determines when CS signal is asserted during read cycles (synchronous
RCSA or asynchronous mode), according to the settings shown below. RCSA is cleared by a hardware reset.
Example settings:
000 0 EIM clock cycles between beginning of read access and CS assertion
Reserved
RCSN Read CS Negation. This bit field determines when CS signal is negated during read cycles in
asynchronous single mode only (SRD=0 and APR = 0), according to the settings shown below. This bit
field is ignored when SRD=1. RCSN is cleared by a hardware reset.
Example settings:
000 0 EIM clock cycles between end of read access and CS negation

22.9.4 Chip Select n Read Configuration Register 2

(EIM_CSnRCR2)
Address: 21B_8000h base + Ch offset + (24d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
APR PAT RL RBEA RBE RBEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EIM_CSnRCR2 field descriptions

Field Description
Reserved
15 Asynchronous Page Read. This bit field determine the asynchronous read mode to the external device.
APR When APR=0, the async. read access is done as single word (where word is defined by the DSZ field).
when APR=1, the async. read access executed as page read. page size is according to BL field config.,
RCSN,RBEN,OEN and RADVN are being ignored.
APR is cleared by a hardware reset for EIM_CS1GCR1 - EIM_CS5GCR1.
NOTE: SRD=0 and MUM=0 must apply when APR=1

14–12 Page Access Time. This bit field is used in Asynchronous Page Read mode only (APR=1). the initial
PAT access is set by RWSC as in regular asynchronous mode. the consecutive address assertions width
determine by PAT field according to the settings shown below. when APR=0 this field is ignored.
PAT is cleared by a hardware reset for EIM_CS1GCR1 - EIM_CS5GCR1.
000 Address width is 2 EIM clock cycles

Reserved
9–8 Read Latency. This bit field indicates cycle latency when executing a synchronous read operation.
RL
The fields holds the feedback clock loop delay in aclk cycle units.
This field is cleared by a hardware reset.
00 Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0
01 Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0


Field Description
Reserved
6–4 Read BE Assertion. This bit field determines when BE signal is asserted during read cycles (synchronous
RBEA or asynchronous mode), according to the settings shown below. RBEA is cleared by a hardware reset.
Example settings:
000 0 EIM clock cycles between beginning of read access and BE assertion
3 Read BE enable. This bit field determines if BE will be asserted during read access.
RBE
0 BE are disabled during read access.
1 BE are enable during read access according to value of RBEA and RBEN bit fields.
RBEN Read BE Negation. This bit field determines when BE signal is negated during read cycles in
asynchronous single mode only (SRD=0 and APR=0), according to the settings shown below. This bit field
is ignored when SRD=1. RBEN is cleared by a hardware reset.
Example settings:
000 0 EIM clock cycles between end of read access and BE negation
22.9.5 Chip Select n Write Configuration Register 1

(EIM_CSnWCR1)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
WBED
WAL WWSC WADVA WADVN WBEA

W
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WBE
WBEN WEA WEN WCSA WCSN
A
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EIM_CSnWCR1 field descriptions

Field Description
31 Write ADV Low. This bit field determine ADV signal negation time in write accesses. When WAL=1,
WAL WADVN bit field is ignored and ADV signal will stay asserted until end of access. When WAL=0 negation
of ADV signal is according to WADVN bit field configuration.
30 Write Byte Enable Disable. When asserted this bit prevent from IPP_DO_BE_B[x] to be asserted during
WBED write accesses.This bit is cleared by hardware reset.
29–24 Write Wait State Control. This bit field programs the number of wait-states, according to the settings
WWSC shown below, for synchronous or asynchronous write access to the external device connected to the chip
select.
When SWR=1 and WFL=0, WWSC indicates the number of burst clock (BCLK) cycles from the start of an
access, before the memory can sample the first data.Since WAIT signal can be asserted one cycle before
the first data can be sampled, the controller starts evaluating the WAIT signal state one cycle before, this
is referred as handshake mode or variable latency mode.
When SWR=1 and WFL=1, WWSC indicates the number of burst clock (BCLK) cycles from the start of an
access, until the external device is ready for data transfer, this is referred as fix latency mode.
When SWR=0, WFL bit is ignored, WWSC indicates the asynchronous access length and the number of
EIM clock cycles from the start of access until the external device is ready for data transfer.
WWSC is cleared by a hardware reset.
NOTE: The reset value for EIM_CS0WCR1, WWSC[5:0] = 0b011100. For EIM_CS1WCR1 -
EIM_CS5WCR1, the reset value of this field is 0b000000.
Example settings:
000000 Reserved
000001 WWSC value is 1
23–21 ADV Assertion. This bit field determines when ADV signal is asserted for synchronous or asynchronous
WADVA write modes according to the settings shown below. WADVA is cleared by a hardware reset.
Example settings:
20–18 ADV Negation. This bit field determines when ADV signal to memory is negated during write accesses.
WADVN
When SWR=1 (synchronous write mode), ADV negation occurs according to the following formula:
(WADVN + WADVA + BCD + BCS + 1) EIM clock cycles.
When asynchronous read mode is applied (SWR=0) ADV negation occurs according to the following
formula: (WADVN + WADVA + 1) EIM clock cycles.
NOTE: Reset value for EIM_CS0WCR for WADVN is 0b010. For EIM_CS1WCR - EIM_CS5WCR reset
value is 0b000.
NOTE: This field should be configured so ADV negation will occur before the end of access. For ADV
negation at the same time as the end of access, S/W should set the WAL bit.
17–15 BE Assertion. This bit field determines when BE signal is asserted during write cycles in async. mode only
WBEA (SWR=0), according to the settings shown below. BEA is cleared by a hardware reset.

EIM_CSnWCR1 field descriptions (continued)

Field Description
NOTE: Reset value for EIM_CS0WCR for WBEA is 0b010. For EIM_CS1WCR - EIM_CS5WCR reset
value is 0b000.
Example settings:
000 0 EIM clock cycles between beginning of access and BE assertion

14–12 BE[3:0] Negation. This bit field determines when BE[3:0] bus signal is negated during write cycles in
WBEN asynchronous mode only (SWR=0), according to the settings shown below. This bit field is ignored when
SWR=1. BEN is cleared by a hardware reset.
NOTE: Reset value for EIM_CS0WCR for WBEN is 0b010. For EIM_CS1WCR - EIM_CS5WCR reset
value is 0b000.
Example settings:
000 0 EIM clock cycles between end of access and BE negation

11–9 WE Assertion. This bit field determines when WE signal is asserted during write cycles (synchronous or
WEA asynchronous mode), according to the settings shown below. This bit field is ignored when executing a
read access to the external device. WEA is cleared by a hardware reset.
NOTE: Reset value for EIM_CS0WCR for WEA is 0b010. For EIM_CS1WCR - EIM_CS5WCR reset
value is 0b000.
Example settings:
000 0 EIM clock cycles between beginning of access and WE assertion

111 7 EIMclock cycles between beginning of access and WE assertion
8–6 WE Negation. This bit field determines when WE signal is negated during write cycles in asynchronous
WEN mode only (SWR=0), according to the settings shown below. This bit field is ignored when SWR=1. WEN
NOTE: Reset value for EIM_CS0WCR for WEN is 0b010. For EIM_CS1WCR - EIM_CS5WCR reset
value is 0b000.
Example settings:
000 0 EIM clock cycles between end of access and WE negation

5–3 Write CS Assertion. This bit field determines when CS signal is asserted during write cycles (synchronous
WCSA or asynchronous mode), according to the settings shown below.this bit field is ignored when executing a
read access to the external device. WCSA is cleared by a hardware reset.
Example settings:
000 0 EIM clock cycles between beginning of write access and CS assertion

EIM_CSnWCR1 field descriptions (continued)

Field Description
111 7 EIMclock cycles between beginning of write access and CS assertion
WCSN Write CS Negation. This bit field determines when CS signal is negated during write cycles in
asynchronous mode only (SWR=0), according to the settings shown below. This bit field is ignored when
SWR=1. WCSN is cleared by a hardware reset.
Example settings:
22.9.6 Chip Select n Write Configuration Register 2

(EIM_CSnWCR2)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
WBCDD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EIM_CSnWCR2 field descriptions

Field Description
Reserved
0 Write Burst Clock Divisor Decrement. If this bit is asserted and BCD value is 0 sync. write access will be
WBCDD preformed as if BCD value is 1.When this bit is negated or BCD value is not 0 this bit has no affect.
This bit is cleared by hardware reset.

22.9.7 EIM Configuration Register (EIM_WCR)

Address: 21B_8000h base + 90h offset = 21B_8090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDOG_EN
R 0 0 0
INTPOL
INTEN
WDOG_
GBCD BCM
LIMIT
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
EIM_WCR field descriptions

Field Description
Reserved
10–9 Memory Watchdog (WDOG) cycle limit.
WDOG_LIMIT
This bit field determines the number of BCLK cycles (ACLK cycles in dtack mode) before the WDOG
counter terminates the access and send an error response to the master.
00 128 BCLK cycles

01 256 BCLK cycles
10 512 BCLK cycles
11 1024 BCLK cycles
8 Memory WDOG enable.
WDOG_EN
This bit controls the operation of the wdog counter that terminates the EIM access.
0 Memory WDOG is Disabled

1 Memory WDOG is Enabled
Reserved
5 Interrupt Polarity. This bit field determines the polarity of the external device interrupt.
INTPOL
0 External interrupt polarity is active low
1 External interrupt polarity is active high
4 Interrupt Enable. When this bit is set the External signal RDY_INT as active interrupt. When interrupt
INTEN occurs, INT bit at the WCR will be set and t EIM_EXT_INT signal will be asserted correspondingly. This bit
0 External interrupt Disable

1 External interrupt Enable

EIM_WCR field descriptions (continued)

Field Description
Reserved
2–1 General Burst Clock Divisor. When BCM bit is set, this bit field contains the value used to program the
GBCD burst clock divisor for Continuous BCLK generation. The other BCD bit fields for each chip select are
ignored. It is used to divide the internal AXI bus frequency. When BCM=0 GBCD bit field has no influence.
GBCD is cleared by a hardware reset.

0 Burst Clock Mode. This bit selects the burst clock mode of operation. It is used for system debug mode.
BCM
BCM is cleared by a hardware reset.
NOTE: The BCLK frequency in this mode is according to GBCD bit field.
NOTE: The BCLK phase is opposite to the EIM clock in this mode if GBCD is 0.
NOTE: This bit should be used only in async. accesses. No sync access can be executed if this bit is set.
NOTE: When this bit is set bcd field shouldn't be configured to 0.
0 The burst clock runs only when accessing a chip select range with the SWR/SRD bits set. When the
burst clock is not running it remains in a logic 0 state. When the burst clock is running it is configured
by the BCD and BCS bit fields in the chip select Configuration Register.
1 The burst clock runs whenever ACLK is active (independent of chip select configuration)
22.9.8 EIM IP Access Register (EIM_WIAR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
ACLK_EN
R
ERRST
IPS_ IPS_
INT
ACK REQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

EIM_WIAR field descriptions

Field Description
Reserved
4 ACLK enable. This bit gates the ACLK for the EIM except from FFs that get ipg_aclk_s. After reset ACLK
ACLK_EN is enabled.
0 ACLK is disabled
1 ACLK is enabled
3 READY After Reset. This bit controls the initial ready/busy status for external devices on CS0 immediately
ERRST after hardware reset. This is a sticky bit which is cleared once the RDY_INT signal is asserted by the
external device.
When ERRST = 1 the first fetch access from EIM to the external device located on CS0 will be pending
until RDY_INT signal indicates that the external device is ready, then EIM will execute the access.
0 RDY_INT After Reset Disable

1 RDY_INT After Reset Enable
2 Interrupt. This bit indicates interrupt assertion by an external device according to RDY_INT signal. When
INT polling this bit, INT=0 indicates interrupt not occurred and INT=1 indicates assertion of the external device
interrupt. This bit is cleared by a hardware reset.
1 IPS ACK. The EIM is ready for ips access. There is no active AXI access and no new AXI access is
IPS_ACK accepted till this bit is cleared. This bit is cleared by the master after it completes the ips accesses.
0 Master cannot access ips.

1 Master can access ips.
0 IPS request. The Master requests to access one of the IPS registers. During such access the EIM should
IPS_REQ not perform any AXI/memory accesses. The EIM finishes the AXI accesses that already starts and asserts
the IPS_ACK bit.
0 No Master requests ips access

1 Master requests ips access
22.9.9 Error Address Register (EIM_EAR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Error_ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EIM_EAR field descriptions

Field Description
Error_ADDR Error Address. This bit field holds the AXI address of the last access that caused error. This register is
read only register.

Chapter 23
10/100/1000-Mbps Ethernet MAC (ENET)
23.1 Introduction
The MAC-NET core, in conjunction with a 10/100/1000-Mbit/s MAC, implements layer
3 network acceleration functions. These functions are designed to accelerate the
processing of various common networking protocols, such as IP, TCP, UDP, and ICMP,
providing wire speed services to client applications.
23.2 Overview
The core implements a triple-speed 10/100/1000-Mbit/s Ethernet MAC compliant with
the IEEE802.3-2002 standard. The MAC layer provides compatibility with half- or full-
duplex 10/100-Mbit/s and full-duplex gigabit Ethernet LANs.
The MAC operation is fully programmable and can be used in Network Interface Card
(NIC), bridging, or switching applications. The core implements the remote network
monitoring (RMON) counters according to IETF RFC 2819.
The core also implements a hardware acceleration block to optimize the performance of
network controllers providing TCP/IP, UDP, and ICMP protocol services. The
acceleration block performs critical functions in hardware, which are typically
implemented with large software overhead.
The core implements programmable embedded FIFOs that can provide buffering on the
receive path for lossless flow control.
Advanced power management features are available with magic packet detection and
programmable power-down modes.
A unified DMA (uDMA), internal to the ENET module, optimizes data transfer between
the ENET core and the SoC, and supports an enhanced buffer descriptor programming
model to support IEEE 1588 functionality.

Overview
The programmable Ethernet MAC with IEEE 1588 integrates a standard IEEE 802.3
Ethernet MAC with a time-stamping module. The IEEE 1588 standard provides accurate
clock synchronization for distributed control nodes for industrial automation applications.
23.2.1 Features
The MAC-NET core includes the following features.
23.2.1.1 Ethernet MAC features

• Implements the full 802.3 specification with preamble/SFD generation, frame
padding generation, CRC generation and checking
• Supports zero-length preamble
• Dynamically configurable to support 10/100-Mbit/s and gigabit operation
• Supports 10/100 Mbit/s full-duplex and configurable half-duplex operation
• Supports gigabit full-duplex operation
• Compliant with the AMD magic packet detection with interrupt for node remote
power management
• Seamless interface to commercial ethernet PHY devices via one of the following:
• a 4-bit Media Independent Interface (MII) operating at 2.5/25 MHz.
• a 4-bit non-standard MII-Lite (MII without the CRS and COL signals) operating
at 2.5/25 MHz.
• a 2-bit Reduced MII (RMII) operating at 50 MHz.
• a (double data rate) 4-bit Reduced GMII (RGMII) operating at 125 MHz.
• Simple 64-Bit FIFO user-application interface
• CRC-32 checking at full speed with optional forwarding of the frame check sequence
(FCS) field to the client
• CRC-32 generation and append on transmit or forwarding of user application
provided FCS selectable on a per-frame basis
• In full-duplex mode:
• Implements automated pause frame (802.3 x31A) generation and termination,
providing flow control without user application intervention
• Pause quanta used to form pause frames — dynamically programmable
• Pause frame generation additionally controllable by user application offering
flexible traffic flow control
• Optional forwarding of received pause frames to the user application
• Implements standard flow-control mechanism
• In half-duplex mode: provides full collision support, including jamming, backoff,
and automatic retransmission
• Supports VLAN-tagged frames according to IEEE 802.1Q

Chapter 23 10/100/1000-Mbps Ethernet MAC (ENET)
• Programmable MAC address: Insertion on transmit; discards frames with

mismatching destination address on receive (except broadcast and pause frames)
• Programmable promiscuous mode support to omit MAC destination address
checking on receive
• Multicast and unicast address filtering on receive based on 64-entry hash table,
reducing higher layer processing load
• Programmable frame maximum length providing support for any standard or
proprietary frame length
• Statistics indicators for frame traffic and errors (alignment, CRC, length) and pause
frames providing for IEEE 802.3 basic and mandatory management information
database (MIB) package and remote network monitoring (RFC 2819)
• Simple handshake user application FIFO interface with fully programmable depth
and threshold levels
• Provides separate status word for each received frame on the user interface providing
information such as frame length, frame type, VLAN tag, and error information
• Multiple internal loopback options
• MDIO master interface for PHY device configuration and management supports two
programmable MDIO base addresses, and standard (IEEE 802.3 Clause 22) and
extended (Clause 45) MDIO frame formats
• Supports legacy FEC buffer descriptors
23.2.1.2 IP protocol performance optimization features

• Operates on TCP/IP and UDP/IP and ICMP/IP protocol data or IP header only
• Enables wire-speed processing
• Supports IPv4 and IPv6
• Transparent passing of frames of other types and protocols
• Supports VLAN tagged frames according to IEEE 802.1q with transparent
forwarding of VLAN tag and control field
• Automatic IP-header and payload (protocol specific) checksum calculation and
verification on receive
• Automatic IP-header and payload (protocol specific) checksum generation and
automatic insertion on transmit configurable on a per-frame basis
• Supports IP and TCP, UDP, ICMP data for checksum generation and checking
• Supports full header options for IPv4 and TCP protocol headers

Overview
• Provides IPv6 support to datagrams with base header only — datagrams with
extension headers are passed transparently unmodifed/unchecked
• Provides statistics information for received IP and protocol errors
• Configurable automatic discard of erroneous frames
• Configurable automatic host-to-network (RX) and network-to-host (TX) byte order
conversion for IP and TCP/UDP/ICMP headers within the frame
• Configurable padding remove for short IP datagrams on receive
• Configurable Ethernet payload alignment to allow for 32-bit word-aligned header
and payload processing
• Programmable store-and-forward operation with clock and rate decoupling FIFOs
23.2.1.3 IEEE 1588 features

• Supports all IEEE 1588 frames.
• Allows reference clock to be chosen independently of network speed.
• Software-programmable precise time-stamping of ingress and egress frames
• Timer monitoring capabilities for system calibration and timing accuracy
management
• Precise time-stamping of external events with programmable interrupt generation
• Programmable event and interrupt generation for external system control
• Supports hardware- and software-controllable timer synchronization.
• Provides a 4-channel IEEE 1588 timer. Each channel supports input capture and
output compare using the 1588 counter.

23.2.2 Block diagram
uDMA TOE functions MAC
MII/RMII/RGMII
RX control
application
TCP/IP
interface
Receive
interface
receive
RX performance
FIFO
optimization
CRC Pause frame
AHB check terminate
system
bus I/F
MII/RMII/RGMII
TX control
application
TCP/IP
interface
interface
Transmit
transmit
TX performance
FIFO optimization
CRC Pause frame
generate generate
management
interface
Configuration MDIO
PHY
statistics master
Register interface
Figure 23-1. Ethernet MAC-NET core block diagram

The table found here describes the external signals of ENET.
Table 23-1. ENET External Signals
Signal Description Mode Pad Alt Mode Direction
ENET_1588_EVENT0_I Capture/compare block input/output MII/RMII/ ENET_TXD1 ALT4 I
N event bus signal. When configured for RGMII
capture and a rising edge is detected,
the current timer value is latched and
transferred into the corresponding
ENET_TCCRn register for inspection
by software. When configured for
compare, the corresponding signal
1588_EVENT is asserted for one cycle
when the timer reaches the compare
value programmed in register
ENET_TCCRn. An interrupt or DMA
request can be triggered if the

External Signals
Table 23-1. ENET External Signals (continued)

corresponding bit in
ENET_TCSRn[TIE] or
ENET_TCSRn[TDRE] is set.
ENET_1588_EVENT0_O Capture/compare block input/output MII/RMII/ GPIO_19 ALT1 O
UT event bus signal. When configured for RGMII
ENET_TCSRn[TIE] or
ENET_1588_EVENT1_I Capture/compare block input/output MII/RMII/ ENET_MDC ALT4 I
ENET_TCSRn[TIE] or
ENET_1588_EVENT1_O Capture/compare block input/output MII/RMII/ ENET_MDIO ALT4 O
ENET_TCSRn[TIE] or
ENET_1588_EVENT2_I Capture/compare block input/output MII/RMII/ GPIO_16 ALT1 I


ENET_TCSRn[TIE] or
ENET_1588_EVENT2_O Capture/compare block input/output MII/RMII/ ENET_RX_ER ALT4 O
ENET_TCSRn[TIE] or
ENET_1588_EVENT3_I Capture/compare block input/output MII/RMII/ GPIO_17 ALT1 I
by software.
When configured for compare, the
corresponding signal 1588_EVENT is
asserted for one cycle when the timer
reaches the compare value
programmed in register
ENET_TCCRn.
An interrupt or DMA request can be
triggered if the corresponding bit in
ENET_TCSRn[TIE] or
ENET_1588_EVENT3_O Capture/compare block input/output MII/RMII/ ENET_RXD1 ALT4 O
by software.

External Signals

When configured for compare, the
corresponding signal 1588_EVENT is
asserted for one cycle when the timer
reaches the compare value
programmed in register
ENET_TCCRn.
An interrupt or DMA request can be
triggered if the corresponding bit in
ENET_TCSRn[TIE] or
ENET_COL Asserted upon detection of a collision MII KEY_ROW1 ALT1 I
and remains asserted while the
collision persists. This signal is not
defined for full duplex mode.
ENET_CRS Carrier sense. When asserted, MII KEY_COL3 ALT1 I
indicates transmit or receive medium
is not idle.
In RMII mode, this signal is present on
the RMII_CRS_DV pin.
ENET_MDC Output clock provides a timing MII/RMII/ ENET_MDC ALT1 O
reference to the PHY for data transfers RGMII KEY_COL2 ALT4
on the MDIO signal.
ENET_MDIO Transfers control information between MII/RMII/ ENET_MDIO ALT1 IO
the external PHY and the media- RGMII KEY_COL1 ALT1
access controller. Data is synchronous
to MDC. This signal is an input after
reset.
ENET_REF_CLK In RMII mode, this signal is the RMII GPIO_16 ALT2 I
reference clock for receive, transmit, RGMII_TX_CTL ALT7
and the control interface.
ENET_RX_CLK In MII mode, provides a timing MII GPIO_18 ALT1 I
reference for RX_EN, RX_DATA[3:0],
and RX_ER.
ENET_RX_DATA0 Contains the Ethernet input data MII/RMII ENET_RXD0 ALT1 I
transferred from the PHY to the
media-access controller when RX_EN
is asserted.
ENET_RX_DATA1 Contains the Ethernet input data MII/RMII ENET_RXD1 ALT1 I
is asserted.
ENET_RX_DATA2 Contains the Ethernet input data MII KEY_COL2 ALT1 I
is asserted.
ENET_RX_DATA3 Contains the Ethernet input data MII KEY_COL0 ALT1 I
is asserted.


ENET_RX_EN Asserting this input indicates the PHY MII/RMII ENET_CRS_DV ALT1 I
has valid nibbles present on the MII.
RX_EN must remain asserted from the
first recovered nibble of the frame
through to the last nibble. Asserting
RX_EN must start no later than the
SFD and exclude any EOF. In RMII
mode, this pin also generates the CRS
signal.
ENET_RX_ER When asserted with RXDV, indicates MII/RMII ENET_RX_ER ALT1 I
the PHY detects an error in the current
frame.
ENET_TX_CLK Input clock In MII mode, provides a MII/RGMII ENET_REF_CLK ALT1 I
timing reference for TX_EN,
TX_DATA[3:0], and TX_ER. IN RGMII
mode, provides the external 125 MHz
reference clock input.
ENET_TX_DATA0 Serial output Ethernet data. Only valid MII/RMII ENET_TXD0 ALT1 O
during TX_EN assertion.
ENET_TX_DATA1 Serial output Ethernet data. Only valid MII/RMII ENET_TXD1 ALT1 O
ENET_TX_DATA2 Serial output Ethernet data. Only valid MII KEY_ROW2 ALT1 O
ENET_TX_DATA3 Serial output Ethernet data. Only valid MII KEY_ROW0 ALT1 O
ENET_TX_EN Indicates when valid nibbles are MII/RMII ENET_TX_EN ALT1 O
present on the MII. This signal is
asserted with the first nibble of a
preamble and is deasserted before the
first TX_CLK following the final nibble
of the frame.
ENET_TX_ER When asserted for one or more clock MII/RMII GPIO_19 ALT6 O
cycles while TXEN is also asserted,
PHY sends one or more illegal
symbols.
RGMII_RD0 Contains the Ethernet input data RGMII RGMII_RD0 ALT1 I
is asserted.
is asserted.
is asserted.

Clocks

is asserted.
RGMII_RXC In RGMII mode, provides a timing RGMII RGMII_RXC ALT1 I
reference for RX_DATA[3:0] and
RX_CTL.
RGMII_RX_CTL In RGMII mode, contains RX_EN on RGMII RGMII_RX_CTL ALT1 I
the rising edge of RGMII_RXC, and a
logical derivative of RX_EN and
RX_ER (RX_EN XOR RX_ER) on the
falling edge of RGMII_RXC.
RGMII_TD0 Serial output Ethernet data. Only valid RGMII RGMII_TD0 ALT1 O
RGMII_TXC In RGMII mode, provides a timing RGMII RGMII_TXC ALT1 O
reference for TX_DATA[3:0] and
TX_CTL.
RGMII_TX_CTL In RGMII mode, contains TX_EN on RGMII RGMII_TX_CTL ALT1 O
the rising edge of RGMII_TXC, and a
logical derivative of TX_EN and
TX_ER (TX_EN XOR TX_ER) on the
falling edge of RGMII_TXC.
23.4 Clocks
The table found here describes the clock sources for ENET. Please see Clock Controller
Table 23-2. ENET Clocks
ipg_clk ahb_clk_root Module clock
ipg_clk_mac0 ahb_clk_root MAC peripheral clock
ipg_clk_mac0_s ipg_clk_root MAC peripheral access clock
ipg_clk_time ipg_clk_root Peripheral clock
mac0_rxmem_clk ahb_clk_root MAC receive memory clock
mac0_txmem_clk ahb_clk_root MAC transmit memory clock

NOTE
The ENET module requires ahb_clk_root to be 125 MHz or
greater.
23.5 Memory map/register definition

ENET registers must be read or written with 32-bit accesses. Non-32 bit accesses will
terminate with an error.
Reserved bits should be written with 0 and ignored on read. Unused registers read zero
and a write has no effect.
This table shows Ethernet registers organization.
Table 23-3. Register map summary
Offset Address Section Description
0x0000 – 0x01FF Configuration Core control and status registers
0x0200 – 0x03FF Statistics counters MIB and Remote Network Monitoring (RFC 2819) registers
0x0400 – 0x0430 1588 control 1588 adjustable timer (TSM) and 1588 frame control
0x0600 – 0x07FC Capture/Compare block Registers for the Capture/Compare block
ENET memory map

Absolute
Width Section/
(in bits) page
(hex)
218_8004 Interrupt Event Register (ENET_EIR) 32 w1c 0000_0000h 23.5.1/914
218_8008 Interrupt Mask Register (ENET_EIMR) 32 R/W 0000_0000h 23.5.2/917
218_8010 Receive Descriptor Active Register (ENET_RDAR) 32 R/W 0000_0000h 23.5.3/920
218_8014 Transmit Descriptor Active Register (ENET_TDAR) 32 R/W 0000_0000h 23.5.4/920
218_8024 Ethernet Control Register (ENET_ECR) 32 R/W F000_0000h 23.5.5/922
218_8040 MII Management Frame Register (ENET_MMFR) 32 R/W 0000_0000h 23.5.6/924
218_8044 MII Speed Control Register (ENET_MSCR) 32 R/W 0000_0000h 23.5.7/925
218_8064 MIB Control Register (ENET_MIBC) 32 R/W C000_0000h 23.5.8/927
218_8084 Receive Control Register (ENET_RCR) 32 R/W 05EE_0001h 23.5.9/929
23.5.10/
218_80C4 Transmit Control Register (ENET_TCR) 32 R/W 0000_0000h
932
23.5.11/
218_80E4 Physical Address Lower Register (ENET_PALR) 32 R/W 0000_0000h
934
23.5.12/
218_80E8 Physical Address Upper Register (ENET_PAUR) 32 R/W 0000_8808h
934

Memory map/register definition
ENET memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
23.5.13/
218_80EC Opcode/Pause Duration Register (ENET_OPD) 32 R/W 0001_0000h
935
23.5.14/
218_8118 Descriptor Individual Upper Address Register (ENET_IAUR) 32 R/W 0000_0000h
935
23.5.15/
218_811C Descriptor Individual Lower Address Register (ENET_IALR) 32 R/W 0000_0000h
936
23.5.16/
218_8120 Descriptor Group Upper Address Register (ENET_GAUR) 32 R/W 0000_0000h
936
23.5.17/
218_8124 Descriptor Group Lower Address Register (ENET_GALR) 32 R/W 0000_0000h
937
23.5.18/
218_8144 Transmit FIFO Watermark Register (ENET_TFWR) 32 R/W 0000_0000h
937
23.5.19/
218_8180 Receive Descriptor Ring Start Register (ENET_RDSR) 32 R/W 0000_0000h
938
Transmit Buffer Descriptor Ring Start Register 23.5.20/
218_8184 32 R/W 0000_0000h
(ENET_TDSR) 939
23.5.21/
218_8188 Maximum Receive Buffer Size Register (ENET_MRBR) 32 R/W 0000_0000h
940
23.5.22/
218_8190 Receive FIFO Section Full Threshold (ENET_RSFL) 32 R/W 0000_0000h
941
23.5.23/
218_8194 Receive FIFO Section Empty Threshold (ENET_RSEM) 32 R/W 0000_0000h
941
23.5.24/
218_8198 Receive FIFO Almost Empty Threshold (ENET_RAEM) 32 R/W 0000_0004h
942
23.5.25/
218_819C Receive FIFO Almost Full Threshold (ENET_RAFL) 32 R/W 0000_0004h
942
23.5.26/
218_81A0 Transmit FIFO Section Empty Threshold (ENET_TSEM) 32 R/W 0000_0000h
943
23.5.27/
218_81A4 Transmit FIFO Almost Empty Threshold (ENET_TAEM) 32 R/W 0000_0004h
943
23.5.28/
218_81A8 Transmit FIFO Almost Full Threshold (ENET_TAFL) 32 R/W 0000_0008h
944
23.5.29/
218_81AC Transmit Inter-Packet Gap (ENET_TIPG) 32 R/W 0000_000Ch
944
23.5.30/
218_81B0 Frame Truncation Length (ENET_FTRL) 32 R/W 0000_07FFh
945
23.5.31/
218_81C0 Transmit Accelerator Function Configuration (ENET_TACC) 32 R/W 0000_0000h
945
23.5.32/
218_81C4 Receive Accelerator Function Configuration (ENET_RACC) 32 R/W 0000_0000h
946
23.5.33/
218_8200 Reserved Statistic Register (ENET_RMON_T_DROP) 32 R 0000_0000h
947
Tx Packet Count Statistic Register 23.5.34/
218_8204 32 R 0000_0000h
(ENET_RMON_T_PACKETS) 948


Absolute
Width Section/
(in bits) page
(hex)
Tx Broadcast Packets Statistic Register 23.5.35/
218_8208 32 R 0000_0000h
(ENET_RMON_T_BC_PKT) 948
Tx Multicast Packets Statistic Register 23.5.36/
218_820C 32 R 0000_0000h
(ENET_RMON_T_MC_PKT) 949
Tx Packets with CRC/Align Error Statistic Register 23.5.37/
218_8210 32 R 0000_0000h
(ENET_RMON_T_CRC_ALIGN) 949
Tx Packets Less Than Bytes and Good CRC Statistic 23.5.38/
218_8214 32 R 0000_0000h
Register (ENET_RMON_T_UNDERSIZE) 950
Tx Packets GT MAX_FL bytes and Good CRC Statistic 23.5.39/
218_8218 32 R 0000_0000h
Register (ENET_RMON_T_OVERSIZE) 950
Tx Packets Less Than 64 Bytes and Bad CRC Statistic 23.5.40/
218_821C 32 R 0000_0000h
Register (ENET_RMON_T_FRAG) 951
Tx Packets Greater Than MAX_FL bytes and Bad CRC 23.5.41/
218_8220 32 R 0000_0000h
Statistic Register (ENET_RMON_T_JAB) 951
23.5.42/
218_8224 Tx Collision Count Statistic Register (ENET_RMON_T_COL) 32 R 0000_0000h
952
Tx 64-Byte Packets Statistic Register 23.5.43/
218_8228 32 R 0000_0000h
(ENET_RMON_T_P64) 952
Tx 65- to 127-byte Packets Statistic Register 23.5.44/
218_822C 32 R 0000_0000h
(ENET_RMON_T_P65TO127) 953
218_8230 32 R 0000_0000h
218_8234 32 R 0000_0000h
218_8238 32 R 0000_0000h
218_823C 32 R 0000_0000h
Tx Packets Greater Than 2048 Bytes Statistic Register 23.5.49/
218_8240 32 R 0000_0000h
(ENET_RMON_T_P_GTE2048) 955
23.5.50/
218_8244 Tx Octets Statistic Register (ENET_RMON_T_OCTETS) 32 R 0000_0000h
955
23.5.51/
218_8248 Reserved Statistic Register (ENET_IEEE_T_DROP) 32 R 0000_0000h
956
Frames Transmitted OK Statistic Register 23.5.52/
218_824C 32 R 0000_0000h
(ENET_IEEE_T_FRAME_OK) 956
Frames Transmitted with Single Collision Statistic Register 23.5.53/
218_8250 32 R 0000_0000h
(ENET_IEEE_T_1COL) 957
Frames Transmitted with Multiple Collisions Statistic 23.5.54/
218_8254 32 R 0000_0000h
Register (ENET_IEEE_T_MCOL) 957
Frames Transmitted after Deferral Delay Statistic Register 23.5.55/
218_8258 32 R 0000_0000h
(ENET_IEEE_T_DEF) 958
Frames Transmitted with Late Collision Statistic Register 23.5.56/
218_825C 32 R 0000_0000h
(ENET_IEEE_T_LCOL) 958


Absolute
Width Section/
(in bits) page
(hex)
Frames Transmitted with Excessive Collisions Statistic 23.5.57/
218_8260 32 R 0000_0000h
Register (ENET_IEEE_T_EXCOL) 959
Frames Transmitted with Tx FIFO Underrun Statistic 23.5.58/
218_8264 32 R 0000_0000h
Register (ENET_IEEE_T_MACERR) 959
Frames Transmitted with Carrier Sense Error Statistic 23.5.59/
218_8268 32 R 0000_0000h
Register (ENET_IEEE_T_CSERR) 960
R (reads 23.5.60/
218_826C Reserved Statistic Register (ENET_IEEE_T_SQE) 32 0000_0000h
0) 960
Flow Control Pause Frames Transmitted Statistic Register 23.5.61/
218_8270 32 R 0000_0000h
(ENET_IEEE_T_FDXFC) 961
Octet Count for Frames Transmitted w/o Error Statistic 23.5.62/
218_8274 32 R 0000_0000h
Register (ENET_IEEE_T_OCTETS_OK) 961
Rx Packet Count Statistic Register 23.5.63/
218_8284 32 R 0000_0000h
(ENET_RMON_R_PACKETS) 962
Rx Broadcast Packets Statistic Register 23.5.64/
218_8288 32 R 0000_0000h
(ENET_RMON_R_BC_PKT) 962
Rx Multicast Packets Statistic Register 23.5.65/
218_828C 32 R 0000_0000h
(ENET_RMON_R_MC_PKT) 963
Rx Packets with CRC/Align Error Statistic Register 23.5.66/
218_8290 32 R 0000_0000h
(ENET_RMON_R_CRC_ALIGN) 963
Rx Packets with Less Than 64 Bytes and Good CRC 23.5.67/
218_8294 32 R 0000_0000h
Statistic Register (ENET_RMON_R_UNDERSIZE) 964
Rx Packets Greater Than MAX_FL and Good CRC Statistic 23.5.68/
218_8298 32 R 0000_0000h
Register (ENET_RMON_R_OVERSIZE) 964
Rx Packets Less Than 64 Bytes and Bad CRC Statistic 23.5.69/
218_829C 32 R 0000_0000h
Register (ENET_RMON_R_FRAG) 965
Rx Packets Greater Than MAX_FL Bytes and Bad CRC 23.5.70/
218_82A0 32 R 0000_0000h
Statistic Register (ENET_RMON_R_JAB) 965
R (reads 23.5.71/
218_82A4 Reserved Statistic Register (ENET_RMON_R_RESVD_0) 32 0000_0000h
0) 965
Rx 64-Byte Packets Statistic Register 23.5.72/
218_82A8 32 R 0000_0000h
(ENET_RMON_R_P64) 966
Rx 65- to 127-Byte Packets Statistic Register 23.5.73/
218_82AC 32 R 0000_0000h
(ENET_RMON_R_P65TO127) 966
218_82B0 32 R 0000_0000h
218_82B4 32 R 0000_0000h
218_82B8 32 R 0000_0000h
218_82BC 32 R 0000_0000h
Rx Packets Greater than 2048 Bytes Statistic Register 23.5.78/
218_82C0 32 R 0000_0000h
(ENET_RMON_R_P_GTE2048) 969


Absolute
Width Section/
(in bits) page
(hex)
23.5.79/
218_82C4 Rx Octets Statistic Register (ENET_RMON_R_OCTETS) 32 R 0000_0000h
969
Frames not Counted Correctly Statistic Register 23.5.80/
218_82C8 32 R 0000_0000h
(ENET_IEEE_R_DROP) 970
Frames Received OK Statistic Register 23.5.81/
218_82CC 32 R 0000_0000h
(ENET_IEEE_R_FRAME_OK) 970
Frames Received with CRC Error Statistic Register 23.5.82/
218_82D0 32 R 0000_0000h
(ENET_IEEE_R_CRC) 971
Frames Received with Alignment Error Statistic Register 23.5.83/
218_82D4 32 R 0000_0000h
(ENET_IEEE_R_ALIGN) 971
Receive FIFO Overflow Count Statistic Register 23.5.84/
218_82D8 32 R 0000_0000h
(ENET_IEEE_R_MACERR) 972
Flow Control Pause Frames Received Statistic Register 23.5.85/
218_82DC 32 R 0000_0000h
(ENET_IEEE_R_FDXFC) 972
Octet Count for Frames Received without Error Statistic 23.5.86/
218_82E0 32 R 0000_0000h
Register (ENET_IEEE_R_OCTETS_OK) 973
23.5.87/
218_8400 Adjustable Timer Control Register (ENET_ATCR) 32 R/W 0000_0000h
973
23.5.88/
218_8404 Timer Value Register (ENET_ATVR) 32 R/W 0000_0000h
975
23.5.89/
218_8408 Timer Offset Register (ENET_ATOFF) 32 R/W 0000_0000h
975
23.5.90/
218_840C Timer Period Register (ENET_ATPER) 32 R/W 3B9A_CA00h
976
23.5.91/
218_8410 Timer Correction Register (ENET_ATCOR) 32 R/W 0000_0000h
976
23.5.92/
218_8414 Time-Stamping Clock Period Register (ENET_ATINC) 32 R/W 0000_0000h
977
23.5.93/
218_8418 Timestamp of Last Transmitted Frame (ENET_ATSTMP) 32 R 0000_0000h
977
23.5.94/
218_8604 Timer Global Status Register (ENET_TGSR) 32 R/W 0000_0000h
978
23.5.95/
218_8608 Timer Control Status Register (ENET_TCSR0) 32 R/W 0000_0000h
979
23.5.96/
218_860C Timer Compare Capture Register (ENET_TCCR0) 32 R/W 0000_0000h
980
23.5.95/
979
23.5.96/
218_8614 Timer Compare Capture Register (ENET_TCCR1) 32 R/W 0000_0000h
980
23.5.95/
979
23.5.96/
218_861C Timer Compare Capture Register (ENET_TCCR2) 32 R/W 0000_0000h
980


Absolute
Width Section/
(in bits) page
(hex)
23.5.95/
979
23.5.96/
218_8624 Timer Compare Capture Register (ENET_TCCR3) 32 R/W 0000_0000h
980
23.5.1 Interrupt Event Register (ENET_EIR)

When an event occurs that sets a bit in EIR, an interrupt occurs if the corresponding bit in
the interrupt mask register (EIMR) is also set. Writing a 1 to an EIR bit clears it; writing
0 has no effect. This register is cleared upon hardware reset.
NOTE
TxBD[INT] and RxBD[INT] must be set to 1 to allow setting
the corresponding EIR register flags in enhanced mode,
ENET_ECR[EN1588] = 1. Legacy mode does not require these
flags to be enabled.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_AVAIL
WAKEUP
EBERR
BABR
BABT
GRA
UN
0 TXF TXB RXF RXB MII PLR
LC
RL
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_TIMER
W w1c 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENET_EIR field descriptions

Field Description
30 Babbling Receive Error
BABR
Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
29 Babbling Transmit Error
BABT
Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually this condition is caused
when a frame that is too long is placed into the transmit data buffer(s). Truncation does not occur.
28 Graceful Stop Complete
GRA
This interrupt is asserted after the transmitter is put into a pause state after completion of the frame
currently being transmitted. See Graceful Transmit Stop (GTS) for conditions that lead to graceful stop.
NOTE: The GRA interrupt is asserted only when the TX transitions into the stopped state. If this bit is
cleared by writing 1 and the TX is still stopped, the bit is not set again.
27 Transmit Frame Interrupt
TXF
Indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated.
26 Transmit Buffer Interrupt
TXB
Indicates a transmit buffer descriptor has been updated.
25 Receive Frame Interrupt
RXF
Indicates a frame has been received and the last corresponding buffer descriptor has been updated.
24 Receive Buffer Interrupt
RXB
Indicates a receive buffer descriptor is not the last in the frame has been updated.
23 MII Interrupt.
MII
Indicates that the MII has completed the data transfer requested.
22 Ethernet Bus Error
EBERR
Indicates a system bus error occurred when a uDMA transaction is underway. When this bit is set,
ECR[ETHEREN] is cleared, halting frame processing by the MAC. When this occurs, software must
ensure proper actions, possibly resetting the system, to resume normal operation.
21 Late Collision
LC
Indicates a collision occurred beyond the collision window (slot time) in half-duplex mode. The frame
truncates with a bad CRC and the remainder of the frame is discarded.
20 Collision Retry Limit
RL
Indicates a collision occurred on each of 16 successive attempts to transmit the frame. The frame is
discarded without being transmitted and transmission of the next frame commences. This error can only
occur in half-duplex mode.
19 Transmit FIFO Underrun
UN
Indicates the transmit FIFO became empty before the complete frame was transmitted.
NOTE: In situations where the device has various masters generating high traffic, a FIFO underrun can
occur on the transmit FIFO. To avoid transmit FIFO underrun, store and forward can be enabled

ENET_EIR field descriptions (continued)

Field Description
in ENET_TFWR[STRFWD]. See STRFWD. Also, a higher priority can be set for ENET traffic
using available means on the central bus fabric connecting the ENET module.
18 Payload Receive Error
PLR
Indicates a frame was received with a payload length error. See Frame Length/Type Verification: Payload
Length Check for more information.
17 Node Wakeup Request Indication
WAKEUP
Read-only status bit to indicate that a magic packet has been detected. Will act only if ECR[MAGICEN] is
set.
16 Transmit Timestamp Available
TS_AVAIL
Indicates that the timestamp of the last transmitted timing frame is available in the ATSTMP register.
15 Timestamp Timer
TS_TIMER
The adjustable timer reached the period event. A period event interrupt can be generated if
ATCR[PEREN] is set and the timer wraps according to the periodic setting in the ATPER register. Set the
timer period value before setting ATCR[PEREN].
Reserved This write-only field is reserved. It must always be written with the value 0.
Reserved This field is reserved.
This write-only field is reserved. It must always be written with the value 0.

23.5.2 Interrupt Mask Register (ENET_EIMR)

EIMR controls which interrupt events are allowed to generate actual interrupts. A
hardware reset clears this register. If the corresponding bits in the EIR and EIMR
registers are set, an interrupt is generated. The interrupt signal remains asserted until a 1
is written to the EIR field (write 1 to clear) or a 0 is written to the EIMR field.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_AVAIL
R
WAKEUP
EBERR
BABR BABT GRA TXF TXB RXF RXB MII LC RL UN PLR
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_TIMER
W 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_EIMR field descriptions

Field Description
30 BABR Interrupt Mask
BABR
Corresponds to interrupt source EIR[BABR] and determines whether an interrupt condition can generate
an interrupt. At every module clock, the EIR samples the signal generated by the interrupting source. The
corresponding EIR BABR field reflects the state of the interrupt signal even if the corresponding EIMR field
is cleared.
0 The corresponding interrupt source is masked.

1 The corresponding interrupt source is not masked.
29 BABT Interrupt Mask
BABT
Corresponds to interrupt source EIR[BABT] and determines whether an interrupt condition can generate
corresponding EIR BABT field reflects the state of the interrupt signal even if the corresponding EIMR field
is cleared.

28 GRA Interrupt Mask
GRA
Corresponds to interrupt source EIR[GRA] and determines whether an interrupt condition can generate an
interrupt. At every module clock, the EIR samples the signal generated by the interrupting source. The

ENET_EIMR field descriptions (continued)

Field Description
corresponding EIR GRA field reflects the state of the interrupt signal even if the corresponding EIMR field
is cleared.

27 TXF Interrupt Mask
TXF
Corresponds to interrupt source EIR[TXF] and determines whether an interrupt condition can generate an
corresponding EIR TXF field reflects the state of the interrupt signal even if the corresponding EIMR field
is cleared.

26 TXB Interrupt Mask
TXB
Corresponds to interrupt source EIR[TXB] and determines whether an interrupt condition can generate an
corresponding EIR TXF field reflects the state of the interrupt signal even if the corresponding EIMR field
is cleared.

25 RXF Interrupt Mask
RXF
Corresponds to interrupt source EIR[RXF] and determines whether an interrupt condition can generate an
corresponding EIR RXF field reflects the state of the interrupt signal even if the corresponding EIMR field
is cleared.
24 RXB Interrupt Mask
RXB
Corresponds to interrupt source EIR[RXB] and determines whether an interrupt condition can generate an
corresponding EIR RXB field reflects the state of the interrupt signal even if the corresponding EIMR field
is cleared.
23 MII Interrupt Mask
MII
Corresponds to interrupt source EIR[MII] and determines whether an interrupt condition can generate an
corresponding EIR MII field reflects the state of the interrupt signal even if the corresponding EIMR field is
cleared.
22 EBERR Interrupt Mask
EBERR
Corresponds to interrupt source EIR[EBERR] and determines whether an interrupt condition can generate
corresponding EIR EBERR field reflects the state of the interrupt signal even if the corresponding EIMR
field is cleared.
21 LC Interrupt Mask
LC
Corresponds to interrupt source EIR[LC] and determines whether an interrupt condition can generate an
corresponding EIR LC field reflects the state of the interrupt signal even if the corresponding EIMR field is
cleared.

ENET_EIMR field descriptions (continued)

Field Description
20 RL Interrupt Mask
RL
Corresponds to interrupt source EIR[RL] and determines whether an interrupt condition can generate an
corresponding EIR RL field reflects the state of the interrupt signal even if the corresponding EIMR field is
cleared.
19 UN Interrupt Mask
UN
Corresponds to interrupt source EIR[UN] and determines whether an interrupt condition can generate an
corresponding EIR UN field reflects the state of the interrupt signal even if the corresponding EIMR field is
cleared.
18 PLR Interrupt Mask
PLR
Corresponds to interrupt source EIR[PLR] and determines whether an interrupt condition can generate an
corresponding EIR PLR field reflects the state of the interrupt signal even if the corresponding EIMR field
is cleared.
17 WAKEUP Interrupt Mask
WAKEUP
Corresponds to interrupt source EIR[WAKEUP] register and determines whether an interrupt condition can
generate an interrupt. At every module clock, the EIR samples the signal generated by the interrupting
source. The corresponding EIR WAKEUP field reflects the state of the interrupt signal even if the
corresponding EIMR field is cleared.
16 TS_AVAIL Interrupt Mask
TS_AVAIL
Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether an interrupt condition
can generate an interrupt. At every module clock, the EIR samples the signal generated by the interrupting
source. The corresponding EIR TS_AVAIL field reflects the state of the interrupt signal even if the
15 TS_TIMER Interrupt Mask
TS_TIMER
Corresponds to interrupt source EIR[TS_TIMER] register and determines whether an interrupt condition
can generate an interrupt. At every module clock, the EIR samples the signal generated by the interrupting
source. The corresponding EIR TS_TIMER field reflects the state of the interrupt signal even if the
This write-only field is reserved. It must always be written with the value 0.

23.5.3 Receive Descriptor Active Register (ENET_RDAR)
RDAR is a command register, written by the user, to indicate that the receive descriptor
ring has been updated, that is, that the driver produced empty receive buffers with the
empty bit set.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
RDAR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RDAR field descriptions

Field Description
24 Receive Descriptor Active
RDAR
Always set to 1 when this register is written, regardless of the value written. This field is cleared by the
MAC device when no additional empty descriptors remain in the receive ring. It is also cleared when
ECR[ETHEREN] transitions from set to cleared or when ECR[RESET] is set.
23.5.4 Transmit Descriptor Active Register (ENET_TDAR)

The TDAR is a command register that the user writes to indicate that the transmit
descriptor ring has been updated, that is, that transmit buffers have been produced by the
driver with the ready bit set in the buffer descriptor.
The TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
cleared, or when ECR[RESET] is set.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
TDAR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_TDAR field descriptions

Field Description
24 Transmit Descriptor Active
TDAR
Always set to 1 when this register is written, regardless of the value written. This bit is cleared by the MAC
device when no additional ready descriptors remain in the transmit ring. Also cleared when
ECR[ETHEREN] transitions from set to cleared or when ECR[RESET] is set.

23.5.5 Ethernet Control Register (ENET_ECR)

ECR is a read/write user register, though hardware may also alter fields in this register. It
controls many of the high level features of the Ethernet MAC, including legacy FEC
support through the EN1588 field.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RXC_ TXC_
Reserved
DLY DLY
W
Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETHEREN
MAGICEN
R
Reserved
Reserved
Reserved
STOPEN
DBSWP
EN1588
DBGEN
SPEED
RESET
SLEEP
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_ECR field descriptions

Field Description
Reserved Always write 11110000000000b to this field.
17 Receive clock delay
RXC_DLY
This field allows you to select a delayed version of the RGMII_RXC clock.
0 Use non-delayed version of RGMII_RXC.

1 Use delayed version of RGMII_RXC.
16 Transmit clock delay
TXC_DLY
This field allows you to generate a delayed version of the RGMII_TXC clock.
0 RGMII_TXC is not delayed.

1 Generate delayed version of RGMII_TXC.
Reserved Always write 0 to this field.
8 Descriptor Byte Swapping Enable
DBSWP

ENET_ECR field descriptions (continued)

Field Description
Swaps the byte locations of the buffer descriptors.
NOTE: This field must be written to 1 after reset.
0 The buffer descriptor bytes are not swapped to support big-endian devices.
1 The buffer descriptor bytes are swapped to support little-endian devices.
7 STOPEN Signal Control
STOPEN
Controls device behavior in doze mode.
In doze mode, if this field is set then all the clocks of the ENET assembly are disabled, except the
RMII /MII clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly depending
on ECR[STOPEN].
NOTE: If module clocks are gated in this mode, the module can still wake the system after receiving a
magic packet in stop mode. MAGICEN must be set prior to entering sleep/stop mode.
6 Debug Enable
DBGEN
Enables the MAC to enter hardware freeze mode when the device enters debug mode.
0 MAC continues operation in debug mode.

1 MAC enters hardware freeze mode when the processor is in debug mode.
5 Selects between 10/100-Mbit/s and 1000-Mbit/s modes of operation.
SPEED
0 10/100-Mbit/s mode
1 1000-Mbit/s mode
4 EN1588 Enable
EN1588
Enables enhanced functionality of the MAC.
0 Legacy FEC buffer descriptors and functions enabled.

1 Enhanced frame time-stamping functions enabled.
3 Sleep Mode Enable
SLEEP
0 Normal operating mode.
1 Sleep mode.
2 Magic Packet Detection Enable
MAGICEN
Enables/disables magic packet detection.
NOTE: MAGICEN is relevant only if the SLEEP field is set. If MAGICEN is set, changing the SLEEP field
enables/disables sleep mode and magic packet detection.
NOTE: EIMR[WAKEUP] must be written to one if Magic packet wakeup is programed to wake up the chip
from low power mode.
0 Magic detection logic disabled.

1 The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
1 Ethernet Enable
ETHEREN
Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer descriptors for an aborted
transmit frame are not updated. The uDMA, buffer descriptor, and FIFO control logic are reset, including
the buffer descriptor and FIFO pointers.
Hardware clears this field under the following conditions:

ENET_ECR field descriptions (continued)

Field Description
• RESET is set by software
• An error condition causes the EBERR field to set.
NOTE: • ETHEREN must be set at the very last step during ENET configuration/setup/initialization,
only after all other ENET-related registers have been configured.
• If ETHEREN is cleared to 0 by software then next time ETHEREN is set, the EIR interrupts
must cleared to 0 due to previous pending interrupts.
0 Reception immediately stops and transmission stops after a bad CRC is appended to any currently
transmitted frame.
1 MAC is enabled, and reception and transmission are possible.
0 Ethernet MAC Reset
RESET
When this field is set, it clears the ETHEREN field.
23.5.6 MII Management Frame Register (ENET_MMFR)

Writing to MMFR triggers a management frame transaction to the PHY device unless
MSCR is programmed to zero.
If MSCR is changed from zero to non-zero during a write to MMFR, an MII frame is
generated with the data previously written to the MMFR. This allows MMFR and MSCR
to be programmed in either order if MSCR is currently zero.
If the MMFR register is written while frame generation is in progress, the frame contents
are altered. Software must use the EIR[MII] interrupt indication to avoid writing to the
MMFR register while frame generation is in progress.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ST OP PA RA TA DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_MMFR field descriptions

Field Description
31–30 Start Of Frame Delimiter
ST
See Table 23-41 (Clause 22) or Table 23-43 (Clause 45) for correct value.
29–28 Operation Code
OP
27–23 PHY Address
PA

ENET_MMFR field descriptions (continued)

Field Description
22–18 Register Address
RA
17–16 Turn Around
TA
This field must be programmed to 10 to generate a valid MII management frame.
DATA Management Frame Data
This is the field for data to be written to or read from the PHY register.
23.5.7 MII Speed Control Register (ENET_MSCR)

MSCR provides control of the MII clock (MDC pin) frequency and allows a preamble
drop on the MII management frame.
The MII_SPEED field must be programmed with a value to provide an MDC frequency
of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification.
The MII_SPEED must be set to a non-zero value to source a read or write management
frame. After the management frame is complete, the MSCR register may optionally be
cleared to turn off MDC. The MDC signal generated has a 50% duty cycle except when
MII_SPEED changes during operation. This change takes effect following a rising or
falling edge of MDC.
For example, if the internal module clock (that is, peripheral bus clock) is 25 MHz,
programming MII_SPEED to 0x4 results in an MDC as given in the following equation:
MII clock frequency = 25 MHz / ((4 + 1) x 2) = 2.5 MHz
The following table shows the optimum values for MII_SPEED as a function of IPS bus
clock frequency.
Table 23-4. Programming Examples for MSCR
Internal module clock frequency MSCR [MII_SPEED] MDC frequency
25 MHz 0x4 2.50 MHz
33 MHz 0x6 2.36 MHz
40 MHz 0x7 2.50 MHz
50 MHz 0x9 2.50 MHz
66 MHz 0xD 2.36 MHz

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 DIS_ 0
HOLDTIME MII_SPEED
W PRE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_MSCR field descriptions

Field Description
10–8 Hold time On MDIO Output
HOLDTIME
IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO output. Depending on the
host bus frequency, the setting may need to be increased.
000 1 internal module clock cycle

001 2 internal module clock cycles
7 Disable Preamble
DIS_PRE
Enables/disables prepending a preamble to the MII management frame. The MII standard allows the
preamble to be dropped if the attached PHY devices do not require it.
0 Preamble enabled.
1 Preamble (32 ones) is not prepended to the MII management frame.
6–1 MII Speed
MII_SPEED
Controls the frequency of the MII management interface clock (MDC) relative to the internal module clock.
A value of 0 in this field turns off MDC and leaves it in low voltage state. Any non-zero value results in the
MDC frequency of:
1/((MII_SPEED + 1) x 2) of the internal module clock frequency

23.5.8 MIB Control Register (ENET_MIBC)

MIBC is a read/write register controlling and observing the state of the MIB block.
Access this register to disable the MIB block operation or clear the MIB counters. The
MIB_DIS field resets to 1.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIB_IDLE
R 0
MIB_CLEAR
MIB_DIS
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_MIBC field descriptions

Field Description
31 Disable MIB Logic
MIB_DIS
If this control field is set,
0 MIB logic is enabled.

1 MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

ENET_MIBC field descriptions (continued)

Field Description
30 MIB Idle
MIB_IDLE
0 The MIB block is updating MIB counters.
1 The MIB block is not currently updating any MIB counters.
29 MIB Clear
MIB_CLEAR
NOTE: This field is not self-clearing. To clear the MIB counters set and then clear this field.
0 See note above.

1 All statistics counters are reset to 0.

23.5.9 Receive Control Register (ENET_RCR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GRS
NLC MAX_FL
Reset 0 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RMII_MODE
MII_MODE
RGMII_EN
CRCFWD
RMII_10T
PAUFWD
PADEN
PROM
LOOP
CFEN
BC_
FCE DRT
REJ
W 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ENET_RCR field descriptions

Field Description
31 Graceful Receive Stopped
GRS
Read-only status indicating that the MAC receive datapath is stopped.
30 Payload Length Check Disable
NLC
Enables/disables a payload length check.
0 The payload length check is disabled.

1 The core checks the frame's payload length with the frame length/type field. Errors are indicated in the
EIR[PLR] field.
29–16 Maximum Frame Length
MAX_FL

ENET_RCR field descriptions (continued)

Field Description
Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame.
Transmit frames longer than MAX_FL cause the BABT interrupt to occur. Receive frames longer than
MAX_FL cause the BABR interrupt to occur and set the LG field in the end of frame receive buffer
descriptor. The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
supported.
15 MAC Control Frame Enable
CFEN
Enables/disables the MAC control frame.
0 MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to
the client interface.
1 MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
14 Terminate/Forward Received CRC
CRCFWD
Specifies whether the CRC field of received frames is transmitted or stripped.
NOTE: If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC field is checked
and always terminated and removed.
0 The CRC field of received frames is transmitted to the user application.

1 The CRC field is stripped from the frame.
13 Terminate/Forward Pause Frames
PAUFWD
Specifies whether pause frames are terminated or forwarded.
0 Pause frames are terminated and discarded in the MAC.

1 Pause frames are forwarded to the user application.
12 Enable Frame Padding Remove On Receive
PADEN
Specifies whether the MAC removes padding from received frames.
0 No padding is removed on receive by the MAC.

1 Padding is removed from received frames.
9 Enables 10-Mbit/s mode of the RMII or RGMII .
RMII_10T
0 100-Mbit/s operation.
1 10-Mbit/s operation.
8 RMII Mode Enable
RMII_MODE
Specifies whether the MAC is configured for MII mode or RMII operation , when ECR[SPEED] is cleared .
NOTE: Do not set both RCR[RGMII_EN] and RCR[RMII_MODE].
0 MAC configured for MII mode.

1 MAC configured for RMII operation.
6 RGMII Mode Enable
RGMII_EN
NOTE: Do not set both RCR[RGMII_EN] and RCR[RMII_MODE].


ENET_RCR field descriptions (continued)

Field Description
0 MAC configured for non-RGMII operation
1 MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode.
If ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
5 Flow Control Enable
FCE
If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the transmitter stops
transmitting data frames for a given duration.
4 Broadcast Frame Reject
BC_REJ
If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are rejected unless the PROM
field is set. If BC_REJ and PROM are set, frames with broadcast DA are accepted and the MISS (M) is set
in the receive buffer descriptor.
3 Promiscuous Mode
PROM
All frames are accepted regardless of address matching.
0 Disabled.
1 Enabled.
2 Media Independent Interface Mode
MII_MODE
This field must always be set.
0 Reserved.
1 MII or RMII mode, as indicated by the RMII_MODE field.
1 Disable Receive On Transmit
DRT
0 Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor
transmit activity in half-duplex mode.
1 Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
0 Internal Loopback
LOOP
This is an MII internal loopback, therefore MII_MODE must be written to 1 and RMII_MODE must be
written to 0.
0 Loopback disabled.
1 Transmitted frames are looped back internal to the device and transmit MII output signals are not
asserted. DRT must be cleared.

23.5.10 Transmit Control Register (ENET_TCR)

TCR is read/write and configures the transmit block. This register is cleared at system
reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFC_PAUSE
R 0
TFC_PAUSE
CRCFWD
Reserved
ADDINS
FDEN
ADDSEL GTS
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_TCR field descriptions

Field Description
Reserved This field is read/write and must be set to 0.
9 Forward Frame From Application With CRC
CRCFWD

ENET_TCR field descriptions (continued)

Field Description
0 TxBD[TC] controls whether the frame has a CRC from the application.
1 The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC
from the application.
8 Set MAC Address On Transmit
ADDINS
0 The source MAC address is not modified by the MAC.
1 The MAC overwrites the source MAC address with the programmed MAC address according to
ADDSEL.
7–5 Source MAC Address Select On Transmit
ADDSEL
If ADDINS is set, indicates the MAC address that overwrites the source MAC address.
000 Node MAC address programmed on PADDR1/2 registers.

100 Reserved.
101 Reserved.
110 Reserved.
4 Receive Frame Control Pause
RFC_PAUSE
This status field is set when a full-duplex flow control pause frame is received and the transmitter pauses
for the duration defined in this pause frame. This field automatically clears when the pause duration is
complete.
3 Transmit Frame Control Pause
TFC_PAUSE
Pauses frame transmission. When this field is set, EIR[GRA] is set. With transmission of data frames
stopped, the MAC transmits a MAC control PAUSE frame. Next, the MAC clears TFC_PAUSE and
resumes transmitting data frames. If the transmitter pauses due to user assertion of GTS or reception of a
PAUSE frame, the MAC may continue transmitting a MAC control PAUSE frame.
0 No PAUSE frame transmitted.

1 The MAC stops transmission of data frames after the current transmission is complete.
2 Full-Duplex Enable
FDEN
If this field is set, frames transmit independent of carrier sense and collision inputs. Only modify this bit
when ECR[ETHEREN] is cleared.
0 Graceful Transmit Stop
GTS
When this field is set, MAC stops transmission after any frame currently transmitted is complete and
EIR[GRA] is set. If frame transmission is not currently underway, the GRA interrupt is asserted
immediately. After transmission finishes, clear GTS to restart. The next frame in the transmit FIFO is then
transmitted. If an early collision occurs during transmission when GTS is set, transmission stops after the
collision. The frame is transmitted again after GTS is cleared. There may be old frames in the transmit
FIFO that transmit when GTS is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA
interrupt.

23.5.11 Physical Address Lower Register (ENET_PALR)

PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used in the
address recognition process to compare with the destination address (DA) field of receive
frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the
six-byte source address field when transmitting PAUSE frames.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
PADDR1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_PALR field descriptions

Field Description
PADDR1 Pause Address
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used
for exact match and the source address field in PAUSE frames.
23.5.12 Physical Address Upper Register (ENET_PAUR)

PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address
recognition process to compare with the destination address (DA) field of receive frames
with an individual DA. In addition, this register is used in bytes 4 and 5 of the six-byte
source address field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a
constant type field (0x8808) for transmission of PAUSE frames.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TYPE
PADDR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
ENET_PAUR field descriptions

Field Description
31–16 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the
PADDR2 source address field in PAUSE frames.
TYPE Type Field In PAUSE Frames
These fields have a constant value of 0x8808.

23.5.13 Opcode/Pause Duration Register (ENET_OPD)

OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause
duration fields used in transmission of a PAUSE frame. The opcode field is a constant
value, 0x0001. When another node detects a PAUSE frame, that node pauses
transmission for the duration specified in the pause duration field. The lower 16 bits of
this register are not reset and you must initialize it.
Address: 218_8000h base + ECh offset = 218_80ECh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OPCODE
PAUSE_DUR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_OPD field descriptions

Field Description
31–16 Opcode Field In PAUSE Frames
OPCODE
These fields have a constant value of 0x0001.
PAUSE_DUR Pause Duration
Pause duration field used in PAUSE frames.
23.5.14 Descriptor Individual Upper Address Register

(ENET_IAUR)
IAUR contains the upper 32 bits of the 64-bit individual address hash table. The address
recognition process uses this table to check for a possible match with the destination
address (DA) field of receive frames with an individual DA. This register is not reset and
you must initialize it.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IADDR1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IAUR field descriptions

Field Description
IADDR1 Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive
frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains
hash index bit 32.

23.5.15 Descriptor Individual Lower Address Register

(ENET_IALR)
IALR contains the lower 32 bits of the 64-bit individual address hash table. The address
recognition process uses this table to check for a possible match with the DA field of
receive frames with an individual DA. This register is not reset and you must initialize it.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IADDR2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IALR field descriptions

Field Description
IADDR2 Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive
frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains
hash index bit 0.
23.5.16 Descriptor Group Upper Address Register (ENET_GAUR)

GAUR contains the upper 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. You must initialize this register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
GADDR1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_GAUR field descriptions

Field Description
GADDR1 Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive
frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains
hash index bit 32.

23.5.17 Descriptor Group Lower Address Register (ENET_GALR)

GALR contains the lower 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. You must initialize this register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
GADDR2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_GALR field descriptions

Field Description
GADDR2 Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive
frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains
hash index bit 0.
23.5.18 Transmit FIFO Watermark Register (ENET_TFWR)

If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required in
the transmit FIFO before transmission of a frame can begin. This allows you to minimize
transmit latency (TFWR = 00 or 01) or allow for larger bus access latency (TFWR = 11)
due to contention for the system bus. Setting the watermark to a high value minimizes the
risk of transmit FIFO underrun due to contention for the system bus. The byte counts
associated with the TFWR field may need to be modified to match a given system
requirement, for example, worst-case bus access latency by the transmit data uDMA
channel.
When the FIFO level reaches the value the TFWR field and when the STR_FWD is set to
‘0’, the MAC transmit control logic starts frame transmission even before the end-of-
frame is available in the FIFO (cut-through operation).
If a complete frame has a size smaller than the threshold programmed with TFWR, the
MAC also transmits the Frame to the line.
To enable store and forward on the Transmit path, set STR_FWD to ‘1’. In this case, the
MAC starts to transmit data only when a complete frame is stored in the Transmit FIFO.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
STRFWD
TFWR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_TFWR field descriptions

Field Description
8 Store And Forward Enable
STRFWD
0 Reset. The transmission start threshold is programmed in TFWR[TFWR].
1 Enabled.
TFWR Transmit FIFO Write
If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in steps of 64 bytes, written to the
transmit FIFO before transmission of a frame begins.
NOTE: If a frame with less than the threshold is written, it is still sent independently of this threshold
setting. The threshold is relevant only if the frame is larger than the threshold given.
000000 64 bytes written.

... ...
23.5.19 Receive Descriptor Ring Start Register (ENET_RDSR)

RDSR points to the beginning of the circular receive buffer descriptor queue in external
memory. This pointer must be 64-bit aligned (bits 2–0 must be zero); however, it is
recommended to be 128-bit aligned, that is, evenly divisible by 16.
NOTE
This register must be initialized prior to operation

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
R_DES_START
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
R_DES_START
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RDSR field descriptions

Field Description
31–3 Pointer to the beginning of the receive buffer descriptor queue.
R_DES_START
23.5.20 Transmit Buffer Descriptor Ring Start Register

(ENET_TDSR)
TDSR provides a pointer to the beginning of the circular transmit buffer descriptor queue
in external memory. This pointer must be 64-bit aligned (bits 2–0 must be zero);
however, it is recommended to be 128-bit aligned, that is, evenly divisible by 16.
NOTE
This register must be initialized prior to operation.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
X_DES_START
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
X_DES_START
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_TDSR field descriptions

Field Description
31–3 Pointer to the beginning of the transmit buffer descriptor queue.
X_DES_START

ENET_TDSR field descriptions (continued)

Field Description
23.5.21 Maximum Receive Buffer Size Register (ENET_MRBR)

The MRBR is a user-programmable register that dictates the maximum size of all receive
buffers. This value should take into consideration that the receive CRC is always written
into the last receive buffer.
• R_BUF_SIZE is concatentated with the four least-significant bits of this register and
are used as the maximum receive buffer size.
• To allow one maximum size frame per buffer, MRBR must be set to RCR[MAX_FL]
or larger.
• To properly align the buffer, MRBR must be evenly divisible by 16. To ensure this,
the lower four bits are set to zero by the device.
• To minimize bus usage (descriptor fetches), set MRBR greater than or equal to 256
bytes.
NOTE
This register must be initialized before operation.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
R_BUF_SIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_MRBR field descriptions

Field Description
10–4 Receive buffer size in bytes. This value, concatenated with the four least-significant bits of this register
R_BUF_SIZE (which are always zero), is the effective maximum receive buffer size.
Reserved This field, which is always zero, is the four least-significant bits of the maximum receive buffer size.
This field is reserved.


23.5.22 Receive FIFO Section Full Threshold (ENET_RSFL)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RX_SECTION_FULL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RSFL field descriptions

Field Description
RX_SECTION_ Value Of Receive FIFO Section Full Threshold
FULL
Value, in 64-bit words, of the receive FIFO section full threshold. Clear this field to enable store and
forward on the RX FIFO. When programming a value greater than 0 (cut-through operation), it must be
greater than RAEM[RX_ALMOST_EMPTY].
When the FIFO level reaches the value in this field, data is available in the Receive FIFO (cut-through
operation).
23.5.23 Receive FIFO Section Empty Threshold (ENET_RSEM)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 RX_SECTION_EMPTY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RSEM field descriptions

Field Description
RX_SECTION_ Value Of The Receive FIFO Section Empty Threshold
EMPTY
Value, in 64-bit words, of the receive FIFO section empty threshold. When the FIFO has reached this
level, a pause frame will be issued.
A value of 0 disables automatic pause frame generation.
When the FIFO level goes below the value programmed in this field, an XON pause frame is issued to
indicate the FIFO congestion is cleared to the remote Ethernet client.

ENET_RSEM field descriptions (continued)

Field Description
NOTE: The section-empty threshold indications from both FIFOs are OR'ed to cause XOFF pause frame
generation.
23.5.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RX_ALMOST_EMPTY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
ENET_RAEM field descriptions

Field Description
RX_ALMOST_ Value Of The Receive FIFO Almost Empty Threshold
EMPTY
Value, in 64-bit words, of the receive FIFO almost empty threshold. When the FIFO level reaches the
value programmed in this field and the end-of-frame has not been received for the frame yet, the core
receive read control stops FIFO read (and subsequently stops transferring data to the MAC client
application). It continues to deliver the frame, if again more data than the threshold or the end-of-frame is
available in the FIFO. A minimum value of 4 should be set.
23.5.25 Receive FIFO Almost Full Threshold (ENET_RAFL)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RX_ALMOST_FULL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
ENET_RAFL field descriptions

Field Description
RX_ALMOST_ Value Of The Receive FIFO Almost Full Threshold
FULL
Value, in 64-bit words, of the receive FIFO almost full threshold. When the FIFO level comes close to the
maximum, so that there is no more space for at least RX_ALMOST_FULL number of words, the MAC
stops writing data in the FIFO and truncates the received frame to avoid FIFO overflow. The
corresponding error status will be set when the frame is delivered to the application. A minimum value of 4
should be set.

23.5.26 Transmit FIFO Section Empty Threshold (ENET_TSEM)

Address: 218_8000h base + 1A0h offset = 218_81A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TX_SECTION_EMPTY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_TSEM field descriptions

Field Description
TX_SECTION_ Value Of The Transmit FIFO Section Empty Threshold
EMPTY
Value, in 64-bit words, of the transmit FIFO section empty threshold. See Transmit FIFO for more
information.
23.5.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TX_ALMOST_EMPTY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
ENET_TAEM field descriptions

Field Description
TX_ALMOST_ Value of Transmit FIFO Almost Empty Threshold
EMPTY
Value, in 64-bit words, of the transmit FIFO almost empty threshold.
When the FIFO level reaches the value programmed in this field, and no end-of-frame is available for the
frame, the MAC transmit logic, to avoid FIFO underflow, stops reading the FIFO and transmits a frame
with an MII error indication. See Transmit FIFO for more information.
A minimum value of 4 should be set.

23.5.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TX_ALMOST_FULL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
ENET_TAFL field descriptions

Field Description
TX_ALMOST_ Value Of The Transmit FIFO Almost Full Threshold
FULL
Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum value of six is required . A
recommended value of at least 8 should be set allowing a latency of two clock cycles to the application. If
more latency is required the value can be increased as necessary (latency = TAFL - 5).
When the FIFO level comes close to the maximum, so that there is no more space for at least
TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the application does not react on
this signal, the FIFO write control logic, to avoid FIFO overflow, truncates the current frame and sets the
error status. As a result, the frame will be transmitted with an GMII/MII error indication. See Transmit FIFO
for more information.
NOTE: A FIFO overflow is a fatal error and requires a global reset on the transmit datapath or at least
deassertion of ETHEREN.
23.5.29 Transmit Inter-Packet Gap (ENET_TIPG)

Address: 218_8000h base + 1ACh offset = 218_81ACh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 IPG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
ENET_TIPG field descriptions

Field Description
IPG Transmit Inter-Packet Gap
Indicates the IPG, in bytes, between transmitted frames. Valid values range from 8 to 26. If the written
value is less than 8 or greater than 26, the internal (effective) IPG is 12.
NOTE: The IPG value read will be the value that was written, even if it is out of range.

23.5.30 Frame Truncation Length (ENET_FTRL)

Address: 218_8000h base + 1B0h offset = 218_81B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TRUNC_FL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
ENET_FTRL field descriptions

Field Description
TRUNC_FL Frame Truncation Length
Indicates the value a receive frame is truncated, if it is greater than this value. Must be greater than or
equal to RCR[MAX_FL].
NOTE: Truncation happens at TRUNC_FL. However, when truncation occurs, the application (FIFO) may
receive less data, guaranteeing that it never receives more than the set limit.
23.5.31 Transmit Accelerator Function Configuration

(ENET_TACC)
TACC controls accelerator actions when sending frames. The register can be changed
before or after each frame, but it must remain unmodified during frame writes into the
transmit FIFO.
The TFWR[STRFWD] field must be set to use the checksum feature.
Address: 218_8000h base + 1C0h offset = 218_81C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PROCHK
SHIFT16
IPCHK
W 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENET_TACC field descriptions

Field Description
4 Enables insertion of protocol checksum.
PROCHK
0 Checksum not inserted.
1 If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
frame. The checksum field must be cleared. The other frames are not modified.
3 Enables insertion of IP header checksum.
IPCHK
0 Checksum is not inserted.
1 If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field
must be cleared. If a non-IP frame is transmitted the frame is not modified.
0 TX FIFO Shift-16
SHIFT16
0 Disabled.
1 Indicates to the transmit data FIFO that the written frames contain two additional octets before the
frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet
header is extended to a 16-byte header.
23.5.32 Receive Accelerator Function Configuration

(ENET_RACC)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PADREM
SHIFT16
LINEDIS
PRODIS
IPDIS
W 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RACC field descriptions

Field Description

ENET_RACC field descriptions (continued)

Field Description
7 RX FIFO Shift-16
SHIFT16
When this field is set, the actual frame data starts at bit 16 of the first word read from the RX FIFO aligning
the Ethernet payload on a 32-bit boundary.
NOTE: This function only affects the FIFO storage and has no influence on the statistics, which use the
actual length of the frame received.
0 Disabled.
1 Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
6 Enable Discard Of Frames With MAC Layer Errors
LINEDIS
0 Frames with errors are not discarded.
1 Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to
the user application interface.
2 Enable Discard Of Frames With Wrong Protocol Checksum
PRODIS
0 Frames with wrong checksum are not discarded.
1 If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum,
the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward
mode (RSFL cleared).
1 Enable Discard Of Frames With Wrong IPv4 Header Checksum
IPDIS
0 Frames with wrong IPv4 header checksum are not discarded.
1 If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
header checksum and is not affected by this setting. Discarding is only available when the RX FIFO
operates in store and forward mode (RSFL cleared).
0 Enable Padding Removal For Short IP Frames
PADREM
0 Padding not removed.
1 Any bytes following the IP payload section of the frame are removed from the frame.
23.5.33 Reserved Statistic Register (ENET_RMON_T_DROP)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_DROP field descriptions

Field Description
Reserved This read-only field always has the value 0.

23.5.34 Tx Packet Count Statistic Register

(ENET_RMON_T_PACKETS)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_PACKETS field descriptions

Field Description
TXPKTS Packet count
Transmit packet count
23.5.35 Tx Broadcast Packets Statistic Register

(ENET_RMON_T_BC_PKT)
RMON Tx Broadcast Packets
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_BC_PKT field descriptions

Field Description
TXPKTS Broadcast packets

23.5.36 Tx Multicast Packets Statistic Register

(ENET_RMON_T_MC_PKT)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_MC_PKT field descriptions

Field Description
TXPKTS Multicast packets
23.5.37 Tx Packets with CRC/Align Error Statistic Register

(ENET_RMON_T_CRC_ALIGN)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_CRC_ALIGN field descriptions

Field Description
TXPKTS Packets with CRC/align error

23.5.38 Tx Packets Less Than Bytes and Good CRC Statistic

Register (ENET_RMON_T_UNDERSIZE)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_UNDERSIZE field descriptions

Field Description
TXPKTS Number of transmit packets less than 64 bytes with good CRC
23.5.39 Tx Packets GT MAX_FL bytes and Good CRC Statistic

Register (ENET_RMON_T_OVERSIZE)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_OVERSIZE field descriptions

Field Description
TXPKTS Number of transmit packets greater than MAX_FL bytes with good CRC

23.5.40 Tx Packets Less Than 64 Bytes and Bad CRC Statistic

Register (ENET_RMON_T_FRAG)
.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_FRAG field descriptions

Field Description
TXPKTS Number of packets less than 64 bytes with bad CRC
23.5.41 Tx Packets Greater Than MAX_FL bytes and Bad CRC

Statistic Register (ENET_RMON_T_JAB)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_JAB field descriptions

Field Description
TXPKTS Number of transmit packets greater than MAX_FL bytes and bad CRC

23.5.42 Tx Collision Count Statistic Register

(ENET_RMON_T_COL)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_COL field descriptions

Field Description
TXPKTS Number of transmit collisions
23.5.43 Tx 64-Byte Packets Statistic Register

(ENET_RMON_T_P64)
.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_P64 field descriptions

Field Description
TXPKTS Number of 64-byte transmit packets

23.5.44 Tx 65- to 127-byte Packets Statistic Register

(ENET_RMON_T_P65TO127)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_P65TO127 field descriptions

Field Description
TXPKTS Number of 65- to 127-byte transmit packets

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description

.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
23.5.49 Tx Packets Greater Than 2048 Bytes Statistic Register

(ENET_RMON_T_P_GTE2048)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TXPKTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_T_P_GTE2048 field descriptions

Field Description
TXPKTS Number of transmit packets greater than 2048 bytes
23.5.50 Tx Octets Statistic Register (ENET_RMON_T_OCTETS)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TXOCTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENET_RMON_T_OCTETS field descriptions

Field Description
TXOCTS Number of transmit octets
23.5.51 Reserved Statistic Register (ENET_IEEE_T_DROP)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_DROP field descriptions

Field Description
Reserved This read-only field always has the value 0.
23.5.52 Frames Transmitted OK Statistic Register

(ENET_IEEE_T_FRAME_OK)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_FRAME_OK field descriptions

Field Description
COUNT Number of frames transmitted OK
NOTE: Does not increment for the broadcast frames when broadcast reject is enabled and promiscuous
mode is disabled within the receive control register (RCR).

23.5.53 Frames Transmitted with Single Collision Statistic

Register (ENET_IEEE_T_1COL)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_1COL field descriptions

Field Description
COUNT Number of frames transmitted with one collision
23.5.54 Frames Transmitted with Multiple Collisions Statistic

Register (ENET_IEEE_T_MCOL)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_MCOL field descriptions

Field Description
COUNT Number of frames transmitted with multiple collisions

23.5.55 Frames Transmitted after Deferral Delay Statistic

Register (ENET_IEEE_T_DEF)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_DEF field descriptions

Field Description
COUNT Number of frames transmitted with deferral delay
23.5.56 Frames Transmitted with Late Collision Statistic Register

(ENET_IEEE_T_LCOL)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_LCOL field descriptions

Field Description
COUNT Number of frames transmitted with late collision

23.5.57 Frames Transmitted with Excessive Collisions Statistic

Register (ENET_IEEE_T_EXCOL)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_EXCOL field descriptions

Field Description
COUNT Number of frames transmitted with excessive collisions
23.5.58 Frames Transmitted with Tx FIFO Underrun Statistic

Register (ENET_IEEE_T_MACERR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_MACERR field descriptions

Field Description
COUNT Number of frames transmitted with transmit FIFO underrun

23.5.59 Frames Transmitted with Carrier Sense Error Statistic

Register (ENET_IEEE_T_CSERR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_CSERR field descriptions

Field Description
COUNT Number of frames transmitted with carrier sense error
23.5.60 Reserved Statistic Register (ENET_IEEE_T_SQE)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_SQE field descriptions

Field Description
COUNT This read-only field is reserved and always has the value 0.
NOTE: Counter not implemented as no SQE information is available.

23.5.61 Flow Control Pause Frames Transmitted Statistic

Register (ENET_IEEE_T_FDXFC)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_FDXFC field descriptions

Field Description
COUNT Number of flow-control pause frames transmitted
23.5.62 Octet Count for Frames Transmitted w/o Error Statistic

Register (ENET_IEEE_T_OCTETS_OK)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_T_OCTETS_OK field descriptions

Field Description
COUNT Octet count for frames transmitted without error
NOTE
Counts total octets (includes header and FCS fields).

23.5.63 Rx Packet Count Statistic Register

(ENET_RMON_R_PACKETS)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_PACKETS field descriptions

Field Description
COUNT Number of packets received
23.5.64 Rx Broadcast Packets Statistic Register

(ENET_RMON_R_BC_PKT)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_BC_PKT field descriptions

Field Description
COUNT Number of receive broadcast packets

23.5.65 Rx Multicast Packets Statistic Register

(ENET_RMON_R_MC_PKT)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_MC_PKT field descriptions

Field Description
COUNT Number of receive multicast packets
23.5.66 Rx Packets with CRC/Align Error Statistic Register

(ENET_RMON_R_CRC_ALIGN)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_CRC_ALIGN field descriptions

Field Description
COUNT Number of receive packets with CRC or align error

23.5.67 Rx Packets with Less Than 64 Bytes and Good CRC

Statistic Register (ENET_RMON_R_UNDERSIZE)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_UNDERSIZE field descriptions

Field Description
COUNT Number of receive packets with less than 64 bytes and good CRC
23.5.68 Rx Packets Greater Than MAX_FL and Good CRC

Statistic Register (ENET_RMON_R_OVERSIZE)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_OVERSIZE field descriptions

Field Description
COUNT Number of receive packets greater than MAX_FL and good CRC

23.5.69 Rx Packets Less Than 64 Bytes and Bad CRC Statistic

Register (ENET_RMON_R_FRAG)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_FRAG field descriptions

Field Description
COUNT Number of receive packets with less than 64 bytes and bad CRC
23.5.70 Rx Packets Greater Than MAX_FL Bytes and Bad CRC

Statistic Register (ENET_RMON_R_JAB)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_JAB field descriptions

Field Description
COUNT Number of receive packets greater than MAX_FL and bad CRC
23.5.71 Reserved Statistic Register (ENET_RMON_R_RESVD_0)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENET_RMON_R_RESVD_0 field descriptions

Field Description
23.5.72 Rx 64-Byte Packets Statistic Register

(ENET_RMON_R_P64)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_P64 field descriptions

Field Description
COUNT Number of 64-byte receive packets
23.5.73 Rx 65- to 127-Byte Packets Statistic Register

(ENET_RMON_R_P65TO127)
Address: 218_8000h base + 2ACh offset = 218_82ACh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_P65TO127 field descriptions

Field Description
COUNT Number of 65- to 127-byte recieve packets


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description

Address: 218_8000h base + 2BCh offset = 218_82BCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description

23.5.78 Rx Packets Greater than 2048 Bytes Statistic Register

(ENET_RMON_R_P_GTE2048)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_P_GTE2048 field descriptions

Field Description
COUNT Number of greater-than-2048-byte recieve packets
23.5.79 Rx Octets Statistic Register (ENET_RMON_R_OCTETS)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_RMON_R_OCTETS field descriptions

Field Description
COUNT Number of receive octets

23.5.80 Frames not Counted Correctly Statistic Register

(ENET_IEEE_R_DROP)
Counter increments if a frame with invalid or missing SFD character is detected and has
been dropped. None of the other counters increments if this counter increments.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_R_DROP field descriptions

Field Description
COUNT Frame count
23.5.81 Frames Received OK Statistic Register

(ENET_IEEE_R_FRAME_OK)
Address: 218_8000h base + 2CCh offset = 218_82CCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_R_FRAME_OK field descriptions

Field Description
COUNT Number of frames received OK

23.5.82 Frames Received with CRC Error Statistic Register

(ENET_IEEE_R_CRC)
Address: 218_8000h base + 2D0h offset = 218_82D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_R_CRC field descriptions

Field Description
COUNT Number of frames received with CRC error
23.5.83 Frames Received with Alignment Error Statistic Register

(ENET_IEEE_R_ALIGN)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_R_ALIGN field descriptions

Field Description
COUNT Number of frames received with alignment error

23.5.84 Receive FIFO Overflow Count Statistic Register

(ENET_IEEE_R_MACERR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_R_MACERR field descriptions

Field Description
COUNT Receive FIFO overflow count
23.5.85 Flow Control Pause Frames Received Statistic Register

(ENET_IEEE_R_FDXFC)
Address: 218_8000h base + 2DCh offset = 218_82DCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_R_FDXFC field descriptions

Field Description
COUNT Number of flow-control pause frames received

23.5.86 Octet Count for Frames Received without Error Statistic

Register (ENET_IEEE_R_OCTETS_OK)
Address: 218_8000h base + 2E0h offset = 218_82E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_IEEE_R_OCTETS_OK field descriptions

Field Description
COUNT Number of octets for frames received without error
NOTE: Counts total octets (includes header and FCS fields). Does not increment for the broadcast
frames when broadcast reject is enabled and promiscuous mode is disabled within the receive
control register (RCR).
23.5.87 Adjustable Timer Control Register (ENET_ATCR)

ATCR command fields can trigger the corresponding events directly. It is not necessary
to preserve any of the configuration fields when a command field is set in the register,
that is, no read-modify-write is required.
NOTE
The CAPTURE and RESTART fields and bits 12 and 10 must
be 0 in order to write to the other fields in this register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
CAPTURE
RESTART
R
Reserved
Reserved
OFFRST
PINPER
PEREN
OFFEN
SLAVE
EN
W 0 0 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENET_ATCR field descriptions

Field Description
13 Enable Timer Slave Mode
SLAVE
NOTE: Timer slave mode is not supported on this device. This field must be set to 0.
0 The timer is active and all configuration fields in this register are relevant.
1 The internal timer is disabled and the externally provided timer value is used. All other fields, except
CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer
value.
11 Capture Timer Value
CAPTURE
When this field is set, all other fields are ignored during a write. This field automatically clears to 0 after the
command completes.
NOTE: To ensure that the correct time value is read from the ATVR register, a minimum amount of time
must elapse from issuing this command to reading the ATVR register. This minimum time is
defined by the greater of either six register clock cycles or six 1588/timestamp clock cycles.
0 No effect.
1 The current time is captured and can be read from the ATVR register.
9 Reset Timer
RESTART
Resets the timer to zero. This has no effect on the counter enable. If the counter is enabled when this field
is set, the timer is reset to zero and starts counting from there. When set, all other fields are ignored during
a write. This field automatically clears to 0 after the command completes. RESTART should be used when
the timer is enabled.
NOTE: The Reset Timer command requires at least 6 clock cycles of either the register clock or the
1588/timestamp clock, whichever is greater, to complete.
Reserved
7 Enables event signal output assertion on period event.
PINPER
NOTE: Not all devices contain the event signal output. See the chip configuration details.
0 Disable.
1 Enable.
Reserved
Reserved
NOTE: This field must be written always with one.
4 Enable Periodical Event
PEREN

ENET_ATCR field descriptions (continued)

Field Description
0 Disable.
1 A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted
when the timer wraps around according to the periodic setting ATPER. The timer period value must be
set before setting this bit.
NOTE: Not all devices contain the event signal output. See the chip configuration details.
3 Reset Timer On Offset Event
OFFRST
0 The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
1 If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not
cause a timer interrupt.
2 Enable One-Shot Offset Event
OFFEN
0 Disable.
1 The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
when the offset event is reached, so no further event occurs until the field is set again. The timer offset
value must be set before setting this field.
Reserved
0 Enable Timer
EN
0 The timer stops at the current value.
1 The timer starts incrementing.
23.5.88 Timer Value Register (ENET_ATVR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ATIME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_ATVR field descriptions

Field Description
ATIME A write sets the timer. A read returns the last captured value. To read the current value, issue a capture
command (i.e., set ATCR[CAPTURE]) prior to reading this register.
23.5.89 Timer Offset Register (ENET_ATOFF)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OFFSET
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENET_ATOFF field descriptions

Field Description
OFFSET Offset value for one-shot event generation. When the timer reaches the value, an event can be generated
to reset the counter. If the increment value in ATINC is given in true nanoseconds, this value is also given
in true nanoseconds.
23.5.90 Timer Period Register (ENET_ATPER)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
PERIOD
Reset 0 0 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0
ENET_ATPER field descriptions

Field Description
PERIOD Value for generating periodic events. Each instance the timer reaches this value, the period event occurs
and the timer restarts. If the increment value in ATINC is given in true nanoseconds, this value is also
given in true nanoseconds. The value should be initialized to 1,000,000,000 (1✕109) to represent a timer
wrap around of one second. The increment value set in ATINC should be set to the true nanoseconds of
the period of clock ts_clk, hence implementing a true 1 second counter.
NOTE: The value of PERIOD has the following constraint:

232 − ENET_ATINC[INC_COR] − 3✕ENET_ATINC[INC] ≥ PERIOD > 0.
23.5.91 Timer Correction Register (ENET_ATCOR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 COR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
COR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_ATCOR field descriptions

Field Description
COR Correction Counter Wrap-Around Value

ENET_ATCOR field descriptions (continued)

Field Description
Defines after how many timer clock cycles (ts_clk) the correction counter should be reset and trigger a
correction increment on the timer. The amount of correction is defined in ATINC[INC_CORR]. A value of 0
disables the correction counter and no corrections occur.
NOTE: This value is given in clock cycles, not in nanoseconds as all other values.
23.5.92 Time-Stamping Clock Period Register (ENET_ATINC)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
INC_CORR INC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_ATINC field descriptions

Field Description
14–8 Correction Increment Value
INC_CORR
This value is added every time the correction timer expires (every clock cycle given in ATCOR). A value
less than INC slows down the timer. A value greater than INC speeds up the timer.
INC Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
The timer increments by this amount each clock cycle. For example, set to 10 for 100 MHz, 8 for 125 MHz,
5 for 200 MHz.
NOTE: For highest precision, use a value that is an integer fraction of the period set in ATPER.
23.5.93 Timestamp of Last Transmitted Frame (ENET_ATSTMP)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TIMESTAMP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENET_ATSTMP field descriptions

Field Description
TIMESTAMP Timestamp of the last frame transmitted by the core that had TxBD[TS] set . This register is only valid
when EIR[TS_AVAIL] is set.
23.5.94 Timer Global Status Register (ENET_TGSR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TF3 TF2 TF1 TF0

W w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_TGSR field descriptions

Field Description
3 Copy Of Timer Flag For Channel 3
TF3
0 Timer Flag for Channel 3 is clear
1 Timer Flag for Channel 3 is set
TF2
TF1
TF0

23.5.95 Timer Control Status Register (ENET_TCSRn)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
TF
R
Reserved
Reserved TMODE TDRE
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_TCSRn field descriptions

Field Description
Reserved This field must be written with 0.
7 Timer Flag
TF
Sets when input capture or output compare occurs. This flag is double buffered between the module clock
and 1588 clock domains. When this field is 1, it can be cleared to 0 by writing 1 to it.
0 Input Capture or Output Compare has not occurred.

1 Input Capture or Output Compare has occurred.
6 This field must be written with 0.
Reserved
5–2 Timer Mode
TMODE
Updating the Timer Mode field takes a few cycles to register because it is synchronized to the 1588 clock.
The version of Timer Mode returned on a read is from the 1588 clock domain. When changing Timer
Mode, always disable the channel and read this register to verify the channel is disabled first.

ENET_TCSRn field descriptions (continued)

Field Description
0000 Timer Channel is disabled.
0001 Timer Channel is configured for Input Capture on rising edge.
0010 Timer Channel is configured for Input Capture on falling edge.
0011 Timer Channel is configured for Input Capture on both edges.
0100 Timer Channel is configured for Output Compare - software only.
0101 Timer Channel is configured for Output Compare - toggle output on compare.
0110 Timer Channel is configured for Output Compare - clear output on compare.
0111 Timer Channel is configured for Output Compare - set output on compare.
1000 Reserved
1010 Timer Channel is configured for Output Compare - clear output on compare, set output on
overflow.
10X1 Timer Channel is configured for Output Compare - set output on compare, clear output on
overflow.
110X Reserved
1110 Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-
clock cycle.
1111 Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-
clock cycle.
0 Timer DMA Request Enable
TDRE
0 DMA request is disabled
1 DMA request is enabled
23.5.96 Timer Compare Capture Register (ENET_TCCRn)

Address: 218_8000h base + 60Ch offset + (8d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
TCC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_TCCRn field descriptions

Field Description
TCC Timer Capture Compare
This register is double buffered between the module clock and 1588 clock domains.
When configured for compare, the 1588 clock domain updates with the value in the module clock domain
whenever the Timer Channel is first enabled and on each subsequent compare. Write to this register with
the first compare value before enabling the Timer Channel. When the Timer Channel is enabled, write the
second compare value either immediately, or at least before the first compare occurs. After each compare,
write the next compare value before the previous compare occurs and before clearing the Timer Flag.
The compare occurs one 1588 clock cycle after the IEEE 1588 Counter increments past the compare
value in the 1588 clock domain. If the compare value is less than the value of the 1588 Counter when the
Timer Channel is first enabled, then the compare does not occur until following the next overflow of the

ENET_TCCRn field descriptions (continued)

Field Description
1588 Counter. If the compare value is greater than the IEEE 1588 Counter when the 1588 Counter
overflows, or the compare value is less than the value of the IEEE 1588 Counter after the overflow, then
the compare occurs one 1588 clock cycle following the overflow.
When configured for capture, the value of the IEEE 1588 Counter is captured into the 1588 clock domain
and then updated into the module clock domain, provided the Timer Flag is clear. Always read the capture
value before clearing the Timer Flag.
23.6 Functional description

This section provides a complete functional description of the MAC-NET core.
23.6.1 Ethernet MAC frame formats

The IEEE 802.3 standard defines the Ethernet frame format as follows:
• Minimum length of 64 bytes
• Maximum length of 1518 bytes excluding the preamble and the start frame delimiter
(SFD) bytes
An Ethernet frame consists of the following fields:

• Seven bytes preamble
• Start frame delimiter (SFD)
• Two address fields
• Length or type field
• Data field
• Frame check sequence (CRC value)
• Extension field is defined only for Gigabit Ethernet half-duplex implementations and
is not supported by the MAC core

Functional description
7 octets Preamble
1 octet SFD
6 octets Destination address
6 octets Source address
2 octets Length/type Payload Length

Frame Length
0–1500/9000 octets Payload data
0–46 octets Pad
4 octets Frame check sequence (FCS)
Extension (half dup only)
Figure 23-2. MAC frame format overview
Optionally, MAC frames can be VLAN-tagged with an additional four-byte field inserted
between the MAC source address and the type/length field. VLAN tagging is defined by
the IEEE P802.1q specification. VLAN-tagged frames have a maximum length of 1522
bytes, excluding the preamble and the SFD bytes.
7 octets Preamble
1 octet SFD
6 octets Destination address
6 octets Source address
2 octets VLAN tag (0x8100)
2 octets VLAN info

Frame Length
2 octets Length/type Payload Length
0–1500/9000 octets Payload data
0–42 octets Pad
4 octets Frame check sequence (FCS)
Extension (half dup only)
Figure 23-3. VLAN-tagged MAC frame format overview
Table 23-5. MAC frame definition

Term Description
Frame length Defines the length, in octets, of the complete frame without preamble and SFD. A frame has a valid
length if it contains at least 64 octets and does not exceed the programmed maximum length.
Payload length The length/type field indicates the length of the frame's payload section. The most significant byte is
sent/received first.
• If the length/type field is set to a value less than 46, the payload is padded so that the
minimum frame length requirement (64 bytes) is met. For VLAN-tagged frames, a value less
than 42 indicates a padded frame.
• If the length/type field is set to a value larger than the programmed frame maximum length
(e.g. 1518) it is interpreted as a type field.

Table 23-5. MAC frame definition (continued)

Term Description
Destination and source 48-bit MAC addresses. The least significant byte is sent/received first and the first two least
address significant bits of the MAC address distinguish MAC frames, as detailed in MAC address check.
Note
Although the IEEE specification defines a maximum frame
length, the MAC core provides the flexibility to program any
value for the frame maximum length.
23.6.1.1 Pause Frames

The receiving device generates a pause frame to indicate a congestion to the emitting
device, which should stop sending data.
Pause frames are indicated by the length/type set to 0x8808. The two first bytes of a
pause frame following the type, defines a 16-bit opcode field set to 0x0001 always. A 16-
bit pause quanta is defined in the frame payload bytes 2 (P1) and 3 (P2) as defined in the
following table. The P1 pause quanta byte is the most significant.
Table 23-6. Pause Frame Format (Values in Hex)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
55 55 55 55 55 55 55 D5 01 80 C2 00 00 01
Preamble SFD Multicast Destination Address
15 16 17 18 19 20 21 22 23 24 25 26 27 –68
00 00 00 00 00 00 88 08 00 01 hi lo 00
Source Address Type Opcode P1 P2 pad (42)
69 70 71 72
26 6B AE 0A
CRC-32
There is no payload length field found within a pause frame and a pause frame is always
padded with 42 bytes (0x00).
If a pause frame with a pause value greater than zero (XOFF condition) is received, the
MAC stops transmitting data as soon the current frame transfer is completed. The MAC
stops transmitting data for the value defined in pause quanta. One pause quanta fraction
refers to 512 bit times.
If a pause frame with a pause value of zero (XON condition) is received, the transmitter
is allowed to send data immediately (see Full-duplex flow control operation for details).
23.6.1.2 Magic packets

A magic packet is a unicast, multicast, or broadcast packet, which carries a defined
sequence in the payload section.
Magic packets are received and inspected only under specific conditions as described in
Magic packet detection.
The defined sequence to decode a magic packet is formed with a synchronization stream
which consists of six consecutive 0xFF bytes, and is followed by sequence of sixteen
consecutive unicast MAC addresses of the node to be awakened.
This sequence can be located anywhere in the magic packet payload. The magic packet is
formed with a standard Ethernet header, optional padding, and CRC.
23.6.2 IP and higher layers frame format

The following sections use the term datagram to describe the protocol specific data unit
that is found within the payload section of its container entity.
For example, an IP datagram specifies the payload section of an Ethernet frame. A TCP
datagram specifies the payload section within an IP datagram.
23.6.2.1 Ethernet types

IP datagrams are carried in the payload section of an Ethernet frame. The Ethernet frame
type/length field discriminates several datagram types.
The following table lists the types of interest:
Table 23-7. Ethernet type value examples
Type Description
0x8100 VLAN-tagged frame. The actual type is found 4 octets later in the frame.
0x0800 IPv4
0x0806 ARP
0x86DD IPv6

23.6.2.2 IPv4 datagram format

The following figure shows the IP Version 4 (IPv4) header, which is located at the
beginning of an IP datagram. It is organized in 32-bit words. The first byte sent/received
is the leftmost byte of the first word (in other words, version/IHL field).
The IP header can contain further options, which are always padded if necessary to
guarantee the payload following the header is aligned to a 32-bit boundary.
The IP header is immediately followed by the payload, which can contain further
protocol headers (for example, TCP or UDP, as indicated by the protocol field value).
The complete IP datagram is transported in the payload section of an Ethernet frame.
Table 23-8. IPv4 header format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Version IHL TOS Length
Fragment ID Flags Fragment offset
TTL Protocol Header checksum
Source address
Destination address
Options
Table 23-9. IPv4 header fields

Field name Description
Version 4-bit IP version information. 0x4 for IPv4 frames.
IHL 4-bit Internet header length information. Determines number of 32-bit words found within the
IP header. If no options are present, the default value is 0x5.
TOS Type of service/DiffServ field.
Length Total length of the datagram in bytes, including all octets of header and payload.
Fragment ID, flags, fragment Fields used for IP fragmentation.
offset
TTL Time-to-live. In effect, is decremented at each router arrival. If zero, datagram must be
discarded.
Protocol Identifier of protocol that follows in the datagram.
Header checksum Checksum of IP header. For computational purposes, this field's value is zero.
Source address Source IP address.
Destination address Destination IP address.

23.6.2.3 IPv6 datagram format

The following figure shows the IP version 6 (IPv6) header, which is located at the
beginning of an IP datagram. It is organized in 32-bit words and has a fixed length of ten
words (40 bytes). The next header field identifies the type of the header that follows the
IPv6 header. It is defined similar to the protocol identifier within IPv4, with new
definitions for identifying extension headers. These headers can be inserted between the
IPv6 header and the protocol header, which will shift the protocol header accordingly.The
accelerator currently only supports IPv6 without extension headers (in other words, the
next header specifies TCP, UDP, or IMCP).
The first byte sent/received is the leftmost byte of the first word (in other words, version/
traffic class fields).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Version Traffic class Flow label
Payload length Next header Hop limit
Source address
Destination address
Start of next header/payload
Figure 23-4. IPv6 header format
Table 23-10. IPv6 header fields

Version 4-bit IP version information. 0x6 for all IPv6 frames.
Traffic class 8-bit field defining the traffic class.
Flow label 20-bit flow label identifying frames of the same flow.
Payload length 16-bit length of the datagram payload in bytes. It includes all octets following the IPv6 header.
Next header Identifies the header that follows the IPv6 header. This can be the protocol header or any IPv6
defined extension header.
Hop limit Hop counter, decremented by one by each station that forwards the frame. If hop limit is 0 the frame
must be discarded.
Source address 128-bit IPv6 source address.
Destination address 128-bit IPv6 destination address.

23.6.2.4 Internet Control Message Protocol (ICMP) datagram format

An internet control message protocol (ICMP) is found following the IP header, if the
protocol identifier is 1. The ICMP datagram has a four-octet header followed by
additional message data.
Table 23-11. ICMP header format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type Code Checksum
ICMP message data
Table 23-12. IP header fields

Type 8-bit type information
Code 8-bit code that is related to the message type
Checksum 16-bit one's complement checksum over the complete ICMP datagram
23.6.2.5 User Datagram Protocol (UDP) datagram format

A user datagram protocol header is found after the IP header, when the protocol identifier
is 17.
The payload of the datagram is after the UDP header. The header byte order follows the
conventions given for the IP header above.
Table 23-13. UDP header format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Source port Destination port
Length Checksum
Table 23-14. UDP header fields

Source port Source application port
Destination port Destination application port
Length Length of user data which immediately follows the header, including the UDP header (that is,
minimum value is 8)
Checksum Checksum over the complete datagram and some IP header information

23.6.2.6 TCP datagram format

A TCP header is found following the IP header, when the protocol identifier has a value
of 6.
The TCP payload immediately follows the TCP header.
Table 23-15. TCP header format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Source port Destination port
Sequence number
Acknowledgement number
Offset Reserved Flags Window
Checksum Urgent pointer
Options
Table 23-16. TCP header fields

Source port Source application port
Destination port Destination application port
Sequence Transmit sequence number
number
Ack. number Receive sequence number
Offset Data offset, which is number of 32-bit words within TCP header — if no options selected, defaults to
value of 5
Flags URG, ACK, PSH, RST, SYN, FIN flags
Window TCP receive window size information
Checksum Checksum over the complete datagram (TCP header and data) and IP header information
Options Additional 32-bit words for protocol options
23.6.3 IEEE 1588 message formats

The following sections describe the IEEE 1588 message formats.

23.6.3.1 Transport encapsulation

The precision time protocol (PTP) datagrams are encapsulated in Ethernet frames using
the UDP/IP transport mechanism, or optionally, with the newer 1588v2 directly in
Ethernet frames (layer 2).
Typically, multicast addresses are used to allow efficient distribution of the
synchronization messages.
23.6.3.1.1 UDP/IP
The 1588 messages (v1 and v2) can be transported using UDP/IP multicast messages.
Table 23-17 shows IP multicast groups defined for PTP. The table also shows their
respective MAC layer multicast address mapping according to RFC 1112 (last three
octets of IP follow the fixed value of 01-00-5E).
Table 23-17. UDP/IP multicast domains
Name IP Address MAC Address mapping
DefaultPTPdomain 224.0.1.129 01-00-5E-00-01-81
AlternatePTPdomain1 224.0.1.130 01-00-5E-00-01-82
Table 23-18. UDP port numbers

Message type UDP port Note
Event 319 Used for SYNC and DELAY_REQUEST messages
General 320 All other messages (for example, follow-up, delay-response)
23.6.3.1.2 Native Ethernet (PTPv2)

In addition to using UDP/IP frames, IEEE 1588v2 defines a native Ethernet frame format
that uses ethertype = 0x88F7. The payload of the Ethernet frame immediately contains
the PTP datagram, starting with the PTPv2 header.
Besides others, version 2 adds a peer delay mechanism to allow delay measurements
between individual point-to-point links along a path over multiple nodes. The following
multicast domains are also defined in PTPv2.

Table 23-19. PTPv2 multicast domains

Name MAC address
Normal messages 01-1B-19-00-00-00
Peer delay messages 01-80-C2-00-00-0E
23.6.3.2 PTP header

All PTP frames contain a common header that determines the protocol version and the
type of message, which defines the remaining content of the message.
All multi-octet fields are transmitted in big-endian order (the most significant byte is
transmitted/received first).
The last four bits of versionPTP are at the same position (second byte) for PTPv1 and
PTPv2 headers. This allows accurate identification by inspecting the first two bytes of the
message.
23.6.3.2.1 PTPv1 header

Table 23-20. Common PTPv1 message header
Bits
Offset Octets
7 6 5 4 3 2 1 0
0 2 versionPTP = 0x0001
2 2 versionNetwork
4 16 subdomain
20 1 messageType
21 1 sourceCommunicationTechnology
22 6 sourceUuid
28 2 sourcePortId
30 2 sequenceId
32 1 control
33 1 0x00
34 2 flags
36 4 reserved
The type of message is encoded in the messageType and control fields as shown in Table
23-21 :

Table 23-21. PTPv1 message type identification

messageType control Message Name Message
0x01 0x0 SYNC Event message
0x01 0x1 DELAY_REQ Event message
0x02 0x2 FOLLOW_UP General message
0x02 0x3 DELAY_RESP General message
0x02 0x4 MANAGEMENT General message
other other — Reserved
The field sequenceId is used to non-ambiguously identify a message.
23.6.3.2.2 PTPv2 header

Table 23-22. Common PTPv2 message header
Bits
Offset Octets
7 6 5 4 3 2 1 0
0 1 transportSpecific messageId
1 1 reserved versionPTP = 0x2
2 2 messageLength
4 1 domainNumber
5 1 reserved
6 2 flags
8 8 correctionField
16 4 reserved
20 10 sourcePortIdentity
30 2 sequenceId
32 1 control
33 1 logMeanMessageInterval
The type of message is encoded in the field messageId as follows:

Table 23-23. PTPv2 message type identification
messageId Message name Message
0x0 SYNC Event message
0x1 DELAY_REQ Event message
0x2 PATH_DELAY_REQ Event message
0x3 PATH_DELAY_RESP Event message
0x4–0x7 — Reserved
0x8 FOLLOW_UP General message
0x9 DELAY_RESP General message

Table 23-23. PTPv2 message type identification (continued)

messageId Message name Message
0xa PATH_DELAY_FOLLOW_UP General message
0xb ANNOUNCE General message
0xc SIGNALING General message
0xd MANAGEMENT General message
The PTPv2 flags field contains further details on the type of message, especially if one-
step or two-step implementations are used. The one- or two-step implementation is
controlled by the TWO_STEP bit in the first octet of the flags field as shown below.
Reserved bits are cleared.
Table 23-24. PTPv2 message flags field definitions
Bit Name Description
0 ALTERNATE_MASTER See IEEE 1588 Clause 17.4
1 TWO_STEP 1 Two-step clock
0 One-step clock
2 UNICAST 1 Transport layer address uses a unicast destination address
0 Multicast is used
3 — Reserved
4 — Reserved
5 Profile specific
6 Profile specific
7 — Reserved
23.6.4 MAC receive

The MAC receive engine performs the following tasks:
• Check frame framing
• Remove frame preamble and frame SFD field
• Discard frame based on frame destination address field
• Terminate pause frames
• Check frame length
• Remove payload padding if it exists

• Calculate and verify CRC-32

• Write received frames in the core receive FIFO
If the MAC is programmed to operate in half-duplex mode, it will also check if the frame
is received with a collision.
Discard Detect Preamble
Collision
Discard
Half duplex only
Discard Compare destination address

with local/multicast/broadcast
Discard Discriminate length/type

information
Receive payload
Remove padding
Verify CRC
Verify frame length
Write data FIFO

and frame status
Figure 23-5. MAC receive flow
23.6.4.1 Collision detection in half-duplex mode

If the packet is received with a collision detected during reception of the first 64 bytes,
the packet is discarded (if frame size was less than ~14 octets) or transmitted to the user
application with an error and RxBD[CE] set.
23.6.4.2 Preamble processing

The IEEE 802.3 standard allows a maximum size of 56 bits (seven bytes) for the
preamble, while the MAC core allows any preamble length, including zero length
preamble.
The MAC core checks for the start frame delimiter (SFD) byte. If the next byte of the
preamble, which is different from 0x55, is not 0xD5, the frame is discarded.

Although the IEEE specification dictates that the inner-packet gap should be at least 96
bits, the MAC core is designed to accept frames separated by only 64 10/100-Mbit/s
operation (MII) bits.
The MAC core removes the preamble and SFD bytes.
23.6.4.3 MAC address check

The destination address bit 0 differentiates between multicast and unicast addresses.
• If bit 0 is 0, the MAC address is an individual (unicast) address.
• If bit 0 is 1, the MAC address defines a group (multicast) address.
• If all 48 bits of the MAC address are set, it indicates a broadcast address.
23.6.4.3.1 Unicast address check

If a unicast address is received, the destination MAC address is compared to the node
MAC address programmed by the host in the PADDR1/2 registers.
If the destination address matches any of the programmed MAC addresses, the frame is
accepted.
If Promiscuous mode is enabled (RCR[PROM] = 1) no address checking is performed
and all unicast frames are accepted.
23.6.4.3.2 Multicast and unicast address resolution

The hash table algorithm used in the group and individual hash filtering operates as
follows.
• The 48-bit destination address is mapped into one of 64 bits, represented by 64 bits in
ENETn_GAUR/GALR (group address hash match) or ENETn_IAUR/IALR
(individual address hash match).
• This mapping is performed by passing the 48-bit address through the on-chip 32-bit
CRC generator and selecting the six most significant bits of the CRC-encoded result
to generate a number between 0 and 63.
• The msb of the CRC result selects ENETn_GAUR (msb = 1) or ENETn_GALR
(msb = 0).
• The five lsbs of the hash result select the bit within the selected register.
• If the CRC generator selects a bit set in the hash table, the frame is accepted; else, it
is rejected.

For example, if eight group addresses are stored in the hash table and random group
addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group
address frames from reaching memory. Those that do reach memory must be further
filtered by the processor to determine if they truly contain one of the eight desired
addresses.
The effectiveness of the hash table declines as the number of addresses increases.
The user must initialize the hash table registers. Use this CRC32 polynomial to compute
the hash:
• FCS(x) = x32+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x1+ 1
If Promiscuous mode is enabled (ENETn_RCR[PROM] = 1) all unicast and multicast

frames are accepted regardless of ENETn_GAUR/GALR and ENETn_IAUR/IALR
settings.
23.6.4.3.3 Broadcast address reject

All broadcast frames are accepted if BC_REJ is cleared or ENETn_RCR[PROM] is set.
If PROM is cleared when ENETn_RCR[BC_REJ] is set, all broadcast frames are
rejected.
Table 23-25. Broadcast address reject programming
PROM BC_REJ Broadcast frames
0 0 Accepted
0 1 Rejected
1 0 Accepted
1 1 Accepted
23.6.4.3.4 Miss-bit implementation

For higher layer filtering purposes, RxBD[M] indicates an address miss when the MAC
operates in promiscuous mode and accepts a frame that would otherwise be rejected.
If a group/individual hash or exact match does not occur and Promiscuous mode is
enabled (RCR[PROM] = 1), the frame is accepted and the M bit is set in the buffer
descriptor; otherwise, the frame is rejected.
This means the status bit is set in any of the following conditions during Promiscuous
mode:
• A broadcast frame is received when BC_REJ is set

• A unicast is received that does not match either:

• Node address (PALR[PADDR1] and PAUR[PADDR2])
• Hash table for unicast (IAUR[IADDR1] and IALR[IADDR2])
• A multicast is received that does not match the GAUR[GADDR1] and
GALR[GADDR2] hash table entries
23.6.4.4 Frame length/type verification: payload length check

If the length/type is less than 0x600 and NLC is set, the MAC checks the payload length
and reports any error in the frame status word and interrupt bit PLR.
If the length/type is greater than or equal to 0x600, the MAC interprets the field as a type
and no payload length check is performed.
The length check is performed on VLAN and stacked VLAN frames. If a padded frame is
received, no length check can be performed due to the extended frame payload because
padded frames can never have a payload length error.
23.6.4.5 Frame length/type verification: frame length check

When the receive frame length exceeds MAX_FL bytes, the BABR interrupt is generated
and the RxBD[LG] bit is set.
The frame is not truncated unless the frame length exceeds the value programmed in
ENETn_FTRL[TRUNC_FL]. If the frame is truncated, RxBD[TR] is set. In addition, a
truncated frame always has the CRC error indication set (RxBD[CR]).
23.6.4.6 VLAN frames processing

VLAN frames have a length/type field set to 0x8100 immediately followed by a 16-Bit
VLAN control information field.
VLAN-tagged frames are received as normal frames because the VLAN tag is not
interpreted by the MAC function, and are pushed complete with the VLAN tag to the user
application. If the length/type field of the VLAN-tagged frame, which is found four
octets later in the frame, is less than 42, the padding is removed. In addition, the frame
status word (RxBD[NO]) indicates that the current frame is VLAN tagged.

23.6.4.7 Pause frame termination

The receive engine terminates pause frames and does not transfer them to the receive
FIFO. The quanta is extracted and sent to the MAC transmit path via a small internal
clock rate decoupling asynchronous FIFO.
The quanta is written only if a correct CRC and frame length are detected by the control
state machine. If not, the quanta is discarded and the MAC transmit path is not paused.
Good pause frames are ignored if ENETn_RCR[FCE] is cleared and are forwarded to the
client interface when ENETn_RCR[PAUFWD] is set.
23.6.4.8 CRC check

The CRC-32 field is checked and forwarded to the core FIFO interface if
ENETn_RCR[CRCFWD] is cleared and ENETn_RCR[PADEN] is cleared. When
CRCFWD is set (regardless of PADEN), the CRC-32 field is checked and terminated
(not transmitted to the FIFO).
The CRC polynomial, as specified in the 802.3 standard, is:
The 32 bits of the CRC value are placed in the frame check sequence (FCS) field with the
x31 term as right-most bit of the first octet. The CRC bits are thus received in the
following order: x31, x30,..., x1, x0.
If a CRC error is detected, the frame is marked invalid and RxBD[CR] is set.
23.6.4.9 Frame padding removal

When a frame is received with a payload length field set to less than 46 (42 for VLAN-
tagged frames and 38 for frames with stacked VLANs), the zero padding can be removed
before the frame is written into the data FIFO depending on the setting of
ENETn_RCR[PADEN].
Note
If a frame is received with excess padding (in other words, the
length field is set as mentioned above, but the frame has more
than 64 octets) and padding removal is enabled, then the

padding is removed as normal and no error is reported if the

frame is otherwise correct (for example: good CRC, less than
maximum length, and no other error).
23.6.5 MAC transmit

Frame transmission starts when the transmit FIFO holds enough data.
After a transfer starts, the MAC transmit function performs the following tasks:
• Generates preamble and SFD field before frame transmission
• Generates XOFF pause frames if the receive FIFO reports a congestion or if
ENETn_TCR[TFC_PAUSE] is set with ENETn_OPD[PAUSE_DUR] set to a non-
zero value
• Generates XON pause frames if the receive FIFO congestion condition is cleared or
if TFC_PAUSE is set with PAUSE_DUR cleared
• Suspends Ethernet frame transfer (XOFF) if a non-zero pause quanta is received
from the MAC receive path
• Adds padding to the frame if required
• Calculates and appends CRC-32 to the transmitted frame
• Sends the frame with correct inter-packet gap (IPG) (deferring)
When the MAC is configured to operate in half-duplex mode, the following additional
tasks are performed:
• Collision detection
• Frame retransmit after back-off timer expires

Send Preamble
Send destination address
Send local MAC address

(overwrite FIFO data)
Send payload
Send padding
(if necessary)
Send CRC
Figure 23-6. Frame transmit overview
23.6.5.1 Frame payload padding

The IEEE specification defines a minimum frame length of 64 bytes.
If the frame sent to the MAC from the user application has a size smaller than 60 bytes,
the MAC automatically adds padding bytes (0x00) to comply with the Ethernet minimum
frame length specification. Transmit padding is always performed and cannot be
disabled.
If the MAC is not allowed to append a CRC (TxBD[TC] = 1), the user application is
responsible for providing frames with a minimum length of 64 octets.
23.6.5.2 MAC address insertion

On each frame received from the core transmit FIFO interface, the source MAC address
is either:
• Replaced by the address programmed in the PADDR1/2 fields
(ENETn_TCR[ADDINS] = 1)
• Transparently forwarded to the Ethernet line (ENETn_TCR[ADDINS] = 0)
23.6.5.3 CRC-32 generation

The CRC-32 field is optionally generated and appended at the end of a frame.

The CRC polynomial, as specified in the 802.3 standard, is:

The 32 bits of the CRC value are placed in the FCS field so that the x31 term is the right-
most bit of the first octet. The CRC bits are thus transmitted in the following order: x31,
x30,..., x1, x0.
23.6.5.4 Inter-packet gap (IPG)

In full-duplex mode, after frame transmission and before transmission of a new frame, an
IPG (programmed in ENETn_TIPG) is maintained. The minimum IPG can be
programmed between 8 and 26 byte-times (64 and 208 bit-times).
In half-duplex mode, the core constantly monitors the line. Actual transmission of the
data onto the network occurs only if it has been idle for a 96-bit time period, and any
back-off time requirements have been satisfied. In accordance with the standard, the core
begins to measure the IPG from CRS/GMII_CRS de-assertion.
23.6.5.5 Collision detection and handling — half-duplex operation

only
A collision occurs on a half-duplex network when concurrent transmissions from two or
more nodes take place. During transmission, the core monitors the line condition and
detects a collision when the PHY device asserts COL.
When the core detects a collision while transmitting, it stops transmission of the data and
transmits a 32-bit jam pattern. If the collision is detected during the preamble or the SFD
transmission, the jam pattern is transmitted after completing the SFD, which results in a
minimum 96-bit fragment. The jam pattern is a fixed pattern that is not compared to the
actual frame CRC, and has a very low probability (0.532) of having a jam pattern
identical to the CRC.
If a collision occurs before transmission of 64 bytes (including preamble and SFD), the
MAC core waits for the backoff period and retransmits the packet data (stored in a 64-
byte re-transmit buffer) that has already been sent on the line. The backoff period is
generated from a pseudo-random process (truncated binary exponential backoff).
If a collision occurs after transmission of 64 bytes (including preamble and SFD), the
MAC discards the remainder of the frame, optionally sets the LC interrupt bit, and sets
TxBD[LCE].

MAC Tx Engine
Backoff
Control
Period
PHY
MAC FIFO
Retransmit Enable
Buffer
Control MAC Transmit
address
address
Control
read
write
64x8 Frame
Discard
Retransmit
Buffer
Transmit FIFO
Interface
Interface
MAC Transmit
PHY
Datapath
Figure 23-7. Packet re-transmit overview
The backoff time is represented by an integer multiple of slot times. One slot is equal to a
512-bit time period. The number of the delay slot times, before the nth re-transmission
attempt, is chosen as a uniformly-distributed random integer in the range:
• 0 < r < 2k
• k = min(n, N); where n is the number of retransmissions and N = 10
For example, after the first collision, the backoff period is 0 or 1 slot time. If a collision
occurs on the first retransmission, the backoff period is 0, 1, 2, or 3, and so on.
The maximum backoff time (in 512-bit time slots) is limited by N = 10 as specified in the
IEEE 802.3 standard.
If a collision occurs after 16 consecutive retransmissions, the core reports an excessive
collision condition (ENETn_EIR[RL] interrupt field and TxBD[EE]) and discards the
current packet from the FIFO.
In networks violating the standard requirements, a collision may occur after transmission
of the first 64 bytes. In this case, the core stops the current packet transmission and
discards the rest of the packet from the transmit FIFO. The core resumes transmission
with the next packet available in the core transmit FIFO.
warning
Ethernet PHYs that support the SQE Test, or "heartbeat,"
feature must disable this feature. When this feature is enabled,

the PHY asserts the collision signal after a frame is transmitted

to indicate to the ENET that the PHY's collision logic is
working. This may cause data corruption in the next frame from
the ENET. This corrupted frame contains up to 21 zero bytes
which start somewhere within the MAC destination address
field. The ENET, however, will still generate a good FCS
(CRC-32) but with corrupted data.
23.6.6 Full-duplex flow control operation

Three conditions are handled by the core's flow control engine:
• Remote device congestion — The remote device connected to the same Ethernet
segment as the core reports congestion and requests that the core stop sending data.
• Core FIFO congestion — When the core's receive FIFO reaches a user-
programmable threshold (RX section empty), the core sends a pause frame back to
the remote device requesting the data transfer to stop.
• Local device congestion — Any device connected to the core can request (typically,
via the host processor) the remote device to stop transmitting data.
23.6.6.1 Remote device congestion

When the MAC transmit control gets a valid pause quanta from the receive path and if
ENETn_RCR[FCE] is set, the MAC transmit logic:
• Completes the transfer of the current frame.
• Stops sending data for the amount of time specified by the pause quanta in 512 bit
time increments.
• Sets ENETn_TCR[RFC_PAUSE].
Frame transfer resumes when the time specified by the quanta expires and if no new
quanta value is received, or if a new pause frame with a quanta value set to 0x0000 is
received. The MAC also resets RFC_PAUSE to zero.
If ENETn_RCR[FCE] cleared, the MAC ignores received pause frames.
Optionally and independent of ENETn_RCR[FCE], pause frames are forwarded to the
client interface if PAUFWD is set.

23.6.6.2 Local device/FIFO congestion

The MAC transmit engine generates pause frames when the local receive FIFO is not
able to receive more than a pre-defined number of words (FIFO programmable threshold)
or when pause frame generation is requested by the local host processor.
• To generate a pause frame, the host processor sets ENETn_TCR[TFC_PAUSE]. A
single pause frame is generated when the current frame transfer is completed and
TFC_PAUSE is automatically cleared. Optionally, an interrupt is generated.
• An XOFF pause frame is generated when the receive FIFO asserts its section empty
flag (internal). An XOFF pause frame is generated automatically, when the current
frame transfer completes.
• An XON pause frame is generated when the receive FIFO deasserts its section empty
flag (internal). An XON pause frame is generated automatically, when the current
frame transfer completes.
When an XOFF pause frame is generated, the pause quanta (payload byte P1 and P2) is
filled with the value programmed in ENETn_OPD[PAUSE_DUR].
From Ethernet line

To Ethernet line
TFC_PAUSE PAUSE_DUR
Pause frame generation

Programmable
threshold
Figure 23-8. Pause frame generation overview
Note
Although the flow control mechanism should prevent any FIFO
overflow on the MAC core receive path, the core receive FIFO
is protected. When an overflow is detected on the receive FIFO,
the current frame is truncated with an error indication set in the
frame status word. The frame should subsequently be discarded
by the user application.

23.6.7 Magic packet detection

Magic packet detection wakes a node that is put in power-down mode by the node
management agent. Magic packet detection is supported only if the MAC is configured in
sleep mode.
23.6.7.1 Sleep mode

To put the MAC in Sleep mode, set ENETn_ECR[SLEEP]. At the same time
ENETn_ECR[MAGICEN] should also be set to enable magic packet detection.
In addition, if ENET is enabled, write 1 to ENETn_ECR[SLEEP] before entering into
low power mode.
When the MAC is in Sleep mode:
• The transmit logic is disabled.
• The FIFO receive/transmit functions are disabled.
• The receive logic is kept in Normal mode, but it ignores all traffic from the line
except magic packets. They are detected so that a remote agent can wake the node.
23.6.7.2 Magic packet detection

The core is designed to detect magic packets (see Magic packets) with the destination
address set to:
• Any multicast address
• The broadcast address
• The unicast address programmed in PADDR1/2
When a magic packet is detected, EIR[WAKEUP] is set and none of the statistic registers
are incremented.

23.6.7.3 Wakeup
When a magic packet is detected, indicated by ENETn_EIR[WAKEUP],
ENETn_ECR[SLEEP] should be cleared to resume normal operation of the MAC.
Clearing the SLEEP bit automatically masks ENETn_ECR[MAGICEN], disabling magic
packet detection.
23.6.8 IP accelerator functions

The following sections describe the IP accelerator functions.
23.6.8.1 Checksum calculation

The IP and ICMP, TCP, UDP checksums are calculated with one's complement
arithmetic summing up 16-bit values.
• For ICMP, the checksum is calculated over the complete ICMP datagram, in other
words without IP header.
• For TCP and UDP, the checksums contain the header and data sections and values
from the IP header, which can be seen as a pseudo-header that is not actually present
in the data stream.
Table 23-26. IPv4 pseudo-header for checksum calculation

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Source address
Destination address
Zero Protocol TCP/UDP length
Table 23-27. IPv6 pseudo-header for checksum calculation

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Source address
Destination address
TCP/UDP length
Zero Next header

The TCP/UDP length value is the length of the TCP or UDP datagram, which is equal to
the payload of an IP datagram. It is derived by subtracting the IP header length from the
complete IP datagram length that is given in the IP header (IPv4), or directly taken from
the IP header (IPv6). The protocol field is the corresponding value from the IP header.
The Zero fields are all zeroes.
For IPv6, the complete 128-bit addresses are considered. The next header value identifies
the upper layer protocol as either TCP or UDP. It may differ from the next header value
of the IPv6 header if extension headers are inserted before the protocol header.
The checksum calculation uses 16-bit words in network byte order: The first byte sent/
received is the MSB, and the second byte sent/received is the LSB of the 16-bit value to
add to the checksum. If the frame ends on an odd number of bytes, a zero byte is
appended for checksum calculation only, and is not actually transmitted.
23.6.8.2 Additional padding processing

According to IEEE 802.3, any Ethernet frame must have a minimum length of 64 octets.
The MAC usually removes padding on receive when a frame with length information is
received. Because IP frames have a type value instead of length, the MAC does not
remove padding for short IP frames, as it is not aware of the frame contents.
The IP accelerator function can be configured to remove the Ethernet padding bytes that
might follow the IP datagram.
On transmit, the MAC automatically adds padding as necessary to fill any frame to a 64-
byte length.
23.6.8.3 32-bit Ethernet payload alignment

The data FIFOs allow inserting two additional arbitrary bytes in front of a frame. This
extends the 14-byte Ethernet header to a 16-byte header, which leads to alignment of the
Ethernet payload, following the Ethernet header, on a 32-bit boundary.
This function can be enabled for transmit and receive independently with the
corresponding SHIFT16 bits in the ENETn_TACC and ENETn_RACC registers.
When enabled, the valid frame data is arranged as shown in Table 23-28.
Table 23-28. 64-bit interface data structure with SHIFT16 enabled
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0

Table 23-28. 64-bit interface data structure with SHIFT16 enabled (continued)
Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Any value Any value
Byte 13 Byte 12 Byte 11 Byte 10 Byte 9 Byte 8 Byte 7 Byte 6
...
23.6.8.3.1 Receive processing

When ENETn_RACC[SHIFT16] is set, each frame is received with two additional bytes
in front of the frame.
The user application must ignore these first two bytes and find the first byte of the frame
in bits 23–16 of the first word from the RX FIFO.
Note
SHIFT16 must be set during initialization and kept set during
the complete operation, because it influences the FIFO write
behavior.
23.6.8.3.2 Transmit processing

When ENETn_TACC[SHIFT16] is set, the first two bytes of the first word written (bits
15–0) are discarded immediately by the FIFO write logic.
The SHIFT16 bit can be enabled/disabled for each frame individually if required, but can
be changed only between frames.
23.6.8.4 Received frame discard

Because the receive FIFO must be operated in store and forward mode (ENETn_RSFL
cleared), received frames can be discarded based on the following errors:
• The MAC function receives the frame with an error:
• The frame has an invalid payload length
• Frame length is greater than MAX_FL
• Frame received with a CRC-32 error
• Frame truncated due to receive FIFO overflow
• Frame is corrupted as PHY signaled an error (RX_ERR asserted during
reception)

• An IP frame is detected and the IP header checksum is wrong

• An IP frame with a valid IP header and a valid IP header checksum is detected, the
protocol is known but the protocol-specific checksum is wrong
If one of the errors occurs and the IP accelerator function is configured to discard frames
(ENETn_RACC), the frame is automatically discarded. Statistics are maintained
normally and are not affected by this discard function.
23.6.8.5 IPv4 fragments

When an IPv4 IP fragment frame is received, only the IP header is inspected and its
checksum verified. 32-bit alignment operates the same way on fragments as it does on
normal IP frames, as specified above.
The IP fragment frame payload is not inspected for any protocol headers. As such, a
protocol header would only exist in the very first fragment. To assist in protocol-specific
checksum verification, the one's-complement sum is calculated on the IP payload (all
bytes following the IP header) and provided with the frame status word.
The frame fragment status field (RxBD[FRAG]) is set to indicate a fragment reception,
and the one's-complement sum of the IP payload is available in RxBD[Payload
checksum].
Note
After all fragments have been received and reassembled, the
application software can take advantage of the payload
checksum delivered with the frame's status word to calculate
the protocol-specific checksum of the datagram.
For example, if a TCP payload is delivered by multiple IP
fragments, the application software can calculate the pseudo-
header checksum value from the first fragment, and add the
payload checksums delivered with the status for all fragments
to verify the TCP datagram checksum.
23.6.8.6 IPv6 support

The following sections describe the IPv6 support.

23.6.8.6.1 Receive processing

An Ethernet frame of type 0x86DD identifies an IP Version 6 frame (IPv6) frame. If an
IPv6 frame is received, the first IP header is inspected (first ten words), which is
available in every IPv6 frame.
If the receive SHIFT16 function is enabled, the IP header is aligned on a 32-bit boundary
allowing more efficient processing (see 32-bit Ethernet payload alignment).
For TCP and UDP datagrams, the pseudo-header checksum calculation is performed and
verified.
To assist in protocol-specific checksum verification, the one's-complement sum is always
calculated on the IP payload (all bytes following the IP header) and provided with the
frame status word. For example, if extension headers were present, their sums can be
subtracted in software from the checksum to isolate the TCP/UDP datagram checksum, if
required.
23.6.8.6.2 Transmit processing

For IPv6 transmission, the SHIFT16 function is supported to process 32-bit aligned
datagrams.
IPv6 has no IP header checksum; therefore, the IP checksum insertion configuration is
ignored.
The protocol checksum is inserted only if the next header of the IP header is a known
protocol (TCP, UDP, or ICMP). If a known protocol is detected, the checksum over all
bytes following the IP header is calculated and inserted in the correct position.
The pseudo-header checksum calculation is performed for TCP and UDP datagrams
accordingly.
23.6.9 Resets and stop controls

The following sections describe the resets and stop controls.
23.6.9.1 Hardware reset

To reset the Ethernet module, set ENETn_ECR[RESET].

23.6.9.2 Soft reset

When ENETn_ECR[ETHER_EN] is cleared during operation, the following occurs:
• uDMA, buffer descriptor, and FIFO control logic are reset, including the buffer
descriptor and FIFO pointers.
• A currently ongoing transmit is terminated by asserting GMII/TXER to the PHY.
• A currently ongoing transmit FIFO write from the application is terminated by
stopping the write to the FIFO, and all further data from the application is ignored.
All subsequent writes are ignored until re-enabled.
• A currently ongoing receive FIFO read is terminated. The RxBD has arbitrary values
in this case.
23.6.9.3 Hardware freeze

When the processor enters debug mode and ECR[DBGEN] is set, the MAC enters a
freeze state where it stops all transmit and receive activities gracefully.
The following happens when the MAC enters hardware freeze:
• A currently ongoing receive transaction on the receive application interface is
completed as normal. No further frames are read from the FIFO.
• A currently ongoing transmit transaction on the transmit application interface is
completed as normal (in other words, until writing end-of-packet (EOP)).
• A currently ongoing frame receive is completed normally, after which no further
frames are accepted from the MII/GMII.
• A currently ongoing frame transmit is completed normally, after which no further
frames are transmitted.
23.6.9.4 Graceful stop

During a graceful stop, any currently ongoing transactions are completed normally and
no further frames are accepted. The MAC can resume from a graceful stop without the
need for a reset (for example, clearing ETHER_EN is not required).
The following conditions lead to a graceful stop of the MAC transmit or receive
datapaths.

23.6.9.4.1 Graceful transmit stop (GTS)

When gracefully stopped, the MAC is no longer reading frame data from the transmit
FIFO and has completed any ongoing transmission.
In any of the following conditions, the transmit datapath stops after an ongoing frame
transmission has been completed normally.
• ENETn_TCR[GTS] is set by software.
• ENETn_TCR[TFC_PAUSE] is set by software requesting a pause frame
transmission. The status (and register bit) is cleared after the pause frame has been
sent.
• A pause frame was received stopping the transmitter. The stopped situation is
terminated when the pause timer expires or a pause frame with zero quanta is
received.
• MAC is placed in Sleep mode by software or the processor entering Stop mode (see
Sleep mode).
• The MAC is in Hardware Freeze mode.
When the transmitter has reached its stopped state, the following events occur:
• The GRA interrupt is asserted, when transitioned into stopped.
• In Hardware Freeze mode, the GRA interrupt does not wait for the application write
completion and asserts when the transmit state machine (in other words, line side of
TX FIFO) reaches its stopped state.
23.6.9.4.2 Graceful receive stop (GRS)

When gracefully stopped, the MAC is no longer writing frames into the receive FIFO.
The receive datapath stops after any ongoing frame reception has been completed
normally, if any of the following conditions occur:
• MAC is placed in Sleep mode either by the software or the processor is in Stop
mode). The MAC continues to receive frames and search for magic packets if
enabled (see Magic packet detection). However, no frames are written into the
receive FIFO, and therefore are not forwarded to the application.
• The MAC is in Hardware Freeze mode. The MAC does not accept any frames from
the MII/GMII.

When the receive datapath is stopped, the following events occur:

• If the RX is in the stopped state, RCR[GRS] is set
• The GRA interrupt is asserted when the transmitter and receiver are stopped
• Any ongoing receive transaction to the application (RX FIFO read) continues
normally until the frame end of package (EOP) is reached. After this, the following
occurs:
• When Sleep mode is active, all further frames are discarded, flushing the RX
FIFO
• In Hardware Freeze mode, no further frames are delivered to the application and
they stay in the receive FIFO.
Note
The assertion of GRS does not wait for an ongoing FIFO read
transaction on the application side of the FIFO (FIFO read).
23.6.9.4.3 Graceful stop interrupt (GRA)

The graceful stopped interrupt (GRA) is asserted for the following conditions:
• In Sleep mode, the interrupt asserts only after both TX and RX datapaths are stopped.
• In Hardware Freeze mode, the interrupt asserts only after both TX and RX datapaths
are stopped.
• The MAC transmit datapath is stopped for any other condition (GTS, TFC_PAUSE,
pause received).
The GRA interrupt is triggered only once when the stopped state is entered. If the
interrupt is cleared while the stop condition persists, no further interrupt is triggered.

23.6.10 IEEE 1588 functions

To allow for IEEE 1588 or similar time synchronization protocol implementations, the
MAC is combined with a time-stamping module to support precise time-stamping of
incoming and outgoing frames. Set ENETn_ECR[EN1588] to enable 1588 support.
MAC with 1588
10/100 MAC PHY

Frame data
Control/status
Adjustable Events
timer generator
n pulses/sec (pps)
Timing module
Control/status
Data Control
User application
Figure 23-9. IEEE 1588 functions overview
23.6.10.1 Adjustable timer module

The adjustable timer module (TSM) implements the free-running counter (FRC), which
generates the timestamps. The FRC operates with the time-stamping clock, which can be
set to any value depending on your system requirements.
Through dedicated correction logic, the timer can be adjusted to allow synchronization to
a remote master and provide a synchronized timing reference to the local system. The
timer can be configured to cause an interrupt after a fixed time period, to allow
synchronization of software timers or perform other synchronized system functions.
The timer is typically used to implement a period of one second; hence, its value ranges
from 0 to (1 × 109)-1. The period event can trigger an interrupt, and software can
maintain the seconds and hours time values as necessary.
23.6.10.1.1 Adjustable timer implementation

The adjustable timer consists of a programmable counter/accumulator and a correction
counter. The periods of both counters and their increment rates are freely configurable,
allowing very fine tuning of the timer.

Adjustable
Counter
timer
ENET_ATPER mod
To MAC
Correction
counter
ENET_ATCOR ENET_ATINC ENET_ATINC

[INC_CORR] [INC]
Figure 23-10. Adjustable timer implementation detail
The counter produces the current time. During each time-stamping clock cycle, a constant
value is added to the current time as programmed in ENETn_ATINC. The value depends
on the chosen time-stamping clock frequency. For example, if it operates at 125 MHz,
setting the increment to eight represents 8 ns.
The period, configured in ENETn_ATPER, defines the modulo when the counter wraps.
In a typical implementation, the period is set to 1 × 109 so that the counter wraps every
second, and hence all timestamps represent the absolute nanoseconds within the one
second period. When the period is reached, the counter wraps to start again respecting the
period modulo. This means it does not necessarily start from zero, but instead the counter
is loaded with the value (Current + Inc –(1 × 109)), assuming the period is set to 1 × 109.
The correction counter operates fully independently, and increments by one with each
time-stamping clock cycle. When it reaches the value configured in ENETn_ATCOR, it
restarts and instructs the timer once to increment by the correction value, instead of the
normal value.
The normal and correction increments are configured in ENETn_ATINC. To speed up
the timer, set the correction increment more than the normal increment value. To slow
down the timer, set the correction increment less than the normal increment value.
The correction counter only defines the distance of the corrective actions, not the amount.
This allows very fine corrections and low jitter (in the range of 1 ns) independent of the
chosen clock frequency.

23.6.10.2 Transmit timestamping

Only 1588 event frames need to be time-stamped on transmit. The client application (for
example, the MAC driver) should detect 1588 event frames and set TxBD[TS] together
with the frame.
If TxBD[TS] is set, the MAC records the timestamp for the frame in ENETn_ATSTMP.
ENETn_EIR[TS_AVAIL] is set to indicate that a new timestamp is available.
Software implements a handshaking procedure by setting TxBD[TS] when it transmits
the frame for which a timestamp is needed, and then waits for ENETn_EIR[TS_AVAIL]
to determine when the timestamp is available. The timestamp is then read from
ENETn_ATSTMP. This is done for all event frames. Other frames do not use TxBD[TS]
and, therefore, do not interfere with the timestamp capture.
23.6.10.3 Receive timestamping

When a frame is received, the MAC latches the value of the timer when the frame's start
of frame delimiter (SFD) field is detected, and provides the captured timestamp on
RxBD[1588 timestamp]. This is done for all received frames.
23.6.10.4 Time synchronization

The adjustable timer module is available to synchronize the local clock of a node to a
remote master. It implements a free running 32-bit counter, and also contains an
additional correction counter.
The correction counter increases or decreases the rate of the free running counter,
enabling very fine granular changes of the timer for synchronization, yet adding only
very low jitter when performing corrections.
The timer and all timestamp-related information should be configured to show the true
nanoseconds value of a second (in other words, the timer is configured to have a period
of one second). Hence, the values range from 0 to (1 × 109)–1. In this application, the
seconds counter is implemented in software using an interrupt function that is executed
when the nanoseconds counter wraps at 1 × 109.
23.6.10.5 Input Capture and Output Compare

The Input Capture Output Compare block can be used to provide precise hardware timing
for input and output events.

23.6.10.5.1 Input capture

The TCCRn capture registers latch the time value when the corresponding external event
occurs. An event can be a rising-, falling-, or either-edge of one of the 1588_TMRn
signals. An event will cause the corresponding TCSRn[TF] timer flag to be set, indicating
that an input capture has occurred. If the corresponding interrupt is enabled with the
TCSRn[TIE] field, an interrupt can be generated.
23.6.10.5.2 Output compare

The TCCRn compare registers are loaded with the time at which the corresponding event
should occur. When the ENET free-running counter value matches the output compare
reference value in the TCCRn register, the corresponding flag, TCSRn[TF], is set,
indicating that an output compare has occurred. The corresponding 1588_TMRn output
signal will be asserted according to TCSRn[TMODE].
NOTE
If TSCRn[TMODE] is set to 10X1b or 1010b then the timer
output pin toggle-on-overflow will occur only when PINPER,
PEREN, and EN bits of the ATCR register are one.
23.6.10.5.3 DMA requests

A DMA request can be enabled by setting TCSRn[TDRE]. The corresponding DMA
request is generated when the TCSRn[TF] timer flag is set. When the DMA has
completed, the corresponding TCSRn[TF] flag is cleared.
23.6.11 FIFO thresholds

The core FIFO thresholds are fully programmable to dynamically change the FIFO
operation.
For example, store and forward transfer can be enabled by a simple change in the FIFO
threshold registers.
The thresholds are defined in 64-bit words.
The receive and transmit FIFOs both have a depth of 512 words.

23.6.11.1 Receive FIFO

Four programmable thresholds are available, which can be set to any value to control the
core operation as follows.
Table 23-29. Receive FIFO thresholds definition
Register Description
ENETn_RSFL When the FIFO level reaches the ENETn_RSFL value, the MAC status signal is asserted to indicate that
data is available in the receive FIFO (cut-through operation). Once asserted, if the FIFO empties below the
[RX_SECTION_F
threshold set with ENETn_RAEM and if the end-of-frame is not yet stored in the FIFO, the status signal is
ULL]
deasserted again.
If a frame has a size smaller than the threshold (in other words, an end-of-frame is available for the
frame), the status is also asserted.
To enable store and forward on the receive path, clear ENETn_RSFL. The MAC status signal is asserted
only when a complete frame is stored in the receive FIFO.
When programming a non-zero value to ENETn_RSFL (cut-through operation) it should be greater than
ENETn_RAEM.
ENETn_RAEM When the FIFO level reaches the ENETn_RAEM value, and the end-of-frame has not been received, the
core receive read control stops the FIFO read (and subsequently stops transferring data to the MAC client
[RX_ALMOST_E
application).
MPTY]
It continues to deliver the frame, if again more data than the threshold or the end-of-frame is available in
the FIFO.
Set ENETn_RAEM to a minimum of six.
ENETn_RAFL When the FIFO level approaches the maximum and there is no more space remaining for at least
ENETn_RAFL number of words, the MAC control logic stops writing data in the FIFO and truncates the
[RX_ALMOST_F
receive frame to avoid FIFO overflow.
ULL]
The corresponding error status is set when the frame is delivered to the application.
Set ENETn_RAFL to a minimum of 4.
ENETn_RSEM When the FIFO level reaches the ENETn_RSEM value, an indication is sent to the MAC transmit logic,
which generates an XOFF pause frame. This indicates FIFO congestion to the remote Ethernet client.
[RX_SECTION_E
MPTY] When the FIFO level goes below the value programmed in ENETn_RSEM, an indication is sent to the
MAC transmit logic, which generates an XON pause frame. This indicates the FIFO congestion is cleared
to the remote Ethernet client.
Clearing ENETn_RSEM disables any pause frame generation.

FIFO read control
RSFL - Section full RAEM - Almost empty

(FIFO read control)
RSEM - Section empty RAFL - Almost full

(Pause frame (FIFO write protection)
generation)
MAC receive
Figure 23-11. Receive FIFO overview
23.6.11.2 Transmit FIFO

Four programmable thresholds are available which control the core operation as
described below.
Table 23-30. Transmit FIFO thresholds definition
ENETn_TAEM When the FIFO level reaches the ENETn_TAEM value and no end-of-frame is available for the frame, the
MAC transmit logic avoids a FIFO underflow by stopping FIFO reads and transmitting the Ethernet frame
[TX_ALMOST
with an MII error indication.
_EMPTY]
Set ENETn_TAEM to a minimum of 4.
ENETn_TAFL When the FIFO level approaches the maximum, so that there is no more space for at least ENETn_TAFL
number of words, the MAC deasserts its control signal to the application.
[TX_ALMOST
If the application does not react on this signal, the FIFO write control logic avoids FIFO overflow by
_FULL]
truncating the current frame and setting the error status. As a result, the frame is transmitted with an
GMII/MII error indication.
Set ENETn_TAFL to a minimum of 4. Larger values allow more latency for the application to react on the
MAC control signal deassertion, before the frame is truncated. A typical setting is 8, which offers 3–4 clock
cycles of latency to the application to react on the MAC control signal deassertion.
ENETn_TSEM When the FIFO level reaches the ENETn_TSEM value, a MAC status signal is deasserted to indicate that
the transmit FIFO is getting full. This gives the ENET module an indication to slow or stop its write
[TX_SECTION
transaction to avoid a buffer overflow. This is a pure indication function to the application. It has no effect
_EMPTY] within the MAC.
When ENETn_TSEM is 0, the signal is never deasserted.
ENETn_TFWR When the FIFO level reaches the ENETn_TFWR value and when STRFWD is cleared, the MAC transmit
control logic starts frame transmission before the end-of-frame is available in the FIFO (cut-through
operation).

Table 23-30. Transmit FIFO thresholds definition

If a complete frame has a size smaller than the ENETn_TFWR threshold, the MAC also transmits the
frame to the line.
To enable store and forward on the transmit path, set STRFWD. In this case, the MAC starts to transmit
data only when a complete frame is stored in the transmit FIFO.
FIFO write control
TSEM - Section empty TAFL - Almost full

(Core FIFO status) (FIFO write control)
TFWR - Section full TAEM - Almost empty

(MAC transmit start) (MAC read control)
MAC transmit
Figure 23-12. Transmit FIFO overview
23.6.12 Loopback options

The core implements external and internal loopback options, which are controlled by the
ENETn_RCR register fields found here.
The core implements external and internal loopback options, which are controlled by the
following ENETn_RCR register fields:
Table 23-31. Loopback options
Register field Description
LOOP Internal MII loopback. The MAC transmit is returned to the MAC receive. No data is transmitted to the
external interfaces.
In MII internal loopback, MII_TXCLK and MII_RXCLK must be provided with a clock signal (2.5 MHz for 10
Mbit/s, and 25 MHz for 100 Mbit/s))

Line interface
MAC interface
ENETn_RCR[LOOP],
Figure 23-13. Loopback options
23.6.13 Legacy buffer descriptors

To support the Ethernet controller on previous chips, legacy FEC buffer descriptors are
available. To enable legacy support, write 0 to ENETn_ECR[1588EN].
NOTE
• The legacy buffer descriptor tables show the byte order for
little-endian chips. DBSWP must be set to 1 after reset to
enable little-endian mode.
23.6.13.1 Legacy receive buffer descriptor

The following table shows the legacy FEC receive buffer descriptor. Table 23-35
contains the descriptions for each field.
Table 23-32. Legacy FEC receive buffer descriptor (RxBD)
Byte 1 Byte 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset + 0 Data length
Offset + 2 E RO1 W RO2 L — — M BC MC LG NO — CR OV TR
Offset + 4 Rx data buffer pointer — low halfword
Offset + 6 Rx data buffer pointer — high halfword

23.6.13.2 Legacy transmit buffer descriptor

The following table shows the legacy FEC transmit buffer descriptor. Table 23-37
Table 23-33. Legacy FEC transmit buffer descriptor (TxBD)
Byte 1 Byte 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset + 0 Data Length
Offset + 2 R TO1 W TO2 L TC ABC1 — — — — — — — — —
Offset + 4 Tx Data Buffer Pointer — low halfword
Offset + 6 Tx Data Buffer Pointer — high halfword
1. This field is not supported by the uDMA.
23.6.14 Enhanced buffer descriptors

This section provides a description of the enhanced operation of the driver/uDMA via the
buffer descriptors.
It is followed by a detailed description of the receive and transmit descriptor fields. To
enable the enhanced features, set ENETn_ECR[1588EN].
NOTE
The enhanced buffer descriptor tables show the byte order for
little-endian chips. DBSWP must be set to 1 after reset to
enable little-endian mode.
23.6.14.1 Enhanced receive buffer descriptor

The following table shows the enhanced uDMA receive buffer descriptor. Table 23-35
Table 23-34. Enhanced uDMA receive buffer descriptor (RxBD)
Byte 1 Byte 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset + 2 E RO1 W RO2 L — — M BC MC LG NO — CR OV TR
Offset + 4 Rx data buffer pointer – low halfword
Offset + 6 Rx data buffer pointer – high halfword

Table 23-34. Enhanced uDMA receive buffer descriptor (RxBD) (continued)

VLA FRA
Offset + 8 — — — — — — — — — — ICE PCR — IPV6
N G
Offset + A ME — — — — PE CE UC INT — — — — — — —
Offset + C Payload checksum
Offset + E Header length — — — Protocol type
Offset + 10 — — — — — — — — — — — — — — — —
Offset + 12 BDU — — — — — — — — — — — — — — —
Offset + 14 1588 timestamp – low halfword
Offset + 16 1588 timestamp – high halfword
Offset + 18 — — — — — — — — — — — — — — — —
Offset + 1A — — — — — — — — — — — — — — — —
Offset + 1C — — — — — — — — — — — — — — — —
Offset + 1E — — — — — — — — — — — — — — — —
Table 23-35. Receive buffer descriptor field definitions

Word Field Description
Offset + 0 15–0 Data length. Written by the MAC. Data length is the number of octets written by the MAC into
this BD's data buffer if L is cleared (the value is equal to EMRBR), or the length of the frame
Data
including CRC if L is set. It is written by the MAC once as the BD is closed.
Length
Offset + 2 15 Empty. Written by the MAC (= 0) and user (= 1).
E 0 The data buffer associated with this BD is filled with received data, or data reception has
aborted due to an error condition. The status and length fields have been updated as
required.
1 The data buffer associated with this BD is empty, or reception is currently in progress.
Offset + 2 14 Receive software ownership. This field is reserved for use by software. This read/write field is
not modified by hardware, nor does its value affect hardware.
RO1
Offset + 2 13 Wrap. Written by user.
W 0 The next buffer descriptor is found in the consecutive location.
1 The next buffer descriptor is found at the location defined in ENETn_RDSR.
Offset + 2 12 Receive software ownership. This field is reserved for use by software. This read/write field is
not modified by hardware, nor does its value affect hardware.
RO2
Offset + 2 11 Last in frame. Written by the uDMA.
L 0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
Offset + 2 10–9 Reserved, must be cleared.
Offset + 2 8 Miss. Written by the MAC. This field is set by the MAC for frames accepted in promiscuous
mode, but flagged as a miss by the internal address recognition. Therefore, while in
M
promiscuous mode, you can use the this field to quickly determine whether the frame was
destined to this station. This field is valid only if the L and PROM bits are set.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.

Table 23-35. Receive buffer descriptor field definitions (continued)

The information needed for this field comes from the promiscuous_miss(ff_rx_err_stat[26])
sideband signal.
Offset + 2 7 Set if the DA is broadcast (FFFF_FFFF_FFFF).
BC
Offset + 2 6 Set if the DA is multicast and not BC.
MC
Offset + 2 5 Receive frame length violation. Written by the MAC. A frame length greater than
RCR[MAX_FL] was recognized. This field is valid only if the L field is set. The receive data is
LG
not altered in any way unless the length exceeds TRUNC_FL bytes.
Offset + 2 4 Receive non-octet aligned frame. Written by the MAC. A frame that contained a number of
bits not divisible by 8 was received, and the CRC check that occurred at the preceding byte
NO
boundary generated an error or a PHY error occurred. This field is valid only if the L field is
set. If this field is set, the CR field is not set.
Offset + 2 3 Reserved, must be cleared.
Offset + 2 2 Receive CRC or frame error. Written by the MAC. This frame contains a PHY or CRC error
and is an integral number of octets in length. This field is valid only if the L field is set.
CR
Offset + 2 1 Overrun. Written by the MAC. A receive FIFO overrun occurred during frame reception. If this
field is set, the other status fields, M, LG, NO, and CR, lose their normal meaning and are
OV
zero. This field is valid only if the L field is set.
Offset + 2 0 Set if the receive frame is truncated (frame length >TRUNC_FL). If the TR field is set, the
frame must be discarded and the other error fields must be ignored because they may be
TR
incorrect.
Offset + 4 15–0 Receive data buffer pointer, low halfword
Data buffer
pointer low
0ffset + 6 15–0 Receive data buffer pointer, high halfword
Data buffer The receive buffer pointer, containing the address of the associated data buffer, must always
pointer be evenly divisible by 16. The buffer must reside in memory external to the MAC. The
high Ethernet controller never modifies this value.
Offset + 8 5 IP header checksum error. This is an accelerator option. This field is written by the uDMA. Set
when either a non-IP frame is received or the IP header checksum was invalid. An IP frame
ICE
with less than 3 bytes of payload is considered to be an invalid IP frame. This field is only
valid if the L field is set.
Offset + 8 4 Protocol checksum error. This is an accelerator option. This field is written by the uDMA. Set
when the checksum of the protocol is invalid or an unknown protocol is found and
PCR
checksumming could not be performed. This field is only valid if the L field is set.
Offset + 8 2 VLAN. This is an accelerator option. This field is written by the uDMA. It means that the frame
has a VLAN tag. This field is valid only if the L field is set.
VLAN
Offset + 8 1 IPV6 Frame. This field is written by the uDMA. This field indicates that the frame has an IPv6
frame type. If this field is not set it means that an IPv4 or other protocol frame was received.
IPV6
This field is valid only if the L field is set.
Offset + 8 0 IPv4 Fragment.This is an accelerator option.This field is written by the uDMA. It indicates that
the frame is an IPv4 fragment frame. This field is only valid when the L field is set.
FRAG

Table 23-35. Receive buffer descriptor field definitions (continued)

Offset + A 15 MAC error. This field is written by the uDMA. This field means that the frame stored in the
system memory was received with an error (typically, a receive FIFO overflow). This field is
ME
only valid when the L field is set.
Offset + A 14–11 Reserved, must be cleared.
Offset + A 10 PHY Error. This field is written by the uDMA. Set to "1"when the frame was received with an
Error character on the PHY interface. The frame is invalid. This field is valid only when the L
PE
field is set.
Offset + A 9 Collision. This field is written by the uDMA. Set when the frame was received with a collision
detected during reception. The frame is invalid and sent to the user application. This field is
CE
valid only when the L field is set.
Offset + A 8 Unicast. This field is written by the uDMA, and means that the frame is unicast. This field is
valid regardless of whether the L field is set.
UC
Offset + A 7 Generate RXB/RXF interrupt. This field is set by the user to indicate that the uDMA is to
generate an interrupt on the dma_int_rxb / dma_int_rxfevent.
INT
Offset + C 15–0 Internet payload checksum. This is an accelerator option. It is the one's complement sum of
the payload section of the IP frame. The sum is calculated over all data following the IP
Payload
header until the end of the IP payload. This field is valid only when the L field is set.
checksum
Offset + E 15–11 Header length. This is an accelerator option. This field is written by the uDMA. This field is the
sum of 32-bit words found within the IP and its following protocol headers. If an IP datagram
Header
with an unknown protocol is found, then the value is the length of the IP header. If no IP
length
frame or an erroneous IP header is found, the value is 0. The following values are minimum
values if no header options exist in the respective headers:
• ICMP/IP: 6 (5 IP header, 1 ICMP header)
• UDP/IP: 7 (5 IP header, 2 UDP header)
• TCP/IP: 10 (5 IP header, 5 TCP header)
This field is only valid if the L field is set.

Offset + E 10–8 Reserved, must be cleared.
Offset + E 7–0 Protocol type. This is an accelerator option. The 8-bit protocol field found within the IP header
of the frame. It is valid only when ICE is cleared. This field is valid only when the L field is set.
Protocol
type
Offset + 12 15 Last buffer descriptor update done. Indicates that the last BD data has been updated by
uDMA. This field is written by the user (=0) and uDMA (=1).
BDU
Offset + 14 15–0 This value is written by the uDMA. It is only valid if the L field is set.
Offset + 16 1588
timestamp
–
Offset + 1E

23.6.14.2 Enhanced transmit buffer descriptor

Table 23-36. Enhanced transmit buffer descriptor (TxBD)
Byte 1 Byte 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Offset + 2 R TO1 W TO2 L TC — — — — — — — — — —
Offset + 4 Tx Data Buffer Pointer – low halfword
Offset + 6 Tx Data Buffer Pointer – high halfword
Offset + 8 TXE — UE EE FE LCE OE TSE — — — — — — — —
Offset + A — INT TS PINS IINS — — — — — — — — — — —
Offset + C — — — — — — — — — — — — — — — —
Offset + E — — — — — — — — — — — — — — — —
Offset + 10 — — — — — — — — — — — — — — — —
Offset + 12 BDU — — — — — — — — — — — — — — —
Offset + 14 1588 timestamp – low halfword
Offset + 16 1588 timestamp – high halfword
Offset + 18 — — — — — — — — — — — — — — — —
Offset + 1A — — — — — — — — — — — — — — — —
Offset + 1C — — — — — — — — — — — — — — — —
Offset + 1E — — — — — — — — — — — — — — — —
Table 23-37. Enhanced transmit buffer descriptor field definitions

Offset + 0 15–0 Data length, written by user.
Data Length Data length is the number of octets the MAC should transmit from this BD's data
buffer. It is never modified by the MAC.
Offset + 2 15 Ready. Written by the MAC and you.
R 0 The data buffer associated with this BD is not ready for transmission. You
are free to manipulate this BD or its associated data buffer. The MAC
clears this field after the buffer has been transmitted or after an error
condition is encountered.
1 The data buffer, prepared for transmission by you, has not been
transmitted or currently transmits. You may write no fields of this BD after
this field is set.
Offset + 2 14 Transmit software ownership. This field is reserved for software use. This read/
write field is not modified by hardware and its value does not affect hardware.
TO1
Offset + 2 13 Wrap. Written by user.
W 0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ETDSR.

Table 23-37. Enhanced transmit buffer descriptor field definitions (continued)

Offset + 2 12 Transmit software ownership. This field is reserved for use by software. This
read/write field is not modified by hardware and its value does not affect
TO2
hardware.
Offset + 2 11 Last in frame. Written by user.
L 0 The buffer is not the last in the transmit frame
1 The buffer is the last in the transmit frame
Offset + 2 10 Transmit CRC. Written by user, and valid only when L is set.
TC 0 End transmission immediately after the last data byte
1 Transmit the CRC sequence after the last data byte
This field is valid only when the L field is set.
Offset + 2 9 Append bad CRC.
ABC Note: This field is not supported by the uDMA and is ignored.
Offset + 4 15–0 Tx data buffer pointer, low halfword
Data buffer
pointer low
Offset + 6 15–0 Tx data buffer pointer, high halfword. The buffer must reside in memory external
to the MAC. This value is never modified by the Ethernet controller.
Data buffer
pointer high
Offset + 8 15 Transmit error occurred. This field is written by the uDMA. This field indicates
that there was a transmit error of some sort reported with the frame. Effectively
TXE
this field is an OR of the other error fields including UE, EE, FE, LCE, OE, and
TSE. This field is valid only when the L field is set.
Offset + 8 13 Underflow error. This field is written by the uDMA. This field indicates that the
MAC reported an underflow error on transmit. This field is valid only when the L
UE
field is set.
Offset + 8 12 Excess Collision error. This field is written by the uDMA. This field indicates that
the MAC reported an excess collision error on transmit. This field is valid only
EE
when the L field is set.
Offset + 8 11 Frame with error. This field is written by the uDMA. This field indicates that the
MAC reported that the uDMA reported an error when providing the packet. This
FE
field is valid only when the L field is set.
Offset + 8 10 Late collision error. This field is written by the uDMA. This field indicates that the
MAC reported that there was a Late Collision on transmit. This field is valid only
LCE
when the L field is set.
Offset + 8 9 Overflow error. This field is written by the uDMA. This field indicates that the
MAC reported that there was a FIFO overflow condition on transmit. This field is
OE
only valid when the L field is set.
Offset + 8 8 Timestamp error. This field is written by the uDMA. This field indicates that the
MAC reported a different frame type then a timestamp frame. This field is valid
TSE
only when the L field is set.

Offset + A 15 Reserved, must be cleared.

Table 23-37. Enhanced transmit buffer descriptor field definitions (continued)

Offset + A 14 Generate interrupt flags. This field is written by the user. This field is valid
regardless of the L field and must be the same for all EBD for a given frame. The
INT
uDMA does not update this value.
Offset + A 13 Timestamp. This field is written by the user. This indicates that the uDMA is to
generate a timestamp frame to the MAC. This field is valid regardless of the L
TS
field and must be the same for all EBD for the given frame. The uDMA does not
update this value.
Offset + A 12 Insert protocol specific checksum. This field is written by the user. If set, the
MAC's IP accelerator calculates the protocol checksum and overwrites the
PINS
corresponding checksum field with the calculated value. The checksum field
must be cleared by the application generating the frame. The uDMA does not
update this value. This field is valid regardless of the L field and must be the
same for all EBD for a given frame.
Offset + A 11 Insert IP header checksum. This field is written by the user. If set, the MAC's IP
accelerator calculates the IP header checksum and overwrites the corresponding
IINS
header field with the calculated value. The checksum field must be cleared by
the application generating the frame. The uDMA does not update this value. This
field is valid regardless of the L field and must be the same for all EBD for a
given frame.
Offset + C 15–0 Reserved, must be cleared.
Offset + E 15–0 Reserved, must be cleared.
Offset + 12 15 Last buffer descriptor update done. Indicates that the last BD data has been
updated by uDMA. This field is written by the user (=0) and uDMA (=1).
BDU
Offset + 14 15–0 This value is written by the uDMA . It is valid only when the L field is set.
Offset + 16 1588 timestamp
Offset + 18–Offset + 1E 15–0 Reserved, must be cleared.
23.6.15 Client FIFO application interface

The FIFO interface is completely asynchronous from the Ethernet line, and the transmit
and receive interface can operate at a different clock rate.
All transfers to/from the user application are handled independently of the core operation,
and the core provides a simple interface to user applications based on a two-signal
handshake.

23.6.15.1 Data structure description

The data structure defined in the following tables for the FIFO interface must be
respected to ensure proper data transmission on the Ethernet line. Byte 0 is sent to and
received from the line first.
Table 23-38. FIFO interface data structure
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
Word 0 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Word 1 Byte 15 Byte 14 Byte 13 Byte 12 Byte 11 Byte 10 Byte 9 Byte 8
... ...
The size of a frame on the FIFO interface may not be a modulo of 64-bit.
The user application may not care about the Ethernet frame formats in full detail. It needs
to provide and receive an Ethernet frame with the following structure:
• Ethernet MAC destination address
• Ethernet MAC source address
• Optional 802.1q VLAN tag (VLAN type and info field)
• Ethernet length/type field
• Payload
Frames on the FIFO interface do not contain preamble and SFD fields, which are inserted
and discarded by the MAC on transmit and receive, respectively.
• On receive, CRC and frame padding can be stripped or passed through transparently.
• On transmit, padding and CRC can be provided by the user application, or appended
automatically by the MAC independently for each frame. No size restrictions apply.
Note
On transmit, if ENETn_TCR[ADDINS] is set, bytes 6–11 of
each frame can be set to any value, since the MAC overwrites
the bytes with the MAC address programmed in the
ENETn_PAUR and ENETn_PALR registers.
Table 23-39. FIFO interface frame format
Byte number Field
0–5 Destination MAC address

Table 23-39. FIFO interface frame format (continued)

Byte number Field
6–11 Source MAC address
12–13 Length/type field
14–N Payload data
VLAN-tagged frames are supported on both transmit and receive, and implement
additional information (VLAN type and info).
Table 23-40. FIFO interface VLAN frame format
Byte number Field
0–5 Destination MAC address
6–11 Source MAC address
12–15 VLAN tag and info
16–17 Length/type field
18–N Payload data
Note
The standard defines that the LSB of the MAC address is sent/
received first, while for all the other header fields — in other
words, length/type, VLAN tag, VLAN info, and pause quanta
— the MSB is sent/received first.
23.6.15.2 Data structure examples

Bits 0–7
transmitted
63 55 47 39 31 23 15 7 first
Word 0 Source address Destination address
1 Payload Length Length Source address (cont.)

(low) (high)
2 Payload (cont.)
3 Payload (cont.)
N Unused (0x00) Payload Payload Payload

(last) (last-1) (last-2)
Figure 23-14. Normal Ethernet frame 64-bit mapping example

Bits 0–7
transmitted
63 55 47 39 31 23 15 7 first
Word 0 Source address Destination address
1 VLAN info VLAN info VLAN tag VLAN tag Source address (cont.)
(low) (high) (0x00) (0x81)
2 Payload Length Length

(low) (high)
3 Payload (cont.)
N Unused (0x00) Payload Payload Payload

(last) (last-1) (last-2)
Figure 23-15. VLAN-tagged frame 64-bit mapping example
If CRC forwarding is enabled (CRCFWD = 0), the last four valid octets of the frame
contain the FCS field. The non-significant bytes of the last word can have any value.
23.6.15.3 Frame status

A MAC layer status word and an accelerator status word is available in the receive buffer
descriptor.
See Enhanced buffer descriptors for details.
The status is available with each frame with the last data of the frame.
If the frame status contains a MAC layer error (for example, CRC or length error),
RxBD[ME] is also set with the last data of the frame.
23.6.16 FIFO protection

The following sections describe the FIFO protection mechanisms.
23.6.16.1 Transmit FIFO underflow

During a frame transfer, when the transmit FIFO reaches the almost empty threshold with
no end-of-frame indication stored in the FIFO, the MAC logic:
• Stops reading data from the FIFO

• Asserts the MII error signal (MII_TXER) (1 in Figure 23-16) to indicate that the
fragment already transferred is not valid
• Deasserts the MII transmit enable signal (MII_TXEN) to terminate the frame transfer
(2)
After an underflow, when the application completes the frame transfer (3), the MAC
transmit logic discards any new data available in the FIFO until the end of packet is
reached (4) and sets the enhanced TxBD[UE] field.
The MAC starts to transfer data on the MII interface when the application sends a new
frame with a start of frame indication (5).
4
3
Transmit FIFO
TX CLK
TX ready
FIFO data
Internal signals
section empty
Write enable
Start of packet
End of packet
TX data
TX error status
MII Transmit
External signals
MII_TXCLK
MII_TXEN
MII_TXD[3:0] 55 55
MII_TXER
2 5
1
Figure 23-16. Transmit FIFO underflow protection
23.6.16.2 Transmit FIFO overflow

On the transmit path, when the FIFO reaches the programmable almost full threshold, the
internal MAC ready signal is deasserted. The application should stop sending new data.
However, if the application keeps sending data, the transmit FIFO overflows, corrupting
contents that were previously stored. The core logic sets the enhanced TxBD[OE] field
for the next frame transmitted to indicate this overflow occurence.

Note
Overflow is a fatal error and must be addressed by resetting the
core or clearing ENETn_ECR[ETHER_EN], to clear the FIFOs
and prepare for normal operation again.
23.6.16.3 Receive FIFO overflow

During a frame reception, if the client application is not able to receive data (1), the MAC
receive control truncates the incoming frame when the FIFO reaches the programmable
almost-full threshold to avoid an overflow.
The frame is subsequently received on the FIFO interface with an error indication
(enhanced RxBD[ME] field set together with receive end-of-packet) (2) with the
truncation error status field set (3).
MII Receive
External signals
MII_RXCLK
MII_RXDV
MII_RXD[3:0]
MII_RXER
Receive FIFO
RX CLK
RX ready
Frame available
Internal signals
Data valid
Start of packet
End of packet
RX data
RX error
RX error status
2 3
1
Figure 23-17. Receive FIFO overflow protection
23.6.17 PHY management interface

The MDIO interface is a two-wire management interface. The MDIO management
interface implements a standardized method to access the PHY device management
registers.

The core implements a master MDIO interface, which can be connected to up to 32 PHY
devices.
23.6.17.1 MDIO clause 22 frame format

The core MDIO master controller communicates with the slave (PHY device) using
frames that are defined in the following table.
A complete frame has a length of 64 bits made up of an optional 32-bit preamble, 14-bit
command, 2-bit bus direction change, and 16-bit data. Each bit is transferred on the rising
edge of the MDIO clock (MDC signal). The MDIO data signal is tri-stated between
frames.
The core PHY management interface supports the standard MDIO specification (IEEE
802.3 Clause 22).
Table 23-41. MDIO clause 22 frame structure
ST OP PHYADR REGADR TA DATA
Table 23-42. MDIO frame field descriptions

Field Description
ST Start indication field, programmed with ENETn_MMFR[ST] and equal to 01 for Standard MDIO
(Clause 22).
(2 bits)
OP Opcode defines type of operation. Programmed with ENETn_MMFR[OP].
(2 bits) 01 Write operation
10 Read operation
PHYADR Five-bit PHY device address, programmed with ENETn_MMFR[PA]. Up to 32 devices can be
addressed.
(5 bits)
REGADR Five-bit register address, programmed with ENETn_MMFR[RA]. Each PHY can implement up to 32
registers.
(5 bits)
TA Turnaround time, programmed with ENETn_MMFR[TA]. Two bit-times are reserved for read
operations to switch the data bus from write to read. The PHY device presents its register contents
(2 bits)
in the data phase and drives the bus from the second bit of the turnaround phase.
Data Data, set by ENETn_MMFR[DATA]. Written to or read from the PHY
(16 bits)

23.6.17.2 MDIO clause 45 frame format

The extended MDIO frame structure defined in IEEE 802.3 Clause 45 introduces indirect
addressing. First, a write transaction to an address register is done, followed by a write or
read transaction which will put the 16-bit data in the register or retrieve the register
contents respectively. A preamble of 32 bits of logical ones is sent prior to every
transaction. The MDIO data signal is tri-stated between frames.
The extended MDIO defines four transactions, which are determined by the two-bit
opcode field.
Table 23-43. MDIO clause 45 frame structure
ST OP PRTAD DEVAD TA ADDR/DATA
All bits are transmitted from left to right (Preamble bits first) and all fields have their
Most-Significant bit sent first (leftmost in above table). The complete frame has a length
of 64 bits (32-bit preamble, 14-bit command, 2-bit bus direction change, 16-bit data).
Each bit is transferred with the rising edge of the MDIO clock (MDC).
The fields and transactions are summarized in the following tables.
Table 23-44. MDIO clause 45 frame field descriptions
Field Description
ST Start indication. Indicates the end of the preamble and start of the frame. This value is 00 for
extended MDIO (Clause 45) frames.
OP Opcode defines if a read or write operation is performed and is programmed with
ENETn_MMFR[OP]. See Table 23-45 for more information.
00 Address write
01 Write operation
10 Read inc. operation
11 Read operation
PRTAD The port address specifies a MDIO port. Each Port can have up to 32 devices which each can have
a separate set of registers.
DEVAD Device address. Up to 32 devices can be addressed (within a port).
TA Turnaround time, programmed with ENETn_MMFR[TA]. Two bit-times are reserved for read
operations to switch the data bus from write to read. The PHY device presents its register contents
in the data phase and drives the bus from the second bit of the turnaround phase.
ADDR/DATA 16-bit address (for address write) or data, set by ENETn_MMFR[DATA], written to or read from the
PHY.

Table 23-45. MDIO Clause 45 Transactions

Transaction Type Description
Address A write transaction to the internal address register of the device/port. The data section of the frame
contains the value to be stored in the device's internal address "pointer" register for further
transactions.
Write Data write to a register. The 16 bit data will be written to the register identified by the device-internal
address.
Read Data is read from the register identified by the device-internal address.
Read inc. Read with address postincrement. The register identified by the device-internal address is read.
After this, the device-internal address is incremented. If the address register is all '1' (0xFFFF) no
increment is done (i.e. increment does not wrap around).
23.6.17.3 MDIO clock generation

The MDC clock is generated from the internal bus clock (i.e., IPS bus clock) divided by
the value programmed in ENETn_MSCR[MII_SPEED].
23.6.17.4 MDIO operation

To perform an MDIO access, set the MDIO command register (ENETn_MMFR)
according to the description provided in MII Management Frame Register
(ENETn_MMFR).
To check when the programmed access completes, read the ENETn_EIR[MII] field.
Start
Load ENETn_MMFR register
Read ENETn_EIR
N
MII = 1?
Figure 23-18. MDIO access overview
23.6.18 Ethernet interfaces

The following Ethernet interfaces are implemented:

• Fast Ethernet MII (Media Independent Interface)
• RMII 10/100 using interface converters/gaskets
• RGMII 10/100/1000 by way of interface converters/gaskets
The following table shows how to configure ENET registers to select each interface.
Mode ECR[SPEED] RCR[RMII_10T] RCR[RMII_MODE] RCR[RGMII_EN]
MII - 10 Mbit/s 0 — 0 0
MII - 100 Mbit/s 0 — 0 0
RMII - 10 Mbit/s 0 1 1 0
RMII - 100 Mbit/s 0 0 1 0
RGMII - 10 Mbit/s 0 1 0 1
RGMII - 100 Mbit/s 0 0 0 1
RGMII - 1000 Mbit/s 1 — 0 1
23.6.18.1 RMII interface

In RMII receive mode, for normal reception following assertion of CRS_DV, RXD[1:0]
is 00 until the receiver determines that the receive event has a proper start-of-stream
delimiter (SSD).
The preamble appears (RXD[1:0]=01) and the MACs begin capturing data following
detection of SFD.
RMII_REF_CLK
RMII_CRS_DV
RMII_RXD1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x x x 0
RMII_RXD0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 x x x x x x 0
/J/ /K / Pream bl e SFD D ata
Figure 23-19. RMII receive operation
If a false carrier is detected (bad SSD), then RXD[1:0] is 10 until the end of the receive
event. This is a unique pattern since a false carrier can only occur at the beginning of a
packet where the preamble is decoded (RXD[1:0] = 01).

RMII_REF_CLK
RMII_CRS_DV
RMII_RXD1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
RMII_RXD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
False carrier detected
Figure 23-20. RMII receive operation with false carrier
In RMII transmit mode, TXD[1:0] provides valid data for each REF_CLK period while
TXEN is asserted.
RMII_REF_CLK
RMII_TXEN
RMII_TXD1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x x x 0
RMII_TXD0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x 0
Pream bl e SFD D ata
Figure 23-21. RMII transmit operation
23.6.18.2 RGMII interface

In RGMII modes, the data and control information is multiplexed by taking advantage of
both edges of the reference clocks.
The data signals contain the lower four data bits on the rising edge and the upper four bits
on the falling edge. The control signals are multiplexed into a single clock cycle using the
same technique.
RGMII_TXC
(at transmitter)
RGMII_TXD[3:0] TXD[3:0] TXD[7:4]
RGMII_TX_CTL TXEN *
* TXERR XOR TXEN
RGMII_TXC
(at receiver)
Figure 23-22. RGMII transmit operation

RGMII_RXC
(at transmitter)
RGMII_RXD[3:0] RXD[3:0] RXD[7:4]
RGMII_RX_CTL RXDV *
* RXERR XOR RXDV
RGMII_RXC
(at receiver)
Figure 23-23. RGMII receive operation
23.6.18.3 MII Interface — transmit

On transmit, all data transfers are synchronous to MII_TXCLK rising edge. The MII data
enable signal MII_TXEN is asserted to indicate the start of a new frame, and remains
asserted until the last byte of the frame is present on the MII_TXD[3:0] bus.
Between frames, MII_TXEN remains deasserted.
CRC-32
Preamble SFD
MII_TXCLK
MII_TXD[3:0] 5 04 05 06 07 08 09 0A 0F 10 11 12 13 14 15 16 17 18 19 1A 1C 1E 1F 20 21 22 23 24 25 26 27 28 29 2B 2E 2F 30 31 32 33 34 35 36 37 38 39 3B 3F 40 99 80 28
MII_TXEN
MII_TXER
Figure 23-24. MII transmit operation
If a frame is received on the FIFO interface with an error (for example, RxBD[ME] set)
the frame is subsequently transmitted with the MII_TXER error signal for one clock
cycle at any time during the packet transfer.

CRC-32
Preamble SFD
MII_TXCLK
MII_TXD[3:0] 5
MII_TXEN
MII_TXER
Figure 23-25. MII transmit operation — errored frame
23.6.18.3.1 Transmit with collision — half-duplex

When a collision is detected during a frame transmission (MII_COL asserted), the MAC
stops the current transmission, sends a 32-bit jam pattern, and re-transmits the current
frame.
(See Collision detection in half-duplex mode for details)
Jam
MII_TXCLK
MII_TXD[3:0] 5
MII_TXEN
MII_TXER
MII_CRS
MII_COL
Figure 23-26. MII transmit operation — transmission with collision
23.6.18.4 MII interface — receive

On receive, all signals are sampled on the MII_RXCLK rising edge. The MII data enable
signal, MII_RXDV, is asserted by the PHY to indicate the start of a new frame and
remains asserted until the last byte of the frame is present on MII_RXD[3:0] bus.
Between frames, MII_RXDV remains deasserted.

CRC-32
Preamble SFD
MII_RXCLK
MII_RXD[3:0] 5
MII_RXDV
MII_RXER
Figure 23-27. MII receive operation
If the PHY detects an error on the frame received from the line, the PHY asserts the MII
error signal, MII_RXER, for at least one clock cycle at any time during the packet
transfer.
CRC-32
Preamble SFD
MII_RXCLK
MII_RXD[3:0] 5
MII_RXDV
MII_RXER
Figure 23-28. MII receive operation — errored frame
A frame received on the MII interface with a PHY error indication is subsequently
transferred on the FIFO interface with RxBD[ME] set.

Chapter 24
Enhanced Periodic Interrupt Timer (EPIT)
24.1 Overview
EPIT is a 32-bit set-and-forget timer that is capable of providing precise interrupts at
regular intervals with minimal processor intervention. EPIT begins counting after it is
enabled by software.
The following figure shows the EPIT block diagram.
Clock off
ipg_clk 12 bit Prescaler

1 ... 4096
ipg_clk_32k
ipg_clk_highfreq
Prescaled
Peripheral Bus Clock
Counter Reload
32
Counter Register ITIF EPITn_OUT
32 bit
CMP OM
Load Register
32 bit
ITIE interrupt
Compare Register
32 bit
Figure 24-1. EPIT block diagram

External signals
24.1.1 EPIT features

EPIT has the following key features:
• 32-bit down counter with clock source selection
• 12-bit prescaler for division of input clock frequency
• Counter value that can be programmed on the fly
• Can be programmed to be active during low-power and debug modes
• Interrupt generation when counter reaches the compare value
24.1.2 EPIT modes and operations

EPIT supports the following modes: set-and-forget and free running. See the following
sections for more information.
• Operating in set-and-forget mode
• Operating in free-running mode
See Operations for a description of the operations that EPIT supports.
24.2 External signals

The following table describes EPIT's I/O signals.
Table 24-1. EPIT External Signals
EPIT1_OUT Output 1 pin at chip boundary for EIM_D19 ALT6 O
indicating the occurrence of an GPIO_0 ALF4
output compare event through a
specified transition. GPIO_7 ALT2
EPIT2_OUT Output 2 pin at chip boundary for EIM_D20 ALT6 O
indicating the occurrence of an GPIO_8 ALT2
output compare event through a
specified transition.
24.3 Clocks
The table found here describes the clock sources for EPIT.
Please see Clock Controller Module (CCM) for clock setting, configuration and gating
information.

Chapter 24 Enhanced Periodic Interrupt Timer (EPIT)
Table 24-2. EPIT Clocks

ipg_clk_32k ckil_sync_clk_root Low-frequency reference clock (32 kHz)
ipg_clk_highfreq perclk_clk_root High-frequency reference clock
The clock that feeds the prescaler can be selected from among the following sources:
• High-frequency reference clock (ipg_clk_highfreq)
This clock is provided by the Clock Control Module (CCM). This clock remains on
during low-power mode when the peripheral clock is turned off, allowing EPIT to
use this clock in low-power mode. In normal mode, the CCM synchronizes this clock
to ahb_clk; in low-power mode, CCM switches to an unsynchronized version.
• Low-frequency reference clock (ipg_clk_32k)
This 32 kHz reference clock is provided by the CCM. This clock remains on in low-
power mode when the peripheral clock is turned off, so EPIT can use this clock
during low-power mode. In normal mode, the CCM synchronizes this clock to
ahb_clk; in low-power mode, CCM switches to an unsynchronized version. This
clock is derived from the external 32 kHz crystal.
• Peripheral clock (ipg_clk)
This is the peripheral clock (PER Clock) which is provided (and optionally gated) by
the CCM. This clock is typically used in normal operations. In low-power modes, if
the EPIT is programmed to be disabled (via STOPEN or WAITEN), then the
peripheral clock can be switched off.
The clock input source is determined by the CLKSRC field in the control register. The
clock input to the prescaler can also be disabled by setting CLKSRC to 0b00. This field
value should only be changed after first disabling the EPIT by clearing the EN bit in
the EPIT_EPITCR. For other programming requirements that apply while changing
clock source, refer section Change of Clock Source.
The PRESCALER field in the control register is used to select the divide ratio of the
input clock that drives the main counter. The prescaler can divide the input clock by a
value between 1 and 4096. A change in the value of the PRESCALER field is
immediately reflected on its output clock frequency. The following figure shows the
timing for a change in the prescaler value.

Clk
Prescaler Value 100 010
Prescaled Clk
Figure 24-2. Prescaler Value Change Diagram

24.4.1 Operating modes

EPIT can operate in either set-and-forget or free-running mode. Use EPIT_CR[RLD] to
select the desired mode.
24.4.1.1 Operating in set-and-forget mode

To select this mode of operation, set the RLD bit in the control register (EPIT_CR).
In this mode, the counter obtains its data from the load register (EPIT_LR); it cannot be
written to directly from the block data bus. Whenever the counter reaches zero, the value
in EPIT_LR is loaded into the counter. This value is then decremented to zero.
To directly initialize the counter instead of waiting for the count to reach zero, set the
EPIT counter overwrite enable bit (EPIT_CR[IOVW]) and write to EPIT_LR with the
required initialization value.
24.4.1.2 Operating in free-running mode

To select this mode of operation, clear the RLD bit.
In this mode, the counter rolls over from 0000 0000h to FFFF FFFFh without reloading
from the modulus register. After rolling over, the counter continues counting down.

To directly initalize the counter, set the EPIT counter overwrite enable bit
(EPIT_EPITCL[IOVW]) and write to EPIT_EPITLR with the required initialization
value.
24.4.2 Operations
EPIT has a single 32-bit down counter, which starts counting when the block is enabled
by software.
The start value of the counter is loaded from the EPIT load register, which can be written
to at any time by the processor. The value in the compare register determines the time
that the interrupt occurs.
When EPIT is disabled (EN = 0), both the main counter and the prescaler counter freeze
their count at their current count values. When EPIT is re-enabled (EN = 1), the ENMOD
bit, which is a RW bit, decides the counter value:
• If ENMOD is set, the main counter is loaded with the load value (If RLD = 1)/
FFFF FFFFh (If RLD = 0) and the prescaler counter is reset (000h).
• If ENMOD is cleared, both main counter and prescaler counter restart counting from
their frozen values.
If EPIT is programmed to be disabled in a low-power mode (STOP/WAIT), both the
main counter and the prescaler counter freeze at their current count values when EPIT
enters low-power mode. When EPIT exits the low-power mode, both the main counter
and the prescaler counter start counting from their frozen values regardless of the
ENMOD bit.
A hardware reset resets all EPIT registers to their respective reset values. There is a
software reset which has the same effect on all registers except for the EN, ENMOD,
STOPEN and WAITEN bits in the control register. The state of these bits are not affected
by software reset. A software reset can be asserted even when the EPIT is disabled.
24.4.3 Compare Event

When the programmed value of EPIT_EPITCMPR matches the value in EPIT_EPITCNR
a compare status flag is set, and an interrupt is generated if the OCIEN bit is set in the
control register.

The compare output pin is set, cleared, toggled, or not affected at all depending on the
setting of the output mode (OM) bits in the control register. If an interrupt is required at
rollover (when the counter value reaches 0x0000_0000 and the new value is loaded) then
the compare register value should be set equal to the load register value in set-and-forget
mode, or equal to 0xFFFF_FFFF in free-running mode.
The following figure shows the timing for a compare event and interrupt.
Clk
Counter 0 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0
Compare Value 2
Load Value 4
Output Mode 001 010 011
Output Signal
toggle clear set
Interrupt
Figure 24-3. Compare Event and Interrupt Timing Diagram
EPIT will generate a compare event in the next count if the EPITx_CNR from the
previous count equals the new EPITx_CMPR configured before re-enabling the EPIT in
the next count. Even in case a new start counter value was updated in EPITx_LR before
re-enabling the EPIT for the next round. To avoid this, configure the EPITx_CMPR to
previous EPITx_CNR+1. Or, in set and forget mode, configure EPITx_LR with
IOVW=1, before disabling EPIT. Also can do an extra disable/enable iteration to clear
OCIF and update EPITx_CNR.
24.4.3.1 Counter Value Overwrite

The EPIT counter value can be overwritten to acquire a desired value at any point of
time. The procedure for this is to set the IOVW bit in the control register and then write
the desired value into the load register.
This results in the load register acquiring that value and also the counter being
overwritten with it. If the EPIT is running the counter resumes counting from the
overwritten value.

24.4.3.2 Low-Power Mode Behavior

The EPIT timer's behavior in low-power modes depends on which clock source is being
used.
If the selected clock source is available and the corresponding low-power enable bit is
set, then the EPIT continues to function in the low-power mode. If the EPIT is
programmed to be disabled in a low-power mode (STOP/WAIT), then main counter and
the prescaler counter freeze at the current count values when the EPIT enters low-power
mode. When the EPIT exits the low-power mode, both main counter and prescaler
counter start counting from their frozen values irrespective of the ENMOD bit.
24.4.3.3 Debug Mode Behavior

In debug mode, the user has the option to run or halt the EPIT timers. If the DBGEN bit
is reset in the EPIT Control Register, the timer is halted.
When debug mode is exited, the timer operation reverts to what it was prior to entering
debug mode.
24.5 Initialization/ Application Information
24.5.1 Change of Clock Source

The CLKSRC field in EPIT_EPITCR determines the clock source. This field value
should be changed only after disabling the EPIT (EN = 0).
Below is the software sequence which must be followed while changing clock source.
1. Disable the EPIT - set EN=0 in EPIT_EPITCR.
2. Disable EPIT ouput - program OM=00 in the EPIT_EPITCR.
3. Disable EPIT interrupts.
4. Program CLKSRC to desired clock source in EPIT_EPITCR.
5. Clear the EPIT status register (EPIT_EPITSR), that is, write "1" to clear (w1c).
6. Set ENMOD= 1 in the EPIT_EPITCR, to bring the EPIT Counter to defined state
(EPIT_EPITLR value or 0xFFFF_FFFF).
7. Enable EPIT - set (EN=1) in the EPIT_EPITCR
8. Enable the EPIT interrupts.

EPIT Memory Map/Register Definition
24.6 EPIT Memory Map/Register Definition
The EPIT includes five user-accessible 32-bit registers. The following table summarizes
these registers and their addresses.
Peripheral bus write access to the EPIT control register (EPITCR) and the EPIT load
register (EPITLR) results in one cycle of wait state, while other valid peripheral bus
accesses are with 0 wait state.
EPIT memory map

Absolute
Width Section/
(in bits) page
(hex)
20D_0000 Control register (EPIT1_CR) 32 R/W 0000_0000h 24.6.1/1048
20D_0004 Status register (EPIT1_SR) 32 R/W 0000_0000h 24.6.2/1051
20D_0008 Load register (EPIT1_LR) 32 R/W FFFF_FFFFh 24.6.3/1051
20D_000C Compare register (EPIT1_CMPR) 32 R/W 0000_0000h 24.6.4/1052
20D_0010 Counter register (EPIT1_CNR) 32 R FFFF_FFFFh 24.6.5/1052
20D_4000 Control register (EPIT2_CR) 32 R/W 0000_0000h 24.6.1/1048
20D_4004 Status register (EPIT2_SR) 32 R/W 0000_0000h 24.6.2/1051
20D_4008 Load register (EPIT2_LR) 32 R/W FFFF_FFFFh 24.6.3/1051
20D_400C Compare register (EPIT2_CMPR) 32 R/W 0000_0000h 24.6.4/1052
20D_4010 Counter register (EPIT2_CNR) 32 R FFFF_FFFFh 24.6.5/1052
24.6.1 Control register (EPITx_CR)

The EPIT control register (EPIT_CR) is used to configure the operating settings of the
EPIT. It contains the clock division prescaler value and also the interrupt enable bit.
Additionally, it contains other control bits which are described below.
Peripheral Bus Write access to EPIT Control Register (EPIT_CR) results in one cycle of
the wait state, while other valid peripheral bus accesses are with 0 wait state.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
STOPEN
WAITEN
DBGEN
IOVW
CLKSRC OM SWR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENMOD
OCIEN
PRESCALAR RLD EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPITx_CR field descriptions

Field Description
Reserved
25–24 Select clock source
CLKSRC
These bits determine which clock input is to be selected for running the counter. This field value should
only be changed when the EPIT is disabled by clearing the EN bit in this register. For other programming
requirements while changing clock source, refer to Change of Clock Source.
00 Clock is off
01 Peripheral clock
10 High-frequency reference clock
11 Low-frequency reference clock
23–22 EPIT output mode.This bit field determines the mode of EPIT output on the output pin.
OM
00 EPIT output is disconnected from pad
01 Toggle output pin
10 Clear output pin
11 Set output pin
21 EPIT stop mode enable. This read/write control bit enables the operation of the EPIT during stop mode.
STOPEN This bit is reset by a hardware reset and unaffected by software reset.
0 EPIT is disabled in stop mode

1 EPIT is enabled in stop mode
Reserved
19 This read/write control bit enables the operation of the EPIT during wait mode. This bit is reset by a
WAITEN hardware reset. A software reset does not affect this bit.
0 EPIT is disabled in wait mode

1 EPIT is enabled in wait mode
18 This bit is used to keep the EPIT functional in debug mode. When this bit is cleared, the input clock is
DBGEN gated off in debug mode.This bit is reset by hardware reset. A software reset does not affect this bit.
0 Inactive in debug mode

1 Active in debug mode
17 EPIT counter overwrite enable. This bit controls the counter data when the modulus register is written.
IOVW When this bit is set, all writes to the load register overwrites the counter contents and the counter starts
subsequently counting down from the programmed value.
0 Write to load register does not result in counter value being overwritten.
1 Write to load register results in immediate overwriting of counter value.

EPITx_CR field descriptions (continued)

Field Description
16 Software reset. The EPIT is reset when this bit is set to 1. It is a self clearing bit. This bit is set when the
SWR block is in reset state and is cleared when the reset procedure is over. Setting this bit resets all the
registers to their reset values, except for the EN, ENMOD, STOPEN, WAITEN and DBGEN bits in this
control register
0 EPIT is out of reset

1 EPIT is undergoing reset
15–4 Counter clock prescaler value. This bit field determines the prescaler value by which the clock is divided
PRESCALAR before it goes to the counter
0x000 Divide by 1
0x001 Divide by 2...
0xFFF Divide by 4096
3 Counter reload control.
RLD
This bit is cleared by hardware reset. It decides the counter functionality, whether to run in free-running
mode or set-and-forget mode.
0 When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode)
1 When the counter reaches zero it reloads from the modulus register (set-and-forget mode)
2 Output compare interrupt enable.
OCIEN
This bit enables the generation of interrupt on occurrence of compare event.
0 Compare interrupt disabled

1 Compare interrupt enabled
1 EPIT enable mode.
ENMOD
When EPIT is disabled (EN=0), both main counter and prescaler counter freeze their count at current
count values. ENMOD bit is a r/w bit that determines the counter value when the EPIT is enabled again by
setting EN bit. If ENMOD bit is set, then main counter is loaded with the load value (If RLD=1)/
0xFFFF_FFFF (If RLD=0) and prescaler counter is reset, when EPIT is enabled (EN=1). If ENMOD is
programmed to 0 then both main counter and prescaler counter restart counting from their frozen values
when EPIT is enabled (EN=1). If EPIT is programmed to be disabled in a low-power mode (STOP/WAIT/
DEBUG), then both the main counter and the prescaler counter freeze at their current count values when
EPIT enters low-power mode. When EPIT exits the low-power mode, both main counter and prescaler
counter start counting from their frozen values irrespective of the ENMOD bit. This bit is reset by a
hardware reset. A software reset does not affect this bit.
0 Counter starts counting from the value it had when it was disabled.
1 Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0)
0 This bit enables the EPIT. EPIT counter and prescaler value when EPIT is enabled (EN = 1), is dependent
EN upon ENMOD and RLD bit as described for ENMOD bit. It is recommended that all registers be properly
programmed before setting this bit. This bit is reset by a hardware reset. A software reset does not affect
this bit.
0 EPIT is disabled
1 EPIT is enabled

24.6.2 Status register (EPITx_SR)
The EPIT status register (EPIT_SR) has a single status bit for the output compare event.
The bit is a write 1 to clear bit.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 OCIF
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPITx_SR field descriptions

Field Description
Reserved
0 Output compare interrupt flag. This bit is the interrupt flag that is set when the content of counter equals
OCIF the content of the compare register (EPIT_CMPR). The bit is a write 1 to clear bit.
0 Compare event has not occurred

1 Compare event occurred
24.6.3 Load register (EPITx_LR)
The EPIT load register (EPIT_LR) contains the value that is to be loaded into the counter
when EPIT counter reaches zero if the RLD bit in EPIT_CR is set. If the IOVW bit in the
EPIT_CR is set then a write to this register overwrites the value of the EPIT counter
register in addition to updating this registers value. This overwrite feature is active even
if the RLD bit is not set.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
LOAD
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

EPITx_LR field descriptions

Field Description
LOAD Load value. Value that is loaded into the counter at the start of each count cycle.
24.6.4 Compare register (EPITx_CMPR)
The EPIT compare register (EPIT_CMPR) holds the value that determines when a
compare event is generated.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
COMPARE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPITx_CMPR field descriptions

Field Description
COMPARE Compare Value. When the counter value equals this bit field value a compare event is generated.
24.6.5 Counter register (EPITx_CNR)
The EPIT counter register (EPIT_CNR) contains the current count value and can be read
at any time without disturbing the counter. This is a read-only register and any attempt to
write into it generates a transfer error. But if the IOVW bit in EPIT_CR is set, the value
of this register can be overwritten with a write to EPIT_LR. This change is reflected
when this register is subsequently read.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPITx_CNR field descriptions

Field Description
COUNT Counter value. This contains the current value of the counter.

Chapter 25
Enhanced Serial Audio Interface (ESAI)
25.1 Overview
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial
Sony/Phillips Digital Interface (SPDIF) transceivers, and other DSPs.
The ESAI consists of independent transmitter and receiver sections, each section with its
own clock generator. It is a superset of the 56300 Family ESSI peripheral and of the
56000 Family SAI peripheral.
All serial transfers in the module are synchronized to a clock. Additional synchronization
signals are used to delineate the word frames. The normal mode of operation is used to
transfer data at a periodic rate, one word per period. The network mode is similar in that
it is also intended for periodic transfers; however, it supports up to 32 words (time slots)
per period. This mode can be used to build time division multiplexed (TDM) networks. In
contrast, the on-demand mode is intended for non-periodic transfers of data and to
transfer data serially at high speed when the data becomes available.
The following figure shows the ESAI block diagram.

Overview
TX RX
FIFO FIFO
IP Bus
ESAI_TX0
ESAI_RSMA
ESAI_RSMB Shift Register TX0 [PC11]
ESAI_TSMA
ESAI_TX1
ESAI_TSMB
Shift Register TX1 [PC10]
ESAI_RCCR ESAI_TX2
ESAI_RCR
Shift Register TX2_RX3 [PC9]
ESAI_TCCR ESAI_RX3
ESAI_TCR
ESAI_TX3
ESAI_SAICR Shift Register TX3_RX2 [PC8]
ESAI_SAISR ESAI_RX2
ESAI_TX4
ESAI_TSR
ESAI_RX1
Clock/Frame Sync
Generators
and
Control Logic ESAI_TX5
RCLK
TCLK
ESAI_RX0
[PC2] HCKR
[PC0] SCKR
[PC5] HCKT
[PC3] SCKT
[PC1] FSR
[PC4] FST
Figure 25-1. ESAI Block Diagram

Chapter 25 Enhanced Serial Audio Interface (ESAI)
25.1.1 Features
• Independent (asynchronous mode) or shared (synchronous mode) transmit and
receive sections with separate or shared internal/external clocks and frame syncs,
operating in Master or Slave mode.
• Up to six transmitters and four receivers with TX2_RX3, TX3_RX2, TX4_RX1, and
TX5_RX0 pins shared by transmitters 2 to 5 and receivers 0 to 3. TX0 AND TX1
pins are used by transmitters 0 and 1 only.
• Programmable data interface modes such as I2S, LSB aligned, MSB aligned
• Programmable word length (8, 12, 16, 20 or 24bits)
• Flexible selection between system clock or external oscillator as input clock source,
programmable internal clock divider and frame sync generation
• AC97 support
• Time Slot Mask Registers for reduced ARM platform overhead (for both Transmit
and Receive)
• 128-word Transmit FIFO shared by six transmitters
• 128-word Receive FIFO shared by four receivers

ESAI has three basic operating modes and many data/operation formats.
ESAI operating mode are selected by the ESAI control registers (ESAI_TCCR,
ESAI_TCR, ESAI_RCCR, ESAI_RCR, and ESAI_SAICR). The main operating modes
are described in the following section.
25.1.2.1 Normal/Network/On-Demand Mode Selection

Selecting between the normal mode and network mode is accomplished by clearing or
setting the TMOD0-TMOD1 bits in the ESAI_TCR register for the transmitter section, as
well as in the RMOD0-RMOD1 bits in the ESAI_RCR register for the receiver section.
For normal mode, the ESAI functions with one data word of I/O per frame (per enabled
transmitter or receiver). The normal mode is typically used to transfer data to or from a
single device.

Overview
For the network mode, 2 to 32 time slots per frame may be selected. During each frame, 0
to 32 data words of I/O may be received or transmitted. In either case, the transfers are
periodic. The frame sync signal indicates the first time slot in the frame. Network mode is
typically used in time division multiplexed (TDM) networks of codecs, DSPs with
multiple words per frame, or multi-channel devices.
Selecting the network mode and setting the frame rate divider to zero (DC=00000) selects
the on-demand mode. This special case does not generate a periodic frame sync. A frame
sync pulse is generated only when data is available to transmit. The on-demand mode
requires that the transmit frame sync be internal (output) and the receive frame sync be
external (input). Therefore, for simplex operation, the synchronous mode could be used;
however, for full-duplex operation, the asynchronous mode must be used. Data
transmission that is data driven is enabled by writing data into each TX. Although the
ESAI is double buffered, only one word can be written to each TX, even if the transmit
shift register is empty. The receive and transmit interrupts function as usual using TDE
and RDF; however, transmit underruns are impossible for on-demand transmission and
are disabled.
25.1.2.2 Synchronous/Asynchronous Operating Modes

The transmit and receive sections of the ESAI may be synchronous or asynchronous, that
is, the transmitter and receiver sections may use common clock and synchronization
signals (synchronous operating mode), or they may have their own separate clock and
sync signals (asynchronous operating mode).
The SYN bit in the ESAI_SAICR register selects synchronous or asynchronous
operation. Because the ESAI is designed to operate either synchronously or
asynchronously, separate receive and transmit interrupts are provided.
When SYN is cleared, the ESAI transmitter and receiver clocks and frame sync sources
are independent. If SYN is set, the ESAI transmitter and receiver clocks and frame sync
come from the transmitter section (either external or internal sources).
Data clock and frame sync signals can be generated internally by the ARM Core or may
be obtained from external sources. If internally generated, the ESAI clock generator is
used to derive high frequency clock, bit clock and frame sync signals from the ARM
Core internal system clock.
25.1.2.3 Frame Sync Selection

The frame sync can be either a bit-long or word-long signal.

The transmitter frame format is defined by the TFSL bit in the ESAI_TCR register. The
receiver frame format is defined by the RFSL bit in the ESAI_RCR register.
1. In the word-long frame sync format, the frame sync signal is asserted during the
entire word data transfer period. This frame sync length is compatible with codecs,
SPI serial peripherals, serial A/D and D/A converters, shift registers and
telecommunication PCM serial I/O.
2. In the bit-long frame sync format, the frame sync signal is asserted for one bit clock
immediately before the data transfer period. This frame sync length is compatible
with Intel and National components, codecs and telecommunication PCM serial I/O.
The relative timing of the word length frame sync as referred to the data word is specified
by the TFSR bit in the ESAI_TCR register for the transmitter section and by the RFSR
bit in the ESAI_RCR register for the receive section. The word length frame sync may be
generated (or expected) with the first bit of the data word, or with the last bit of the
previous word. TFSR and RFSR are ignored when a bit length frame sync is selected.
Polarity of the frame sync signal may be defined as positive (asserted high) or negative
(asserted low). The TFSP bit in the ESAI_TCCR register specifies the polarity of the
frame sync for the transmitter section. The RFSP bit in the ESAI_RCCR register
specifies the polarity of the frame sync for the receiver section.
The ESAI receiver looks for a receive frame sync leading edge (trailing edge if RFSP is
set) only when the previous frame is completed. If the frame sync goes high before the
frame is completed (or before the last bit of the frame is received in the case of a bit
frame sync or a word length frame sync with RFSR set), the current frame sync is not
recognized, and the receiver is internally disabled until the next frame sync. Frames do
not have to be adjacent, that is, a new frame sync does not have to immediately follow
the previous frame. Gaps of arbitrary periods can occur between frames. Enabled
transmitters are tri-stated during these gaps.
When operating in the synchronous mode (SYN=1), all clocks including the frame sync
are generated by the transmitter section.
25.1.2.4 Shift Direction Selection

Some data formats, such as those used by codecs, specify MSB first while other data
formats, such as the AES-EBU digital audio interface, specify LSB first.
The MSB/LSB first selection is made by programming RSHFD bit in the ESAI_RCR
register for the receiver section and by programming the TSHFD bit in the ESAI_TCR
register for the transmitter section.

External Signals

Three to twelve pins are required for operation, depending on the operating mode
selected and the number of transmitters and receivers enabled.
The TX0 and TX1 pins are used by transmitters 0 and 1 only. The TX2_RX3, TX3_RX2,
TX4_RX1, and TX5_RX0 pins are shared by transmitters 2 to 5 with receivers 0 to 3.
The actual mode of operation is selected under software control. All transmitters operate
fully synchronized under control of the same transmitter clock signals. All receivers
operate fully synchronized under control of the same receiver clock signals.
The following table describes the external signals of ESAI:
Table 25-1. ESAI External Signals
ESAI_RX_CLK RX serial bit clock for the ESAI ENET_MDIO ALT2 IO
interface. The direction can be GPIO_1 ALT0
programmed.
ESAI_RX_FS RX frame sync signal for the ESAI ENET_REF_CLK ALT2 IO
interface. GPIO_9 ALT0
ESAI_RX_HF_CLK RX high frequency clock for the ENET_RX_ER ALT2 IO
ESAI interface. GPIO_3 ALT0
ESAI_TX0 Used for transmitting data from the GPIO_17 ALT0 IO
ESAI_TX0 serial transmit shift NANDF_CS2 ALT2
register.
ESAI_TX1 Used for transmitting data from the GPIO_18 ALT0 IO
ESAI_TX1 serial transmit shift NANDF_CS3 ALT2
register.
ESAI_TX2_RX3 Used as TX2 for transmitting data ENET_TXD1 ALT2 IO
from the ESAI_TX2 serial transmit GPIO_5 ALT0
shift register when programmed as a
transmitter pin
Used as the RX3 signal for receiving
serial data to the ESAI_RX3 serial
receive shift register when
programmed as a receiver pin
ESAI_TX3_RX2 Used as TX3 for transmitting data ENET_TX_EN ALT2 IO
transmitter pin

Table 25-1. ESAI External Signals

(continued)
ESAI_TX4_RX1 Used as TX4 for transmitting data ENET_TXD0 ALT2 IO
from the ESAI_TX4 serial transmit
GPIO_7 ALT0
transmitter pin
ESAI_TX5_RX0 Used as TX5 for transmitting data ENET_MDC ALT2 IO
transmitter pin
ESAI_TX_CLK TX serial bit clock for the ESAI ENET_CRS_DV ALT2 IO
interface. The direction can be GPIO_6 ALT0
programmed.
ESAI_TX_FS Frame sync for both the transmitters ENET_RXD1 ALT2 IO
and receivers in the synchronous GPIO_2 ALT0
mode (SYN=1) and for the
transmitters only in asynchronous
mode
ESAI_TX_HF_CLK TX high frequency clock for the ENET_RXD0 ALT2 IO
ESAI interface. GPIO_4 ALT0
25.2.1 Serial Transmit 0 Data Pin

TX0 is used for transmitting data from the ESAI_TX0 serial transmit shift register.
TX0 is an output when data is being transmitted from the ESAI_TX0 shift register. In the
on-demand mode with an internally generated bit clock, the TX0 pin becomes high
impedance for a full clock period after the last data bit has been transmitted, assuming
another data word does not follow immediately. If a data word follows immediately,
there is no high-impedance interval.
TX0 may be programmed as a disconnected pin (PC11) when the ESAI TX0 function is
not being used. See Table 25-14.

External Signals
25.2.2 Serial Transmit 1 Data Pin

TX1 is used for transmitting data from the ESAI_TX1 serial transmit shift register.
TX1 is an output when data is being transmitted from the ESAI_TX1 shift register. In the
on-demand mode with an internally generated bit clock, the TX1 pin becomes high
impedance for a full clock period after the last data bit has been transmitted, assuming
another data word does not follow immediately. If a data word follows immediately,
there is no high-impedance interval.
TX1 may be programmed as a disconnected pin (PC10) when the ESAI TX1 function is
25.2.3 Serial Transmit 2/Receive 3 Data Pin

TX2_RX3 is used as the TX2 for transmitting data from the ESAI_TX2 serial transmit
shift register when programmed as a transmitter pin, or as the RX3 signal for receiving
serial data to the ESAI_RX3 serial receive shift register when programmed as a receiver
pin.
TX2_RX3 is an input when data is being received by the ESAI_RX3 shift register.
TX2_RX3 is an output when data is being transmitted from the ESAI_TX2 shift register.
In the on-demand mode with an internally generated bit clock, the TX2_RX3 pin
becomes high impedance for a full clock period after the last data bit has been
transmitted, assuming another data word does not follow immediately. If a data word
follows immediately, there is no high-impedance interval.
TX2_RX3 may be programmed as a disconnected pin (PC9) when the ESAI TX2 and
RX3 functions are not being used. See Table 25-14.

TX3_RX2 is used as the TX3 signal for transmitting data from the ESAI_TX3 serial
transmit shift register when programmed as a transmitter pin, or as the RX2 signal for
receiving serial data to the ESAI_RX2 serial receive shift register when programmed as a
receiver pin.


transmit shift register when programmed as transmitter pin, or as the RX1 signal for
receiving serial data to the RX1 serial receive shift register when programmed as a
receiver pin.

transmit shift register when programmed as transmitter pin, or as the RX0 signal for
receiving serial data to the ESAI_RX0 serial shift register when programmed as a
receiver pin.

External Signals
25.2.7 Receiver Serial Clock

SCKR is a bidirectional pin providing the receivers serial bit clock for the ESAI
interface.
The direction of this pin is determined by the RCKD bit in the ESAI_RCCR register. The
SCKR operates as a clock input or output used by all the enabled receivers in the
asynchronous mode (SYN = 0), or as serial flag 0 pin in the synchronous mode (SYN =
1).
When this pin is configured as serial flag pin, its direction is determined by the RCKD bit
in the ESAI_RCCR register. When configured as the output flag OF0, this pin reflects the
value of the OF0 bit in the ESAI_SAICR register, and the data in the OF0 bit shows up at
the pin synchronized to the frame sync being used by the transmitter and receiver
sections. When this pin is configured as the input flag IF0, the data value at the pin is
stored in the IF0 bit in the ESAI_SAISR register, synchronized by the frame sync in
normal mode or the slot in network mode.
SCKR may be programmed as a disconnected pin (PC0) when the ESAI SCKR function
is not being used. See Table 25-14.
NOTE
Although the external ESAI serial clocks can be independent of
and asynchronous to the internal ESAI system clock, the
external ESAI serial clock cannot exceed the internal ESAI
system clock divided by 6.
For SCKR pin mode definitions, see Table 25-11.
The table below provides a list of asynchronous-mode receiver clock sources. For more
information about EXTAL/ESAI clocking control bits (ERI, ERO), refer to ESAI Control
Register (ESAI_ECR).
Table 25-2. Receiver Clock Sources (Asynchronous Mode Only)
RHCKD RFSD RCKD ERI ERO Receiver OUTPUTS
Bit Clock
Source
0 0 0 N/A N/A SCKR - - -
0 0 1 N/A N/A HCKR - - SCKR
0 1 0 N/A N/A SCKR - FSR -
0 1 1 N/A N/A HCKR - FSR SCKR
1 0 0 0 0 SCKR HCKR - -
1 0 0 0 1 SCKR HCKR - -

Table 25-2. Receiver Clock Sources (Asynchronous Mode Only)

(continued)
RHCKD RFSD RCKD ERI ERO Receiver OUTPUTS
Bit Clock
Source
1 0 0 1 0 SCKR HCKR - -
1 0 0 1 1 SCKR HCKR - -
1 0 1 0 0 Fsys1 HCKR - SCKR
1 0 1 0 1 Fsys HCKR - SCKR
1 0 1 1 0 EXTAL2 HCKR - SCKR
1 0 1 1 1 EXTAL HCKR - SCKR
1 1 0 0 0 SCKR HCKR FSR -
1 1 1 0 0 Fsys HCKR FSR SCKR
1 1 1 0 1 Fsys HCKR FSR SCKR
1 1 1 1 0 EXTAL HCKR FSR SCKR
1 1 1 1 1 EXTAL HCKR FSR SCKR
Fsys = ipg_clk_esai
EXTAL is the on-chip clock source other than ipg_clk_esai ESAI system clock, and it is from esai_clk_root in CCM.
25.2.8 Transmitter Serial Clock

SCKT is a bidirectional pin providing the transmitters serial bit clock for the ESAI
interface.
The direction of this pin is determined by the TCKD bit in the ESAI_TCCR register. The
SCKT is a clock input or output used by all the enabled transmitters in the asynchronous
mode (SYN = 0) or by all the enabled transmitters and receivers in the synchronous mode
(SYN = 1).
The following table provides a list of asynchronous-mode transmitter clock sources.
Table 25-3. Transmitter Clock Sources (Asynchronous Mode Only)
THCKD TFSD TCKD ETI ETO Transmitte OUTPUTS
r Bit Clock
Source
0 0 0 N/A N/A SCKT - - -
0 0 1 N/A N/A HCKT - - SCKT
0 1 0 N/A N/A SCKT - FST -

External Signals
Table 25-3. Transmitter Clock Sources (Asynchronous Mode Only)

(continued)
THCKD TFSD TCKD ETI ETO Transmitte OUTPUTS
r Bit Clock
Source
0 1 1 N/A N/A HCKT - FST SCKT
1 0 0 0 0 SCKT HCKT - -
1 0 0 0 1 SCKT HCKT - -
1 0 0 1 0 SCKT HCKT - -
1 0 0 1 1 SCKT HCKT - -
1 0 1 0 0 Fsys1 HCKT - SCKT
1 0 1 0 1 Fsys HCKT - SCKT
1 0 1 1 0 EXTAL2 HCKT - SCKT
1 0 1 1 1 EXTAL HCKT - SCKT
1 1 0 0 0 SCKR HCKT FST -
1 1 1 0 0 Fsys HCKT FST SCKT
1 1 1 0 1 Fsys HCKT FST SCKT
1 1 1 1 0 EXTAL HCKT FST SCKT
1 1 1 1 1 EXTAL HCKT FST SCKT
Fsys = ipg_clk_esai
EXTAL is the on-chip clock sources other than ipg_clk_easi ESAI system clock, and it is from esai_clk_root in CCM
SCKT may be programmed as a disconnected pin (PC3) when the ESAI SCKT function
For more information about EXTAL/ESAI clocking control bits (ETI, ETO), see ESAI
Control Register (ESAI_ECR).
NOTE
Although the external ESAI serial clocks can be independent of
and asynchronous to the internal ESAI system clock, the
external ESAI serial clock cannot exceed the internal ESAI
system clock divided by 6.
25.2.9 Frame Sync for Receiver

FSR is a bidirectional pin providing the receivers frame sync signal for the ESAI
interface. The direction of this pin is determined by the RFSD bit in ESAI_RCR register.

In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or
output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates
as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable
control (TEBE=1, RFSD=1). For FSR pin mode definitions, see Table 25-12; for receiver
clock signals, see Table 25-2.
When this pin is configured as serial flag pin, its direction is determined by the RFSD bit
in the ESAI_RCCR register. When configured as the output flag OF1, this pin reflects the
value of the OF1 bit in the ESAI_SAICR register, and the data in the OF1 bit shows up at
the pin synchronized to the frame sync being used by the transmitter and receiver
sections. When configured as the input flag IF1, the data value at the pin is stored in the
IF1 bit in the ESAI_SAISR register, synchronized by the frame sync in normal mode or
the slot in network mode.
FSR may be programmed as a disconnected pin (PC1) when the ESAI FSR function is
25.2.10 Frame Sync for Transmitter

FST is a bidirectional pin providing the frame sync for both the transmitters and receivers
in the synchronous mode (SYN=1) and for the transmitters only in asynchronous mode
(SYN=0).
See Table 25-3. The direction of this pin is determined by the TFSD bit in the
ESAI_TCCR register. When configured as an output, this pin is the internally generated
frame sync signal. When configured as an input, this pin receives an external frame sync
signal for the transmitters (and the receivers in synchronous mode).
FST may be programmed as a disconnected pin (PC4) when the ESAI FST function is
25.2.11 High Frequency Clock for Transmitter

HCKT is a bidirectional pin providing the transmitters high frequency clock for the ESAI
interface.
The direction of this pin is determined by the THCKD bit in the ESAI_TCCR register. In
the asynchronous mode (SYN=0), the HCKT pin operates as the high frequency clock
input or output used by all enabled transmitters. In the synchronous mode (SYN=1), it
operates as the high frequency clock input or output used by all enabled transmitters and
receivers. When programmed as input this pin is used as an alternative high frequency

External Signals
clock source to the ESAI transmitter rather than the ARM Core main clock. When
programmed as output it can serve as a high frequency sample clock (to external DACs
for example) or as an additional system clock (see Table 25-3).
HCKT may be programmed as a disconnected pin (PC5) when the ESAI HCKT function
25.2.12 High Frequency Clock for Receiver

HCKR is a bidirectional pin providing the receivers high frequency clock for the ESAI
interface.
The direction of this pin is determined by the RHCKD bit in the ESAI_RCCR register. In
the asynchronous mode (SYN=0), the HCKR pin operates as the high frequency clock
input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it
operates as the serial flag 2 pin. For HCKR pin mode definitions, see Table 25-13; for
receiver clock signals, see Table 25-2.
When this pin is configured as serial flag pin, its direction is determined by the RHCKD
bit in the ESAI_RCCR register. When configured as the output flag OF2, this pin reflects
the value of the OF2 bit in the ESAI_SAICR register, and the data in the OF2 bit shows
up at the pin synchronized to the frame sync being used by the transmitter and receiver
sections. When configured as the input flag IF2, the data value at the pin is stored in the
IF2 bit in the ESAI_SAISR register, synchronized by the frame sync in normal mode or
the slot in network mode.
HCKR may be programmed as a disconnected pin (PC2) when the ESAI HCKR function
25.2.13 Serial I/O Flags

Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the
ESAI is operating in the synchronous mode (SYN=1).
Their operation is controlled by RCKD, RFSD, TEBE bits in the ESAI_RCR,
ESAI_RCCR and ESAI_SAICR registers.The output data bits (OF2, OF1 and OF0) and
the input data bits (IF2, IF1 and IF0) are double buffered to/from the HCKR, FSR and
SCKR pins. Double buffering the flags keeps them in sync with the TX and RX data
lines.

Each flag can be separately programmed. Flag 0 (SCKR pin) direction is selected by
RCKD, RCKD=1 for output and RCKD=0 for input. Flag 1 (FSR pin) is enabled when
the pin is not configured as external transmitter buffer enable (TEBE=0) and its direction
is selected by RFSD, RFSD=1 for output and RFSD=0 for input. Flag 2 (HCKR pin)
direction is selected by RHCKD, RHCKD=1 for output and RHCKD=0 for input.
When programmed as input flags, the SCKR, FSR and HCKR logic values, respectively,
are latched at the same time as the first bit of the receive data word is sampled. Because
the input was latched, the signal on the input flag pin (SCKR, FSR or HCKR) can change
without affecting the input flag until the first bit of the next receive data word. When the
received data words are transferred to the receive data registers, the input flag latched
values are then transferred to the IF0, IF1 and IF2 bits in the SAISR register, where they
may be read by software.
When programmed as output flags, the SCKR, FSR and HCKR logic values are driven by
the contents of the OF0, OF1 and OF2 bits in the ESAI_SAICR register respectively, and
they are driven when the transmit data registers are transferred to the transmit shift
registers. The value on SCKR, FSR and HCKR is stable from the time the first bit of the
transmit data word is transmitted until the first bit of the next transmit data word is
transmitted. Software may change the OF0-OF2 values thus controlling the SCKR, FSR
and HCKR pin values for each transmitted word. The normal sequence for setting output
flags when transmitting data is as follows: wait for TDE (transmitter empty) to be set;
first write the flags, and then write the transmit data to the transmit registers. OF0, OF1,
and OF2 are double buffered so that the flag states appear on the pins when the transmit
data is transferred to the transmit shift register, that is, the flags are synchronous with the
data.
25.3 Clocks
The table found here describes the clock sources for ESAI.
Please see clock control block for clock setting, configuration and gating information.
Table 25-4. ESAI Clocks
extal_clk esai_clk_root ESAI system clock
ipg_clk_esai ahb_clk_root Bus clock
mem_clk ahb_clk_root Mem clock


25.4.1 ESAI After Reset

Hardware or software reset clears the port control register bits and the port direction
control register bits, which configure all ESAI I/O pins as disconnected and both ESAI
FIFOs are also in reset state.
The ESAI is in personal reset state while all ESAI pins are programmed as disconnected,
and it is active only if at least one of the ESAI I/O pins is programmed as an ESAI pin.
25.4.2 ESAI Interrupt Requests

The ESAI can generate eight different interrupt requests.
Ordered from the highest to the lowest priority):
1. ESAI Receive Data with Exception Status
Occurs when the receive exception interrupt is enabled (REIE=1 in the RCR
register), at least one of the enabled receive data registers is full (RDF=1) and a
receiver overrun error has occurred (ROE=1 in the SAISR register). ROE is cleared
by first reading the SAISR and then reading all the enabled receive data registers.
2. ESAI Receive Even Data
Occurs when the receive even slot data interrupt is enabled (REDIE=1), at least one
of the enabled receive data registers is full (RDF=1), the data is from an even slot
(REDF=1) and no exception has occurred (ROE=0 or REIE=0).
Reading all enabled receiver data registers clears RDF and REDF.
3. ESAI Receive Data
Occurs when the receive interrupt is enabled (RIE=1), at least one of the enabled
receive data registers is full (RDF=1), no exception has occurred (ROE=0 or
REIE=0) and no even slot interrupt has occurred (REDF=0 or REDIE=0). Reading
all enabled receiver data registers clears RDF.
4. ESAI Receive Last Slot Interrupt

Occurs, if enabled (RLIE=1), after the last slot of the frame ended (in network mode
only) regardless of the receive mask register setting. The receive last slot interrupt
may be used for resetting the receive mask slot register, reconfiguring the DMA
channels and reassigning data memory pointers. Using the receive last slot interrupt
guarantees that the previous frame was serviced with the previous setting and the
new frame is serviced with the new setting without synchronization problems. Note
that the maximum receive last slot interrupt service time should not exceed N-1
ESAI bits service time (where N is the number of bits in a slot).
5. ESAI Transmit Data with Exception Status
Occurs when the transmit exception interrupt is enabled (TEIE=1), at least one
transmit data register of the enabled transmitters is empty (TDE=1) and a transmitter
underrun error has occurred (TUE=1). TUE is cleared by first reading the SAISR and
then writing to all the enabled transmit data registers, or to the TSR register.
6. ESAI Transmit Last Slot Interrupt
Occurs, if enabled (TLIE=1), at the start of the last slot of the frame in network mode
regardless of the transmit mask register setting. The transmit last slot interrupt may
be used for resetting the transmit mask slot register, reconfiguring the DMA channels
and reassigning data memory pointers. Using the transmit last slot interrupt
guarantees that the previous frame was serviced with the previous setting and the
new frame is serviced with the new setting without synchronization problems. Note
that the maximum transmit last slot interrupt service time should not exceed N-1
ESAI bits service time (where N is the number of bits in a slot).
7. ESAI Transmit Even Data
Occurs when the transmit even slot data interrupt is enabled (TEDIE=1), at least one
of the enabled transmit data registers is empty (TDE=1), the slot is an even slot
(TEDE=1) and no exception has occurred (TUE=0 or TEIE=0). Writing to all the TX
registers of the enabled transmitters or to TSR clears this interrupt request.
8. ESAI Transmit Data
Occurs when the transmit interrupt is enabled (TIE=1), at least one of the enabled
transmit data registers is empty (TDE=1), no exception has occurred (TUE=0 or
TEIE=0) and no even slot interrupt has occurred (TEDE=0 or TEDIE=0). Writing to
all the TX registers of the enabled transmitters, or to the TSR clears this interrupt
request.

25.4.3 ESAI DMA Requests from the FIFOs

The ESAI can generate two different DMA requests:
1. ESAI Transmit FIFO Empty - Asserts when the number of empty slots in the ESAI
transmit FIFO exceeds the threshold programmed in the ESAI Transmit FIFO
Configuration Register (TFCR). Automatically negates when the number of empty
slots is less than the threshold programmed in the ESAI Transmit FIFO
Configuration Register.
2. ESAI Receive FIFO Full - Asserts when the number of data words in the ESAI
receive FIFO exceeds the threshold programmed in the ESAI Receive FIFO
Configuration Register (RFCR). Automatically negates when the number of words is
less than the threshold programmed in the ESAI Receive FIFO Configuration
Register.
25.4.4 ESAI Transmit and Receive Shift Registers
25.4.4.1 ESAI Transmit Shift Registers

The transmit shift registers contain the data being transmitted.
See Figure 25-2 and Figure 25-3.
Data is shifted out to the serial transmit data pins by the selected (internal/external) bit
clock when the associated frame sync I/O is asserted.
The number of bits shifted out before the shift registers are considered empty and may be
written to again can be 8, 12, 16, 20, 24 or 32 bits (determined by the slot length control
bits in the TCR register). Data is shifted out of these registers MSB first if TSHFD=0 and
LSB first if TSHFD=1.

(a) Receive Registers
23 16 15 8 7 0
ESAI RECEIVE DATA REGISTER

RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE
(READ ONLY)
7 0 7 0 7 0
23 16 15 8 7 0
RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE

SERIAL
RECEIVE 7 0 7 0 7 0
SHIFT 24 BIT
REGISTER
20 BIT
16 BIT RX
12 BIT
8 BIT RSWS4-
RSW0
MSB LSB LEAST SIGNIFICANT

8-BIT DATA 0 0 0 0
ZERO FILL
MSB LSB
12-BIT DATA
MSB LSB
16-BIT DATA
MSB LSB
20-BIT DATA
MSB LSB
24-BIT DATA
NOTES:
1. Data is received MSB first if RSHFD=0.
2. 24-bit fractional format (ALC=0).
(b) Transmit Registers 3. 32-bit mode is not shown
23 16 15 8 7 0
ESAI TRANSMIT DATA
TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE REGISTER
(WRITE ONLY)
7 0 7 0 7 0
23 16 15 8 7 0
TX TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE ESAI TRANSMIT
SHIFT REGISTER
7 0 7 0 7 0
MSB LSB * - LEAST SIGNIFICANT

8-BIT DATA * * * *
BIT FILL
MSB LSB
12-BIT DATA
MSB LSB
16-BIT DATA
MSB LSB
20-BIT DATA
MSB LSB
24-BIT DATA
NOTES:
1. Data is sent MSB first if TSHFD=0.
3. 32-bit mode is not shown.
4. Data word is left-aligned (TWA=0, PADC=0).
Figure 25-2. ESAI Data Path Programming Model ([R/T]SHFD=0)

(a) Receive Registers
23 16 15 8 7 0
ESAI RECEIVE DATA
RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE REGISTER
(READ ONLY)
7 0 7 0 7 0
23 16 15 8 7 0
RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE ESAI RECEIVE
RX
SHIFT REGISTER
7 0 7 0 7 0
MSB LSB LEAST SIGNIFICANT

8-BIT DATA 0 0 0 0
ZERO FILL
MSB LSB
12-BIT DATA
MSB LSB
16-BIT DATA
MSB LSB
20-BIT DATA
MSB LSB
24-BIT DATA
NOTES:
1. Data is received LSB first if RSHFD=1.
(b) Transmit Registers
23 16 15 8 7 0
ESAI TRANSMIT DATA REGISTER

TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE (WRITE ONLY)
7 0 7 0 7 0
23 16 15 8 7 0
TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE ESAI TRANSMIT
SHIFT REGISTER
7 0 7 0 7 0
24 BIT
20 BIT
16 BIT TX
12 BIT
8 BIT TSWS4-
TSW0
MSB LSB
8-BIT DATA 0 0 0 0
MSB LSB
12-BIT DATA
MSB LSB
16-BIT DATA
MSB LSB
20-BIT DATA
MSB LSB
24-BIT DATA
NOTES:
1. Data is sent LSB first if TSHFD=1.
4. Data word is left aligned (TWA=0,PADC=0).
Figure 25-3. ESAI Data Path Programming Model ([R/T]SHFD=1)

25.4.4.2 ESAI Receive Shift Registers

The receive shift registers (Figure 25-2 and Figure 25-3) receive the incoming data from
the serial receive data pins. Data is shifted in by the selected (internal/external) bit clock
when the associated frame sync I/O is asserted. Data is assumed to be received MSB first
if RSHFD=0 and LSB first if RSHFD=1. Data is transferred to the ESAI receive data
registers after 8, 12, 16, 20, 24, or 32 serial clock cycles were counted, depending on the
slot length control bits in the ESAI_RCR register.
25.5.1 ESAI Initialization

The correct way to initialize the ESAI is as follows:
1. Enable the ESAI logic clock by asserting bit 0 of ESAI Control Register
(ESAI_ECR[0]).
2. Hardware, software, ESAI individual reset. Note that asserting bit 1 of ESAI Control
Register only reset the ESAI core logic, including configuration registers, but not the
ESAI FIFOs.
3. Reset ESAI FIFOs by asserting bit 1 of ESAI_TFCR and ESAI_RFCR.
4. Clear the ESAI_TSMA/ESAI_TSMB.
5. Program ESAI control registers. (The transmit/receive enable bits of TCR/RCR
should not be set.)
6. Program ESAI FIFOs via TFCR and RFCR. (Enable Transmit/Receive FIFO, enable
transmitters/receivers, transmit initialization and set Transmit FIFO/Receive FIFO
watermark.)
7. Write initial words to ESAI Transmit Data Register (ESAI_ETDR), at least one word
per enabled transmitter slot but as many as desired. For example 4 channels with 2
slot-per-channel are enabled, then 8 words need to be written into ESAI_ETDR
8. Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC.
9. Enabled Transmitters/Receivers in ESAI_TCR/ESAI_RCR.
10. Configure time slot registers, first set ESAI_TSMB, then ESAI_TSMA.
During program execution, all ESAI pins may be defined disconnected, causing the ESAI
to stop serial activity and enter the individual reset state.

Initialization Information
All status bits of the interface are set to their reset state however, the control bits are not
affected. This procedure allows the programmer to reset the ESAI separately from the
other internal peripherals. During individual reset, internal DMA accesses to the data
registers of the ESAI are not valid and data read is undefined.
The programmer must use an individual ESAI reset when changing the ESAI control
registers (except for TEIE, REIE, TLIE, RLIE, TIE, RIE, TE0-TE5, RE0-RE3) to ensure
proper operation of the interface.
NOTE
If the ESAI receiver section is already operating with some of
the receivers and enabling additional receivers on the fly, that
is, without first putting the ESAI receiver in the personal reset
state by setting their REx control bits, it will result in erroneous
data being received as the first data word for the newly enabled
receivers.
25.5.2 ESAI Initialization Examples
25.5.2.1 Initializing the ESAI using Personal Reset

1. Enable the ESAI logic clock by setting bit 0 of ESAI Control
Register(ESAI_ECR[0]).
2. The ESAI should be in its personal reset state (ESAI_PCRC = 0x000 and
ESAI_PRRC = 0x000). In the personal reset state, both the transmitter and receiver
sections of the ESAI are simultaneously reset. The TPR bit in the ESAI_TCR register
may be used to reset just the transmitter section. The RPR bit in the ESAI_RCR
register may be used to reset just the receiver section.
3. Clear the ESAI_TSMA/ESAI_TSMB and ESAI_RSMA/ESAI_RSMB.
4. Configure the control registers (ESAI_TCCR, ESAI_TCR, ESAI_RCCR,
ESAI_RCR) and ESAI FIFOs configuration Registers (ESAI_TFCR, ESAI_RFCR)
according to the operating mode, but do not enable transmitters (TE5-TE0 = 0x0) or
receivers (RE3-RE0 = 0x0). It is possible to set the interrupt enable bits which are in
use during the operation (no interrupt occurs).
5. Enable the ESAI by setting the ESAI_PCRC and ESAI_PRRC register bits according
to pins which are in use during operation.
slot-per-channel are enabled, then 8 words need to be written into ESAI_ETDR. This
step is needed even if DMA is used to service the transmitters.
7. Enable the transmitters and receivers.
8. Configure time slot registers, first set ESAI_TSMB, then ESAI_TSMA, then
ESAI_RSMB, then ESAI_RSMA.
9. From now on ESAI can be serviced either by polling, interrupts, or DMA.
Operation proceeds as follows:
• For internally generated clock and frame sync, these signals are active immediately
after ESAI is enabled (step 4 above).
• Data is received only when one of the receive enable (REx) bits is set and after the
occurrence of frame sync signal (either internally or externally generated).
• Data is transmitted only when the transmitter enable (TEx) bit is set and after the
occurrence of frame sync signal (either internally or externally generated). The
transmitter outputs remain tri-stated after TEx bit is set until the frame sync occurs.
25.5.2.2 Initializing the ESAI Transmitter Section

1. It is assumed that the ESAI is operational; that is, at least one pin is defined as an
ESAI pin.
2. Enable the ESAI logic clock by setting bit 0 of ESAI Control
Register(ESAI_ECR[0])
3. The transmitter section should be in its individual reset state (TPR = 1) and also reset
the ESAI Transmit FIFO (ESAI_TFCR[1] = 1).
4. Clear the ESAI_TSMA/ESAI_TSMB.
5. Configure the control registers ESAI_TCCR and ESAI_TCR according to the
operating mode, configure the Transmit FIFO Configuration Register (bring transmit
FIFO out of reset, enable Transmit FIFO, enable transmitters, transmit initialization
and set watermark). Make sure to clear the transmitter enable bits (TE0-TE5). TPR
must remain set.
6. Take the transmitter section out of the individual reset state by clearing TPR.
slot-per-channel are enabled, then 8 words need to be written into ESAI_ETDR
8. Enable the transmitters by setting their TE bits.
9. Configure time slot registers, first set ESAI_TSMB, then ESAI_TSMA.
10. Data is transmitted only when the transmitter enable (TEx) bit is set and after the
occurrence of frame sync signal (either internally or externally generated). The
transmitter outputs remain tri-stated after TEx bit is set until the frame sync occurs.
11. From now on the transmitters are operating and can be serviced either by polling,
interrupts, or DMA.

ESAI Memory Map/Register Definition
25.5.2.3 Initializing the ESAI Receiver Section

1. It is assumed that the ESAI is operational; that is, at least one pin is defined as an
ESAI pin.
2. Enable the ESAI logic clock by setting bit 0 of ESAI Control Register
(ESAI_ECR[0])
3. The receiver section should be in its individual reset state (RPR = 1) and also reset
the ESAI Receive FIFO (ESAI_RFCR[1] = 1).
4. Clear the ESAI_RSMA/ESAI_RSMB.
5. Configure the control registers ESAI_RCCR and ESAI_RCR according to the
operating mode, configure the Receive FIFO Configuration Register (bring receive
FIFO out of reset, enable Receive FIFO, receivers, and set watermark). Making sure
to clear the receiver enable bits (RE0-RE3). RPR must remain set.
6. Take the receiver section out of the individual reset state by clearing RPR.
7. Enable the receivers by setting their RE bits.
8. Configure time slot registers, first set ESAI_RSMB, then set ESAI_RSMA.
9. From now on the receivers are operating and can be serviced either by polling,
interrupts, or DMA.
25.6 ESAI Memory Map/Register Definition

ESAI memory map
Absolute
Width Section/
(in bits) page
(hex)
W
202_4000 ESAI Transmit Data Register (ESAI_ETDR) 32 (always 0000_0000h 25.6.1/1078
reads 0)
202_4004 ESAI Receive Data Register (ESAI_ERDR) 32 R 0000_0000h 25.6.2/1078
202_4008 ESAI Control Register (ESAI_ECR) 32 R/W 0000_0000h 25.6.3/1079
202_400C ESAI Status Register (ESAI_ESR) 32 R 0000_0000h 25.6.4/1080
202_4010 Transmit FIFO Configuration Register (ESAI_TFCR) 32 R/W 0000_0000h 25.6.5/1082
202_4014 Transmit FIFO Status Register (ESAI_TFSR) 32 R 0000_0000h 25.6.6/1084
202_4018 Receive FIFO Configuration Register (ESAI_RFCR) 32 R/W 0000_0000h 25.6.7/1085
202_401C Receive FIFO Status Register (ESAI_RFSR) 32 R 0000_0000h 25.6.8/1087
W
202_4080 Transmit Data Register n (ESAI_TX0) 32 (always 0000_0000h 25.6.9/1088
reads 0)
W
reads 0)

ESAI memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
W
reads 0)
W
202_408C Transmit Data Register n (ESAI_TX3) 32 (always 0000_0000h 25.6.9/1088
reads 0)
W
reads 0)
W
reads 0)
W
25.6.10/
202_4098 ESAI Transmit Slot Register (ESAI_TSR) 32 (always 0000_0000h
1088
reads 0)
25.6.11/
202_40A0 Receive Data Register n (ESAI_RX0) 32 R 0000_0000h
1089
25.6.11/
1089
25.6.11/
1089
25.6.11/
202_40AC Receive Data Register n (ESAI_RX3) 32 R 0000_0000h
1089
25.6.12/
202_40CC Serial Audio Interface Status Register (ESAI_SAISR) 32 R 0000_0000h
1090
25.6.13/
202_40D0 Serial Audio Interface Control Register (ESAI_SAICR) 32 R/W 0000_0000h
1092
25.6.14/
202_40D4 Transmit Control Register (ESAI_TCR) 32 R/W 0000_0000h
1095
25.6.15/
202_40D8 Transmit Clock Control Register (ESAI_TCCR) 32 R/W 0000_0000h
1103
25.6.16/
202_40DC Receive Control Register (ESAI_RCR) 32 R/W 0000_0000h
1107
25.6.17/
202_40E0 Receive Clock Control Register (ESAI_RCCR) 32 R/W 0000_0000h
1111
25.6.18/
202_40E4 Transmit Slot Mask Register A (ESAI_TSMA) 32 R/W 0000_FFFFh
1114
25.6.19/
202_40E8 Transmit Slot Mask Register B (ESAI_TSMB) 32 R/W 0000_FFFFh
1115
25.6.20/
202_40EC Receive Slot Mask Register A (ESAI_RSMA) 32 R/W 0000_FFFFh
1116
25.6.21/
202_40F0 Receive Slot Mask Register B (ESAI_RSMB) 32 R/W 0000_FFFFh
1117
25.6.22/
202_40F8 Port C Direction Register (ESAI_PRRC) 32 R/W 0000_0000h
1118

ESAI memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
25.6.23/
202_40FC Port C Control Register (ESAI_PCRC) 32 R/W 0000_0000h
1118
25.6.1 ESAI Transmit Data Register (ESAI_ETDR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W ETDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_ETDR field descriptions

Field Description
ETDR ESAI Transmit Data Register. Writing to this register stores the data written into the ESAI Transmit FIFO.
Writing to this register when the Transmit FIFO is full causes the data written to be lost (the existing data
within the FIFO is not overwritten). When multiple ESAI transmitters are enabled, the data for each
transmitter must be interleaved from lowest transmitter to highest transmitter (for example, if transmitters
0, 2 and 3 are enabled then data must be written as follows: transmitter #0, transmitter #2, transmitter #3,
transmitter #0, transmitter #2, transmitter #3, transmitter #0, etc). Data within the ESAI Transmit FIFO is
passed to the ESAI transmit shifter registers as defined by the Transmit Word Alignment configuration bits.
25.6.2 ESAI Receive Data Register (ESAI_ERDR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ERDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_ERDR field descriptions

Field Description
ERDR ESAI Receive Data Register. Reading this register returns the data within the ESAI Receive FIFO.
Reading this register when the Receive FIFO is empty returns the last valid data word. When multiple
ESAI receivers are enabled, the data for each receiver is interleaved from lowest receiver to highest
receiver (for example, if receivers 0, 2 and 3 are enabled then data is returned as follows: receiver #0,
receiver #2, receiver #3, receiver #0, receiver #2, receiver #3, receiver #0, etc). Data is passed from the
ESAI receive shift registers to the ESAI Receive FIFO as defined by the Receiver Word Alignment
configuration bits either zero or sign-extended based on the Receive Extension control bit.

25.6.3 ESAI Control Register (ESAI_ECR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
ETI ETO ERI ERO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
ESAIEN
ERST
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_ECR field descriptions

Field Description
19 EXTAL Transmitter In. Mux EXTAL in place of the High Frequency Transmitter Clock input pin. HCKT can
ETI still be used to drive a divided down EXTAL or as GPIO.
0 HCKT pin has normal function.

1 EXTAL muxed into HCKT input.
18 EXTAL Transmitter Out. Drive the EXTAL input on the High Frequency Transmitter Clock pin.
ETO
0 HCKT pin has normal function.
1 EXTAL driven onto HCKT pin.
17 EXTAL Receiver In. Mux EXTAL in place of the High Frequency Receiver Clock input pin. HCKR can still
ERI be used to drive a divided down EXTAL or as GPIO.
0 HCKR pin has normal function.

1 EXTAL muxed into HCKR input.
16 EXTAL Receiver Out. Drive the EXTAL input on the High Frequency Receiver Clock pin.
ERO
0 HCKR pin has normal function.
1 EXTAL driven onto HCKR pin.
1 ESAI Reset. Reset the ESAI core logic (including configuration registers) but not the ESAI FIFOs.
ERST
0 ESAI not reset.
1 ESAI reset.
0 ESAI Enable. Enables/disables the ESAI logic clock. Enable the ESAI before reading or writing other ESAI
ESAIEN registers.

ESAI_ECR field descriptions (continued)

Field Description
0 ESAI disabled.
1 ESAI enabled.
25.6.4 ESAI Status Register (ESAI_ESR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TINIT RFF TFE TLS TDE TED TD RLS RDE RED RD

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_ESR field descriptions

Field Description
10 Transmit Initialization. Indicates that the Transmit FIFO is writing the first word for each enabled
TINIT transmitter into the Transmit Data Registers. This bit sets when the Transmit FIFO is enabled (provided
Transmit Initialization is enabled) and clears after the Transmit Data Registers have been initialized. The
Transmit Enable bits in the Transmit Control Register should not be set until this flag has cleared.
0 Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or
Transmit Initialization is not enabled).
1 Transmitter has not finished initializing the Transmit Data Registers.
9 Receive FIFO Full. Indicates that the number of data words in the Receive FIFO has equaled or exceeded
RFF the Receive FIFO Watermark. This flag also drives the ESAI Receiver DMA request line. ESAI FIFO DMA
requests see ESAI DMA Requests from the FIFOs.
0 Number of words in Receive FIFO less than Receive FIFO watermark.

1 Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark.
8 Transmit FIFO Empty. Indicates that the number of empty slots in the Transmit FIFO has met or exceeded
TFE the Transmit FIFO Watermark. This flag also drives the ESAI Transmitter DMA request line. ESAI FIFO
DMA request see ESAI DMA Requests from the FIFOs.
0 Number of empty slots in Transmit FIFO less than Transmit FIFO watermark.
1 Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark.
7 Transmit Last Slot. Reading this register when TLS is set will negate the Transmit Last Slot interrupt.
TLS
0 TLS is not the highest priority active interrupt.
1 TLS is the highest priority active interrupt.

ESAI_ESR field descriptions (continued)

Field Description
6 Transmit Data Exception.
TDE
0 TDE is not the highest priority active interrupt.
1 TDE is the highest priority active interrupt.
5 Transmit Even Data.
TED
0 TED is not the highest priority active interrupt.
1 TED is the highest priority active interrupt.
4 Transmit Data.
TD
0 TD is not the highest priority active interrupt.
1 TD is the highest priority active interrupt.
3 Receive Last Slot. Reading this register when RLS is set will negate the Receive Last Slot interrupt.
RLS
0 RLS is not the highest priority active interrupt.
1 RLS is the highest priority active interrupt.
2 Receive Data Exception.
RDE
0 RDE is not the highest priority active interrupt.
1 RDE is the highest priority active interrupt.
1 Receive Even Data.
RED
0 RED is not the highest priority active interrupt.
1 RED is the highest priority active interrupt.
0 Receive Data.
RD
0 RD is not the highest priority active interrupt.
1 RD is the highest priority active interrupt.

25.6.5 Transmit FIFO Configuration Register (ESAI_TFCR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reserved
Reserved
TIEN TWA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFWM TE5 TE4 TE3 TE2 TE1 TE0 TFR TFE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_TFCR field descriptions

Field Description
Reserved Reserved
Reserved Reserved
19 Transmitter Initialization Enable. Enables the initialization of the Transmit Data Registers when the
TIEN Transmitter FIFO is enabled. TIEN=1 is recommended.
0 Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software
must manually initialize the Transmit Data Registers separately.
1 Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled.
18–16 Transmit Word Alignment. Configures the alignment of the data written into the ESAI Transmit Data
TWA Register and then passed to the relevant 24 bit Transmit shift register.
NOTE: The settings shown below assume TCR[TWA]=0, TCR[PADC]=1 and TCR[TSHFD]=0.
000 MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register.
001 MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register.
010 MSB of data is bit 23.

ESAI_TFCR field descriptions (continued)

Field Description
011 MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed.
15–8 Transmit FIFO Watermark. These bits configure the threshold at which the Transmit FIFO Empty flag will
TFWM set. The TFE is set when the number of empty slots in the Transmit FIFO equal or exceed the selected
threshold.
7 Transmitter #5 FIFO Enable. This bit enables transmitter #5 to use the Transmit FIFO. Do not change this
TE5 bit when the Transmitter FIFO is enabled.
0 Transmitter #5 is not using the Transmit FIFO.

1 Transmitter #5 is using the Transmit FIFO.





1 Transmit FIFO Reset. This bit resets the Transmit FIFO pointers.
TFR
0 Transmit FIFO not reset.
1 Transmit FIFO reset.
0 Transmit FIFO Enable. This bit enables the use of the Transmit FIFO.
TFE
0 Transmit FIFO disabled.
1 Transmit FIFO enabled.

25.6.6 Transmit FIFO Status Register (ESAI_TFSR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 NTFO 0 NTFI TFCNT

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_TFSR field descriptions

Field Description
14–12 Next Transmitter FIFO Out. Indicates which Transmit Data Register receives the top word of the Transmit
NTFO FIFO. This will usually equal the lowest enabled transmitter, unless the transmit FIFO is empty.
000 Transmitter #0 receives next word from the Transmit FIFO.

110 Reserved.
111 Reserved.
10–8 Next Transmitter FIFO In. Indicates which transmitter receives the next word written to the FIFO.
NTFI
000 Transmitter #0 receives next word written to the Transmit FIFO.
110 Reserved.
111 Reserved.
TFCNT Transmit FIFO Counter. These bits indicate the number of data words stored in the Transmit FIFO.

25.6.7 Receive FIFO Configuration Register (ESAI_RFCR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reserved
Reserved
REXT RWA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RFWM RE3 RE2 RE1 RE0 RFR RFE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_RFCR field descriptions

Field Description
Reserved Reserved
Reserved Reserved
19 Receive Extension. Enables the receive data to be returned sign extended when the Receive Word
REXT Alignment is configured to return data where the MSB is not aligned with bit 31.
0 Receive data is zero extended.

1 Receive data is sign extended.
18–16 Receive Word Alignment. Configures the alignment of the data passed from the relevant 24 bit Receive
RWA shift register and read out the ESAI Receive Data Register.
000 MSB of data is at bit 31. Data bits 7-0 are zeroed.
001 MSB of data is at bit 27. Data bits 3-0 are zeroed.
010 MSB of data is at bit 23.
011 MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored.

ESAI_RFCR field descriptions (continued)

Field Description
15–8 Receive FIFO Watermark. These bits configure the threshold at which the Receive FIFO Full flag will set.
RFWM The RFF is set when the number of words in the Receive FIFO equal or exceed the selected threshold. It
can be set to a non-zero value.
5 Receiver #3 FIFO Enable. This bit enables receiver #3 to use the Receive FIFO. Do not change this bit
RE3 when the Receiver FIFO is enabled.
0 Receiver #3 is not using the Receive FIFO.

1 Receiver #3 is using the Receive FIFO.



1 Receive FIFO Reset. This bit resets the Receive FIFO pointers.
RFR
0 Receive FIFO not reset.
1 Receive FIFO reset.
0 Receive FIFO Enable. This bit enables the use of the Receive FIFO.
RFE
0 Receive FIFO disabled.
1 Receive FIFO enabled.

25.6.8 Receive FIFO Status Register (ESAI_RFSR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 NRFI 0 NRFO RFCNT

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_RFSR field descriptions

Field Description
13–12 Next Receiver FIFO In. Indicates which Receiver Data Register the Receive FIFO will load next. This will
NRFI usually equal the lowest enabled receiver, unless the receive FIFO is full.
00 Receiver #0 returns next word to the Receive FIFO.

9–8 Next Receiver FIFO Out. Indicates which receiver returns the top word of the Receive FIFO.
NRFO
00 Receiver #0 returns next word from the Receive FIFO.
RFCNT Receive FIFO Counter. These bits indicate the number of data words stored in the Receive FIFO.

25.6.9 Transmit Data Register n (ESAI_TXn)
ESAI_TX5, ESAI_TX4, ESAI_TX3, ESAI_TX2, ESAI_TX1 and ESAI_TX0 are 32-bit

write-only registers. Data to be transmitted is written into these registers and is
automatically transferred to the transmit shift registers (Figure 25-2 and Figure 25-3).
The data written (8, 12, 16, 20, or 24 bits) should occupy the most significant portion of
the TXn according to the ALC control bit setting. The unused bits (least significant
portion and the 8 most significant bits when ALC=1) of the TXn are don't care bits. The
Core is interrupted whenever the TXn becomes empty if the transmit data register empty
interrupt has been enabled.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
W TXn
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_TXn field descriptions

Field Description
TXn Stores the data to be transmitted and is automatically transferred to the transmit shift registers.
See ESAI Transmit Shift Registers.
25.6.10 ESAI Transmit Slot Register (ESAI_TSR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
W TSR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_TSR field descriptions

Field Description

ESAI_TSR field descriptions (continued)

Field Description
TSR The write-only Transmit Slot Register (ESAI_TSR) is effectively a null data register that is used when the
data is not to be transmitted in the available transmit time slot. The transmit data pins of all the enabled
transmitters are in the high-impedance state for the respective time slot where TSR has been written. The
Transmitter External Buffer Enable pin (FSR pin when SYN=1, TEBE=1, RFSD=1) disables the external
buffers during the slot when the ESAI_TSR register has been written.
25.6.11 Receive Data Register n (ESAI_RXn)
ESAI_RX3, ESAI_RX2, ESAI_RX1, and ESAI_RX0 are 32-bit read-only registers that
accept data from the receive shift registers when they become full (Figure 25-2 and
Figure 25-3). The data occupies the most significant portion of the receive data registers,
according to the ALC control bit setting. The unused bits (least significant portion and 8
most significant bits when ALC=1) read as zeros. The Core is interrupted whenever RXn
becomes full if the associated interrupt is enabled.
Address: 202_4000h base + A0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RXn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_RXn field descriptions

Field Description
RXn Accept data from the receive shift registers when they become full
See ESAI Receive Shift Registers

25.6.12 Serial Audio Interface Status Register (ESAI_SAISR)
The Status Register (ESAI_SAISR) is a read-only status register used by the ARM Core
to read the status and serial input flags of the ESAI.
Address: 202_4000h base + CCh offset = 202_40CCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TODFE
TEDE
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RODF
REDF
ROE
RDF
TDE
R TUE TFS 0 RFS 0 IF2 IF1 IF0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_SAISR field descriptions

Field Description
17 ESAI_SAISR Transmit Odd-Data Register Empty. When set, TODFE indicates that the enabled
TODFE transmitter data registers became empty at the beginning of an odd time slot. Odd time slots are all odd-
numbered slots (1, 3, 5, and so on). Time slots are numbered from zero to N-1, where N is the number of
time slots in the frame. This flag is set when the contents of the transmit data register of all the enabled
transmitters are transferred to the transmit shift registers; it is also set for a TSR disabled time slot period
in network mode (as if data were being transmitted after the TSR was written). When set, TODFE
indicates that data should be written to all the TX registers of the enabled transmitters or to the transmit
slot register (ESAI_TSR). TODE is cleared when the Core writes to all the transmit data registers of the

ESAI_SAISR field descriptions (continued)

Field Description
enabled transmitters, or when the Core writes to the TSR to disable transmission of the next time slot. If
TIE is set, an ESAI transmit data interrupt request is issued when TODFE is set. Hardware, software,
ESAI individual reset clear TODFE.
16 ESAI_SAISR Transmit Even-DataRegister Empty. When set, TEDE indicates that the enabled transmitter
TEDE data registers became empty at the beginning of an even time slot. Even time slots are all even-numbered
slots (0, 2, 4, 6, etc.). Time slots are numbered from zero to N-1, where N is the number of time slots in
the frame. The zero time slot is considered even. This flag is set when the contents of the transmit data
register of all the enabled transmitters are transferred to the transmit shift registers; it is also set for a TSR
disabled time slot period in network mode (as if data were being transmitted after the TSR was written).
When set, TEDE indicates that data should be written to all the TX registers of the enabled transmitters or
to the transmit slot register (ESAI_TSR). TEDE is cleared when the Core writes to all the transmit data
registers of the enabled transmitters, or when the Core writes to the TSR to disable transmission of the
next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TEDE is set. Hardware,
software, ESAI individual reset clear TEDE.
15 ESAI_SAISR Transmit Data Register Empty. TDE is set when the contents of the transmit data register of
TDE all the enabled transmitters are transferred to the transmit shift registers; it is also set for a TSR disabled
time slot period in network mode (as if data were being transmitted after the TSR was written). When set,
TDE indicates that data should be written to all the TX registers of the enabled transmitters or to the
transmit slot register (ESAI_TSR). TDE is cleared when the Core writes to all the transmit data registers of
the enabled transmitters, or when the Core writes to the TSR to disable transmission of the next time slot.
If TIE is set, an ESAI transmit data interrupt request is issued when TDE is set. Hardware, software, ESAI
individual reset clear TDE.
14 ESAI_SAISR Transmit Underrun Error Flag. TUE is set when at least one of the enabled serial transmit
TUE shift registers is empty (no new data to be transmitted) and a transmit time slot occurs. When a transmit
underrun error occurs, the previous data (which is still present in the TX registers that were not written) is
retransmitted. If TEIE is set, an ESAI transmit data with exception (underrun error) interrupt request is
issued when TUE is set. Hardware, software, ESAI individual reset clear TUE. TUE is also cleared by
reading the ESAI_SAISR with TUE set, followed by writing to all the enabled transmit data registers or to
ESAI_TSR.
13 ESAI_SAISR Transmit Frame Sync Flag. When set, TFS indicates that a transmit frame sync occurred in
TFS the current time slot. TFS is set at the start of the first time slot in the frame and cleared during all other
time slots. Data written to a transmit data register during the time slot when TFS is set is transmitted (in
network mode), if the transmitter is enabled, during the second time slot in the frame. TFS is useful in
network mode to identify the start of a frame. TFS is cleared by hardware, software, ESAI individual reset.
TFS is valid only if at least one transmitter is enabled, that is, one or more of TE0, TE1, TE2, TE3, TE4
and TE5 are set. (In normal mode, TFS always reads as a one when transmitting data because there is
only one time slot per frame - the "frame sync" time slot)
10 ESAI_SAISR Receive Odd-Data Register Full. When set, RODF indicates that the received data in the
RODF receive data registers of the enabled receivers have arrived during an odd time slot when operating in the
network mode. Odd time slots are all odd-numbered slots (1, 3, 5, and so on). Time slots are numbered
from zero to N-1, where N is the number of time slots in the frame. RODF is set when the contents of the
receive shift registers are transferred to the receive data registers. RODF is cleared when the Core reads
all the enabled receive data registers or cleared by hardware, software, ESAI individual resets.
9 ESAI_SAISR Receive Even-Data Register Full. When set, REDF indicates that the received data in the
REDF receive data registers of the enabled receivers have arrived during an even time slot when operating in the
network mode. Even time slots are all even-numbered slots (0, 2, 4, 6, and so on). Time slots are
numbered from zero to N-1, where N is the number of time slots in the frame. The zero time slot is
considered even. REDF is set when the contents of the receive shift registers are transferred to the
receive data registers. REDF is cleared when the Core reads all the enabled receive data registers or

ESAI_SAISR field descriptions (continued)

Field Description
cleared by hardware, software, ESAI individual resets. If REDIE is set, an ESAI receive even slot data
interrupt request is issued when REDF is set.
8 ESAI_SAISR Receive Data Register Full. RDF is set when the contents of the receive shift register of an
RDF enabled receiver is transferred to the respective receive data register. RDF is cleared when the Core
reads the receive data register of all enabled receivers or cleared by hardware, software, ESAI individual
reset. If RIE is set, an ESAI receive data interrupt request is issued when RDF is set.
7 ESAI_SAISR Receive Overrun Error Flag. The ROE flag is set when the serial receive shift register of an
ROE enabled receiver is full and ready to transfer to its receiver data register (RXn) and the register is already
full (RDF=1). If REIE is set, an ESAI receive data with exception (overrun error) interrupt request is issued
when ROE is set. Hardware, software, ESAI individual reset clear ROE. ROE is also cleared by reading
the SAISR with ROE set, followed by reading all the enabled receive data registers.
6 ESAI_SAISR Receive Frame Sync Flag. When set, RFS indicates that a receive frame sync occurred
RFS during reception of the words in the receiver data registers. This indicates that the data words are from the
first slot in the frame. When RFS is clear and a word is received, it indicates (only in the network mode)
that the frame sync did not occur during reception of that word. RFS is cleared by hardware, software,
ESAI individual reset. RFS is valid only if at least one of the receivers is enabled (REx=1). (In normal
mode, RFS always reads as a one when reading data because there is only one time slot per frame - the
"frame sync" time slot)
2 ESAI_SAISR Serial Input Flag 2. The IF2 bit is enabled only when the HCKR pin is defined as ESAI in the
IF2 Port Control Register, SYN=1 and RHCKD=0, indicating that HCKR is an input flag and the synchronous
mode is selected. Data present on the HCKR pin is latched during reception of the first received data bit
after frame sync is detected. The IF2 bit is updated with this data when the receive shift registers are
transferred into the receiver data registers. IF2 reads as a zero when it is not enabled. Hardware,
software, ESAI individual reset clear IF2.
1 ESAI_SAISR Serial Inout Flag 1. The IF1 bit is enabled only when the FSR pin is defined as ESAI in the
IF1 Port Control Register, SYN =1, RFSD=0 and TEBE=0, indicating that FSR is an input flag and the
synchronous mode is selected. Data present on the FSR pin is latched during reception of the first
received data bit after frame sync is detected. The IF1 bit is updated with this data when the receiver shift
registers are transferred into the receiver data registers. IF1 reads as a zero when it is not enabled.
Hardware, software, ESAI individual reset clear IF1.
0 ESAI_SAISR Serial Input Flag 0. The IF0 bit is enabled only when the SCKR pin is defined as ESAI in the
IF0 Port Control Register, SYN=1 and RCKD=0, indicating that SCKR is an input flag and the synchronous
mode is selected. Data present on the SCKR pin is latched during reception of the first received data bit
after frame sync is detected. The IF0 bit is updated with this data when the receiver shift registers are
transferred into the receiver data registers. IF0 reads as a zero when it is not enabled. Hardware,
software, ESAI individual reset clear IF0.
25.6.13 Serial Audio Interface Control Register (ESAI_SAICR)

The read/write Common Control Register (ESAI_SAICR) contains control bits for
functions that affect both the receive and transmit sections of the ESAI.

ASYNCHRONOUS (SYN=0)
TRANSMITTER
SDO
FRAME
CLOCK SYNC
EXTERNAL TRANSMIT CLOCK EXTERNAL TRANSMIT FRAME SYNC

SCKT FST
ESAI BIT INTERNAL CLOCK INTERNAL FRAME SYNC

CLOCK
EXTERNAL RECEIVE CLOCK EXTERNAL RECEIVE FRAME SYNC
SCKR FSR
CLOCK FRAME
SYNC
SDI
RECEIVER
NOTE: Transmitter and receiver may have different clocks and frame syncs.
SYNCHRONOUS (SYN=1)
TRANSMITTER
SDO
FRAME
CLOCK SYNC
EXTERNAL CLOCK EXTERNAL FRAME SYNC

SCKT FST
ESAI BIT INTERNAL CLOCK INTERNAL FRAME SYNC

CLOCK
CLOCK FRAME
SYNC
SDI
RECEIVER
NOTE: Transmitter and receiver have the same clocks and frame syncs.
Figure 25-4. SAICR SYN Bit Operation

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
ALC TEBE SYN OF2 OF1 OF0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_SAICR field descriptions

Field Description
8 ESAI_SAICR Alignment Control. The ESAI is designed for 24-bit fractional data, thus shorter data words
ALC are left aligned to the MSB (bit 23). Some applications use 16-bit fractional data. In those cases, shorter
data words may be left aligned to bit 15. The Alignment Control (ALC) bit supports these applications.
If ALC is set, transmitted and received words are left aligned to bit 15 in the transmit and receive shift
registers. If ALC is cleared, transmitted and received word are left aligned to bit 23 in the transmit and
receive shift registers.
While ALC is set, 20-bit and 24-bit words may not be used, and word length control should specify 8-, 12-,
or 16-bit words; otherwise, results are unpredictable.
7 ESAI_SAICR Transmit External Buffer Enable. The Transmitter External Buffer Enable (TEBE) bit controls
TEBE the function of the FSR pin when in the synchronous mode. If the ESAI is configured for operation in the
synchronous mode (SYN=1), and TEBE is set while FSR pin is configured as an output (RFSD=1), the
FSR pin functions as the transmitter external buffer enable control to enable the use of an external buffers
on the transmitter outputs. If TEBE is cleared, the FSR pin functions as the serial I/O flag 1. See Port C
Control Register for a summary of the effects of TEBE on the FSR pin.
6 ESAI_SAICR Synchronous Mode Selection. The Synchronous Mode Selection (SYN) bit controls whether
SYN the receiver and transmitter sections of the ESAI operate synchronously or asynchronously with respect to
each other (see Port C Control Register ). When SYN is cleared, the asynchronous mode is chosen and
independent clock and frame sync signals are used for the transmit and receive sections. When SYN is
set, the synchronous mode is chosen and the transmit and receive sections use common clock and frame
sync signals.
When in the synchronous mode (SYN=1), the transmit and receive sections use the transmitter section
clock generator as the source of the clock and frame sync for both sections. Also, the receiver clock pins
SCKR, FSR and HCKR now operate as I/O flags. Refer to Table 25-11, Table 25-12, and Table 25-13 for
the effects of SYN on the receiver clock pins.
2 ESAI_SAICR Serial Output Flag 2. The Serial Output Flag 2 (OF2) is a data bit used to hold data to be
OF2 send to the OF2 pin. When the ESAI is in the synchronous clock mode (SYN=1), the HCKR pin is
configured as the ESAI flag 2. If the receiver high frequency clock direction bit (RHCKD) is set, the HCKR
pin is the output flag OF2, and data present in the OF2 bit is written to the OF2 pin at the beginning of the
frame in normal mode or at the beginning of the next time slot in network mode.
OF1 send to the OF1 pin. When the ESAI is in the synchronous clock mode (SYN=1), the FSR pin is
configured as the ESAI flag 1. If the receiver frame sync direction bit (RFSD) is set and the TEBE bit is
cleared, the FSR pin is the output flag OF1, and data present in the OF1 bit is written to the OF1 pin at the
beginning of the frame in normal mode or at the beginning of the next time slot in network mode.

ESAI_SAICR field descriptions (continued)

Field Description
OF0 send to the OF0 pin. When the ESAI is in the synchronous clock mode (SYN=1), the SCKR pin is
configured as the ESAI flag 0. If the receiver serial clock direction bit (RCKD) is set, the SCKR pin is the
output flag OF0, and data present in the OF0 bit is written to the OF0 pin at the beginning of the frame in
normal mode or at the beginning of the next time slot in network mode.
25.6.14 Transmit Control Register (ESAI_TCR)

The read/write Transmit Control Register (ESAI_TCR) controls the ESAI transmitter
section. Interrupt enable bits for the transmitter section are provided in this control
register. Operating modes are also selected in this register.
Table 25-5. Transmit Network Mode Selection
TMOD1 TMOD0 TDC4-TDC0 Transmitter Network Mode
0 0 0x0-0x1F Normal Mode
0 1 0x0 On-Demand Mode
0 1 0x1-0x1F Network Mode
1 0 X Reserved
1 1 0x0C AC97

NORMAL MODE
SERIAL CLOCK
FRAME SYNC
TRANSMITTER INTERRUPT (OR DMA REQUEST)
AND FLAGS SET
DATA DATA
SERIAL DATA
RECEIVER INTERRUPT (OR DMA
REQUEST) AND FLAGS SET
NOTE: Interrupts occur and data is transferred once per frame sync.
NETWORK MODE
SERIAL CLOCK
FRAME SYNC
TRANSMITTER INTERRUPT (OR DMA REQUEST)
AND FLAGS SET
SERIAL DATA SLOT 0 SLOT 1 SLOT 2 SLOT 0 SLOT 1
RECEIVER INTERRUPT (OR DMA

REQUEST) AND FLAGS SET
NOTE: Interrupts occur and a word may be transferred at every time slot.
Figure 25-5. Normal and Network Operation
Table 25-6. ESAI Transmit Slot and Word Length Selection

TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 SLOT LENGTH WORD
LENGTH
0 0 0 0 0 8 8
0 0 1 0 0 12 8
0 0 0 0 1 12
0 1 0 0 0 16 8
0 0 1 0 1 12
0 0 0 1 0 16
0 1 1 0 0 20 8
0 1 0 0 1 12
0 0 1 1 0 16
0 0 0 1 1 20
1 0 0 0 0 24 8
0 1 1 0 1 12
0 1 0 1 0 16
0 0 1 1 1 20

Table 25-6. ESAI Transmit Slot and Word Length Selection

(continued)
TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 SLOT LENGTH WORD
LENGTH
1 1 1 1 0 24
1 1 0 0 0 32 8
1 0 1 0 1 12
1 0 0 1 0 16
0 1 1 1 1 20
1 1 1 1 1 24
0 1 0 1 1 Reserved
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1

WORD LENGTH: TFSL=0, RFSL=0
SERIAL CLOCK
RX, TX FRAME SYNC
RX, TX SERIAL DATA DATA DATA
NOTE: Frame sync occurs while data is valid.
ONE BIT LENGTH: TFSL=1, RFSL=1
SERIAL CLOCK
RX, TX FRAME SYNC
RX, TX SERIAL DATA DATA DATA
NOTE: Frame sync occurs for one bit time preceding the data.
MIXED FRAME LENGTH: TFSL=1, RFSL=0
SERIAL CLOCK
RX FRAME SYNC
RX SERIAL DATA DATA DATA
TX FRAME SYNC
TX SERIAL DATA DATA DATA
MIXED FRAME LENGTH: TFSL=0, RFSL=1
SERIAL
SERIAL CLOCK
CLOCK
RX FRAME SYNC
RX SERIAL DATA DATA DATA
TX FRAME SYNC
TX SERIAL DATA DATA DATA
Figure 25-6. Frame Length Selection

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
TEDIE
PADC
TLIE TIE TEIE TPR TFSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSHFD
TFSL TSWS TMOD TWA TE5 TE4 TE3 TE2 TE1 TE0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_TCR field descriptions

Field Description
23 ESAI_TCR Transmit Last Slot Interrupt Enable. TLIE enables an interrupt at the beginning of last slot of a
TLIE frame in network mode. When TLIE is set the Core is interrupted at the start of the last slot in a frame in
network mode regardless of the transmit mask register setting. When TLIE is cleared the transmit last slot
interrupt is disabled. TLIE is disabled when TDC=0x00000 (on-demand mode). The use of the transmit
last slot interrupt is described in ESAI Interrupt Requests.
22 ESAI_TCR Transmit Interrupt Enable. The Core is interrupted when TIE and the TDE flag in the
TIE ESAI_SAISR status register are set. When TIE is cleared, this interrupt is disabled. Writing data to all the
data registers of the enabled transmitters or to ESAI_TSR clears TDE, thus clearing the interrupt.
Transmit interrupts with exception have higher priority than normal transmit data interrupts, therefore if
exception occurs (TUE is set) and TEIE is set, the ESAI requests an ESAI transmit data with exception
interrupt from the interrupt controller.
21 ESAI_TCR Transmit Even Slot Data Interrupt Enable. The TEDIE control bit is used to enable the transmit
TEDIE even slot data interrupts. If TEDIE is set, the transmit even slot data interrupts are enabled. If TEDIE is
cleared, the transmit even slot data interrupts are disabled. A transmit even slot data interrupt request is
generated if TEDIE is set and the TEDE status flag in the ESAI_SAISR status register is set. Even time
slots are all even-numbered time slots (0, 2, 4, etc.) when operating in network mode. The zero time slot in
the frame is marked by the frame sync signal and is considered to be even. Writing data to all the data
registers of the enabled transmitters or to ESAI_TSR clears the TEDE flag, thus servicing the interrupt.
Transmit interrupts with exception have higher priority than transmit even slot data interrupts, therefore if
exception occurs (TUE is set) and TEIE is set, the ESAI requests an ESAI transmit data with exception
20 ESAI_TCR Transmit Exception Interrupt Enable. When TEIE is set, the Core is interrupted when both TDE
TEIE and TUE in the ESAI_SAISR status register are set. When TEIE is cleared, this interrupt is disabled.
Reading the ESAI_SAISR status register followed by writing to all the data registers of the enabled
transmitters clears TUE, thus clearing the pending interrupt.
19 ESAI_TCR Transmit Section Personal Reset. The TPR control bit is used to put the transmitter section of
TPR the ESAI in the personal reset state. The receiver section is not affected. When TPR is cleared, the
transmitter section may operate normally. When TPR is set, the transmitter section enters the personal
reset state immediately. When in the personal reset state, the status bits are reset to the same state as
after hardware reset. The control bits are not affected by the personal reset state. The transmitter data
pins are tri-stated while in the personal reset state; if a stable logic level is desired, the transmitter data
pins should be defined as GPIO outputs, or external pull-up or pull-down resistors should be used. The

ESAI_TCR field descriptions (continued)

Field Description
transmitter clock outputs drive zeroes while in the personal reset state. Note that to leave the personal
reset state by clearing TPR, the procedure described in ESAI Initialization Examples should be followed.
17 ESAI_TCR Transmit Zero Padding Control. When PADC is cleared, zero padding is disabled. When
PADC PADC is set, zero padding is enabled. PADC, in conjunction with the TCR[TWA] control bit, determines
the way that padding is done for operating modes where the word length is less than the slot length. See
the TCR[TWA] bit description in bit 7 for more details.
Because the data word is shorter than the slot length, the data word is extended until achieving the slot
length, according to the following rule:
If the data word is left-aligned (TCR[TWA]=0), and zero padding is disabled (PADC=0), the last data bit is
repeated after the data word has been transmitted. If zero padding is enabled (PADC=1), zeroes are
transmitted after the data word has been transmitted.
If the data word is right-aligned (TCR[TWA]=1), and zero padding is disabled (PADC=0), the first data bit
is repeated before the transmission of the data word. If zero padding is enabled (PADC=1), zeroes are
transmitted before the transmission of the data word.
16 ESAI_TCR Transmit Frame Sync Relative Timing. TFSR determines the relative timing of the transmit
TFSR frame sync signal as referred to the serial data lines, for a word length frame sync only (TFSL=0). When
TFSR is cleared the word length frame sync occurs together with the first bit of the data word of the first
slot. When TFSR is set the word length frame sync starts one serial clock cycle earlier, that is, together
with the last bit of the previous data word.
15 ESAI_TCR Transmit Frame Sync Length. The TFSL bit selects the length of frame sync to be generated
TFSL or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL is set, a 1-bit clock period
frame sync is selected. See Figure 1-21 for examples of frame length selection.
14–10 ESAI_TCR Tx Slot and Word Length Select (TSWS4-TSWS0). The TSWS4-TSWS0 bits are used to
TSWS select the length of the slot and the length of the data words being transferred through the ESAI. The word
length must be equal to or shorter than the slot length. The possible combinations are shown in Table
25-6. See also the ESAI data path programming model in Figure 25-2 and Figure 25-3.
9–8 ESAI_TCR Transmit Network Mode Control (TMOD1-TMOD0). The TMOD1 and TMOD0 bits are used to
TMOD define the network mode of ESAI transmitters, as shown in Table 25-6. In the normal mode, the frame rate
divider determines the word transfer rate - one word is transferred per frame sync during the frame sync
time slot, as shown in Figure 25-5. In network mode, it is possible to transfer a word for every time slot, as
shown in Figure 25-5. For further details, refer to Modes of Operation
In order to comply with AC-97 specifications, TSWS4-TSWS0 should be set to 00011 (20-bit slot, 20-bit
word length), TFSL and TFSR should be cleared, and TDC4-TDC0 should be set to 0x0C (13 words in
frame). If TMOD=0b11 and the above recommendations are followed, the first slot and word will be 16 bits
long, and the next 12 slots and words will be 20 bits long, as required by the AC97 protocol.
7 ESAI_TCR Transmit Word Alignment Control. The Transmitter Word Alignment Control (TCR[TWA]) bit
TWA defines the alignment of the data word in relation to the slot. This is relevant for the cases where the word
length is shorter than the slot length. If TCR[TWA] is cleared, the data word is left-aligned in the slot frame
during transmission. If TCR[TWA] is set, the data word is right-aligned in the slot frame during
transmission.
Because the data word is shorter than the slot length, the data word is extended until achieving the slot
length, according to the following rule:
If the data word is left-aligned (TCR[TWA]=0), and zero padding is disabled (PADC=0), the last data bit is
repeated after the data word has been transmitted. If zero padding is enabled (PADC=1), zeroes are
transmitted after the data word has been transmitted.


Field Description
If the data word is right-aligned (TCR[TWA]=1), and zero padding is disabled (PADC=0), the first data bit
is repeated before the transmission of the data word. If zero padding is enabled (PADC=1), zeroes are
transmitted before the transmission of the data word.
6 ESAI_TCR Transmit Shift Direction. The TSHFD bit causes the transmit shift registers to shift data out
TSHFD MSB first when TSHFD equals zero or LSB first when TSHFD equals one (see Figure 25-2 and Figure
25-3 .
5 ESAI_TCR ESAI Transmit 5 Enable. TE5 enables the transfer of data from ESAI_TX5 to the transmit shift
TE5 register #5. When TE5 is set and a frame sync is detected, the transmit #5 portion of the ESAI is enabled
for that frame. When TE5 is cleared, the transmitter #5 is disabled after completing transmission of data
currently in the ESAI transmit shift register. Data can be written to ESAI_TX5 when TE5 is cleared but the
data is not transferred to the transmit shift register #5.
The SDO5/SDI0 pin is the data input pin for ESAI_RX0 if TE5 is cleared and RE0 in the ESAI_RCR
register is set. If both RE0 and TE5 are cleared, the transmitter and receiver are disabled, and the pin is
tri-stated. Both RE0 and TE5 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE5 and setting it again disables the transmitter #5 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO5/SDI0 pin remains in the high-impedance state. The on-demand mode transmit enable
sequence can be the same as the normal mode, or TE5 can be left enabled.
The SDO4/SDI1 pin is the data input pin for ESAI_RX1 if TE4 is cleared and RE1 in the RCR register is
set. If both RE1 and TE4 are cleared, the transmitter and receiver are disabled, and the pin is tri-stated.
Both RE1 and TE4 should not be set at the same time.


Field Description
1 ESAI_TCR ESAI Transmit 1 Enable. TE1 enables the transfer of data from TX1 to the transmit shift
currently in the ESAI transmit shift register. The SDO1 output is tri-stated, and any data present in TX1 is
not transmitted, that is, data can be written to TX1 with TE1 cleared, but data is not transferred to the
transmit shift register #1.
period, the SDO1 pin remains in the high-impedance state. The on-demand mode transmit enable
currently in the ESAI transmit shift register. The SDO0 output is tri-stated, and any data present in
ESAI_TX0 is not transmitted, that is, data can be written to ESAI_TX0 with TE0 cleared, but data is not
transferred to the transmit shift register #0.
period, the SDO0 pin remains in the high-impedance state.The on-demand mode transmit enable

25.6.15 Transmit Clock Control Register (ESAI_TCCR)

The read/write Transmitter Clock Control Register (ESAI_TCCR) controls the ESAI
transmitter clock generator bit and frame sync rates, the bit clock and high frequency
clock sources and the directions of the HCKT, FST and SCKT signals. In the
synchronous mode (SYN=1), the bit clock defined for the transmitter determines the
receiver bit clock as well. ESAI_TCCR also controls the number of words per frame for
the serial data. Hardware and software reset clear all the bits of the ESAI_TCCR register.
Care should be taken in asynchronous mode whenever the frame sync clock (FSR, FST)
is not sourced directly from its associated bit clock (SCKR, SCKT). Proper phase
relationships must be maintained between these clocks in order to guarantee proper
operation of the ESAI.
NOTE
ARM Core clock is ipg_clk_esai in block ESAI which is from
CCM's ahb_clk_root.

ERI=1
EXTAL
RHCKD=1 PRESCALE DIVIDER DIVIDER
DIVIDE DIVIDE BY 1 DIVIDE BY 1 DIVIDE BY 1
Fsys OR TO DIVIDE BY TO DIVIDE BY
ERI=0 BY 2 DIVIDE BY 8 256 16
See HCKR Pin Definition RHCKD=0

Table (ESAI_RCCR) for
HCKR FLAG2 IN/OUT
options when SYN=1
RPSR RPM0-RPM7 RFP0-RFP3
ERO=1
EXTAL
HCKR
ERO=0
RHCKD
FLAG0 OUT FLAG0 IN INTERNAL BIT CLOCK

(SYNC MODE) (SYNC MODE)
RSWS4-RSWS0
RX WORD RX WORD
LENGTH DIVIDER CLOCK
SYN=1 SYN=0
SCKR RX SHIFT REGISTER

RCLOCK
SYN=0
RCKD SYN=1 TSWS4-TSWS0
INTERNAL BIT CLOCK TCLOCK

TX WORD TX WORD
SCKT LENGTH DIVIDER CLOCK
TCKD
TX SHIFT REGISTER
THCKD
ETO=0
HCKT
TPSR TPM0-TPM7 TFP0-TFP3

EXTAL
ETO=1
To SPDIF Xmt
THCKD=0
ETI=1 PRESCALE DIVIDER DIVIDER

DIVIDE
EXTAL DIVIDE BY 1 DIVIDE BY 1 DIVIDE BY 1
BY 2 OR TO DIVIDE BY TO DIVIDE BY
DIVIDE BY 8 256 16
THCKD=1
Fsys
ETI=0
Figure 25-7. ESAI Clock Generator Functional Block Diagram
NOTE
1. ETI, ETO, ERI and ERO bit descriptions are covered in
ESAI Control Register (ESAI_ECR). 2. Fsys is the ESAI
system 133 MHz clock. 3. EXTAL is the on-chip clock sources
other than ESAI system 133MHz clock.

RDC0- RDC4 RFSL
RX WORD
CLOCK
INTERNAL RX FRAME CLOCK
RECEIVER SYNC
FRAME RATE TYPE
DIVIDER RFSD
RFSD= 1 SYN=0
FSR
SYN= 0
RECEIVE
RECEIVE
CONTROL
LOGIC FRAME SYNC RFSD= 0 SYN=1
SYN=1
TDC0- TDC4 TFSL

FLAG1 IN FLAG1 OUT
TX WORD (SYNC mODE) (SYNC MODE) TFSD
CLOCK
INTERNAL TX FRAME CLOCK
TRANSMITTER SYNC FST
FRAME RATE TYPE
DIVIDER
TRANSMIT
TRANSMIT
CONTROL
LOGIC FRAME SYNC
Figure 25-8. ESAI Frame Sync Generator Functional Block Diagram
Table 25-7. Transmitter High Frequency Clock Divider

TFP3-TFP0 Divide Ratio
0x0 1
0x1 2
0x2 3
0x3 4
... ...
0xF 16

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
THCKD
THCKP
TCKD
TCKP
TFSD TFSP TFP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFP TDC TPSR TPM

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_TCCR field descriptions

Field Description
23 ESAI_TCCR Transmit High Frequency Clock Direction. THCKD controls the direction of the HCKT pin.
THCKD When THCKD is cleared, HCKT is an input; when THCKD is set, HCKT is an output (see Table 25-3).
22 ESAI_TCCR Transmit Frame Sync Signal Direction. TFSD controls the direction of the FST pin. When
TFSD TFSD is cleared, FST is an input; when TFSD is set, FST is an output (see Table 25-3).
21 ESAI_TCCR Transmit Clock Source Direction. The Transmitter Clock Source Direction (TCKD) bit selects
TCKD the source of the clock signal used to clock the transmit shift registers in the asynchronous mode (SYN=0)
and the transmit shift registers and the receive shift registers in the synchronous mode (SYN=1). When
TCKD is set, the internal clock source becomes the bit clock for the transmit shift registers and word
length divider and is the output on the SCKT pin. When TCKD is cleared, the clock source is external; the
internal clock generator is disconnected from the SCKT pin, and an external clock source may drive this
pin (see Table 25-3).
20 ESAI_TCCR Transmit High Frequency Clock Polarity
THCKP
The Transmitter High Frequency Clock Polarity (THCKP) bit controls the polarity of the HCKT.
0 - Normal polarity
1 - Inverted polarity
19 ESAI_TCCR Transmit Frame Sync Polarity. The Transmitter Frame Sync Polarity (TFSP) bit determines
TFSP the polarity of the transmit frame sync signal. When TFSP is cleared, the frame sync signal polarity is
positive, that is, the frame start is indicated by a high level on the frame sync pin. When TFSP is set, the
frame sync signal polarity is negative, that is, the frame start is indicated by a low level on the frame sync
pin.
18 ESAI_TCCR Transmit Clock Polarity. The Transmitter Clock Polarity (TCKP) bit controls on which bit clock
TCKP edge data and frame sync are clocked out and latched in. If TCKP is cleared the data and the frame sync
are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the transmit
bit clock. If TCKP is set the falling edge of the transmit clock is used to clock the data out and frame sync
and the rising edge of the transmit clock is used to latch the data and frame sync in.
17–14 ESAI_TCCR Tx High Frequency Clock Divider. The TFP3-TFP0 bits control the divide ratio of the
TFP transmitter high frequency clock to the transmitter serial bit clock when the source of the high frequency
clock and the bit clock is the internal ARM Core clock. When the HCKT input is being driven from an
external high frequency clock, the TFP3-TFP0 bits specify an additional division ratio in the clock divider
chain. Table 25-7 shows the specification for the divide ratio. Figure 25-7 shows the ESAI high frequency
clock generator functional diagram.

ESAI_TCCR field descriptions (continued)

Field Description
13–9 ESAI_TCCR Tx Frame Rate Divider Control. The TDC4-TDC0 bits control the divide ratio for the
TDC programmable frame rate dividers used to generate the transmitter frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide
ratio may range from 2 to 32 (TDC=0x00001 to 0x11111) for network mode. A divide ratio of one
(TDC=0x00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32
(TDC=0x00000 to 0x11111) for normal mode. In normal mode, a divide ratio of 1 (TDC=0x00000) provides
continuous periodic data word transfers. A bit-length frame sync (TFSL=1) must be used in this case.
The ESAI frame sync generator functional diagram is shown in Figure 25-8
8
TPSR ESAI_TCCR Transmit Prescaler Range. The TPSR bit controls a fixed divide-by-eight prescaler in series
with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a
slower bit clock is desired. When TPSR is set, the fixed prescaler is bypassed. When TPSR is cleared, the
fixed divide-by-eight prescaler is operational (see Figure 25-7). The maximum internally generated bit
clock frequency is Fsys/6; the minimum internally generated bit clock frequency is Fsys/(2 x 8 x 256 x
16)=Fsys/65536.
NOTE: Do not use the combination TPSR = 1 and TPM7-RPM0 = 0x00, which causes synchronization
problems when using the internal core clock as source (THCKD = 1 or TCKD = 1).
TPM ESAI_TCCR Transmit Prescale Modulus Select. The TPM7-TPM0 bits specify the divide ratio of the
prescale divider in the ESAI transmitter clock generator. A divide ratio from 1 to 256 (TPM=0x00 to 0xFF)
may be selected. The bit clock output is available at the transmit serial bit clock (SCKT) pin. The bit clock
output is also available internally for use as the bit clock to shift the transmit and receive shift registers.
The ESAI transmit clock generator functional diagram is shown in Figure 25-7.
25.6.16 Receive Control Register (ESAI_RCR)

The read/write Receive Control Register (ESAI_RCR) controls the ESAI receiver
section. Interrupt enable bits for the receivers are provided in this control register. The
receivers are enabled in this register (0,1,2 or 3 receivers can be enabled) if the input data
pin is not used by a transmitter. Operating modes are also selected in this register.
Table 25-8. ESAI Receive Network Mode Selection

RMOD1 RMOD0 RDC4-RDC0 Receiver Network Mode
0 0 0x0-0x1F Normal Mode
0 1 0x0 On-Demand Mode
0 1 0x1-0x1F Network Mode
1 0 X Reserved
1 1 0x0C AC97

Table 25-9. ESAI Receive Slot and Word Length Selection

RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 SLOT LENGTH WORD
LENGTH
0 0 0 0 0 8 8
0 0 1 0 0 12 8
0 0 0 0 1 12
0 1 0 0 0 16 8
0 0 1 0 1 12
0 0 0 1 0 16
0 1 1 0 0 20 8
0 1 0 0 1 12
0 0 1 1 0 16
0 0 0 1 1 20
1 0 0 0 0 24 8
0 1 1 0 1 12
0 1 0 1 0 16
0 0 1 1 1 20
1 1 1 1 0 24
1 1 0 0 0 32 8
1 0 1 0 1 12
1 0 0 1 0 16
0 1 1 1 1 20
1 1 1 1 1 24
0 1 0 1 1 Reserved
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1

Address: 202_4000h base + DCh offset = 202_40DCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
REDIE
RLIE RIE REIE RPR RFSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RSHFD
RFSL RSWS RMOD RWA RE3 RE2 RE1 RE0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_RCR field descriptions

Field Description
23 ESAI_RCR Receive Last Slot Interrupt Enable. RLIE enables an interrupt after the last slot of a frame
RLIE ended in network mode only. When RLIE is set the Core is interrupted after the last slot in a frame ended
regardless of the receive mask register setting. When RLIE is cleared the receive last slot interrupt is
disabled. Hardware and software reset clear RLIE. RLIE is disabled when RDC=00000 (on-demand
mode). The use of the receive last slot interrupt is described in ESAI Interrupt Requests.
22 ESAI_RCR Receive Interrupt Enable. The Core is interrupted when RIE and the RDF flag in the
RIE ESAI_SAISR status register are set. When RIE is cleared, this interrupt is disabled. Reading the receive
data registers of the enabled receivers clears RDF, thus clearing the interrupt.
Receive interrupts with exception have higher priority than normal receive data interrupts, therefore if
exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception
21 ESAI_RCR Receive Even Slot Data Interrupt Enable. The REDIE control bit is used to enable the receive
REDIE even slot data interrupts. If REDIE is set, the receive even slot data interrupts are enabled. If REDIE is
cleared, the receive even slot data interrupts are disabled. A receive even slot data interrupt request is
generated if REDIE is set and the REDF status flag in the ESAI_SAISR status register is set. Even time
slots are all even-numbered time slots (0, 2, 4, etc.) when operating in network mode. The zero time slot is
marked by the frame sync signal and is considered to be even. Reading all the data registers of the
enabled receivers clears the REDF flag, thus servicing the interrupt.
Receive interrupts with exception have higher priority than receive even slot data interrupts, therefore if
exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception
20 ESAI_RCR Receive Exception Interrupt Enable. When REIE is set, the Core is interrupted when both RDF
REIE and ROE in the ESAI_SAISR status register are set. When REIE is cleared, this interrupt is disabled.
Reading the ESAI_SAISR status register followed by reading the enabled receivers data registers clears
ROE, thus clearing the pending interrupt.
19 ESAI_RCR Receiver Section Personal Reset. The RPR control bit is used to put the receiver section of
RPR the ESAI in the personal reset state. The transmitter section is not affected. When RPR is cleared, the
receiver section may operate normally. When RPR is set, the receiver section enters the personal reset
state immediately. When in the personal reset state, the status bits are reset to the same state as after
hardware reset.The control bits are not affected by the personal reset state.The receiver data pins are
disconnected while in the personal reset state.

ESAI_RCR field descriptions (continued)

Field Description
NOTE: To leave the personal reset state by clearing RPR, the procedure described in ESAI Initialization
Examples should be followed.
16 ESAI_RCR Receiver Frame Sync Relative Timing. RFSR determines the relative timing of the receive
RFSR frame sync signal as referred to the serial data lines, for a word length frame sync only. When RFSR is
cleared the word length frame sync occurs together with the first bit of the data word of the first slot. When
RFSR is set the word length frame sync starts one serial clock cycle earlier, that is, together with the last
bit of the previous data word.
15 ESAI_RCR Receiver Frame Sync Length. The RFSL bit selects the length of the receive frame sync to be
RFSL generated or recognized. If RFSL is cleared, a word-length frame sync is selected. If RFSL is set, a 1-bit
clock period frame sync is selected. Refer to Figure 25-6 for examples of frame length selection.
14–10 ESAI_RCR Receiver Slot and Word Select. The RSWS4-RSWS0 bits are used to select the length of the
RSWS slot and the length of the data words being received through the ESAI. The word length must be equal to
or shorter than the slot length. The possible combinations are shown in Table 25-9. See also the ESAI
data path programming model in Figure 25-2 and Figure 25-3.
9–8 ESAI_RCR Receiver Network Mode Control. The RMOD1 and RMOD0 bits are used to define the network
RMOD mode of the ESAI receivers, as shown in Table 25-8. In the normal mode, the frame rate divider
determines the word transfer rate - one word is transferred per frame sync during the frame sync time slot,
as shown in Figure 25-5. In network mode, it is possible to transfer a word for every time slot, as shown in
Figure 25-5. For more details, see Modes of Operation.
In order to comply with AC-97 specifications, RSWS4-RSWS0 should be set to 0x00011 (20-bit slot, 20-bit
word); RFSL and RFSR should be cleared, and RDC4-RDC0 should be set to 0x0C (13 words in frame).
7 ESAI_RCR Receiver Word Alignment Control. The Receiver Word Alignment Control (RWA) bit defines
RWA the alignment of the data word in relation to the slot. This is relevant for the cases where the word length is
shorter than the slot length. If RWA is cleared, the data word is assumed to be left-aligned in the slot
frame. If RWA is set, the data word is assumed to be right-aligned in the slot frame.
If the data word is shorter than the slot length, the data bits which are not in the data word field are
ignored.
For data word lengths of less than 24 bits, the data word is right-extended with zeroes before being stored
in the receive data registers.
6 ESAI_RCR Receiver Shift Direction. The RSHFD bit causes the receiver shift registers to shift data in
RSHFD MSB first when RSHFD is cleared or LSB first when RSHFD is set (see Figure 25-2 and Figure 25-3).
3 ESAI_RCR ESAI Receiver 3 Enable. When RE3 is set and TE2 is cleared, the ESAI receiver 3 is enabled
RE3 and samples data at the SDO2/SDI3 pin. ESAI_TX2 and ESAI_RX3 should not be enabled at the same
time (RE3=1 and TE2=1). When RE3 is cleared, receiver 3 is disabled by inhibiting data transfer into
ESAI_RX3. If this bit is cleared while receiving a data word, the remainder of the word is shifted in and
transferred to the ESAI_RX3 data register.
If RE3 is set while some of the other receivers are already in operation, the first data word received in
ESAI_RX3 will be invalid and must be discarded.

ESAI_RCR field descriptions (continued)

Field Description
25.6.17 Receive Clock Control Register (ESAI_RCCR)

The read/write Receiver Clock Control Register (ESAI_RCCR) controls the ESAI
receiver clock generator bit and frame sync rates, word length, and number of words per
frame for the serial data. The ESAI_RCCR control bits are described in the following
paragraphs.
NOTE
ARM Core clock is ipg_clk_esai in block ESAI which is from
CCM's ahb_clk_root.
Table 25-10. Receiver High Frequency Clock Divider

RFP3-RFP0 Divide Ratio
0x0 1
0x1 2
0x2 3
0x3 4
... ...
0xF 16
Table 25-11. SCKR Pin Definition Table

Control Bits SCKR PIN
SYN RCKD
0 0 SCKR input

Table 25-11. SCKR Pin Definition Table (continued)

Control Bits SCKR PIN
SYN RCKD
0 1 SCKR output
1 0 IF0
1 1 OF0
Table 25-12. FSR Pin Definition Table

Control Bits FSR Pin
SYN TEBE RFSD
0 X 0 FSR input
0 X 1 FSR output
1 0 0 IF1
1 0 1 OF1
1 1 0 reserved
1 1 1 Transmitter Buffer Enable
Table 25-13. HCKR Pin Definition Table

Control Bits HCKR PIN
SYN RHCKD
0 0 HCKR input
0 1 HCKR output
1 0 IF2
1 1 OF2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
RHCKD
RHCKP
RCKD
RCKP
RFSD RFSP RFP

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFP RDC RPSR RPM

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ESAI_RCCR field descriptions

Field Description
23 ESAI_RCCR Receiver High Frequency Clock Direction. The Receiver High Frequency Clock Direction
RHCKD (RHCKD) bit selects the source of the receiver high frequency clock when in the asynchronous mode
(SYN=0) and the IF2/OF2 flag direction in the synchronous mode (SYN=1).
In the asynchronous mode, when RHCKD is set, the internal clock generator becomes the source of the
receiver high frequency clock and is the output on the HCKR pin. In the asynchronous mode, when
RHCKD is cleared, the receiver high frequency clock source is external; the internal clock generator is
disconnected from the HCKR pin, and an external clock source may drive this pin.
When RHCKD is cleared, HCKR is an input; when RHCKD is set, HCKR is an output.
In the synchronous mode when RHCKD is set, the HCKR pin becomes the OF2 output flag. If RHCKD is
cleared, the HCKR pin becomes the IF2 input flag. Refer to Table 25-2 and Table 25-13.
22 ESAI_RCCR Receiver Frame Sync Signal Direction. The Receiver Frame Sync Signal Direction (RFSD)
RFSD bit selects the source of the receiver frame sync signal when in the asynchronous mode (SYN=0) and the
IF1/OF1/Transmitter Buffer Enable flag direction in the synchronous mode (SYN=1).
In the asynchronous mode, when RFSD is set, the internal clock generator becomes the source of the
receiver frame sync and is the output on the FSR pin. In the asynchronous mode, when RFSD is cleared,
the receiver frame sync source is external; the internal clock generator is disconnected from the FSR pin,
and an external clock source may drive this pin.
In the synchronous mode when RFSD is set, the FSR pin becomes the OF1 output flag or the Transmitter
Buffer Enable, according to the TEBE control bit. If RFSD is cleared, the FSR pin becomes the IF1 input
flag. Refer to Table 25-2 and Table 25-12 .
21 ESAI_RCCR Receiver Clock Source Direction. The Receiver Clock Source Direction (RCKD) bit selects
RCKD the source of the clock signal used to clock the receive shift register in the asynchronous mode (SYN=0)
and the IF0/OF0 flag direction in the synchronous mode (SYN=1).
In the asynchronous mode, when RCKD is set, the internal clock source becomes the bit clock for the
receive shift registers and word length divider and is the output on the SCKR pin. In the asynchronous
mode when RCKD is cleared, the clock source is external; the internal clock generator is disconnected
from the SCKR pin, and an external clock source may drive this pin.
In the synchronous mode when RCKD is set, the SCKR pin becomes the OF0 output flag. If RCKD is
cleared, the SCKR pin becomes the IF0 input flag. Refer to Table 25-2 and Table 25-11.
20 ESAI_RCCR Receiver High Frequency Clock Polarity. The Receiver High Frequency Clock Polarity
RHCKP (RHCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If
RHCKP is cleared the data and the frame sync are clocked out on the rising edge of the receive high
frequency bit clock and the frame sync is latched in on the falling edge of the receive bit clock. If RHCKP
is set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge
of the receive clock is used to latch the frame sync in.
19 ESAI_RCCR Receiver Frame Sync Polarity. The Receiver Frame Sync Polarity (RFSP) determines the
RFSP polarity of the receive frame sync signal. When RFSP is cleared the frame sync signal polarity is positive,
that is, the frame start is indicated by a high level on the frame sync pin. When RFSP is set the frame sync
signal polarity is negative, that is, the frame start is indicated by a low level on the frame sync pin.
18 The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked
RCKP out and latched in. If RCKP is cleared the data and the frame sync are clocked out on the rising edge of
the receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock. If RCKP is
set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge of
the receive clock is used to latch the frame sync in.
17–14 ESAI_RCCR Rx High Frequency Clock Divider. The RFP3-RFP0 bits control the divide ratio of the
RFP receiver high frequency clock to the receiver serial bit clock when the source of the receiver high
frequency clock and the bit clock is the internal Arm Core clock. When the HCKR input is being driven

ESAI_RCCR field descriptions (continued)

Field Description
from an external high frequency clock, the RFP3-RFP0 bits specify an additional division ration in the
clock divider chain. Table 25-10 provides the specification of the divide ratio. Figure 25-7 shows the ESAI
high frequency generator functional diagram.
13–9 ESAI_RCCR Rx Frame Rate Divider Control. The RDC4-RDC0 bits control the divide ratio for the
RDC programmable frame rate dividers used to generate the receiver frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide
ratio may range from 2 to 32 (RDC=0x00001 to 0x11111) for network mode. A divide ratio of one
(RDC=0x00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32
(RDC=0x00000 to 0x11111) for normal mode. In normal mode, a divide ratio of one (RDC=0x00000)
provides continuous periodic data word transfers. A bit-length frame sync (RFSL=1) must be used in this
case.
The ESAI frame sync generator functional diagram is shown in Figure 25-8 .
8 ESAI_RCCR Receiver Prescaler Range. The RPSR controls a fixed divide-by-eight prescaler in series
RPSR with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a
slower bit clock is desired. When RPSR is set, the fixed prescaler is bypassed. When RPSR is cleared,
the fixed divide-by-eight prescaler is operational (see Figure 25-7). The maximum internally generated bit
clock frequency is Fsys/6, the minimum internally generated bit clock frequency is Fsys/(2 x 8 x 256 x
16)=Fsys/65536. (Do not use the combination RPSR=1 and RPM7-RPM0 =0x00, which causes
synchronization problems when using the internal Core clock as source (RHCKD=1 or RCKD=1))
RPM ESAI_RCCR Receiver Prescale Modulus Select. The RPM7-RPM0 bits specify the divide ratio of the
prescale divider in the ESAI receiver clock generator. A divide ratio from 1 to 256 (RPM=0x00 to 0xFF)
may be selected. The bit clock output is available at the receiver serial bit clock (SCKR) pin. The bit clock
output is also available internally for use as the bit clock to shift the receive shift registers. The ESAI
receive clock generator functional diagram is shown in Figure 25-7.
25.6.18 Transmit Slot Mask Register A (ESAI_TSMA)
The Transmit Slot Mask Register A together with Transmit Slot Mask Register B
(ESAI_TSMA and ESAI_TSMB) are two read/write registers used by the transmitters in
network mode to determine for each slot whether to transmit a data word and generate a
transmitter empty condition (TDE=1), or to tri-state the transmitter data pins. Fields
ESAI_TSMA[TS] and ESAI_TSMB[TS] are concatenated to form the 32-bit field
TS[31:0]. Bit number n in TS is the enable/disable control bit for transmission in slot
number n.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

ESAI_TSMA field descriptions

Field Description
TS Lower 16 bits of TS
When bit number N in ESAI_TSMA is cleared, all the transmit data pins of the enabled transmitters are tri-
stated during transmit time slot number N. The data is still transferred from the transmit data registers to
the transmit shift registers but neither the TDE nor the TUE flags are set. This means that during a
disabled slot, no transmitter empty interrupt is generated. The Core is interrupted only for enabled slots.
Data that is written to the transmit data registers when servicing this request is transmitted in the next
enabled transmit time slot.
When bit number N in ESAI_TSMA register is set, the transmit sequence is as usual: data is transferred
from the TX registers to the shift registers and transmitted during slot number N, and the TDE flag is set.
Using the slot mask in ESAI_TSMA does not conflict with using TSR. Even if a slot is enabled in
ESAI_TSMA, the user may choose to write to TSR instead of writing to the transmit data registers TXn.
This causes all the transmit data pins of the enabled transmitters to be tri-stated during the next slot.
Data written to the ESAI_TSMA affects the next frame transmission. The frame being transmitted is not
affected by this data and would comply to the last ESAI_TSMA setting. Data read from ESAI_TSMA
returns the last written data.
After hardware or software reset, the ESAI_TSMA register is preset to 0x0000FFFF, which means that all
16 possible slots are enabled for data transmission.
When operating in normal mode, bit 0 of the ESAI_TSMA register must be set, otherwise no output is
generated.
25.6.19 Transmit Slot Mask Register B (ESAI_TSMB)
The Transmit Slot Mask Register B together with Transmit Slot Mask Register A
(ESAI_TSMA and ESAI_TSMB) are two read/write registers used by the transmitters in
network mode to determine for each slot whether to transmit a data word and generate a
transmitter empty condition (TDE=1), or to tri-state the transmitter data pins. Fields
ESAI_TSMA[TS] and ESAI_TSMB[TS] are concatenated to form the 32-bit field
TS[31:0]. Bit number n in TS is the enable/disable control bit for transmission in slot
number n.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

ESAI_TSMB field descriptions

Field Description
TS When bit number N in ESAI_TSMB is cleared, all the transmit data pins of the enabled transmitters are tri-
stated during transmit time slot number N. The data is still transferred from the transmit data registers to
the transmit shift registers but neither the TDE nor the TUE flags are set. This means that during a
disabled slot, no transmitter empty interrupt is generated. The Core is interrupted only for enabled slots.
Data that is written to the transmit data registers when servicing this request is transmitted in the next
enabled transmit time slot.
When bit number N in ESAI_TSMB register is set, the transmit sequence is as usual: data is transferred
from the TX registers to the shift registers and transmitted during slot number N, and the TDE flag is set.
Using the slot mask in ESAI_TSMB does not conflict with using TSR. Even if a slot is enabled in TSMB,
the user may chose to write to TSR instead of writing to the transmit data registers TXn. This causes all
the transmit data pins of the enabled transmitters to be tri-stated during the next slot.
Data written to the ESAI_TSMB affects the next frame transmission. The frame being transmitted is not
affected by this data and would comply to the last ESAI_TSMB setting. Data read from ESAI_TSMB
returns the last written data.
After hardware or software reset, the ESAI_TSMB register is preset to 0x0000FFFF, which means that all
16 possible slots are enabled for data transmission.
25.6.20 Receive Slot Mask Register A (ESAI_RSMA)
The Receive Slot Mask Register A together with Receive Slot Mask Register B
(ESAI_RSMA and ESAI_RSMB) are two read/write registers used by the receiver in
network mode to determine for each slot whether to receive a data word and generate a
receiver full condition (RDF=1), or to ignore the received data. Fields ESAI_RSMA[RS]
and ESAI_RSMB[RS] are concatenated to form the 32-bit field RS[31:0]. Bit number n
in RS is an enable/disable control bit for receiving data in slot number n.
Address: 202_4000h base + ECh offset = 202_40ECh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ESAI_RSMA field descriptions

Field Description
RS When bit number N in the ESAI_RSMA register is cleared, the data from the enabled receivers input pins
are shifted into their receive shift registers during slot number N. The data is not transferred from the
receive shift registers to the receive data registers, and neither the RDF nor the ROE flag is set. This

ESAI_RSMA field descriptions (continued)

Field Description
means that during a disabled slot, no receiver full interrupt is generated. The Core is interrupted only for
enabled slots.
When bit number N in the ESAI_RSMA is set, the receive sequence is as usual: data which is shifted into
the enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set.
Data written to the ESAI_RSMA affects the next received frame. The frame being received is not affected
by this data and would comply to the last ESAI_RSMA setting. Data read from ESAI_RSMA returns the
last written data.
After hardware or software reset, the ESAI_RSMA register is preset to 0x0000FFFF, which means that all
16 possible slots are enabled for data reception.
When operating in normal mode, bit 0 of the ESAI_RSMA register must be set to one, otherwise no input
is received.
25.6.21 Receive Slot Mask Register B (ESAI_RSMB)
The Receive Slot Mask Register B together with Receive Slot Mask Register A
(ESAI_RSMA and ESAI_RSMB) are two read/write registers used by the receiver in
network mode to determine for each slot whether to receive a data word and generate a
receiver full condition (RDF=1), or to ignore the received data. Fields ESAI_RSMA[RS]
and ESAI_RSMB[RS] are concatenated to form the 32-bit field RS[31:0]. Bit number n
in RS is an enable/disable control bit for receiving data in slot number n.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ESAI_RSMB field descriptions

Field Description
RS When bit number N in the ESAI_RSMB register is cleared, the data from the enabled receivers input pins
are shifted into their receive shift registers during slot number N. The data is not transferred from the
receive shift registers to the receive data registers, and neither the RDF nor the ROE flag is set. This
means that during a disabled slot, no receiver full interrupt is generated. The Core is interrupted only for
enabled slots.
When bit number N in the ESAI_RSMB is set, the receive sequence is as usual: data which is shifted into
the enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set.
Data written to the ESAI_RSMB affects the next received frame. The frame being received is not affected
by this data and would comply to the last ESAI_RSMB setting. Data read from ESAI_RSMB returns the
last written data.

ESAI_RSMB field descriptions (continued)

Field Description
After hardware or software reset, the ESAI_RSMB register is preset to 0x0000FFFF, which means that all
16 possible slots are enabled for data reception.
25.6.22 Port C Direction Register (ESAI_PRRC)

There are two registers to control the ESAI personal reset status: Port C Direction
Register (ESAI_PRRC) and Port C Control Register (ESAI_PCRC).
The read/write 32-bit Port C Direction Register (ESAI_PRRC) in conjunction with the
Port C Control Register (ESAI_PCRC) controls the functionality of the ESAI personal
reset state. Table 25-14 provides the port pin configurations. Hardware and software reset
clear all ESAI_PRRC bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 PDC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_PRRC field descriptions

Field Description
PDC See Table 25-14.
25.6.23 Port C Control Register (ESAI_PCRC)

The read/write 32-bit Port C Control Register (ESAI_PCRC) in conjunction with the Port
C Direction Register (ESAI_PRRC) controls the functionality of the ESAI personal reset
state. Each of the PC(11:0) bits controls the functionality of the corresponding port pin.
Table 25-14 provides the port pin configurations. Hardware and software reset clear all
ESAI_PCRC bits.
Table 25-14. PCRC and PRRC Bits Functionality
PDC[i] PC[i] Port Pin[i] Function
0 0 Disconnected
1 1 ESAI

Address: 202_4000h base + FCh offset = 202_40FCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 PC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESAI_PCRC field descriptions

Field Description
PC See Table 25-14.


Chapter 26
Flexible Controller Area Network (FLEXCAN)
26.1 Overview
The Flexible Controller Area Network (FLEXCAN) module is a communication
controller implementing the CAN protocol according to the CAN 2.0B protocol
specification.
The CAN protocol was primarily designed to be used as a vehicle serial data bus meeting
the specific requirements of this field: real-time processing, reliable operation in the EMI
environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN
module is a full implementation of the CAN protocol specification, which supports both
standard and extended message frames. 64 Message Buffers are supported by the Flexcan
module.

A general block diagram is shown in the figure below,which describes the main sub-
blocks implemented in the FLEXCAN module, including the associated memory for
storing Mailboxes, Rx Global Mask Registers, Rx Individual Mask Registers, Rx FIFO
and Rx FIFO ID Filters.
Support for 64 Mailboxes and 6-deep Rx FIFO is provided. The functions of the sub-
modules are described in subsequent sections.

Overview
IPS
Control
IRQs Registers Host
Interface
MB 0
MB 1 Rx
Match
MB 5
Tx
Arbitration
MB 63
RAM
FlexCAN
Protocol
Engine
RX Pin
Tx Pin
CAN Bus
Figure 26-1. FLEXCAN Block Diagram

Chapter 26 Flexible Controller Area Network (FLEXCAN)
26.1.2 FLEXCAN Module Features

The FLEXCAN module includes these distinctive legacy features:
• Version 2.0B
• Standard data and remote frames
• Extended data and remote frames
• Zero to eight bytes data length
• Programmable bit rate up to 1 Mb/sec
• Content-related addressing
• Flexible Mailboxes of eight bytes data length
• Each Mailbox is configurable as Rx or Tx, all supporting standard and extended
messages
• Individual Rx Mask Registers per Mailbox
• Full featured Rx FIFO with storage capacity for 6 frames and internal pointer
handling
• Transmission abort capability
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 128
extended, 256 standard or 512 partial (8 bits) IDs, with up to 32 individual masking
capability
• 100% backwards compatibility with previous FLEXCAN version
• Unused structures space can be used as general purpose RAM space
• Listen only mode capability
• Programmable loop-back mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number or
highest priority
• Time Stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts independent of the transmission medium (an external transceiver
is assumed)
• Short latency time due to an arbitration scheme for high-priority messages
• Low power modes, with programmable wake up on bus activity
• Configurable Glitch filter width to filter the noise on CAN bus when waking up
• Remote request frames may be handled automatically or by software.
• ID filter configuration in Normal Mode
• CAN bit time settings and configuration bits can only be written in Freeze Mode
• Tx mailbox status (Lowest priority buffer or empty buffer)
• SYNC bit status to inform that the module is synchronous with CAN bus
• CRC status for transmitted message
• Selectable priority between Mailboxes and Rx FIFO during matching process

Overview

The FLEXCAN module has four functional modes: Normal Mode (User and Supervisor),
Freeze Mode, Listen-Only Mode and Loop-Back Mode. There are also two low power
modes: Disable Mode and Stop Mode.
• Normal Mode (User or Supervisor):
In Normal Mode, the module operates receiving and/or transmitting message frames,
errors are handled normally and all the CAN Protocol functions are enabled. User and
Supervisor Modes differ in the access to some restricted control registers.
• Freeze Mode:
It is enabled when the FRZ bit in the MCR Register is asserted. If enabled, Freeze Mode
is entered when the HALT bit in MCR is set or when Debug Mode is requested at MCU
level and the FRZ_ACK bit in the MCR Register is asserted by the FlexCAN. In this
mode, no transmission or reception of frames is done and synchronicity to the CAN bus
is lost. See Freeze Mode for more information.
• Listen-Only Mode:
The module enters this mode when the LOM bit in the Control Register is asserted. In
this mode, transmission is disabled, all error counters are frozen and the module operates
in a CAN Error Passive mode. Only messages acknowledged by another CAN station
will be received. If FLEXCAN detects a message that has not been acknowledged, it will
flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the
message.
• Loop-Back Mode:
The module enters this mode when the LPB bit in the Control Register is asserted. In this
mode, FLEXCAN performs an internal loop back that can be used for self test operation.
The bit stream output of the transmitter is internally fed back to the receiver input. The
FLEXCAN_RX input pin is ignored and the FLEXCAN_TX output goes to the recessive
state (logic '1'). FLEXCAN behaves as it normally does when transmitting and treats its
own transmitted message as a message received from a remote node. In this mode,
FLEXCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field
to ensure proper reception of its own message. Both transmit and receive interrupts are
generated.
• Module Disable Mode:

This low power mode is entered when the MDIS bit in the MCR Register is asserted and
the LPM_ACK is asserted by the FlexCAN. When disabled, the module requests to
disable the clocks to the CAN Protocol Engine and Controller Host Interface sub-
modules. Exit from this mode is done by negating the MDIS bit in the MCR Register. See
Module Disable Mode for more information.
• Stop Mode:
This low power mode is entered when Stop Mode is requested at Arm level and the
LPM_ACK bit in the MCR Register is asserted by the FlexCAN. When in Stop Mode,
the module puts itself in an inactive state and then informs the Arm that the clocks can be
shut down globally. Exit from this mode happens when the Stop Mode request is
removed or when activity is detected on the CAN bus and the Self Wake Up mechanism
is enabled. See Stop Mode for more information.

The FLEXCAN module has two I/O signals.
Table 26-1. FLEXCAN External Signals
FLEXCAN1_RX FLEXCAN receive pin. This pin is GPIO_8 ALT3 I
the receive pin from the CAN bus KEY_ROW2 ALT2
transceiver. Dominant state is
represented by logic level '0'. SD3_CLK ALT2
Recessive state is represented by
logic level '1'.
FLEXCAN1_TX FLEXCAN transmit pin. This pin is GPIO_7 ALT3 O
the transmit pin to the CAN bus KEY_COL2 ALT2
represented by logic level '0'. SD3_CMD ALT2
logic level '1'.
FLEXCAN2_RX FLEXCAN receive pin. This pin is KEY_ROW4 ALT0 I
the receive pin from the CAN bus SD3_DAT1 ALT2
represented by logic level '0'.
logic level '1'.
FLEXCAN2_TX FLEXCAN transmit pin. This pin is KEY_COL4 ALT0 O
the transmit pin to the CAN bus SD3_DAT0 ALT2
represented by logic level '0'.
logic level '1'.

Clocks
26.3 Clocks
The table found here describes the clock sources for FLEXCAN.
information.
Table 26-2. FLEXCAN Clocks
ipg_clk_chi ipg_clk_root CHI clock
ipg_clk_pe can_clk_root Protocol Engine clock
ipg_clk_pe_nogate can_clk_root Protocol Engine clock (no gating)
mem_ram_CLK ipg_clk_root RAM clock
26.4 Message Buffer Structure

Message Buffer Address: Base + 0x0080-0x047C.
The Message Buffer structure used by the FLEXCAN module is represented in the
following table.
Both Extended and Standard Frames (29-bit Identifier and 11-bit Identifier, respectively)
used in the CAN specification are represented.
Each individual Message buffer is formed by 16 bytes.
Table 26-3. Message Buffer Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0 CODE S I R DLC TIME STAMP
R T
D
R R
E
0x4 PRIO ID Standard ID Extended
0x8 DATA BYTE 0 DATA BYTE 1 DATA BYTE 2 DATA BYTE 3

0xC DATA BYTE 4 DATA BYTE 5 DATA BYTE 6 DATA BYTE 7
CODE - Message Buffer Code

This 4-bit field can be accessed (read or write) by the CPU and by the FLEXCAN
module itself, as part of the message buffer matching and arbitration process. The
encoding is shown in the following tables. See Functional Description for additional
information.
Table 26-4. Message Buffer Code for Rx buffers
CODE Description Rx Code SRV1 Rx Code RRS3 Comment
BEFORE AFTER
receive successfu
New l
Frame reception2
0b0000: INACTIVE- INACTIVE - - - MB does not participate in the matching
MB is not active. process.
0b0100: EMPTY - EMPTY - FULL - When a frame is received successfully (after
move-in process. Refer to Move-in for details),
MB is active and
the CODE field is automatically updated to
empty.
FULL.
0b0010: FULL - FULL Yes FULL - The act of reading the C/S word followed by
unlocking the MB (SRV) does not make the
MB is full.
code return to EMPTY. It remains FULL. If a
new frame is moved to the MB after the MB
was serviced, the code still remains FULL.
Refer to Matching Process for matching details
related to FULL code.
No OVERRUN - If the MB is FULL and a new frame is moved to
this MB before the CPU services it, the CODE
field is automatically updated to OVERRUN.
Refer to Matching Process for details about
overrun behavior.
0b0110: OVERRUN - OVERRUN Yes FULL - If the CODE field indicates OVERRUN and
MB is being overwritten CPU has serviced the MB, when a new frame
into a full buffer. is moved to the MB, the code returns to FULL.
No OVERRUN - If the CODE field already indicates OVERRUN,
and another new frame must be moved, the MB
will be overwritten again, and the code will
remain OVERRUN. Refer to Matching Process
for details about overrun behavior.
0b1010: RANSWER4 - RANSWER - TANSWER( 0 A Remote Answer was configured to recognize
A frame was configured 0b1110) a remote request frame received, after that a
to recognize a Remote MB is set to transmit a response frame. The
Request Frame and code is automatically changed to TANSWER
transmit a Response (0b1110). Refer to Matching Process for
Frame in return. details.
If CTRL2[RRS] is negated, transmit a response
frame whenever a remote request frame with
the same ID is received.
- 1 This code is ignored during matching and
arbitration process. Refer to Matching Process
for details.

Message Buffer Structure
Table 26-4. Message Buffer Code for Rx buffers (continued)

CODE Description Rx Code SRV1 Rx Code RRS3 Comment
BEFORE AFTER
receive successfu
New l
Frame reception2
CODE[0]=1b1: BUSY - BUSY5 - FULL - Indicates that the MB is being updated, it will be
FlexCAN is updating negated automatically and does not interfere on
OVERRUN -
the contents of the MB. the next CODE.
The CPU must not
access the MB.
1. SRV: Serviced MB. MB was read and unlocked by reading TIMER or other MB.
2. A frame is considered successful reception after the frame to be moved to MB (move-in process). Refer to Move-in for
details)
3. Remote Request Stored bit from CTRL2 register. Refer to CTRL2 for details.
4. Code 4'b1010 is not considered as a Tx and a MB with this code should not to be aborted.
5. Note that for Tx MBs, the BUSY bit should be ignored upon read, except when AEN bit is set in the MCR register. If this bit
is asserted, the corresponding MB does not participate in the matching process.
Table 26-5. Message Buffer Code for Tx buffers

CODE Description Tx Code MB Tx Code Comment
BEFORE tx RT AFTER
frame R successful
transmissio
n
0b1000: INACTIVE - INACTIVE - - MB does not participate in the arbitration process.
MB is not active
0b1001: ABORT - ABORT - - MB does not participate in the arbitration process.
MB is aborted
0b1100: DATA - DATA 0 INACTIVE Transmit data frame unconditionally once. After transmission, the
MB automatically returns to the INACTIVE state.
MB is a Tx Data
Frame (MB RTR
must be 0)
0b1100: REMOTE - REMOTE 1 EMPTY Transmit remote request frame unconditionally once. After
MB is a Tx Remote transmission, the MB automatically becomes an Rx Empty MB
Request Frame (MB with the same ID.
RTR must be 1)
0b1110: TANSWER TANSWER - RANSWER This is an intermediate code that is automatically written to the
- MB is a Tx MB by the CHI as a result of match to a remote request frame.
Response Frame The remote response frame will be transmitted unconditionally
from an incoming once and then the code will automatically return to RANSWER
Remote Request (0b1010). The CPU can also write this code with the same effect.
Frame
The remote response frame can be either a data frame or
another remote request frame depending on the RTR bit value.
Refer to Matching Process and Arbitration process for details.
SRR - Substitute Remote Request

Fixed recessive bit, used only in extended format. It must be set to '1' by the user for
transmission (Tx Buffers) and will be stored with the value received on the CAN bus for
Rx receiving buffers. It can be received as either recessive or dominant. If FLEXCAN
receives this bit as dominant, then it is interpreted as arbitration loss.
1= Recessive value is compulsory for transmission in Extended Format frames
0= Dominant is not a valid value for transmission in Extended Format frames
IDE - ID Extended Bit
This bit identifies whether the frame format is standard or extended. It is also used as part
of the reception filter.
1= Frame format is extended
0= Frame format is standard
RTR - Remote Transmission Request
This bit affects the behavior of Remote Frames and is part of the reception filter. Refer to
the tables above and RRS bit in Control 2 Register (FLEXCAN_CTRL2) for additional
details.
If FLEXCAN transmits this bit as '1' (recessive) and receives it as '0' (dominant), it is
interpreted as arbitration loss. If this bit is transmitted as '0' (dominant), then if it is
received as '1' (recessive), the FLEXCAN module treats it as bit error. If the value
received matches the value transmitted, it is considered as a successful bit transmission.
1= Indicates the current MB has a Remote Frame to be transmitted if MB is Tx. If the
MB is Rx then incoming Remote Request Frames may be stored.
0= Indicates the current MB has a Data Frame to be transmitted. In Rx MB it may be
considered in matching processes.
DLC - Length of Data in Bytes
This 4-bit field is the length (in bytes) of the Rx or Tx data, which is located in offset
0x08 through 0x0F of the MB space (see the first table above). In reception, this field is
written by the FLEXCAN module, copied from the DLC (Data Length Code) field of the
received frame. In transmission, this field is written by the Arm and corresponds to the
DLC field value of the frame to be transmitted. When RTR=1, the Frame to be
transmitted is a Remote Frame and does not include the data field, regardless of the
Length field. The DLC field indicates which DATA BYTEs are valid as shown in the
table below.
TIME STAMP - Free-Running Counter Time Stamp

Rx FIFO Structure
This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at
the time when the beginning of the Identifier field appears on the CAN bus.
PRIO - Local priority
This 3-bit field is only used when MCR[LPRIO_EN] bit is asserted and it only makes
sense for Tx mailboxes. These bits are not transmitted. They are appended to the regular
ID to define the transmission priority. See Arbitration process.
ID - Frame Identifier
In Standard Frame format, only the 11 most significant bits (28 to 18) are used for frame
identification in both receive and transmit cases. The 18 least significant bits are ignored.
In Extended Frame format, all bits are used for frame identification in both receive and
transmit cases.
DATA BYTE 0-7 - Data Field
Up to eight bytes can be used for a data frame.
For Rx frames, the data is stored as it is received from the CAN bus. DATA BYTE (n) is
valid only if n is less than DLC as shown in the table below.
For Tx frames, the CPU prepares the data field to be transmitted within the frame.
Table 26-6. DATA BYTEs validity
DLC Valid DATA BYTEs
0 none
1 DATA BYTE 0
2 DATA BYTE 0-1
3 DATA BYTE 0-2
4 DATA BYTE 0-3
5 DATA BYTE 0-4
6 DATA BYTE 0-5
7 DATA BYTE 0-6
8 DATA BYTE 0-7
26.5 Rx FIFO Structure

When the MCR[RFEN] bit is set, the memory area from 0x80 to 0xDC (which is
normally occupied by MBs 0 to 5) is used by the reception FIFO engine.

The region 0x80-0x8C contains the output of the FIFO which must be read by the CPU as
a Message Buffer. This output contains the oldest message received and not read yet. The
region 0x90-0xDC is reserved for internal use of the FIFO engine.
An additional memory area, that starts at 0xE0 and may extend up to 0x2DC (normally
occupied by MBs 6 up to 37) depending on the CTRL2[RFFN] field setting, contains the
ID Filter Table (configurable from 8 to 128 memory positions) that specifies filtering
criteria for accepting frames into the FIFO.Table 26-7 shows the Rx FIFO data structure.
Each ID Filter Table Element occupies an entire 32-bit word and can be compounded by
one, two or four Identifier Acceptance Filters (IDAF) depending on the MCR[IDAM]
field setting. Table 26-8, Table 26-9 and Table 26-10 show the IDAF indexation. Table
26-11 show the three different formats that the IDAF can assume, depending on the
MCR[IDAM] field setting. Note that all elements of the table must have the same format.
See Rx FIFO for more information.
Out of reset, the ID Filter Table flexible memory area defaults to 0xE0 and only extends
to 0xFC, which corresponds to MBs 6 to 7 for RFFN=0.
Table 26-7. Rx FIFO Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x80 S I R DLC TIME STAMP
R D T
R E R
0x84 ID Standard ID Extended
0x88 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3
0x8C Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
0x90 Reserved
to
0xDC
0xE0 ID Filter Table Element 0
0xE4 ID Filter Table Element 1
0xE8 ID Filter Table Elements 2 through 125
to
0x2D
4
0x2D ID Filter Table Element 126
8
0x2D ID Filter Table Element 127
C

Rx FIFO Structure
Table 26-8. Position of ID Filter Table Elements in format A

Element 31 0
0 IDAF0
1 IDAF1
2 Identifier Acceptance Filter 2 through 125
through
125
126 IDAF126
127 IDAF127
Table 26-9. Position of ID Filter Table Elements in format B

Element 31 16 15 0
0 IDAF0 IDAF1
1 IDAF2 IDAF3
through
125
126 IDAF252 IDAF253
127 IDAF254 IDAF255
Table 26-10. Position of ID Filter Table Elements in format C

Element 31 24 23 16 15 8 7 0
0 IDAF0 IDAF1 IDAF2 IDAF3
through
125
Table 26-11. Identifier Acceptance Filter Format A,B and C

Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A R ID RXIDA
T E
(Standard = 29-19, Extended = 29-1)
R
B R ID RXIDB_0 R ID RXIDB_1
T E T E
(Standard = 29-19, Extended = 29-16) (Standard = 13-3, Extended = 13-0)
R R
C RXIDC_0 RXIDC_1 RXIDC_2 RXIDC_3

Table 26-11. Identifier Acceptance Filter Format A,B and C

(Std/Ext = 31-24) (Std/Ext = 23-16) (Std/Ext = 15-8) (Std/Ext = 7-0)
RTR - Remote Frame

This bit specifies whether Remote Request Frames are accepted into the FIFO if they
match the target ID in Formats A and B. If Format C is chosen the acceptance does not
depend on whether the frame is a Remote Request Frame or not.
1= Remote Frames can be accepted and data frames are rejected
0= Remote Frames are rejected and data frames can be accepted
IDE - Extended Frame
Specifies if either Extended or Standard Format frames are accepted into the FIFO if they
match the target ID in Formats A and B. If Format C is chosen the acceptance does not
depend on whether the frame is of the Extended or Standard Format.
1= Extended frames can be accepted and standard frames are rejected
0= Extended frames are rejected and standard frames can be accepted
RXIDA - Rx Frame Identifier (Format A)
Specifies an ID to be used as acceptance criteria for the FIFO. In the Standard Format
(IDAF's or incoming frame's IDE bit is negated), only the 11 most significant bits (29 to
19 ) are used for frame identification. In the Extended Format (both IDAF's and incoming
frame's IDE are asserted), all bits are used.
RXIDB_0, RXIDB_1 - Rx Frame Identifier (Format B)
Specifies an ID to be used as acceptance criteria for the FIFO. In the Standard Format
(IDAF's or incoming frame's IDE bit is negated), the 11 most significant bits (29 to 19
and 13 to 3 ) are used for frame identification. In the Extended Format (both IDAF's and
incoming frame's IDE are asserted), all 14 bits of the field are compared with the 14 most
significant bits of the Identifier of the incoming frame. The 15 least significant bits of the
Identifier of an incoming Extended Format frame do not affect the acceptance.
RXIDC_0, RXIDC_1, RXIDC_2, RXIDC_3 - Rx Frame Identifier (Format C)
Specifies an ID to be used as acceptance criteria for the FIFO. In both Standard Format
and Extended Format, all 8 bits of the field are compared to the 8 most significant bits of
the Identifier of the incoming frame. The 3 least significant bits of the Identifier of an
incoming Standard Format frame and the 21 least significant bits of the Identifier of an
incoming Extended Format frame do not affect the acceptance.


26.6.1 Functional Overview

The FLEXCAN module is a CAN protocol engine with a very flexible mailbox system
for transmitting and receiving CAN frames. The mailbox system consists of a set of 64
Message Buffers (MB) that store configuration and control data, time stamp, message ID
and data (see Message Buffer Structure). The memory corresponding to the first 38 MBs
can be configured to support a FIFO reception scheme with a powerful ID filtering
mechanism, capable of checking incoming frames against a table of IDs (up to 128
extended IDs or 256 standard IDs or 512 8-bit ID slices), with individual mask register
for up to 32 ID Filter Table elements. Simultaneous reception through FIFO and mailbox
is supported. For mailbox reception, a matching algorithm makes it possible to store
received frames only into MBs that have the same ID. A masking scheme makes it
possible to match the ID programmed on the MB with a range of Identifiers on received
CAN frames. For transmission, an arbitration algorithm decides the prioritization of MBs
to be transmitted based on the message ID (optionally augmented by 3 local priority bits)
or the MB ordering.
Before proceeding with the functional description, an important concept must be
explained. A Message Buffer is said to be "active" at a given time if it can participate in
both the Matching and Arbitration processes. An Rx MB with a 0b0000 code is inactive
(refer to Table 26-4). Similarly, a Tx MB with a 0b1000 or 0b1001 code is also inactive
(refer to Table 26-5).
26.6.2 Transmit Process

In order to transmit a CAN frame, the CPU must prepare a Message Buffer for
transmission by executing the procedure found here.
1. Check if the respective interruption bit is set and clear it.
2. If the MB is active (transmission pending), write the ABORT code (0b1001) to the
CODE field of the Control and Status word to request an abortion of the
transmission. Wait for the corresponding IFLAG to be asserted by polling the IFLAG
register or by the interrupt request if enabled by the respective IMASK. Then read
back the CODE field to check if the transmission was aborted or transmitted (see
Transmission Abort Mechanism). If backwards compatibility is desired (MCR[AEN]
bit negated), just write the INACTIVE code (0b1000) to the CODE field to inactivate
the MB but then the pending frame may be transmitted without notification (see
Message Buffer Inactivation).
3. Write the ID word.
4. Write the data bytes.
5. Write the DLC, Control and Code fields of the Control and Status word to activate
the MB.
Once the MB is activated, it will participate into the arbitration process and eventually be
transmitted according to its priority.
At the end of the successful transmission, the value of the Free Running Timer at the time
of the second bit of frame's Identifier field is written into the MB's Time Stamp field, the
CODE field in the Control and Status word is updated, the CRC Register is updated, a
status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by
the corresponding Interrupt Mask Register bit. The new CODE field after transmission
depends on the code that was used to activate the MB in step four (see Table 26-4 and
Table 26-5 in Message Buffer Structure).
When the Abort feature is enabled (MCR[AEN] bit is asserted), after the Interrupt Flag is
asserted for a Mailbox configured as transmit buffer, the Mailbox is blocked, therefore
the CPU is not able to update it until it negates the Interrupt Flag. It means that the CPU
must clear the corresponding IFLAG before starting to prepare this MB for a new
transmission or reception.
26.6.3 Arbitration process

The arbitration process scans the Mailboxes searching the Tx one that holds the message
to be sent in the next opportunity. This Mailbox is called the arbitration winner.
The scan starts from the lowest Mailbox number and runs toward the higher ones.
The arbitration process is triggered in the following events:
• From the CRC field of the CAN frame. The start point depends on the
CTRL2[TASD] field value. See Control 2 Register (FLEXCAN_CTRL2) for details.
• During the error delimiter field of the CAN frame
• During the Overload Delimiter field of a CAN frame.
• When the winner is inactivated and the CAN bus has still not reached the first bit of
the Intermission field.
• When Arm write to the C/S word of a winner MB and the CAN bus has still not
reached the first bit of the Intermission field.
• When CHI is in Idle state and Arm writes to the C/S word of any MB.

• When FlexCAN exits Bus Off state

• Upon leaving Freeze Mode or Low Power Mode
If the arbitration process does not manage to evaluate all Mailboxes before the CAN bus
has reached the first bit of the Intermission field the temporary arbitration winner is
invalidated and the FlexCAN will not compete for the CAN bus in the next opportunity.
The arbitration process selects the winner among the active Tx Mailboxes at the end of
the scan according to both CTRL1[LBUF] and MCR[LPRIO_EN] bits settings.
26.6.3.1 Lowest Mailbox number first

If CTRL1[LBUF] bit is asserted the first (lowest number) active Tx Mailbox found is the
arbitration winner. MCR[LPRIO_EN] bit has no effect when CTRL1[LBUF] is asserted.
26.6.3.2 Highest Mailbox priority first

If CTRL1[LBUF] bit is negated then the arbitration process searches the active Tx
Mailbox with the highest priority, and this Mailbox would have a higher probability to
win the arbitration on CAN bus.
The sequence of bits considered for this arbitration is called the arbitration value of the
Mailbox. The highest priority Tx Mailbox is the one that has the least arbitration value
among all Tx Mailboxes.
If two or more Mailboxes have equivalent arbitration values the lowest Mailbox number
is the arbitration winner.
The composition of the arbitration value depends on MCR[LPRIO_EN] bit setting.
26.6.3.2.1 Local Priority disabled

If MCR[LPRIO_EN] bit is negated the arbitration value is built in the exact sequence of
bits as they would be transmitted in a CAN frame (see Table 26-12) in such a way that
the Local Priority is disabled.
Table 26-12. Composition of the arbitration value when Local Priority is disabled
Format Mailbox Arbitration Value (32 bits)
Standard Standard ID RTR IDE - -
(IDE = 0) (11 bits) (1 bit) (1 bit) (18 bits) (1 bit)
Extended Extended ID[28:18 ] SRR IDE Extended ID[17:0 ] RTR

26.6.3.2.2 Local Priority enabled

If Local Priority is desired MCR[LPRIO_EN] must be asserted.
In this case the Mailbox PRIO field is included at the very left of the arbitration value
(see the table below).
Table 26-13. Composition of the arbitration value when Local Priority is enabled
Format Mailbox Arbitration Value (35 bits)
Standard PRIO Standard ID RTR IDE - -
(IDE = 0) (3 bits) (11 bits) (1 bit) (1 bit) (18 bits) (1 bit)
Extended PRIO Extended ID[28:18 ](11 bits) SRR IDE Extended ID[17:0 ] RTR
As the PRIO field is the most significant part of the arbitration value Mailboxes with low
PRIO values have higher priority than Mailboxes with high PRIO values regardless the
rest of their arbitration values.
Note that the PRIO field is not part of the frame on the CAN bus. Its purpose is only to
affect the internal arbitration process.
Once the arbitration winner is found, its content is copied to a hidden auxiliary MB called
Tx Serial Message Buffer (Tx SMB), which has the same structure as a normal MB but is
not user accessible. This operation is called "move-out" and after it is done, write access
to the corresponding MB is blocked (if the AEN bit in MCR is asserted). The write
access is released in the following events:
• After the MB is transmitted
• FlexCAN enters in Freeze Mode or Bus Off
• FlexCAN loses the bus arbitration or there is an error during the transmission
At the first opportunity window on the CAN bus, the message on the Tx SMB is
transmitted according to the CAN protocol rules. FlexCAN transmits up to eight data
bytes, even if the DLC (Data Length Code) field value is greater than that.
Arbitration process can be triggered in the following situations:
• During Rx and Tx frames from CAN CRC field to end of frame. Arbitration start
point depends on instantiation parameters NUMBER_OF_MB and TASD.
Additionally, TASD value may be changed (see Control 2 Register
(FLEXCAN_CTRL2)) to optimize the arbitration start point.
• During CAN Bus Off state from TX_ERR_CNT=124 to 128. Arbitration start point
depends on instantiation parameters NUMBER_OF_MB and TASD. Additionally,

TASD value may be changed(see Control 2 Register (FLEXCAN_CTRL2)) to

optimize the arbitration start point.
• During C/S write by CPU in Bus Idle. First C/S write starts arbitration process and a
second C/S write during this same arbitration restarts the process. If other C/S writes
are performed, Tx arbitration process is pending. If there is no arbitration winner
after arbitration process has finished, then TX arbitration machine begins a new
arbitration process.
• Arbitration winner deactivation during a valid arbitration window.
• Upon Leave Freeze Mode. If there is a re-synchronization during WaitForBusIdle
arbitration process is restarted.
Arbitration process stops in the following situation:
• All Mailboxes were scanned.
• A Tx active Mailbox is found in case of Lowest Buffer feature enabled.
• Arbitration winner inactivation or abort during any arbitration process.
• There was not enough time to finish Tx arbitration process. For instance, a
deactivation was performed near the end of frame). In this case arbitration process is
pending.
• Error or Overload flag in the bus.
• Low Power or Freeze Mode request in Idle state
Arbitration is considered pending as described below:
• It was not possible to finish arbitration process in time.
• C/S write during arbitration if write is performed in a MB which number is lower
than the Tx arbitration pointer.
• Any C/S write if there is no Tx Arbitration process in progress.
• Rx Match has just updated a Rx Code to Tx Code.
• Entering Bus off state.
C/S write during arbitration has the following effect:
• If C/S write is performed in the arbitration winner, a new process is restarted
immediately.
• C/S write during arbitration if write is performed in a MB which number is higher
than the Tx arbitration pointer.
26.6.4 Receive Process

To be able to receive CAN frames into a Mailbox, the CPU must prepare it for reception
by executing the steps listed here.

1. If the Mailbox is active (either Tx or Rx) inactivate the Mailbox (see Message Buffer
Inactivation), preferably with a safe inactivation (see Transmission Abort
Mechanism);
2. Write the ID word;
3. Write the EMPTY code (0b0100) to the CODE field of the Control and Status word
to activate the Mailbox.
Once the Mailbox is activated in the third step, it will be able to receive frames that
match the programmed filter. At the end of a successful reception, the Mailbox is updated
by the move-in process (see Move-in) as follows:
1. The received Data field (8 bytes at most) is stored;
2. The received Identifier field is stored;
3. The value of the Free Running Timer at the time of the second bit of frame's
Identifier field is written into the Mailbox Time Stamp field;
4. The received SRR, IDE, RTR and DLC fields are stored;
5. The CODE field in the Control and Status word is updated. (see Table 26-4 and
Table 26-5 in Section Message Buffer Structure)
6. A status flag is set in the Interrupt Flag Register and an interrupt is generated if
allowed by the corresponding Interrupt Mask Register bit.
The recommended way for the CPU servicing (read) the frame received in a Mailbox is
using the following procedure:
1. Read the Control and Status word of that Mailbox;
2. Check if the BUSY bit is deasserted, indicating that the Mailbox is locked. Repeat
step 1) while it is asserted. See Message Buffer Lock Mechanism;
3. Read the contents of the Mailbox. Once Mailbox is locked now, its contents won't be
modified by FlexCAN Move-in processes. See Move-in;
4. Acknowledge the proper flag at IFLAG registers;
5. Read the Free Running Timer. It is optional but recommended to unlock Mailbox as
soon as possible and make it available for reception.
The CPU should synchronize to frame reception by the status flag bit for the specific
Mailbox in one of the IFLAG Registers and not by the CODE field of that Mailbox.
Polling the CODE field does not work because once a frame was received and the CPU
services the Mailbox (by reading the C/S word followed by unlocking the Mailbox), the
CODE field will not return to EMPTY. It will remain FULL. If the CPU tries to
workaround this behavior by writing to the C/S word to force an EMPTY code after
reading the Mailbox without a prior safe inactivation, a newly received message
matching the filter of that Mailbox may be lost.
In summary: never do polling by reading directly the C/S word of the Mailboxes. Instead,
read the IFLAG registers.

Note that the received frame's Identifier field is always stored in the matching Mailbox,
thus the contents of the ID field in a Mailbox may change if the match was due to
masking. Note also that FlexCAN does receive frames transmitted by itself if there exists
a matching Rx Mailbox, provided the MCR[SRX_DIS] bit is not asserted. If
MCR[SRX_DIS] bit is asserted, FlexCAN will not store messages transmitted by itself in
any MB, even if it contains a matching MB, and no interrupt flag or interrupt signal will
be generated due to the frame reception.
To be able to receive CAN messages through the Rx FIFO, the CPU must enable and
configure the Rx FIFO during Freeze Mode(see Rx FIFO). Upon receiving the Frames
Available in Rx FIFO interrupt(see Interrupt Masks 1 Register (FLEXCAN_IMASK1),
bit IFLAG[BUF5I] - Frames available in Rx FIFO), the CPU should service the received
frame using the following procedure:
1. Read the Control and Status word (optional - needed only if a mask was used for IDE
and RTR bits);
2. Read the ID field (optional - needed only if a mask was used);
3. Read the Data field;
4. Read the RXFIR register (optional);
5. Clear the Frames Available in Rx FIFO interrupt by writing 1 to IFLAG[BUF5I] bit
(mandatory - releases the MB and allows the CPU to read the next Rx FIFO entry)
26.6.5 Matching Process

The matching process scans the MB memory looking for Rx MBs programmed with the
same ID as the one received from the CAN bus. If the FIFO is enabled, the priority of
scanning can be selected between Mailboxes and FIFO filters. In any case, the matching
starts from the lowest number Message Buffer toward the higher ones. If no match is
found within the first structure then the other is scanned subsequently. In the event that
the FIFO is full, the matching algorithm will always look for a matching MB outside the
FIFO region.
As the frame is being received, it is stored in a hidden auxiliary MB called Rx Serial
Message Buffer (Rx SMB).
The matching process start point depends on the following conditions:
• if the received frame is a remote frame, the start point is the CRC field of the frame;
• if the received frame is a data frame with DLC field equal to zero, the start point is
the CRC field of the frame;
• if the received frame is a data frame with DLC field different than zero, the start
point is the DATA field of the frame;

If a matching ID is found in the FIFO table or in one of the Mailboxes, the contents of the
SMB will be transferred to the FIFO or to the matched Mailbox by the move-in process.
If any CAN protocol error is detected then no match results will be transferred to the
FIFO or to the matched Mailbox at the end of reception.
The matching process scans all matching elements of both Rx FIFO (if enabled) and
active Rx Mailboxes (CODE is EMPTY, FULL, OVERRUN or RANSWER) in search of
a successful comparison with the matching elements of the Rx SMB that is receiving the
frame on the CAN bus. The SMB has the same structure of a Mailbox. The reception
structures (Rx FIFO or Mailboxes) associated with the matching elements that had a
successful comparison are the matched structures. The matching winner is selected at the
end of the scan among those matched structures and depends on conditions described
ahead. Refer to the following table for details.
Table 26-14. Matching architecture
Structure SMB[RTR] CTRL2[RRS] CTRL2[EACEN] MB[IDE] MB[RTR] MB[ID]1 MB[CODE]
Mailbox 0 - 0 cmp2 no_cmp3 cmp_msk4 EMPTY or
FULL or
OVERRUN
Mailbox 0 - 1 cmp_msk cmp_msk cmp_msk EMPTY or
FULL or
OVERRUN
Mailbox 1 0 - cmp no_cmp cmp RANSWER
Mailbox 1 1 0 cmp no_cmp cmp_msk EMPTY or
FULL or
OVERRUN
Mailbox 1 1 1 cmp_msk cmp_msk cmp_msk EMPTY or
FULL or
OVERRUN
FIFO5 - - - cmp_msk cmp_msk cmp_msk -
1. For Mailbox structure, If SMB[IDE] is asserted, the ID is 29 bits (ID Standard + ID Extended). In case of SMB[IDE] to be
negated, the ID is only 11 bits (ID Standard). Please, refer to Message Buffer Structure for ID details. For FIFO structure,
the ID depends on IDAM. Please, refer to Rx FIFO Structure for IDAM details.
2. cmp: Compares the SMB contents with the MB contents regardless the masks.
3. no_cmp: The SMB contents are not compared with the MB contents.
4. cmp_msk: Compares the SMB contents with MB contents taking into account the masks.
5. SMB[IDE] and SMB[RTR] are not taken into account when IDAM is type C.
A reception structure is free-to-receive when any of the following conditions is satisfied:

• the CODE field of the Mailbox is EMPTY;
• the CODE field of the Mailbox is either FULL or OVERRUN and it has already been
serviced (the C/S word was read by the Arm and unlocked as described in Message
Buffer Lock Mechanism);

• the CODE field of the Mailbox is either FULL or OVERRUN and an inactivation is
performed. (see Message Buffer Inactivation)
• the Rx FIFO is not full.
The scan order for Mailboxes and Rx FIFO is from the matching element with lowest
number to the higher ones.
The matching winner search for Mailboxes is affected by the MCR[IRMQ] bit. If it is
negated the matching winner is the first matched Mailbox regardless if it is free-to-
receive or not . If it is asserted, the matching winner is selected according to the priority
below:
1. the first free-to-receive matched Mailbox;
2. the last non free-to-receive matched Mailbox.
It is possible to select the priority of scan between Mailboxes and Rx FIFO by the
CTRL2[MRP] bit.
If the selected priority is Rx FIFO first:
• if the Rx FIFO is a matched structure and is free-to-receive then the Rx FIFO is the
matching winner regardless of the scan for Mailboxes;
• otherwise (the Rx FIFO is not a matched structure or is not free-to-receive), then the
matching winner is searched among Mailboxes as described above.
If the selected priority is Mailboxes first:
• if a free-to-receive matched Mailbox is found, it is the matching winner regardless
the scan for Rx FIFO;
• if no matched Mailbox is found, then the matching winner is searched in the scan for
the Rx FIFO;
• if both conditions above are not satisfied and a non free-to-receive matched Mailbox
is found then the matching winner determination is conditioned by the MCR[IRMQ]
bit:
• if MCR[IRMQ] bit is negated the matching winner is the first matched Mailbox;
• if MCR[IRMQ] bit is asserted the matching winner is the Rx FIFO if it is a free-
to-receive matched structure, otherwise the matching winner is the last non free-
to-receive matched Mailbox.
Please, refer to the table below for a summary of matching possibilities.
If a non-safe Mailbox inactivation (see Message Buffer Inactivation) occurs during
matching process and the Mailbox inactivated is the temporary matching winner then the
temporary matching winner is invalidated. The matching elements scan is not stopped nor

restarted, it continues normally. The consequence is that the current matching process
works as if the matching elements compared before the inactivation did not exist,
therefore a message may be lost.
Suppose, for example, that the FIFO is disabled, IRMQ is enabled and there are two MBs
with the same ID, and FlexCAN starts receiving messages with that ID. Let us say that
these MBs are the second and the fifth in the array. When the first message arrives, the
matching algorithm will find the first match in MB number 2. The code of this MB is
EMPTY, so the message is stored there. When the second message arrives, the matching
algorithm will find MB number 2 again, but it is not "free-to-receive", so it will keep
looking and find MB number 5 and store the message there. If yet another message with
the same ID arrives, the matching algorithm finds out that there are no matching MBs
that are "free-to-receive", so it decides to overwrite the last matched MB, which is
number 5. In doing so, it sets the CODE field of the MB to indicate OVERRUN.
Table 26-15. Matching Possibilities and Resulting Reception Structures
RFEN IRMQ MRP Matched in MB Matched in Reception Description
FIFO Structure
No FIFO, only MB, match is always MB first
0 0 X1 None2 -3 None Frame lost by no match
0 0 X Free4 - FirstMB
0 1 X None - None Frame lost by no match
0 1 X Free - FirstMB
0 1 X NotFree - LastMB Overrun
FIFO enabled, no match in FIFO is as if FIFO does not exist
1 0 X None None5 None Frame lost by no match
1 0 X Free None FirstMB
1 1 X None None None Frame lost by no match
1 1 X Free None FirstMB
1 1 X NotFree None LastMB Overrun
FIFO enabled, Queue disabled
1 0 0 X NotFull6 FIFO
1 0 0 None Full7 None Frame lost by FIFO full (FIFO Overflow)
1 0 0 Free Full FirstMB
1 0 0 NotFree Full FirstMB
1 0 1 None NotFull FIFO
1 0 1 None Full None Frame lost by FIFO full (FIFO Overflow)
1 0 1 Free X FirstMB
1 0 1 NotFree X FirtsMB Overrun
FIFO enabled, Queue enabled
1 1 0 X NotFull FIFO
1 1 0 None Full None Frame lost by FIFO full (FIFO Overflow)

Table 26-15. Matching Possibilities and Resulting Reception Structures

(continued)
RFEN IRMQ MRP Matched in MB Matched in Reception Description
FIFO Structure
1 1 0 Free Full FirstMB
1 1 0 NotFree Full LastMB Overrun
1 1 1 None NotFull FIFO
1 1 1 Free X FirstMB
1 1 1 NotFree NotFull FIFO
1 1 1 NotFree Full LastMB Overrun
1. It is a don't care condition.

2. Matched in MB "None" means that the frame has not matched any MB (free-to-receive or non-free-to-receive).
3. It is a forbidden condition.
4. Matched in MB "Free" means that the frame matched at least one MB free-to-receive regardless it has matched MBs non-
free-to-receive.
5. Matched in FIFO "None" means that the frame has not matched any filter in FIFO. It is as the FIFO didn't exist
(CTRL2[RFEN]=0).
6. Matched in FIFO "NotFull" means that the frame has matched a FIFO filter and has empty slots to receive it.
7. Matched in FIFO "Full" means that the frame has matched a FIFO filter but couldn't store it because it has no empty slots
to receive it.
The ability to match the same ID in more than one MB can be exploited to implement a
reception queue (in addition to the full featured FIFO) to allow more time for Arm to
service the MBs. By programming more than one MB with the same ID, received
messages will be queued into the MBs. Arm can examine the Time Stamp field of the
MBs to determine the order in which the messages arrived.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN
supports individual masking per MB. Please refer to Rx Mailboxes Global Mask Register
(FLEXCAN_RXMGMASK). During the matching algorithm, if a mask bit is asserted,
then the corresponding ID bit is compared. If the mask bit is negated, the corresponding
ID bit is "don't care". Please note that the Individual Mask Registers are implemented in
RAM, so they are not initialized out of reset. Also, they can only be programmed while
the module is in Freeze Mode,, otherwise they are blocked by hardware.
FlexCAN also supports an alternate masking scheme with only four mask registers
(RGXMASK, RX14MASK, RX15MASK and RXFGMASK) for backward
compatibility. This alternate masking scheme is enabled when the IRMQ bit in the MCR
Register is negated.
26.6.6 Move Process

There are two types of move process, namely move-in and move-out.

26.6.6.1 Move-in
The move-in process is the copy of a message received by an Rx SMB to a Rx Mailbox
or FIFO that has matched it. If the move destination is the Rx FIFO, attributes of the
message are also copied to the RXFIR FIFO. Each Rx SMB has its own move-in process,
but only one is performed at a given time as described ahead. The move-in starts only
when the message held by the Rx SMB has a corresponding matching winner (see
Matching Process) and all of the following conditions are true:
• the CAN bus has reached or let past either:
• the second bit of Intermission field next to the frame that carried the message
that is in the Rx SMB;
• the first bit of an overload frame next to the frame that carried the message that
is in the Rx SMB;
• there is no ongoing matching process;
• the destination Mailbox is not locked by Arm;
• there is no ongoing move-in process from another Rx SMB. If more than one move-
in processes are to be started at the same time both are performed and the newest
substitutes the oldest.
The term pending move-in is used throughout the document and stands for a move-to-be
that still does not satisfy all of the aforementioned conditions.
The move-in is cancelled and the Rx SMB is able to receive another message if any of
the following conditions is satisfied:
• the destination Mailbox is inactivated after the CAN bus has reached the first bit of
Intermission field next to the frame that carried the message and its matching process
has finished;
• there is a previous pending move-in to the same destination Mailbox.
• the Rx SMB is receiving a frame transmitted by the FlexCAN itself and the self-
reception is disabled;
• any CAN protocol error is detected.
Note that the pending move-in is not cancelled if the module enters in Freeze or Low
Power Mode. It only stays on hold waiting for exiting Low Power Mode and to be
unlocked. If an MB is unlocked during Freeze Mode, the move-in happens immediately.
The move-in process consists of the following steps:
1. if the message is destined to the Rx FIFO, push IDHIT into the RXFIR FIFO;
2. reads the words DATA0-3 and DATA4-7 from the Rx SMB;
3. writes it in the words DATA0-3 and DATA4-7 of the Rx Mailbox;

4. reads the words Control/Status and ID from the Rx SMB;

5. writes it in the words Control/Status and ID of the Rx Mailbox, updating the CODE
field according to Table 26-4.
The move-in process is not atomic, in such a way that it is immediately cancelled by the
inactivation of the destination Mailbox (see Message Buffer Inactivation) and in this case
the Mailbox may be left partially updated, thus incoherent. The exception is if the move-
in destination is an Rx FIFO Message Buffer, then the process cannot be cancelled.
The BUSY Bit (least significant bit of the CODE field) of the destination Message Buffer
is asserted while the move-in is being performed in such a way that Arm beware that the
Message Buffer content is temporarily incoherent.
26.6.6.2 Move-out
The move-out process is the copy of the content from a Tx Mailbox to the Tx SMB when
a message for transmission is available (see Arbitration process). The move-out occurs in
the following conditions:
• the first bit of Intermission field;
• during Bus off field when TX Error Counter is in the 124 to 128 range;
• during BusIdle field;
• during Wait For Bus Idle field.
The move-out process is not atomic. Only Arm has priority to access the memory
concurrently out of BusIdle state. In BusIdle, the move-out has the lowest priority to the
concurrent memory accesses.
26.6.7 Data Coherence

In order to maintain data coherency and FlexCAN proper operation, the Arm must obey
the rules described in the Transmit Process and Receive Process.
Any form of Arm accessing an MB structure within FlexCAN other than those specified
may cause FlexCAN to behave in an unpredictable way.
26.6.7.1 Transmission Abort Mechanism

The abort mechanism provides a safe way to request the abortion of a pending
transmission. A feedback mechanism is provided to inform Arm if the transmission was
aborted or if the frame could not be aborted and was transmitted instead.

In order to abort a transmission, Arm must write a specific abort code (0b1001) to the
CODE field of the Control and Status word. The active MBs configured as transmission
must be aborted first and then they may be updated. If the abort code is written to a
Mailbox that is currently being transmitted, or to a Mailbox that was already loaded into
the SMB for transmission, the write operation is blocked and the MB is kept active, but
the abort request is captured and kept pending until one of the following conditions are
satisfied:
• The module loses the bus arbitration
• There is an error during the transmission
• The module is put into Freeze Mode
• The module enters in BusOff state
• There is an overload frame
If none of conditions above are reached, the MB is transmitted correctly, the interrupt
flag is set in the IFLAG register and an interrupt to the Arm is generated (if enabled). The
abort request is automatically cleared when the interrupt flag is set. In the other hand, if
one of the above conditions is reached, the frame is not transmitted, therefore the abort
code is written into the CODE field, the interrupt flag is set in the IFLAG and an interrupt
is (optionally) generated to Arm.
If Arm writes the ABORT code before the transmission begins internally, then the write
operation is not blocked, therefore the MB is updated and the interrupt flag is set. In this
way Arm just needs to read the abort code to make sure the active MB was safely
inactivated. Although the AEN bit is asserted and Arm wrote the abort code, in this case
the MB is inactivated and not aborted, because the transmission did not start yet. One
Mailbox is only aborted when the abort request is captured and kept pending until one of
the previous conditions are satisfied.
The abort procedure can be summarized as follows:
1. Arm checks the corresponding IFLAG and clears it, if asserted.
2. Arm writes 0b1001 into the CODE field of the C/S word.
3. Arm waits for the corresponding IFLAG indicating that the frame was either
transmitted or aborted.
4. Arm reads the CODE field to check if the frame was either transmitted
(CODE=0b1000) or aborted (CODE=0b1001).
5. It is necessary to clear the corresponding IFLAG in order to allow the MB to be
reconfigured.

26.6.7.2 Message Buffer Inactivation

Inactivation is a mechanism provided to protect the Mailbox against updates by the
FlexCAN internal processes, thus allowing Arm to rely on Mailbox data coherence after
having updated it, even in Normal Mode.
If a Mailbox is inactivated it does not participate neither in the arbitration nor in the
matching process until it is reactivated. See Transmit Process and Receive Process for
more detailed instruction on how to inactivate and reactivate a Mailbox.
In order to inactivate a Mailbox Arm must update its CODE field to INACTIVE (either
0b0000 or 0b1000).
As the user is not able to synchronize the CODE field update with the FlexCAN internal
processes an inactivation can lead to undesirable results:
• a frame in the bus that matches the filtering of the inactivated Rx Mailbox may be
lost without notice, even if there are other Mailboxes with the same filter;
• a frame containing the message within the inactivated Tx Mailbox may be
transmitted without notice.
In order to eliminate such risk and perform a safe inactivation Arm must use the
following mechanism along with the inactivation itself:
• for Tx Mailboxes, the Transmission Abort (see Transmission Abort Mechanism);
The inactivation automatically unlocks the Mailbox (see Message Buffer Lock
Mechanism).
Message Buffers that are part of the Rx FIFO cannot be inactivated. There is no write
protection on FIFO region by FlexCAN. Arm must keep the data coherence into FIFO
region when RFEN is asserted.
26.6.7.3 Message Buffer Lock Mechanism

Besides MB inactivation, FlexCAN has another data coherence mechanism for the
receive process. When Arm reads the Control and Status word of an Rx MB with codes
FULL or OVERRUN, FlexCAN assumes that Arm wants to read the whole MB in an
atomic operation, and thus it sets an internal lock flag for that MB. The lock is released
when Arm reads the Free Running Timer (global unlock operation), or when it reads the
Control and Status word of another MB regardless of its code or when Arm writes into
C/S word from locked MB. The MB locking is done to prevent a new frame to be written
into the MB while Arm is reading it.

The locking mechanism only applies to Rx MBs that are not part of FIFO and have a
code different than INACTIVE (0b0000) or EMPTY1 (0b0100). Also, Tx MBs can not
be locked.
Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the
array are programmed with the same ID, and FlexCAN has already received and stored
messages into these two MBs. Suppose now that the Arm decides to read MB number 5
and at the same time another message with the same ID is arriving. When Arm reads the
Control and Status word of MB number 5, this MB is locked. The new message arrives
and the matching algorithm finds out that there are no "free-to-receive" MBs, so it
decides to override MB number 5. However, this MB is locked, so the new message can
not be written there. It will remain in the SMB waiting for the MB to be unlocked, and
only then will be written to the MB. If the MB is not unlocked in time and yet another
new message with the same ID arrives, then the new message overwrites the one on the
SMB and there will be no indication of lost messages either in the CODE field of the MB
or in the Error and Status Register.
While the message is being moved-in from the SMB to the MB, the BUSY bit on the
CODE field is asserted. If Arm reads the Control and Status word and finds out that the
BUSY bit is set, it should defer accessing the MB until the BUSY bit is negated.
If the BUSY bit is asserted or if the MB is empty, then reading the Control and Status
word does not lock the MB.
Inactivation takes precedence over locking. If Arm inactivates a locked Rx Mailbox, then
its lock status is negated and the Mailbox is marked as invalid for the current matching
round. Any pending message on the SMB will not be transferred anymore to the
Mailbox.An MB is unlocked when Arm reads the Free Running Timer Register (see Free
Running Timer Register (FLEXCAN_TIMER)), or the C/S word of another MB.
Lock and unlock mechanisms have the same functionality in both Normal and Freeze
modes.
An unlock during Normal or Freeze mode results in the move-in of the pending message.
However, the move-in is postponed if an unlock occurs during any of the low power
modes (see in Modes of Operation specific information on Module Disable or Stop
modes) and it will take place only when the module resumes to Normal or Freeze modes.
26.6.8 Rx FIFO
The receive-only FIFO is enabled by asserting the RFEN bit in the MCR.
1. In previous FlexCAN versions, reading the C/S word locks the MB even if it is EMPTY. This behavior is maintained when
the IRMQ bit is negated.

The reset value of this bit is zero to maintain software backward compatibility with
previous versions of the module that did not have the FIFO feature. The FIFO is 6-
message deep, therefore when the FIFO is enabled, the memory region occupied by the
first 6 Message Buffers is reserved for use of the FIFO engine (see Rx FIFO Structure).
Arm can read the received messages sequentially, in the order they were received, by
repeatedly reading a Message Buffer structure at the output of the FIFO.
The IFLAG[BUF5I] (Frames available in Rx FIFO) is asserted when there is at least one
frame available to be read from the FIFO. An interrupt is generated if it is enabled by the
corresponding mask bit. Upon receiving the interrupt, Arm can read the message
(accessing the output of the FIFO as a Message Buffer) and the RXFIR register and then
clear the interrupt. If there are more messages in the FIFO the act of clearing the interrupt
updates the output of the FIFO with the next message and update the RXFIR with the
attributes of that message, reissuing the interrupt to Arm. Otherwise, the flag remains
negated. The output of the FIFO is only valid when the IFLAG[BUF5I] is asserted.
The IFLAG[BUF6I] (Rx FIFO Warning) is asserted when the number of unread
messages within the Rx FIFO is increased to 5 from 4 due to the reception of a new one,
meaning that the Rx FIFO is almost full. The flag remains asserted until Arm clears it.
The IFLAG[BUF7I] (Rx FIFO Overflow) is asserted when an incoming message was lost
because the Rx FIFO is full. Note that the flag will not be asserted when the Rx FIFO is
full and the message was captured by a Mailbox. The flag remains asserted until the Arm
clears it.
Clearing one of those three flags does not affect the state of the other two.
An interrupt is generated if an IFLAG bit is asserted and the corresponding mask bit is
asserted too.
A powerful filtering scheme is provided to accept only frames intended for the target
application, thus reducing the interrupt servicing work load. The filtering criteria is
specified by programming a table of up to 128 32-bit registers, according to
CTRL2[RFFN] setting, that can be configured to one of the following formats (see also
Rx FIFO Structure):
• Format A: 128 IDAFs (extended or standard IDs including IDE and RTR)
• Format B: 256 IDAFs (standard IDs or extended 14-bit ID slices including IDE and
RTR)
• Format C: 512 IDAFs (standard or extended 8-bit ID slices)
Every frame available in the FIFO has a corresponding IDHIT (Identifier Acceptance
Filter Hit Indicator) that can be read by accessing the RXFIR register. The
RXFIR[IDHIT] field refers to the message at the output of the FIFO and is valid whilst

the IFLAG[BUF5I] flag is asserted. The RXFIR register must be read only before
clearing the flag, which guarantees that the information refers to the correct frame within
the FIFO.
Up to thirty two elements of the ID Filter Table are individually affected by the
Individual Mask Registers (RXIMR0 - RXIMR31), according to CTRL2[RFFN] setting
(refer to Control 2 Register (FLEXCAN_CTRL2)), allowing very powerful filtering
criteria to be defined. If the MCR[IRMQ] bit is negated (or if the RXIMR are not
available for the particular MCU), then the FIFO ID Filter Table is affected by
RXFGMASK.
26.6.9 CAN Protocol Related Features
26.6.9.1 Remote Frames

Remote frame is a special kind of frame. The user can program a mailbox to be a Remote
Request Frame by writing the mailbox as Transmit with the RTR bit set to '1'. After the
remote request frame is transmitted successfully, the mailbox becomes a Receive
Message Buffer, with the same ID as before.
When a remote request frame is received by FlexCAN, it can be treated in three ways,
depending on Remote Request Storing (CTRL2[RRS]) and Rx FIFO Enable
(MCR[RFEN]) bits:
• If RRS is negated the frame's ID is compared to the IDs of the Transmit Message
Buffers with the CODE field 0b1010. If there is a matching ID, then this mailbox
frame will be transmitted. Note that if the matching mailbox has the RTR bit set, then
FlexCAN will transmit a remote frame as a response. The received remote request
frame is not stored in a receive buffer. It is only used to trigger a transmission of a
frame in response. The mask registers are not used in remote frame matching, and all
ID bits (except RTR) of the incoming received frame should match. In the case that a
remote request frame was received and matched a mailbox, this message buffer
immediately enters the internal arbitration process, but is considered as normal Tx
mailbox, with no higher priority. The data length of this frame is independent of the
DLC field in the remote frame that initiated its transmission.
• If RRS is asserted the frame's ID is compared to the IDs of the receive mailboxes
with the CODE field 0b0100, 0b0010 or 0b0110. If there is a matching ID, then this
mailbox will store the remote frame in the same fashion of a data frame. No

automatic remote response frame will be generated. The mask registers are used in
the matching process.
• If RFEN is asserted FlexCAN will not generate an automatic response for remote
request frames that match the FIFO filtering criteria. If the remote frame matches one
of the target IDs, it will be stored in the FIFO and presented to the Arm. Note that for
filtering formats A and B, it is possible to select whether remote frames are accepted
or not. For format C, remote frames are always accepted (if they match the
ID).Remote Request Frames are considered as normal frames, and generate a FIFO
overflow when a successful reception occurs and the FIFO is already full.
26.6.9.2 Overload Frames

FLEXCAN does transmit overload frames due to detection of following conditions on
CAN bus:
• Detection of a dominant bit in the first/second bit of Intermission
• Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames)
• Detection of a dominant bit at the 8th bit (last) of Error Frame Delimiter or Overload
Frame Delimiter
26.6.9.3 Time Stamp

The value of the Free Running Timer is sampled at the beginning of the Identifier field on
the CAN bus, and is stored at the end of "move-in" in the TIME STAMP field, providing
network behavior with respect to time.
Note that the Free Running Timer can be reset upon a specific frame reception, enabling
network time synchronization. Refer to TSYN description in Control 1 Register
(FLEXCAN_CTRL1).
26.6.9.4 Protocol Timing

The FLEXCAN module supports a variety of means to setup bit timing parameters that
are required by the CAN protocol. The Control Register has various fields used to control
bit timing parameters: PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW. See Control 1
Register (FLEXCAN_CTRL1).
The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose
period defines the 'time quantum' used to compose the CAN waveform. A time quantum
is the atomic unit of time handled by the CAN engine.

fCANCLK
fTq =
(Prescaler value)
A bit time is subdivided into three segments2 (reference Table 26-16):

• SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are
expected to happen within this section.
• Time Segment 1: This segment includes the Propagation Segment and the Phase
Segment 1 of the CAN standard. It can be programmed by setting the PROPSEG and
the PSEG1 fields of the CTRL Register so that their sum (plus 2) is in the range of 2
to 16 time quanta.
• Time Segment 2: This segment represents the Phase Segment 2 of the CAN standard.
It can be programmed by setting the PSEG2 field of the CTRL Register (plus 1) to be
2 to 8 time quanta long.
fTq
Bit Rate =
(number of Time Quanta)
2. For further explanation of the underlying concepts please refer to ISO/DIS 11519-1, Section 10.3. Reference also the
Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing.

NRZ Signal
Time Segment 1 TIme Segment 2

SYNC_SEG (PROP_SEG + PSEG1 +2) (PSEG2 +1)
1 2 ... 16 2 ... 8
8 ... 25 Time Quanta

= 1 Bit Time
Transmit Point Sample Point

(single or triple sampling)
Figure 26-2. Segments within the Bit Time
Whenever CAN bit is used as a measure of duration (e.g. MCR[FRZ_ACK] and

MCR[LPM_ACK] in Module Configuration Register (FLEXCAN_MCR)), the number
of peripheral clocks in one CAN bit can be calculated as:
fsys x [1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1)] x (PRESDIV + 1)

NCCP =
fCANCLK
where:
NCCP is the number of peripheral clocks in one CAN bit;
fCANCLK is the Protocol Engine (PE) Clock in Hz;
fSYS is the frequency of operation of the system (CHI) clock, in Hz;
PSEG1 is the value in CTRL1[PSEG1] field;
PROPSEG is the value in CTRL1[PROPSEG] field;
PRESDIV is the value in CTRL1[PRESDIV] field.
For example, 180 CAN bits = 180 x NCCP peripheral clock periods.

Figure 26-2 gives an overview of the CAN compliant segment settings and the related
parameter values.
Table 26-16. Time Segment Syntax
Syntax Description
SYNC_SEG System expects transitions to occur on the bus during this period.
Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point.
Sample Point A node samples the bus at this point. If the three samples per bit option is selected, then this
point marks the position of the third sample.
Table 26-17. CAN Standard Compliant Bit Time Segment Settings

Time Segment 1 Time Segment 2 Re-synchronization Jump Width
5 .. 10 2 1 .. 2
4 .. 11 3 1 .. 3
5 .. 12 4 1 .. 4
6 .. 13 5 1 .. 4
7 .. 14 6 1 .. 4
8 .. 15 7 1 .. 4
9 .. 16 8 1 .. 4
NOTE
The user must ensure the bit time settings are in compliance
with the CAN Protocol standard (ISO 11898-1).
26.6.9.5 Arbitration and Matching Timing

During normal reception and transmission of frames, the matching, arbitration, move-in
and move-out processes are executed during certain time windows inside the CAN frame,
as shown in the following figures.
Start Move
(bit 2)
DLC (4) DATA and/ or CRC (15 to79) EOF (7) Interm
Move-in
Matching WIndow (26 to90 bits) Window
Figure 26-3. Matching and Move-In Time Windows

Arb Start Move

Start Arbitration
Process (bit 1)
(delayed by TASD)
CRC (15) EOF (7) Interm
Move-out
Arbitration Window (25 bits) Window
Figure 26-4. Arbitration and Move-Out Time Windows
BusOff
0 1 2 3 ... 123 124 125 126 ... 128
TASD Arb Move-out

ECR [TX_ERR_CNT]
Count Process Window
(Transmit Error Counter)
Figure 26-5. Arbitration at the end of Bus Off and Move-Out Time Windows
When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer
memory during the available time window. In order to have sufficient time to do that, the
following requirements must be observed:
• A valid CAN bit timing must be programmed, as indicated in Table 26-17
• The peripheral clock frequency can not be smaller than the oscillator clock
frequency, i.e. the PLL can not be programmed to divide down the oscillator clock
• There must be a minimum ratio between the peripheral clock frequency and the CAN
bit rate, as specified in the following table.
Table 26-18. Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate
Number of Message Buffers RFEN Minimum Number of Peripheral
Clocks per CAN bit
16 and 32 0 16
64 0 25
16 1 16
32 1 17
64 1 30

A direct consequence of the first requirement is that the minimum number of time quanta
per CAN bit must be 8, so the oscillator clock frequency should be at least 8 times the
CAN bit rate. The minimum frequency ratio specified in Table 26-18 can be achieved by
choosing a high enough peripheral clock frequency when compared to the oscillator clock
frequency, or by adjusting one or more of the bit timing parameters (PRESDIV,
PROPSEG, PSEG1, PSEG2). As an example, taking the case of 64 MBs, if the oscillator
and peripheral clock frequencies are equal and the CAN bit timing is programmed to
have 8 time quanta per bit, then the prescaler factor (PRESDIV + 1) should be at least 2.
For prescaler factor equal to one and CAN bit timing with 8 time quanta per bit, the ratio
between peripheral and oscillator clock frequencies should be at least 2.
26.6.10 Modes of Operation Details

The FlexCAN module has four functional modes (Normal Mode, Freeze Mode, Listen-
Only Mode and Loop-Back Mode) and two low power modes (Disable Mode and Stop
Mode).See in Modes of Operation an introductory description of all these modes of
operation. The following sub-sections bring functional details on Freeze mode and the
low power modes.
26.6.10.1 Freeze Mode

This mode is requested by Arm through the assertion of the HALT bit in the MCR
Register or when the MCU is put into Debug Mode . In both cases it is also necessary
that the FRZ bit is asserted in the MCR Register and the module is not in any of the low
power modes (Disable, Stop). The acknowledgement is obtained through the assertion by
the FlexCAN of FRZ_ACK bit in the same register. The Arm must only consider the
FlexCAN in Freeze Mode when both request and acknowledgement conditions are
satisfied.
When Freeze Mode is requested during transmission or reception, FlexCAN does the
following:
• Waits to be in either Intermission, Passive Error, Bus Off or Idle state
• Waits for all internal activities like arbitration, matching, move-in and move-out to
finish. Pending move-in is not taken in account
• Ignores the FLEXCAN_RX input pin and drives the FLEXCAN_TX pin as recessive
• Stops the prescaler, thus halting all CAN protocol activities
• Grants write access to the Error Counters Register, which is read-only in other modes
• Sets the NOT_RDY and FRZ_ACK bits in MCR

After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in
MCR before executing any other action, otherwise FlexCAN may operate in an
unpredictable way. In Freeze mode, all memory mapped registers are accessible, except
for CTRL1[CLK_SRC] bit that can be read but cannot be written.
Exiting Freeze Mode is done in one of the following ways:
• Arm negates the FRZ bit in the MCR Register
• The Arm is removed from Debug Mode and the HALT bit is negated
The FRZ_ACK bit is negated after protocol engine recognizes the negation of freeze
request. Once out of Freeze Mode, FlexCAN tries to re-synchronize to the CAN bus by
waiting for 11 consecutive recessive bits.
26.6.10.2 Module Disable Mode

This low power mode is normally used to temporarily disable a complete FlexCAN
block, with no power consumption. It is requested by the Arm through the assertion of
the MDIS bit in the MCR Register and the acknowledgement is obtained through the
assertion by the FlexCAN of the LPM_ACK bit in the same register. The Arm must only
consider the FlexCAN in Disable Mode when both request and acknowledgement
conditions are satisfied.
If the module is disabled during Freeze Mode, it requests to disable the clocks to the PE
and CHI sub-modules, sets the LPM_ACK bit and negates the FRZ_ACK bit. The ability
to shut down the clocks depends on how FlexCAN is integrated into the MCU. If the
module is disabled during transmission or reception, FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of
Intermission and then checks it to be recessive
• Ignores its FLEXCAN_RX input pin and drives its FLEXCAN_TX pin as recessive
• May shut down the clocks to the PE and CHI sub-modules, depending on how
FlexCAN is integrated into the MCU
• Sets the NOT_RDY and LPM_ACK bits in MCR
The Bus Interface Unit continues to operate, enabling the Arm to access memory mapped
registers, except the Rx Mailboxes Global Mask Registers, the Rx Buffer 14 Mask
Register, the Rx Buffer 15 Mask Register, the Rx FIFO Global Mask Register. The Rx
FIFO Information Register, the Message Buffers, the Rx Individual Mask Registers, and
the reserved words within RAM may not be accessed when the module is in Disable
Mode depending on how FlexCAN RAM is integrated into the Arm. Exiting from this

mode is done by negating the MDIS bit by Arm, which make FlexCAN requests to
resume the clocks and negates the LPM_ACK bit after CAN protocol engine recognizes
the negation of disable mode requested by Arm.
26.6.10.3 Stop Mode

This is a system low power mode in which system clocks can be stopped for maximum
power savings. To enter stop mode, the CPU should manually assert a global Stop Mode
request (see the CAN1_STOP_REQ and CAN2_STOP_REQ bit in the register
IOMUXC_GPR4) and check the acknowledgement asserted by the FlexCAN (see the
CAN1_STOP_ACK and CAN2_STOP_ACK in the register IOMUXC_GPR4). The CPU
must only consider the FlexCAN in Stop Mode when both request and acknowledgement
conditions are satisfied.
If FlexCAN receives the global Stop Mode request during Freeze Mode, it sets the
LPM_ACK bit, negates the FRZ_ACK bit and then sends the Stop Acknowledge signal
to the CPU, in order to shut down the clocks globally. If Stop Mode is requested during
transmission or reception, FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of
Intermission and checks it to be recessive
• Ignores its FLEXCAN_RX input pin and drives its FLEXCAN_TX pin as recessive
• Sets the NOT_RDY and LPM_ACK bits in MCR
• Sends a Stop Acknowledge signal to the CPU, so that it can shut down the clocks
globally
Exiting Stop Mode is done in one of the following ways:
• Arm resuming the clocks and removing the Stop Mode request
• Arm resuming the clocks and Stop Mode request as a result of the Self Wake
mechanism
In the Self Wake mechanism, if the SLF_WAK bit in MCR Register was set at the time
FlexCAN entered Stop Mode, then upon detection of a recessive to dominant transition
on the CAN bus, FlexCAN sets the WAK_INT bit in the ESR Register and, if enabled by
the WAK_MSK bit in MCR, generates a Wake Up interrupt to the Arm. Upon receiving
the interrupt, the Arm should resume the clocks and remove the Stop Mode request
manually. FlexCAN will then wait for 11 consecutive recessive bits to synchronize to the
CAN bus. As a consequence, it will not receive the frame that woke it up .

Initialization/Application Information
The sensitivity to CAN bus activity can be modified by applying a low-pass filter
function to the FLEXCAN_RX input line while in Stop Mode. See the WAK_SRC bit in
Module Configuration Register (FLEXCAN_MCR) . This feature can be used to protect
FlexCAN from waking up due to short glitches on the CAN bus lines. Such glitches can
result from electromagnetic interference within noisy environments, the glitch filter width
can be set in Glitch Filter Width Register (FLEXCAN_GFWR).
26.6.11 Interrupts
The module can generate up to 70 interrupt sources (64 interrupts due to message buffers
and 6 interrupts due to Ored interrupts from MBs, Bus Off, Error, Tx Warning, Rx
Warning and Wake Up)).
The number of actual sources depends on the configured number of message buffers.
Each one of the message buffers can be an interrupt source, if its corresponding IMASK
bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer,
under the assumption that the buffer is initialized for either transmission or reception.
Each of the buffers has assigned a flag bit in the IFLAG Registers. The bit is set when the
corresponding buffer completes a successful transmission/reception and is cleared when
the Arm writes it to '1' (unless another interrupt is generated at the same time).
If the Rx FIFO is enabled (bit RFEN on MCR set), the interrupts corresponding to MBs 0
to 7 have a different behavior. Bit 7 of the IFLAG1 becomes the "FIFO Overflow" flag;
bit 6 becomes the FIFO Warning flag, bit 5 becomes the "Frames Available in FIFO flag"
and bits 4-0 are unused. See Interrupt Flags 1 Register (FLEXCAN_IFLAG1) for more
information.
A combined interrupt for all MBs is also generated by an Or of all the interrupt sources
from MBs. This interrupt gets generated when any of the Mailboxes or FIFO generates an
interrupt. The Arm must read the IFLAG Registers to determine which MB or FIFO
caused the interrupt.
The other 5 interrupt sources (Bus Off, Error, Tx Warning, Rx Warning and Wake Up
generate interrupts like the MB ones, and can be read from both the Error and Status
Register 1 and 2. The Bus Off, Error, Tx Warning and Rx Warning interrupt mask bits
are located in the Control 1 Register and the Wake-Up interrupt mask bit is located in the
MCR.

26.7 Initialization/Application Information

This section provide instructions for initializing the FLEXCAN module.
26.7.1 FLEXCAN Initialization Sequence

The FLEXCAN module may be reset in two ways:
• SOC level hard reset which resets all memory mapped registers asynchronously
• SOFT_RST bit in MCR, which resets some of the memory mapped registers
synchronously
Soft reset is synchronous and has to follow an internal request/acknowledge procedure
across clock domains. Therefore, it may take some time to fully propagate its effects. The
SOFT_RST bit remains asserted while soft reset is pending, so software can poll this bit
to know when the reset has completed. Also, soft reset can not be applied while clocks
are shut down in any of the low power modes. The low power mode should be exited and
the clocks resumed before applying soft reset.
After the module is enabled (MDIS bit negated), FLEXCAN automatically goes to
Freeze Mode. In Freeze Mode, FLEXCAN is un-synchronized to the CAN bus, the
HALT and FRZ bits in MCR Register are set, the internal state machines are disabled and
the FRZ_ACK and NOT_RDY bits in the MCR Register are set. The FLEXCAN_TX pin
is in recessive state and FLEXCAN does not initiate any transmission or reception of
CAN frames. Note that the Message Buffers and the Rx Individual Mask Registers are
not affected by reset, so they are not automatically initialized.
For any configuration change/initialization it is required that FLEXCAN is put into
Freeze Mode. The following is a generic initialization sequence applicable to the
FLEXCAN module:
• Initialize the Module Configuration Register
• Enable the individual filtering per MB and reception queue features by setting
the IRMQ bit
• Enable the warning interrupts by setting the WRN_EN bit
• If required, disable frame self reception by setting the SRX_DIS bit
• Enable the FIFO by setting the RFEN bit
• Enable the abort mechanism by setting the AEN bit
• Enable the local priority feature by setting the LPRIO_EN bit
• Initialize the Control Register
• Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW
• Determine the bit rate by programming the PRESDIV field
• Determine the internal arbitration mode (LBUF bit)

FLEXCAN Memory Map/Register Definition
• Initialize the Message Buffers

• The Control and Status word of all Message Buffers must be initialized
• If FIFO was enabled, the 8-entry ID table must be initialized
• Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask Registers
• Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in
CTRL Register (for Bus Off and Error interrupts) and in MCR Register for Wake-Up
interrupt
• Negate the HALT bit in MCR
Starting with the last event, FLEXCAN attempts to synchronize to the CAN bus.
26.8 FLEXCAN Memory Map/Register Definition
The complete memory map for a FLEXCAN module with 64 MBs capability is shown in
the following table. Each individual register is identified by its complete name and the
corresponding mnemonic. The access type can be Supervisor (S) or Unrestricted (U).
Most of the registers can be configured to have either Supervisor or Unrestricted access
by programming the SUPV bit in the MCR Register. The MCR register allows only
Supervisor access regardless the SUPV bit state.
The FLEXCAN module stores CAN messages for transmission and reception using a
Mailboxes and Rx FIFO structure.
FLEXCAN memory map
Absolute
Width Section/
(in bits) page
(hex)
209_0000 Module Configuration Register (FLEXCAN1_MCR) 32 R/W 5980_000Fh 26.8.1/1169
209_0004 Control 1 Register (FLEXCAN1_CTRL1) 32 R/W 0000_0000h 26.8.2/1174
209_0008 Free Running Timer Register (FLEXCAN1_TIMER) 32 R/W 0000_0000h 26.8.3/1177
Rx Mailboxes Global Mask Register
209_0010 32 R/W FFFF_FFFFh 26.8.4/1177
(FLEXCAN1_RXMGMASK)
209_0014 Rx Buffer 14 Mask Register (FLEXCAN1_RX14MASK) 32 R/W FFFF_FFFFh 26.8.5/1178
209_001C Error Counter Register (FLEXCAN1_ECR) 32 R/W 0000_0000h 26.8.7/1180
209_0020 Error and Status 1 Register (FLEXCAN1_ESR1) 32 R/W 0000_0000h 26.8.8/1181
209_0024 Interrupt Masks 2 Register (FLEXCAN1_IMASK2) 32 R/W 0000_0000h 26.8.9/1185
26.8.10/
209_0028 Interrupt Masks 1 Register (FLEXCAN1_IMASK1) 32 R/W 0000_0000h
1185

FLEXCAN memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
26.8.11/
209_002C Interrupt Flags 2 Register (FLEXCAN1_IFLAG2) 32 R/W 0000_0000h
1186
26.8.12/
209_0030 Interrupt Flags 1 Register (FLEXCAN1_IFLAG1) 32 R/W 0000_0000h
1186
26.8.13/
209_0034 Control 2 Register (FLEXCAN1_CTRL2) 32 R/W 0000_0000h
1188
26.8.14/
209_0038 Error and Status 2 Register (FLEXCAN1_ESR2) 32 R 0000_0000h
1194
26.8.15/
209_0044 CRC Register (FLEXCAN1_CRCR) 32 R 0000_0000h
1196
26.8.16/
209_0048 Rx FIFO Global Mask Register (FLEXCAN1_RXFGMASK) 32 R/W FFFF_FFFFh
1197
26.8.17/
209_004C Rx FIFO Information Register (FLEXCAN1_RXFIR) 32 R 0000_0000h
1198
26.8.18/
209_0880 Rx Individual Mask Registers (FLEXCAN1_RXIMR0) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_088C Rx Individual Mask Registers (FLEXCAN1_RXIMR3) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_08A0 Rx Individual Mask Registers (FLEXCAN1_RXIMR8) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_08AC Rx Individual Mask Registers (FLEXCAN1_RXIMR11) 32 R/W 0000_0000h
1199
26.8.18/
209_08B0 Rx Individual Mask Registers (FLEXCAN1_RXIMR12) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199


Absolute
Width Section/
(in bits) page
(hex)
26.8.18/
209_08BC Rx Individual Mask Registers (FLEXCAN1_RXIMR15) 32 R/W 0000_0000h
1199
26.8.18/
209_08C0 Rx Individual Mask Registers (FLEXCAN1_RXIMR16) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_08CC Rx Individual Mask Registers (FLEXCAN1_RXIMR19) 32 R/W 0000_0000h
1199
26.8.18/
209_08D0 Rx Individual Mask Registers (FLEXCAN1_RXIMR20) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_08DC Rx Individual Mask Registers (FLEXCAN1_RXIMR23) 32 R/W 0000_0000h
1199
26.8.18/
209_08E0 Rx Individual Mask Registers (FLEXCAN1_RXIMR24) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_08EC Rx Individual Mask Registers (FLEXCAN1_RXIMR27) 32 R/W 0000_0000h
1199
26.8.18/
209_08F0 Rx Individual Mask Registers (FLEXCAN1_RXIMR28) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_08FC Rx Individual Mask Registers (FLEXCAN1_RXIMR31) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199


Absolute
Width Section/
(in bits) page
(hex)
26.8.18/
1199
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1199
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1199
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1199
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1199
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1199
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1199
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1199
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1199
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1199
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1199
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1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
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1199
26.8.18/
1199
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1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199


Absolute
Width Section/
(in bits) page
(hex)
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.19/
209_09E0 Glitch Filter Width Registers (FLEXCAN1_GFWR) 32 R/W 0000_007Fh
1199
209_4000 Module Configuration Register (FLEXCAN2_MCR) 32 R/W 5980_000Fh 26.8.1/1169
209_4004 Control 1 Register (FLEXCAN2_CTRL1) 32 R/W 0000_0000h 26.8.2/1174
209_4008 Free Running Timer Register (FLEXCAN2_TIMER) 32 R/W 0000_0000h 26.8.3/1177
Rx Mailboxes Global Mask Register
209_4010 32 R/W FFFF_FFFFh 26.8.4/1177
(FLEXCAN2_RXMGMASK)
209_401C Error Counter Register (FLEXCAN2_ECR) 32 R/W 0000_0000h 26.8.7/1180
209_4020 Error and Status 1 Register (FLEXCAN2_ESR1) 32 R/W 0000_0000h 26.8.8/1181
209_4024 Interrupt Masks 2 Register (FLEXCAN2_IMASK2) 32 R/W 0000_0000h 26.8.9/1185
26.8.10/
209_4028 Interrupt Masks 1 Register (FLEXCAN2_IMASK1) 32 R/W 0000_0000h
1185
26.8.11/
209_402C Interrupt Flags 2 Register (FLEXCAN2_IFLAG2) 32 R/W 0000_0000h
1186
26.8.12/
209_4030 Interrupt Flags 1 Register (FLEXCAN2_IFLAG1) 32 R/W 0000_0000h
1186
26.8.13/
209_4034 Control 2 Register (FLEXCAN2_CTRL2) 32 R/W 0000_0000h
1188
26.8.14/
209_4038 Error and Status 2 Register (FLEXCAN2_ESR2) 32 R 0000_0000h
1194
26.8.15/
209_4044 CRC Register (FLEXCAN2_CRCR) 32 R 0000_0000h
1196
26.8.16/
209_4048 Rx FIFO Global Mask Register (FLEXCAN2_RXFGMASK) 32 R/W FFFF_FFFFh
1197
26.8.17/
209_404C Rx FIFO Information Register (FLEXCAN2_RXFIR) 32 R 0000_0000h
1198
26.8.18/
1199
26.8.18/
1199


Absolute
Width Section/
(in bits) page
(hex)
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_48AC Rx Individual Mask Registers (FLEXCAN2_RXIMR11) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_48BC Rx Individual Mask Registers (FLEXCAN2_RXIMR15) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_48CC Rx Individual Mask Registers (FLEXCAN2_RXIMR19) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_48DC Rx Individual Mask Registers (FLEXCAN2_RXIMR23) 32 R/W 0000_0000h
1199


Absolute
Width Section/
(in bits) page
(hex)
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_48EC Rx Individual Mask Registers (FLEXCAN2_RXIMR27) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
209_48FC Rx Individual Mask Registers (FLEXCAN2_RXIMR31) 32 R/W 0000_0000h
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
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1199
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1199
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1199
26.8.18/
1199


Absolute
Width Section/
(in bits) page
(hex)
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
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1199
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1199
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1199
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1199
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1199
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1199
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1199
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1199
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1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.18/
1199
26.8.19/
209_49E0 Glitch Filter Width Registers (FLEXCAN2_GFWR) 32 R/W 0000_007Fh
1199
26.8.1 Module Configuration Register (FLEXCANx_MCR)

This register defines global system configurations, such as the module operation mode
(e.g., low power) and maximum message buffer configuration.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NOT_RDY
LPM_ACK
FRZ_ACK
R
SOFT_RST
WAK_MSK
WAK_SRC
WRN_EN
Reserved
SRX_DIS
SUPV
HALT
SLF_
MDIS FRZ RFEN IRMQ
WAK
Reset 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LPRIO_EN
Reserved
Reserved AEN Reserved IDAM MAXMB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

FLEXCANx_MCR field descriptions

Field Description
31 This bit controls whether FLEXCAN is enabled or not. When disabled, FLEXCAN shuts down the clocks to
MDIS the CAN Protocol Interface and Message Buffer Management sub-modules. This is the only bit in MCR not
affected by soft reset. See Module Disable Mode for more information.
1 Disable the FLEXCAN module

0 Enable the FLEXCAN module
30 The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when
FRZ Debug Mode is requested at Arm level. When FRZ is asserted, FLEXCAN is enabled to enter Freeze
Mode. Negation of this bit field causes FLEXCAN to exit from Freeze Mode.
1 Enabled to enter Freeze Mode

0 Not enabled to enter Freeze Mode
29 This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is set, MBs 0 to 5 cannot be
RFEN used for normal reception and transmission because the corresponding memory region (0x80-0xDC) is
used by the FIFO engine as well as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which
are used as Rx FIFO ID Filter Table elements.RFEN also impacts the definition of the minimum number of
peripheral clocks per CAN bit as described in Table 26-18 (see Arbitration and Matching Timing).This bit
can only be written in Freeze mode as it is blocked by hardware in other modes.
1 FIFO enabled
0 FIFO not enabled
28 Assertion of this bit puts the FLEXCAN module into Freeze Mode. The Arm should clear it after initializing
HALT the Message Buffers and Control Register. No reception or transmission is performed by FLEXCAN before
this bit is cleared. Freeze Mode can not be entered while FLEXCAN is in any of the low power modes.See
Freeze Mode for more information
1 Enters Freeze Mode if the FRZ bit is asserted.

0 No Freeze Mode request.
27 This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode. It is
NOT_RDY negated once FLEXCAN has exited these modes.
1 FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode

0 FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
26 This bit enables the Wake Up Interrupt generation.
WAK_MSK
1 Wake Up Interrupt is enabled
0 Wake Up Interrupt is disabled
25 When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped
SOFT_RST registers. The following registers are reset: MCR (except the MDIS bit), TIMER, ECR, ESR1, ESR2,
IMASK1, IMASK2, IFLAG1, IFLAG2 and CRCR. Configuration registers that control the interface to the
CAN bus are not affected by soft reset. The following registers are unaffected:
CTRL1, CTRL2, RXIMR0_RXIMR63, RXGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR and all
Message Buffers
The SOFT_RST bit can be asserted directly by the Arm when it writes to the MCR Register. It may take
some time to fully propagate its effect. The SOFT_RST bit remains asserted while reset is pending, and is
automatically negated when reset completes. Therefore, software can poll this bit to know when the soft
reset has completed.
Soft reset cannot be applied while clocks are shut down in any of the low power modes. The module
should be first removed from low power mode, and then soft reset can be applied.

FLEXCANx_MCR field descriptions (continued)

Field Description
1 Reset the registers
0 No reset request
24 This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped. The Freeze
FRZ_ACK Mode request cannot be granted until current transmission or reception processes have finished.
Therefore the software can poll the FRZ_ACK bit to know when FLEXCAN has actually entered Freeze
Mode. If Freeze Mode request is negated, then this bit is negated once the FLEXCAN prescaler is running
again. If Freeze Mode is requested while FLEXCAN is in any of the low power modes, then the FRZ_ACK
bit will only be set when the low power mode is exited. See Freeze Mode for more information
1 FLEXCAN in Freeze Mode, prescaler stopped

0 FLEXCAN not in Freeze Mode, prescaler running
23 This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode. Reset value
SUPV of this bit is '1', so the affected registers start with Supervisor access allowance only. This bit can only be
written in Freeze mode as it is blocked by hardware in other modes.
1 FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access
behaves as though the access was done to an unimplemented register location
0 FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses
22 This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode. If this bit had been asserted
SLF_WAK by the time FLEXCAN entered Stop Mode, then FLEXCAN will look for a recessive to dominant transition
on the bus during these modes. If a transition from recessive to dominant is detected during Stop Mode,
then FLEXCAN generates, if enabled to do so, a Wake Up interrupt to the Arm so that it can resume the
clocks globally and FlexCAN can request to resume the clocks. This bit can not be written while the
module is in Stop Mode.
1 FLEXCAN Self Wake Up feature is enabled

0 FLEXCAN Self Wake Up feature is disabled
21 When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and
WRN_EN Status Register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will always be zero,
independent of the values of the error counters, and no warning interrupt will ever be generated.This bit
1 TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to ≥ 96.
0 TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
20 This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode. Either of these low
LPM_ACK power modes can not be entered until all current transmission or reception processes have finished, so
the Arm can poll the LPM_ACK bit to know when FLEXCAN has actually entered low power mode. See
Module Disable Mode, and Stop Mode for more information
1 FLEXCAN is either in Disable Mode, or Stop mode

0 FLEXCAN not in any of the low power modes
19 This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from
WAK_SRC spurious wake up. See Stop Mode for more information. This bit can only be written in Freeze mode as it
is blocked by hardware in other modes.
1 FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN
bus
0 FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN
bus.
- Reserved


Field Description
17 This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this bit is asserted,
SRX_DIS frames transmitted by the module will not be stored in any MB, regardless if the MB is programmed with
an ID that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due to
the frame reception. This bit can only be written in Freeze mode as it is blocked by hardware in other
modes.
1 Self reception disabled

0 Self reception enabled
16 This bit indicates whether Rx matching process will be based either on individual masking and queue or
IRMQ on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK. This bit can only be
written in Freeze mode as it is blocked by hardware in other modes.
1 Individual Rx masking and queue feature are enabled.

0 Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S
word locks the MB even if it is EMPTY.
- Reserved
13 This bit is provided for backwards compatibility reasons. It controls whether the local priority feature is
LPRIO_EN enabled or not. It is used to extend the ID used during the arbitration process. With this extended ID
concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted ID still has
11-bit for standard frames and 29-bit for extended frames.This bit can only be written in Freeze mode as it
is blocked by hardware in other modes.
1 Local Priority enabled

0 Local Priority disabled
12 This bit is supplied for backwards compatibility reasons. When asserted, it enables the Tx abort feature.
AEN This feature guarantees a safe procedure for aborting a pending transmission, so that no frame is sent in
the CAN bus without notification. This bit can only be written in Freeze mode as it is blocked by hardware
in other modes.Write Abort code into Rx Mailboxes can cause unpredictable results when the MCR[AEN]
is asserted.
1 Abort enabled
0 Abort disabled
- Reserved
9–8 This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below. Note that
IDAM all elements of the table are configured at the same time by this field (they are all the same format). See
Rx FIFO Structure. This bit can only be written in Freeze mode as it is blocked by hardware in other
modes.
00 Format A One full ID (standard or extended) per ID filter Table element.

01 Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element.
10 Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element.
11 Format D All frames rejected.
- Reserved
MAXMB This 7-bit field defines the number of the last Message Buffers that will take part in the matching and
arbitration processes. The reset value (0x0F) is equivalent to 16 MB configuration. This field can only be
written in Freeze Mode as it is blocked by hardware in other modes
Number of the last MB = MAXMB.


Field Description
NOTE: Additionally, the value of MAXMB must encompass the FIFO size defined by CTRL2[RFFN]
MAXMB also impacts the definition of the minimum number of peripheral clocks per CAN bit as described
in Table 26-18 (see Arbitration and Matching Timing).
26.8.2 Control 1 Register (FLEXCANx_CTRL1)
This register is defined for specific FLEXCAN control features related to the CAN bus,
such as bit-rate, programmable sampling point within an Rx bit, Loop Back Mode, Listen
Only Mode, Bus Off recovery behavior and interrupt enabling (Bus-Off, Error, Warning).
It also determines the Division Factor for the clock prescaler.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESDIV RJW PSEG1 PSEG2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RWRN_MSK
TWRN_MSK
BOFF_MSK
BOFF_REC
Reserved
ERR_
LPB Reserved SMP TSYN LBUF LOM PROP_SEG
MSK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_CTRL1 field descriptions

Field Description
31–24 This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency.
PRESDIV The Sclock period defines the time quantum of the CAN protocol. For the reset value, the Sclock
frequency is equal to the PE clock frequency. The Maximum value of this register is 0xFF, that gives a
minimum Sclock frequency equal to the PE clock frequency divided by 256.For more information refer to
Protocol Timing. This field can only be written in Freeze mode as it is blocked by hardware in other
modes.
FLEXCANx_CTRL1 field descriptions (continued)

Field Description
Sclock frequency = CPI clock frequency / (PRESDIV+1)
23–22 This 2-bit field defines the maximum number of time quanta1 that a bit time can be changed by one re-
RJW synchronization. The valid programmable values are 0-3. This field can only be written in Freeze mode as
it is blocked by hardware in other modes
Resync Jump Width = RJW + 1.
21–19 This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time . The valid programmable
PSEG1 values are 0-7. This field can only be written in Freeze mode as it is blocked by hardware in other modes
Phase Buffer Segment 1 = (PSEG1 + 1) x Time-Quanta.
18–16 This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time . The valid programmable
PSEG2 values are 1-7. This field can only be written in Freeze mode as it is blocked by hardware in other modes
Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta.
15 This bit provides a mask for the Bus Off Interrupt.
BOFF_MSK
1 Bus Off interrupt enabled
0 Bus Off interrupt disabled
14 This bit provides a mask for the Error Interrupt.
ERR_MSK
1 Error interrupt enabled
0 Error interrupt disabled
- Reserved
12 This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an internal
LPB loop back that can be used for self test operation. The bit stream output of the transmitter is fed back
internally to the receiver input. The FLEXCAN_RX input pin is ignored and the FLEXCAN_TX output goes
to the recessive state (logic '1'). FlexCAN behaves as it normally does when transmitting, and treats its
own transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the
bit sent during the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit to
ensure proper reception of its own message. Both transmit and receive interrupts are generated. This bit
1 Loop Back enabled

0 Loop Back disabled
11 This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and
TWRN_MSK Status Register. This bit is read as zero when MCR[WRN_EN] bit is negated. This bit can only be written if
MCR[WRN_EN] bit is asserted.
1 Tx Warning Interrupt enabled

0 Tx Warning Interrupt disabled
10 This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and
RWRN_MSK Status Register. This bit is read as zero when MCR[WRN_EN] bit is negated. This bit can only be written if
MCR[WRN_EN] bit is asserted.
1 Rx Warning Interrupt enabled

0 Rx Warning Interrupt disabled
- Reserved
7 This bit defines the sampling mode of CAN bits at the FLEXCAN_RX. This bit can only be written in
SMP Freeze mode as it is blocked by hardware in other modes.


Field Description
1 Three samples are used to determine the value of the received bit: the regular one (sample point) and
2 preceding samples, a majority rule is used
0 Just one sample is used to determine the bit value
6 This bit defines how FLEXCAN recovers from Bus Off state. If this bit is negated, automatic recovering
BOFF_REC from Bus Off state occurs according to the CAN Specification 2.0B. If the bit is asserted, automatic
recovering from Bus Off is disabled and the module remains in Bus Off state until the bit is negated by the
user. If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus, then
Bus Off recovery happens as if the BOFF_REC bit had never been asserted. If the negation occurs after
128 sequences of 11 recessive bits occurred, then FLEXCAN will re-synchronize to the bus by waiting for
11 recessive bits before joining the bus. After negation, the BOFF_REC bit can be re-asserted again
during Bus Off, but it will only be effective the next time the module enters Bus Off. If BOFF_REC was
negated when the module entered Bus Off, asserting it during Bus Off will not be effective for the current
Bus Off recovery.
1 Automatic recovering from Bus Off state disabled

0 Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
5 This bit enables a mechanism that resets the free-running timer each time a message is received in
TSYN Message Buffer 0. This feature provides means to synchronize multiple FLEXCAN stations with a special
"SYNC" message (i.e., global network time). If the RFEN bit in MCR is set (FIFO enabled), the first
available Mailbox, according to CTRL2[RFFN] setting, is used for timer synchronization instead of
MB0.This bit can only be written in Freeze mode as it is blocked by hardware in other modes.
1 Timer Sync feature enabled

0 Timer Sync feature disabled
4 This bit defines the ordering mechanism for Message Buffer transmission. When asserted, the LPRIO_EN
LBUF bit does not affect the priority arbitration.This bit can only be written in Freeze mode as it is blocked by
hardware in other modes.
1 Lowest number buffer is transmitted first

0 Buffer with highest priority is transmitted first
3 This bit configures FLEXCAN to operate in Listen Only Mode. In this mode, transmission is disabled, all
LOM error counters are frozen and the module operates in a CAN Error Passive mode. Only messages
acknowledged by another CAN station will be received. If FLEXCAN detects a message that has not been
acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the
message.
Listen-Only Mode acknowledgement can be obtained by the state of ESR1[FLT_CONF] field which is
Passive Error when Listen-Only Mode is entered. There can be some delay between the Listen-Only
Mode request and acknowledge.
This bit can only be written in Freeze mode as it is blocked by hardware in other modes.
1 FLEXCAN module operates in Listen Only Mode

0 Listen Only Mode is deactivated
PROP_SEG This 3-bit field defines the length of the Propagation Segment in the bit time. The valid programmable
values are 0-7. This field can only be written in Freeze mode as it is blocked by hardware in other modes
Propagation Segment Time = (PROPSEG + 1) * Time-Quanta.
Time-Quantum = one Sclock period.
1. One time quantum is equal to the Sclock period.

26.8.3 Free Running Timer Register (FLEXCANx_TIMER)

This register represents a 16-bit free running counter that can be read and written by the
Arm. The timer starts from $0000 after Reset, counts linearly to $FFFF, and wraps
around.
The timer is clocked by the FLEXCAN bit-clock (which defines the baud rate on the
CAN bus). During a message transmission/reception, it increments by one for each bit
that is received or transmitted. When there is no message on the bus, it counts using the
previously programmed baud rate. During Freeze Mode, disable, and stop mode, the
timer is not incremented.
The timer value is captured at the beginning of the identifier field of any frame on the
CAN bus. This captured value is written into the Time Stamp entry in a message buffer
after a successful reception or transmission of a message.
If bit CTRL1[TSYN] is asserted the Timer is reset whenever a message is received in the
first available Mailbox, according to CTRL2[RFFN] setting.
Arm can write to this register anytime. However, if the write occurs at the same time that
the Timer is being reset by a reception in the first Mailbox, then the write value is
discarded.
Reading this register affects the Mailbox Unlocking procedure. For additional details,
refer to Message Buffer Lock Mechanism.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved TIMER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_TIMER field descriptions

Field Description
- Reserved
TIMER TIMER
26.8.4 Rx Mailboxes Global Mask Register

(FLEXCANx_RXMGMASK)
RXMGMASK is provided for legacy support. Asserting the MCR[IRMQ] bit causes the
RXMGMASK Register to have no effect on the module operation.

RXMGMASK is used to mask the filter fields of all Rx MBs, excluding MBs 14-15,
which have individual mask registers.
This register can only be written in Freeze mode as it is blocked by hardware in other
modes.
Table 26-19. Rx Mailboxes Global Mask usage
SMB[RTR]1 CTRL2[RRS] CTRL2[EACEN] Mailbox filter fields
MB[RTR] MB[IDE] MB[ID] reserved
0 - 0 - - MG[28:0] MG[31:29]
Note2 Note3
0 - 1 MG[31] MG[30] MG[28:0] MG[29]
1 0 - - - - MG[31:0]
1 1 0 - - MG[28:0] MG[31:29]
1 1 1 MG[31] MG[30] MG[28:0] MG[29]
1. RTR bit of the Incoming Frame. It is saved into an auxiliary MB called Rx Serial Message Buffer (Rx SMB).
2. If CTRL2[EACEN] bit is negated the RTR bit of Mailbox is never compared with the RTR bit of the Incoming Frame (Rx
SMB[RTR]).
3. If CTRL2[EACEN] bit is negated the IDE bit of Mailbox is always compared with the IDE bit of the Incoming Frame (Rx
SMB[IDE]).

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
MG31_MG0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLEXCANx_RXMGMASK field descriptions

Field Description
MG31_MG0 These bits mask the Mailbox filter bits as shown in the figure above. Note that the alignment with the ID
word of the Mailbox is not perfect as the two most significant MG bits affect the fields RTR and IDE which
are located in the Control and Status word of the Mailbox. Rx Mailboxes Global Mask Register
(FLEXCAN_RXMGMASK) shows in detail which MG bits mask each Mailbox filter field.
1 The corresponding bit in the filter is checked against the one received
0 the corresponding bit in the filter is "don't care"
26.8.5 Rx Buffer 14 Mask Register (FLEXCANx_RX14MASK)

RX14MASK is provided for legacy support, asserting the MCR[IRMQ] bit causes the
RX14MASK to have no effect on the module operation.
RX14MASK is used to mask the filter fields of Message Buffer 14.
This register can only be programmed while the module is in Freeze Mode as it is
blocked by hardware in other modes.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
RX14M31_RX14M0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLEXCANx_RX14MASK field descriptions

Field Description
RX14M31_ These bits mask Mailbox 14 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters
RX14M0 (see Rx Mailboxes Global Mask Register (FLEXCAN_RXMGMASK))
1 The corresponding bit in the filter is checked

26.8.6 Rx Buffer 15 Mask Register (FLEXCANx_RX15MASK)

RX15MASK is provided for legacy support, asserting the MCR[IRMQ] bit causes the
RX15MASK Register to have no effect on the module operation.
RX15MASK is used to mask the filter fields of Message Buffer 15.
This register can only be programmed while the module is in Freeze Mode as it is
blocked by hardware in other modes.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
RX15M31_RX15M0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLEXCANx_RX15MASK field descriptions

Field Description
RX15M31_ These bits mask Mailbox 15 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters
RX15M0 (see Rx Mailboxes Global Mask Register (FLEXCAN_RXMGMASK)).


26.8.7 Error Counter Register (FLEXCANx_ECR)

This register has 2 8-bit fields reflecting the value of two FLEXCAN error counters:
Transmit Error Counter (Tx_Err_Counter field) and Receive Error Counter
(Rx_Err_Counter field). The rules for increasing and decreasing these counters are
described in the CAN protocol and are completely implemented in the FLEXCAN
module. Both counters are read only except in Freeze Mode, where they can be written
by the Arm.
FLEXCAN responds to any bus state as described in the protocol, e.g. transmit 'Error
Active' or 'Error Passive' flag, delay its transmission start time ('Error Passive') and avoid
any influence on the bus when in 'Bus Off' state. The following are the basic rules for
FLEXCAN bus state transitions.
• If the value of Tx_Err_Counter or Rx_Err_Counter increases to be greater than or
equal to 128, the FLT_CONF field in the Error and Status Register is updated to
reflect 'Error Passive' state.
• If the FLEXCAN state is 'Error Passive', and either Tx_Err_Counter or
Rx_Err_Counter decrements to a value less than or equal to 127 while the other
already satisfies this condition, the FLT_CONF field in the Error and Status Register
is updated to reflect 'Error Active' state.
• If the value of Tx_Err_Counter increases to be greater than 255, the FLT_CONF
field in the Error and Status Register is updated to reflect 'Bus Off' state, and an
interrupt may be issued. The value of Tx_Err_Counter is then reset to zero.
• If FLEXCAN is in 'Bus Off' state, then Tx_Err_Counter is cascaded together with
another internal counter to count the 128th occurrences of 11 consecutive recessive
bits on the bus. Hence, Tx_Err_Counter is reset to zero and counts in a manner where
the internal counter counts 11 such bits and then wraps around while incrementing
the Tx_Err_Counter. When Tx_Err_Counter reaches the value of 128, the
FLT_CONF field in the Error and Status Register is updated to be 'Error Active' and
both error counters are reset to zero. At any instance of dominant bit following a
stream of less than 11 consecutive recessive bits, the internal counter resets itself to
zero without affecting the Tx_Err_Counter value.
• If during system start-up, only one node is operating, then its Tx_Err_Counter
increases in each message it is trying to transmit, as a result of acknowledge errors
(indicated by the ACK_ERR bit in the Error and Status Register). After the transition
to 'Error Passive' state, the Tx_Err_Counter does not increment anymore by
acknowledge errors. Therefore the device never goes to the 'Bus Off' state.
• If the Rx_Err_Counter increases to a value greater than 127, it is not incremented
further, even if more errors are detected while being a receiver. At the next

successful message reception, the counter is set to a value between 119 and 127 to
resume to 'Error Active' state.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved RX_ERR_COUNTER TX_ERR_COUNTER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_ECR field descriptions

Field Description
- Reserved
15–8 Rx_Err_Counter
RX_ERR_
COUNTER
TX_ERR_ Tx_Err_Counter
COUNTER
26.8.8 Error and Status 1 Register (FLEXCANx_ESR1)

This register reflects various error conditions, some general status of the device and it is
the source of four interrupts to the Arm.
The Arm read action clears bits 15-10, therefore the reported error conditions(bits 15-10)
are those that occurred since the last time the Arm read this register. Bits 9-3 are status
bits .
Some bits in this register are read-only and some are not .
Table 26-20. FlexCAN State
SYNCH IDLE TX RX FlexCAN state
0 0 0 0 Not synchronized to CAN bus
1 1 x x Idle
1 0 1 0 Transmitting
1 0 0 1 Receiving
other combinations Reserved


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCH
R
RWRN_INT
TWRN_INT
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_ERR
FRM_ERR
BIT1_ERR
BIT0_ERR
ACK_ERR
RX_WRN
TX_WRN
STF_ IDLE
R TX FLT_CONF RX
ERR
BOFF_INT
WAK_INT
ERR_INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_ESR1 field descriptions

Field Description
- Reserved
18 This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate
SYNCH in the communication process. It is set and cleared by the FlexCAN. Refer to Table 26-20
1 FlexCAN is synchronized to the CAN bus

0 FlexCAN is not synchronized to the CAN bus
17 If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0'
TWRN_INT to '1', meaning that the Tx error counter reached 96. If the corresponding mask bit in the Control Register
(TWRN_MSK) is set, an interrupt is generated to the Arm. This bit is cleared by writing it to '1'. When
WRN_EN is negated, this flag is masked. Arm must clear this flag before disabling the bit. Otherwise it will
be set when the WRN_EN is set again. Writing '0' has no effect. This flag is not generated during "Bus Off"
state. This bit is not updated during Freeze mode.
1 The Tx error counter transition from < 96 to >= 96

0 No such occurrence

FLEXCANx_ESR1 field descriptions (continued)

Field Description
16 If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0'
RWRN_INT to '1', meaning that the Rx error counters reached 96. If the corresponding mask bit in the Control Register
(RWRN_MSK) is set, an interrupt is generated to the Arm. This bit is cleared by writing it to '1'. When
WRN_EN is negated, this flag is masked. Arm must clear this flag before disabling the bit. Otherwise it will
be set when the WRN_EN is set again. Writing '0' has no effect. This bit is not updated during Freeze
mode.
1 The Rx error counter transition from < 96 to >= 96

15 This bit indicates when an inconsistency occurs between the transmitted and the received bit in a
BIT1_ERR message.
This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node sending a
passive error flag that detects dominant bits.
1 At least one bit sent as recessive is received as dominant

14 This bit indicates when an inconsistency occurs between the transmitted and the received bit in a
BIT0_ERR message.
1 At least one bit sent as dominant is received as recessive

13 This bit indicates that an Acknowledge Error has been detected by the transmitter node, i.e., a dominant
ACK_ERR bit has not been detected during the ACK SLOT.
1 An ACK error occurred since last read of this register

12 This bit indicates that a CRC Error has been detected by the receiver node, i.e., the calculated CRC is
CRC_ERR different from the received.
1 A CRC error occurred since last read of this register.

11 This bit indicates that a Form Error has been detected by the receiver node, i.e., a fixed-form bit field
FRM_ERR contains at least one illegal bit.
1 A Form Error occurred since last read of this register

10 This bit indicates that a Stuffing Error has been detected.
STF_ERR
1 A Stuffing Error occurred since last read of this register.
0 No such occurrence.
9 This bit indicates when repetitive errors are occurring during message transmission.
TX_WRN
1 TX_Err_Counter ≥ 96
8 This bit indicates when repetitive errors are occurring during message reception.
RX_WRN
1 Rx_Err_Counter ≥ 96
7 This bit indicates when CAN bus is in IDLE state.Refer to Table 26-20.
IDLE

FLEXCANx_ESR1 field descriptions (continued)

Field Description
1 CAN bus is now IDLE
6 This bit indicates if FLEXCAN is transmitting a message.Refer to Table 26-20.
TX
1 FLEXCAN is transmitting a message
0 FLEXCAN is receiving a message
5–4 If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the
FLT_CONF FLT_CONF field will indicate "Error Passive". The very same delay affects the way how FLT_CONF
reflects an update to ECR register by the Arm. It may be necessary up to one CAN bit time to get them
coherent again.
Since the Control Register is not affected by soft reset, the FLT_CONF field will not be affected by soft
reset if the LOM bit is asserted.
This 2-bit field indicates the Confinement State of the FLEXCAN module, as shown in below:
00 Error Active
01 Error Passive
1x Bus off
3 This bit indicates if FlexCAN is receiving a message. Refer to Table 26-20.
RX
1 FLEXCAN is transmitting a message
0 FLEXCAN is receiving a message
2 This bit is set when FLEXCAN enters 'Bus Off' state. If the corresponding mask bit in the Control Register
BOFF_INT (BOFF_MSK) is set, an interrupt is generated to the Arm. This bit is cleared by writing it to '1'. Writing '0'
has no effect.
1 FLEXCAN module entered 'Bus Off' state

1 This bit indicates that at least one of the Error Bits (bits 15-10) is set. If the corresponding mask bit in the
ERR_INT Control Register (ERR_MSK) is set, an interrupt is generated to the Arm. This bit is cleared by writing it to
'1'.Writing '0' has no effect.
1 Indicates setting of any Error Bit in the Error and Status Register
0 When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if
WAK_INT the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm. This bit is cleared by
writing it to '1'. When SLF_WAK is negated, this flag is masked. Arm must clear this flag before disabling
the bit. Otherwise it will be set when the SLF_WAK is set again. Writing '0' has no effect
1 Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is
in Stop Mode

26.8.9 Interrupt Masks 2 Register (FLEXCANx_IMASK2)
This register allows any number of a range of 32 Message Buffer Interrupts to be enabled
or disabled. It contains one interrupt mask bit per buffer, enabling the Arm to determine
which buffer generates an interrupt after a successful transmission or reception (i.e. when
the corresponding IFLAG2 bit is set).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BUF63M_BUF32M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_IMASK2 field descriptions

Field Description
BUF63M_ Each bit enables or disables the respective FLEXCAN Message Buffer (MB32 to MB63) Interrupt.
BUF32M
Setting or clearing a bit in the IMASK2 Register can assert or negate an interrupt request, if the
corresponding IFLAG2 bit is set.
1 The corresponding buffer Interrupt is enabled

0 The corresponding buffer Interrupt is disabled
26.8.10 Interrupt Masks 1 Register (FLEXCANx_IMASK1)
This register allows to enable or disable any number of a range of 32 Message Buffer
Interrupts. It contains one interrupt mask bit per buffer, enabling the Arm to determine
which buffer generates an interrupt after a successful transmission or reception (i.e.,
when the corresponding IFLAG1 bit is set).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BUF31M_BUF0M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_IMASK1 field descriptions

Field Description
BUF31M_BUF0M Each bit enables or disables the respective FLEXCAN Message Buffer (MB0 to MB31) Interrupt.
Setting or clearing a bit in the IMASK1 Register can assert or negate an interrupt request, if the
corresponding IFLAG1 bit is set

FLEXCANx_IMASK1 field descriptions (continued)

Field Description
1 The corresponding buffer Interrupt is enabled
0 The corresponding buffer Interrupt is disabled
26.8.11 Interrupt Flags 2 Register (FLEXCANx_IFLAG2)
This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt
flag bit per buffer. Each successful transmission or reception sets the corresponding
IFLAG2 bit. If the corresponding IMASK2 bit is set, an interrupt will be generated. The
interrupt flag must be cleared by writing it to '1'. Writing '0' has no effect.Before updating
MCR[MAXMB] field, Arm must treat the IFLAG2 bits which MB value is greater than
the MCR[MAXMB] to be updated, otherwise they will keep set and be inconsistent with
the amount of MBs available.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BUF63I_BUF32I
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_IFLAG2 field descriptions

Field Description
BUF63I_BUF32I Each bit flags the respective FLEXCAN Message Buffer (MB32 to MB63) interrupt.
1 The corresponding buffer has successfully completed transmission or reception

26.8.12 Interrupt Flags 1 Register (FLEXCANx_IFLAG1)

This register defines the flags for 32 Message Buffer interrupts and FIFO interrupts. It
contains one interrupt flag bit per buffer. Each successful transmission or reception sets
the corresponding IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt will
be generated. The Interrupt flag must be cleared by writing it to '1'. Writing '0' has no
effect.
When the RFEN bit in the MCR is set (Rx FIFO enabled), the function of the 8 least
significant interrupt flags (BUF7I - BUF0I) is changed to support the FIFO operation.
BUF7I, BUF6I and BUF5I indicate operating conditions of the FIFO, while BUF4I to
BUF0I are not used. Before enabling the RFEN, Arm must service the IFLAGS asserted

in the Rx FIFO region (see Rx FIFO). Otherwise, these IFLAGS will mistakenly show
the related MBs now belonging to FIFO as having contents to be serviced. When the
RFEN is negated, the FIFO flags must be cleared. The same care must be taken when a
RFFN value is selected extending Rx FIFO filters beyond MB7 (see Control 2 Register
(FLEXCAN_CTRL2)). For example, when RFFN is 0x8, the MB0-23 range is occupied
by Rx FIFO filters and related IFLAGS must be cleared.
Before updating MCR[MAXMB] field, Arm must service the IFLAG1 which MB value
is greater than the MCR[MAXMB] to be updated, otherwise they will keep set and be
inconsistent with the amount of MBs available.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUF31I_BUF8I
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUF7I
BUF6I
BUF5I
BUF31I_BUF8I BUF4I_BUF0I
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_IFLAG1 field descriptions

Field Description
31–8 Each bit flags the respective FLEXCAN Message Buffer (MB8 to MB31) interrupt.
BUF31I_BUF8I
1 The corresponding MB has successfully completed transmission or reception
7 If the Rx FIFO is not enabled, this bit flags the interrupt for MB7.
BUF7I
If the MCR[RFEN] bit is asserted, this flag indicates that a message was lost because Rx FIFO is full. Note
that the flag will not be asserted when the Rx FIFO is full and the message was captured by a Mailbox.
This flag is cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by Arm writes.
1 MB7 completed transmission/reception or FIFO overflow

6 If the Rx FIFO is not enabled, this bit flags the interrupt for MB6.
BUF6I
If the MCR[RFEN] bit is asserted, this flag indicates when the number of unread messages within the Rx
FIFO is increased to 5 from 4 due to the reception of a new one, meaning that the Rx FIFO is almost full.
Note that if the flag is cleared while the number of unread messages is greater than 4 it will not assert
again until the number of unread messages within the Rx FIFO is decreased to equal or less than 4.

FLEXCANx_IFLAG1 field descriptions (continued)

Field Description
1 MB6 completed transmission/reception or FIFO almost full
5 If the Rx FIFO is not enabled, this bit flags the interrupt for MB5. If the Rx FIFO is enabled, this flag
BUF5I indicates that at least one frame is available to be read from the Rx FIFO.
1 MB5 completed transmission/reception or frames available in the FIFO

BUF4I_BUF0I If the Rx FIFO is not enabled, these bits flag the interrupts for MB0 to MB4 . If the Rx FIFO is enabled,
these flags are not used and must be considered as reserved locations.
These flags are cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by Arm writes.
1 Corresponding MB completed transmission/reception

26.8.13 Control 2 Register (FLEXCANx_CTRL2)

This register contains control bits for CAN errors, FIFO features and mode selection.
Table 26-21. Rx FIFO Filters
RFFN[3:0] Number of Rx FIFO Message Buffers Remaining Rx FIFO ID Filter Rx FIFO ID Filter
filters occupied by Rx Available Table Elements Table Elements
FIFO and ID Filter Mailboxes1 Affected by Rx Affected by Rx
Table Individual Masks2 FIFO Global Mask2
0x0 8 MB 0-7 MB 8-63 Elements 0-7 none
0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15
0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements 28-87
0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95
0xC 104 MB 0-31 MB 32-63 Elements 0-31 Elements 32-103
0xD 112 MB 0-33 MB 34-63 Elements 0-31 Elements 32-111
0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119
0xF 128 MB 0-37 MB 38-63 Elements 0-31 Elements 32-127
1. The number of the last remaining available mailboxes is defined by the MCR[MAXMB] field.
2. If Rx Individual Mask Registers are not enabled then all Rx FIFO filters are affected by the Rx FIFO Global Mask.

Each group of eight filters occupies a memory space equivalent to two Message Buffers
which means that the more filters are implemented the less Mailboxes will be available.
Considering that the Rx FIFO occupies the memory space originally reserved for MB0-5,
RFFN should be programmed with a value corresponding to a number of filters not
greater than the number of available memory words which can be calculated as follows:
(SETUP_MB - 6) x 4
where SETUP_MB is MAXMB.

The number of remaining Mailboxes available will be:
SETUP_MB - 8 - (RFFN x 2)
If the Number of Rx FIFO Filters programmed through RFFN exceeds the SETUP_MB
value, the exceeding ones will not be functional.Unshaded regions in Table 26-22
indicate the valid combinations of MAXMB, RFEN and RFFN, shaded regions are not
functional.
Table 26-22. Valid Combinations of MAXMB, RFEN and RFFN
RFF 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
N
RFE 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
N
MAX
MB
0-6
7-8
9 - 10
11 -
12
13
-14
15 -
16
17
-18
19 -
20
21 -
22

Table 26-22. Valid Combinations of MAXMB, RFEN and RFFN (continued)

RFF 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
N
RFE 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
N
MAX
MB
23 -
24
25 -
26
27 -
28
29
-30
31 -
32
33 -
34
35 -
36
37 -
63

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
WRMFRZ
EACEN
Reserved RFFN TASD MRP RRS
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_CTRL2 field descriptions

Field Description
31 must be written as 0
-
- Reserved


Field Description
28 Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit can only be written in
WRMFRZ Freeze mode and has no effect out of Freeze mode.
1 Enable unrestricted write access to FlexCAN memory

0 Keep the write access restricted in some regions of FlexCAN memory
27–24 This 4-bit field defines the number of Rx FIFO filters according to Table 26-21 . The maximum selectable
RFFN number of filters is determined by the Arm. This field can only be written in Freeze mode as it is blocked
by hardware in other modes. RFFN defines a number of Message Buffers occupied by Rx FIFO and ID
Filter (see Table 26-21) that may not exceed the number of available Mailboxes present in module,
defined by MCR[MAXMB].Default RFFN value is 0x0, which leads to a total of 8 Rx FIFO filters, occupies
the first 8 Message Buffers (MB 0-7) and makes available the next Message Buffers (MB 8-63) for
Mailboxes. As a second example, when RFFN is set to 0xD, there will be 112 Rx FIFO filters, located in
MB 0-33, and MB 34-63 are available for Mailboxes. Notice that, in this case, individual masks (RXIMR)
will just cover Rx FIFO filters in 0-31 range, and filters 32-111 will use RXFGMASK. In case of reducing
the number of last Message Buffers, MCR[MAXMB] (see Module Configuration Register
(FLEXCAN_MCR)) can be adjusted by the application to minimum of 33, in order to give room to the Rx
FIFO and its ID Filter Table defined by RFFN. On the contrary, if the application sets MCR[MAXMB] to 16,
for instance, the maximum RFFN is limited to 0x4. RFFN also impacts the definition of the minimum
number of peripheral clocks per CAN bit as described in Table 26-18 (see Arbitration and Matching
Timing).
23–19 This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the
TASD first bit of CRC field on CAN bus. This field can only be written in Freeze mode as it is blocked by
hardware in other modes.
This field is useful to optimize the transmit performance based on factors such as: peripheral/serial clock
ratio, CAN bit timing and number of MBs . The duration of an arbitration process, in terms of CAN bits, is
directly proportional to the number of available MBs and CAN baud rate and inversely proportional to the
peripheral clock frequency.
The optimal arbitration timing is that in which the last MB is scanned right before the first bit of the
Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial clock ratio is high
and the CAN baud rate is low then the arbitration can be delayed and vice-versa.
If TASD is 0 then the arbitration start is not delayed, thus Arm has less time to configure a Tx MB for the
next arbitration, but more time is reserved for arbitration . In the other hand, if TASD is 24 then Arm can
configure a Tx MB later and less time is reserved for arbitration.
If too little time is reserved for arbitration the FlexCAN may be not able to find winner MBs in time to
compete with other nodes for the CAN bus. If the arbitration ends too much time before the first bit of
Intermission field then there is a chance that Arm reconfigure some Tx MBs and the winner MB is not the
best to be transmitted.
The reset value is different on various platforms, according to their peripheral clock frequency, number of
MBs and target CAN baud rate.
The optimal configuration for TASD can be calculated as:


Field Description
fCANCLK x [MAXMB + 3 - (RFEN x 8) - (RFEN x RFFN x 2)] x 2

TASD = 25 -
fsys x [1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1)] x (PRESDIV + 1)
where:
fCANCLK is the Protocol Engine (PE) Clock in Hz; PE clock is derrived from CAN_CLK_ROOT in CCM. See
the Clock controller module.
fSYS is the peripheral clock in Hz;
MAXMB is the value in CTRL1[MAXMB] field;
RFEN is the value in CTRL1[RFEN] bit;
RFFN is the value in CTRL2[RFFN] field;
PROPSEG is the value in CTRL1[PROPSEG] field;
PRESDIV is the value in CTRL1[PRESDIV] field.
Please refer to Arbitration process and Protocol Timing for more details.
18 If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching
MRP continues on the Rx FIFO. This bit can only be written in Freeze mode as it is blocked by hardware in
other modes.
1 Matching starts from Mailboxes and continues on Rx FIFO

0 Matching starts from Rx FIFO and continues on Mailboxes
17 If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the
RRS corresponding Message Buffer in the same fashion of a Data Frame. No automatic Remote Response
Frame will be generated.
If this bit is negated the Remote Request Frame is submitted to a matching process and an automatic
Remote Response Frame is generated if a Message Buffer with CODE=0b1010 is found with the same ID.
This bit can only be written in Freeze mode as it is blocked by hardware in other modes.
1 Remote Request Frame is stored

0 Remote Response Frame is generated
16 This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding
EACEN bits in the incoming frame by the matching process. This bit does not affect matching for Rx FIFO. This bit
1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within
the incoming frame. Mask bits do apply.
0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.


Field Description
Reserved

26.8.14 Error and Status 2 Register (FLEXCANx_ESR2)
This register reflects various interrupt flags and some general status.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LPTM
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VPS IMB
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLEXCANx_ESR2 field descriptions

Field Description
- Reserved
22–16 If ESR2[VPS] is asserted, his 7-bit field indicates the lowest number inactive Mailbox (refer to IMB bit
LPTM description). If there is no inactive Mailbox then the Mailbox indicated depends on CTRL1[LBUF] bit
value . If CTRL1[LBUF] bit is negated then the Mailbox indicated is the one which has the greatest
arbitration value (see Highest Mailbox priority first). If CTRL1[LBUF] bit is asserted then the Mailbox
indicated is the highest number active Tx Mailbox. If a Tx Mailbox is being transmitted it is not considered
in LPTM calculation. If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
updated with its Mailbox number.
- Reserved
14 This bit indicates whether IMB and LPTM contents are currently valid or not. VPS is asserted upon every
VPS complete Tx arbitration process unless the Arm writes to Control and Status word of a Mailbox that has
already been scanned (i.e. it is behind Tx Arbitration Pointer) during the Tx arbitration process . If there is
no inactive Mailbox and only one Tx Mailbox which is being transmitted then VPS is not asserted. VPS is
negated upon the start of every Tx arbitration process or upon a write to Control and Status word of any
Mailbox.ESR2[VPS] is not affected by any Arm write into Control Status (C/S) of a MB which is blocked by
abort mechanism. When MCR[AEN] is asserted, the abort code write in C/S of a MB that is been
transmitted (pending abort), or any write attempt into a Tx MB with IFLAG set is blocked.
1 Contents of IMB and LPTM are valid

0 Contents of IMB and LPTM are invalid
13 If ESR2[VPS] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either
IMB 0b1000 or 0b0000).
This bit is asserted in the following cases:
(1) During arbitration, if a LPTM is found and it is inactive.
(2) If IMB is not asserted and a frame is transmitted successfully.
(3) This bit is cleared in all start of arbitration (see Arbitration process).
LPTM mechanism have the following behavior: if a MB is successfully transmitted and ESR2[IMB]=0 (no
inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and the index related to the MB just
transmitted is loaded into ESR2[LPTM].
1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the
first one.
0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
Reserved

26.8.15 CRC Register (FLEXCANx_CRCR)
This register provides information about the CRC of transmitted messages

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MBCRC
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TXCRC
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLEXCANx_CRCR field descriptions

Field Description
- Reserved
22–16 This field indicates the number of the Mailbox corresponding to the value in TXCRC field.
MBCRC
- Reserved
TXCRC This field indicates the CRC value of the last message transmitted. This field is updated at the same time
the Tx Interrupt Flag is asserted.
26.8.16 Rx FIFO Global Mask Register (FLEXCANx_RXFGMASK)

If Rx FIFO is enabled RXFGMASK is used to mask the Rx FIFO ID Filter Table
elements that do not have a corresponding RXIMR according to CTRL2[RFFN] field
setting.
This register can only be written in Freeze Mode as it is blocked by hardware in other
modes.
Table 26-23. Rx FIFO Global Mask usage
Rx FIFO Identifier Acceptance Filter fields
ID Filter Table RTR IDE RXIDA RXIDB RXIDC reserved
Elements Format
(MCR[IDAM])
A FGM[31] FGM[30] FGM[29:1] - - FGM[0]
B FGM[31] FGM[30] - FGM[29:16] -
FGM[15] FGM[14] FGM[13:0]
1
C - - - FGM[31:24]
FGM[23:16]
FGM[15:8]
FGM[7:0]
2
1. If MCR[IDAM] field is equivalent to the format B only the fourteen most significant bits of the Identifier of the incoming
frame are compared with the Rx FIFO filter.
2. If MCR[IDAM] field is equivalent to the format C only the eight most significant bits of the Identifier of the incoming frame
are compared with the Rx FIFO filter.


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
FGM31_FGM0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLEXCANx_RXFGMASK field descriptions

Field Description
FGM31_FGM0 These bits mask the ID Filter Table elements bits in a perfect alignment.Rx FIFO Global Mask Register
(FLEXCAN_RXFGMASK) shows in detail which FGM bits mask each IDAF field. Clear this register has
the effect of disabling the ID Filter.

0 The corresponding bit in the filter is "don't care"
26.8.17 Rx FIFO Information Register (FLEXCANx_RXFIR)

RXFIR provides information on Rx FIFO.
This register is the port through which Arm accesses the output of the RXFIR FIFO
located in RAM. The RXFIR FIFO is written by the FlexCAN whenever a new message
is moved into the Rx FIFO as well as its output is updated whenever the output of the Rx
FIFO is updated with the next message. Refer to Rx FIFO to find instructions on reading
this register.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IDHIT
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_RXFIR field descriptions

Field Description
- Reserved
IDHIT This 9-bit field indicates which Identifier Acceptance Filter (see Rx FIFO Structure) was hit by the received
message that is in the output of the Rx FIFO . (refer to Rx FIFO for details) If multiple filters match the
incoming message ID then the first matching IDAF found (lowest number) by the matching process is
indicated. This field is valid only while the IFLAG[BUF5I] is asserted.

26.8.18 Rx Individual Mask Registers (FLEXCANx_RXIMRn)

RXIMR are used as acceptance masks for ID filtering in Rx MBs and the Rx FIFO . If
the Rx FIFO is not enabled, one mask register is provided for each available Mailbox,
providing ID masking capability on a per Mailbox basis.
When the Rx FIFO is enabled (MCR[RFEN] bit is asserted), up to 32 Rx Individual
Mask Registers can apply to the Rx FIFO ID Filter Table elements on a one-to-one
correspondence depending on CTRL2[RFFN] setting. Refer to Control 2 Register
(FLEXCAN_CTRL2) for details .
RXIMR can only be written by the Arm while the module is in Freeze Mode, otherwise
they are blocked by hardware .
The Individual Rx Mask Registers are not affected by reset and must be explicitly
initialized prior to any reception.
Address: Base address + 880h offset + (4d × i), where i=0d to 63d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
MI31_MI0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXCANx_RXIMRn field descriptions

Field Description
MI31_MI0 These bits mask both Mailbox filter and Rx FIFO ID Filter Table element in distinct ways.
For Mailbox filter refer to Rx Mailboxes Global Mask Register (FLEXCAN_RXMGMASK).
For Rx FIFO ID Filter Table element refer to Rx FIFO Global Mask Register (FLEXCAN_RXFGMASK).

26.8.19 Glitch Filter Width Registers (FLEXCANx_GFWR)
The Glitch Filter just takes effects when FLEXCAN enters the STOP mode.
Address: Base address + 9E0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 GFWR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

FLEXCANx_GFWR field descriptions

Field Description
Reserved
GFWR It determines the Glitch Filter Width. The width will be divided from Oscillator clock by GFWR values. By
default, it is 5.33 μs when the oscillator is 24 MHz.
Filter Pulse Width = [(GFWR FIELD + 1) x (1 / Osc. Frequency)]

Chapter 27
General Power Controller (GPC)
27.1 Overview
The General Power Control (GPC) block includes the sub-blocks listed here.
• CPU Power Gating Control (PGC)
• GPU/VPU accelerators power gating controller
Each sub-block has its own IP registers.
GPC determines wake-up IRQ for exiting WAIT/STOP mode (with or without CPU
power gating).
interrupts wake-up to CCM/ CPU

128 irq masking
PGC GPU/ VPU
PGC ARM
GPC control bits
IP interface
GPC_IP
Figure 27-1. GPC Block Diagram

Clocks
27.2 Clocks
The table found here describes the clock sources for GPC.
information.
Table 27-1. GPC Clocks
pgc_clk ipg_clk_root PGC peripheral clock
sys_clk ipg_clk_root Module clock
27.3 Power Gating Control (PGC)

Power Gating (PGC) is applied to the Arm CPU only in STOP low power mode, after all
essential CPU registers data are saved by Arm dormant procedure.
If any of the unmasked interrupts appears, CPU is powered up and clock restore request
(exit from STOP mode) is sent to CCM.
PGC power down sequence:
• CCM sends power down request when the chip is about to enter stop mode. The user
should define which modules will be powered down (CTRL registers of
corresponding PGC module, bit 0).
PGC power up sequence:
• One of the power up irq is asserted.
• Power up request is asserted in GPC and in CCM.
• The Power Gated modules are powered up, according to PGC settings of appropriate
module.
The Power Gated modules require reset after powering up. The next figure describes
GPC-SRC handshake procedure for reset after power gating.

Chapter 27 General Power Controller (GPC)
Figure 27-2. GPC-SRC handshake for reset after power gating
27.3.1 Overview
The Power Gating Controller (PGC) is a power management component that controls the
power-down and power-up sequencing of individual subsystems.
The sequence timing is programmable using the PGC control registers. Figure 27-3
shows PGC as part of the SoC’s overall power management scheme.

GPC Interrupt Controller (INTC)
SoC
Power Management and Clock-Control Subsystems
Power Management PGC

Request (Up or Down) Power and
Reset Control
Higher-level Power (Up or Down) Target Subsystem
Component Gating to be managed
Controller
Acknowledge
Figure 27-3. PGC Block Diagram
27.3.1.1 Features
Key features of the PGC include:
• Provides the ability to switch off power to a target subsystem.
• Generates power-up and power-down control sequences.
• Provides programmable registers to adjust the timing of the power control signals.
27.4 GPC Interrupt Controller (INTC)

The INTC (Interrupt Controller) detects an interrupt and generates the wakeup signal. It
supports up to 128 interrupts.
27.4.1 Interrupt Controller features

The features of the GPC INTC are listed below.
Features:
• Provides an option to mask/unmask each interrupt
• Detects interrupts and generates the wake up signal
• 32-bits IP bus interface
• All registers are byte-accessible

27.5 GPC Memory Map/Register Definition
Detailed descriptions of each register can be found below.

GPC memory map
Absolute
Width Section/
(in bits) page
(hex)
20D_C000 GPC Interface control register (GPC_CNTR) 32 R/W 0010_0000h 27.5.1/1205
20D_C008 IRQ masking register 1 (GPC_IMR1) 32 R/W 0000_0000h 27.5.2/1207
20D_C00C IRQ masking register 2 (GPC_IMR2) 32 R/W 0000_0000h 27.5.3/1207
20D_C018 IRQ status resister 1 (GPC_ISR1) 32 R 0000_0000h 27.5.6/1208
20D_C01C IRQ status resister 2 (GPC_ISR2) 32 R 0000_0000h 27.5.7/1209
27.5.1 GPC Interface control register (GPC_CNTR)
Address: 20D_C000h base + 0h offset = 20D_C000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 1
GPCIRQM
Reserved
- -
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

GPC Memory Map/Register Definition
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
gpu_vpu_pup_req
gpu_vpu_pdn_req
R 0 0 0
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_CNTR field descriptions

Field Description
Reserved
- Reserved
21 GPC interrupt/event masking
GPCIRQM
1 interrupt/event is masked
0 not masked
Reserved
19–17 Reserved
-
This bitfield is readable/writeable, but avoid writing to this reserved bitfield.
16 Reserved
-
This bitfield is readable/writeable, but avoid writing to this reserved bitfield.
Reserved
- Reserved
Reserved
Reserved
1 GPU/VPU Power Up request. Self-cleared bit.
gpu_vpu_pup_re
* Note: Power switch for GPU/VPU power domain is controlled by ANALOG configuration, not GPU/VPU
q
PGC signals
1 Request Power Up sequence to start for GPU/VPU

0 no request
0 GPU/VPU Power Down request. Self-cleared bit.
gpu_vpu_pdn_re
* Note: Power switch for GPU/VPU power domain is controlled by ANALOG configuration, not GPU/VPU
q
PGC signals
1 Request Power Down sequence to start for GPU/VPU

0 no request

27.5.2 IRQ masking register 1 (GPC_IMR1)
IMR1 Register - masking of irq[63:32].

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR1 field descriptions

Field Description
IMR1 IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked

Address: 20D_C000h base + Ch offset = 20D_C00Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC Memory Map/Register Definition

Field Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
27.5.6 IRQ status resister 1 (GPC_ISR1)
ISR1 Register - status of irq [63:32].

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR1 field descriptions

Field Description
ISR1 IRQ[63:32] status, read only


Address: 20D_C000h base + 1Ch offset = 20D_C01Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description

PGC Memory Map/Register Definition

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
27.6 PGC Memory Map/Register Definition
The PGC registers can be accessed only in supervisor mode.

Attempts to access registers when not in supervisor mode or attempts to access an
unimplemented address location might trigger a bus transfer error. (The hardware asserts
the signal ips_xfr_err if the PGC has been integrated with resp_sel tied low.) In this case,
software should take appropriate action (such as ignore the error, log the error, or initiate
a soft reset).
All PGC registers are byte-accessible.
NOTE
The base address of each PGC module instantiation is specified
in the GPC module. Absolute address values will be calculated
by [GPC base address] + [PGC CPU/GPU/DISPLAY Offset].
PGC memory map
Absolute
Width Section/
(in bits) page
(hex)
20D_C260 PGC GPU PGC Control Register (PGC_GPU_CTRL) 32 R/W 0000_0000h 27.6.1/1211

PGC memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
PGC GPU Power Up Sequence Control Register
20D_C264 32 R/W 0000_0F01h 27.6.2/1212
(PGC_GPU_PUPSCR)
PGC GPU Pull Down Sequence Control Register
20D_C268 32 R/W 0000_0101h 27.6.3/1212
(PGC_GPU_PDNSCR)
PGC GPU Power Gating Controller Status Register
20D_C26C 32 R/W 0000_0000h 27.6.4/1213
(PGC_GPU_SR)
20D_C2A0 PGC CPU Control Register (PGC_CPU_CTRL) 32 R/W 0000_0000h 27.6.5/1214
PGC CPU Power Up Sequence Control Register
20D_C2A4 32 R/W 0000_0F01h 27.6.6/1214
(PGC_CPU_PUPSCR)
PGC CPU Pull Down Sequence Control Register
20D_C2A8 32 R/W 0000_0101h 27.6.7/1215
(PGC_CPU_PDNSCR)
PGC CPU Power Gating Controller Status Register
20D_C2AC 32 R/W 0000_0000h 27.6.8/1216
(PGC_CPU_SR)
27.6.1 PGC GPU PGC Control Register (PGC_GPU_CTRL)
The PGCR enables the response to a power-down request.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 PCR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PGC_GPU_CTRL field descriptions

Field Description
Reserved
0 Power Control
PCR
NOTE: PCR must not change from power-down request (pdn_req) assertion until the target subsystem is
completely powered up.
0 Do not switch off power even if pdn_req is asserted.

1 Switch off power when pdn_req is asserted.

27.6.2 PGC GPU Power Up Sequence Control Register

(PGC_GPU_PUPSCR)
The PUPSCR contains the power-up timing parameters.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
SW2ISO SW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1
PGC_GPU_PUPSCR field descriptions

Field Description
Reserved
13–8 After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the
SW2ISO value of SW2ISO before negating isolation.
NOTE: SW2ISO must not be programmed to zero.

Reserved
SW After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of
SW before asserting power toggle on/off signal (switch_b).
NOTE: SW must not be programmed to zero.
NOTE: The PGC clock is generated from the IPG_CLK_ROOT. for frequency configuration of the
IPG_CLK_ROOT. See Clock Controller Module (CCM).
27.6.3 PGC GPU Pull Down Sequence Control Register

(PGC_GPU_PDNSCR)
The SR contains the status parameters.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
ISO2SW ISO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

PGC_GPU_PDNSCR field descriptions

Field Description
Reserved
13–8 After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before
ISO2SW negating power toggle on/off signal (switch_b).
NOTE: ISO2SW must not be programmed to zero.

Reserved
ISO After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value
of ISO before asserting isolation.
NOTE: ISO must not be programmed to zero.
27.6.4 PGC GPU Power Gating Controller Status Register

(PGC_GPU_SR)

Address: 20D_C000h base + 26Ch offset = 20D_C26Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 PSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PGC_GPU_SR field descriptions

Field Description
Reserved
0 Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as soon
PSR as any of the power control output changes its state to one. Write one to clear this bit. Software should
clear this bit after power up; otherwise, PSR continues to reflect the power status of the initial power down.
0 The target subsystem was not powered down for the previous power-down request.
1 The target subsystem was powered down for the previous power-down request.

27.6.5 PGC CPU Control Register (PGC_CPU_CTRL)
The PGCR enables the response to a power-down request.

Address: 20D_C000h base + 2A0h offset = 20D_C2A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 PCR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PGC_CPU_CTRL field descriptions

Field Description
Reserved
0 Power Control
PCR
NOTE: PCR must not change from power-down request (pdn_req) assertion until the target subsystem is
completely powered up.
0 Do not switch off power even if pdn_req is asserted.

1 Switch off power when pdn_req is asserted.
27.6.6 PGC CPU Power Up Sequence Control Register

(PGC_CPU_PUPSCR)
The PUPSCR contains the power-up timing parameters.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
SW2ISO SW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1

PGC_CPU_PUPSCR field descriptions

Field Description
Reserved
13–8 After asserting , the PGC waits a number of 32k clocks equal to the value of SW2ISO before negating
SW2ISO isolation.
NOTE: SW2ISO must not be programmed to zero. The SW2ISO value should be chosen such that the
delay before negating isolation is greater than the LDO ramp-up time.
Reserved
SW After a power-up request (pup_req assertion), the PGC waits a number of 32k clocks equal to the value of
SW before asserting.
NOTE: SW must not be programmed to zero.
27.6.7 PGC CPU Pull Down Sequence Control Register

(PGC_CPU_PDNSCR)
The PDNSCR contains the power-down timing parameters.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
ISO2SW ISO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
PGC_CPU_PDNSCR field descriptions

Field Description
Reserved
13–8 After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before
ISO2SW negating.
NOTE: ISO2SW must not be programmed to zero.

Reserved
ISO After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value
of ISO before asserting isolation.
NOTE: ISO must not be programmed to zero.

27.6.8 PGC CPU Power Gating Controller Status Register

(PGC_CPU_SR)

Address: 20D_C000h base + 2ACh offset = 20D_C2ACh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 PSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PGC_CPU_SR field descriptions

Field Description
Reserved
0 Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as soon
PSR as any of the power control output changes its state to one (isolation or power off occurs). Write one to
clear this bit. Software should clear this bit after power up; otherwise, PSR continues to reflect the power
status of the initial power down.
0 The target subsystem was not powered down for the previous power-down request.
1 The target subsystem was powered down for the previous power-down request.

Chapter 28
General Purpose Input/Output (GPIO)
28.1 Overview
The GPIO general-purpose input/output peripheral provides dedicated general-purpose
pins that can be configured as either inputs or outputs.
When configured as an output, it is possible to write to an internal register to control the
state driven on the output pin. When configured as an input, it is possible to detect the
state of the input by reading the state of an internal register. In addition, the GPIO
peripheral can produce CORE interrupts.
The GPIO is one of the blocks controlling the IOMUX of the chip.

Overview
Block
This block not

configured as a GPIO
GPIO IOMUX
GPIO.DR input_on
GPIO.GDIR
GPIO.PSR Dir
Data_out
GPIO.ICR1 GPIO.ICR2 Data_in
GPIO.EDGE_SEL PAD1
GPIO.IMR
GPIO.ISR
IOMUXC alternate input
SW_MUX_CTL_PAD_*
MUX_MODE
SW_PAD_CTL_PAD_*
pad settings
IOMUX input_on
Dir
Data_out
Data_in
PAD2
Figure 28-1. Chip IOMUX Scheme
The GPIO functionality is provided through eight registers, an edge-detect circuit, and
interrupt generation logic.
The eight registers are:
• Data register (GPIO_DR)
• GPIO direction register (GPIO_GDIR)
• Pad sample register (GPIO_PSR)
• Interrupt control registers (GPIO_ICR1, GPIO_ICR2)

Chapter 28 General Purpose Input/Output (GPIO)
• Edge select register (GPIO_EDGE_SEL)

• Interrupt mask register (GPIO_IMR)
• Interrupt status register (GPIO_ISR)
These registers are described in detail in GPIO Memory Map/Register Definition.
Each GPIO input has a dedicated edge-detect circuit which can be configured through
software to detect rising edges, falling edges, logic low-levels or logic high-levels on the
input signals. The outputs of the edge detect circuits are optionally masked by setting the
corresponding bit in the interrupt mask register (GPIO_IMR). These qualified outputs are
OR'ed together to generate two one-bit interrupt lines:
• Combined interrupt indication for GPIOx signals 0 - 15
• Combined interrupt indication for GPIOx signals 16 - 31
In addition, GPIO1 provides visibility to each of its 8 low order interrupt sources (i.e.
GPIO1 interrupt n, for n = 0 – 7). However, individual interrupt indications from other
GPIOx are not available.
The GPIO edge detection is described further in Interrupt Control Unit.
The GPIO's overall functionality is described further in GPIO Functional Description.

The GPIO subsystem contains multiple GPIO blocks, which can generate and control up
to 32 signals for general purpose.
A block diagram of the GPIO is shown in Figure 28-2

External Signals
GDIR
gdir
GPIO_DR gpio_dr
GPIO_PSR gpio_in
IP Bus Interface
ICR0
Interrupt
Control
GPIO_ICR1 Unit
GPIO_EDGE_SEL int_31_16
GPIO_ISR int_15_0
int_31_0
GPIO_IMR
Figure 28-2. GPIO Block Diagram
28.1.2 Features
The GPIO includes the following features:
• General purpose input/output logic capabilities:
• Drives specific data to output using the data register (GPIO_DR)
• Controls the direction of the signal using the GPIO direction register
(GPIO_GDIR)
• Enables the core to sample the status of the corresponding inputs by reading the
pad sample register (GPIO_PSR).
• GPIO interrupt capabilities:
• Identifies interrupt edges
• Generates three active-high interrupts to the SoC interrupt controller


The tables found here describe the external signals of GPIO.
Table 28-1. GPIO1 External Signals
GPIO1_IO00 - GPIO_0 ALT5 IO
GPIO1_IO10 - SD2_CLK ALT5 IO
GPIO1_IO11 - SD2_CMD ALT5 IO
GPIO1_IO12 - SD2_DAT3 ALT5 IO
GPIO1_IO22 - ENET_MDIO ALT5 IO
GPIO1_IO23 - ENET_REF_CLK ALT5 IO
GPIO1_IO24 - ENET_RX_ER ALT5 IO
GPIO1_IO25 - ENET_CRS_DV ALT5 IO
GPIO1_IO26 - ENET_RXD1 ALT5 IO
GPIO1_IO27 - ENET_RXD0 ALT5 IO
GPIO1_IO28 - ENET_TX_EN ALT5 IO
GPIO1_IO29 - ENET_TXD1 ALT5 IO
GPIO1_IO30 - ENET_TXD0 ALT5 IO
GPIO1_IO31 - ENET_MDC ALT5 IO

External Signals

GPIO2_IO00 - NANDF_D0 ALT5 IO
GPIO2_IO16 - EIM_A22 ALT5 IO
GPIO2_IO23 - EIM_CS0 ALT5 IO
GPIO2_IO24 - EIM_CS1 ALT5 IO
GPIO2_IO25 - EIM_OE ALT5 IO
GPIO2_IO26 - EIM_RW ALT5 IO
GPIO2_IO27 - EIM_LBA ALT5 IO
GPIO2_IO28 - EIM_EB0 ALT5 IO

GPIO3_IO00 - EIM_DA0 ALT5 IO

Table 28-3. GPIO3 External Signals (continued)

GPIO3_IO16 - EIM_D16 ALT5 IO

GPIO4_IO06 - KEY_COL0 ALT5 IO
GPIO4_IO07 - KEY_ROW0 ALT5 IO

External Signals

GPIO4_IO16 - DI0_DISP_CLK ALT5 IO
GPIO4_IO17 - DI0_PIN15 ALT5 IO
GPIO4_IO21 - DISP0_DAT0 ALT5 IO

GPIO5_IO00 - EIM_WAIT ALT5 IO


GPIO5_IO18 - CSI0_PIXCLK ALT5 IO
GPIO5_IO19 - CSI0_MCLK ALT5 IO
GPIO5_IO20 - CSI0_DATA_EN ALT5 IO
GPIO5_IO21 - CSI0_VSYNC ALT5 IO
GPIO5_IO22 - CSI0_DAT4 ALT5 IO

GPIO6_IO07 - NANDF_CLE ALT5 IO
GPIO6_IO08 - NANDF_ALE ALT5 IO
GPIO6_IO09 - NANDF_WP_B ALT5 IO
GPIO6_IO10 - NANDF_RB0 ALT5 IO
GPIO6_IO11 - NANDF_CS0 ALT5 IO
GPIO6_IO19 - RGMII_TXC ALT5 IO
GPIO6_IO20 - RGMII_TD0 ALT5 IO

Clocks

GPIO6_IO24 - RGMII_RX_CTL ALT5 IO
GPIO6_IO25 - RGMII_RD0 ALT5 IO
GPIO6_IO26 - RGMII_TX_CTL ALT5 IO
GPIO6_IO30 - RGMII_RXC ALT5 IO
GPIO6_IO31 - EIM_BCLK ALT5 IO

GPIO7_IO08 - SD3_RST ALT5 IO
28.3 Clocks
The table found here describes the clock sources for GPIO.
Please see the clock controller Module for clock setting, configuration and gating
information.

Table 28-8. GPIO Clocks

28.4 GPIO Functional Description

28.4.1 GPIO Function

A GPIO signal can operate as a general-purpose input/output when the IOMUX is set to
GPIO mode. Each GPIO signal may be independently configured as either an input or an
output using the GPIO direction register (GPIO_GDIR).
When configured as an output (GPIO_GDIR bit = 1), the value in the data bit in the
GPIO data register (GPIO_DR) is driven on the corresponding GPIO line. When a signal
is configured as an input (GPIO_GDIR bit = 0), the state of the input can be read from
the corresponding GPIO_PSR bit.

GPIO Functional Description
28.4.2 GPIO pad structure
output buffer enable (OBE)
PAD
DSE
Output
Driver
SRE
Driver PUS
SPEED Config
Logic
ODE
Resd
PU / PD / Keeper
PKE Logic
pull_en_b
input buffer enable (IBE)
PU / PD Keeper
IND
Input
Receiver esd clamp or
HYS trigger circuit
Figure 28-3. GPIO pad functional diagram
28.4.2.1 Input Driver

Input driver characteristics
• Selectable Schmitt trigger or CMOS input mode
• Keeper structure with buffer at the input receiver output to Core
• Receiver is tri-stated when I/O supply (OVDD) is powered down. (Keeper at receiver
output keeps its previous state).
28.4.2.1.1 Schmitt trigger

The anti-jamming functionality of the Schmitt trigger is illustrated below.

Vo
Vi
Vt- Vt+
Figure 28-4. Schmitt trigger transfer characteristic
Vt+
noisy input voltage
Vth
Vt-
cmos receiver output with multiple

transitions caused by input noise
noise is filtered out in receiver with

hysteresis mode
time
Figure 28-5. Receiver output in CMOS and hysteresis
28.4.2.1.2 Input keeper

A simple latch to hold the input value when OVDD is powered down, or the first inverter
is tri-stated. Input buffer’s keeper is always enabled for all the pads.
28.4.2.2 Output driver

Output driver characteristics
• Selectable CMOS or open-drain output type

• Selectable pull-keeper enable signal to enable/disable the pull-up/down and output

keeper
• Selectable pull-up resistors of 22K, 47K, 100K and a pull-down resistor of
100KOhm. Unsilicided P+ poly resistor is used to limit resistance variation to within
± 20%.
• Internal pull-up, pull-down resistors, and pad keeper are disabled in output mode.
• Seven drive strengths in each operating mode
• Additional 2-bit slew rate control to select between 50, 100, and 200 MHz IO cell
operation range with reduced switching noise
OVDD
OVDD
Predriver
do
Vpad
Output buffer
OVSS
OVSS
Figure 28-6. Output Driver Functional Diagram
28.4.2.2.1 Drive strength

Drive strength selection can be use to make the impedance matched and get better signal
integrity.
28.4.2.2.2 Output keeper

A simple latch to hold the input value.

measure
PKE = VDD
keeper_n
OVDD
DO
pad
OBE
keeper_p OVDD
OVDD
Figure 28-7. Keeper functional diagram
28.4.2.2.3 PU / PD / Keeper Logic

When Keeper is enabled, the pull-up and pull-down are disabled, and the output value of
the pad depends on the Keeper. The output keeper is powered by OVDD. When the core
VDD is powered down or the first inverter is tri-stated, the pad’s state can be kept.
Keeper and Pull can’t be enabled together.
28.4.2.2.4 Open drain

Open drain is a circuit technique which allows multiple devices to communication over a
single wire bi-directionally. Open drain drivers usually operate with an external or
internal pull-up resistor that holds the signal line high until a device sinks enough current
to pull the line low, usually used for a bus with multiple devices.

OVDD1 OVDD2
external
If internal pull-up resistor (Rpu) is
Rpu Rpu
used, output level will depend on
OVDD1
If external Rpu is used, output level

will depend on OVDD2
OVSS1
Figure 28-8. Output buffer in open drain mode
28.4.2.3 Operating Frequency

Table 28-9. IO Operating Frequency
DSE Setting SRE / SPEED Setting R_fixture (Ohm) R_fixture (Ohm) Operating Frequency
(MHz)
OVDD = 1.8V nominal OVDD = 3.3V nominal
1 0 400 220 50
1 100
10 100
11 100
100 50
101 100
110 100
111 150
10 0 200 110 50
1 100
10 100
11 100
100 50
101 100
110 100
111 150
11 0 132 73 50
1 100

Table 28-9. IO Operating Frequency (continued)

(MHz)
10 100
11 100
100 50
101 100
110 100
111 150
100 0 104 58 50
1 100
10 100
11 100
100 50
101 100
110 100
111 150
101 0 83 46 50
1 100
10 100
11 100
100 50
101 100 (OVDD=1.8V nom)
150 (OVDD=3.3V nom)
110 100 (OVDD=1.8V nom)
150 (OVDD=3.3V nom)
111 150 (OVDD=1.8V nom)
200 (OVDD=3.3V nom)
110 0 70 38 50
1 100
10 100
11 100
100 50
101 150
110 150
111 200
111 0 55 32 50
1 100
10 100
11 100
100 50

Table 28-9. IO Operating Frequency (continued)

(MHz)
101 150
110 150
111 200
28.4.3 GPIO Programming
28.4.3.1 GPIO Read Mode

The programming sequence for reading input signals should be as follows:
1. Configure IOMUX to select GPIO mode (Via IOMUX Controller (IOMUXC) ).
2. Configure GPIO direction register to input (GPIO_GDIR[GDIR] set to 0b).
3. Read value from data register/pad status register.
A pseudocode description to read [input3:input0] values is as follows:
// SET INPUTS TO GPIO MODE.
write sw_mux_ctl_<input0>_<input1>_<input2>_<input3>, 32'h00000000
// SET GDIR TO INPUT.
write GDIR[31:4,input3_bit, input2_bit, input1_bit, input0_bit,] 32'hxxxxxxx0
// READ INPUT VALUE FROM DR.
read DR
// READ INPUT VALUE FROM PSR.
read PSR
NOTE
While the GPIO direction is set to input (GPIO_GDIR = 0), a
read access to GPIO_DR does not return GPIO_DR data.
Instead, it returns the GPIO_PSR data, which is the
corresponding input signal value.
28.4.3.2 GPIO Write Mode

The programming sequence for driving output signals should be as follows:
1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
to read loopback pad value through PSR
2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
3. Write value to data register (GPIO_DR).

A pseudocode description to drive 4'b0101 on [output3:output0] is as follows:
// SET PADS TO GPIO MODE VIA IOMUX.

write sw_mux_ctl_pad_<output[0-3]>.mux_mode, <GPIO_MUX_MODE>
// Enable loopback so we can capture pad value into PSR in output mode
write sw_mux_ctl_pad_<output[0-3]>.sion, 1
// SET GDIR=1 TO OUTPUT BITS.
write GDIR[31:4,output3_bit,output2_bit, output1_bit, output0_bit,] 32'hxxxxxxxF
// WRITE OUTPUT VALUE=4’b0101 TO DR.
write DR, 32'hxxxxxxx5
// READ OUTPUT VALUE FROM PSR ONLY.
read_cmp PSR, 32'hxxxxxxx5
28.4.4 Interrupt Control Unit

In addition to the general-purpose input/output function, the edge-detect logic in the
GPIO peripheral reflects whether a transition has occurred on a given GPIO signal that is
configured as an input (GDIR bit = 0). The interrupt control registers (GPIO_ICR1 and
GPIO_ICR2) may be used to independently configure the interrupt condition of each
input signal (low-to-high transition, high-to-low transition, low, or high). For information
about GPIO_ICR1 and GPIO_ICR2 settings, see GPIO Memory Map/Register
Definition.
The interrupt control unit is built of 32 interrupt control subunits, where each subunit
handles a single interrupt line.
28.5 GPIO Memory Map/Register Definition
There are eight 32-bit GPIO registers. All registers are accessible from the IP interface.
Only 32-bit access is supported.
The GPIO memory map is shown in the following table.
GPIO memory map
Absolute
Width Section/
(in bits) page
(hex)
209_C000 GPIO data register (GPIO1_DR) 32 R/W 0000_0000h 28.5.1/1237
209_C004 GPIO direction register (GPIO1_GDIR) 32 R/W 0000_0000h 28.5.2/1238
209_C008 GPIO pad status register (GPIO1_PSR) 32 R 0000_0000h 28.5.3/1239
209_C00C GPIO interrupt configuration register1 (GPIO1_ICR1) 32 R/W 0000_0000h 28.5.4/1239
209_C010 GPIO interrupt configuration register2 (GPIO1_ICR2) 32 R/W 0000_0000h 28.5.5/1243

GPIO Memory Map/Register Definition
GPIO memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
209_C014 GPIO interrupt mask register (GPIO1_IMR) 32 R/W 0000_0000h 28.5.6/1246
209_C018 GPIO interrupt status register (GPIO1_ISR) 32 w1c 0000_0000h 28.5.7/1247
209_C01C GPIO edge select register (GPIO1_EDGE_SEL) 32 R/W 0000_0000h 28.5.8/1248
20A_0000 GPIO data register (GPIO2_DR) 32 R/W 0000_0000h 28.5.1/1237
20A_0004 GPIO direction register (GPIO2_GDIR) 32 R/W 0000_0000h 28.5.2/1238
20A_0008 GPIO pad status register (GPIO2_PSR) 32 R 0000_0000h 28.5.3/1239
20A_000C GPIO interrupt configuration register1 (GPIO2_ICR1) 32 R/W 0000_0000h 28.5.4/1239
20A_0010 GPIO interrupt configuration register2 (GPIO2_ICR2) 32 R/W 0000_0000h 28.5.5/1243
20A_0014 GPIO interrupt mask register (GPIO2_IMR) 32 R/W 0000_0000h 28.5.6/1246
20A_0018 GPIO interrupt status register (GPIO2_ISR) 32 w1c 0000_0000h 28.5.7/1247
20A_001C GPIO edge select register (GPIO2_EDGE_SEL) 32 R/W 0000_0000h 28.5.8/1248
20A_C000 GPIO data register (GPIO5_DR) 32 R/W 0000_0000h 28.5.1/1237
20A_C004 GPIO direction register (GPIO5_GDIR) 32 R/W 0000_0000h 28.5.2/1238
20A_C008 GPIO pad status register (GPIO5_PSR) 32 R 0000_0000h 28.5.3/1239
20A_C00C GPIO interrupt configuration register1 (GPIO5_ICR1) 32 R/W 0000_0000h 28.5.4/1239
20A_C010 GPIO interrupt configuration register2 (GPIO5_ICR2) 32 R/W 0000_0000h 28.5.5/1243
20A_C014 GPIO interrupt mask register (GPIO5_IMR) 32 R/W 0000_0000h 28.5.6/1246
20A_C018 GPIO interrupt status register (GPIO5_ISR) 32 w1c 0000_0000h 28.5.7/1247
20A_C01C GPIO edge select register (GPIO5_EDGE_SEL) 32 R/W 0000_0000h 28.5.8/1248
20B_0000 GPIO data register (GPIO6_DR) 32 R/W 0000_0000h 28.5.1/1237
20B_0004 GPIO direction register (GPIO6_GDIR) 32 R/W 0000_0000h 28.5.2/1238
20B_0008 GPIO pad status register (GPIO6_PSR) 32 R 0000_0000h 28.5.3/1239

GPIO memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
20B_000C GPIO interrupt configuration register1 (GPIO6_ICR1) 32 R/W 0000_0000h 28.5.4/1239
20B_0010 GPIO interrupt configuration register2 (GPIO6_ICR2) 32 R/W 0000_0000h 28.5.5/1243
20B_0014 GPIO interrupt mask register (GPIO6_IMR) 32 R/W 0000_0000h 28.5.6/1246
20B_0018 GPIO interrupt status register (GPIO6_ISR) 32 w1c 0000_0000h 28.5.7/1247
20B_001C GPIO edge select register (GPIO6_EDGE_SEL) 32 R/W 0000_0000h 28.5.8/1248
20B_4000 GPIO data register (GPIO7_DR) 32 R/W 0000_0000h 28.5.1/1237
20B_4004 GPIO direction register (GPIO7_GDIR) 32 R/W 0000_0000h 28.5.2/1238
20B_4008 GPIO pad status register (GPIO7_PSR) 32 R 0000_0000h 28.5.3/1239
20B_400C GPIO interrupt configuration register1 (GPIO7_ICR1) 32 R/W 0000_0000h 28.5.4/1239
20B_4010 GPIO interrupt configuration register2 (GPIO7_ICR2) 32 R/W 0000_0000h 28.5.5/1243
20B_4014 GPIO interrupt mask register (GPIO7_IMR) 32 R/W 0000_0000h 28.5.6/1246
20B_4018 GPIO interrupt status register (GPIO7_ISR) 32 w1c 0000_0000h 28.5.7/1247
20B_401C GPIO edge select register (GPIO7_EDGE_SEL) 32 R/W 0000_0000h 28.5.8/1248
28.5.1 GPIO data register (GPIOx_DR)

The 32-bit GPIO_DR register stores data that is ready to be driven to the output lines. If
the IOMUXC is in GPIO mode and a given GPIO direction bit is set, then the
corresponding DR bit is driven to the output. If a given GPIO direction bit is cleared, then
a read of GPIO_DR reflects the value of the corresponding signal.Two wait states are
required in read access for synchronization.
The results of a read of a DR bit depends on the IOMUXC input mode settings and the
corresponding GDIR bit as follows:
• If GDIR[n] is set and IOMUXC input mode is GPIO, then reading DR[n] returns the
contents of DR[n].
• If GDIR[n] is cleared and IOMUXC input mode is GPIO, then reading DR[n] returns
the corresponding input signal's value.
• If GDIR[n] is set and IOMUXC input mode is not GPIO, then reading DR[n] returns
the contents of DR[n].
• If GDIR[n] is cleared and IOMUXC input mode is not GPIO, then reading DR[n]
always returns zero.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOx_DR field descriptions

Field Description
DR Data bits. This register defines the value of the GPIO output when the signal is configured as an output
(GDIR[n]=1). Writes to this register are stored in a register. Reading GPIO_DR returns the value stored in
the register if the signal is configured as an output (GDIR[n]=1), or the input signal's value if configured as
an input (GDIR[n]=0).
NOTE: The I/O multiplexer must be configured to GPIO mode for the GPIO_DR value to connect with the
signal. Reading the data register with the input path disabled always returns a zero value.
28.5.2 GPIO direction register (GPIOx_GDIR)
GPIO_GDIR functions as direction control when the IOMUXC is in GPIO mode. Each
bit specifies the direction of a one-bit signal. The mapping of each DIR bit to a
corresponding SoC signal is determined by the SoC's pin assignment and the IOMUX
table. For more details consult the IOMUXC chapter.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
GDIR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_GDIR field descriptions

Field Description
GDIR GPIO direction bits. Bit n of this register defines the direction of the GPIO[n] signal.
NOTE: GPIO_GDIR affects only the direction of the I/O signal when the corresponding bit in the I/O MUX
is configured for GPIO.
0 INPUT — GPIO is configured as input.

1 OUTPUT — GPIO is configured as output.

28.5.3 GPIO pad status register (GPIOx_PSR)
GPIO_PSR is a read-only register. Each bit stores the value of the corresponding input
signal (as configured in the IOMUX). This register is clocked with the ipg_clk_s clock,
meaning that the input signal is sampled only when accessing this location. Two wait
states are required any time this register is accessed for synchronization.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PSR field descriptions

Field Description
PSR GPIO pad status bits (status bits). Reading GPIO_PSR returns the state of the corresponding input signal.
Settings:
NOTE: The IOMUXC must be configured to GPIO mode for GPIO_PSR to reflect the state of the
corresponding signal.
28.5.4 GPIO interrupt configuration register1 (GPIOx_ICR1)
GPIO_ICR1 contains 16 two-bit fields, where each field specifies the interrupt
configuration for a different input signal.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 ICR9 ICR8
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_ICR1 field descriptions

Field Description
31–30 Interrupt configuration 1 fields. This register controls the active condition of the interrupt function for GPIO
ICR15 interrupt 15.
GPIOx_ICR1 field descriptions (continued)

Field Description
Settings:
Bits ICRn[1:0] determine the interrupt condition for signal n as follows:
00 LOW_LEVEL — Interrupt n is low-level sensitive.

01 HIGH_LEVEL — Interrupt n is high-level sensitive.
10 RISING_EDGE — Interrupt n is rising-edge sensitive.
11 FALLING_EDGE — Interrupt n is falling-edge sensitive.
ICR14 interrupt 14.
Settings:

ICR13 interrupt 13.
Settings:

ICR12 interrupt 12.
Settings:

ICR11 interrupt 11.
Settings:

ICR10 interrupt 10.
Settings:


Field Description

ICR9 interrupt 9.
Settings:

ICR8 interrupt 8.
Settings:

ICR7 interrupt 7.
Settings:

ICR6 interrupt 6.
Settings:

ICR5 interrupt 5.
Settings:


Field Description
ICR4 interrupt 4.
Settings:

ICR3 interrupt 3.
Settings:

ICR2 interrupt 2.
Settings:

ICR1 interrupt 1.
Settings:

ICR0 Interrupt configuration 1 fields. This register controls the active condition of the interrupt function for GPIO
interrupt 0.
Settings:



Field Description
28.5.5 GPIO interrupt configuration register2 (GPIOx_ICR2)
GPIO_ICR2 contains 16 two-bit fields, where each field specifies the interrupt
configuration for a different input signal.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_ICR2 field descriptions

Field Description
ICR31 interrupt 31.
Settings:

ICR30 interrupt 30.
Settings:

ICR29 interrupt 29.


Field Description
Settings:

ICR28 interrupt 28.
Settings:

ICR27 interrupt 27.
Settings:

ICR26 interrupt 26.
Settings:

ICR25 interrupt 25.
Settings:

ICR24 interrupt 24.
Settings:


Field Description

ICR23 interrupt 23.
Settings:

ICR22 interrupt 22.
Settings:

ICR21 interrupt 21.
Settings:

ICR20 interrupt 20.
Settings:

ICR19 interrupt 19.
Settings:


Field Description
ICR18 interrupt 18.
Settings:

ICR17 interrupt 17.
Settings:

ICR16 Interrupt configuration 2 fields. This register controls the active condition of the interrupt function for GPIO
interrupt 16.
Settings:

28.5.6 GPIO interrupt mask register (GPIOx_IMR)
GPIO_IMR contains masking bits for each interrupt line.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOx_IMR field descriptions

Field Description
IMR Interrupt Mask bits. This register is used to enable or disable the interrupt function on each of the 32 GPIO
signals.
Settings:
Bit IMR[n] (n=0...31) controls interrupt n as follows:
0 MASKED — Interrupt n is disabled.

1 UNMASKED — Interrupt n is enabled.
28.5.7 GPIO interrupt status register (GPIOx_ISR)
The GPIO_ISR functions as an interrupt status indicator. Each bit indicates whether an
interrupt condition has been met for the corresponding input signal. When an interrupt
condition is met (as determined by the corresponding interrupt condition register field),
the corresponding bit in this register is set. Two wait states are required in read access for
synchronization. One wait state is required for reset.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_ISR field descriptions

Field Description
ISR Interrupt status bits - Bit n of this register is asserted (active high) when the active condition (as
determined by the corresponding ICR bit) is detected on the GPIO input and is waiting for service. The
value of this register is independent of the value in GPIO_IMR.
When the active condition has been detected, the corresponding bit remains set until cleared by software.
Status flags are cleared by writing a 1 to the corresponding bit position.

28.5.8 GPIO edge select register (GPIOx_EDGE_SEL)
GPIO_EDGE_SEL may be used to override the ICR registers' configuration. If the

GPIO_EDGE_SEL bit is set, then a rising edge or falling edge in the corresponding
signal generates an interrupt. This register provides backward compatibility. On reset all
bits are cleared (ICR is not overridden).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
GPIO_EDGE_SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_EDGE_SEL field descriptions

Field Description
GPIO_EDGE_ Edge select. When GPIO_EDGE_SEL[n] is set, the GPIO disregards the ICR[n] setting, and detects any
SEL edge on the corresponding input signal.

Chapter 29
General Purpose Media Interface (GPMI)
29.1 Overview
The GPMI controller is a flexible interface to supporting up to four NAND flash chip
selects.
• ONFI 2.2, DDR Mode, Samsung / Toshiba Toggle NAND protocol compatible.
• Fully configurable address and command behavior, providing support for future
devices not yet specified.
The GPMI resides on the APBH. The GPMI also provides an interface to the BCH
module to allow direct parity processing.
Registers are clocked on the HCLK domain. The I/O and pin timing are clocked on a
dedicated GPMICLK domain. GPMICLK can be set to maximize I/O performance.
The following figure shows a block diagram of the GPMI controller.

External Signals
Arm Core SRAM System Clock

Generator
AMBA
APBHDMA
AHB SLAVE AHB MASTER
GPMICLK
HCLK
SHARED DMA
DMA Request 3
DMA Request 2
DMA Request 0
DMA Request 1
APBH MASTER
APBH
GPMI DMA Interface State Machine
BCH GPMI FIFO
GPMI GPMI Pin State Machine div2
Other Modules GPIO
GPMI / Memory /
GPIO Pin Mux
Pins
Figure 29-1. General-Purpose Media Interface Controller Block Diagram

Chapter 29 General Purpose Media Interface (GPMI)

The table found here describes the external signals of GPMI.
Table 29-1. GPMI External Signals
NAND_ALE Address latch enable signal NANDF_ALE ALT0 O
NAND_CE0_B Chip enable signal NANDF_CS0 ALT0 O
NAND_CLE Command latch enable signal NANDF_CLE ALT0 O
NAND_DATA00 Data signal NANDF_D0 ALT0 I/O
NAND_DQS DQS signal SD4_DAT0 ALT2 I/O
NAND_READY Ready signal NANDF_RB0 ALT0 I/O
NAND_RE_B Read enable signal SD4_CMD ALT1 O
NAND_WE_B Write enable signal SD4_CLK ALT1 O
NAND_WP_B Wait polarity signal NANDF_WP_B ALT0 O
29.3 Clocks
The table found here describes the clock sources for GPMI.
information.
Table 29-2. GPMI Clocks
bch_input_apb_clk usdhc3_clk_root BCH to APBH input clock
gpmi_bch_input_bch_cl usdhc4_clk_root BCH input clock
k
gpmi_bch_input_gpmi_i enfc_clk_root GPMI IO input clock
o_clk
gpmi_input_apb_clk usdhc3_clk_root GPMI to APBH clock

GPMI NAND Mode
29.4 GPMI NAND Mode

The general-purpose media interface has several features to efficiently support NAND:
• Individual chip select pins and ganged ready/busy pin for up to four NANDs.
• Individual state machine and DMA channel for each chip select.
• Special command modes work with DMA controller to perform all normal NAND
functions without CPU intervention.
• Configurable timing based on a dedicated clock allows optimal balance of high
NAND performance and low system power.
GPMI and DMA have been designed to handle complex multi-page operations without
CPU intervention. The DMA uses a linked descriptor function with branching capability
to automatically handle all of the operations needed to read/write multiple pages:
• Data/Register Read/Write-The GPMI can be programmed to read or write multiple
cycles to the NAND address, command or data registers.
• Wait for NAND Ready-The GPMI's Wait-for-Ready mode can monitor the ready/
busy signal of a single NAND flash and signal the DMA when the device has
become ready. It also has a time-out counter and can indicate to the DMA that a
time-out error has occurred. The DMAs can conditionally branch to a different
descriptor in the case of an error.
• Check Status-The Read-and-Compare mode allows the GPMI to check NAND
status against a reference. If an error is found, the GPMI can instruct the DMA to
branch to an alternate descriptor, which attempts to fix the problem or asserts a CPU
IRQ.
29.4.1 Multiple NAND Support

The GPMI supports up to four NAND chip selects, with ganged ready/busy pins. Since
they share a data bus and control lines, the GPMI can only actively communicate with a
single NAND at a time. However, all NANDs can concurrently perform internal read,
write, or erase operations. With fast NAND flash and software support for concurrent
NAND operations, this architecture allows the total throughput to approach the data bus
speed, which can be as high as 50 MB/s (8-bit bus running at 50 MHz single clock edge)
in asynchronous mode and 200MB/s (8-bit bus running at 100MHz both clock edges) in
Source Synchronous mode.

There are two options for controlling the four NAND chip selects via the DMA interface.
The first option is the one to one mapping, where the each DMA channel is tied to its
own NAND chip select. For example DMA channel 'n' accesses only NAND attached to
chip select 'n'. The second option is the decoupled mode where a DMA channel can
access any or all NAND chip selects connected to the GPMI. A DMA channel will
signify the NAND chip select it wants to access by writing its chip select value in the
GPMI_CTRL0[CS] field and setting the GPMI_CTRL1[DECOUPLE_CS] to 1. This
option is useful if software chooses to use only one DMA channel to access all the
attached NAND devices.
29.4.2 GPMI NAND Timing and Clocking

The dedicated clock, GPMICLK, is used as a timing reference for NAND flash I/O. Since
various NANDs have different timing requirements, GPMICLK may need to be adjusted
for each application.
While the actual pin timings are limited by the NAND chips used and the I/O pad
configuration, the GPMI can support data bus speeds of up to 200 MHz x 8 bits. The
actual read/write strobe timing parameters are adjusted as indicated in the register
descriptions in Memory Map.
29.4.3 Basic NAND Timing
29.4.3.1 NAND Asynchronous Timing

Figure 29-3 and illustrates the operation of the output (from host to device) timing
parameters in NAND ONFI asynchronous mode.

GPMI NAND Mode
dev_clk
CE0_B
CLE/ CLE = HW_GPMI_CTRL0.bit18 (ADDRESS[1])

0 0
ALE ALE = HW_GPMI_CTRL0.bit17 (ADDRESS[0])
tAS tDS tDH tDS tDH tDS tDH tDS tDH
WE_B
1 cycle
DATA[07:00]
as
Output No.1 No.2 No.(n-1) No.n
output[7:0] output[7:0] output[7:0] output[7:0]
from
device
1 cycle
Host controller drives the DATA[07:00] bus

And also don't care if device will drive that or not and what will be drived
Host controller drives the DATA[07:00] bus, but

the data in the DATA[07:00] should be ignored by the device
- tAS is configurable by programming HW_GPMI_TIMING0 Address_Setup: in this example, Address_Setup = 4, tAS is equal to 4 dev_clk cycles.
- tDS is configurable by programming HW_GPMI_TIMING0 Data_Setup; in this example, Data_Setup = 3, tDS is equal to 3 dev_clk cycles
- tDH is configuarble by programming HW_GPMI_TIMING0 Data_Hold: in this example, Data_Hold = 2, tDH is equal to 2 dev_clk cycles
- tAS/tDS/tDH will extend, if the output data is not ready in device fifo.
Figure 29-2. Asynchronous Mode Basic Write Timing Diagram (command write, address
write, or data write

tCK
dev_clk
CE0_B
CLE/ CLE = HW_GPMI_CTRL0.bit18 (ADDRESS[1])

0 0
ALE ALE - HW_GPMI_CTRL0.bit17 (ADDRESS[0])
tAS tDS tDH tDS tDH tDS tDH tDS tDH
RE_B 1 cycle or more

1 cycle
tRD tRD tRD tRD
read data
DATA[07:00] sampling edge
as
No. 1 No. 2 No. (n-1) No. (n-1)
input
input input input input
from
device
- tAS is configurable by programming HW_GPMI_TIMING0 Address_Setup: in this example, Address_Setup = 4, tAS is equal to 4 dev_clk cycles.
- tDS is configurable by programming HW_GPMI_TIMING0 Data_Setup; in this example, Data_Setup = 3, tDS is equal to 3 dev_clk cycles
- tDH is configuarble by programming HW_GPMI_TIMING0 Data_Hold: in this example, Data_Hold = 2, tDH is equal to 2 dev_clk cycles
- tRD is the delay from RE_B rising edge to the read datas ampling edge. If SDR DLL is not enabled, tRD is 0. If SDR DLL enabled, the delay depends on SDR DLL delay.
Host controller drives the DATA[07:00] bus

ONFI asynchronous mode basic read timing diagram

(data read)
Figure 29-3. ONFI Asynchronous Mode Basic Read Timing Diagram (data read)
29.4.3.2 NAND Asynchronous EDO Mode Timing

In high-speed NANDS, the read data may not be valid until after the read strobe
(NAND_RE_B) deasserts. This is the case when the minimum tDS is programmed to
achieve higher bandwidth.
The GPMI implements a feedback read strobe to sample the read data. The feedback read
strobe can be delayed to support fast nand EDO (Extended Data Out) timing where the
read strobe may deassert before the read data is valid, and read data is valid for some time
after read strobe. Nand EDO timings is applied typically for read cycle frequency above
33 MHz. See Figure 29-4.
The GPMI provides control over the amount of delay applied to the feedback read strobe.
This delay depends on the maximum read access time (tREA) of the nand and the read
pulse width (tRP) used to access the nand. tRP is specified by
GPMI_TIMING0[DATA_SETUP] register. When (tREA + 4ns) is less than tRP, no

GPMI NAND Mode
delay is required to sample to nand read data. (The 4ns provides adequate data setup time
for the GPMI.) In this case set GPMI_CTRL1[HALF_PERIOD] = 0;
GPMI_CTRL1[RDN_DELAY] = 0; GPMI_CTRL1[DLL_ENABLE] = 0.
When (tREA + 4ns) is greater than or equal to tRP, a delay of the feedback read strobe is
required to sample to nand read data. This delay is equal to the difference between these
two timings:
DELAY = tREA + 4ns - tRP.
Since the GPMI delay chain is limited to 12ns maximum, if DELAY > 12ns then increase
tRP by increasing the value of GPMI_TIMING0[DATA_SETUP] until DELAY is less
than or equal to 12ns.
The GPMI programming for this DELAY depends on the GPMICLK period. The GPMI
DLL will not function properly if the GPMICLK period is greater than 24ns: disable the
DLL if this is the case. If the GPMICLK period is greater than 12ns (and not greater than
24ns), set the GPMI_CTRL1[HALF_PERIOD]=1; This will cause the DLL reference
period (RP) to be one-half of the GPMICLK period. If the GPMICLK period is 12ns or
less then set the GPMI_CTRL1[HALF_PERIOD]=0; This will cause the DLL reference
period (RP) to be equal to the GPMICLK period. DELAY is a multiple (0 to 1.875) of
RP.
The GPMI_CTRL1[RDN_DELAY] is encoded as a 1-bit integer and 3-bit fraction delay
factor. DELAY is a multiple of the delay factor and the reference period. See table below
for details.
Table 29-3. RDN DELAY
HW_GPMI_CTRL1[RDN_DELAY] Delay Factor
0 0.000
1 0.125
2 0.250
3 0.375
4 0.500
5 0.625
6 0.750
7 0.875
8 1.000
9 1.125
10 1.250
11 1.375
12 1.500
13 1.625

Table 29-3. RDN DELAY (continued)

HW_GPMI_CTRL1[RDN_DELAY] Delay Factor
14 1.750
15 1.875
DELAY = DelayFactor x RP or DELAY = GPMI_CTRL1[RDN_DELAY] x 0.125 x RP.

Use this equation to calculate the value for GPMI_CTRL1[RDN_DELAY]. Then set
GPMI_CTRL1[DLL_ENABLE]=1.
GPMI NAND Read Path Timing Diagram (Non-EDO)
tRP
tREA
RE_B
ReadData A B C
Feedback RE_B
(tREA + 4 ns) is less than tRP, no delay is required on rising edge of Feedback RDN to sample Read Data
GPMI NAND Read Path Timing Diagram (EDO mode)
tREA
tRP
RE_B
Read Data A B C
Delay
Feedback RE_B
Where (tREA + 4 ns) is greater than or equal to tRP, a delay of the Feedback RDN is required to sample to nand read data
Figure 29-4. NAND Read Path Timing
For example, a NAND with tREAmax = 20 ns, tRPmin = 12 ns, and tRCmin = 25 ns
(read cycle time) may be programmed as follows:
• GPMICLK clock frequency: Consider 480/6 = 80 MHz which is 12.5 ns clock
period. This is too close to the minimum NAND spec if we program the data setup
and hold to 1 GPMICLK cycle. Consider 480/7=68.57 MHz which is 14.58 ns clock
period. With data setup and hold set to 1, we have a tRP of 14.58ns and a tRC of
29.16 ns (good margins).
• Since (tREA +4ns) is greater than tRP, required DELAY = tREA + 4ns - tRP = 20 +
4 - 14.58ns = 9.42 ns.

GPMI NAND Mode
• GPMI_CTRL1[HALF_PERIOD] =1, since GPMICLK period is large than 12ns. So

RP=GPMICLK period = 7.29ns.
• DELAY = GPMI_CTRL1[RDN_DELAY] x 0.125 x RP. 9.42 ns =
GPMI_CTRL1[RDN_DELAY] x 0.125 x 7.29ns. GPMI_CTRL1[RDN_DELAY] =
10 (round of 10.33)
For ONFI spec EDO timing mode 4/5, It's recommended to have below settings.
EDO timing mode 5 :
GPMICLK=100MHz;GPMI_CTRL1[RDN_DELAY]=8;GPMI_CTRL1[HALF_PERIO
D] =0;
EDO timing mode 4 :
GPMICLK=80MHz;GPMI_CTRL1[RDN_DELAY]=15;GPMI_CTRL1[HALF_PERIO
D] =1;
NOTE
It is recommended that the drive strength of NAND_RE_B and
NAND_WE_B output pins be set to 8 mA. This will reduce the
transition time under heavy loads. Low transition times will be
important when NAND interface read and write cycle times are
below 30 ns. The other GPMI pins may remain at 4 mA, since
their frequency is only up to half that of NAND_RE_B and
NAND_WE_B.
29.4.3.3 NAND ONFI Source Synchronous Mode Timing

NOTE
In the following figures, CLK shares the same pin as WE_B in
Async Mode. And W/R# shares the same pin as RE_B in Async
Mode.

tCH
tCE
CE_B
CLE
tCAS
tCAH
ALE
tCK
CLK
W/R#
DQS
DQS
output
enable
CMD
DATA[07:00]
DATA[07:00]
tPRE tPOST
Output
Enable
Host controller does not drives the DATA[07:00] bus


tCK is equal to device clock period

tCAS = 0.5 * tCK
tCAH = 0.5 * tCK
tCE = HW_GPMI_TIMING2.CE_DELAY * tCK
tCH = 0.5 * tCK
tPRE = HW_GPMI_TIMING2.PREAMBLE_DELAY * tCK
tPOST = HW_GPMI_TIMING2.POST_DELAY * tCK
Figure 29-5. ONFI Source Synchronous Mode Basic Command Write Timing Diagram

GPMI NAND Mode
tCH
tCE
CE_B
CLE
tCAS
tCAH
ALE
tCK
CLK
W/R#
DQS
DQS
oen
ADD
DATA[07:00]
DATA[07:00] tPRE tPOST

oen

And also don't care if device will drive that or not and what will be drived.


tCAS = 0.5 * tCK
tCAH = 0.5 * tCK
tCH = 0.5 * tCK
Figure 29-6. ONFI Source Synchronous Mode Basic Address Write Timing Diagram

tCH
tCE
CE_B
tCAS
CLE tCAH
1CMDADDPAUSE 1CMDADDPAUSE
tCAS
ALE tCAH
tCK
CLK
W/R#
DQS
DQS
output
enable
CMD ADD ADD

DATA[07:00]
DATA[07:00]
Output tPRE tPOST
enable

And also do not care if device will drive that or not and what will be drived.

tCAS = 0.5 * tCK
tCAH = 0.5 *tCK
tCH = 0.5 * tCK
tCMDADDPAUSE = HW_GPMI_TIMING2.CMDADD_PAUSE * tCK
Figure 29-7. ONFI Source Synchronous Mode Command + Address Write Timing
Diagram

GPMI NAND Mode
tCH
tCE
CE_B
tDATAPAUSE
tCALS tCALH
CLE
tPRE tCALS tPOST

ALE
tCK
CLK
W/R#
tDQSS tDQSS
tDQSS
DQS
DQS
output
enable
DATA[07:00]
DATA[07:00]
Output
enable



tCE = HW_GPI_TIMING2.CE_DELAY * tCK
tCH = 0.5 * tCK
tCALS = 0.5 * tCK
tCALH = 0.5 * tCK
tPRE = HW_GPMI_TIMING2.PREAMBLE_DELAY *tCK
tDATAPAUSE = HW_GPMI_TIMING2.DATA_PAUSE * tCK
tDQSS = tCK
Figure 29-8. ONFI Source Synchronous Mode Data Write Timing Diagram

tCH
tCE
CE_B
tDATAPAUSE
tCALS tCALH
CLE
tPRE tPOST
ALE
tCK
CLK
tCALS
W/R# tCALS
Internal
DQS input 4 tCK
Valid
window tWRCK tCKWR
tD QSCK tD QSCK tDQSHZ
DQS
tDQSD
DQS
output
enable
DATA[07:00]
DATA[07:00]
Output
enable
Host controller does not drive the DATA[07:00] bus



tCE = HW_GPI_TIMING2.CE_DELAY * tCK
tCH = 0.5 * tCK
tCALS = 0.5 * tCK
tCALH = 0.5 * tCK
tPRE = HW_GPMI_TIMING2.PREAMBLE_DELAY *tCK
tDATAPAUSE = HW_GPMI_TIMING2.DATA_PAUSE * tCK
tWRCK/tCKWR/tDQSD/tDASCK/tDASHZ are device parameters
Figure 29-9. ONFI Source Synchronous Mode Data Read Timing Diagram

GPMI NAND Mode
29.4.3.4 NAND Toggle Mode Timing
dev_clk
CE_B
1 cycle 1 cycle
CLE
ALE
tDS
WE_B
tAS tDH
RE_B
DQS
0.51CK 0.51CK
DATA[07:00] as
Output to
command
device

And also does not care if device will drive that or not and what will be drived.

- tAS is configurable by programming HW_GPMI_TIMING0 Address_Setup;

- tDS is configurable by programming HW_GPMI_TIMING0 Data_Setup;
- tDH is configurable br programming HW_GPMI_TIMING Data_Hold;
Figure 29-10. Samsung Toggle Mode Basic Command Write Timing Diagram

dev_clk
CE_B
1 cycle 1 cycle
CLE
ALE
tDS
WE_B
tAS tDH
RE_B
DQS
0.5 tCK 0.5 tCK

IDATA[07:00] as
Output to
address
device



- tDS is configurable by programming HW_GPMI_TIMING0 Data_Setup;
- tDH is configurable br programming HW_GPMI_TIMING Data_Hold;
Figure 29-11. Samsung Toggle Mode Basic Address Write Timing Diagram

GPMI NAND Mode
Not lock cs
CE_B lock cs
1 cycle
1 cycle
address increment
CLE
ALE
tDS tDS tDS tDS tDS tDS

WE_B
tAS tDH tDH tDH tDH tDH tDH
RE_B Program command 0x80/81/85 sent,

1 cycle
host will drive DQS to 1
DQS
Program command not sent,

host will not drive DQS
DATA[07:00] as
Output to
command address address address address address
device


- tAS is configurable by programming HW_GPMI_TIMING0 Address_Setup.

- tDS is configurable by programming HW_GPMI_TIMING0 Data_Setup
- tDH is configurable br programming HW_GPMI_TIMING Data_Hold
Figure 29-12. Samsung Toggle Mode Basic Command + Address Timing Diagram

dev_clk
0
CE_B
0
CEL
0
ALE
WE_B 1
RE_B 1
tPRE 1tCK tPOST Idle cycles
DQS
1tCK tDATAPAUSE 0.5 tCK
0.5 tCK
DATA[07:00]
Host controller does not drive the DATA[07:00] bus.

It also does not care if the device will drive or what will be driven.

the data in the DATA[07:00] should be ignored by device.

tCE = HW_GPMI_TIMIN G2.CE_DELAY* tCK
tPRE = HW_GPMI_TIMIN G2.PREAMBLE_DELAY* tCK
tPOST = HW_GPMI_TIMIN G2.POSTAMBLE_DELAY* tCK
tDATAPAUSE = HW_GPMI_TIMIN G2.DATA_PAUSE* tCK
Figure 29-13. Toggle Mode Data Write Timing Diagram

GPMI NAND Mode
dev_clk
CE_B
tCE
CEL
ALE
WE_B 1 1tCK
1tCK tPOST 1tCK
RE_B tPRE tDATAPAUSE
tDQSRE
tDQSRE
tDQSRE tCHZ
DQS
DATA[07:00]
Host controller does not drive the DATA[07:00] bus.

It also does not care if the device will drive or what will be driven.
the data in the DATA[07:00] should be ignored by device.
tCE = HW_GPMI_TIMIN G2.CE_DELAY* tCK
tPRE = HW_GPMI_TIMIN G2.PREAMBLE_DELAY* tCK
tPOST = HW_GPMI_TIMIN G2.POSTAMBLE_DELAY* tCK
tDATAPAUSE = HW_GPMI_TIMIN G2.DATA_PAUSE* tCK
Figure 29-14. Toggle Mode Data Read Timing Diagram

dev_clk
lock cs
CE_B
1 tCK address increment
CLE
ALE
1 tCK
tDS tDS tDS tDS tDS

tDS
WE_B
tDH
tAS tAS tDH tDH tDH tDH tDH
RE_B
1 tCK
DQS
0.5 tCK
0.5 tCK
Command
DATA[07:00] 0x80/81/85
address address address address address

And also does not care if device will drive that or not and what will be drived. A
Figure 29-15. Toggle Mode Program Timing Diagram (A)

GPMI NAND Mode
dev_clk
lock cs
CE_B
Idle cycles
CLE
1 tCK
1 tCK
ALE
WE_B
tCE
RE_B tPRE
Idle cycles
1 tCK 1 tCK tPOST
DATA PAUSE
DQS
0.5 tCK 0.5 tCK
0.5 tCK
DATA[07:00] address
A B


Figure 29-16. Toggle Mode Program Timing Diagram (B)

dev_clk
idle cycles
CE_B
CLE 1 tCK 1 tCK
ALE
tDS
WE_B
tAS tDH
RE_B
tPOST
0.5 tCK 1 tCK
DQS
0.5 tCK 0.5 tCK
Command
DATA[07:00]
0x10/11


- tCK is equal to device clock period

- tDS is configuraable by programming HW_GPMI_TIMING0 Data_Setup;
- tDH is configurable programming HW_GPMI_TIMING0 Data_Hold;
- tPOST is configurable by programming HW_GPMI_TIMING2.POST_DELAY;
Figure 29-17. Toggle Mode Program Timing Diagram (C)
29.4.4 Hardware BCH Interface

The GPMI provides an interface to the BCH module. This reduces the SOC bus traffic
and the software involvement.
.
When BCH ECC is enable, parity information is inserted on-the-fly during writes to 8-bit
NAND devices. The BCH will supply payload and parity to the GPMI to write to the
NAND. During NAND reads, parity is checked and ECC processing is performed after
each read block. In this case the GPMI reads the NAND device and redirects the data and
parity to the BCH module for ECC processing.

Behavior During Reset
To program the BCH for NAND writes, remove the soft reset and clock gates from
BCH_CTRL[SFTRST] and BCH_CTRL[CLKGATE]. The bulk of BCH programming is
actually applied to the GPMI via PIO operations embedded in its DMA command
structures. This has a subtle implication when writing to the GPMI ECC registers: access
to the these registers must be written in progressive register order. Thus, to write to the
GPMI_ECCCOUNT register, write first (in order) to registers GPMI_CTRL0,
GPMI_COMPARE, and GPMI_ECCCTRL before writing to GPMI_ECCCOUNT.
These additional register writes need to be accounted for in the CMDWORDS field of the
respective DMA channel command register.
NOTE
Note that the GPMI_PAYLOAD and GPMI_AUXILIARY
pointers need to be word-aligned for proper ECC operation. If
those pointers are non-word-aligned, then the BCH engine will
not operate properly and could possibly corrupt system memory
in the adjoining memory regions.
29.5 Behavior During Reset

A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically.
29.6 GPMI Memory Map/Register Definition
The following registers provide control for programmable elements of the GPMI module.
NOTE
All ATA or UDMA features are not supported for the chip.
NOTE
GPMI does not support the Set feature command in Toggle
mode. The NANDF_DQS output is only enabled in program
operation for Toggle mode, but the Set feature command also
needs to use the NANDF_DQS signal to write data to Toggle
NAND flash. So the Set feature command in Toggle mode is
not supported.

GPMI memory map

Absolute
Width Section/
(in bits) page
(hex)
11_2000 GPMI Control Register 0 Description (GPMI_CTRL0) 32 R/W C000_0000h 29.6.1/1274
11_2004 GPMI Control Register 0 Description (GPMI_CTRL0_SET) 32 R/W C000_0000h 29.6.1/1274
11_2008 GPMI Control Register 0 Description (GPMI_CTRL0_CLR) 32 R/W C000_0000h 29.6.1/1274
11_200C GPMI Control Register 0 Description (GPMI_CTRL0_TOG) 32 R/W C000_0000h 29.6.1/1274
11_2010 GPMI Compare Register Description (GPMI_COMPARE) 32 R/W 0000_0000h 29.6.2/1276
GPMI Integrated ECC Control Register Description
11_2020 32 R/W 0000_0000h 29.6.3/1277
(GPMI_ECCCTRL)
11_2024 32 R/W 0000_0000h 29.6.3/1277
(GPMI_ECCCTRL_SET)
11_2028 32 R/W 0000_0000h 29.6.3/1277
(GPMI_ECCCTRL_CLR)
11_202C 32 R/W 0000_0000h 29.6.3/1277
(GPMI_ECCCTRL_TOG)
GPMI Integrated ECC Transfer Count Register Description
11_2030 32 R/W 0000_0000h 29.6.4/1278
(GPMI_ECCCOUNT)
GPMI Payload Address Register Description
11_2040 32 R/W 0000_0000h 29.6.5/1278
(GPMI_PAYLOAD)
GPMI Auxiliary Address Register Description
11_2050 32 R/W 0000_0000h 29.6.6/1279
(GPMI_AUXILIARY)
11_2060 GPMI Control Register 1 Description (GPMI_CTRL1) 32 R/W 0004_0004h 29.6.7/1280
11_2064 GPMI Control Register 1 Description (GPMI_CTRL1_SET) 32 R/W 0004_0004h 29.6.7/1280
11_2068 GPMI Control Register 1 Description (GPMI_CTRL1_CLR) 32 R/W 0004_0004h 29.6.7/1280
11_206C GPMI Control Register 1 Description (GPMI_CTRL1_TOG) 32 R/W 0004_0004h 29.6.7/1280
11_2070 GPMI Timing Register 0 Description (GPMI_TIMING0) 32 R/W 0001_0203h 29.6.8/1283
11_2080 GPMI Timing Register 1 Description (GPMI_TIMING1) 32 R/W 0000_0000h 29.6.9/1283
29.6.10/
11_2090 GPMI Timing Register 2 Description (GPMI_TIMING2) 32 R/W 0302_3336h
1284
GPMI DMA Data Transfer Register Description 29.6.11/
11_20A0 32 R/W 0000_0000h
(GPMI_DATA) 1285
29.6.12/
11_20B0 GPMI Status Register Description (GPMI_STAT) 32 R 0000_0005h
1285
GPMI Debug Information Register Description 29.6.13/
11_20C0 32 R 0000_0000h
(GPMI_DEBUG) 1288
29.6.14/
11_20D0 GPMI Version Register Description (GPMI_VERSION) 32 R 0501_0000h
1289
GPMI Debug2 Information Register Description 29.6.15/
11_20E0 32 R/W 0000_F100h
(GPMI_DEBUG2) 1289
GPMI Debug3 Information Register Description 29.6.16/
11_20F0 32 R 0000_0000h
(GPMI_DEBUG3) 1292
GPMI Double Rate Read DLL Control Register Description 29.6.17/
11_2100 32 R/W 0000_0038h
(GPMI_READ_DDR_DLL_CTRL) 1293
GPMI Double Rate Write DLL Control Register Description 29.6.18/
11_2110 32 R/W 0000_0038h
(GPMI_WRITE_DDR_DLL_CTRL) 1294

GPMI Memory Map/Register Definition
GPMI memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
GPMI Double Rate Read DLL Status Register Description 29.6.19/
11_2120 32 R 0000_0000h
(GPMI_READ_DDR_DLL_STS) 1296
GPMI Double Rate Write DLL Status Register Description 29.6.20/
11_2130 32 R 0000_0000h
(GPMI_WRITE_DDR_DLL_STS) 1297
29.6.1 GPMI Control Register 0 Description (GPMI_CTRL0n)
The GPMI control register 0 specifies the GPMI transaction to perform for the current
command chain item.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMMAND_MODE
WORD_LENGTH
DEV_IRQ_EN
INCREMENT
ADDRESS_
CLKGATE
LOCK_CS
SFTRST
UDMA
RUN CS ADDRESS
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFER_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_CTRL0n field descriptions

Field Description
31 Set to zero for normal operation. When this bit is set to one (default),
SFTRST
then the entire block is held in its reset state. This will not work if the CLKGATE bit is already set to '1'.
CLKGATE must be cleared to '0' before issuing a soft reset. Also the GPMICLK must be running for this to
work properly.
RUN = 0x0 Allow GPMI to operate normally.
RESET = 0x1 Hold GPMI in reset.
30 Set this bit zero for normal operation. Setting this bit to one (default),
CLKGATE

GPMI_CTRL0n field descriptions (continued)

Field Description
gates all of the block level clocks off for miniminizing AC energy consumption.
RUN = 0x0 Allow GPMI to operate normally.
NO_CLKS = 0x1 Do not clock GPMI gates in order to minimize power consumption.
29 The GPMI is busy running a command whenever this bit is set to '1'. The GPMI is idle whenever this bit
RUN set to zero. This can be set to one by a CPU write. In addition, the DMA sets this bit each time a DMA
command has finished its PIO transfer phase.
IDLE = 0x0 The GPMI is idle.
BUSY = 0x1 The GPMI is busy running a command.
28 When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert.
DEV_IRQ_EN
27 For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete. 1= Continue to assert chip
LOCK_CS select (CS) after RUN is complete.
For Camera Mode: 0= Dont wait for VSYNC rising edge before capturing data. 1= Wait for VSYNC rising
edge before capturing data (Camera mode only).
DISABLED = 0x0 Deassert chip select (CS) after RUN is complete.
ENABLED = 0x1 Continue to assert chip select (CS) after RUN is complete.
26 DISABLED = 0x0 Use ATA-PIO mode on the external bus.
UDMA
ENABLED = 0x1 Use ATA-Ultra DMA mode on the external bus.
0 Use ATA-PIO mode on the external bus.

1 Use ATA-Ultra DMA mode on the external bus.
25–24 WRITE = 0x0 Write mode.
COMMAND_
READ = 0x1 Read mode.
MODE
READ_AND_COMPARE = 0x2 Read and Compare mode (setting sense flop).
WAIT_FOR_READY = 0x3 Wait for Ready mode. For ATA WAIT_FOR_READY command set CS=01.
00 Write mode.
01 Read Mode.
10 Read and Compare Mode (setting sense flop).
11 Wait for Ready.
23 This bit should only be changed when RUN==0.
WORD_LENGTH
Reserve = 0x0 Reserved.
8_BIT = 0x1 8-bit Data Bus mode.
0 Reserved.
1 8-bit Data Bus mode.
22–20 Selects which chip select is active for this command. For ATA WAIT_FOR_READY command, this must
CS be set to b01.
19–17 Specifies the three address lines for ATA mode. In NAND mode, use A0 for CLE and A1 for ALE.
ADDRESS
NAND_DATA = 0x0 In NAND mode, this address is used to read and write data bytes.
NAND_CLE = 0x1 In NAND mode, this address is used to write command bytes.
NAND_ALE = 0x2 In NAND mode, this address is used to write address bytes.


Field Description
16 In ATA mode, the address will increment with each cycle. In NAND mode, the address will increment
ADDRESS_ once, after the first cycle (going from CLE to ALE).
INCREMENT
DISABLED = 0x0 Address does not increment.
ENABLED = 0x1 Increment address.
0 Address does not increment.

1 Increment address.
XFER_COUNT Number of bytes to transfer for this command. A value of zero will transfer 64K bytes.
29.6.2 GPMI Compare Register Description (GPMI_COMPARE)

The GPMI compare register specifies the expect data and the xor mask for comparing to
the status values read from the device. This register is used by the Read and Compare
command.
GPMI_COMPARE 0x010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
MASK REFERENCE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_COMPARE field descriptions

Field Description
31–16 16-bit mask which is applied after the read data is XORed with the REFERENCE bit field.
MASK
REFERENCE 16-bit value which is XORed with data read from the NAND device.

29.6.3 GPMI Integrated ECC Control Register Description

(GPMI_ECCCTRLn)
The GPMI ECC control register handles configuration of the integrated ECC accelerator.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HANDLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
ENABLE_ECC
RSVD2
ECC_CMD BUFFER_MASK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_ECCCTRLn field descriptions

Field Description
31–16 This is a register available to software to attach an identifier to a transaction in progress. This handle will
HANDLE be available from the ECC register space when the completion interrupt occurs.
15 Always write zeroes to this bit field.
RSVD2
14–13 ECC Command information.
ECC_CMD
DECODE = 0x0 Decode.
ENCODE = 0x1 Encode.
RESERVE2 = 0x2 Reserved.
RESERVE3 = 0x3 Reserved.

GPMI_ECCCTRLn field descriptions (continued)

Field Description
12 Enable ECC processing of GPMI transfers.
ENABLE_ECC
ENABLE = 0x1 Use integrated ECC for read and write transfers.
DISABLE = 0x0 Integrated ECC remains in idle.
11–9 Always write zeroes to this bit field.
RSVD1
BUFFER_MASK ECC buffer information. The BCH error correction only allows two configurations of the buffer mask -
software may either read just the first block on the flash page or the entire flash page. Write operations
must be for the entire flash page. Invalid buffer mask values will cause the DMA descriptor command to be
terminated.
BCH_AUXONLY = 0x100 Set to request transfer from only the auxiliary buffer (block 0 on flash).
BCH_PAGE = 0x1FF Set to request transfer to/from the entire page.
29.6.4 GPMI Integrated ECC Transfer Count Register Description

(GPMI_ECCCOUNT)
The GPMI ECC Transfer Count Register contains the count of bytes that flow through
the ECC subsystem.
GPMI_ECCCOUNT 0x030
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
RSVD2 COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_ECCCOUNT field descriptions

Field Description
RSVD2
COUNT Number of bytes to pass through ECC. This is the GPMI transfer count plus the syndrome count that will
be inserted into the stream by the ECC. In DMA2ECC_MODE this count must match the
GPMI_CTRL0_XFER_COUNT. A value of zero will transfer 64K words.
29.6.5 GPMI Payload Address Register Description

(GPMI_PAYLOAD)
The GPMI payload address register specifies the location of the data buffers in system
memory. This value must be word aligned.
GPMI_PAYLOAD 0x040
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_PAYLOAD field descriptions

Field Description
31–2 Pointer to an array of one or more 512 byte payload buffers.
ADDRESS
RSVD0 Always write zeroes to this bit field.
29.6.6 GPMI Auxiliary Address Register Description

(GPMI_AUXILIARY)
The GPMI auxiliary address register specifies the location of the auxiliary buffers in
system memory. This value must be word aligned.
GPMI_AUXILIARY 0x050
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD0
ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_AUXILIARY field descriptions

Field Description
31–2 Pointer to ECC control structure and meta-data storage.
ADDRESS

29.6.7 GPMI Control Register 1 Description (GPMI_CTRL1n)
The GPMI control register 1 specifies additional control fields that are not used on a per-
transaction basis.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD1
R
GPMI_CLK_DIV2_EN
GANGED_RDYBUSY
SSYNC_CLK_STOP
WRITE_CLK_STOP
TIMEOUT_IRQ_EN
DEV_CLK_STOP
TOGGLE_MODE
DECOUPLE_CS
HALF_PERIOD
SSYNCMODE
DLL_ENABLE
UPDATE_CS
BCH_MODE
WRN_DLY_
SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABORT_WAIT_REQUEST
ATA_IRQRDY_POLARITY
R
DMA2ECC_MODE
CAMERA_MODE
TIMEOUT_IRQ
GPMI_MODE
DEV_RESET
BURST_EN
DEV_IRQ
ABORT_WAIT_
RDN_DELAY FOR_READY_
CHANNEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

GPMI_CTRL1n field descriptions

Field Description
31 set this bit to 1 will stop gpmi io working clk.
DEV_CLK_STOP
30 set this bit to 1 will stop the source synchronous mode clk.
SSYNC_CLK_
STOP
29 In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK
WRITE_CLK_ signal high (i.e. stopping the CLK). The host may only stop the CLK during data write, by setting this bit to
STOP 1, if the device supports this feature as indicated in the parameter page.
28 enable samsung toggle mode.
TOGGLE_MODE
27 This bit should be reset to 0 in asynchronous mode. The frequence ratio of (device clock : ccm gpmi clock)
GPMI_CLK_ will be (1 : 1).
DIV2_EN
This bit should be set to 1, in source synchronous mode or toggle mode. The frequence raito of (device
clock : ccm gpmi clock) will be (1 : 2).
enable the gpmi clk divider.
0x0 internal factor-2 clock divider is disabled

0x1 internal factor-2 clock divider is enabled.
26 force the CS value is be updated to external chip select pin, even GPMI is idle.
UPDATE_CS
25 source synchronouse mode 1 or asynchrous mode 0.
SSYNCMODE
ASYNC = 0x0 Asynchronous mode.
SSYNC = 0x1 Source Synchronous mode.
24 Decouple Chip Select from DMA Channel. Setting this bit to 1 will allow a DMA channel to specify any
DECOUPLE_CS value in the CTRL0_CS register field. Software can use one DMA channel to access all 8 Nand devices.
23–22 Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to
WRN_DLY_SEL match the load on this pin.
0 = 4ns to 8ns; 1 = 6ns to 10ns; 2 = 7ns to 12ns; 3 = no delay.
21 Always write zeroes to this bit field.
RSVD1
20 Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY
TIMEOUT_IRQ_ commands in both ATA and Nand mode. The Device_Busy_Timeout value is used for this timeout.
EN
19 Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0. This will
GANGED_ free up all, except one, RDY_BUSY input pins.
RDYBUSY
18 This bit selects which error correction unit will access GPMI. This bit must always be set to '1', since only
BCH_MODE the BCH unit is available in this design.
17 Set this bit to 1 to enable the GPMI DLL. This is required for fast NAND reads (above 30 MHz read
DLL_ENABLE strobe).
After setting this bit, wait 64 GPMI clock cycles for the DLL to lock before performing a NAND read.
16 Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation. DLL_ENABLE
HALF_PERIOD must be zero while changing this field.
15–12 This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data
RDN_DELAY sampling.


Field Description
The applied delay (AD) is between 0 and 1.875 times the reference period (RP). RP is one half of the
GPMI clock period if HALF_PERIOD=1
otherwise it is the full GPMI clock period. The equation is: AD = RDN_DELAY x 0.125 x RP. This value
must not exceed 16ns.
This variable is used to achieve faster NAND access. For example if the Read Strobe is asserted from
time 0 to 13ns but the read access time is 20ns,
then choose AD=12ns will cause the data to be sampled at time 25ns (13+12) giving a 5ns data setup
time. If RP=13ns then RDN_DELAY = 12/(0.125 x 13ns)
= 7.38 (0111b). DLL_ENABLE must be zero while changing this field.
11 This is mainly for testing HWECC without involving the Nand device. Setting this bit will cause DMA write
DMA2ECC_ data to redirected to HWECC module (instead of Nand Device) for encoding or decoding.
MODE
10 This bit is set when an Interrupt is received from the ATA device. Write 0 to clear.
DEV_IRQ
9 This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear.
TIMEOUT_IRQ
8 When set to 1 each DMA request will generate a 4-transfer burst on the APB bus.
BURST_EN
7 Request to abort "wait for ready" command on channel indicated by
ABORT_WAIT_ ABORT_WAIT_FOR_READY_CHANNEL. Hardware will clear this bit when abort is done.
REQUEST
6–4 Abort a wait for ready command on selected channel. Set the ABORT_WAIT_REQUEST to kick of
ABORT_WAIT_ operation.
FOR_READY_
CHANNEL
3 ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted).
DEV_RESET
DISABLED = 0x1 NANDF_WP_B(WPN) pin is held high (de-asserted).
0 NANDF_WP_B pin is held low (asserted).

1 NANDF_WP_B pin is held high (de-asserted).
2 For ATA MODE:
ATA_IRQRDY_
Note NAND_RDY_BUSY[3:2] are not affected by this bit.
POLARITY
ACTIVELOW = 0x0 ATA IORDY and IRQ are active low, or NAND_RDY_BUSY[1:0] are active low ready.
ACTIVEHIGH = 0x1 ATA IORDY and IRQ are active high, or NAND_RDY_BUSY[1:0] are active high
ready.
0 External ATA IORDY and IRQ are active low.
1 External ATA IORDY and IRQ are active high.
For NAND MODE:
0 External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
1 External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
1 When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface.
CAMERA_MODE
0 ATA mode is only supported on channel zero.
GPMI_MODE
If ATA mode is selected, then only channel three is available for NAND use.


Field Description
NAND = 0x0 NAND mode.
ATA = 0x1 ATA mode.
0 NAND mode.
1 ATA mode.
29.6.8 GPMI Timing Register 0 Description (GPMI_TIMING0)

The GPMI timing register 0 specifies the timing parameters that are used by the cycle
state machine to guarantee the various setup, hold and cycle times for the external media
type.
GPMI_TIMING0 0x070
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDRESS_SETUP DATA_HOLD DATA_SETUP
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1
GPMI_TIMING0 field descriptions

Field Description
RSVD1
23–16 Number of GPMICLK cycles that the CE/ADDR signals are active before a strobe is asserted. A value of
ADDRESS_ zero is interpreted as 0. For ATA PIO modes this is known in the ATA7 specification as "Address valid to
SETUP DIOR-/DIOW- setup"
15–8 Data bus hold time in GPMICLK cycles. Also the time that the data strobe is de-asserted in a cycle. A
DATA_HOLD value of zero is interpreted as 256. For ATA PIO modes this is known in the ATA7 specification as "DIOR-/
DIOW- recovery time"
DATA_SETUP Data bus setup time in GPMICLK cycles. Also the time that the data strobe is asserted in a cycle. This
value must be greater than 2 for ATA devices that use IORDY to extend transfer cycles. A value of zero is
interpreted as 256. For ATA PIO modes this is known in the ATA7 specification as ""DIOR-/DIOW-"

The GPMI timing register 1 specifies the timeouts used when monitoring the NAND
READY pin or the ATA IRQ and IOWAIT signals.
GPMI_TIMING1 0x080

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1
DEVICE_BUSY_TIMEOUT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
31–16 Timeout waiting for NAND Ready/Busy or ATA IRQ. Used in WAIT_FOR_READY mode. This value is the
DEVICE_BUSY_ number of GPMI_CLK cycles multiplied by 4096.
TIMEOUT

The GPMI timing register 2 specifies the double data rate timing parameters that are used
by the cycle state machine to guarantee the various cs delay, pre-amble delay, post-amble
delay, command/address delay, data delay, and read latency cycle times for the external
media type.
GPMI_TIMING2 0x090
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RSVD1 READ_ RSVD0 PREAMBLE_ POSTAMBLE CMDADD_ DATA_

LATENC CE_DELAY
W DELAY _DELAY PAUSE PAUSE
Y
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0

Field Description
RSVD1
26–24 This field is for double data rate read latency configuration.
READ_
others READ LATENCY is 3
LATENCY
000 READ LATENCY is 0
RSVD0

GPMI_TIMING2 field descriptions (continued)

Field Description
20–16 GPMI dealy from CEn assert to W/Rn changing edge. value of zero is interpreted as 32.
CE_DELAY
15–12 GPMI pre-amble delay in GPMICLK cycles. A value of zero is interpreted as 16.
PREAMBLE_
DELAY
11–8 GPMI post-amble delay in GPMICLK cycles. A value of zero is interpreted as 16.
POSTAMBLE_
DELAY
7–4 GPMI delay time from command or addres pause to command or address resume in GPMICLK cycles. A
CMDADD_ value of zero is interpreted as 16.
PAUSE
DATA_PAUSE GPMI delay time from data pause to data resume in GPMICLK cycles. A value of zero is interpreted as 16.
29.6.11 GPMI DMA Data Transfer Register Description

(GPMI_DATA)
The GPMI DMA data transfer register is used by the DMA to read or write data to or
from the ATA/NAND control state machine.
GPMI_DATA 0x0A0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_DATA field descriptions

Field Description
DATA In 8-bit mode, one, two, three or four bytes can can be accessed to send the same number of bus cycles.
29.6.12 GPMI Status Register Description (GPMI_STAT)

The GPMI control and status register provides a read back path for various operational
states of the GPMI controller.
GPMI_STAT 0x0B0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R READY_BUSY RDY_TIMEOUT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INVALID_BUFFER_MASK
DEV7_ERROR
DEV6_ERROR
DEV5_ERROR
DEV4_ERROR
DEV3_ERROR
DEV2_ERROR
DEV1_ERROR
DEV0_ERROR
FIFO_EMPTY
FIFO_FULL
PRESENT
ATA_IRQ
R RSVD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

GPMI_STAT field descriptions

Field Description
31–24 Read-only view of NAND Ready_Busy Input pins.
READY_BUSY
23–16 State of the RDY/BUSY Timeout Flags. When any bit is set to '1' in this field, it indicates that a time out
RDY_TIMEOUT
has occurred while waiting for the ready state of the requested NAND device. Multiple bits may be set
simultaneously.
When GPMI_CTRL1_DECOUPLE_CS = 0, RDY_TIMEOUT[n] is associated with the NAND device on
chip_select[n].
When GPMI_CTRL1_DECOUPLE_CS = 1, these flags become associated to a DMA channel instead of a
NAND device.
For example if DMA channel 6 sends a WAIT_FOR_READY command for NAND Device 2, and a timeout
occured on READY_BUSY2,
then READY_TIMEOUT[6] will be set instead of READY_TIMEOUT[2].
15 DMA channel 7 (Timeout or compare failure, depending on COMMAND_MODE).
DEV7_ERROR
0 No error condition present on ATA/NAND Device accessed by DMA channel 7.
1 An Error has occurred on ATA/NAND Device accessed by
DEV6_ERROR
DEV5_ERROR
DEV4_ERROR
DEV3_ERROR
DEV2_ERROR
DEV1_ERROR
DEV0_ERROR
RSVD1

GPMI_STAT field descriptions (continued)

Field Description
4 Status of the ATA_IRQ input pin.
ATA_IRQ
3 Buffer Mask Validity bit.
INVALID_
BUFFER_MASK 0 ECC Buffer Mask is not invalid.
1 ECC Buffer Mask is invalid.
2 NOT_EMPTY = 0x0 FIFO is not empty.
FIFO_EMPTY
EMPTY = 0x1 FIFO is empty.
0 FIFO is not empty.

1 FIFO is empty.
1 NOT_FULL = 0x0 FIFO is not full.
FIFO_FULL
FULL = 0x1 FIFO is full.
0 FIFO is not full.

1 FIFO is full.
0 UNAVAILABLE = 0x0 GPMI is not present in this product.
PRESENT
AVAILABLE = 0x1 GPMI is present in this product.
0 GPMI is not present in this product.

1 GPMI is present is in this product.
29.6.13 GPMI Debug Information Register Description

(GPMI_DEBUG)
The GPMI debug information register provides a read back path for diagnostics to
determine the current operating state of the GPMI controller.
GPMI_DEBUG 0x0C0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R WAIT_FOR_READY_END DMA_SENSE DMAREQ CMD_END

W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_DEBUG field descriptions

Field Description
31–24 Read Only view of the Wait_For_Ready End toggle signals to DMA. One per channel
WAIT_FOR_
READY_END

GPMI_DEBUG field descriptions (continued)

Field Description
23–16 Read-only view of sense state of the 8 DMA channels. A value of "1" in any bit position indicates that a
DMA_SENSE read and compare command failed or a timeout occured for the corresponding channel.
15–8 Read-only view of DMA request line for 8 DMA channels. A toggle on any bit position indicates a DMA
DMAREQ request for the corresponding channel.
CMD_END Read Only view of the Command End toggle signals to DMA. One per channel
29.6.14 GPMI Version Register Description (GPMI_VERSION)

This register reflects the version number for the GPMI.
GPMI_VERSION 0x0D0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR MINOR STEP

W
Reset 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_VERSION field descriptions

Field Description
31–24 Fixed read-only value reflecting the MAJOR field of the RTL version.
MAJOR
23–16 Fixed read-only value reflecting the MINOR field of the RTL version.
MINOR
29.6.15 GPMI Debug2 Information Register Description

(GPMI_DEBUG2)
The GPMI Debug2 information register provides a read back path for diagnostics to
GPMI_DEBUG2 0x0E0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY
R UDMA_STATE PIN_STATE MAIN_STATE
RSVD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMI2SYND_READY
SYND2GPMI_READY
GPMI2SYND_VALID
SYND2GPMI_VALID
UPDATE_WINDOW
R SYND2GPMI_BE RDN_TAP
VIEW_DELAYED_RDN
Reset 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0

GPMI_DEBUG2 field descriptions

Field Description
RSVD1
27–24 USM_IDLE = 4'h0, idle
UDMA_STATE
USM_DMARQ = 4'h1, DMA req
USM_ACK = 4'h2, DMA ACK
USM_FIFO_E = 4'h3, Fifo empty
USM_WPAUSE = 4'h4, WR DMA Paused by device
USM_TSTRB = 4'h5, Toggle HSTROBE
USM_CAPTUR = 4'h6, Capture Stage, (data sampled with DSTROBE is valid)
USM_DATOUT = 4'h7, Change Burst DATAOUT
USM_CRC = 4'h8, Source CRC to Device
USM_WAIT_R = 4'h9, Waiting for DDMARDY-
USM_END = 4'ha; Negate DMAACK (end of DMA)
USM_WAIT_S = 4'hb, Waiting for DSTROBE
USM_RPAUSE = 4'hc, Rd DMA Paused by Host
USM_RSTOP = 4'hd, Rd DMA Stopped by Host
USM_WTERM = 4'he, Wr DMA Termination State
USM_RTERM = 4'hf, Rd DMA Termination state
23 When asserted the GPMI is busy. Undefined results may occur if any registers are written when BUSY is
BUSY asserted.
DISABLED = 0x0 The GPMI is not busy.
ENABLED = 0x1 The GPMI is busy.
22–20 parameter PSM_IDLE = 3'h0, PSM_BYTCNT = 3'h1, PSM_ADDR = 3'h2, PSM_STALL = 3'h3,
PIN_STATE PSM_STROBE = 3'h4, PSM_ATARDY = 3'h5, PSM_DHOLD = 3'h6, PSM_DONE = 3'h7.
PSM_IDLE = 0x0
PSM_BYTCNT = 0x1
PSM_ADDR = 0x2
PSM_STALL = 0x3
PSM_STROBE = 0x4
PSM_ATARDY = 0x5
PSM_DHOLD = 0x6
PSM_DONE = 0x7
19–16 parameter MSM_IDLE = 4'h0, MSM_BYTCNT = 4'h1, MSM_WAITFE = 4'h2, MSM_WAITFR = 4'h3,
MAIN_STATE MSM_DMAREQ = 4'h4, MSM_DMAACK = 4'h5, MSM_WAITFF = 4'h6, MSM_LDFIFO = 4'h7,
MSM_LDDMAR = 4'h8, MSM_RDCMP = 4'h9, MSM_DONE = 4'hA.
MSM_IDLE = 0x0
MSM_BYTCNT = 0x1
MSM_WAITFE = 0x2
MSM_WAITFR = 0x3

GPMI_DEBUG2 field descriptions (continued)

Field Description
MSM_DMAREQ = 0x4
MSM_DMAACK = 0x5
MSM_WAITFF = 0x6
MSM_LDFIFO = 0x7
MSM_LDDMAR = 0x8
MSM_RDCMP = 0x9
MSM_DONE = 0xA
15–12 Data byte enable Input from BCH.
SYND2GPMI_BE
11 Data handshake output to BCH.
GPMI2SYND_
VALID
10 Data handshake output to BCH.
GPMI2SYND_
READY
9 Data handshake Input from BCH.
SYND2GPMI_
VALID
8 Data handshake Input from BCH.
SYND2GPMI_
READY
7 Set to a 1 to select the delayed feedback RE_B to drive the GPMI_ADDR[0] (Nand CLE) pin. For debug
VIEW_ purposes, this will allow you see if DLL is functioning properly.
DELAYED_RDN
6 A 1 indicates that the DLL is busy generating the required delay.
UPDATE_
WINDOW
RDN_TAP This is the DLL tap calculated by the DLL controller. The selects the amount of delay form the DLL chain.
29.6.16 GPMI Debug3 Information Register Description

(GPMI_DEBUG3)
The GPMI Debug3 information register provides a read back path for diagnostics to
GPMI_DEBUG3 0x0F0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R APB_WORD_CNTR DEV_WORD_CNTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPMI_DEBUG3 field descriptions

Field Description
31–16 Reflects the number of bytes remains to be transferred on the APB bus.
APB_WORD_
CNTR
DEV_WORD_ Reflects the number of bytes remains to be transferred on the ATA/Nand bus.
CNTR
29.6.17 GPMI Double Rate Read DLL Control Register

Description (GPMI_READ_DDR_DLL_CTRL)
GPMI DDR Read Delay Loop Lock Control Register. This register provides
programmability in DDR mode for data input timing and data formats.
GPMI_READ_DDR_DLL_CTRL 0x100
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD1
SLV_
REF_UPDATE_INT SLV_UPDATE_INT OVERRIDE_
VAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLV_FORCE_UPD
SLV_OVERRIDE
GATE_UPDATE
REFCLK_ON
ENABLE
RESET
SLV_OVERRIDE_VAL SLV_DLY_TARGET
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0

GPMI_READ_DDR_DLL_CTRL field descriptions

Field Description
31–28 This field allows the user to add additional delay cycles to the DLL control loop (reference delay line
REF_UPDATE_ control). By default, the DLL control loop shall update every two GPMICLK cycles. Programming this field
INT results in a DLL control loop update interval of (2 + REF_UPDATE_INT) * GPMICLK. It should be noted
that increasing the reference delay-line update interval reduces the ability of the DLL to adjust to fast
changes in conditions that may effect the delay (such as voltage and temperature)
27–20 Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256
SLV_UPDATE_ GPMICLK cycles. A value of 0 results in an update interval of 256 GPMICLK cycles (default setting). A
INT value of 0x0f results in 15 cycles and so on. Note that software can always cause an update of the slave-
delay line using the SLV_FORCE_UPDATE register. Note that the slave delay line will also update
automatically when the reference DLL transitions to a locked state (from an un-locked state).
19–18 Reserved
RSVD1
17–10 When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually. A value of 0 selects
SLV_ tap 1, and a value of 0x7f selects tap 256.
OVERRIDE_VAL
9 Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to
SLV_OVERRIDE disable manual override. This feature does not require the DLL to tbe enabled using the ENABLE bit. In
fact to reduce power, if SLV_OVERRIDE is used, it is recommended to disable the DLL with ENABLE=0
8 set this bit to 1 will turn on the reference clock
REFCLK_ON
7 Setting this bit to 1, forces the slave delay line not update
GATE_UPDATE
6–3 The delay target for the read clock is can be programmed in 1/16th increments of an GPMICLK half-
SLV_DLY_ period. So the input read-clock can be delayed relative input data from (GPMICLK/2)/16 to GPMICLK/2.
TARGET
2 Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately. The
SLV_FORCE_ slave delay line shall update automatically based on the SLV_UPDATE_INT interval or when a DLL lock
UPD condition is sensed. Subsequent forcing of the slave-line update can only occur if SLV_FORCE_UP is set
back to 0 and then asserted again (edge triggered).
1 Setting this bit to 1 force a reset on DLL. This will cause the DLL to lose lock and re-calibrate to detect an
RESET GPMICLK half period phase shift. This signal is used by the DLL as edge-sensitive, so in order to create a
subsequent reset, RESET must be taken low and then asserted again.
0 Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL. Note that using
ENABLE the slave delay line override feature with SLV_OVERRIDE and SLV_OVERRIDE VAL, the DLL does not
need to be enabled.
29.6.18 GPMI Double Rate Write DLL Control Register

Description (GPMI_WRITE_DDR_DLL_CTRL)
GPMI DDR Write Delay Loop Lock Control Register. This register provides
programmability in DDR mode for data output timing and data formats.
GPMI_WRITE_DDR_DLL_CTRL 0x110

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RSVD1
SLV_
REF_UPDATE_INT SLV_UPDATE_INT OVERRIDE_
VAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLV_FORCE_UPD
SLV_OVERRIDE
GATE_UPDATE
REFCLK_ON
ENABLE
RESET
SLV_OVERRIDE_VAL SLV_DLY_TARGET
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0
GPMI_WRITE_DDR_DLL_CTRL field descriptions

Field Description
31–28 This field allows the user to add additional delay cycles to the DLL control loop (reference delay line
REF_UPDATE_ control). By default, the DLL control loop shall update every two GPMICLK cycles. Programming this field
INT results in a DLL control loop update interval of (2 + REF_UPDATE_INT) * GPMICLK. It should be noted
that increasing the reference delay-line update interval reduces the ability of the DLL to adjust to fast
changes in conditions that may effect the delay (such as voltage and temperature)
27–20 Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256
SLV_UPDATE_ GPMICLK cycles. A value of 0 results in an update interval of 256 GPMICLK cycles (default setting). A
INT value of 0x0f results in 15 cycles and so on. Note that software can always cause an update of the slave-
delay line using the SLV_FORCE_UPDATE register. Note that the slave delay line will also update
automatically when the reference DLL transitions to a locked state (from an un-locked state).
19–18 Reserved
RSVD1
17–10 When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually. A value of 0 selects
SLV_ tap 1, and a value of 0x7f selects tap 256.
OVERRIDE_VAL
9 Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to
SLV_OVERRIDE disable manual override. This feature does not require the DLL to tbe enabled using the ENABLE bit. In
fact to reduce power, if SLV_OVERRIDE is used, it is recommended to disable the DLL with ENABLE=0

GPMI_WRITE_DDR_DLL_CTRL field descriptions (continued)

Field Description
8 set this bit to 1 will turn on the reference clock
REFCLK_ON
7 Setting this bit to 1, forces the slave delay line not update
GATE_UPDATE
6–3 The delay target for the read clock can be programmed in 1/16th increments of an GPMICLK half-period.
SLV_DLY_ So the input read-clock can be delayed relative input data from (GPMICLK/2)/16 to GPMICLK/2.
TARGET
2 Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately. The
SLV_FORCE_ slave delay line shall update automatically based on the SLV_UPDATE_INT interval or when a DLL lock
UPD condition is sensed. Subsequent forcing of the slave-line update can only occur if SLV_FORCE_UP is set
back to 0 and then asserted again (edge triggered).
1 Setting this bit to 1 force a reset on DLL. This will cause the DLL to lose lock and re-calibrate to detect an
RESET GPMICLK half period phase shift. This signal is used by the DLL as edge-sensitive, so in order to create a
subsequent reset, RESET must be taken low and then asserted again.
0 Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL. Note that using
ENABLE the slave delay line override feature with SLV_OVERRIDE and SLV_OVERRIDE VAL, the DLL does not
need to be enabled.
29.6.19 GPMI Double Rate Read DLL Status Register Description

(GPMI_READ_DDR_DLL_STS)
GPMI Double Rate Read DLL Status Register, Read Only. GPMI DLL status fields are
provided in this register.
GPMI_READ_DDR_DLL_STS 0x120
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REF_LOCK
R RSVD1 REF_SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLV_LOCK
R RSVD0 SLV_SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_READ_DDR_DLL_STS field descriptions

Field Description
31–25 Reserved
RSVD1
24–17 Reference delay line select status.
REF_SEL
16 Reference DLL lock status. This signifies that the DLL has detected and locked to a half-phase GPMICLK
REF_LOCK shift, allowing the slave delay-line to perform programmed clock delays.
15–9 Reserved
RSVD0
8–1 Slave delay line select status
SLV_SEL
0 Slave delay-line lock status. This signifies that a valid calibration has been set to the slave-delay line and
SLV_LOCK that the slave-delay line is implementing the programmed delay value.
29.6.20 GPMI Double Rate Write DLL Status Register Description

(GPMI_WRITE_DDR_DLL_STS)
GPMI Double Rate Write DLL Status Register, Read Only. GPMI DLL status fields are
provided in this register.
GPMI_WRITE_DDR_DLL_STS 0x130

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REF_LOCK
R RSVD1 REF_SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLV_LOCK
R RSVD0 SLV_SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPMI_WRITE_DDR_DLL_STS field descriptions

Field Description
31–25 Reserved
RSVD1
24–17 Reference delay line select status.
REF_SEL
16 Reference DLL lock status. This signifies that the DLL has detected and locked to a half-phase GPMICLK
REF_LOCK shift, allowing the slave delay-line to perform programmed clock delays.
15–9 Reserved
RSVD0
8–1 Slave delay line select status
SLV_SEL

GPMI_WRITE_DDR_DLL_STS field descriptions (continued)

Field Description
0 Slave delay-line lock status. This signifies that a valid calibration has been set to the slave-delay line and
SLV_LOCK that the slave-delay line is implementing the programmed delay value.


Chapter 30
General Purpose Timer (GPT)
30.1 Overview
This chapter describes the General Purpose Timer (GPT) module interface. It is also a
reference for software driver programming. The GPT has a 32-bit up-counter. The timer
counter value can be captured in a register using an event on an external pin. The capture
trigger can be programmed to be a rising or/and falling edge. The GPT can also generate
an event on the output compare pins and an interrupt when the timer reaches a
programmed value. The GPT has a 12-bit prescaler, which provides a programmable
clock frequency derived from multiple clock sources.

Overview
Prescaler FRR
output ROVIE
Clock input from Prescaler
clock selection 12-bit
block 1... 4096 Timer
Counter ROV
Counter Value Bus

32-bit
GPT interrupts
Processor Interrupt Bus

sync IM1
GPT_CAPTURE 1 IF1 Timer
Input Reg 1
32-bit
IF1IE
Timer
Input Reg 2
IF2IE 32-bit
OF1IE
IF2
sync IM2
GPT_CAPTURE2 Timer
Output Reg1 cmp OF1 OM1
32-bit GPT_COMPARE1
OF2IE
Processor Data Bus
Timer
Output Reg2
32-bit cmp OF2 OM2
OF3IE GPT_COMPARE2
Timer
Output Reg3
32-bit cmp OF3 OM3
GPT_COMPARE3
Figure 30-1. GPT Block Diagram

Chapter 30 General Purpose Timer (GPT)
Clock off
Crystal Oscillator
(ipg_clk_24M) Prescaler 24M
Sync
External Clock
(GPT_CLK)
To Prescaler
Peripheral Clock
(ipg_clk)
Low Frequency Reference Clock
(ipg_clk_32k)
High Frequency Reference Clock
(ipg_clk_highfreq)
Figure 30-2. GPT Counter Clocks Diagram
30.1.1 Features
• One 32-bit up-counter with clock source selection, including external clock.
• Two input capture channels with a programmable trigger edge.
• Three output compare channels with a programmable output mode. A "forced
compare" feature is also available.
• Can be programmed to be active in low power and debug modes.
• Interrupt generation at capture, compare, and rollover events.
• Restart or free-run modes for counter operations.
30.1.2 Modes and Operation

The GPT supports the modes described in the indicated sections:
• Operating Modes
• Restart Mode
• Free-Run Mode

External Signals

The GPT follows the IP Bus protocol for interfacing with the processor core. The GPT
does not have any interface signals with any other module inside the chip, except for the
clock and reset inputs (from the clock and reset controller module) and for the interrupt
signals to the processor interrupt handler. There are functional and clock inputs, and
functional output signals going outside the chip boundary.
The following table describes all block signals that connect off-chip.
Table 30-1. GPT External Signals
GPT_CLK Input pin for an external clock that SD1_CLK ALT3 I
the counter can be operated at.
GPT_CAPTURE1 Input pin for a capture event for SD1_DAT0 ALT3 I
Input Capture Channel 1.
GPT_CAPTURE2 Input pin for a capture event for SD1_DAT1 ALT3 I
Input Capture Channel 2.
GPT_COMPARE1 Output pin that indicates a "compare SD1_CMD ALT3 O
event" occurrence in Output
Compare Channel 1.
GPT_COMPARE2 Output pin that indicates a "compare SD1_DAT2 ALT2 O
Compare Channel 2.
GPT_COMPARE3 Output pin that indicates a "compare SD1_DAT3 ALT2 O
Compare Channel 3.
There are six signals (three input, three output) in the GPT module that can be connected
to the chip pads.
30.2.1 External Clock Input

The GPT counter can be operated using an external clock from outside the device, and
this is the input pin used for that purpose. The external clock input (GPT_CLK) is treated
as asynchronous to the peripheral clock (ipg_clk). To ensure proper operations of GPT,
the external clock input frequency should be less than 1/4 of frequency of the peripheral
clock (ipg_clk). Hysteresis characteristics on this pad will be required because this is a
clock input.

30.2.2 Input Capture Trigger Signals

The GPT counter value can be stored in a register, triggered by an event from outside the
device. A positive or/and negative edge on these signals GPT_CAPTURE1 ,
GPT_CAPTURE2 can trigger this capture event. These signals are treated as
asynchronous to the peripheral clock (ipg_clk). Only those transitions which occur at
least a single clock cycle (the clock selected to run the counter) after the previous
recorded transition are guaranteed to trigger a capture event.
30.2.3 Output Compare Signals

The output compare signals: GPT_COMPARE1, GPT_COMPARE2,
GPT_COMPARE3, indicate that output compare events have gone through a specified
transition.
30.3 Clocks
The clock that is input to the prescaler can be selected from 4 clock sources. The
following table describes the clock sources for GPT. Please see Clock Controller Module
(CCM) for clock setting, configuration and gating information.
Table 30-2. GPT Clocks
ipg_clk_32k ckil_sync_clk_root Low-frequency reference clock (32 kHz)
ipg_clk_highfreq perclk_clk_root High-frequency reference clock
• High-Frequency Clock (ipg_clk_highfreq)

Provided by the Clock Controller Module (CCM), the High Frequency Clock is
intended to be ON in Normal Power mode when the Peripheral Clock (ipg_clk) is
turned OFF, thereby enabling the GPT to be operated using the High Frequency
Clock in Normal Power mode. The CCM is expected to provide this clock after
synchronizing it to the System Bus Clock (ahb_clk) in Normal functional mode; the
CCM is also expected to switch to the unsynchronized version of the High Frequency
Clock in a Low Power mode.
• Low-Reference Clock (ipg_clk_32k)

Clocks
This 32 kHz Low Reference Clock (provided by the CCM) is intended to be ON in

Low Power mode when the Peripheral Clock (ipg_clk) is turned OFF, thereby
enabling the GPT to be operated using the Low Reference Clock in Low Power
mode. The CCM is expected to provide the Low Reference Clock after
synchronizing it to the System Bus Clock (ahb_clk) in Normal functional mode; the
CCM is also expected to switch to the unsynchronized version of the Low Reference
Clock in a Low Power mode.
• Peripheral Clock (ipg_clk)
If the Peripheral Clock (ipg_clk) or the External Clock (GPT_CLK) is selected
(CLKSRC=001 or 011) as Clock Source, then the Peripheral Clock will be ON in
normal GPT operations. In Low Power modes, if the GPT is programmed to be
disabled (STOPEN or WAITEN or DOZEN=0), then the Peripheral Clock (ipg_clk)
can be switched OFF.
• External Clock (GPT_CLK)
The External Clock comes from outside the device and can be selected to run the
GPT counter. The External Clock is treated as asynchronous to the Peripheral Clock,
(ipg_clk) and is synchronized to the Peripheral Clock (ipg_clk), inside the module.
Therefore, the External Clock frequency is limited to < 1/4 frequency of the
Peripheral Clock (ipg_clk), for proper GPT operations. Note that in Low Power
modes, if the Peripheral Clock (ipg_clk) is not available, then the External Clock
cannot be used to run the counter.
• Crystal Oscillator Clock (ipg_clk_24M)
This 24 MHz Crystal Oscillator Clock (provided by the CCM) is intended to be used
against frequency change of Peripheral Clock (ipg_clk) changes to provide a more
accurate timer clock for operation system. The CCM is expected to provide the 24
MHz Crystal Oscillator Clock without synchronizing it to the System Bus Clock
(ahb_clk) in Normal functional mode. Synchronization is done in GPT module.
Before synchronization, the 24 MHz Crystal Oscillator Clock is divided by a 24 MHz
clock prescaler, to make sure the clock frequency less than half of System Bus Clock
(ahb_clk).
The clock input source is configured using the clock source field (CLKSRC, in the
GPT_CR control register). The clock input to the prescaler can be disabled by
programming the CLKSRC bits (of the GPT_CR control register) to 000. The CLKSRC
field value should be changed only after disabling the GPT (by setting the EN bit in the
GPT_CR to 0).

The PRESCALER field selects the divide ratio of the input clock that drives the main
counter. The prescaler can divide the input clock by a value (from 1 to 4096) and can be
changed at any time. A change in the value of the PRESCALER field immediately affects
the output clock frequency.
Clk
Prescaler Value 0x004 0x002
Prescaled Clk
Figure 30-3. Prescaler Value Change Timing Diagram

This section provides a complete functional description of the GPT.

The GPT counter can be programmed to work in either of two modes: Restart mode or
Free-Run mode.
30.4.1.1 Restart Mode

In Restart mode (selectable through the GPT Control Register GPT_CR), when the
counter reaches the compared value, the counter resets and starts again from 0x00000000.
The Restart feature is associated only with Compare Channel 1.
Any write access to the Compare register of Channel 1 will reset the GPT counter. This is
done to avoid possibly missing a compare event when compare value is changed from a
higher value to lower value while counting is proceeding.
For the other two compare channels, when the compare event occurs the counter is not
reset.

30.4.1.2 Free-Run Mode

In Free-Run mode, when compare events occur for all 3 channels, the counter is not
reset; instead the counter continues to count until 0xffffffff, and then rolls over (to
0x00000000).
30.4.2 Operation
The General Purpose Timer (GPT) has a single counter (GPT_CNT) that is a 32-bit free-
running up-counter, which starts counting after it is enabled by software (EN=1). The
counter's clock source is the output of the prescaler labelled "Prescaler output" in Figure
30-1.
• If the GPT timer is disabled (EN=0), then the Main Counter and Prescaler Counter
freeze their current count values. The ENMOD bit determines the value of the GPT
counter when the EN bit is set and the Counter is enabled again.
• If the ENMOD bit is set (=1), then the Main Counter and Prescaler Counter
values are reset to 0, when GPT is enabled (EN=1).
• If ENMOD bit is programmed to 0, then the Main Counter and Prescaler Counter
restart counting from their frozen values, when GPT is enabled again (EN=1).
• If GPT is programmed to be disabled in a low power mode (STOP/WAIT), then the
Main Counter and Prescaler Counter freeze at their current count values when GPT
enters low power mode. When GPT exits a low power mode, the Main Counter and
Prescaler Counter start counting from their frozen values regardless of the ENMOD
bit value. Note that the GPT_CNT can be read at any time by the processor, and that
both Input Capture Channels use the same counter (GPT_CNT).
• A hardware reset resets all the GPT registers to their respective reset values. All
registers except the Output Compare Registers (OCR1, OCR2, OCR3) obtain a value
of 0x0. The Compare registers are reset to 0xFFFF_FFFF.
• The software reset (SWR bit in the GPT_CR control register) resets all of the register
bits except the EN, ENMOD, STOPEN, WAITEN, and DBGEN bits. The state of
these bits is not affected by a software reset. Note that a software reset can be given
while the GPT is disabled.
30.4.2.1 Input Capture

There are two Input Capture Channels, and each Input Capture Channel has a dedicated
capture pin, capture register and input edge detection/selection logic. Each input capture
function has an associated status flag, and can cause the processor to make an interrupt
service request.

When a selected edge transition occurs on an Input Capture pin, the contents of the
GPT_CNT is captured on the corresponding capture register and the appropriate interrupt
status flag is set. An interrupt request can be generated when the transition is detected if
its corresponding enable bit is set (in the Interrupt Register). The capture can be
programmed to occur on the input pin's rising edge, falling edge, on both rising and
falling edges, or the capture can be disabled. The events are synchronized with the clock
that was selected to run the counter. Only those transitions that occur at least one clock
cycle (clock selected to run the counter) after the previous recorded transition will be
guaranteed to trigger a capture event. There can be up to one clock cycle of uncertainty in
the latching of the input transition. The Input Capture registers can be read at any time
without affecting their values.
Clk
ipp_ind_capin1
Sig
Clk = The clock selected from CLKSRC bit field setting
ipp_ind_capin1 = Pad signal for capture channel 1
Sig = Capture signal as sensed by the module
Figure 30-4. Input Capture Event Timing
30.4.2.2 Output Compare

The three Output Compare Channels use the same counter (GPT_CNT) as the Input
Capture Channels. When the programmed content of an Output Compare register
matches the value in GPT_CNT, an output compare status flag is set and an interrupt is
generated (if the corresponding bit is set in the interrupt register). Consequently, the
Output Compare timer pin will be set, cleared, toggled, not affected at all or provide an
active-low pulse for one input clock period (subject to the restriction on the maximum
frequency allowed on the pad) according to the mode bits (that were programmed).
There is also a "forced-compare" feature that allows the software to generate a compare
event when required, without the condition of the counter value that is equal to the
compare value. The action taken as a result of a forced compare is the same as when an
output compare match occurs, except that the status flags are not set and no interrupt can
be generated. Forced channels take programmed action immediately after the write to the
force-compare bits. These bits are self-negating and always read as zeros.
Clk
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0
Counter
Compare Value 4
Output Mode 001 100 010 011
Output Signal toggle clear set

low pulse
Interrupt
Figure 30-5. Output Compare and Interrupt Timing
30.4.2.3 Interrupts
There are 6 different interrupts that are generated by the GPT. If the selected clock for
running the counter is available, then all interrupts can be generated in Low Power and
Debug modes.
• Rollover Interrupt
The Rollover Interrupt is generated when the GPT counter reaches 0xffffffff, then
resets to 0x00000000 and continues counting. The Rollover Interrupt is enabled by
the ROVIE bit in the GPT_IR register; the associated status bit is the ROV bit in the
GPT_SR register.
• Input Capture Interrupt 1, 2
After a capture event occurs, the associated Input Capture Channel generates an
interrupt. The "capture event" interrupts are enabled by the IF2IE and IF1IE bits (in
the GPT_IR register); the associated status bits are IF2 and IF1 (in the GPT_SR
register). The capture of the counter value because of a capture event is not affected
by a pending capture interrupt. The Capture register is updated with a new counter
value when a capture event occurs, regardless of whether that Capture Channels'
interrupt has been serviced or not.
• Output Compare Interrupt 1, 2, 3

After a compare event occurs, the associated Output Compare Channel generates an
interrupt. The "compare event" interrupts are enabled by the OF3IE, OF2IE, and
OF1IE bits (in the GPT_IR register); the associated status bits are OF3, OF2, and
OF1 (in the GPT_SR register). A "forced compare" does not generate an interrupt.
A cumulative interrupt line is also present, which is asserted whenever any of the above
interrupts are posted. The cumulative interrupt line has no associated enables or status
bits.
30.4.2.4 Low Power Mode Behavior

In Low Power modes, if the clock from the selected clock source is available (except for
the External Clock (GPT_CLK), which can be used only if the Peripheral Clock (ipg_clk)
is available), the counter will continue to run depending on whether the control bit for
that mode is set. If the clock is not present or if the corresponding low power bit in the
GPT_CR control register is 0, the Main Counter and the Prescaler Counter freeze at their
current values and resume counting (from their frozen values) when the Low Power
mode is exited.
30.4.2.5 Debug Mode Behavior

In Debug mode, the modules in the device have the option of continuing to run or be
halted.
• If the DBGEN bit is set, then the GPT timer will continue to run in Debug mode.
• If the DBGEN bit is not set (in the GPT_CR control register), then the GPT timer is
halted.
30.5 Initialization/ Application Information
30.5.1 Selecting the Clock Source

The CLKSRC field in the GPT_CR register selects the clock source. The CLKSRC field
value should be changed only after disabling the GPT (EN=0).
The software sequence to be followed while changing clock source is:
1. Disable GPT by setting EN=0 in GPT_CR register.
2. Disable GPT interrupt register (GPT_IR).
GPT Memory Map/Register Definition
3. Configure Output Mode to unconnected/ disconnected—Write zeros in OM3, OM2,

and OM1 in GPT_CR
4. Disable Input Capture Modes—Write zeros in IM1 and IM2 in GPT_CR
5. Change clock source CLKSRC to the desired value in GPT_CR register.
6. Assert the SWR bit in GPT_CR register.
7. Clear GPT status register (GPT_SR) (i.e., w1c).
8. Set ENMOD=1 in GPT_CR register, to bring GPT counter to 0x00000000.
9. Enable GPT (EN=1) in GPT_CR register.
10. Enable GPT interrupt register (GPT_IR).
30.6 GPT Memory Map/Register Definition
The GPT has 10 user-accessible 32-bit registers, which are used to configure, operate,
and monitor the state of the GPT.
An IP bus write access to the GPT Control Register (GPT_CR) and the GPT Output
Compare Register1 (GPT_OCR1) results in one cycle of wait state, while other valid IP
bus accesses incur 0 wait states.
Irrespective of the Response Select signal value, a Write access to the GPT Status
Registers (Read-only registers GPT_ICR1, GPT_ICR2, GPT_CNT) will generate a bus
exception.
• If the Response Select signal is driven Low, then the Read/Write access to the
unimplemented address space of GPT (ips_addr is greater than or equal to $BASE +
$028) will generate a bus exception.
• If the Response Select is driven High, then the Read/Write access to the
unimplemented address space of GPT will not generate any error response (like a bus
exception).
GPT memory map
Absolute
Width Section/
(in bits) page
(hex)
209_8000 GPT Control Register (GPT_CR) 32 R/W 0000_0000h 30.6.1/1313
209_8004 GPT Prescaler Register (GPT_PR) 32 R/W 0000_0000h 30.6.2/1317
209_8008 GPT Status Register (GPT_SR) 32 R/W 0000_0000h 30.6.3/1318
209_800C GPT Interrupt Register (GPT_IR) 32 R/W 0000_0000h 30.6.4/1319
209_8010 GPT Output Compare Register 1 (GPT_OCR1) 32 R/W FFFF_FFFFh 30.6.5/1320

GPT memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
209_801C GPT Input Capture Register 1 (GPT_ICR1) 32 R 0000_0000h 30.6.8/1322
209_8020 GPT Input Capture Register 2 (GPT_ICR2) 32 R 0000_0000h 30.6.9/1322
30.6.10/
209_8024 GPT Counter Register (GPT_CNT) 32 R 0000_0000h
1323
30.6.1 GPT Control Register (GPT_CR)
The GPT Control Register (GPT_CR) is used to program and configure GPT operations.
An IP Bus Write to the GPT Control Register occurs after one cycle of wait state, while
an IP Bus Read occurs after 0 wait states.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0
OM3 OM2 OM1 IM2 IM1

FO3
FO2
FO1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
DOZEEN
STOPEN
WAITEN
ENMOD
DBGEN
EN_
SWR FRR CLKSRC EN
24M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPT_CR field descriptions

Field Description
31 FO3 Force Output Compare Channel 3
FO3
FO2 Force Output Compare Channel 2

GPT_CR field descriptions (continued)

Field Description
FO1 Force Output Compare Channel 1
The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn
bits in this register).
• The OFn flag (OF3, OF2, OF1) in the status register is not affected.
• This bit is self-negating and always read as zero.
0 Writing a 0 has no effect.

1 Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
30 See F03
FO2
29 See F03
FO1
28–26 OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode.
OM3
OM2 (bits 25-23) controls the Output Compare Channel 2 operating mode.
OM1 (bits 22-20) controls the Output Compare Channel 1 operating mode.
The OMn bits specify the response that a compare event will generate on the output pin of Output
Compare Channel n.
• The toggle, clear, and set options cause a change on the output pin only if a compare event occurs.
• When OMn is programmed as 1xx (active low pulse), the output pin is set to one immediately on the
next input clock; a low pulse (that is an input clock in width) occurs when there is a compare event.
Note that here, "input clock" refers to the clock selected by the CLKSRC bits of the GPT Control
Register.
000 Output disconnected. No response on pin.

001 Toggle output pin
010 Clear output pin
011 Set output pin
1xx Generate an active low pulse (that is one input clock wide) on the output pin.
25–23 See OM3
OM2
22–20 See OM3
OM1
19–18 IM2 (bits 19-18, Input Capture Channel 2 operating mode)
IM2
IM1 (bits 17-16, Input Capture Channel 1 operating mode)
The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a
capture event.
00 capture disabled
01 capture on rising edge only
10 capture on falling edge only
11 capture on both edges
17–16 See IM2
IM1
15 Software reset.
SWR
This is the software reset of the GPT module. It is a self-clearing bit.
• The SWR bit is set when the module is in reset state.


Field Description
• The SWR bit is cleared when the reset procedure finishes.
• Setting the SWR bit resets all of the registers to their default reset values, except for the EN,
ENMOD, STOPEN, DOZEEN, WAITEN, and DBGEN bits in the GPT Control Register (this control
register).
0 GPT is not in reset state

1 GPT is in reset state
Reserved
10 Enable 24 MHz clock input from crystal.
EN_24M • A hardware reset resets the EN_24M bit.
• A software reset does not affect the EN_24M bit.
0 24M clock disabled

1 24M clock enabled
9 Free-Run or Restart mode.
FRR
The FFR bit determines the behavior of the GPT when a compare event in channel 1 occurs.
• In Restart mode, after a compare event, the counter resets to 0x00000000 and resumes counting
(after the occurrence of a compare event).
• In Free-Run mode, after a compare event, the counter continues counting until 0xFFFFFFFF and
then rolls over to 0.
0 Restart mode
1 Free-Run mode
8–6 Clock Source select.
CLKSRC
The CLKSRC bits select which clock will go to the prescaler (and subsequently be used to run the GPT
counter).
• The CLKSRC bit field value should only be changed after disabling the GPT by clearing the EN bit in
this register (GPT_CR).
• A software reset does not affect the CLKSRC bit.
000 No clock
001 Peripheral Clock (ipg_clk)
010 High Frequency Reference Clock (ipg_clk_highfreq)
011 External Clock
100 Low Frequency Reference Clock (ipg_clk_32k)
101 Crystal oscillator divided by 8 as Reference Clock (ipg_clk_24M)
111 Crystal oscillator as Reference Clock (ipg_clk_24M)
others Reserved
5 GPT Stop Mode enable.
STOPEN
The STOPEN read/write control bit enables GPT operation during Stop mode.
• A hardware reset resets the STOPEN bit.
• A software reset does not affect the STOPEN bit.
0 GPT is disabled in Stop mode.

1 GPT is enabled in Stop mode.
4 GPT Doze Mode Enable.
DOZEEN


Field Description
• A hardware reset resets the DOZEEN bit.
• A software reset does not affect the DOZEEN bit.
0 GPT is disabled in doze mode.

1 GPT is enabled in doze mode.
3 GPT Wait Mode enable.
WAITEN
The WAITEN read/write control bit enables GPT operation during Wait mode.
• A hardware reset resets the WAITEN bit.
• A software reset does not affect the WAITEN bit.
0 GPT is disabled in wait mode.

1 GPT is enabled in wait mode.
2 GPT debug mode enable.
DBGEN
The DBGEN read/write control bit enables GPT operation during Debug mode.
• A hardware reset resets the DBGEN bit.
• A software reset does not affect the DBGEN bit.
0 GPT is disabled in debug mode.

1 GPT is enabled in debug mode.
1 GPT Enable mode.
ENMOD
When the GPT is disabled (EN=0), then both the Main Counter and Prescaler Counter freeze their current
count values. The ENMOD bit determines the value of the GPT counter when Counter is enabled again (if
the EN bit is set).
• If the ENMOD bit is 1, then the Main Counter and Prescaler Counter values are reset to 0 after GPT
is enabled (EN=1).
• If the ENMOD bit is 0, then the Main Counter and Prescaler Counter restart counting from their
frozen values after GPT is enabled (EN=1).
• If GPT is programmed to be disabled in a low power mode (STOP/WAIT), then the Main Counter
and Prescaler Counter freeze at their current count values when the GPT enters low power mode.
• When GPT exits low power mode, the Main Counter and Prescaler Counter start counting from their
frozen values, regardless of the ENMOD bit value.
• Setting the SWR bit will clear the Main Counter and Prescaler Counter values, regardless of the
value of EN or ENMOD bits.
• A hardware reset resets the ENMOD bit.

• A software reset does not affect the ENMOD bit.
0 GPT counter will retain its value when it is disabled.

1 GPT counter value is reset to 0 when it is disabled.
0 GPT Enable.
EN
The EN bit is the GPT module enable bit.
Before setting the EN bit, we recommend that all registers be properly programmed.
• A hardware reset resets the EN bit.
• A software reset does not affect the EN bit.
0 GPT is disabled.
1 GPT is enabled.

30.6.2 GPT Prescaler Register (GPT_PR)
The GPT Prescaler Register (GPT_PR) contains bits that determine the divide value of
the clock that runs the counter.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
PRESCALER24M PRESCALER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPT_PR field descriptions

Field Description
Reserved
15–12 Prescaler bits.
PRESCALER24M
24M crystal clock is divided by [PRESCALER24M + 1] before selected by the CLKSRC field. If 24M
crystal clock is not selected, this feild takes no effect.
0x0 Divide by 1
0x1 Divide by 2
... ...
0xF Divide by 16
PRESCALER Prescaler bits.
The clock selected by the CLKSRC field is divided by [PRESCALER + 1], and then used to run the
counter.
• A change in the value of the PRESCALER bits cause the Prescaler counter to reset and a new
count period to start immediately.
• See Figure 30-3 for the timing diagram.
0x000 Divide by 1
0x001 Divide by 2
... ...
0xFFF Divide by 4096

30.6.3 GPT Status Register (GPT_SR)
The GPT Status Register (GPT_SR) contains bits that indicate that a counter has rolled
over, and if any event has occurred on the Input Capture and Output Compare channels.
The bits are cleared by writing a 1 to them.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ROV IF2 IF1 OF3 OF2 OF1

W w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPT_SR field descriptions

Field Description
Reserved
5 Rollover Flag.
ROV
The ROV bit indicates that the counter has reached its maximum possible value and rolled over to 0 (from
which the counter continues counting). The ROV bit is only set if the counter has reached 0xFFFFFFFF in
both Restart and Free-Run modes.
0 Rollover has not occurred.

1 Rollover has occurred.
4 IF2 Input capture 2 Flag
IF2
IF1 Input capture 1 Flag
The IFn bit indicates that a capture event has occurred on Input Capture channel n.
0 Capture event has not occurred.

1 Capture event has occurred.
3 See IF2
IF1
2 OF3 Output Compare 3 Flag
OF3
OF2 Output Compare 2 Flag
OF1 Output Compare 1 Flag
The OFn bit indicates that a compare event has occurred on Output Compare channel n.

GPT_SR field descriptions (continued)

Field Description
0 Compare event has not occurred.
1 Compare event has occurred.
1 See OF3
OF2
0 See OF3
OF1
30.6.4 GPT Interrupt Register (GPT_IR)
The GPT Interrupt Register (GPT_IR) contains bits that control whether interrupts are
generated after rollover, input capture and output compare events.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
ROVIE
OF3IE
OF2IE
OF1IE
IF2IE IF1IE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPT_IR field descriptions

Field Description
Reserved
5 Rollover Interrupt Enable.
ROVIE
The ROVIE bit controls the Rollover interrupt.
0 Rollover interrupt is disabled.

1 Rollover interrupt enabled.
4 IF2IE Input capture 2 Interrupt Enable
IF2IE
IF1IE Input capture 1 Interrupt Enable
The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable.

GPT_IR field descriptions (continued)

Field Description
0 IF2IE Input Capture n Interrupt Enable is disabled.
1 IF2IE Input Capture n Interrupt Enable is enabled.
3 See IF2IE
IF1IE
2 OF3IE Output Compare 3 Interrupt Enable
OF3IE
OF2IE Output Compare 2 Interrupt Enable
OF1IE Output Compare 1 Interrupt Enable
The OFnIE bit controls the Output Compare Channel n interrupt.
0 Output Compare Channel n interrupt is disabled.

1 Output Compare Channel n interrupt is enabled.
1 See OF3IE
OF2IE
0 See OF3IE
OF1IE
30.6.5 GPT Output Compare Register 1 (GPT_OCR1)

The GPT Compare Register 1 (GPT_OCR1) holds the value that determines when a
compare event will be generated on Output Compare Channel 1. Any write access to the
Compare register of Channel 1 while in Restart mode (FRR=0) will reset the GPT
counter.
An IP Bus Write access to the GPT Output Compare Register1 (GPT_OCR1) occurs
after one cycle of wait state; an IP Bus Read access occurs immediately (0 wait states).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
COMP
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
GPT_OCR1 field descriptions

Field Description
COMP Compare Value.
When the counter value equals the COMP bit field value, a compare event is generated on Output
Compare Channel 1.

compare event will be generated on Output Compare Channel 2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
COMP
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
COMP Compare Value.
Compare Channel 2.
compare event will be generated on Output Compare Channel 3.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
COMP
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Field Description
COMP Compare Value.
Compare Channel 3.

30.6.8 GPT Input Capture Register 1 (GPT_ICR1)
The GPT Input Capture Register 1 (GPT_ICR1) is a read-only register that holds the
value that was in the counter during the last capture event on Input Capture Channel 1.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CAPT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPT_ICR1 field descriptions

Field Description
CAPT Capture Value.
After a capture event on Input Capture Channel 1 occurs, the current value of the counter is loaded into
GPT Input Capture Register 1.
30.6.9 GPT Input Capture Register 2 (GPT_ICR2)
The GPT Input capture Register 2 (GPT_ICR2) is a read-only register which holds the
value that was in the counter during the last capture event on input capture channel 2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CAPT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPT_ICR2 field descriptions

Field Description
CAPT Capture Value.
After a capture event on Input Capture Channel 2 occurs, the current value of the counter is loaded into
GPT Input Capture Register 2.

30.6.10 GPT Counter Register (GPT_CNT)
The GPT Counter Register (GPT_CNT) is the main counter's register. GPT_CNT is a
read-only register and can be read without affecting the counting process of the GPT.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPT_CNT field descriptions

Field Description
COUNT Counter Value.
The COUNT bits show the current count value of the GPT counter.


Chapter 31
31.1 Overview
The 2D Graphics Processing Unit (GPU2D) is a high-performance multi-pipe 2D
graphics core that accelerates the 2D graphics display on a variety of devices. The
GPU2D supports a wide-range of addressable screen sizes and resolutions.
The R2D GPU Hardware acceleration is brought to numerous 2D applications including
graphical user interfaces (GUI), menu displays, flash animation, and gaming.
31.2 GPU2D Block Diagram
31.2.1 R2D GPU

The R2D Graphics Processing Unit (GPU) defines a high-performance 2D raster graphics
core that accelerates the 2D graphics display.
R2D GPU supports acceleration of the following graphics APIs:
• DirectFB (Linux / Linux Embedded)
• GDI / DirectDraw (Windows Embedded Compact 7 / Embedded CE 6)
• Android

GPU2D Features
GPU Core
AHB AXI
Host Interface
Memory Controller
2-D Pipeline
PE Pipe0
PE Pipe1
Pixel Pixel
Graphics Draw Engine Engine
Pipeline Engine Distribute PE Pipe2 Cache
G
Front Fnd P
PE Pipe 3 Fr
OPF
Figure 31-1. R2D GPU Block Diagram
31.3 GPU2D Features

The following sections describe the functional features of the R2D GPU.
31.3.1 Full Featured R2D GPU Pipeline

• Bit BLT
• Stretch BLT
• Rectangle fill and clear
• Line drawing
• Filter BLT
• Mono expansion for text rendering
• ROP2, ROP3, and ROP4
• Alpha blending, including Java 2 Porter-Duff compositing blending rules
• 32K x 32K coordinate system
• 90 / 180 / 270 degree rotation
• Transparency by monochrome mask, chroma key, or pattern mask

Chapter 31 2D Graphics Processing Unit (GPU2D)
31.4 GPU2D OPERATIONS
31.4.1 R2D GPU Operations

Information detailing the R2D GPU operations can be found in this section.
31.4.1.1 Line
The LINE operation draws a line. Coordinates for two points are given: start point and
end point. The end point is not drawn. Lines are rendered using the Bresenham algorithm.
The Bresenham algorithm has the advantage of using integer arithmetic and has no
accumulation of rounding errors.
In the case of line, only ROP2 and ROP4 are supported. It operates on pattern and
destination. The pattern should have a transparency mask in order to use ROP4.
Clipping is supported for lines on a per pixel basis.
P0(X0,Y0)
P1(X1,Y1)
Figure 31-2. Line
31.4.1.2 Rectangle Fill and Clear

Rectangle fill creates a rectangle area with a given color or a pattern fill. Essentially
rectangle fill is a pattern fill, where an 8x8 pattern is initialized with the specified color. It
supports ROP2 and ROP4 with the pattern and destination as its inputs. If ROP4 is used,
the pattern should have a transparency mask.

GPU2D OPERATIONS
Clear is similar to Rectangle Fill except that it does not use a pattern. A 32-bit clear value
with 4-bit byte mask is used to fill the entire rectangle area.
Both Rectangle Fill and Clear support clipping, which is performed on a per primitive
basis.
31.4.1.3 BitBLT
Bit blit (BitBLT) transfers data from one area of a memory (source) to another area of the
memory (destination).
The source and destination can be from the same or different memory locations. Both
source and destination must be described by a rectangular area. The source and
destination rectangles can be of the same size (most bit blits are of this nature) or of
different sizes, in which case, the operation becomes a stretch or shrink blit.
BitBLT supports ROP2, ROP3, and ROP4 which includes source, destination and
pattern, and an optional transparency color. Clipping can be performed on a primitive
basis.
p0 (left, top) p1 (right, top)
Destination
p0 (left, top)
p2 (left, bottom) p2 (right, bottom)

Source
p2 (left, bottom) p2 (right, bottom)
Figure 31-3. BitBLT
The graphics engine supports the following source and destination formats for data bit
blits and filter blits. In addition to these source and destination RGB formats, their
swizzle formats (ARGB, RGBA, ABGR, BGRA) are also supported.
Table 31-1. BitBLT Formats
Formats Source Image Destination Image
A1R5G5B5 Yes Yes
A4R4G4B4 Yes Yes
X1R5G5B5 Yes Yes

Table 31-1. BitBLT Formats (continued)

X4R4G4B4 Yes Yes
R5G6B5 Yes Yes
A8R8G8B8 Yes Yes
X8R8G8B8 Yes Yes
A8 Yes Yes
1-bit monochrome Yes No
8-bit color index No No
31.4.1.4 Stretch BLT
The stretch blit (Stretch BLT) primitive performs a bit blt operation with stretch or
shrink. The modified Bresenham algorithm is used to generate corresponding coordinates
for fast stretching. The stretch factor is specified in a 15.0 fixed-point format. Stretch blit
is not allowed to overlap, therefore no part of source and destination can share any piece
of memory. Non-stretch blits can overlap. For stretch blit, clipping is performed on a per
pixel basis.
31.4.1.5 Monochrome Expansion and Mask BLT

Monochrome expansion and mask blit are different operations, although both use the bit
stream from command buffer and both can be the source for ROP4 source selection. This
means that each output pixel can be a combination of source, pattern, monochrome mask
(for masked blits) and destination.
31.4.1.5.1 Monochrome expansion

For monochrome expansion, the bit from the stream is used to switch on/off a solid color
that is defined in a register. This mechanism enables the use of just one bit per pixel to
represent colors. In effect, the MONO EXPANSION primitive increases color
representation from one bit per pixel to multiple bits per pixel. A typical application for
mono color is font drawing.
Monochrome expansion does not support overlapping of the source and destination. It is
the responsibility of the driver to make sure that the command will never be executed
with overlapping source and destination.

GPU2D OPERATIONS
31.4.1.5.2 Mask BLT

For Mask BLT, the bit from the stream is used to toggle on/off a color in the source
frame buffer. Mask BLT takes its color source from memory and its monochrome mask
from the command stream. Clipping is supported and is performed on a per pixel basis.
31.4.1.6 Filter BLT

Filter blit performs high quality scaling, up or down, using an FIR re-sampling filter with
up to 9 taps. The sub-pixel coordinates (locations between the pixel grids) are generated
by the drawing engine. The filter block in the drawing engine uses the sub-pixel
information to select the appropriate filter kernel. R2D GPU processes 1 pixel every
cycle when performing filter blit.
A stretch- or shrink-factor of 15.16 fixed-point format is supported. To generate a single
destination pixel requires 9 source pixels. An image is scaled in two passes, one for X-
dimension (HOR_FILTER_BLT) and the other for Y-dimension (VER_FILTER_BLT).
The software sets up the filter kernel/coefficient table and the kernel size, as well as a
temporary buffer for storing intermediate results. After the first pass is completed,
intermediate results are sent back to memory, and then the second pass starts to scale the
first-pass image. Because of this two-step procedure, the throughput of FILTER BLT is
lower than that of STRETCH BLT. Also the Filter Kernel Table may need to be reloaded,
and some cycles are consumed in calculating the stepping parameters.
When the stretch or shrink factor is 1, the filterBlit works as a bitBlit copy. It can be used
as format converter in that case, for instance, YUV to RGB converter. To use as a format
converter, only one pass (HOR_FILTER_BLT or VER_FILTER_BLT) is needed. To
optimize the memory bandwidth, when using filterBlit to do YUV to RGB filtering, the
temporary target buffer format can be specified as YUY2 to process Y-dimension
filtering (VER_FILTER_BLT). This is to avoid converting YUV to A8R8G8B8 in the
1st vertical pass to reduce the memory bandwidth and increase the pixel processing rate.
This is the only special case that GPU may use YUY2 as target format.
The Filter BLT primitive supports the following source and destination image formats:
Table 31-2. Filter BLT Formats
A1R5G5B5 Yes Yes
A4R4G4B4 Yes Yes
A8R8G8B8 Yes Yes
R5G6B5 Yes Yes
X1R5G5B5 Yes Yes

Table 31-2. Filter BLT Formats (continued)

X4R4G4B4 Yes Yes
X8R8G8B8 Yes Yes
YUV NV12 (4:2:0, 2 planes) Yes No
NV16 (4:2:2, 2 planes) Yes No
UYVY (4:2:2, interleave) Yes No
YUY2 (4:2:2, interleave) Yes No
YV12 (4:2:0, 3 planes) Yes No
8-bit color index Yes No
A8 Yes Yes
31.4.1.7 R2D Performance of different operations

Table 31-3. Performance of different operations without rotation
Primitive Peak Source/destination overlap Clipping
Performance
Line 1 pixel / cycle N/A Done on pixel basis
Rectangle 2.4 pixel / cycle N/A Done on primitive basis
Clear 2.4 pixel / cycle N/A Done on primitive basis
Blit 2.4 pixel / cycle Overlap is allowed Done on primitive basis
Stretch blit 1 pixel / cycle No overlap allowed Done on pixel basis
Monochrome expansion 1.6 pixel / cycle No overlap allowed Done on pixel basis
Filter blit 1 pixel / cycle N/A N/A
Table 31-4. Performance of different operations with rotation

Primitive Performance Source/destination overlap Clipping
Line 1 pixel / cycle N/A Done on pixel basis
Rectangle 2 pixel / cycle N/A Done on primitive basis
Clear 2 pixel / cycle N/A Done on primitive basis
Blit 2 pixel / cycle Overlap is allowed Done on primitive basis
Stretch blit 1 pixel / cycle No overlap allowed Done on pixel basis
Monochrome expansion 1 pixel / cycle No overlap allowed Done on pixel basis
Filter blit 1 pixel / cycle N/A N/A
NOTE
The performance decreases for filter blit operations which
require two passes.

GPU2D OPERATIONS
31.4.1.8 Rotation
• 90° / 180° / 270° / X-Flip / Y-Flip/ Mirror rotation is supported for all primitives.
31.4.1.9 Transparency Mode

For monochrome expansion:
• Opaque
• Conditional transparency: Transparent if the current pixel matches the specified
value.
For blits:
• Opaque
• Masked transparency: Transparent if the mask for the current pixel or pattern is zero.
• Source Conditional transparency: Transparent if the source pixel is within the
specified value range.
• Destination Conditional transparency: Transparent if the destination pixel is not
within the specified value range.
31.4.1.10 Clipping
One clipping rectangle is supported for all bit blit primitives.
31.4.1.11 R2D GPU Data Formats

The graphics engine supports the following source and destination formats for data bit
blits and filter blits. In addition to these source and destination RGB formats, their
swizzle formats (ARGB, RGBA, ABGR, BGRA) are also supported. For YUV formats,
the GPU supports their U/V swap formats.
Table 31-5. Data Formats
Format Bit Blit Bit Blit Stretch Stretch Filter Blit Filter Blit OPF Input OPF Dst
Input Output Blit Input Blit Dst Input Dst
A1R5G5B5 Y Y Y Y Y Y Y Y
X1R5G5B5 Y Y Y Y Y Y Y Y

Table 31-5. Data Formats (continued)

Format Bit Blit Bit Blit Stretch Stretch Filter Blit Filter Blit OPF Input OPF Dst
Input Output Blit Input Blit Dst Input Dst
R5G6B5 Y Y Y Y Y Y Y Y
A8 Y Y Y Y Y Y Y Y
YUY2 (4:2:2) Y N Y N Y N Y N
UYVY (4:2:2) Y N Y N Y N Y N
YV12 (4:2:0) Y N Y N Y N Y N
NV12 Y N Y N Y N Y N
NV16 Y N Y N Y N Y N
8-bit color index Y N Y N Y N N N
1-bit monochrome Y N N N N N N N
31.4.1.12 ARGB Data Conversion of R2D GPU

The pixels read from source or destination will be expanded into A8R8G8B8 format to
maintain lossless pixel operations. The resulting pixels will be converted into the
destination format.
31.4.1.13 YUV to RGB Conversion of R2D GPU

YUV data can be converted into 8-bit per component RGB format at the output of the
cache only. Once converted, there is no way back to YUV format. GPU supports BT.601
and BT.709 YUV to RGB color conversion standards.
In BT.601, the YUV to RGB conversion is done using the following approximation:
16 <= Y <= 235
16 <= U <= 240
16 <= V <= 240
A = Y - 16
B = U - 128
C = V - 128
R = clip(( 298*A + 410*C + 128) >> 8)
G = clip((298*A - 101*B - 209*C + 128) >> 8)
B = clip((298*A + 519*B + 128) >> 8)
The Y, U and V components are clamped prior to the conversion.
GPU2D OPERATIONS
Y is clamped between 16 and 235, inclusively.

U and V are clamped between 16 and 240, inclusively.
In BT.709, the R, G, B equations are slightly changed to
R = clip(( 298*A + 461*C + 128) >> 8)
G = clip((298*A - 55*B - 137*C + 128) >> 8)
B = clip((298*A + 543*B + 128) >> 8)
31.4.1.14 Color Index Input Conversion Support of R2D GPU

Color index is supported for source data only. A look-up table with 256 entries is
provided for indexing the data. The table is fully programmable. The conversion is done
when pixels are read out of the cache.
31.4.1.15 Source/Destination Pre-multiply and De-Multiply Support

GPU supports source pre-multiply source alpha or global alpha, or source global color for
global colorizing. On destination, the GPU supports destination pre-multiply destination
alpha, destination de-multiply alpha.
31.4.1.16 Alpha Blending

The GPU supports alpha blending together with ROP. The alpha blending function is
performed on ROP function result source.
The general alpha blending equations are:
Cd = Fs * Cs' + Fd * Cd'
Ad = Fs * As'' + Fd * Ad''
Where
• Cs' is the source color component (adjusted for NPM if necessary)
• Cd' is the destination color component (adjusted for NPM if necessary)
• As'' is the modified source alpha component
• Ad'' is the modified destination alpha component
• Fs is fraction of the source that contributes to the final value
• Fd is fraction of the destination that contributes to the final value
The blending is done in 5 logical stages (not real implementation stages):
1. Transparent/opaque conversion

• In this stage, the incoming alpha (source or destination independently) can be

inverted if needed to match the internal alpha rule. Internally, an alpha of 0
means transparent, while an alpha of "0xFF" means opaque. External content
might follow the opposite rule. The output of the block is either As (Ad for
destination) or 1-As (1-Ad for destination).
2. Global value substitution
• A global alpha value from a register can be used to substitute or scale the
incoming alpha. An incoming alpha As can pass-through, be directly substituted
by Ags (global alpha) or scaled by the global alpha value (As * Ags). The source
and destination have distinct global alpha values.
3. Blending factor generation
• At this stage, the blending factors are generated (refer to table below). Each
alpha can take the values 0, 1, A or 1-A depending on the blending mode.
4. Final blending
• This is the final stage which implements blending equations.
The fractions take the values described in the following table, depending on the
blending mode.
Table 31-6. Blending Modes Fractions
Description
Blending Mode Fs Fd
Clear 0 0
SRC 1 0
DST 0 1
SRC_OVER 1 1 - As''
DST_OVER 1 - Ad'' 1
SRC_IN Ad'' 0
DST_IN 0 As''
SRC_OUT 1 - Ad'' 0
DST_OUT 0 1 - As''
SRC_ATOP Ad'' 1 - As''
DST_ATOP 1 - Ad'' As''
XOR 1 - Ad'' 1 - As''
To control the blending modes, the following register fields are used:
• 1 bit for transparent/opaque conversion for source alpha

GPU2D OPERATIONS
• 1 bit for transparent/opaque conversion for destination alpha

• 2 bits for source alpha modifications, to specify the 3 cases (As, Ags, As*Ags)
• 2 bits for destination alpha modifications, to specify the 3 cases (Ad, Agd,
Ad*Agd)
• 4 bits to select between the 12 blending modes
• 8 bits for global source alpha
• 8 bits for global destination alpha
Alpha blending is supported on bit blit and filter blit primitives.
31.4.1.17 GPU Cache Management

The software cache flush is supported to flush the GPU cache to memory. Auto-flush of
GPU cache is also supported. The software sets up the auto-flush interval, and hardware
will do the cache flush automatically at programmable intervals.

Chapter 32
32.1 Overview
The GPU3D is a high-performance core that delivers hardware acceleration for 3D
graphics display.
Addressable screen sizes range from the smallest cell phones to HD 1080p displays. It
provides high performance, high quality graphics, low power consumption, and the
smallest silicon footprint.
GPU3D accelerates numerous 3D graphics applications, including graphical user
interfaces (GUI), menu displays, flash animation, and gaming. This module supports the
following graphics APIs:
• OpenGL ES 2.0
• OpenGL ES 1.1
• OpenVG 1.1
• DirectX 11 (9_3)
• OpenGL 2.1 and 3.0
• OpenCL 1.1 E
• EGL 1.4
32.2 GPU3D Block Diagram

The main functional units of the GPU3D are shown in the figure below and their
description is as follows:
• Host Interface: Allows GPU3D to communicate with external memory and the CPU
through AXI or AHB bus. In this block data crosses clock domain boundaries.
• Memory Controller: Internal memory management unit that controls the block-to-
host memory request interface.

GPU3D Block Diagram
• Graphic Pipeline Front End: Inserts high level primitives and commands into the
graphics pipeline.
• Ultra-threaded Unified Shader: SIMD processor that performs as both vertex shader
and fragment shader. When used as a vertex shader it performs geometry
transformations and lighting computations. When used as a fragment shader, it
applies texture data and computes color values for each pixel. GPU3D has four such
shaders.
• 3D Rendering Engine: Converts triangles and lines into pixels. Computes slopes of
color attributes and texture coordinates. Performs clipping.
• Texture Engine: Retrieves texture information from memory upon request by the
fragment shader. Performs interpolation and filtering, and transfers the computed
value to the fragment shader or the vertex shader. The texture unit can process 2
pixels or 2 vertices/cycle.
• Pixel Engine/Resolve: Pixel engine does alpha blending and visible surface
determination. Resolve does tiling and de-tiling as well as FSAA filtering. The pixel
engine can process 2 pixels/cycle.
GC GPU CORE
AHB AXI0 AXI1
Host Interface
Memory Controller
3-D Pipeline
Texture
3D Rendering
Engine
Engine
Graphics Pixel
Pipeline Engine
Front Fnd Ultra-threaded Unifed Shader
up to 256 threads per shader
Figure 32-1. GPU3D Top Level Block Diagram

There are two main clocks for the processing control: shader clk for the shader part, and
core clk for the remaining part. The core clk and shader clk frequency are programmable
in CCM module (as the clk frequency for GPU3D_CORE_CLK_ROOT,
GPU3D_SHADER_CLK_ROOT).
The GPU3D provides architectural support for the following features:
Table 32-1. GPU3D Architectural Support
Feature GPU Support
Primary API OpenGL ES1.1, 2.0, and 3.0 OpenCL1.1
Additional API's OpenVG1.1
OpenGL
OpenCL
Other Graphics Support EGL1.4
Drivers OpenGLES1.1 and Halti
OpenVG1.1
EGL1.4
OpenGL2.1 and 3.0
OpenCL1.1 EP
Operating Systems Windows CE
Linux Embedded
Z (depth) Early Z support included

Stencil Early stencil support included
Shader Languages GLSL ES 1.0
Shader model compatability Shader model 3.0
Shader types and execution units Four programmable Scalable Ultra-threaded Unified Shaders
(SIMD4:transcendental,ctl-flow,tx-load)
one instruction issue per shader per clock; IEEE 32-bit
floating-point pipeline supports long shader instructions
FSAA anti-aliasing mechanisms High quality MSAA 4x
MSAA 16x for OpenVG
Code and data memory location restrictions Unrestricted; arbitrary memory reads and writes
Physical address 32 bits
MMU description 32-bit virtual address, 4 kB pages, error reporting outside of
address space
TLB 4 cache lines per requestor
Resource locks with CPU Semaphore lock
Max memory latency without a performance hit 256 GPU cycles

GPU3D Hardware Features
32.3 GPU3D Hardware Features

The GPU3D block has the following hardware features:
• OpenGL ES 2.0 compliance, including extensions; OpenGL ES 1.1; OpenVG 1.1
• IEEE 32-bit floating-point pipeline
• Ultra-threaded, unified vertex and fragment shaders
• Low bandwidth at both high and low data rates
• Low CPU loading
• Up to 16 programmable elements per vertex
• Dependent texture operation with high-performance
• Alpha blending
• Depth and stencil compare
• Support for 16 fragment shader simultaneous textures
• Support for 16 vertex shader simultaneous textures
• Point sampling, bi-linear sampling, tri-linear filtering, and cubic textures
• Resolve and fast clear
• 8k x 8k texture size and 8k x 8k rendering target
• 8 Vertex DMA streams
• 2 texture units and 2 pixel units for higher pixel processing rate
Table 32-2. Unified vertex-fragment shader features
Feature GPU Support
Shader type and execution units Four (4) unified shaders, SIMD4, SFP32 Trans
Swizzle capabilities Full 32-bit word level swizzle in a 128-bit vector
GPR's per shader Up to 512 general purpose registers, 128 bits each
Uniform registers Vertex Shader: 168 registers, 128 bits each
Fragment Shader: 64 registers, 128 bits each
FP denorm and rounding options Denorms are set to zero. Supports rounding to zero.
Maximum number of data input attributes Maximum of 16 vertex shader input elements;
Maximum of 12 fragment shader input elements;
Maximum number of instructions 512 unified for both vertex and fragment shaders
Maximum number of vertex streams 8
Maximum number of threads in flight per shader core 256
Subroutines 4 levels
Conditional branch support GT, LT, EQ, GE, LE, NE, ISNAN, ISFINITY, ISINFINITY,
ISNORMAL, AND, OR, XOR, NOT, ANYMSB, ALLMSB,
SELMSB
Shader instruction rate 1-cycle throughput for all shader instructions
Floating-point instruction precision Transcendental: 22 bits
SIMD4 (vector): 23.5 bits
Fragment shader video Supports video texture

Table 32-2. Unified vertex-fragment shader features (continued)

Feature GPU Support
Control flow instructions Yes
Standard derivatives Yes
Integer pipeline Support 8, 16, 32-bit integer operations
Local shared memory 1 kB
L1 Cache 4 kB
Table 32-3. Vertex Processing Features

Feature GPU Support
Vx D3D, OGL ES formats supported BYTE, UBYTE, SHORT, USHORT, INT, UINT, DEC, UDEC,
FLOAT, FLOAT16, D3DCOLOR,
FIXED16DOT16,R10B10G10A02
Vertex data size limits 256 bytes
Pre shader cache 2 kB
Post shader cache 8/16 vertices
Table 32-4. Primitive Processing Features

Feature GPU Support
Primitives supported triangle strip, fan, and list; line strip line loop and list; point list
Vertex/primitive geometry input index sizes 8-bit ,16-bit and 32-bit indices
Setup parameters available to fragment shader 12 vec4 parameters; all available to fragment shader
Primitive restart Yes
AA line support Yes
Table 32-5. Texture Processing Features

Feature GPU Support
Fixed-point input texture formats A8, L8, I8, A8L8, ARGB4, XRGB4, ARGB8, XRGB8, ABGR8, XBGR8, R5G6B5, A1RGB5,
X1RGB5, YV12, YUY2, UYVY, D16, D24S8, A8_OES, DXT1, DXT2, DXT3, DXT4, DXT5,
EAC11, ETC1, A8G8, R10G10B10A02; all fixed-point formats are filtered. sRGB
conversion and Swizzling supported for color channels.
Bits Format Alpha R G B

16 ARGB4444 4 4 4 4
16 XRGB4444 4 don't care 4 4 4
16 ARGB1555 1 5 5 5
16 RGB565 0 5 6 5
32 ARGB8888 8 8 8 8

Table 32-5. Texture Processing Features (continued)

Feature GPU Support
32 ABGR8888 8 8 8 8
32 XBGR8888 8 don't care 8 8 8
Planes Format Mode Y U V UV YUYV UYVY

3 YV12 4:2:0 1 1 1
2 NV12 4:2:0 1 1
1 YUY2 4:2:2 1
1 UYVY 4:2:2 1
Texture compression 4 bits and 8 bits per texel

Compressed texture formats DXT1, DXT2, DXT3, DXT4, DXT5, EAC11, ETC1,
All compressed formats are filtered.
Texture size maximum 8k x 8k
Addressing modes Wrap, mirror, clamp
Mipmap support 14 mipmap levels; programmable LOD biasing & replacement
Shadow texture Depth texture PCF filtering
Texture cache organization Tiled, 4x4 texels; Linear, 1x16 texels
Texture cache size 32 cache lines, with 64 bytes per cache line; 2 KB texture cache total
Texture coordinate fraction bits 5 bits
Texture sampler units 12 samplers, indexable
Textures per fragment maximum 8 texture samplers
Dependent texture operation High performance; unlimited dependent texture reads
Dependent tx per fragment max, No limit
relative sampling
Texture repeat max 256
Texture types 2D, cube map, 1D, projected, depth, bump map, displacement map, PCF, 3D, texture array
Texture filters Point sample, bi-linear, tri-linear, quad-linear, Anistropic
Texture component mapping: Supports both D3D and OES options
D3D, OGL, ES options
Texture size types Power-of-2, Non-square, Non-power-of-2
Texture swizzle Yes
32.3.1 Rasterization
Table 32-6. Rasterization features
Feature GPU Support

Table 32-6. Rasterization features (continued)

Interpolant attributes limit 12
Hierarchical Z Yes
Render target size 8K x 8K
Clipping window support Yes
Centroid interpolation Yes
32.3.2 Fragment Processing

Table 32-7. Fragment Processing Features
Feature GPU Support
FSAA mechanisms MSAA 4x, SSAA 4x;
FSAA mechanisms using fragment centroid MSAA 4x
Fragment color, alpha, Z, stencil precision

Table 32-7. Fragment Processing Features (continued)
Bits Format Alpha R B G
16 ARGB4444 4 4 4 4
4
16 XRGB4444 4 4 4
don't care
16 ARGB1555 1 5 5 5
16 XRGB1555 1 5 5 5
don't care
16 RGB565 0 5 6 5
32 ARGB8888 8 8 8 8
32 XRGB8888 8 8 8 8
don't care
32 ABGR8888 8 8 8 8
8
32 XBGR8888 don't care 8 8 8
32 RGB10_a2ui 2 10 10 10
Bits Format Depth Stencil
16 D16 16 0
32 D2488 24 8
Fragment storage 16-bit color and z, 32-bit color and z for each fragment. Lossless compression,
no storage reduction.
Individual fragment alpha masking Yes
Two sided stencil support Yes
Fragment cache 32 cache lines for color 32 cache lines for Z 64 bytes per cache line
32 cache lines for Z
Multiple render target Yes

32.3.3 Dest/Alpha Blending

Table 32-8. Dest/Alpha Blending Features
Feature GPU Support
Destination color formats
Bits Format Alpha R B G
16 ARGB4444 4 4 4 4
16 ARGB1555 1 5 5 5
16 RGB565 0 5 6 5
32 ARGB8888 8 8 8
32 ABGR8888 8 8 8
32 RGB10_a2ui 10 10 10
Blend modes Porter-Duff blending modes

Render target dithering support Yes
32.3.4 Z/Stencil Buffer

Table 32-9. Z/Stencil Buffer Features
Feature GPU Support
Z/stencil formats 16-bit Z; 24-bit Z plus 8-bit stencil, with lossless compression
support
Z/stencil buffer 32 cache lines; 64 bytes per line;
Z compression Yes, 30% - 70%
Stencil compression Yes
Fast clear and initialization options Yes

Usage Mode
32.3.5 Render Target

Feature GPU Support
Formats 16-bit and 32-bit, with lossless compression support
RT buffer cache 32 cache lines; 64 bytes per line;
RT caches are fully set associative.
Compressed formats Yes, 30% - 70%
Fast clear and initialization options Yes
Multi-Render Target support 4 Targets
32.4 Usage Mode

The GPU3D should be programmed through the NXP provided driver. NXP does not
provide support for software that directly programs the GPU3D registers. APIs for
programming the GPU3D through the software driver are described in separate driver
documentation.

Chapter 33
HDMI Transmitter (HDMI)
33.1 Overview
33.1.1 HDMI Operational Model Overview

The High Definition Multimedia Interface (HDMI) is a wired digital interconnect that
replaces the analog TV out or VGA out.
HDMI is capable of transferring uncompressed video, audio, and data using a single
cable. The video pixel rates are typically from 25 MHz up to 266 MHz (and 3D video
modes), but HDMI can support higher rates up to 266 MHz. It can support S/PDIF
(IEC60958 L-PCM and IEC61937 compressed non-linear PCM: AC-3, MPEG-1/-2
Audio, DTS®, MPEG-2/-4 AAC, ATRAC, WMA, MAT) and Parallel HBR (high bit
rate) audio interface, enabling the support of Dolby® True-HD and DTS-HD Master
Audio. HDMI has the capability of automatically setting the display format configuration
(intelligent link).
HDMI include a content protection system called HDCP (High-bandwidth Data Content
Protection). The HDMI connections can be used to connect DVD recorders, set-top
boxes, and game consoles to flat panel televisions and an AV amplifier that can act as
repeater/router.
HDMI system architecture consists of sources (transmitter) and sinks (receiver). As
shown in the figure below, the HDMI cable and connectors carry four differential pairs
that make up the TMDS data and clock channels. These channels are used to carry video,
audio, and auxiliary data. In addition, HDMI carries a VESA Data Display Channel
(DDC). The DDC is used for configuration and status exchange between a single source
and a single sink. The optional CEC protocol provides high-level control functions
between all of the various audiovisual products in a user's environment.

Overview
HDMI Source HDMI Sink
Video TMDS Channel 0 Video
Audio TMDS Channel 1 Audio

HDMI HDMI
Transmitter Receiver
Control/Status TMDS Channel 2 Control/Status
TMDS Clock Channel
EDID
Display Data Channel (DDC) ROM
CEC CEC
CEC Line
HEAC Utility Line HEAC
detect
HPD Line
High/Low
Figure 33-1. HDMI Block Diagram
Audio, video, and auxiliary data is transmitted across the three TMDS data channels. A
TMDS clock running at 1x (24-bit true color mode), the video pixel rate is transmitted on
the TMDS clock channel and used by the receiver as a frequency reference for data
recovery on the three TMDS data channels. Video data can have a pixel size of 24bits .
Video at the default 24-bit color depth is carried at a TMDS clock rate equal to the pixel
clock rate. Higher color depths are carried using a correspondingly higher TMDS clock
rate. Video formats with TMDS rates below 25MHz (such as, 13.5MHz for 480i/NTSC)
can be transmitted using a pixel-repetition scheme. The video pixels can be encoded in
either RGB, YCBCR 4:4:4, or YCBCR 4:2:2 formats.
HDMI uses a packet structure to transmit audio and auxiliary data across the TMDS
channels. To attain the highest reliability required of audio and control data, this data is
protected with a BCH error correction code and is encoded using a special error reduction
code to produce the transmitted 10-bit word.
Basic audio functionality consists of a single IEC 60958 L-PCM audio stream (two audio
channels) at sample rates of 32 KHz, 44.1 KHz, or 48 KHz, which can accommodate any
normal stereo stream. Optionally, HDMI can carry audio at sample rates up to 192KHz
Chapter 33 HDMI Transmitter (HDMI)
and with three to eight audio channels. HDMI can also carry an IEC 61937 compressed
(such as, surround sound) audio stream at bit rates up to 24.576 Mbps. For bit rates above
6.144 Mbps, compressed audio streams conforming to IEC 61937 are carried using HBR
Audio Stream Packets. Each packet carries four IEC 60958 frames, which corresponds to
(4x2x16 =) 128 contiguous bits of an IEC 61937 stream.
The source uses the DDC to read the sink's Enhanced Extended Display Identification
Data (E-EDID) to obtain the sink's configuration and/or capabilities.
The HDMI TX Controller schedules the three periods: Video Data Period, Data Island
period, and Control period. During the Video Data Period, the active pixels of an active
video line are transmitted. During the Data Island period, audio and auxiliary data are
transmitted using a series of packets. The Control period is used when no video, audio, or
auxiliary data needs to be transmitted. A Control Period is required between any two
periods that are not Control Periods.
An example of each period placement is shown in the figure below.
TMDS Periods in 720x480 Video Frame
Data Island Period

Vertical
Control Period
Control Period
Total Lines
Active Lines
525
Data Video Data Period

Island Active Video
Period
480
Horizontal
Horizontal Blanking
Blanking 720 Active Pixels
858 Total Pixels
Figure 33-2. TMDS Periods in 720x480p Video Frame
33.1.1.1 Interfaces
HDMI TX has the following interfaces:

Overview
• HDCP interface
• External ROM interface for key storage
• External RAM interface for revocation
• Random number generator interface
• Video input interface
• RGB 4:4:4
• YCbCr4:2:2
• YCbCr4:4:4
• Digital audio input interface
• AHB audio DMA
• System interface
• AMBA AHB
• Scan test interface
• HDMI TX PHY interface
• CEC interface
33.1.1.2 Features
HDMI TX includes the following features:
• Supported video formats:
• All CEA-861-E video formats up to 1080p at 60Hz and 720p/1080i at 120Hz
• Supported colorimetry:
• 24bit RGB 4:4:4
• 24bit YCbCr 4:4:4
• 16bit YCbCr 4:2:2
• xvYCC601
• xvYCC709
• Integrated color space converter:
• RGB(4:4:4) to/from YCbCr(4:4:4 or 4:2:2)
• Optional HDMI 1.4a supported video formats:
• HDMI 1.4a 3D video modes with up to 266MHz (TMDS clock)
• Optional HDMI 1.4a supported colorimetry:
• sYCC601
• Adobe RGB
• Adobe YCC601
• Optional HDMI 1.4a supported Infoframes:
• Audio InfoFrame packet extension to support LFE playback level information
• AVI infoFrame packet extension to support YCC Quantization range (Limited
Range, Full
• Range)

• AVI infoFrame packet extension to support Content type (Graphics, Photo, Cinema,
Game)
• Supported Audio formats:
• Up to four I2S interface for eight-channel Linear-PCM audio
• S/PDIF interface for linear and non-linear PCM formats:
• AC-3
• MPEG-1/-2 Audio
• DTS
• MPEG- 2/-4 AAC
• ATRAC
• WMA
• MAT
• Parallel audio interface for High-Bit Rate (HBR) Audio:
• Dolby® True-HD
• DTS®-HD Master Audio
• Generic Parallel Audio interface
• AHB DMA Audio interface
• Up to 192 KHz IEC60958 audio sampling rate
• Pixel clock from 13.5MHz up to 266 MHz
• Option to remove pixel repetition clock (prepclk) from HDMI TX interface for an
easy integration with third-party HDMI TX PHYs
• Flexible synchronous enable per clock domain to set functional power down modes
• Register access:
• AMBA AHB
• I2C DDC, EDID block read mode
• Advanced PHY testability
• Integrated CEC hardware engine

See HDMI PHY for external signal information.
33.3 Clocks
The table found here describes the clock sources for HDMI.

information.
Table 33-1. HDMI Clocks
iahbclk ahb_clk_root Bus clock
icecclk ckil_sync_clk_root CEC low-frequency clock (32kHZ)
ihclk ahb_clk_root Module clock
isfrclk video_27m_clk_root Internal SFR clock (video clock 27MHz)

This section describes the functional architecture of the HDMI TX controller.
33.4.1 HDMI TX Functional Overview

The HDMI TX provides a variety of standard audio, video, and system interfaces.
It includes an high-bandwidth data content protection (HDCP) encryption engine for
HDMI receiver authentication, revocation, and data encryption.
Figure below illustrates the top level diagram of the HDMI TX solution.

HDMI TX controller
References
Video Sampler Color Video

Video Space Packetizer HDMI_TX_CLK_P
Converter PLL HDMI_TX_CLK_N
Interface
HDMI_TX_DATA0_P
PLL HDMI_TX_DATA0_N
Audio Frame HDCP HDMI_TX_DATA1_P

Audio DMA Packetizer Composer Encryptor PLL HDMI_TX_DATA1_N
Interface
HDMI_TX_DATA2_P
Audio Sampler
PLL HDMI_TX_DATA2_N
Register I2C Master HDMI TX PHY

Control AMBA AHB
Bank
Interface I2C/DDC
HDMI_TX_DDC_SCL
Master
Main Control HDMI_TX_DDC_SDA
Logic HDMI_TX_DDC_CEC
CEC
Configuration
& Controller
Control
Figure 33-3. HDMI TX Top Level Block Diagram
The HDCP encryption engine is responsible for HDMI receiver authentication,

revocation, and data encryption.
The input video stream can be either RGB 4:4:4, YcbCr 4:2:2, or YcbCr 4:44 in single
data rate (SDR) bus formats as described in Table 33-2. The video mode's timing format
must follow the CEA-861-E specification. An embedded color space conversion allows
the pixel color format to be converted on the HDMI source side to match the best with
the HDMI sink capabilities. 24
The input audio stream can be provided through audio AHB DMA interface;
Finally, HDMI_TX can output video in full HD with up to 48-bit color mode and inserts
high fidelity audio up to eight-channels over low resolution video formats by performing
automatic pixel repetition over the input video stream.
33.4.2 Video Pixel Sampler

The Video pixel sampler block is responsible for the video data synchronization,
according to the video data input mapping defined by the Color Depth (Deep Color) and
format configuration.

Optionally, for YCbCr 4:2:2 format, data mapping can be performed to conform to ITU.
601 and ITU.656 standards but without the support of embedded synchronizers.
The video pixel sampler registers base address is 0x0200.
33.4.2.1 HDMI Transmitter Controller Databook Functional

Description
Table 33-2. Input Data Mapping
Video Input ivdata[47:0] mapping
Format
Color Color 47-4 45- 43- 41- 39- 37- 35- 33- 31-3 29- 27- 25- 23- 21- 19- 17- 15-1 13- 11- 9- 7 5 3- 1-
Space Depth 6 44 42 40 38 35 34 32 0 28 26 24 22 20 18 16 4 12 10 8 - - 2 0
6 4
RGB 8-bit R[7:0] G[7:0] B[7:0]
4:4:4
YCbCr 8-bit Cb[7:0] Y[7:0] Cr[7:0]
4:4:4
YCbCr 8-bit Cb[7:0] Y[7:0]
4:2:2 Cr[7:0] Y[7:0]
For each video timing format, there is a specific timing parameters defined in the
CEA-861-E specification.
The following timing diagram is an example for the video mode format 1 (640x480p @
59.94/60 Hz): Data Enable = idataen, HSYNC = ihsync, VSYNC = ivsync.

800 Total Horizontal Clocks per line
Data
Enable
160 640 Clocks for Active Video
16 48 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines 480 Active Vertical Lines
Data
Enable
800 clocks 144

16
HSYNC
515 515 517 24 525 1 2 3 4 5 6 7 35 36 515 516 525
VSYNC
Figure 33-4. Timing Parameters for 640x480p @ 59.94/60 Hz
For a complete list of timing parameters and diagrams, refer to the CEA-861-E
specification. The SDR video sample input format is illustrated in the figure below.

idataen
ipclk
idata Data N Data N + 1
Figure 33-5. Video Sample Timing Interface for RGB and YCbCr SDR Format
33.4.3 Supported Video Mode

The table below shows examples of the supported video modes.
Table 33-3. Video Modes
2D 3D Structure
VideoMod Mode HxV Refre 2D Frame Field Line Side- L+depth L Side- Top-
e Active sh Pixel Packin Alt. Alt. by- Pixel +depth by- and-
Resolutio Rate Rate g Pixel Pixel Pixel Side Rate + Side Bottom
n (pixel) (Hz) (Mp/s Rate Rate Rate (full) (Mp/s) graphic (Half) Pixel
) (Mp/s) (Mp/s) (Mp/s) Pixel s+ Pixel Rate
Rate graphic Rate (Mp/s)
(Mp/s) s- (Mp/s)
depth
Pixel
Rate
(Mp/s)
ALL Interlace Progr. ALL Progr. Progr. ALL ALL
CEA d Only CEA Only Only CEA CEA
Only
Primary HDMI Video Format Timings (CEA-861-
E)

Table 33-3. Video Modes (continued)

1 640x480p 640 x 480 59.94 25.18 50.35 50.35 50.35 50.35 100.70 25.18 25.18
(EDTV)
1 60.00 25.2 50.40 50.40 50.40 50.40 100.80 25.2 25.2
19 1280x720p 1280 x 50.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25
(HDTV) 720
4 59.94 74.18 148.35 148.35 148.35 148.35 296.70 74.18 74.18
4 60.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25
20 1920x1080i 1920 x 50.00 74.25 148.50 148.50 148.50 74.25 74.25
(HDTV) 1080
5 59.94 74.18 148.35 148.35 148.35 74.18 74.18
5 60.00 74.25 148.50 148.50 148.50 74.25 74.25
2.3 720x480p 720 x 480 59.94 27.00 54.00 54.00 54.00 54.00 108.00 27.00 27.00
(EDTV)
2.3 60.00 27.03 54.05 54.05 54.05 54.05 108.11 27.03 27.03
6.7 720(1440)x4 1440 x 59.94 27.00 54.00 54.00 54.00 27.00 27.00
80i (SDTV) 480
6.7 60.00 27.03 54.05 54.05 54.05 27.03 27.03
17.18 720x576p 720 x 576 50.00 27.00 54.00 54.00 27.00 27.00
(EDTV)
21.22 720(1440)x5 1440 x 50.00 27.00 54.00 54.00 54.00 27.00 27.00
76i (SDTV) 576
Secondary HDMI video format timings (CEA-861-
E)
8.9 720(1440)x2 1440 x 59.94 27.00 54.00 54.00 54.00 54.00 108.00 27.00 27.00
40p 240
8.9 60.00 27.03 54.05 54.05 54.05 54.05 108.11 27.03 27.03
10.11 1440(2880)x 2880 x 59.94 54.00 108.00 108.00 108.00 54.00 54.00
480i 480
10.11 60.00 54.05 108.11 108.11 108.11 54.05 54.05
12.13 1440(2880)x 2880 x 59.94 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
240p 240
12.13 60.00 54.05 108.11 108.11 108.11 108.11 216.22 54.05 54.05
32 1920x1080p 1920 x 23.98 74.18 148.35 148.35 148.35 148.35 296.70 74.18 74.18
(HDTV) 1080
32 24.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25
33 25.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25
34 29.97 74.18 148.35 148.35 148.35 148.35 296.70 74.18 74.18
34 30.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25
31 50.00 148.5 297.00 297.00 297.00 297.00 148.5 148.5
16 59.94 148.3 296.70 296.70 296.70 296.70 148.35 148.35
5
16 60.00 148.5 297.00 297.00 297.00 297.00 148.5 148.5
64 100.0 297.0 297.00 297.00
0 0


63 120.0 297.0 297.00 297.00
0 0
40 1920x1080i 1920 x 100.0 148.5 297.00 297.00 297.00 148.5 148.5
(HDTV) 1080 0
46 119.8 148.3 296.70 296.70 296.70 148.35 148.35
8 5
46 120.0 148.5 297.00 297.00 297.00 148.5 148.5
0
60 1280x720p 1280 x 24.00 59.40 118.80 118.80 118.80 118.80 237.60 59.40 59.40
(HDTV) 720
61 25.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25
62 30.00 74.25 148.50 148.50 148.50 148.50 297.00 74.25 74.25
41 100.0 148.5 297.00 297.00 297.00 297.00 148.5 148.5
0
47 119.8 148.3 296.70 296.70 296.70 296.70 148.35 148.35
8 5
47 120.0 148.5 297.00 297.00 297.00 297.00 148.5 148.5
0
29, 30 1440x576p 1440 x 50.00 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
(EDTV) 576
37.38 2880x576p 2880 x 50.00 108.0 216.00 216.00 216.00 216.00 108.00 108.00
(EDTV) 576 0
14.15 1440x480p 1440 x 59.94 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
(EDTV) 480
14.15 60.00 54.05 108.11 108.11 108.11 108.11 216.22 54.05 54.05
35.36 2880x480p 2880 x 59.94 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
(EDTV) 480
35.36 60.00 54.05 108.11 108.11 108.11 108.11 216.22 54.05 54.05
48.49 720x480p 720 x 480 119.8 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
(EDTV) 8
48.49 120.0 54.05 108.11 108.11 108.11 108.11 216.22 54.05 54.05
0
56.57 239.7 108.0 216.00 216.00 216.00 216.00 108.00 108.00
6 0
56.57 240.0 108.1 216.22 216.22 216.22 216.22 108.11 108.11
0 1
50.51 720(1440)x4 1440 x 119.8 54.00 108.00 108.00 108.00 54.00 54.00
80i (SDTV) 480 8
50.51 120.0 54.05 108.11 108.11 108.11 54.05 54.05
0
58.59 239.7 108.0 216.00 216.00 216.00 108.00 108.00
6 0
58.59 240.0 108.1 216.22 216.22 216.22 108.11 108.11
0 1
42.43 720x576p 720 x 576 100.0 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
(EDTV) 0


52.53 200.0 108.0 216.00 216.00 216.00 216.00 108.00 108.00
0 0
44.45 720(1440)x5 1440 x 100.0 54.00 108.00 108.00 108.00 54.00 54.00
76i (SDTV) 576 0
54.55 200.0 108.0 216.00 216.00 216.00 108.00 108.00
0 0
23.24 720(1440)x2 1440 x 50.00 27.00 54.00 54.00 54.00 54.00 108.00 27.00 27.00
88p 288
25.26 720(1440)x5 1440 x 50.00 54.00 108.00 108.00 108.00 54.00 54.00
76i 576
27.28 1440(2880)x 2880 x 50.00 54.00 108.00 108.00 108.00 108.00 216.00 54.00 54.00
288p 288
39 1920x1080i 1920 x 50.00 72.00 144.00 144.00 144.00 72.00 72.00
1080
33.4.4 Video Packetizer

This block is responsible for:
• Pixel repetition (if not already performed in the input video stream and needed by the
user)
• 10-bit, 12-bit, and 16-bit packing when in deep color modes
• YCC 422 remapping according to the HDMI 1.4a specification
• Clock rate transformation from pixel or repetition clock to the final TMDS clock
domain (by means of FIFOs)
The figure below depicts a functional diagram of the Video Packetizer block.

default_phase
fix_pp_to_last
cx_goto_p0
pp_en
bypass_selector pp_stuffing
output_selector
Input_data
Pixel
Packing
output_data
Pixel
Repeater 10, 12, 16
Packing Phase
FSM
16, 20, 24
YCC 422
remap
ycc422_size
ycc422_en
8-bit bypass
bypass en
Figure 33-6. Video Packetizer Functional Diagram
33.4.5 Color Space Conversion

This block is responsible for carrying out the following video color space conversion
functions:
• RGB to/from YCbCr
• 4:2:2 to/from 4:4:4 up (pixel repetition or linear interpolation)/down-converter
• Limited to/from full quantization range conversion

g_y_data[15:0] g_y_data_csc[15:0]
r_cr_data[15:0] r_cr_data_csc[15:0]
b_cb_data[15:0] YCbCr YCbCr YCbCr YCbCr YCbCr YCbCr b_cb_data_csc[15:0]
de 4:2:2 4:4:4 4:4:4 4:4:4 4:4:4 4:2:2 de_csc
hsync Chroma Color Chroma
hsync_csc
Interpolation Space Decimation
vsync vsync_csc
pixelclk pixelclk_csc
Figure 33-7. Color Space Converter Simplified Block Diagram
The Color Space Converter (CSC) supports all the timings reported in the CEA-861-D
specification and the following pixel modes:
• RGB444 and YCbCr444: 24, 30, 36, and 48 bits
• YCbCr422: 16, 20, and 24 bits
The color space conversion matrix is ruled by the following equations listed below. The
color space conversion registers base address is 0x4100.
out1 = (X1 x in1 /4096 + X2 x in2 /4096 + X3 x in3 /4096 + X4) x 2scale
out2 = (Y1 x in1 /4096 + Y2 x in2 /4096 + Y3 x in3 /4096 + Y4) x 2scale
out3 = (Z1 x in1 /4096 + Z2 x in2 /4096 + Z3 x in3 /4096 + Z4) x 2scale
33.4.6 Audio Interfaces

The supported audio input interfaces are:
• AHB Direct Memory Access (DMA)

No lipsync support is available inside the HDMI TX. If necessary, this feature can be
performed at the system audio processor side. From the HDMI TX, no audio/video delay
or skew is added.
The audio sampler registers base address is 0x3100.
33.4.6.1 CTS Calculation

Because there is no audio clock carried through the HDMI link, only the pixel clock is
used.
The CTS/N has to be set by software with value taken in the following table. Table below
shows the CTS and N value for the supported standard. All other TMDS clocks are not
supported; the TMDS clocks divided or multiplied by 1,001 coefficients are not
supported.
Table 33-4. N and CTS for 8-Bit Color Depth
TMDS Clock (MHz)
25.2 27 54 74.25 148.5 297
Fs N CTS N CTS N CTS N CTS N CTS N CTS
(kHZ)
32 4096 25200 4096 27000 4096 54000 4096 74250 4096 148500 3072 222750
44.1 6272 28000 6272 30000 6272 60000 6272 82500 6272 165000 4704 247500
48 6144 25200 6144 27000 6144 54000 6144 74250 6144 148500 5120 247500
88.2 12544 28000 12544 30000 12544 60000 12544 82500 12544 165000 9408 247500
96 12288 25200 12288 27000 12288 54000 12288 74250 12288 148500 10240 247500
176.4 25088 28000 25088 30000 25088 60000 25088 82500 25088 165000 18816 247500
192 24576 25200 24576 27000 24576 54000 24576 74250 24576 148500 20480 247500
768 Used for HBR audio only. N and CTS configured for Fs=192kHZ (1/4th ACR value per spec)
To support the deep color mode and/or 3D video modes, the TMDS clock is multiplied
by 4, 2, 1.5, or 1.25, depending on the mode. In this case, the CTS value must also follow
the same ratio.
33.4.6.2 Audio DMA Interface

This audio direct memory access (DMA) interface is intended for advanced systems
running 32-bit CPU SoC solutions.

This module provides a direct audio DMA interface, which is useful in systems where a
DSP handles audio processing. In these systems, sending the incoming audio samples
directly to the memory provides a cleaner architecture to the SoC, without the overhead
of converting several audio standards.
DMA FIFO Audio DMA BUFFER

(programmable FIFO Sync (Fixed 16 samples
29 depth) 29 per channel)
8
AHB Master
DMA
Engine
hclk tmdsclk
Figure 33-8. Audio DMA Block Diagram
The audio DMA block combines an AHB master interface with a FIFO to perform direct
memory access to audio samples stored in a system memory.
The DMA engine is configurable through programmable software registers to perform
autonomous burst reading on a configured memory range.
33.4.6.2.1 AHB Master

The AHB master is compliant with the AMBA AHB Specification, Revision 2.0 from
ARM.
It has the following features:
• Multi-master capable operation
• 32-bit data transfer
• OKAY, ERROR, RETRY, and SPLIT slave responses
• Rescheduling of burst requirements
• IDLE, NONSEQ, and SEQ transfer types
• Incremental burst modes: unspecified lengths (upper limit is 1 kB boundary) and
INCR, INCR4, INCR8, and INCR16 fixed-beat bursts
• Master burst lock mechanism

• Bus access granting

• The following features are not supported:
• Write transaction
• Protection control
• BUSY transfer type
• Wrapping burst
Data Organization in System Memory
The AHB master block fetches the samples from system memory. The Audio Samples
are organized according to the channel allocation.
For example, channel 0, 1, 3, 5 are enabled (0 and 1 are always enabled). The Audio
Samples must be organized in the system memory like the following:
Table 33-5. Audio Sample Arrangement in System Memory
Position Sample Channel
0 n-1 0
1 n-1 1
2 n-1 3
3 n-1 5
4 n-1 0
5 n-1 1
6 n-1 3
7 n-1 5
... ... ...
Table 33-6. Data Arrangement in System Memory for L-PCM (24 bits)
Bit Description
28 B - IEC B bit
27 P - Parity bit
26 C - Channel Status bit
25 U - User Data bit
24 V - Validity Bit
[23:0] Audio Sample Data
Table 33-7. Data Arrangement in System Memory for L-PCM (16 bits) and NL-PCM (16 bits)
Bit Description
28 B - IEC B bit
27 P - Parity bit
26 C - Channel Status bit

Table 33-7. Data Arrangement in System Memory for L-PCM (16 bits) and NL-PCM (16 bits)
(continued)
25 U - User Data bit
24 V - Validity Bit
[23:8] Audio Sample Data
[7:0] 0x00
33.4.6.2.2 DMA Engine

The DMA engine is responsible for requesting burst transfers to the AHB master, taking
into account the FIFO threshold and register settings.
33.4.6.2.2.1 Functional Behavior

The engine:
• Arbitrates read requests to start the burst in the initial address with the size sufficient
to fill the FIFO (the size of the FIFO is a parameter in the audio DMA core).
• After this first request, the DMA engine performs subsequent burst requests
(incrementing accordingly ohaddr[31:0] and determining correct ohburst[2:0])
towards final_addr[31:0] configured at the register bank and taking into account the
AUDIO_FIFO_DEPTH parameter and fifo_threshold[7:0] configuration.
• In the burst mode (INCR4, INCR8, INCR16), the operation stops at the end of the
burst.
• Stops operation upon ERROR slave response, signaling ointerror interrupt and
staterror signal
• Continues burst transaction:
• Upon RETRY/SPLIT slave response, signaling ointretrysplit interrupt and
statretrysplit signal
• Upon losing ownership (no ihgrant) as consequence of arbiter action, signaling
ointlostownership interrupt and statlostownership signal
• Decides through register configuration which burst method (unspecified length
incrementing or fixed beat incrementing) to use in the read transfers
• Issues ointdone interrupt when it reaches final address reading or is stopped upon
user request
• Automatically starts new burst requests until the final_addr[31:0] is reached
• The DMA engine is either stopped by the user or an error/fail condition appears at
the slave response.
• Takes into account that an incrementing burst can be of any length (if unspecified
INCR type), but upper limit is set because the address must not cross a 1kB boundary

• A maximum theoretical length of a burst is 1024. The burst size must be declared on
the mburstlength_addr[10:0].
• Has INCR with an unspecified burst as the default operation burst mode
33.4.6.2.2.2 DMA Operation

Normal operation of the DMA engine is as follows:
1. The enable_hlock, incr_type[1:0], burst_mode, fifo_threshold[7:0],
initial_addr[31:0], and final_addr[31:0] are configured according to desired DMA
operation.
NOTE
Configured values have to follow these rules:
The number of memory positions (between initial_addr and final_addr) has to be a
multiple of theactive audio channels.
The final_addr[31:0] signal is always bigger than the initial_addr[31:0].
2. To start the audio DMA operation, a '1' is written to data_buffer_ready.
3. The DMA engine starts the operation. The first burst transfer is:
ohaddr[31:0] = initial_addr[31:0];
ohburst[2:0] = INCR;
mburstlength[10:0] = ((initial_addr[31:0] + AUDIO_FIFO_DEPTH) <=
final_addr[31:0]) ?
((AUDIO_FIFO_DEPTH < 1024) ? AUDIO_FIFO_DEPTH : 1024) : (final_addr[31:0] -
initial_addr[31:0]);
4. While DMA is reading samples from the AHB master and writing samples to the
Audio FIFO, a datafetch request from the internal frame composer block might
happen at the Audio FIFO interface, diminishing the number of samples in the FIFO.
5. When the number of samples in the Audio FIFO is lower than the configured
fifo_threshold[7:0], the DMA engine requests a new burst request to the AHB master
interface with:
ohaddr[15:0] = last address in step 5);
ohburst[2:0] = INCR;
mburstlength[10:0] = AUDIO_FIFO_DEPTH - fifo_threshold[7:0];
6. Steps 4) and 5) continue until the final_addr[31:0] is reached.

NOTE
In the last burst request, the DMA engine calculates the
mburstlength[10:0] such that the last requested read
position is the final_addr[31:0].
7. After completion of the DMA operation, the DMA engine issues the ointdone
interrupt signaling end of operation.
Variations of the DMA engine's behavior occur when fixed-beat, incremental bursts are
used by INCR4/INCR8/INCR16 burst selects. When this forcing mode is used, you must
correctly configure the FIFO's threshold such that the last of the consecutive INCRx
(with x = 4, 8, or 16) bursts correctly fill the FIFO at last burst received. Note there is a
re-alignment at the 1k boundary.
The following are exceptions to the described DMA behavior:
1. When a user requests end stop_dma_transaction, the DMA engine stops at the end of
the current burst operation and signals its completion with an ointdone interrupt.
2. When the AHB slave sends an error response, the DMA engine stops the current
operation and signals ointerror interrupt.
Rules for Configuration of Address Registers:
1. Configure the last 2 bits of initial_addr with 0.
For example, 32’h0000_0000.
2. Configure the last 2 bits of final_addr with non-zero values.
For example
32’hxxx_xxx3 or
32’hxxx_xxx7 or
32’hxxx_xxxB or
32’hxxx_xxxF
Where x= any value
3. The number of samples is calculated by using the following formula:
Number of samples = (final_addr - initial_addr + 1) / 4
Therefore, final_addr = (Number of samples x 4) + initial_addr -1
If a defined length burst is used, align initial_addr, final_addr and

fifo_threshold with the value. If
the burst is not aligned, DMA uses AHB INCR transfers when required.

Then the number of samples = 100 (a multiple of 5)
4. The threshold must be
Greater than the selected FIFO DEPTH;
Greater than the number of channels enabled in channel allocation.
Due to the limit of audio DMA design, some registers configuration are updated by
SDMA (Smart Direct Memory Access). SDMA need to do these items below:
1. clear the audio DMA done request(actually it’s an interrupt); set offset 0x00120109
-- bit2.
2. configure next audio DMA start address(offset 0x00123604~0x00123607) and next
stop address(offset 0x00123608~0x0012360b); Start address and stop address are
provided by S/W and it’s variable.
3. Set offset 0x00123601 – bit0 “1” to start DMA;
33.4.6.2.2.3 Transfer Data, Package, and Word

One transfer data can be composed of several transfer packages, and one transfer package
can be composed of one or several transfer bursts. One transfer burst can be composed of
several transfer words.
The figure below shows the transfer data structure for a fixed-beat, incremental burst.
Package 1 Package M
. . . . . . burst2 . . .
burst1 burst2 burstN burst1 burstN
word1 word2 . . . wordL
L = 4(for INCR4), 8(INCR8), 16(INCR16)
Figure 33-9. Transfer Data Constitution for Fixed-Beat, Incremental Burst
The figure below depicts the transfer data structure for an unspecified burst length.

Package 1 Package M
burst1 . . . burst1
word1 word2 . . . wordL
L = unspecified number for INCR
Figure 33-10. Transfer Data Constitution for Unspecified Burst Length
The figure below illustrates the DMA state machine.
dy
rea DMA IDLE
er_
uff
ta_b
da Next Cycle
Next Cycle
DMA REQ DMA ERR DMA STOP
When on pkg xter finished On Error Condition

or lost ownership
Required Transfer When stop_dma_transaction

Information DMA XFER asserted or final address reached
(addr, pkg length, etc.)
Figure 33-11. DMA FSM Diagram
1. When the operation request is written into the data_buffer_ready, the state switches
from IDLE to DMAREQ.
2. When enough transfer information is ready, the state changes to DMAXFER.

3. When one package is completed-indicated by "OnePackOver"-or a lost ownership

occurs, the state jumps back to DMAREQ, so the new transaction information can be
calculated.
4. When the DMA is ready again, it jumps to DMAXFER.
The previous steps continue until you request an end operation or until the whole
operation is completed.
33.4.6.2.3 Audio FIFO

This block contains a FIFO with a configurable depth.
The statthrfiffoempty flag is a version of the FIFO empty, that is active whenever the
amount of samples in the FIFO is smaller than four samples. The AHB_DMA_THRSLD
and the statthrfifoempty indicators are different. The AHB_DMA_THRSLD defines the
occupation of the FIFO, while statthrfifoempty helps the HDMI TX's Frame Composer in
the audio packet composition (required when non-linear audio is being packed, in which
case four pair of samples are needed to compose one packet).
33.4.6.2.4 FIFO Occupancy/FIFO Almost Empty Flags

The FIFO depth is configured by setting the AUDIO_FIFO_DEPTH parameter in
coreConsultant. The FIFO occupancy is calculated from the pointer values.
Also, the most significant pointer bits are used to perform the following calculation:
occupancy = wrptr[n-1:0] - rdptr_previous[n-1:0], if wrptr > rdptr_previous
occupancy = AUDIO_FIFO_DEPTH + wrptr[n-1:0] - rdptr_previous[n-1:0], if wrptr <

rdptr_previous
If occupancy is less than 4, then statthrfifoempty is active.

An example of full/empty flags and FIFO occupancy is shown in the figure below.

N FIFO_RP
FIFO_RP
FIFO_RP
FIFO_WP
FIFO_WP FIFO_WP
FIFO_WP
FIFO_WP
0
FIFO_RP FIFO_RP
Normal IF Write IF Read IF Read will Occupancy
condition Will FULL Will EMPTY threshold Below
EMPTY threshold
Have No data
data inside
inside
Figure 33-12. Audio FIFO Status Indication
33.4.7 Supported Audio Formats

The HDMI TX has several audio interfaces and each of them has different audio format
support capabilities.
Table below represents the audio interface and format dependencies.
Table 33-8. Supported Audio Formats
Audio Input Interface Audio Format Supported
Audio DMA Up to eight channels L-PCM/NL-PCM and HBR audio, allowing all audio formats listed
to support one single audio DMA interface.
33.4.8 Frame Composer

This block is responsible for assembling video, audio, and data packets in a consistent
frame that are streamed to the HDCP cipher and then finally to the HDMI TX PHY.

The HDMI 1.3a standard precisely describes the packet insertion timing and distribution
that must be followed to correctly compose an HDMI TMDS (transition minimized
differential signaling) stream. In this context, there are data island packets that-when
available (ready for insertion in output stream)-have higher priority over others. Two
packet descriptor queues are responsible for prioritizing packet insertion.
The higher priority packets are described in Table below. These packets are inserted in
the output stream as soon as data to compose them is available (see the HDMI 1.3a
standard).
Table 33-9. High Priority Data Island Packets
Packet Description
Audio Clock Regeneration (ACR) Indicates to sink device the N/CTS values that should be used in the ACR process
Audio Sample (AUDS) Transports L-PCM and IEC 61937 compressed audio
General Control (GCP) Indicates Color Depth, Pixel Packing phase, and AV mute information to sink device
The packets described in tables below can be considered as low priority packets-even
though they have precise timing insertion-because their insertion timing is large (for
example, one per frame or one per two frames without specific location for some of the
packet types and on user request transmit for others).
Table 33-10. Low Priority Data Island Packets
Packet Description
Audio Content Protection (ACP) Used to convey content-related information about the active audio stream
transmitted
Audio InfoFrame (AUDI) Indicates characteristics of the active audio stream by using IEC 60958 channel
status bits, IEC 61937 burst info, and/or stream data (if present).
Null (NULL) Ignored by sink devices.
International Standard Recording Code See HDMI 1.3a section 5.3.8.
(ISRC1/ISRC2)
Vendor Specific (VSD) InfoFrame According to CEA-861-E standard.
AVI infoFrame (AVI) Video information from source to sink.
Source Data Product Descriptor (SPD) Name and product type of the source device. MPEG (MPEG) Source InfoFrame
infoFrame packets (optional, implementation discouraged by CEA-861-E Section 6.7).
Describes several aspects of the compressed video stream that were used to
produce the uncompressed video.
The Frame Composer distributes and assembles the data island packets according to the
module register bank configuration. The block allows extended control periods to appear
with a certain programmed spacing. The Frame Composer uses two packet buffers that
allow a packet to be composed while another is being sent to the output HDMI stream.

Packet requests are inserted into the packet queues by a data island flexible scheduler.
The HDMI 1.3a specification requires that packet distribution and insertion timing
correctly compose an output HDMI TMDS stream. In this context, there are data island
packets that are sent on data availability, while others are sent once per frame or once per
two frames. and finally others that are sent on user request. Classification of the packets
according to this insertion timing is described in the table below.
Table 33-11. Packet Classification
Packet Classification
Audio Clock Regeneration (ACR) Sent on data availability.
Audio Sample (AUDS) Sent on data availability (precede ACR if present).
Audio Content Protection (ACP) On user request or automatic insertion.
Audio InfoFrame (AUDI) Once per two frames.
Null (NULL) On user request or automatic insertion to fill Data Island period.
General Control (GCP) Once per frame.
International Standard Recording Code (ISRC1/ On user request.
ISRC2)
Vendor Specific (VSD) InfoFrame On user request or automatic insertion.
AVI infoFrame (AVI) Once per frame.
Source Data Product Descriptor (SPD) infoFrame On user request or automatic insertion.
The Data Island Scheduler (DIS) handles packet distribution in the Frame Composer. The
DIS is a round- robin (RDRB) state machine that is able to schedule packet insertion on
an input video frame or line basis. The DIS is fully configurable and can schedule any
packet type to be inserted at a given input video frame rate or input video line rate.
While determining packet distribution on an input video frame or line basis, the DIS
schedules the packets to be inserted in the output HDMI stream by inserting the packet
descriptor in the corresponding packet priority queue, according to packet priority
classification.
After the packet descriptor has been inserted in the packet priority queues, the Data
Island Packer (DIP) is responsible for assembling and sequencing the packets for output
HDMI stream insertion.
Dedicated ECC generators and checksum byte-wide sum hardware generate the BCH
ECC parity codes and infoFrames checksums for all the data islands packets.
The content of GCP, ISRC1/2, VSD, AVI, SPD, and MPEG packets are configured
through the registers bank starting at address 0x1000.

33.4.9 HDCP Encryption Engine

HDCP is designed to protect the transmission of audio-visual content between an HDCP
Transmitter and an HDCP Receiver.
The system also allows for HDCP Repeaters that support downstream HDCP-protected
interface ports. The HDCP system allows up to seven levels of HDCP Repeaters and as
many as 128 total HDCP devices, including HDCP Repeaters, to be attached to an
HDCP-protected interface port.
NOTE
This feature must be configured and requires a separate license.
Contact your NXP representative for more information on
HDCP.
The authentication protocol enables the HDCP Transmitter to verify that a given HDCP
Receiver is licensed. With the legitimacy of the Receiver determined, encrypted HDCP
content is transmitted between the two based on shared secrets established during
authentication. In the event that legitimate devices are compromised to permit
unauthorized use of the content, renewability allows an HDCP Transmitter to identify
such compromised devices and prevent the transmission of the content.
The implemented HDCP functionality is compliant with HDCP revision 1.4. The HDCP
transmitter implements the three layers of the HDCP cipher, including LFSR and other
functions required to generate the encryption key bytes that are then XORed with the
data.
33.4.10 EDID/HDCP I2C E-DDC Interface

The E-DDC channel is a dedicated I2C master interface that allows the read of sink E-
EDID based on system needs.
Data read from sink E-EDID can be then transferred to the I2C Master register bank,
starting at address 0x7E00.
This block reads the E-EDID (and all its segments according to user configuration) and,
after completion, it warns the CPU of data availability. This block also arbitrates the I2C
master interface to allow the HDMI TX's HDCP authentication protocol to be performed
through this interface. Sink HDCP links (with addresses 0x74 and/or 0x76) should be
present at these lines to enable HDCP-compliant behavior.
The interface is shared with the DDC channel of the HDMI controller through
multiplexers and is I2C compliant.

33.4.10.1 I2C Master Interface Normal Mode

This operation implements a single read or write operation using the Special Function
Register configuration.
The I2C data transfer protocol used is the 7-bit addressed, as defined in Section 9 of the
I2C-bus Specification, version 2.1.
S slaveaddr[6:0] W A addr[7:0] datao[7:0] A/A PA/A
Legend:
Transaction from master to slave A - Acknowledge (sdao low)

A - not Acknowledge (sdao high)
Transaction from slave to master S - Start condition
P - Stop condition
W - Write indication
Figure 33-13. Data Write Transaction
S Slaveaddr[6:0] W A addr[7:0] A/A Sr slaveddr[6:0] R A datai[7:0] A P
A - Acknowledge (sdao low)

Legend: A - not Acknowledge (sdao high)
Transaction from master to slave S - Start condition
Sr - Repeated start condition
Transaction from slave to master P - Stop condition
W - Write indication
R - Read indication
Figure 33-14. Data Read Transaction

33.4.10.2 I2C Master Interface Extended Read Mode

This I2C extended read mode operation implements a segment pointer-based read
operation using the Special Register configuration.
B segaddr[6:0] W X segpointer[7:0] X Br slaveaddr[6:0] W A addr[7:0] A/A Br slaveaddr[6:0] R A data[7:0] A P
Transaction from master to slave
Transaction from slave to master
A- Acknowledge (sdao low)

A- No Acknowledge (sdao high)
B- Start Condition
Br - Repeated Start Condition
P- Stop Condition
W- Write Condition
R- Read Condition
X- Don't Care
Figure 33-15. Extended Data Read Operation
33.4.11 System Configuration Interfaces

The internal register set is distributed with the HDMI TX. The system interface (the
interface that connects to the processor bus) bridges these registers using a simple
standard interface.
The system interface is AMBA AHB,.
The AHB bridges the bus to the internal SFR bus.
33.4.11.1 AMBA AHB Slave Interface

The AMBA AHB slave interface is compatible with the AMBA Specification, revision
2.0.
The AHB slave interface is used for register configuration implementing only a simple
transaction mode and single master slave operation.
The HDMI TX does not support protection control, burst transfers, or split transactions.
33.4.12 CEC Hardware Engine

Consumer Electronics Control (CEC) is a protocol that provides high-level control
functions between all of the various audiovisual products in a user's environment.

It is an optional feature in the HDMI 1.3a Specification. It uses only one bidirectional
line for transmission and reception.
All transactions on the CEC line consist of an initiator and one or more followers. The
initiator is responsible for sending the message structure and the data. The follower is the
recipient of any data and is responsible for setting any acknowledgement bits.
ocecout
CEC
icecin
Engine
Configuration
Register
Bank
Figure 33-16. CEC Engine Simplified Block Diagram
There are two operation modes for a CEC controller.

• Initiator Mode
• In this mode, the CEC controller sends messages out and waits for a follower to
feedback. The CEC controller works in this mode when it starts to send a frame.
After the transmission is done, it automatically returns to the follower mode (no
software control involved).

HDMI Memory Map/Register Definition
• Follower Mode
• In this mode, the CEC controller receives messages and feeds back the initiator with
appropriate signals. The CEC controller always works in the follower mode
whenever it is not transmitting any data.
For correct CEC controller interface operation, initial reset is required in order to set
internal registers to a known state. After this reset, the interface is in an IDLE state,
waiting for a read or write request coming from the register configuration.
A specific CEC API is provided that implements all necessary low-level register
configuration to send and receive CEC messages. For more information, see the CEC
API documentation.
The CEC engine registers base address is 0x7D00. For more information about these
registers, see HDMI Memory Map/Register Definition.
For more information about CEC, see Consumer Electronics Control (CEC) Application
Note.
33.5 HDMI Memory Map/Register Definition
All registers are addressable on 32-bit boundaries; each unused bit or address location is
reserved for future use and read back as 0.
.
HDMI memory map
Absolute
Width Section/
(in bits) page
(hex)
12_0000 Design Identification Register (HDMI_DESIGN_ID) 8 R 00h 33.5.1/1395
12_0001 Revision Identification Register (HDMI_REVISION_ID) 8 R 00h 33.5.2/1396
12_0002 Product Identification Register 0 (HDMI_PRODUCT_ID0) 8 R 00h 33.5.3/1396
12_0003 Product Identification Register 1 (HDMI_PRODUCT_ID1) 8 R 00h 33.5.4/1397
12_0004 Configuration Identification Register 0 (HDMI_CONFIG0_ID) 8 R 00h 33.5.5/1397
Frame Composer Interrupt Status Register 0
12_0100 8 w1c 00h 33.5.9/1400
(HDMI_IH_FC_STAT0)

HDMI memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
Frame Composer Interrupt Status Register 1 33.5.10/
12_0101 8 w1c 00h
(HDMI_IH_FC_STAT1) 1401
Frame Composer Interrupt Status Register 2 33.5.11/
12_0102 8 w1c 00h
(HDMI_IH_FC_STAT2) 1402
Audio Sampler Interrupt Status Register 33.5.12/
12_0103 8 w1c 00h
(HDMI_IH_AS_STAT0) 1403
PHY Interface Interrupt Status Register 33.5.13/
12_0104 8 w1c 00h
(HDMI_IH_PHY_STAT0) 1404
E-DDC I2C Master Interrupt Status Register 33.5.14/
12_0105 8 w1c 00h
(HDMI_IH_I2CM_STAT0) 1405
33.5.15/
12_0106 CEC Interrupt Status Register (HDMI_IH_CEC_STAT0) 8 w1c 00h
1406
Video Packetizer Interrupt Status Register 33.5.16/
12_0107 8 w1c 00h
(HDMI_IH_VP_STAT0) 1407
PHY GEN2 I2C Master Interrupt Status Register 33.5.17/
12_0108 8 w1c 00h
(HDMI_IH_I2CMPHY_STAT0) 1408
AHB Audio DMA Interrupt Status Register 33.5.18/
12_0109 8 w1c 00h
(HDMI_IH_AHBDMAAUD_STAT0) 1408
Frame Composer Interrupt Mute Control Register 0 33.5.19/
12_0180 8 R/W 00h
(HDMI_IH_MUTE_FC_STAT0) 1410
12_0181 8 R/W 00h
12_0182 8 R/W 00h
Audio Sampler Interrupt Mute Control Register 0 33.5.22/
12_0183 8 R/W 00h
(HDMI_IH_MUTE_AS_STAT0) 1412
PHY Interface Interrupt Mute Control Register 33.5.23/
12_0184 8 R/W 00h
(HDMI_IH_MUTE_PHY_STAT0) 1413
E-DDC I2C Master Interrupt Mute Control Register 33.5.24/
12_0185 8 R/W 00h
(HDMI_IH_MUTE_I2CM_STAT0) 1414
CEC Interrupt Mute Control Register 33.5.25/
12_0186 8 R/W 00h
(HDMI_IH_MUTE_CEC_STAT0) 1414
Video Packetizer Interrupt Mute Control Register 33.5.26/
12_0187 8 R/W 00h
(HDMI_IH_MUTE_VP_STAT0) 1415
PHY GEN 2 I2C Master Interrupt Mute Control Register 33.5.27/
12_0188 8 R/W 00h
(HDMI_IH_MUTE_I2CMPHY_STAT0) 1416
AHB Audio DMA Interrupt Mute Control Register 33.5.28/
12_0189 8 R/W 00h
(HDMI_IH_MUTE_AHBDMAAUD_STAT0) 1417
33.5.29/
12_01FF Global Interrupt Mute Control Register (HDMI_IH_MUTE) 8 R/W 03h
1418
Video Input Mapping and Internal Data Enable Configuration 33.5.30/
12_0200 8 R/W 01h
Register (HDMI_TX_INVID0) 1418
Video Input Stuffing Enable Register 33.5.31/
12_0201 8 R/W 00h
(HDMI_TX_INSTUFFING) 1419


Absolute
Width Section/
(in bits) page
(hex)
Video Input GY Data Channel Stuffing Register 0 33.5.32/
12_0202 8 R/W 00h
(HDMI_TX_GYDATA0) 1420
Video Input GY Data Channel Stuffing Register 1 33.5.33/
12_0203 8 R/W 00h
(HDMI_TX_GYDATA1) 1421
Video Input RCR Data Channel Stuffing Register 0 33.5.34/
12_0204 8 R/W 00h
(HDMI_TX_RCRDATA0) 1421
Video Input RCR Data Channel Stuffing Register 1 33.5.35/
12_0205 8 R/W 00h
(HDMI_TX_RCRDATA1) 1422
Video Input RCB Data Channel Stuffing Register 0 33.5.36/
12_0206 8 R/W 00h
(HDMI_TX_BCBDATA0) 1422
Video Input RCB Data Channel Stuffing Register 1 33.5.37/
12_0207 8 R/W 00h
(HDMI_TX_BCBDATA1) 1423
Video Packetizer Packing Phase Status Register 33.5.38/
12_0800 8 R 00h
(HDMI_VP_STATUS) 1423
Video Packetizer Pixel Repetition and Color Depth Register 33.5.39/
12_0801 8 R/W 00h
(HDMI_VP_PR_CD) 1424
Video Packetizer Stuffing and Default Packing Phase 33.5.40/
12_0802 8 R/W 00h
Register (HDMI_VP_STUFF) 1425
Video Packetizer YCC422 Remapping Register 33.5.41/
12_0803 8 R/W 00h
(HDMI_VP_REMAP) 1426
Video Packetizer Output, Bypass, and Enable Configuration 33.5.42/
12_0804 8 R/W 46h
Register (HDMI_VP_CONF) 1427
33.5.43/
12_0805 VP_STAT (HDMI_VP_STAT) 8 R 00h
1427
33.5.44/
12_0806 VP_INT (HDMI_VP_INT) 8 R 00h
1428
Video Packetizer Interrupt Mask Register 33.5.45/
12_0807 8 R/W 00h
(HDMI_VP_MASK) 1429
33.5.46/
12_0808 VP_POL (HDMI_VP_POL) 8 R/W FFh
1430
Frame Composer Input Video Configuration and HDCP 33.5.47/
12_1000 8 R/W 70h
Keepout Register (HDMI_FC_INVIDCONF) 1431
Frame Composer Input Video HActive Pixels Register 0 33.5.48/
12_1001 8 R/W 00h
(HDMI_FC_INHACTIV0) 1432
Frame Composer Input Video HActive Pixels Register 1 33.5.49/
12_1002 8 R/W 00h
(HDMI_FC_INHACTIV1) 1433
Frame Composer Input Video HBlank Pixels Register 0 33.5.50/
12_1003 8 R/W 00h
(HDMI_FC_INHBLANK0) 1433
Frame Composer Input Video HBlank Pixels Register 1 33.5.51/
12_1004 8 R/W 00h
(HDMI_FC_INHBLANK1) 1434
Frame Composer Input Video VActive Pixels Register 0 33.5.52/
12_1005 8 R/W 00h
(HDMI_FC_INVACTIV0) 1435
Frame Composer Input Video VActive Pixels Register 1 33.5.53/
12_1006 8 R/W 00h
(HDMI_FC_INVACTIV1) 1435


Absolute
Width Section/
(in bits) page
(hex)
Frame Composer Input Video VBlank Pixels Register 33.5.54/
12_1007 8 R/W 00h
(HDMI_FC_INVBLANK) 1436
Frame Composer Input Video HSync Front Porch Register 0 33.5.55/
12_1008 8 R/W 00h
(HDMI_FC_HSYNCINDELAY0) 1436
Frame Composer Input Video HSync Front Porch Register 1 33.5.56/
12_1009 8 R/W 00h
(HDMI_FC_HSYNCINDELAY1) 1437
Frame Composer Input Video HSync Width Register 0 33.5.57/
12_100A 8 R/W 00h
(HDMI_FC_HSYNCINWIDTH0) 1438
Frame Composer Input Video HSync Width Register 1 33.5.58/
12_100B 8 R/W 00h
(HDMI_FC_HSYNCINWIDTH1) 1438
Frame Composer Input Video VSync Front Porch Register 33.5.59/
12_100C 8 R/W 00h
(HDMI_FC_VSYNCINDELAY) 1439
Frame Composer Input Video VSync Width Register 33.5.60/
12_100D 8 R/W 00h
(HDMI_FC_VSYNCINWIDTH) 1439
Frame Composer Input Video Refresh Rate Register 0 33.5.61/
12_100E 8 R/W 00h
(HDMI_FC_INFREQ0) 1440
12_100F 8 R/W 00h
12_1010 8 R/W 00h
Frame Composer Control Period Duration Register 33.5.64/
12_1011 8 R/W 00h
(HDMI_FC_CTRLDUR) 1442
Frame Composer Extended Control Period Duration 33.5.65/
12_1012 8 R/W 00h
Register (HDMI_FC_EXCTRLDUR) 1442
Frame Composer Extended Control Period Maximum 33.5.66/
12_1013 8 R/W 00h
Spacing Register (HDMI_FC_EXCTRLSPAC) 1443
Frame Composer Channel 0 Non-Preamble Data Register 33.5.67/
12_1014 8 R/W 00h
(HDMI_FC_CH0PREAM) 1443
12_1015 8 R/W 00h
12_1016 8 R/W 00h
Frame Composer AVI Configuration Register 3 33.5.70/
12_1017 8 R/W 00h
(HDMI_FC_AVICONF3) 1445
Frame Composer GCP Packet Configuration Register 33.5.71/
12_1018 8 R/W 00h
(HDMI_FC_GCP) 1445
Frame Composer AVI Packet Configuration Register 0 33.5.72/
12_1019 8 R/W 00h
Frame Composer AVI Packet Configuration Register 1 33.5.73/
12_101A 8 R/W 00h
FC_AVICONFFrame Composer AVI Packet Configuration 33.5.74/
12_101B 8 R/W 00h
Register 2 (HDMI_FC_AVICONF2) 1448
Frame Composer AVI Packet VIC Register 33.5.75/
12_101C 8 R/W 00h
(HDMI_FC_AVIVID) 1449


Absolute
Width Section/
(in bits) page
(hex)
Frame Composer AVI Packet End of Top Bar Register 0 33.5.76/
12_101D 8 R/W 00h
(HDMI_FC_AVIETB0) 1449
Frame Composer AVI Packet End of Top Bar Register 1 33.5.77/
12_101E 8 R/W 00h
(HDMI_FC_AVIETB1) 1450
Frame Composer AVI Packet Start of Bottom Bar Register 0 33.5.78/
12_101F 8 R/W 00h
(HDMI_FC_AVISBB0) 1450
Frame Composer AVI Packet Start of Bottom Bar Register 1 33.5.79/
12_1020 8 R/W 00h
(HDMI_FC_AVISBB1) 1451
Frame Composer AVI Packet End of Left Bar Register 0 33.5.80/
12_1021 8 R/W 00h
(HDMI_FC_AVIELB0) 1451
Frame Composer AVI Packet End of Left Bar Register 1 33.5.81/
12_1022 8 R/W 00h
(HDMI_FC_AVIELB1) 1452
Frame Composer AVI Packet Start of Right Bar Register 0 33.5.82/
12_1023 8 R/W 00h
(HDMI_FC_AVISRB0) 1452
Frame Composer AVI Packet Start of Right Bar Register 1 33.5.83/
12_1024 8 R/W 00h
(HDMI_FC_AVISRB1) 1453
Frame Composer AUD Packet Configuration Register 0 33.5.84/
12_1025 8 R/W 00h
(HDMI_FC_AUDICONF0) 1453
12_1026 8 R/W 00h
12_1027 8 R/W 00h
12_1028 8 R/W 00h
Frame Composer VSI Packet Data IEEE Register 0 33.5.88/
12_1029 8 R/W 00h
(HDMI_FC_VSDIEEEID0) 1455
Frame Composer VSI Packet Data Size Register 33.5.89/
12_102A 8 R/W 1Bh
(HDMI_FC_VSDSIZE) 1456
12_1030 8 R/W 00h
12_1031 8 R/W 00h
12_1032 8 R/W 00h
(HDMI_FC_VSDPAYLOAD0) 1457
12_1033 8 R/W 00h
12_1034 8 R/W 00h
12_1035 8 R/W 00h
12_1036 8 R/W 00h
12_1037 8 R/W 00h


Absolute
Width Section/
(in bits) page
(hex)
12_1038 8 R/W 00h
12_1039 8 R/W 00h
12_103A 8 R/W 00h
12_103B 8 R/W 00h
12_103C 8 R/W 00h
12_103D 8 R/W 00h
12_103E 8 R/W 00h
12_103F 8 R/W 00h
12_1040 8 R/W 00h
12_1041 8 R/W 00h
12_1042 8 R/W 00h
12_1043 8 R/W 00h
12_1044 8 R/W 00h
12_1045 8 R/W 00h
12_1046 8 R/W 00h
12_1047 8 R/W 00h
12_1048 8 R/W 00h
12_1049 8 R/W 00h
Frame Composer SPD Packet Data Vendor Name Register 33.5.116/
12_104A 8 R/W 00h
0 (HDMI_FC_SPDVENDORNAME0) 1469
Frame Composer SPD Packet Data Product Name Register 33.5.117/
12_1052 8 R/W 00h
0 (HDMI_FC_SPDPRODUCTNAME0) 1470
Frame Composer SPD Packet Data Source Product 33.5.118/
12_1062 8 R/W 00h
Descriptor Register (HDMI_FC_SPDDEVICEINF) 1470
Frame Composer Audio Sample Flat and Layout 33.5.119/
12_1063 8 R/W 00h
Configuration Register (HDMI_FC_AUDSCONF) 1471


Absolute
Width Section/
(in bits) page
(hex)
Frame Composer Audio Packet Sample Present Status 33.5.120/
12_1064 8 R 00h
Register (HDMI_FC_AUDSSTAT) 1471
Frame Composer Number of High Priority Packets Attended 33.5.121/
12_1073 8 R/W 0Fh
Configuration Register (HDMI_FC_CTRLQHIGH) 1472
Frame Composer Number of Low Priority Packets Attended 33.5.122/
12_1074 8 R/W 03h
Configuration Register (HDMI_FC_CTRLQLOW) 1473
Frame Composer ACP Packet Type Configuration Register 33.5.123/
12_1075 8 R/W 00h
0 (HDMI_FC_ACP0) 1473
Frame Composer ACP Packet Type Configuration Register 33.5.124/
12_1091 8 R/W 00h
1 (HDMI_FC_ACP1) 1474
FC_ISCR1_Frame Composer Packet Status, Valid, and 33.5.125/
12_1092 8 R/W 00h
Continue Configuration Register (HDMI_FC_ISCR1_0) 1474
Frame Composer ISCR1 Packet Body Register 1 33.5.126/
12_1093 8 R/W 00h
(HDMI_FC_ISCR1_1) 1475
Frame Composer ISCR2 Packet Body Register 0 33.5.127/
12_10A3 8 R/W 00h
(HDMI_FC_ISCR2_0) 1475
Frame Composer Data Island Auto Packet Scheduling 33.5.128/
12_10B3 8 R/W 00h
Register 0 (HDMI_FC_DATAUTO0) 1476
12_10B4 8 R/W 00h
12_10B5 8 R/W 00h
Frame Composer Data Island Manual Packet Request 33.5.131/
12_10B6 8 W 00h
Register (HDMI_FC_DATMAN) 1478
12_10B7 8 R/W 0Fh
Frame Composer Round Robin ACR Packet Insertion 33.5.133/
12_10B8 8 R/W 00h
Register 0 (HDMI_FC_RDRB0) 1480
12_10B9 8 R/W 00h
12_10BA 8 R/W 00h
12_10BB 8 R/W 00h
12_10BC 8 R/W 00h
12_10BD 8 R/W 00h
12_10BE 8 R/W 00h
12_10BF 8 R/W 00h
33.5.141/
12_10D0 FC_STAT0 (HDMI_FC_STAT0) 8 R 00h
1484


Absolute
Width Section/
(in bits) page
(hex)
33.5.142/
12_10D1 FC_INT0 (HDMI_FC_INT0) 8 R/W 00h
1485
Frame Composer Packet Interrupt Mask Register 0 33.5.143/
12_10D2 8 R/W 25h
(HDMI_FC_MASK0) 1486
33.5.144/
12_10D3 FC_POL0 (HDMI_FC_POL0) 8 R/W FFh
1487
33.5.145/
12_10D4 FC_STAT1 (HDMI_FC_STAT1) 8 R/W 00h
1488
33.5.146/
1488
Frame Composer Packet Interrupt Mask Register 1 33.5.147/
12_10D6 8 R/W 00h
(HDMI_FC_MASK1) 1489
33.5.148/
12_10D7 FC_POL1 (HDMI_FC_POL1) 8 R/W FFh
1490
33.5.149/
12_10D8 FC_STAT2 (HDMI_FC_STAT2) 8 R/W 00h
1491
33.5.150/
1492
Frame Composer High/Low Priority Overflow Interrupt Mask 33.5.151/
12_10DA 8 R/W 00h
Register 2 (HDMI_FC_MASK2) 1492
33.5.152/
12_10DB FC_POL2 (HDMI_FC_POL2) 8 R/W 03h
1493
Frame Composer Pixel Repetition Configuration Register 33.5.153/
12_10E0 8 R/W 10h
(HDMI_FC_PRCONF) 1494
Frame Composer GMD Packet Status Register 33.5.154/
12_1100 8 R 00h
(HDMI_FC_GMD_STAT) 1495
Frame Composer GMD Packet Enable Register 33.5.155/
12_1101 8 R/W 00h
(HDMI_FC_GMD_EN) 1496
Frame Composer GMD Packet Update Register 33.5.156/
12_1102 8 W 00h
(HDMI_FC_GMD_UP) 1496
Frame Composer GMD Packet Schedule Configuration 33.5.157/
12_1103 8 R/W 10h
Register (HDMI_FC_GMD_CONF) 1497
Frame Composer GMD Packet Profile and Gamut Sequence 33.5.158/
12_1104 8 R/W 00h
Configuration Register (HDMI_FC_GMD_HB) 1498
Frame Composer GMD Packet Body Register 0 33.5.159/
12_1105 8 R/W 00h
(HDMI_FC_GMD_PB0) 1498
12_1106 8 R/W 00h
12_1107 8 R/W 00h
12_1108 8 R/W 00h
12_1109 8 R/W 00h


Absolute
Width Section/
(in bits) page
(hex)
12_110A 8 R/W 00h
12_110B 8 R/W 00h
12_110C 8 R/W 00h
12_110D 8 R/W 00h
12_110E 8 R/W 00h
12_110F 8 R/W 00h
12_1110 8 R/W 00h
12_1111 8 R/W 00h
12_1112 8 R/W 00h
12_1113 8 R/W 00h
12_1114 8 R/W 00h
12_1115 8 R/W 00h
12_1116 8 R/W 00h
12_1117 8 R/W 00h
12_1118 8 R/W 00h
12_1119 8 R/W 00h
12_111A 8 R/W 00h
12_111B 8 R/W 00h
12_111C 8 R/W 00h
12_111D 8 R/W 00h
12_111E 8 R/W 00h
12_111F 8 R/W 00h


Absolute
Width Section/
(in bits) page
(hex)
12_1120 8 R/W 00h
Frame Composer Video/Audio Force Enable Register 33.5.187/
12_1200 8 R/W 00h
(HDMI_FC_DBGFORCE) 1512
Frame Composer Audio Channel 0 Register 0 33.5.188/
12_1201 8 R/W 00h
(HDMI_FC_DBGAUD0CH0) 1513
12_1202 8 R/W 00h
12_1203 8 R/W 00h
12_1204 8 R/W 00h
12_1205 8 R/W 00h
12_1206 8 R/W 00h
Frame Composer Debug Audio Channel 2 Register 0 33.5.194/
12_1207 8 R/W 00h
Frame Composer Debug Audio Channel 2 Register 1 33.5.195/
12_1208 8 R/W 00h
12_1209 8 R/W 00h
12_120A 8 R/W 00h
12_120B 8 R/W 00h
12_120C 8 R/W 00h
12_120D 8 R/W 00h
12_120E 8 R/W 00h
12_120F 8 R/W 00h
12_1210 8 R/W 00h
12_1211 8 R/W 00h
12_1212 8 R/W 00h
12_1213 8 R/W 00h
12_1214 8 R/W 00h


Absolute
Width Section/
(in bits) page
(hex)
12_1215 8 R/W 00h
12_1216 8 R/W 00h
12_1217 8 R/W 00h
12_1218 8 R/W 00h
Frame Composer TMDS Channel 0 Register 33.5.212/
12_1219 8 R/W 00h
(HDMI_FC_DBGTMDS0) 1525
12_121A 8 R/W 00h
12_121B 8 R/W 00h
33.5.215/
12_3000 PHY Configuration Register (HDMI_PHY_CONF0) 8 R/W 06h
1527
33.5.216/
12_3001 PHY Test Interface Register 0 (HDMI_PHY_TST0) 8 R/W 00h
1528
33.5.217/
12_3002 PHY Test Interface Register 1 (HDMI_PHY_TST1) 8 R/W 00h
1528
33.5.218/
12_3003 PHY Test Interface Register 2 (HDMI_PHY_TST2) 8 R 00h
1529
PHY RXSENSE, PLL lock, and HPD Status Register 33.5.219/
12_3004 8 R 00h
(HDMI_PHY_STAT0) 1529
PHY RXSENSE, PLL lock, and HPD Interrupt Register 33.5.220/
12_3005 8 R 00h
(HDMI_PHY_INT0) 1530
PHY RXSENSE, PLL lock, and HPD Mask Register 33.5.221/
12_3006 8 R/W 00h
(HDMI_PHY_MASK0) 1531
PHY RXSENSE, PLL lock and HPD Polarity Register 33.5.222/
12_3007 8 R/W F3h
(HDMI_PHY_POL0) 1532
PHY I2C Slave Address Configuration Register 33.5.223/
12_3020 8 R/W 00h
(HDMI_PHY_I2CM_SLAVE_ADDR) 1533
PHY I2C Address Configuration Register 33.5.224/
12_3021 8 R/W 00h
(HDMI_PHY_I2CM_ADDRESS_ADDR) 1533
PHY I2C Data Write Register 1 33.5.225/
12_3022 8 R/W 00h
(HDMI_PHY_I2CM_DATAO_1_ADDR) 1534
PHY I2C Data Write Register 0 33.5.226/
12_3023 8 R/W 00h
(HDMI_PHY_I2CM_DATAO_0_ADDR) 1535
PHY I2C Data Read Register 1 33.5.227/
12_3024 8 R 00h
(HDMI_PHY_I2CM_DATAI_1_ADDR) 1535
PHY I2C Data Read Register 0 33.5.228/
12_3025 8 R/W 00h
(HDMI_PHY_I2CM_DATAI_0_ADDR) 1536
PHY I2C Read/Write Operation 33.5.229/
12_3026 8 W 00h
(HDMI_PHY_I2CM_OPERATION_ADDR) 1536


Absolute
Width Section/
(in bits) page
(hex)
PHY I2C Done Interrupt Register 33.5.230/
12_3027 8 R/W 08h
(HDMI_PHY_I2CM_INT_ADDR) 1537
PHY I2C Done Interrupt Register 33.5.231/
12_3028 8 R/W 88h
(HDMI_PHY_I2CM_CTLINT_ADDR) 1538
PHY I2C Speed Control Register 33.5.232/
12_3029 8 R/W 0Bh
(HDMI_PHY_I2CM_DIV_ADDR) 1539
PHY I2C Software Reset Register 33.5.233/
12_302A 8 R/W 01h
(HDMI_PHY_I2CM_SOFTRSTZ_ADDR) 1539
PHY I2C Slow Speed SCL High Level Control Register 1 33.5.234/
12_302B 8 R/W 00h
(HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR) 1540
PHY I2C Slow Speed SCL High Level Control Register 0 33.5.235/
12_302C 8 R/W 6Ch
(HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR) 1541
PHY I2C Slow Speed SCL Low Level Control Register 1 33.5.236/
12_302D 8 R/W 00h
(HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR) 1541
PHY I2C Slow Speed SCL Low Level Control Register 0 33.5.237/
12_302E 8 R/W 7Fh
(HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR) 1542
PHY I2C Fast Speed SCL High Level Control Register 1 33.5.238/
12_302F 8 R/W 00h
(HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR) 1542
PHY I2C Fast Speed SCL High Level Control Register 0 33.5.239/
12_3030 8 R/W 11h
(HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR) 1543
PHY I2C Fast Speed SCL Low Level Control Register 1 33.5.240/
12_3031 8 R/W 00h
(HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR) 1543
PHY I2C Fast Speed SCL Low Level Control Register 0 33.5.241/
12_3032 8 R/W 24h
(HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR) 1544
Audio Clock Regenerator N Value Register 1 33.5.242/
12_3200 8 R/W 00h
(HDMI_AUD_N1) 1544
12_3201 8 R/W 00h
(HDMI_AUD_N2) 1545
12_3202 8 R/W 00h
(HDMI_AUD_N3) 1545
33.5.245/
12_3203 AUD_CTS1 (HDMI_AUD_CTS1) 8 R/W 00h
1546
33.5.246/
1546
33.5.247/
1547
33.5.248/
12_3600 Audio DMA Start Register (HDMI_AHB_DMA_CONF0) 8 R/W 00h
1547
33.5.249/
12_3601 AHB_DMA_START (HDMI_AHB_DMA_START) 8 R/W 00h
1548
33.5.250/
12_3602 Audio DMA Stop Register (HDMI_AHB_DMA_STOP) 8 R/W 00h
1549
Audio DMA FIFO Threshold Register 33.5.251/
12_3603 8 R/W 0100h
(HDMI_AHB_DMA_THRSLD) 1550


Absolute
Width Section/
(in bits) page
(hex)
Audio DMA Start Address Register 0 33.5.252/
12_3604 8 R/W 00h
(HDMI_AHB_DMA_STRADDR0) 1550
12_3605 8 R/W 00h
12_3606 8 R/W 00h
12_3607 8 R/W 00h
Audio DMA Stop Address Register 0 33.5.256/
12_3608 8 R/W 00h
(HDMI_AHB_DMA_STPADDR0) 1552
12_3609 8 R/W 00h
12_360A 8 R/W 00h
12_360B 8 R/W 00h
Audio DMA Burst Start Address Register 0 33.5.260/
12_360C 8 R 00h
(HDMI_AHB_DMA_BSTADDR0) 1554
12_360D 8 R 00h
12_360E 8 R 00h
12_360F 8 R 00h
Audio DMA Burst Length Register 0 33.5.264/
12_3610 8 R 00h
(HDMI_AHB_DMA_MBLENGTH0) 1556
Audio DMA Burst Length Register 1 33.5.265/
12_3611 8 R 00h
(HDMI_AHB_DMA_MBLENGTH1) 1557
Audio DMA Interrupt Status Register 33.5.266/
12_3612 8 R 00h
(HDMI_AHB_DMA_STAT) 1557
33.5.267/
12_3613 Audio DMA Interrupt Register (HDMI_AHB_DMA_INT) 8 R 00h
1558
Audio DMA Mask Interrupt Register 33.5.268/
12_3614 8 R/W 1111_0111h
(HDMI_AHB_DMA_MASK) 1559
Audio DMA Polarity Interrupt Register 33.5.269/
12_3615 8 R/W 1111_0111h
(HDMI_AHB_DMA_POL) 1560
Audio DMA Channel Enable Configuration Register 1 33.5.270/
12_3616 8 R/W 00h
(HDMI_AHB_DMA_CONF1) 1561
Audio DMA Buffer Interrupt Status Register 33.5.271/
12_3617 8 R 00h
(HDMI_AHB_DMA_BUFFSTAT) 1562
Audio DMA Buffer Interrupt Register 33.5.272/
12_3618 8 R 00h
(HDMI_AHB_DMA_BUFFINT) 1563
Audio DMA Buffer Mask Interrupt Register 33.5.273/
12_3619 8 R/W 11h
(HDMI_AHB_DMA_BUFFMASK) 1564


Absolute
Width Section/
(in bits) page
(hex)
Audio DMA Buffer Polarity Interrupt Register 33.5.274/
12_361A 8 R/W 11h
(HDMI_AHB_DMA_BUFFPOL) 1564
Main Controller Synchronous Clock Domain Disable 33.5.275/
12_4001 8 R/W 00h
Register (HDMI_MC_CLKDIS) 1565
Main Controller Software Reset Register 33.5.276/
12_4002 8 R/W FFh
(HDMI_MC_SWRSTZREQ) 1566
Main Controller Feed Through Control Register 33.5.277/
12_4004 8 R/W 00h
(HDMI_MC_FLOWCTRL) 1567
33.5.278/
12_4005 Main Controller PHY Reset Register (HDMI_MC_PHYRSTZ) 8 R/W 00h
1567
Main Controller Clock Present Register 33.5.279/
12_4006 8 w1c 00h
(HDMI_MC_LOCKONCLOCK) 1568
Main Controller HEAC PHY Reset Register 33.5.280/
12_4007 8 R/W 00h
(HDMI_MC_HEACPHY_RST) 1569
Color Space Converter Interpolation and Decimation 33.5.281/
12_4100 8 R/W 00h
Configuration Register (HDMI_CSC_CFG) 1569
Color Space Converter Scale and Deep Color Configuration 33.5.282/
12_4101 8 R/W 01h
Register (HDMI_CSC_SCALE) 1570
33.5.283/
12_4102 CSC_COEF_A1_MSB (HDMI_CSC_COEF_A1_MSB) 8 R/W 20h
1571
33.5.284/
12_4103 CSC_COEF_A1_LSB (HDMI_CSC_COEF_A1_LSB) 8 R/W 00h
1571
33.5.285/
1572
33.5.286/
1572
33.5.287/
1573
33.5.288/
1573
33.5.289/
1574
33.5.290/
1574
33.5.291/
12_410A CSC_COEF_B1_MSB (HDMI_CSC_COEF_B1_MSB) 8 R/W 00h
1575
33.5.292/
12_410B CSC_COEF_B1_LSB (HDMI_CSC_COEF_B1_LSB) 8 R/W 00h
1575
33.5.293/
12_410C CSC_COEF_B2_MSB (HDMI_CSC_COEF_B2_MSB) 8 R/W 20h
1576
33.5.294/
12_410D CSC_COEF_B2_LSB (HDMI_CSC_COEF_B2_LSB) 8 R/W 00h
1576
33.5.295/
12_410E CSC_COEF_B3_MSB (HDMI_CSC_COEF_B3_MSB) 8 R/W 00h
1577


Absolute
Width Section/
(in bits) page
(hex)
33.5.296/
12_410F CSC_COEF_B3_LSB (HDMI_CSC_COEF_B3_LSB) 8 R/W 00h
1577
33.5.297/
12_4110 CSC_COEF_B4_MSB (HDMI_CSC_COEF_B4_MSB) 8 R/W 00h
1578
33.5.298/
12_4111 CSC_COEF_B4_LSB (HDMI_CSC_COEF_B4_LSB) 8 R/W 00h
1578
33.5.299/
12_4112 CSC_COEF_C1_MSB (HDMI_CSC_COEF_C1_MSB) 8 R/W 00h
1579
33.5.300/
12_4113 CSC_COEF_C1_LSB (HDMI_CSC_COEF_C1_LSB) 8 R/W 00h
1579
33.5.301/
1580
33.5.302/
1580
33.5.303/
1581
33.5.304/
1581
33.5.305/
12_4118 CSC_COEFC4_MSB (HDMI_CSC_COEFC4_MSB) 8 R/W 00h
1582
33.5.306/
12_4119 CSC_COEFC4_LSB (HDMI_CSC_COEFC4_LSB) 8 R/W 00h
1582
33.5.307/
12_7D00 CEC_CTRL (HDMI_CEC_CTRL) 8 R/W 02h
1583
33.5.308/
12_7D01 CEC_STAT (HDMI_CEC_STAT) 8 R 00h
1584
33.5.309/
12_7D02 CEC_MASK (HDMI_CEC_MASK) 8 R/W 00h
1585
33.5.310/
12_7D03 CEC_POLARITY (HDMI_CEC_POLARITY) 8 R/W 7Fh
1586
33.5.311/
12_7D04 CEC_INT (HDMI_CEC_INT) 8 R 00h
1587
33.5.312/
12_7D05 CEC_ADDR_L (HDMI_CEC_ADDR_L) 8 R/W 00h
1588
33.5.313/
12_7D06 CEC_ADDR_H (HDMI_CEC_ADDR_H) 8 R/W 80h
1589
33.5.314/
12_7D07 CEC_TX_CNT (HDMI_CEC_TX_CNT) 8 R/W 00h
1590
33.5.315/
12_7D08 CEC_RX_CNT (HDMI_CEC_RX_CNT) 8 R 00h
1591
33.5.316/
12_7D10 CEC_TX_DATA (HDMI_CEC_TX_DATA0) 8 R/W 00h
1592
33.5.316/
1592


Absolute
Width Section/
(in bits) page
(hex)
33.5.316/
1592
33.5.316/
1592
33.5.316/
1592
33.5.316/
1592
33.5.316/
1592
33.5.316/
1592
33.5.316/
1592
33.5.316/
1592
33.5.316/
12_7D1A CEC_TX_DATA (HDMI_CEC_TX_DATA10) 8 R/W 00h
1592
33.5.316/
12_7D1B CEC_TX_DATA (HDMI_CEC_TX_DATA11) 8 R/W 00h
1592
33.5.316/
12_7D1C CEC_TX_DATA (HDMI_CEC_TX_DATA12) 8 R/W 00h
1592
33.5.316/
12_7D1D CEC_TX_DATA (HDMI_CEC_TX_DATA13) 8 R/W 00h
1592
33.5.316/
12_7D1E CEC_TX_DATA (HDMI_CEC_TX_DATA14) 8 R/W 00h
1592
33.5.316/
12_7D1F CEC_TX_DATA (HDMI_CEC_TX_DATA15) 8 R/W 00h
1592
33.5.317/
12_7D20 CEC_RX_DATA (HDMI_CEC_RX_DATA0) 8 R 00h
1592
33.5.317/
1592
33.5.317/
1592
33.5.317/
1592
33.5.317/
1592
33.5.317/
1592
33.5.317/
1592
33.5.317/
1592


Absolute
Width Section/
(in bits) page
(hex)
33.5.317/
1592
33.5.317/
1592
33.5.317/
12_7D2A CEC_RX_DATA (HDMI_CEC_RX_DATA10) 8 R 00h
1592
33.5.317/
12_7D2B CEC_RX_DATA (HDMI_CEC_RX_DATA11) 8 R 00h
1592
33.5.317/
12_7D2C CEC_RX_DATA (HDMI_CEC_RX_DATA12) 8 R 00h
1592
33.5.317/
12_7D2D CEC_RX_DATA (HDMI_CEC_RX_DATA13) 8 R 00h
1592
33.5.317/
12_7D2E CEC_RX_DATA (HDMI_CEC_RX_DATA14) 8 R 00h
1592
33.5.317/
12_7D2F CEC_RX_DATA (HDMI_CEC_RX_DATA15) 8 R 00h
1592
33.5.318/
12_7D30 CEC_LOCK (HDMI_CEC_LOCK) 8 R/W 00h
1593
33.5.319/
12_7D31 CEC_WKUPCTRL (HDMI_CEC_WKUPCTRL) 8 R/W FFh
1593
33.5.320/
12_7E00 I2CM_SLAVE (HDMI_I2CM_SLAVE) 8 R/W 00h
1594
33.5.321/
12_7E01 I2CM_ADDRESS (HDMI_I2CM_ADDRESS) 8 R/W 00h
1595
33.5.322/
12_7E02 I2CM_DATAO (HDMI_I2CM_DATAO) 8 R/W 00h
1595
33.5.323/
12_7E03 I2CM_DATAI (HDMI_I2CM_DATAI) 8 R 00h
1596
33.5.324/
12_7E04 I2CM_OPERATION (HDMI_I2CM_OPERATION) 8 W 00h
1596
33.5.325/
12_7E05 I2CM_INT (HDMI_I2CM_INT) 8 R/W 08h
1597
33.5.326/
12_7E06 I2CM_CTLINT (HDMI_I2CM_CTLINT) 8 R/W 88h
1598
33.5.327/
12_7E07 I2CM_DIV (HDMI_I2CM_DIV) 8 R/W 0Bh
1598
33.5.328/
12_7E08 I2CM_SEGADDR (HDMI_I2CM_SEGADDR) 8 R/W 00h
1599
33.5.329/
12_7E09 I2CM_SOFTRSTZ (HDMI_I2CM_SOFTRSTZ) 8 R/W 01h
1600
33.5.330/
12_7E0A I2CM_SEGPTR (HDMI_I2CM_SEGPTR) 8 R/W 00h
1600
I2CM_SS_SCL_HCNT_1_ADDR 33.5.331/
12_7E0B 8 R/W 00h
(HDMI_I2CM_SS_SCL_HCNT_1_ADDR) 1601


Absolute
Width Section/
(in bits) page
(hex)
I2CM_SS_SCL_HCNT_0_ADDR 33.5.332/
12_7E0C 8 R/W 6Ch
(HDMI_I2CM_SS_SCL_HCNT_0_ADDR) 1601
I2CM_SS_SCL_LCNT_1_ADDR 33.5.333/
12_7E0D 8 R/W 00h
(HDMI_I2CM_SS_SCL_LCNT_1_ADDR) 1602
I2CM_SS_SCL_LCNT_0_ADDR 33.5.334/
12_7E0E 8 R/W 7Fh
(HDMI_I2CM_SS_SCL_LCNT_0_ADDR) 1602
I2CM_FS_SCL_HCNT_1_ADDR 33.5.335/
12_7E0F 8 R/W 00h
(HDMI_I2CM_FS_SCL_HCNT_1_ADDR) 1603
I2CM_FS_SCL_HCNT_0_ADDR 33.5.336/
12_7E10 8 R/W 11h
(HDMI_I2CM_FS_SCL_HCNT_0_ADDR) 1603
I2CM_FS_SCL_LCNT_1_ADDR 33.5.337/
12_7E11 8 R/W 00h
(HDMI_I2CM_FS_SCL_LCNT_1_ADDR) 1604
I2CM_FS_SCL_LCNT_0_ADDR 33.5.338/
12_7E12 8 R/W 24h
(HDMI_I2CM_FS_SCL_LCNT_0_ADDR) 1604
33.5.339/
12_7F00 BASE_POINTER_ADDR (HDMI_BASE_POINTER_ADDR) 8 R/W 00h
1605
33.5.1 Design Identification Register (HDMI_DESIGN_ID)

The following are the registers used to identify the HDMI TX controller.
• Name: Design Identification Register
• Address Offset: 0x0000
• Size: 8 bits
• Value after Reset: Implementation Dependent
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read DESIGN_ID
Write
Reset 0 0 0 0 0 0 0 0
HDMI_DESIGN_ID field descriptions

Field Description
DESIGN_ID This is a 1 byte design ID code fixed by NXP that Identifies the main revision of the HDMI TX controller.
For example, HDMI TX 1.30a, DESIGN_ID = 11h; REVISION_ID = 0Ah

33.5.2 Revision Identification Register (HDMI_REVISION_ID)
• Name: Revision Identification Register

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read REVISION_ID
Write
Reset 0 0 0 0 0 0 0 0
HDMI_REVISION_ID field descriptions

Field Description
REVISION_ID This is a one byte revision ID code fixed by NXP that Identifies the main revision of the HDMI TX
controller. For example, HDMI TX 1.30a, DESIGN_ID = 12h; REVISION_ID = 0Ah
33.5.3 Product Identification Register 0 (HDMI_PRODUCT_ID0)
• Name: Product Identification Register 0

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read PRODUCT_ID0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PRODUCT_ID0 field descriptions

Field Description
PRODUCT_ID0 This one byte fixed code identifies the NXP product line ("A0h" for HDMI TX products).

33.5.4 Product Identification Register 1 (HDMI_PRODUCT_ID1)
• Name: Product Identification Register 1

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read PRODUCT_ID1
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PRODUCT_ID1 field descriptions

Field Description
PRODUCT_ID1 This one byte fixed code identifies the NXP product line according to:
01h HDMI TX Controller
C1h HDMI TX Controller with HDCP encryption engine
33.5.5 Configuration Identification Register 0

(HDMI_CONFIG0_ID)
• Name: Configuration Identification Register 0

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read prepen audhbr audspdif audi2s hdmi14 csc cec hdcp
Write
Reset 0 0 0 0 0 0 0 0

HDMI_CONFIG0_ID field descriptions

Field Description
7 Indicates if it is possible to use internal pixel repetition
prepen
6 Indicates if HBR interface is present
audhbr
5 Indicates if SPDIF interface is present
audspdif
4 Indicates if I2S interface is present
audi2s
3 Indicates if HDMI 1.4 features are present
hdmi14
2 Indicates if Color Space Conversion block is present
csc
1 Indicates if CEC is present
cec
0 Indicates if HDCP is present
hdcp

(HDMI_CONFIG1_ID)

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read confsfrdir confi2c confocp confapb confahb

Reserved
Write
Reset 0 0 0 0 0 0 0 0

Field Description
-
4 Indicates that configuration interface is SFR interface
confsfrdir
3 Indicates that configuration interface is I2C interface
confi2c

HDMI_CONFIG1_ID field descriptions (continued)

Field Description
2 Indicates that configuration interface is OCP interface
confocp
1 Indicates that configuration interface is APB interface
confapb
0 Indicates that configuration interface is AHB interface
confahb

(HDMI_CONFIG2_ID)

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read phytype
Write
Reset 0 0 0 0 0 0 0 0

Field Description
phytype Indicates the type of PHY interface selected:
00h Legacy PHY (HDMI TX PHY)
F2h PHY_Gen2 (HDMI 3D TX PHY)
E2h PHY_Gen2 (HDMI 3D TX PHY) + HEAC PHY


(HDMI_CONFIG3_ID)

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read confgpaud
Reserved
Write
Reset 0 0 0 0 0 0 0 0

Field Description
-
0 Indicates that configuration interface is Generic Parallel Audio (GPAUD) interface
confgpaud
33.5.9 Frame Composer Interrupt Status Register 0

(HDMI_IH_FC_STAT0)
This section describes clear on write (1 to corresponding bit) status registers, which
contain the following active-high, sticky bit interrupts.
HDMI TX introduces a new set of sticky bit mute control registers
(IH_MUTE_FC_STAT0 to IH_MUTE_AHBDMAAUD_STAT0) that correspond to the
interrupt registers. You can ignore a sticky bit interrupt by setting the corresponding mute
control register bit to 1. This puts the global interrupt line on a higher priority than the
sticky bit interrupt.
• Size: 8 bits
• Value after Reset: 0x00
• Access: Read/Clear on Write

Bit 7 6 5 4 3 2 1 0
Read AUDI ACP HBR DST OBA AUDS ACR NULL
Write w1c w1c w1c w1c w1c w1c w1c w1c

Reset 0 0 0 0 0 0 0 0
HDMI_IH_FC_STAT0 field descriptions

Field Description
7 Active after successful transmission of an Audio InfoFrame packet.
AUDI
6 Active after successful transmission of an Audio Content Protection packet.
ACP
5 Active after successful transmission of an Audio HBR packet.
HBR
4 Reserved
DST
3 Reserved
OBA
2 Active after successful transmission of an Audio Sample packet. Due to high number of audio sample
AUDS packets transmitted, this interrupt is by default masked at frame composer.
1 Active after successful transmission of an Audio Clock Regeneration (N/CTS transmission) packet.
ACR
0 Active after successful transmission of an Null packet. Due to high number of audio sample packets
NULL transmitted, this interrupt is by default masked at frame composer.

(HDMI_IH_FC_STAT1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read GMD ISCR1 ISCR2 VSD SPD MPEG AVI GCP
Write w1c w1c w1c w1c w1c w1c w1c w1c

Reset 0 0 0 0 0 0 0 0


Field Description
7 Active after successful transmission of an Gamut metadata packet.
GMD
6 Active after successful transmission of an International Standard Recording Code 1 packet.
ISCR1
ISCR2
4 Active after successful transmission of an Vendor Specific Data infoFrame packet.
VSD
3 Active after successful transmission of an Source Product Descriptor infoFrame packet.
SPD
2 Reserved
MPEG
1 Active after successful transmission of an AVI infoFrame packet.
AVI
0 Active after successful transmission of an General Control Packet.
GCP

(HDMI_IH_FC_STAT2)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
LowPriority_ HighPriority
Read
Reserved overflow _overflow
Write w1c w1c
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
1 Frame Composer low priority packet queue descriptor overflow indication.
LowPriority_
overflow

HDMI_IH_FC_STAT2 field descriptions (continued)

Field Description
0 Frame Composer high priority packet queue descriptor overflow indication.
HighPriority_
overflow
33.5.12 Audio Sampler Interrupt Status Register

(HDMI_IH_AS_STAT0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Aud_fifo_
Aud_fifo_ Aud_fifo_
Read underflow_
Reserved underflow overflow
thr
Write w1c w1c w1c
Reset 0 0 0 0 0 0 0 0
HDMI_IH_AS_STAT0 field descriptions

Field Description
- Reserved
2 Audio Sampler audio FIFO empty threshold (four samples) indication. Only valid in HBR audio.
Aud_fifo_
underflow_thr
1 Audio Sampler audio FIFO empty indication.
Aud_fifo_
underflow
0 Audio Sampler audio FIFO full indication.
Aud_fifo_
overflow

33.5.13 PHY Interface Interrupt Status Register

(HDMI_IH_PHY_STAT0)

• Size: 8 bits
• Access: Clear on Write/Read
Bit 7 6 5 4
Read RX_SENSE3 RX_SENSE2

Reserved
Write w1c w1c
Reset 0 0 0 0
Bit 3 2 1 0
Read RX_SENSE1 RX_SENSE0 TX_PHY_LOCK HDP
Write w1c w1c w1c w1c

Reset 0 0 0 0
HDMI_IH_PHY_STAT0 field descriptions

Field Description
- Reserved
5 TX PHY RX_SENSE indication for driver 3. You may need to mask or change polarity of this interrupt after
RX_SENSE3 it has become active.
1 TX PHY PLL lock indication. Please refer to PHY datasheet for more information. You may need to mask
TX_PHY_LOCK or change polarity of this interrupt after it has become active.
0 HDMI Hot Plug Detect indication. You may need to mask or change polarity of this interrupt after it has
HDP become active.

33.5.14 E-DDC I2C Master Interrupt Status Register

(HDMI_IH_I2CM_STAT0)

• Size: 8 bits
• Access: Clear on Write/Read
Bit 7 6 5 4
Read
Reserved
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read I2Cmasterdone I2CMASTER_ERROR

Reserved
Write w1c w1c
Reset 0 0 0 0
HDMI_IH_I2CM_STAT0 field descriptions

Field Description
- Reserved
1 I2C Master done indication
I2Cmasterdone
0 I2C Master error indication
I2CMASTER_
ERROR

33.5.15 CEC Interrupt Status Register (HDMI_IH_CEC_STAT0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
ERROR_ ERROR_
Read WAKEUP ARB_LOST NACK EOM DONE
Reserved FOLLOW INITIATOR
Write w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0
HDMI_IH_CEC_STAT0 field descriptions

Field Description
- Reserved
6 CEC Wake-up indication
WAKEUP
5 CEC Error_follow indication
ERROR_
FOLLOW
4 CEC Error_follow indication
ERROR_
INITIATOR
3 CEC Arb_Lost indication
ARB_LOST
2 CEC Nack indication
NACK
1 CEC End of Message Indication
EOM
0 CEC Done Indication
DONE

33.5.16 Video Packetizer Interrupt Status Register

(HDMI_IH_VP_STAT0)

• Size: 8 bits
Bit 7 6 5 4
Read fifofullrepet fifoemptyrepet fifofullpp fifoemptypp

Reset 0 0 0 0
Bit 3 2 1 0
Read fifofullremap fifoemptyremap fifofullbyp fifoemptybyp

Reset 0 0 0 0
HDMI_IH_VP_STAT0 field descriptions

Field Description
7 Video packetizer pixel repeater FIFO full interrupt
fifofullrepet
6 Video packetizer pixel repeater FIFO empty interrupt
fifoemptyrepet
5 Video packetizer pixel packing FIFO full interrupt
fifofullpp
4 Video packetizer pixel packing FIFO empty interrupt
fifoemptypp
3 Video packetizer pixel YCC 422 re-mapper FIFO full interrupt
fifofullremap
2 Video packetizer pixel YCC 422 re-mapper FIFO empty interrupt
fifoemptyremap
1 Video packetizer 8-bit bypass fifo full interrupt
fifofullbyp
0 Video packetizer 8-bit bypass fifo empty interrupt
fifoemptybyp

33.5.17 PHY GEN2 I2C Master Interrupt Status Register

(HDMI_IH_I2CMPHY_STAT0)
This clear on write (1 to corresponding bit) register contains the following active high
sticky bit interrupts. That I2C Master PHY is the I2C Master block used to access the
PHY I2C Slave.
• Size: 8 bits
Bit 7 6 5 4
Read
Reserved
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read i2cmphydone i2cmphyerror

Reserved
Write w1c w1c
Reset 0 0 0 0
HDMI_IH_I2CMPHY_STAT0 field descriptions

Field Description
- Reserved
1 I2C Master PHY done indication
i2cmphydone
0 I2C Master PHY error indication
i2cmphyerror
33.5.18 AHB Audio DMA Interrupt Status Register

(HDMI_IH_AHBDMAAUD_STAT0)
Address Offset: 0x0109
Size: 8 bits
Value after Reset: 0x00
Access: Read/Clear on Write

Bit 7 6 5 4
ahbdmaaud_
Read ahbdmaaud_interror
Reserved intlostownership
Write w1c w1c
Reset 0 0 0 0
Bit 3 2 1 0
ahbdmaaud_
Read ahbdmaaud_intretrysplit ahbdmaaud_intdone ahbdmaaud_intbufffull
intbuffempty
Reset 0 0 0 0
HDMI_IH_AHBDMAAUD_STAT0 field descriptions

Field Description
- Reserved
5 AHB audio DMA error interrupt
ahbdmaaud_interror
4 AHB audio DMA lost ownership interrupt
ahbdmaaud_
intlostownership
3 AHB audio DMA RETRY/SPLIT interrupt
ahbdmaaud_
intretrysplit
2 AHB audio DMA done interrupt
ahbdmaaud_intdone
1 AHB audio DMA Buffer full interrupt
ahbdmaaud_
intbufffull
0 AHB audio DMA Buffer empty interrupt
ahbdmaaud_
intbuffempty

33.5.19 Frame Composer Interrupt Mute Control Register 0

(HDMI_IH_MUTE_FC_STAT0)

• Size: 8 bits
• Access: Read/Write
Bit 7 6 5 4 3 2 1 0
Read
AUDI ACP HBR DST OBA AUDS ACR NULL
Write
Reset 0 0 0 0 0 0 0 0
HDMI_IH_MUTE_FC_STAT0 field descriptions

Field Description
7 When set to 1, mutes IH_ FC_STAT0[7]
AUDI
ACP
HBR
DST
OBA
AUDS
ACR
NULL



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
GMD ISCR1 ISCR2 VSD SPD MPEG AVI GCP
Write
Reset 0 0 0 0 0 0 0 0

Field Description
GMD
ISCR1
ISCR2
VSD
SPD
MPEG
AVI
GCP



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read LowPriority_ HighPriority
Reserved
Write overflow _overflow
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
LowPriority_
overflow
HighPriority_
overflow
33.5.22 Audio Sampler Interrupt Mute Control Register 0

(HDMI_IH_MUTE_AS_STAT0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Aud_fifo_
Aud_fifo_ Aud_fifo_
Reserved underflow_
Write underflow overflow
thr
Reset 0 0 0 0 0 0 0 0

HDMI_IH_MUTE_AS_STAT0 field descriptions

Field Description
- Reserved
2 When set to 1, mutes IH_ AS_STAT0[2]
Aud_fifo_
underflow_thr
Aud_fifo_
underflow
Aud_fifo_
overflow
33.5.23 PHY Interface Interrupt Mute Control Register

(HDMI_IH_MUTE_PHY_STAT0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read RX_ RX_ RX_ RX_ TX_PHY_
Reserved HDP
Write SENSE3 SENSE2 SENSE1 SENSE0 LOCK
Reset 0 0 0 0 0 0 0 0
HDMI_IH_MUTE_PHY_STAT0 field descriptions

Field Description
- Reserved
5 When set to 1, mutes IH_ PHY_STAT0[5]
RX_SENSE3
RX_SENSE2
RX_SENSE1
RX_SENSE0
TX_PHY_LOCK
HDP

33.5.24 E-DDC I2C Master Interrupt Mute Control Register

(HDMI_IH_MUTE_I2CM_STAT0)

• Size: 8 bits
Bit 7 6 5 4
Read
Reserved
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read Reserved I2Cmasterdone I2CMASTER_ERROR
Write
Reset 0 0 0 0
HDMI_IH_MUTE_I2CM_STAT0 field descriptions

Field Description
- Reserved
1 When set to 1, mutes IH_ I2CM_STAT0[1]
I2Cmasterdone
0 When set to 1, mutes IH_ I2CM_STAT0[0]
I2CMASTER_
ERROR
33.5.25 CEC Interrupt Mute Control Register

(HDMI_IH_MUTE_CEC_STAT0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read ERROR_ ERROR_
Reserved WAKEUP ARB_LOST NACK EOM DONE
Write FOLLOW INITIATOR
Reset 0 0 0 0 0 0 0 0

HDMI_IH_MUTE_CEC_STAT0 field descriptions

Field Description
- Reserved
6 When set to 1, mutes IH_ CEC_STAT0[6]
WAKEUP
ERROR_
FOLLOW
ERROR_
INITIATOR
ARB_LOST
NACK
EOM
DONE
33.5.26 Video Packetizer Interrupt Mute Control Register

(HDMI_IH_MUTE_VP_STAT0)

• Size: 8 bits
Bit 7 6 5 4
Read fifofullrepet fifoemptyrepet fifofullpp fifoemptypp
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read fifofullremap fifoemptyremap fifofullbyp fifoemptybyp
Write
Reset 0 0 0 0
HDMI_IH_MUTE_VP_STAT0 field descriptions

Field Description
7 When set to 1, mutes IH_ VP_STAT0[7]
fifofullrepet

HDMI_IH_MUTE_VP_STAT0 field descriptions (continued)

Field Description
fifoemptyrepet
fifofullpp
fifoemptypp
fifofullremap
fifoemptyremap
fifofullbyp
fifoemptybyp
33.5.27 PHY GEN 2 I2C Master Interrupt Mute Control Register

(HDMI_IH_MUTE_I2CMPHY_STAT0)

• Size: 8 bits
Bit 7 6 5 4
Read Reserved
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read Reserved i2cmphydone i2cmphyerror
Write
Reset 0 0 0 0
HDMI_IH_MUTE_I2CMPHY_STAT0 field descriptions

Field Description
- Reserved
1 When set to 1, mutes IH_ I2CMPHY_STAT0[1]
i2cmphydone
0 When set to 1, mutes IH_ I2CMPHY_STAT0[0]
i2cmphyerror

33.5.28 AHB Audio DMA Interrupt Mute Control Register

(HDMI_IH_MUTE_AHBDMAAUD_STAT0)

• Size: 8 bits
Bit 7 6 5 4
Read ahbdmaaud_
Reserved ahbdmaaud_interror
Write intlostownership
Reset 0 0 0 0
Bit 3 2 1 0
Read ahbdmaaud_
Write ahbdmaaud_intretrysplit ahbdmaaud_intdone ahbdmaaud_intbufffull
intbuffempty
Reset 0 0 0 0
HDMI_IH_MUTE_AHBDMAAUD_STAT0 field descriptions

Field Description
- Reserved
5 When set to 1, mutes IH_AHBDMAAUD_STAT0[5]
ahbdmaaud_interror
ahbdmaaud_
intlostownership
ahbdmaaud_
intretrysplit
ahbdmaaud_intdone
ahbdmaaud_
intbufffull
ahbdmaaud_
intbuffempty

33.5.29 Global Interrupt Mute Control Register (HDMI_IH_MUTE)
• Address Offset: 0x01FF

• Size: 8 bits
Address: 12_0000h base + 1FFh offset = 12_01FFh
Bit 7 6 5 4 3 2 1 0
Read mute_
mute_all_
Reserved wakeup_
Write interrupt
interrupt
Reset 0 0 0 0 0 0 1 1
HDMI_IH_MUTE field descriptions

Field Description
-
1 When set to 1, mutes the wake-up interrupt line.
mute_wakeup_
The sticky bit interrupt continues with its state; only the wake up interrupt line is muted.
interrupt
0 When set to 1, mutes the main interrupt line (where all interrupts are ORed).
mute_all_
The sticky bit interrupts continue with their state; only the main interrupt line will be muted.
interrupt
33.5.30 Video Input Mapping and Internal Data Enable

Configuration Register (HDMI_TX_INVID0)
This registers contains the input video mapping code as defined in Table 2-1.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read internal_de_
Reserved video_mapping
Write generator
Reset 0 0 0 0 0 0 0 1

HDMI_TX_INVID0 field descriptions

Field Description
7 Internal data enable (DE) generator enable. If data enable is not available for the input video the user may
internal_de_ set this bit to one to activate the internal data enable generator.
generator
NOTE: This feature only works for input video modes that have native repetition (such as, all CEA
videos). No desired pixel repetition can be used with this feature because these configurations
only affect the Frame Composer and not this block.
- Reserved
video_mapping video_mapping
33.5.31 Video Input Stuffing Enable Register

(HDMI_TX_INSTUFFING)
This register enables the stuffing mechanism of the Video Sampler module in order to
correctly perform Color Space Conversion of the ITU.601 standard YCC video. In this
case, when "de" is low, the output video components gydata[15:0], rcrdata[15:0], and
bcbdata[15:0] can be configured.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read BCBDATA_ RCRDATA_ GYDATA_
Reserved
Write STUFFING STUFFING STUFFING
Reset 0 0 0 0 0 0 0 0
HDMI_TX_INSTUFFING field descriptions

Field Description
- Reserved
2 BCBDATA stuffing bit
BCBDATA_
STUFFING 0 When the dataen signal is low, the value in the bcbdata[15:0] output is the one sampled from the
corresponding input data.
1 When the dataen signal is low, the value in the bcbdata[15:0] output is given by the values in register
TX_BCBDTA0 and TX_BCBDATA1.
1 RCRDATA stuffing bit
RCRDATA_
STUFFING

HDMI_TX_INSTUFFING field descriptions (continued)

Field Description
0 When the dataen signal is low, the value in the rcrdata[15:0] output is the one sampled from the
1 When the dataen signal is low, the value in the rcrdata[15:0] output is given by the values in
TX_RCRDTA0 and TX_RCRDATA1 registers.
0 GYDATA stuffing bit
GYDATA_
STUFFING 0 when the dataen signal is low, the value in the gydata[15:0] output is the one sampled from the
1 When the dataen signal is low, the value in the gydata[15:0] output is given by the values in
TX_GYDTA0 and TX_GYDATA1 registers.
33.5.32 Video Input GY Data Channel Stuffing Register 0

(HDMI_TX_GYDATA0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read gydata
Write
Reset 0 0 0 0 0 0 0 0
HDMI_TX_GYDATA0 field descriptions

Field Description
gydata gydata[7:0].This register defines the value of gydata[7:0] when TX_INSTUFFING[0] (gydata_stuffing) is
set to 1b.

33.5.33 Video Input GY Data Channel Stuffing Register 1

(HDMI_TX_GYDATA1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
gydata
Write
Reset 0 0 0 0 0 0 0 0
HDMI_TX_GYDATA1 field descriptions

Field Description
gydata gydata[15:8].This register defines the value of gydata[15:8] when TX_INSTUFFING[0] (gydata_stuffing) is
set to 1b.
33.5.34 Video Input RCR Data Channel Stuffing Register 0

(HDMI_TX_RCRDATA0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read rcrdata
Write
Reset 0 0 0 0 0 0 0 0
HDMI_TX_RCRDATA0 field descriptions

Field Description
rcrdata rcrdata[7:0]. This register defines the value of rcrydata[7:0] when TX_INSTUFFING[1] (rcrdata_stuffing) is
set to 1b.

33.5.35 Video Input RCR Data Channel Stuffing Register 1

(HDMI_TX_RCRDATA1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
rcrdata
Write
Reset 0 0 0 0 0 0 0 0
HDMI_TX_RCRDATA1 field descriptions

Field Description
rcrdata rcrdata[15:8]. This register defines the value of rcrydata[15:8] when TX_INSTUFFING[1] (rcrdata_stuffing)
is set to 1b.
33.5.36 Video Input RCB Data Channel Stuffing Register 0

(HDMI_TX_BCBDATA0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read bcbdata
Write
Reset 0 0 0 0 0 0 0 0
HDMI_TX_BCBDATA0 field descriptions

Field Description
bcbdata bcbdata[7:0]. This register defines the value of bcbdata[7:0] when TX_INSTUFFING[2] (bcbdata_stuffing)
is set to 1b.

33.5.37 Video Input RCB Data Channel Stuffing Register 1

(HDMI_TX_BCBDATA1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
bcbdata
Write
Reset 0 0 0 0 0 0 0 0
HDMI_TX_BCBDATA1 field descriptions

Field Description
bcbdata bcbdata[15:8]. This register defines the value of bcbdata[15:8] when TX_INSTUFFING[2]
(bcbdata_stuffing) is set to 1b.
33.5.38 Video Packetizer Packing Phase Status Register

(HDMI_VP_STATUS)

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read packing_phase
Reserved
Write
Reset 0 0 0 0 0 0 0 0
HDMI_VP_STATUS field descriptions

Field Description
- Reserved

HDMI_VP_STATUS field descriptions (continued)

Field Description
packing_phase Read only register that holds the "packing phase" output by the Video packetizer block. For more
information about "packing" video data, refer to the HDMI1.4a specification. The register is updated at
tmds clock rate.
33.5.39 Video Packetizer Pixel Repetition and Color Depth

Register (HDMI_VP_PR_CD)
This register configures the Color Depth of the input video and Pixel repetition to apply
to video.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read color_depth[3:0] desired_pr_factor[3:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_VP_PR_CD field descriptions

Field Description
7–4 Color depth configuration:
color_depth[3:0]
other Reserved. Not used.
0000 24 bits per pixel video (8 bit per component). 8-bit packing mode.
desired_pr_ Desired pixel repetition factor configuration. The configured value sets H13T PHY PLL to multiply pixel
factor[3:0] clock by the factor in order to obtain the desired repetition clock. For the CEA modes some are already
defined with pixel repetition in the input video. So for CEA modes this shall be always 0. Shall only be
used if the user wants to do pixel repetition using H13TCTRL core.
other Reserved. Not used.
0000 No pixel repetition (pixel sent only once)

0001 Pixel sent 2 times (pixel repeated once)
0010 Pixel sent 3 times

HDMI_VP_PR_CD field descriptions (continued)

Field Description
33.5.40 Video Packetizer Stuffing and Default Packing Phase

Register (HDMI_VP_STUFF)
This register controls the Pixel repetition, pixel packing and YCC422 stuffing.
• Size: 8 bits
Bit 7 6 5 4
Read Reserved idefault_phase ifix_pp_to_last
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read icx_goto_p0_st ycc422_stuffing pp_stuffing pr_stuffing
Write
Reset 0 0 0 0
HDMI_VP_STUFF field descriptions

Field Description
- Reserved
5 Controls the default phase packing machine used according to: "If the transmitted video format has timing
idefault_phase such that the phase of the first pixel of every Video Data Period corresponds to pixel packing phase 0 (for
example, 10P0, 12P0, 16P0), the Source may set the Default_Phase bit in the GCP. The Sink may use
this bit to optimize it's filtering or handling of the PP field." (HDMI specification version 1.4a) This means
that for10 bit mode the Htotal must be dividable by 4 and for 12 bit mode the Htotal must be dividable by
2.
4 Reserved. Controls packing machine strategy.
ifix_pp_to_last
3 Reserved. Controls packing machine strategy.
icx_goto_p0_st
2 YCC 422 remap stuffing control. For horizontal blanking:
ycc422_stuffing
0 YCC 422 remap block in direct mode (input blanking data goes directly to output).
1 YCC 422 remap block in stuffing mode. When "de" goes to low the outputs are fixed to 0x00.

HDMI_VP_STUFF field descriptions (continued)

Field Description
1 Pixel packing stuffing control
pp_stuffing
0 Pixel packing block in direct mode (input blanking data goes directly to output).
1 Pixel packing block in stuffing mode. When "de_rep" goes to low the outputs are fixed to 0x00.
0 Pixel repeater stuffing control
pr_stuffing
0 Pixel repeater block in direct mode (input blanking data goes directly to output).
1 Pixel repeater block in stuffing mode. When "de" goes to low the outputs are fixed to 0x00.
33.5.41 Video Packetizer YCC422 Remapping Register

(HDMI_VP_REMAP)
This register controls YCC422 remap of the Video Packetizer. For more information
about YCC422 remap refer to HDMI 1.4a specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved ycc422_size[1:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_VP_REMAP field descriptions

Field Description
- Reserved
ycc422_size[1:0] YCC 422 remap input video size:
00 YCC 422 16-bit input video (8 bits per component).

11 Reserved. Not used.

33.5.42 Video Packetizer Output, Bypass, and Enable

Configuration Register (HDMI_VP_CONF)
This register controls the Video Packetizer output selection, bypass select, YCC422
enable, Pixel repeater, and pixel packing enabling.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read BYPASS_
Reserved bypass_en pp_en pr_en ycc422_en output_selector[1:0]
Write SELECT
Reset 0 1 0 0 0 1 1 0
HDMI_VP_CONF field descriptions

Field Description
- Reserved
6 Bypass enable. Disabling forces bypass module to output always zeros.
bypass_en
5 Pixel packing enable. Disabling forces bypass module to output always zeros.
pp_en
4 Pixel repeater enable. Disabling forces bypass module to output always zeros.
pr_en
3 YCC 422 select enable. Disabling forces bypass module to output always zeros.
ycc422_en
2 Bypass select bit
BYPASS_
SELECT 0 Data from pixel repeater block.
1 Data from input of video packetizer block.
output_ Video packetizer output selection.
selector[1:0]
00 Data from pixel packing block.
01 Data from YCC 422 remap block.
10 Data from 8-bit bypass block.
11 Data from 8-bit bypass block.
33.5.43 VP_STAT (HDMI_VP_STAT)

This register contains the following active high FIFO status indications:


• Size: 8 bits
• Access: Read
Bit 7 6 5 4
Read ostfullrepet ostemptyrepet ostfullpp ostemptypp
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read ostfullremap ostemptyremap ostfullbyp ostemptybyp
Write
Reset 0 0 0 0
HDMI_VP_STAT field descriptions

Field Description
7 Video packetizer pixel repeater FIFO full status.
ostfullrepet
6 Video packetizer pixel repeater FIFO empty status.
ostemptyrepet
5 Video packetizer pixel packing FIFO full status.
ostfullpp
4 Video packetizer pixel packing FIFO empty status.
ostemptypp
3 Video packetizer pixel YCC 422 re-mapper FIFO full status.
ostfullremap
2 Video packetizer pixel YCC 422 re-mapper FIFO empty status.
ostemptyremap
1 Video packetizer 8-bit bypass FIFO full status.
ostfullbyp
0 Video packetizer 8-bit bypass FIFO empty status.
ostemptybyp
33.5.44 VP_INT (HDMI_VP_INT)

This register contains the interrupt indication of the VP_STAT status interrupts. Interrupt
generation is accomplished in the following way:
interrupt = (mask == 1'b0) && (polarity == status);

All this interrupts are forwarded to the Interrupt Handler sticky bit registers and after
ORed to a single main interrupt line to micro controller. Assertion of this interrupt
implies that data related with the corresponding packet has been sent through the HDMI
interface.
• Size: 8 bits
• Access: Read
Bit 7 6 5 4
Read ointfullrepet ointemptyrepet ointfullpp ointemptypp
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read ointfullremap ointemptyremap ointfullbyp ointemptybyp
Write
Reset 0 0 0 0
HDMI_VP_INT field descriptions

Field Description
7 Video packetizer pixel repeater FIFO full status
ointfullrepet
6 Video packetizer pixel repeater FIFO empty status
ointemptyrepet
5 Video packetizer pixel packing FIFO full status
ointfullpp
4 Video packetizer pixel packing FIFO empty status
ointemptypp
3 Video packetizer pixel YCC 422 re-mapper FIFO full status.
ointfullremap
2 Video packetizer pixel YCC 422 re-mapper FIFO empty status.
ointemptyremap
1 Video packetizer 8-bit bypass FIFO full status.
ointfullbyp
0 Video packetizer 8-bit bypass FIFO empty status.
ointemptybyp
33.5.45 Video Packetizer Interrupt Mask Register

(HDMI_VP_MASK)
Mask register for generation of VP_INT interrupts.


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read VPMASK7 VPMASK6 VPMASK5 VPMASK4 VPMASK3 VPMASK2 VPMASK1 VPMASK0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_VP_MASK field descriptions

Field Description
7 Mask bit for VP_INT[7] interrupt bit.
VPMASK7
VPMASK6
VPMASK5
VPMASK4
VPMASK3
VPMASK2
VPMASK1
VPMASK0
33.5.46 VP_POL (HDMI_VP_POL)

Polarity register for generation of VP_INT interrupts.
• Size: 8 bits
• Value after Reset: 0xFF
Bit 7 6 5 4 3 2 1 0
Read VPPOL7 VPPOL6 VPPOL5 VPPOL4 VPPOL3 VPPOL2 VPPOL1 VPPOL0
Write
Reset 1 1 1 1 1 1 1 1

HDMI_VP_POL field descriptions

Field Description
7 Polarity bit for VP_INT[7] interrupt bit.
VPPOL7
VPPOL6
VPPOL5
VPPOL4
VPPOL3
VPPOL2
VPPOL1
VPPOL0
33.5.47 Frame Composer Input Video Configuration and HDCP

Keepout Register (HDMI_FC_INVIDCONF)
This register configures the Interlaced/progressive, Vblank variation and polarity of all
video synchronism of the input video signal.
• Size: 8 bits
Bit 7 6 5 4
Read Reserved vsync_in_polarity hsync_in_polarity de_in_polarity
Write
Reset 0 1 1 1
Bit 3 2 1 0
Read DVI_mode Reserved r_v_blank_in_osc in_I_P
Write
Reset 0 0 0 0
HDMI_FC_INVIDCONF field descriptions

Field Description
- Reserved

HDMI_FC_INVIDCONF field descriptions (continued)

Field Description
6 Vsync input polarity
vsync_in_polarity
1 Active high
0 Active low
5 Hsync input polarity
hsync_in_polarity
1 Active high
0 Active low
4 Data enable input polarity
de_in_polarity
1 Active high
0 Active low
3 Active low
DVI_mode
0 DVI mode selected
1 HDMI mode selected
- Reserved
1 Used for CEA861-D modes with fractional Vblank (for example, modes 5, 6, 7, 10, 11, 20, 21, and 22. For
r_v_blank_in_osc more modes, refer to CEA861-D specification.
1 Active high
0 Input video mode:
in_I_P
1 Interlaced
0 Progressive
33.5.48 Frame Composer Input Video HActive Pixels Register 0

(HDMI_FC_INHACTIV0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read H_in_activ[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_INHACTIV0 field descriptions

Field Description
H_in_activ[7:0] Input video Horizontal active pixel region width. Number of Horizontal active pixels [0...8191].

33.5.49 Frame Composer Input Video HActive Pixels Register 1

(HDMI_FC_INHACTIV1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
Reserved H_in_activ[12:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_INHACTIV1 field descriptions

Field Description
- Reserved
H_in_activ[12:8] Input video Horizontal active pixel region width.
Dependencies:
Value after Reset: 0000b
• the higher bit of Horizontal active pixels; Number of Horizontal active pixels [0...8191].
33.5.50 Frame Composer Input Video HBlank Pixels Register 0

(HDMI_FC_INHBLANK0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read H_in_blank[7:0]
Write
Reset 0 0 0 0 0 0 0 0

HDMI_FC_INHBLANK0 field descriptions

Field Description
H_in_blank[7:0] Input video Horizontal blanking pixel region width. Number of Horizontal blanking pixels [0...4095].
33.5.51 Frame Composer Input Video HBlank Pixels Register 1

(HDMI_FC_INHBLANK1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved H_in_blank[12:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_INHBLANK1 field descriptions

Field Description
- Reserved
H_in_blank[12:8] Input video Horizontal blanking pixel region width.
Dependencies:
• the higher bits of Horizontal blanking pixels; Number of Horizontal blanking pixels [0...8191].

33.5.52 Frame Composer Input Video VActive Pixels Register 0

(HDMI_FC_INVACTIV0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
V_in_activ[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_INVACTIV0 field descriptions

Field Description
V_in_activ[7:0] Input video Vertical active pixel region width. Number of Vertical active lines [0...4095].
33.5.53 Frame Composer Input Video VActive Pixels Register 1

(HDMI_FC_INVACTIV1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved V_in_activ[12:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_INVACTIV1 field descriptions

Field Description
- Reserved
V_in_activ[12:8] Input video Vertical active pixel region width.
Dependencies:

HDMI_FC_INVACTIV1 field descriptions (continued)

Field Description
• the higher 5 bits of Vertical active line; Number of Vertical active lines [0...8191].
33.5.54 Frame Composer Input Video VBlank Pixels Register

(HDMI_FC_INVBLANK)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read V_in_blank[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_INVBLANK field descriptions

Field Description
V_in_blank[7:0] Input video Vertical blanking pixel region width. Number of Vertical blanking lines [0...255].
Value after Reset: 0x00
33.5.55 Frame Composer Input Video HSync Front Porch

Register 0 (HDMI_FC_HSYNCINDELAY0)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read H_in_delay[7:0]
Write
Reset 0 0 0 0 0 0 0 0

HDMI_FC_HSYNCINDELAY0 field descriptions

Field Description
H_in_delay[7:0] Input video Hsync active edge delay. Integer number of pixel clock cycles from "de" non active edge of the
last "de" valid period [0...4095].
33.5.56 Frame Composer Input Video HSync Front Porch

Register 1 (HDMI_FC_HSYNCINDELAY1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved H_in_delay[12:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_HSYNCINDELAY1 field descriptions

Field Description
- Reserved
H_in_delay[12:8] Input video Hsync active edge delay.
Dependencies:
• the higher 5 bits of delay; Integer number of pixel clock cycles from "de" non active edge of the last
"de" valid period [0...8191].

33.5.57 Frame Composer Input Video HSync Width Register 0

(HDMI_FC_HSYNCINWIDTH0)
• Address Offset: 0x100A

• Size: 8 bits
Address: 12_0000h base + 100Ah offset = 12_100Ah
Bit 7 6 5 4 3 2 1 0
Read
H_in_width[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_HSYNCINWIDTH0 field descriptions

Field Description
H_in_width[7:0] Input video Hsync active pulse width. Integer number of pixel clock cycles [0...511].
33.5.58 Frame Composer Input Video HSync Width Register 1

(HDMI_FC_HSYNCINWIDTH1)
• Address Offset: 0x100B

• Size: 8 bits
Address: 12_0000h base + 100Bh offset = 12_100Bh
Bit 7 6 5 4 3 2 1 0
Read Reserved H_in_width[9:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_HSYNCINWIDTH1 field descriptions

Field Description
- Reserved
H_in_width[9:8] Input video Hsync active pulse width.
Dependencies:
Value after Reset after Reset: 0b

HDMI_FC_HSYNCINWIDTH1 field descriptions (continued)

Field Description
• Integer number of pixel clock cycles [0...1024].
33.5.59 Frame Composer Input Video VSync Front Porch

Register (HDMI_FC_VSYNCINDELAY)
• Address Offset: 0x100C

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read V_in_delay[7..0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_VSYNCINDELAY field descriptions

Field Description
V_in_delay[7..0] Input video Vsync active edge delay. Integer number of Hsync pulses from "de" non active edge of the last
"de" valid period. [0...255].
33.5.60 Frame Composer Input Video VSync Width Register

(HDMI_FC_VSYNCINWIDTH)
• Address Offset: 0x100D

• Size: 8 bits
Address: 12_0000h base + 100Dh offset = 12_100Dh
Bit 7 6 5 4 3 2 1 0
Read Reserved V_in_width[5..0]
Write
Reset 0 0 0 0 0 0 0 0

HDMI_FC_VSYNCINWIDTH field descriptions

Field Description
- Reserved
V_in_width[5..0] Value after Reset: 000000b
Input video Vsync active pulse width: Integer number of pixel clock cycles [0...63].
33.5.61 Frame Composer Input Video Refresh Rate Register 0

(HDMI_FC_INFREQ0)
• Address Offset: 0x100E

• Size: 8 bits
Address: 12_0000h base + 100Eh offset = 12_100Eh
Bit 7 6 5 4 3 2 1 0
Read infreq[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_INFREQ0 field descriptions

Field Description
infreq[7:0] Video refresh rate in Hz*1E3 format. This registers are provided for debug and informative purposes. No
data is written to this registers by the H13TCTRL and the data here written by software is not used in any
way by the H13TCTRL.

(HDMI_FC_INFREQ1)
• Address Offset: 0x100F

• Size: 8 bits
Address: 12_0000h base + 100Fh offset = 12_100Fh
Bit 7 6 5 4 3 2 1 0
Read infreq[7:0]
Write
Reset 0 0 0 0 0 0 0 0


Field Description

(HDMI_FC_INFREQ2)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved infreq[19:16]
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved

33.5.64 Frame Composer Control Period Duration Register

(HDMI_FC_CTRLDUR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
ctrlperiodduration
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_CTRLDUR field descriptions

Field Description
ctrlperiodduration Configuration of the control period minimum duration (min. of 12 pixel clock cycles, refer to HDMI
1.4a specification). Integer number of pixel clocks cycles [0..255].
33.5.65 Frame Composer Extended Control Period Duration

Register (HDMI_FC_EXCTRLDUR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read exctrlperiodduration
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_EXCTRLDUR field descriptions

Field Description
exctrlperiodduration Configuration of the extended control period minimum duration (min. of 32 pixel clock cycles, see
HDMI 1.4a specification). Integer number of pixel clocks cycles [0..255].

33.5.66 Frame Composer Extended Control Period Maximum

Spacing Register (HDMI_FC_EXCTRLSPAC)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
exctrlperiodspacing
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_EXCTRLSPAC field descriptions

Field Description
exctrlperiodspacing Configuration of the maximum spacing between consecutive extended control periods (max of
50msec, see HDMI 1.4a specification):
generated spacing = (1/freq tmds clock)*256*256*extctrlperiodspacing
33.5.67 Frame Composer Channel 0 Non-Preamble Data Register

(HDMI_FC_CH0PREAM)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read ch0_preamble_filter
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_CH0PREAM field descriptions

Field Description
ch0_preamble_ When in control mode, configures 8-bits that are going to fill the channel 0 data lines not used to transmit
filter the preamble (for more clarifications refer to HDMI 1.4a specification).


(HDMI_FC_CH1PREAM)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
Reserved ch1_preamble_filter
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
filter the preamble (for more clarifications refer to HDMI 1.4a specification).

(HDMI_FC_CH2PREAM)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved ch2_preamble_filter
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved

HDMI_FC_CH2PREAM field descriptions (continued)

Field Description
filter the preamble (for more clarifications, see HDMI 1.4a specification).
33.5.70 Frame Composer AVI Configuration Register 3

(HDMI_FC_AVICONF3)
• Size: 8 bits
configuration of Quantization range and IT content type.
Bit 7 6 5 4 3 2 1 0
Read Reserved YQ1_YQ0_YCC CN1_CN0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVICONF3 field descriptions

Field Description
- Reserved
3–2 Quantization range according to CEA specification.
YQ1_YQ0_YCC
CN1_CN0 IT content type according to CEA specification
33.5.71 Frame Composer GCP Packet Configuration Register

(HDMI_FC_GCP)
Configures the General Control Packet A/V mute indicators and the default phase.
• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Read default_ clear_
Reserved set_avmute
Write phase avmute
Reset 0 0 0 0 0 0 0 0
HDMI_FC_GCP field descriptions

Field Description
- Reserved
2 Value of "default_phase" in the GCP packet. This data should be equal to the default phase used at Video
default_phase packetizer packing machine.
1 Value of "set_avmute" in the GCP packet.
set_avmute
0 Value of "clear_avmute" in the GCP packet.
clear_avmute
33.5.72 Frame Composer AVI Packet Configuration Register 0

(HDMI_FC_AVICONF0)
Configures the following contents of the AVI infoFrame:
• RGB/YCC indication
• Bar information
• Scan information
• Active format present
• Progressive/Interlaced indicator
• Active aspect ratio
• Picture aspect ratio
• Colorimetry
• IT content
• Extended colorimetry
• Quantization range
• Non-uniform picture scaling
For more information, refer to HDMI 1.4a and CEA - 861D specifications.
• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Read FC_
FC_
AVICONF0_ FC_AVICONF0_RGB_
Write AVICONF0_ ACTIVE_ FC_AVICONF0_SCAN FC_AVICONF0_BAR
YCC
MISC
FORMAT
Reset 0 0 0 0 0 0 0 0

Field Description
7 Frame composer AVI packet configuration bit
FC_AVICONF0_
MISC
6 Active format present
FC_AVICONF0_
ACTIVE_
FORMAT
5–4 Scan information
FC_AVICONF0_
SCAN
3–2 Bar information
FC_AVICONF0_
BAR
FC_AVICONF0_ RGB/YCC indication
RGB_YCC
33.5.73 Frame Composer AVI Packet Configuration Register 1

(HDMI_FC_AVICONF1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_AVICONF1_
FC_AVICONF0_COLOR FC_AVICONF1_ACTIVE_AR
Write PICTURE_AR
Reset 0 0 0 0 0 0 0 0


Field Description
7–6 Colorimetry
FC_AVICONF0_
COLOR
5–4 Picture aspect ratio
FC_AVICONF1_
PICTURE_AR
FC_AVICONF1_ Active aspect ratio
ACTIVE_AR
33.5.74 FC_AVICONFFrame Composer AVI Packet Configuration

Register 2 (HDMI_FC_AVICONF2)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_
AVICONF2_ FC_AVICONF2_EXT_COLOR - FC_AVICONF2_SCALE
Write
IT
Reset 0 0 0 0 0 0 0 0

Field Description
7 IT content
FC_AVICONF2_
IT
6–4 Extended colorimetry
FC_AVICONF2_
EXT_COLOR
3–2 Quantization range
-
FC_AVICONF2_ Non-uniform picture scaling
SCALE

33.5.75 Frame Composer AVI Packet VIC Register

(HDMI_FC_AVIVID)
Configures the AVI infoFrame Video Identification code. For more information, refer to
the CEA-861-E specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_AVIVID
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVIVID field descriptions

Field Description
FC_AVIVID the AVI infoFrame Video Identification code.
33.5.76 Frame Composer AVI Packet End of Top Bar Register 0

(HDMI_FC_AVIETB0)
These registers define the AVI infoFrame End of Top Bar value. For more information,
refer to CEA-861-E specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVIETB0 field descriptions

Field Description
- Line number of end of top bar (lower 8 bits)

33.5.77 Frame Composer AVI Packet End of Top Bar Register 1

(HDMI_FC_AVIETB1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVIETB1 field descriptions

Field Description
- Line number of end of top bar (upper 8 bits)
33.5.78 Frame Composer AVI Packet Start of Bottom Bar

Register 0 (HDMI_FC_AVISBB0)
These registers define the AVI infoFrame Start of Bottom Bar value. For more
information, refer to CEA-861D specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_AVISBB0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVISBB0 field descriptions

Field Description
FC_AVISBB0 Line number of Start of Bottom Bar (lower 8 bits)

33.5.79 Frame Composer AVI Packet Start of Bottom Bar

Register 1 (HDMI_FC_AVISBB1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_AVISBB1
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVISBB1 field descriptions

Field Description
FC_AVISBB1 Line number of Start of Bottom Bar (upper 8 bits)
33.5.80 Frame Composer AVI Packet End of Left Bar Register 0

(HDMI_FC_AVIELB0)
These registers define the AVI infoFrame End of Left Bar value. For more information,
refer to CEA-861D specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_AVIELB0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVIELB0 field descriptions

Field Description
FC_AVIELB0 Pixel number of end of left Bar (lower 8 bits)

33.5.81 Frame Composer AVI Packet End of Left Bar Register 1

(HDMI_FC_AVIELB1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_AVIELB1
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVIELB1 field descriptions

Field Description
FC_AVIELB1 Pixel number of end of left Bar (lower 8 bits)
33.5.82 Frame Composer AVI Packet Start of Right Bar Register

0 (HDMI_FC_AVISRB0)
These registers define the AVI infoFrame Start of Right Bar value. For more information,
refer to CEA-861D specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_AVISRB0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVISRB0 field descriptions

Field Description
FC_AVISRB0 Pixel number of start of right Bar (lower 8 bits)

33.5.83 Frame Composer AVI Packet Start of Right Bar Register

1 (HDMI_FC_AVISRB1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_AVISRB1
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AVISRB1 field descriptions

Field Description
FC_AVISRB1 Pixel number of start of right Bar (upper 8 bits)
33.5.84 Frame Composer AUD Packet Configuration Register 0

(HDMI_FC_AUDICONF0)
These registers configure the following contents of the AUDIO infoFrame:
• Coding type
• Channel count
• Sampling frequency
• Sampling size
• Channel allocation
• Audio level shift value
• Down mix enable
For more information, refer to CEA-861D specification.
• Address Offset: 0x1025 to 0x1028
• Size: 8 bits
For the FC_AUDICONF0 register, bits [6:5] correspond to LFEPBL1, LFEPBL0 LFE
playback level as compared to the other channels (from HDMI 1.4a specification).

Bit 7 6 5 4 3 2 1 0
Read Reserved CC[2:0] CT[3:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AUDICONF0 field descriptions

Field Description
- Reserved
6–4 Channel count
CC[2:0]
CT[3:0] Coding Type

(HDMI_FC_AUDICONF1)
Bit 7 6 5 4 3 2 1 0
Read Reserved SS[1:0] Reserved SF[2:0]
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
5–4 Sampling size
SS[1:0]
- Reserved
SF[2:0] Sampling frequency

(HDMI_FC_AUDICONF2)
Bit 7 6 5 4 3 2 1 0
Read CA[7:0]
Write
Reset 0 0 0 0 0 0 0 0


Field Description
CA[7:0] Channel allocation

(HDMI_FC_AUDICONF3)
Bit 7 6 5 4 3 2 1 0
Read Reserved LFEPBL[1:0] DM_INH LSV[3:0]
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
6–5 LFE playback information
LFEPBL[1:0]
4 Down mix enable
DM_INH
LSV[3:0] Level shift value (for down mixing)
33.5.88 Frame Composer VSI Packet Data IEEE Register 0

(HDMI_FC_VSDIEEEID0)
These registers configure the Vendor Specific infoFrame IEEE registration identifier. For
more information, refer to CEA-861D specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

HDMI_FC_VSDIEEEID0 field descriptions

Field Description
- the Vendor Specific infoFrame IEEE registration identifier byte 0
33.5.89 Frame Composer VSI Packet Data Size Register

(HDMI_FC_VSDSIZE)
• Size: 8 bits
• Value after Reset: 0x1B
configuration of Packet size.
Bit 7 6 5 4 3 2 1 0
Read Reserved VSDSIZE
Write
Reset 0 0 0 1 1 0 1 1
HDMI_FC_VSDSIZE field descriptions

Field Description
- Reserved
VSDSIZE Packet size as described in HDMI Vendor Specific InfoFrame (from HDMI specification).

• Address Offset: 0x102a

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0


Field Description

• Address Offset: 0x102b

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_VSDPAYLOAD0)
These registers configure the Vendor Specific infoFrame 24 bytes specific payload. For
more information, refer to CEA-861D specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

HDMI_FC_VSDPAYLOAD0 field descriptions

Field Description
- the Vendor Specific infoFrame 24 bytes specific payload byte0


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description

• Address Offset: 0x103c

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Address Offset: 0x103d

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description

• Address Offset: 0x103e

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Address Offset: 0x103f

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read -
Write
Reset 0 0 0 0 0 0 0 0

Field Description



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
-
Write
Reset 0 0 0 0 0 0 0 0

Field Description
33.5.116 Frame Composer SPD Packet Data Vendor Name

Register 0 (HDMI_FC_SPDVENDORNAME0)
These registers configure the Source Product Descriptor infoFrame 8 bytes Vendor name.
• Address Offset: 0x104A to 0x1051
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read vendor_name
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_SPDVENDORNAME0 field descriptions

Field Description
vendor_name Vendor name

33.5.117 Frame Composer SPD Packet Data Product Name

Register 0 (HDMI_FC_SPDPRODUCTNAME0)
These registers configure the Source Product Descriptor infoFrame 16 bytes Product
name. For more information, refer to CEA-861D specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read product_name
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_SPDPRODUCTNAME0 field descriptions

Field Description
product_name Product name
33.5.118 Frame Composer SPD Packet Data Source Product

Descriptor Register (HDMI_FC_SPDDEVICEINF)
This register configures Source Product Descriptor infoFrame description device field.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read product_descriptor
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_SPDDEVICEINF field descriptions

Field Description
product_ Product descriptor
descriptor

33.5.119 Frame Composer Audio Sample Flat and Layout

Configuration Register (HDMI_FC_AUDSCONF)
Configures the Audio sample packet sample flat and layout configuration. For more
information, refer to HDMI 1.4a specification.
• Size: 8 bits
• AEccess: Read/Write
Bit 7 6 5 4 3 2 1 0
Read aud_
aud_packet_sampfit[3:0] Reserved packet_
Write
layout
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AUDSCONF field descriptions

Field Description
7–4 Set the audio packet sample flat value to be sent on the packet.
aud_packet_
sampfit[3:0]
- Reserved
0 Set the audio packet layout to be sent in the packet:
aud_packet_
layout 1 layout 1
0 layout 0
33.5.120 Frame Composer Audio Packet Sample Present Status

Register (HDMI_FC_AUDSSTAT)
Shows the data sample present indication of the last Audio sample packet sent by the
HDMI TX Controller. For more information, refer to HDMI 1.4a specification.
• Size: 8 bits
• Access: Read

Bit 7 6 5 4 3 2 1 0
Read packet_sampprs[3:0]
Reserved
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_AUDSSTAT field descriptions

Field Description
- Reserved
packet_ Shows the data sample present indication of the last Audio sample packet sent by the HDMI TX
sampprs[3:0] Controller. This register information is at tmds clock rate.
33.5.121 Frame Composer Number of High Priority Packets

Attended Configuration Register
(HDMI_FC_CTRLQHIGH)

• Size: 8 bits
• Value after Reset: 0x0F
Bit 7 6 5 4 3 2 1 0
Read Reserved onhighattended[4:0]
Write
Reset 0 0 0 0 1 1 1 1
HDMI_FC_CTRLQHIGH field descriptions

Field Description
- Reserved
onhighattended[4:0] Configures the number of high priority packets or audio sample packets consecutively attended
before checking low priority queue status.
Integer number [0..31]

33.5.122 Frame Composer Number of Low Priority Packets

Attended Configuration Register
(HDMI_FC_CTRLQLOW)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved onlowattended[4:0]
Write
Reset 0 0 0 0 0 0 1 1
HDMI_FC_CTRLQLOW field descriptions

Field Description
- Reserved
onlowattended[4:0] Configures the number of low priority packets or null packets consecutively attended before
checking high priority queue status or audio sample availability.
Integer number [0..31]
33.5.123 Frame Composer ACP Packet Type Configuration

Register 0 (HDMI_FC_ACP0)
Configures the following contents of the ACP packet. For more information, refer to the
HDMI 1.4 specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read acptype[7:0]
Write
Reset 0 0 0 0 0 0 0 0

HDMI_FC_ACP0 field descriptions

Field Description
acptype[7:0] Configures the ACP packet type.
33.5.124 Frame Composer ACP Packet Type Configuration

Register 1 (HDMI_FC_ACP1)
Configures the following contents of the Audio Content Packet (ACP) body:
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Audio_contentpacket
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_ACP1 field descriptions

Field Description
Audio_ Audio content packet
contentpacket
33.5.125 FC_ISCR1_Frame Composer Packet Status, Valid, and

Continue Configuration Register (HDMI_FC_ISCR1_0)
Configures the following contents of the ISRC1 packet:
• Size: 8 bits
For more information, see the HDMI 1.4 specification.
Bit 7 6 5 4 3 2 1 0
Read Reserved isrc_status[2:0] isrc_valid isrc_cont
Write
Reset 0 0 0 0 0 0 0 0

HDMI_FC_ISCR1_0 field descriptions

Field Description
- Reserved
4–2 Status of ISRC1.
isrc_status[2:0]
1 Valid of ISRC1.
isrc_valid
0 Indication of ISRC2.
isrc_cont
33.5.126 Frame Composer ISCR1 Packet Body Register 1

(HDMI_FC_ISCR1_1)
• ISRC1 packet body
• Address Offset: 0x10A2 to 0x1093
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read isrc1
Write
Reset 0 0 0 0 0 0 0 0

Field Description
isrc1 Configures the contents of the ISRC1 packet:
33.5.127 Frame Composer ISCR2 Packet Body Register 0

(HDMI_FC_ISCR2_0)
• ISRC2 packet body
• Address Offset: 0x10B2 to 0x10A3
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read isrc2
Write
Reset 0 0 0 0 0 0 0 0

Field Description
isrc2 Configures the contents of the ISRC1 packet:
33.5.128 Frame Composer Data Island Auto Packet Scheduling

Register 0 (HDMI_FC_DATAUTO0)
Configures the Frame Composer RDRB(1)/Manual(0) data island packet insertion for
SPD, VSD, ISRC2, ISRC1 and ACP packets. On RDRB mode the described packet
scheduling is controlled by registers FC_DATAUTO1 and FC_DATAUTO2, while in
Manual mode register FC_DATMAN requests to FC the insertion of the requested
packet.
• Address Offset: 0x10B3
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved spd_auto vsd_auto iscr2_auto iscr1_auto acp_auto
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_DATAUTO0 field descriptions

Field Description
- Reserved
4 Enables SPD automatic packet scheduling
spd_auto
3 Enables VSD automatic packet scheduling
vsd_auto

HDMI_FC_DATAUTO0 field descriptions (continued)

Field Description
2 Enables ISRC2 automatic packet scheduling
iscr2_auto
1 Enables ISRC1 automatic packet scheduling
iscr1_auto
0 Enables ACP automatic packet scheduling
acp_auto

Configures the Frame Composer (FC) RDRB frame interpolation for SPD, VSD, ISRC2,
ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed
packets.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved AUTO_FRAME_INTERPOLATION
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
AUTO_FRAME_ Packet frame interpolation, for automatic packet scheduling
INTERPOLATION

Configures the Frame Composer (FC) RDRB line interpolation and number of packets in
frame for SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is
on RDRB mode for the listed packets.

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read AUTO_FRAME_PACKETS AUTO_LINE_SPACING
Write
Reset 0 0 0 0 0 0 0 0

Field Description
7–4 Packets per frame, for automatic packet scheduling
AUTO_FRAME_
PACKETS
AUTO_LINE_ Packets line spacing, for automatic packet scheduling
SPACING
33.5.131 Frame Composer Data Island Manual Packet Request

Register (HDMI_FC_DATMAN)
Requests to the Frame Composer the data island packet insertion for NULL, SPD, VSD,
ISRC2, ISRC1 and ACP packets when FC_DATAUTO0 bit is in manual mode for the
packet requested.
• Size: 8 bits
• Access: Write
Bit 7 6 5 4 3 2 1 0
Read
Reserved
Write null_tx spd_tx vsd_tx iscr2_tx isr1_tx acp_tx
Reset 0 0 0 0 0 0 0 0
HDMI_FC_DATMAN field descriptions

Field Description
- Reserved
5 Null packet
null_tx

HDMI_FC_DATMAN field descriptions (continued)

Field Description
4 SPD packet
spd_tx
3 VSD packet
vsd_tx
2 ISRC2 packet
iscr2_tx
1 ISRC1 packet
isr1_tx
0 ACP packet
acp_tx

Configures the Frame Composer Automatic(1)/RDRB(0) data island packet insertion for
AVI, GCP, AUDI and ACR packets. In Automatic mode, the packet will be inserted on
Vblanking when first line with active Vsync appears.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved avi_auto gcp_auto audi_auto acr_auto
Write
Reset 0 0 0 0 1 1 1 1

Field Description
- Reserved
3 Enable AVI packet insertion
avi_auto
2 Enable GCP packet insertion
gcp_auto
1 Enable AUDI packet insertion
audi_auto
0 Enable ACR packet insertion
acr_auto

33.5.133 Frame Composer Round Robin ACR Packet Insertion

Register 0 (HDMI_FC_RDRB0)
Configures the Frame Composer (FC) RDRB frame interpolation for ACR packet
insertion on data island when FC is on RDRB mode for this packet.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved ACRframeinterpolation
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_RDRB0 field descriptions

Field Description
- Reserved
ACRframeinterpolation ACR frame interpolation

frame for the ACR packet insertion on data island when FC is on RDRB mode this
packet.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read ACRpacketsinframe ACRpacketlinespacing
Write
Reset 0 0 0 0 0 0 0 0


Field Description
7–4 ACR packets in frame
ACRpacketsinframe
ACRpacketlinespacing ACR packet line spacing

Configures the Frame Composer (FC) RDRB frame interpolation for AUDI packet
• Address Offset: 0x10BA
• Size: 8 bits
Address: 12_0000h base + 10BAh offset = 12_10BAh
Bit 7 6 5 4 3 2 1 0
Read Reserved AUDIframeinterpolation
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
AUDIframeinterpolation Audio frame interpolation

frame for the AUDI packet insertion on data island when FC is on RDRB mode this
packet.
• Address Offset: 0x10BB
• Size: 8 bits

Address: 12_0000h base + 10BBh offset = 12_10BBh
Bit 7 6 5 4 3 2 1 0
Read AUDIpacketsinframe AUDIpacketlinespacing
Write
Reset 0 0 0 0 0 0 0 0

Field Description
7–4 Audio packets per frame
AUDIpacketsinframe
AUDIpacketlinespacing Audio packets line spacing

Configures the Frame Composer (FC) RDRB frame interpolation for GCP packet
• Address Offset: 0x10BC
• Size: 8 bits
Address: 12_0000h base + 10BCh offset = 12_10BCh
Bit 7 6 5 4 3 2 1 0
Read Reserved GCPframeinterpolation
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
GCPframeinterpolation GCP packets line spacing

frame for the GCP packet insertion on data island when FC is on RDRB mode this
packet.
• Address Offset: 0x10BD
• Size: 8 bits
Address: 12_0000h base + 10BDh offset = 12_10BDh
Bit 7 6 5 4 3 2 1 0
Read GCPpacketsinframe GCPpacketlinespacing
Write
Reset 0 0 0 0 0 0 0 0

Field Description
7–4 GCP packets per frame
GCPpacketsinframe
GCPpacketlinespacing GCP packets line spacing

Configures the Frame Composer (FC) RDRB frame interpolation for AVI packet
• Address Offset: 0x10BE
• Size: 8 bits
Address: 12_0000h base + 10BEh offset = 12_10BEh
Bit 7 6 5 4 3 2 1 0
Read Reserved AVIframeinterpolation
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
AVIframeinterpolation GCP packets line spacing


frame for the AVI packet insertion on data island when FC is on RDRB mode this packet.
• Address Offset: 0x10BF
• Size: 8 bits
Address: 12_0000h base + 10BFh offset = 12_10BFh
Bit 7 6 5 4 3 2 1 0
Read AVIpacketsinframe AVIpacketlinespacing
Write
Reset 0 0 0 0 0 0 0 0

Field Description
7–4 AVI packets per frame
AVIpacketsinframe
AVIpacketlinespacing AVI packets line spacing
33.5.141 FC_STAT0 (HDMI_FC_STAT0)

frame for the AVI packet insertion on data island when FC is on RDRB mode this packet.
• Address Offset: 0x10D0
• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read AUDI ACP HBR AUDS ACR NULL

Reserved
Write
Reset 0 0 0 0 0 0 0 0

HDMI_FC_STAT0 field descriptions

Field Description
7 Status bit
AUDI
Active after successful transmission of an Audio InfoFrame packet.
6 Status bit. Active after successful transmission of an Audio Content Protection Packet.
ACP
5 Status bit. Active after successful transmission of an Audio HBR packet
HBR
- Reserved
2 Status bit
AUDS
Active after successful transmission of an Audio Sample packet.
1 Status bit
ACR
Active after successful transmission of an Audio Clock Regeneration (N/CTS transmission) packet.
0 Status bit
NULL
Active after successful transmission of an Null packet.
33.5.142 FC_INT0 (HDMI_FC_INT0)

This register contains the interrupt indication of the FC_STAT0 status interrupts.
Interrupt generation is accomplished in the following way:
interface.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read AUDI ACP HBR Reserved AUDS ACR NULL
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_INT0 field descriptions

Field Description
7 Interrupt indication bit
AUDI
HDMI_FC_INT0 field descriptions (continued)

Field Description
Active after successful transmission of an Audio InfoFrame packet interrupt.
ACP
Active after successful transmission of an Audio Content Protection packet interrupt.
HBR
Active after successful transmission of a Audio HBR packet interrupt.
- Reserved
AUDS
Active after successful transmission of an Audio Sample packet interrupt.
ACR
Active after successful transmission of an Audio Clock Regeneration (N/CTS transmission) packet
interrupt.
NULL
Active after successful transmission of an Null packet interrupt.
33.5.143 Frame Composer Packet Interrupt Mask Register 0

(HDMI_FC_MASK0)
Mask register for generation of FC_INT0 interrupts.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 1 0 0 1 0 1
HDMI_FC_MASK0 field descriptions

Field Description
7 Mask bit for FC_INT0.AUDI interrupt bit
AUDI
6 Mask bit for FC_INT0.ACP interrupt bit
ACP
5 Mask bit for FC_INT0.HBR interrupt bit
HBR

HDMI_FC_MASK0 field descriptions (continued)

Field Description
- Reserved
2 Mask bit for FC_INT0.AUDS interrupt bit
AUDS
1 Mask bit for FC_INT0.ACR interrupt bit
ACR
0 Mask bit for FC_INT0.NULL interrupt bit
NULL
33.5.144 FC_POL0 (HDMI_FC_POL0)

Polarity register for generation of FC_INT0 interrupts.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 1 1 1 1 1 1 1 1
HDMI_FC_POL0 field descriptions

Field Description
7 Polarity bit for FC_INT0.AUDI interrupt bit
AUDI
6 Polarity bit for FC_INT0.ACP interrupt bit
ACP
5 Polarity bit for FC_INT0.HBR interrupt bit
HBR
- Reserved
2 Polarity bit for FC_INT0.AUDS interrupt bit
AUDS
1 Polarity bit for FC_INT0.ACR interrupt bit
ACR
0 Polarity bit for FC_INT0.NULL interrupt bit
NULL


This register contains the following active high packet sent status indications:
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read GMD ISCR1 ISCR2 VSD SPD Reserved AVI GCP
Write
Reset 0 0 0 0 0 0 0 0

Field Description
7 Status bit
GMD
Active after successful transmission of an Gamut metadata packet.
6 Status bit
ISCR1
Active after successful transmission of an International Standard Recording Code 1 packet.
ISCR2
4 Active after successful transmission of an Vendor Specific Data infoFrame packet.
VSD
3 Active after successful transmission of an Source Product Descriptor infoFrame packet.
SPD
- Reserved
1 Status bit
AVI
Active after successful transmission of an AVI infoFrame packet.
0 Status bit
GCP
Active after successful transmission of an General Content Packet.


interface.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
GMD
Active after successful transmission of an Gamut metadata packet interrupt.
ISCR1
Active after successful transmission of an International Standard Recording
Code 1 packet interrupt.
ISCR2
Active after successful transmission of an International Standard Recording
Code 2 packet interrupt.
VSD
Active after successful transmission of an Vendor Specific Data infoFrame packet interrupt.
SPD
Active after successful transmission of an Source Product Descriptor infoFrame packet interrupt.
- Reserved
AVI
Active after successful transmission of an AVI infoFrame packet interrupt.
GCP
Active after successful transmission of an General Content Packet interrupt.
33.5.147 Frame Composer Packet Interrupt Mask Register 1

(HDMI_FC_MASK1)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
7 Mask bit for FC_INT1.GMD interrupt bit
GMD
6 Mask bit for FC_INT1.ISRC1 interrupt bit
ISCR1
5 Mask bit for FC_INT1.ISRC2 interrupt bit
ISCR2
4 Mask bit for FC_INT1.VSD interrupt bit
VSD
3 Mask bit for FC_INT1.SPD interrupt bit
SPD
- Reserved
1 Mask bit for FC_INT1.AVI interrupt bit
AVI
0 Mask bit for FC_INT1.GCP interrupt bit
GCP

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 1 1 1 1 1 1 1 1


Field Description
7 Polarity bit for FC_INT1.GMD interrupt bit
GMD
6 Polarity bit for FC_INT1.ISRC1 interrupt bit
ISCR1
5 Polarity bit for FC_INT1.ISRC2 interrupt bit
ISCR2
4 Polarity bit for FC_INT1.VSD interrupt bit
VSD
3 Polarity bit for FC_INT1.SPD interrupt bit
SPD
- Reserved
1 Polarity bit for FC_INT1.AVI interrupt bit
AVI
0 Polarity bit for FC_INT1.GCP interrupt bit
GCP

This register contains the following active high packet sent status indications:
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Reserved
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
1 Status bit
LowPriority_
Frame Composer low priority packet queue descriptor overflow indication.
overflow
0 Status bit
HighPriority_
Frame Composer high priority packet queue descriptor overflow indication.
overflow


interface.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Reserved
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
LowPriority_
Frame Composer low priority packet queue descriptor overflow indication interrupt.
overflow
HighPriority_
Frame Composer high priority packet queue descriptor overflow indication interrupt.
overflow
33.5.151 Frame Composer High/Low Priority Overflow Interrupt

Mask Register 2 (HDMI_FC_MASK2)
• Address Offset: 0x10DA
• Size: 8 bits

Address: 12_0000h base + 10DAh offset = 12_10DAh
Bit 7 6 5 4 3 2 1 0
Reserved
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
1 Mask bit for FC_INT1.LowPriority_overflow interrupt bit
LowPriority_
overflow
0 Mask bit for FC_INT1.HighPriority_overflow interrupt bit
HighPriority_
overflow

• Address Offset: 0x10DB
• Size: 8 bits
Address: 12_0000h base + 10DBh offset = 12_10DBh
Bit 7 6 5 4 3 2 1 0
Reserved
Reset 0 0 0 0 0 0 1 1

Field Description
- Reserved
1 Polarity bit for FC_INT1.LowPriority_overflow interrupt bit
LowPriority_
overflow
0 Polarity bit for FC_INT1.HighPriority_overflow interrupt bit
HighPriority_
overflow

33.5.153 Frame Composer Pixel Repetition Configuration

Register (HDMI_FC_PRCONF)
Defines the Pixel Repetition ratio factor of the input and output video signal.
• Address Offset: 0x10E0
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read incoming_pr_factor[3:0] output_pr_factor[3:0]
Write
Reset 0 0 0 1 0 0 0 0
HDMI_FC_PRCONF field descriptions

Field Description
7–4 Configures the input video pixel repetition. A plus 1 factor should be added in this register configuration.
incoming_pr_ For CEA modes this value should be extracted from the CEA spec for the video mode being inputted.
factor[3:0]
NOTE: When working in YCC422 video the actual repetition of the stream will be Incoming_pr_factor *
(desired_pr_factor + 1). This calculation is done internally in the H13TCTRL and no HW overflow
protection is available. Care must be taken to avoid this result passes the maximum number of 10
pixels repeated since no HDMI support is available for this in the spec and the H13TPHY does
not support this higher repetition values.
other: Reserved. Not used.
0000 No action. Shall not be used.

0001 No pixel repetition (pixel sent only once).
0010 Pixel sent twice (pixel repeated once).
0011 Pixel sent 3 times.
output_pr_ Configures the video pixel repetition ratio to be sent on the AVI infoFrame. This value must be valid
factor[3:0] according to HDMI spec. The output_pr_factor = incoming_pr_factor(without the + 1 factor) *
desired_pr_factor.
other: Reserved. Not used.
0000 No action. Shall not be used.

0001 Pixel sent twice (pixel repeated once).

HDMI_FC_PRCONF field descriptions (continued)

Field Description
33.5.154 Frame Composer GMD Packet Status Register

(HDMI_FC_GMD_STAT)
Gamut metadata packet status bit information for no_current_gmd, next_gmd_field,
gmd_packet_sequence and current_gamut_seq_num. For more information, refer to the
HDMI 1.4a specification.
• Size: 8 bits
• Access: Read
Bit 7 6 5 4
Read igmdno_crnt_gbd igmddnext_field igmdpacket_seq[1:0]
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read igmdcurrent_gamut_seq_num[3:0]
Write
Reset 0 0 0 0
HDMI_FC_GMD_STAT field descriptions

Field Description
7 Gamut scheduling: No current gamut data
igmdno_crnt_gbd
6 Gamut scheduling: Gamut Next field
igmddnext_field
5–4 Gamut scheduling: Gamut packet sequence
igmdpacket_
seq[1:0]
igmdcurrent_ Gamut scheduling: Current Gamut packet sequence number
gamut_seq_
num[3:0]

33.5.155 Frame Composer GMD Packet Enable Register

(HDMI_FC_GMD_EN)
This register enables Gamut metadata (GMD) packet transmission. Packets are inserted in
the incoming frame, starting in the line where active Vsync indication starts. After enable
of GMD packets the outgoing packet is sent with no_current_gmd active indication until
update GMD request is performed in the controller.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read gmdenablet
Reserved
Write x
Reset 0 0 0 0 0 0 0 0
HDMI_FC_GMD_EN field descriptions

Field Description
- Reserved
0 Gamut Metadata packet transmission enable (1b).
gmdenabletx
33.5.156 Frame Composer GMD Packet Update Register

(HDMI_FC_GMD_UP)
This register performs an GMD packet content update according to the configured packet
body (FC_GMD_PB0 to FC_GMD_PB27) and packet header (FC_GMD_HB). This
active high auto clear register reflects the body and header configurations on the GMD
packets sent arbitrating the current_gamut_seq_num, gmd_packet_sequence and
next_gmd_field bits on packet to correctly indicate to source the Gamut change to be
performed. After enable GMD packets the first update request is also responsible for
deactivating the no_current_gmd indication bit. Attention packet update request must
only be done after correct configuration of GMD packet body and header registers.
Correct affected_gamut_seq_num and gmd_profile configuration is user responsibility
and must convey with HDMI 1.4a standard gamut rules.

• Size: 8 bits
• Access: Write
Bit 7 6 5 4
Read
Reserved
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read
Reserved
Write gmdupdatepacket
Reset 0 0 0 0
HDMI_FC_GMD_UP field descriptions

Field Description
- Reserved
0 Gamut Metadata packet update.
gmdupdatepacket
33.5.157 Frame Composer GMD Packet Schedule Configuration

Register (HDMI_FC_GMD_CONF)
This register configures the number of GMD packets to be inserted per frame (starting
always in the line where the active Vsync appears) and the line spacing between the
transmitted GMD packets. Note that for profile P0 (refer to HDMI 1.4a spec) this register
should only indicate one GMD packet to be inserted per video field.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read gmdpacketsinframe[3:0] gmdpacketlinespacing[3:0]
Write
Reset 0 0 0 1 0 0 0 0

HDMI_FC_GMD_CONF field descriptions

Field Description
7–4 Number of GMD packets per frame or video field (profile P0)
gmdpacketsinframe[3:0]
gmdpacketlinespacing[3:0] Number of line spacing between the transmitted GMD packets
33.5.158 Frame Composer GMD Packet Profile and Gamut

Sequence Configuration Register (HDMI_FC_GMD_HB)
This register configures the GMD packet header affected_gamut_seq_num and
gmd_profile bits. For more information, refer to the HDMI 1.4a specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved gmdgbd_profile gmdaffected_gamut_seq_num
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_GMD_HB field descriptions

Field Description
- Reserved
6–4 GMD profile bits
gmdgbd_profile
gmdaffected_ Affected gamut sequence number
gamut_seq_num
33.5.159 Frame Composer GMD Packet Body Register 0

(HDMI_FC_GMD_PB0)
Configures the following contents of the GMD packet:
• GMD packet body byte0
• Size: 8 bits

For more information, refer to the HDMI 1.4a specification.

Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_GMD_PB0 field descriptions

Field Description
FC_GMD_PB0 Gamut Metadata packet byte0

(HDMI_FC_GMD_PB1)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB1
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB2)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB2
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB3)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB3
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB4)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB4
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB5)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB5
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB6)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB6
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB7)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB2
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB8)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB8
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB9)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB9
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB10)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB10
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB11)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB11
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB12)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB12
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB13)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB13
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB14)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB14
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB15)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB15
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB16)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB16
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB17)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB17
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB18)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB18
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB19)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB18
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB20)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB20
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB21)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB21
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB22)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB22
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB23)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB23
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB24)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB24
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB25)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB25
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB26)
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB26
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_FC_GMD_PB27)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_GMD_PB27
Write
Reset 0 0 0 0 0 0 0 0

Field Description
33.5.187 Frame Composer Video/Audio Force Enable Register

(HDMI_FC_DBGFORCE)
This register allows to force the controller to output audio and video data the values
configured in the FC_DBGAUD and FC_DBGTMDS registers.
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read Reserved forceaudio Reserved forcevideo
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_DBGFORCE field descriptions

Field Description
- Reserved
4 Force fixed audio output with FC_DBGAUDxCHx registers contain.
forceaudio
- Reserved
0 Force fixed video output with FC_DBGTMDSx registers contain.
forcevideo
33.5.188 Frame Composer Audio Channel 0 Register 0

(HDMI_FC_DBGAUD0CH0)
Configures the audio fixed data to be used in channel 0 when in fixed audio selection.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD0CH0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_DBGAUD0CH0 field descriptions

Field Description
FC_ the audio fixed data byte0 to be used in channel 0 when in fixed audio selection
DBGAUD0CH0



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_DBGAUD1CH0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD1CH0


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD2CH0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD2CH0


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD0CH1
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD0CH1


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD1CH1
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD1CH1



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_DBGAUD2CH1
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD2CH1
33.5.194 Frame Composer Debug Audio Channel 2 Register 0

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD0CH2
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD0CH2

33.5.195 Frame Composer Debug Audio Channel 2 Register 1


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_DBGAUD1CH2
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD1CH2


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD2CH2
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD2CH2


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD0CH3
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD0CH3


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD1CH3
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD1CH3



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_DBGAUD2CH3
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD2CH3

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD0CH4
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD0CH4



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_DBGAUD1CH4
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD1CH4


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD2CH4
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD2CH4


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD0CH5
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD0CH5


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD1CH5
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD1CH5



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_DBGAUD2CH5
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD2CH5

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD0CH6
Write
Reset 0 0 0 0 0 0 0 0

Field Description
FC_ The audio fixed data byte0 to be used in channel 6 when in fixed audio selection
DBGAUD0CH6



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_DBGAUD1CH6
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD1CH6


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD2CH6
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD2CH6


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD0CH7
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD0CH7


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGAUD1CH7
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD1CH7



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
FC_DBGAUD2CH7
Write
Reset 0 0 0 0 0 0 0 0

Field Description
DBGAUD2CH7
33.5.212 Frame Composer TMDS Channel 0 Register

(HDMI_FC_DBGTMDS0)
Configures the video fixed data to be used in tmds channel 0 when in fixed video
selection. This equals to set B pixel component value in RGB video or Cb pixel
component value in YCbCr.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGTMDS0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_FC_DBGTMDS0 field descriptions

Field Description
FC_DBGTMDS0 set B pixel component value in RGB video or Cb pixel component value in YCbCr


(HDMI_FC_DBGTMDS1)
selection. This equals to set G pixel component value in RGB video or Y pixel
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGTMDS1
Write
Reset 0 0 0 0 0 0 0 0

Field Description
FC_DBGTMDS1 set G pixel component value in RGB video or Y pixel component value in YCbCr

(HDMI_FC_DBGTMDS2)
selection. This equals to set R pixel component value in RGB video or Cr pixel
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read FC_DBGTMDS2
Write
Reset 0 0 0 0 0 0 0 0


Field Description
FC_DBGTMDS2 set R pixel component value in RGB video or Cr pixel component value in YCbCr
33.5.215 PHY Configuration Register (HDMI_PHY_CONF0)

This register holds the power down, data enable polarity and interface control of the
HDMI Source PHY control. For more information, refer to the DesignWare Cores HDMI
TX PHY Databook.
• Size: 8 bits
Bit 7 6 5 4
Read PDZ ENTMDS sparectrl gen2_pddq
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read gen2_txpwron gen2_enhpdrxsense seldataenpol seldipif
Write
Reset 0 1 1 0
HDMI_PHY_CONF0 field descriptions

Field Description
7 Power-down enable (active low 0b).
PDZ
6 Enable TMDS drivers, bias, and TMDS digital logic.
ENTMDS
5 Reserved. Spare pin control.
sparectrl
4 PHY_Gen2 PDDQ signal
gen2_pddq
3 PHY_Gen2 TXPWRON signal
gen2_txpwron
2 PHY_Gen2 ENHPDRXSENSE signal
gen2_
enhpdrxsense
1 Select data enable polarity.
seldataenpol

HDMI_PHY_CONF0 field descriptions (continued)

Field Description
0 Select interface control.
seldipif
33.5.216 PHY Test Interface Register 0 (HDMI_PHY_TST0)

PHY TX mapped text interface (control). For more information, refer to the DesignWare
Cores HDMI TX PHY Databook.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved testclr testen Reserved testclk
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_TST0 field descriptions

Field Description
- Reserved
5 Enable TMDS drivers, bias and tmds digital logic.
testclr
4 Reserved. Spare control pins.
testen
- Reserved
0 Test clock signal.
testclk

PHY TX mapped text interface (data in). For more information, refer to the DesignWare
• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Read testdin[7:0]
Write
Reset 0 0 0 0 0 0 0 0

Field Description
testdin[7:0] Test data input.

PHY TX mapped text interface (data out). For more information, refer to the DesignWare
• Size: 8 bits
• Value after Reset: N/A
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read testdout[7:0]
Write
Reset 0 0 0 0 0 0 0 0

Field Description
testdout[7:0] Test data output.
33.5.219 PHY RXSENSE, PLL lock, and HPD Status Register

(HDMI_PHY_STAT0)
This register contains the following active high packet sent status indications. For more
information, see Overview
• Size: 8 bits


• Access: Read
Bit 7 6 5 4
Read RX_SENSE3 RX_SENSE2 RX_SENSE1 RX_SENSE0
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read HPD TX_PHY_LOCK

Reserved
Write
Reset 0 0 0 0
HDMI_PHY_STAT0 field descriptions

Field Description
7 Status bit. TX PHY RX_SENSE indication for TMDS CLK driver. User may need to mask or change
RX_SENSE3 polarity of this interrupt after it has became active.
6 Status bit. TX PHY RX_SENSE indication for TMDS channel 2 driver. User may need to mask or change
- Reserved
1 Status bit. HDMI Hot Plug Detect indication. User may need to mask or change polarity of this interrupt
HPD after it has became active.
0 Status bit. TX PHY PLL lock indication. Please refer to PHY datasheet for more information. User may
TX_PHY_LOCK need to mask or change polarity of this interrupt after it has became active.
33.5.220 PHY RXSENSE, PLL lock, and HPD Interrupt Register

(HDMI_PHY_INT0)
This register contains the interrupt indication of the PHY_STAT0 status interrupts.
interface.
• Size: 8 bits
• Access: Read
Bit 7 6 5 4
Read RX_SENSE3 RX_SENSE2 RX_SENSE1 RX_SENSE0
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read HPD TX_PHY_LOCK

Reserved
Write
Reset 0 0 0 0
HDMI_PHY_INT0 field descriptions

Field Description
RX_SENSE3
TX PHY RX_SENSE indication interrupt for TMDS CLK driver.
RX_SENSE2
TX PHY RX_SENSE indication interrupt for TMDS channel 2 driver.
RX_SENSE1
RX_SENSE0
- Reserved
HPD
HDMI Hot Plug Detect indication interrupt.
TX_PHY_LOCK
TX PHY PLL lock indication interrupt.
33.5.221 PHY RXSENSE, PLL lock, and HPD Mask Register

(HDMI_PHY_MASK0)
Mask register for generation of PHY_INT0 interrupts.
• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Reserved HPD
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_MASK0 field descriptions

Field Description
7 Mask bit for PHY_INT0.RX_SENSE3 interrupt bit
RX_SENSE3
RX_SENSE2
RX_SENSE1
RX_SENSE0
- Reserved
1 Mask bit for PHY_INT0.HPD interrupt bit
HPD
0 Mask bit for PHY_INT0.TX_PHY_LOCK interrupt bit
TX_PHY_LOCK
33.5.222 PHY RXSENSE, PLL lock and HPD Polarity Register

(HDMI_PHY_POL0)
Polarity register for generation of PHY_INT0 interrupts.
• Size: 8 bits
• Value after Reset: 0xF3
Bit 7 6 5 4 3 2 1 0
Reserved HPD
Reset 1 1 1 1 0 0 1 1
HDMI_PHY_POL0 field descriptions

Field Description
7 Polarity bit for PHY_INT0.RX_SENSE3 interrupt bit
RX_SENSE3

HDMI_PHY_POL0 field descriptions (continued)

Field Description
RX_SENSE2
RX_SENSE1
RX_SENSE0
- Reserved
1 Polarity bit for PHY_INT0.HPD interrupt bit
HPD
0 Polarity bit for PHY_INT0.TX_PHY_LOCK interrupt bit
TX_PHY_LOCK
33.5.223 PHY I2C Slave Address Configuration Register

(HDMI_PHY_I2CM_SLAVE_ADDR)
This register writes the slave address of the I2C Master PHY.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved -
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_SLAVE_ADDR field descriptions

Field Description
- Reserved
- Slave address to be sent during read and write operations. The PHY Gen2 slave address is: 7'h69
The HEAC PHY slave address is: 7'h49
33.5.224 PHY I2C Address Configuration Register

(HDMI_PHY_I2CM_ADDRESS_ADDR)
This register writes the address for read and writer operations.


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read address
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_ADDRESS_ADDR field descriptions

Field Description
address Register address for read and write operations.
33.5.225 PHY I2C Data Write Register 1

(HDMI_PHY_I2CM_DATAO_1_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read datao[15:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_DATAO_1_ADDR field descriptions

Field Description
datao[15:8] MSB's of data to be written on register pointed by address [7:0].

33.5.226 PHY I2C Data Write Register 0

(HDMI_PHY_I2CM_DATAO_0_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
datao[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_DATAO_0_ADDR field descriptions

Field Description
datao[7:0] LSB's of data to be written on register pointed by address [7:0].
33.5.227 PHY I2C Data Read Register 1

(HDMI_PHY_I2CM_DATAI_1_ADDR)

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read datai[15:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_DATAI_1_ADDR field descriptions

Field Description
datai[15:8] MSB's of data read from the register pointed by address [7:0].

33.5.228 PHY I2C Data Read Register 0

(HDMI_PHY_I2CM_DATAI_0_ADDR)

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read
datai[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_DATAI_0_ADDR field descriptions

Field Description
datai[7:0] LSB's of data read from the register pointed by address [7:0].
33.5.229 PHY I2C Read/Write Operation

(HDMI_PHY_I2CM_OPERATION_ADDR)
This register requests read and write operations from the I2C Master PHY. This register
can only be written; reading this register always results in 00h. Writing 1'b1
simultaneously to read and write requests is considered a read request.
• Size: 8 bits
• Access: Write
Bit 7 6 5 4 3 2 1 0
Read
Reserved Reserved
Write write read
Reset 0 0 0 0 0 0 0 0

HDMI_PHY_I2CM_OPERATION_ADDR field descriptions

Field Description
- Reserved
4 Write operation request
write
- Reserved
0 Read operation request.
read
33.5.230 PHY I2C Done Interrupt Register

(HDMI_PHY_I2CM_INT_ADDR)
This register contains and configures I2C master PHY done interrupt.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read done_
Reserved done_pol done_mask done_status
Write interrupt
Reset 0 0 0 0 1 0 0 0
HDMI_PHY_I2CM_INT_ADDR field descriptions

Field Description
- Reserved
3 Done interrupt polarity configuration
done_pol
2 Done interrupt mask signal
done_mask
1 Operation done interrupt bit.{done_interrupt =(done_mask==0b)&& (done_status==done_pol)}.
done_interrupt
0 Operation done status bit.Marks the end of a rd or write operation.
done_status

33.5.231 PHY I2C Done Interrupt Register

(HDMI_PHY_I2CM_CTLINT_ADDR)
This register contains and configures the I2C master PHY error interrupts.
• Size: 8 bits
Bit 7 6 5 4
Read nack_pol nack_mask nack_interrupt nack_status
Write
Reset 1 0 0 0
Bit 3 2 1 0
Read arbitration_pol arbitration_mask arbitration_interrupt arbitration_status
Write
Reset 1 0 0 0
HDMI_PHY_I2CM_CTLINT_ADDR field descriptions

Field Description
7 Not acknowledge error interrupt polarity configuration.
nack_pol
6 Not acknowledge error interrupt mask signal
nack_mask
5 Not acknowledge error interrupt bit.{nack_interrupt = nack_mask==0b) && (nack_status==nack_pol)}.
nack_interrupt
4 Not acknowledge error status bit.Error on I2C not acknowledge.
nack_status
3 Arbitration error interrupt polarity configuration.
arbitration_pol
2 Arbitration error interrupt mask signal.
arbitration_mask
1 Arbitration error interrupt bit.{arbitration_interrupt = (arbitration_mask==0b)&&
arbitration_ (arbitration_status==arbitration_pol)}.
interrupt
0 Arbitration error status bit. Error on master I2C protocol arbitration.
arbitration_status

33.5.232 PHY I2C Speed Control Register

(HDMI_PHY_I2CM_DIV_ADDR)
This register wets the I2C Master PHY to work in either Fast or Standard mode.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved fast_mode
Write
Reset 0 0 0 0 1 0 1 1
HDMI_PHY_I2CM_DIV_ADDR field descriptions

Field Description
- Reserved
fast_mode Sets the I2C Master to work in Fast Mode or Standard Mode
(x implies that it can take any value)
1xxxb Fast Mode
0xxxb Standard Mode
33.5.233 PHY I2C Software Reset Register

(HDMI_PHY_I2CM_SOFTRSTZ_ADDR)
This register sets the I2C Master PHY software reset.
• Size: 8 bits
The following *CNT registers must be set before any I2C bus transaction can take place
to ensure proper I/O timing.
The following are the I2C Master SCL clock settings:
• SS: Standard Speed

• FS: Fast Speed

• HCNT: SCL High Level counter
• LCNT: SCL Low Level counter
Bit 7 6 5 4 3 2 1 0
Read Reserved i2c_softrst
Write
Reset 0 0 0 0 0 0 0 1
HDMI_PHY_I2CM_SOFTRSTZ_ADDR field descriptions

Field Description
- Reserved
0 I2C Master PHY Software Reset. Active by writing a zero and auto cleared to one in the following cycle.
i2c_softrst
33.5.234 PHY I2C Slow Speed SCL High Level Control Register 1
(HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read i2cmp_ss_scl_hcnt[15:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR field descriptions

Field Description
i2cmp_ss_scl_ Value after Reset: 8'h00
hcnt[15:8]

33.5.235 PHY I2C Slow Speed SCL High Level Control Register 0
(HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR)

• Size: 8 bits
• Value after Reset: 0x6C
Bit 7 6 5 4 3 2 1 0
Read
i2cmp_ss_scl_hcnt[7:0]
Write
Reset 0 1 1 0 1 1 0 0
HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR field descriptions

Field Description
i2cmp_ss_scl_ Value after Reset: 8'h6C
hcnt[7:0]
33.5.236 PHY I2C Slow Speed SCL Low Level Control Register 1
(HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read i2cmp_ss_scl_lcnt[15:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR field descriptions

Field Description
lcnt[15:8]

33.5.237 PHY I2C Slow Speed SCL Low Level Control Register 0
(HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
i2cmp_ss_scl_lcnt[7:0]
Write
Reset 0 1 1 1 1 1 1 1
HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR field descriptions

Field Description
i2cmp_ss_scl_ Value after Reset: 8'h7F
lcnt[7:0]
33.5.238 PHY I2C Fast Speed SCL High Level Control Register 1
(HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read i2cmp_fs_scl_hcnt[15:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR field descriptions

Field Description
i2cmp_fs_scl_ Value after Reset: 8'h00
hcnt[15:8]

33.5.239 PHY I2C Fast Speed SCL High Level Control Register 0
(HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
i2cmp_fs_scl_hcnt[7:0]
Write
Reset 0 0 0 1 0 0 0 1
HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR field descriptions

Field Description
hcnt[7:0]
33.5.240 PHY I2C Fast Speed SCL Low Level Control Register 1
(HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read i2cmp_fs_scl_lcnt[15:8]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR field descriptions

Field Description
lcnt[15:8]

33.5.241 PHY I2C Fast Speed SCL Low Level Control Register 0
(HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
i2cmp_fs_scl_lcnt[7:0]
Write
Reset 0 0 1 0 0 1 0 0
HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR field descriptions

Field Description
lcnt[7:0]
33.5.242 Audio Clock Regenerator N Value Register 1

(HDMI_AUD_N1)
For N expected values, refer to the HDMI 1.4a specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read AudN[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_AUD_N1 field descriptions

Field Description
AudN[7:0] HDMI Audio Clock Regenerator N value


(HDMI_AUD_N2)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read AudN[15:8]
Write
Reset 0 0 0 0 0 0 0 0

Field Description

(HDMI_AUD_N3)
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved AudN[19:16]
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved

33.5.245 AUD_CTS1 (HDMI_AUD_CTS1)

For CTS expected values, refer to the HDMI 1.4a specification.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read audCTS[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_AUD_CTS1 field descriptions

Field Description
audCTS[7:0] HDMI Audio Clock Regenerator CTS calculated value. This value can be manually set using the
CTS_manual (AUD_CTS3) mechanism.

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read audCTS[15:8]
Write
Reset 0 0 0 0 0 0 0 0

Field Description


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved audCTS[19:16]
Write
Reset 0 0 0 0 0 0 0 0

Field Description
- Reserved
33.5.248 Audio DMA Start Register (HDMI_AHB_DMA_CONF0)

This register contains the software reset bit for the audio FIFOs. It also configures
operating modes of the AHB master.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read enable_
sw_fifo_rst Reserved hbr incr_type[1:0] burst_mode
Write hlock
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_CONF0 field descriptions

Field Description
7 This is the software reset bit for the audio and FIFOs clear.
sw_fifo_rst
Writing 0'b does not result in any action.

HDMI_AHB_DMA_CONF0 field descriptions (continued)

Field Description
Writing 1'b to this register resets all audio FIFOs.
Reading from this register always returns 0'b.
- Reserved
4 HBR packets enable.
hbr
The HDMI TX sends the HBR packets. This bit is enabled when the audio frequency is higher than 192
KHz. If this bit is enabled, the number of channels configured in AHB_DMA_CONF1 is always 8.
3 Enable request of locked burst AHB mechanism.
enable_hlock
1 Enables the usage of ohlock for master request to arbiter of a locked complete burst.\
0 Disables request of locked burst AHB mechanism
2–1 Forced size burst mode.
incr_type[1:0]
00 Corresponds to INCR4 fixed four beat incremental AHB burst mode. Only valid when burst_mode is
high.
01 Corresponds to INCR8 fixed eight beat incremental AHB burst mode. Only valid when burst_mode is
high.
10 Corresponds to INCR16 fixed 16 beat incremental AHB burst mode. Only valid when burst_mode is
high.
11 Corresponds to INCR16 fixed 16 beat incremental AHB burst mode. Only valid when burst_mode is
high.
0 Burst mode bit
burst_mode
1 Forces the burst mode to be fixed beat incremental burst mode designated by the incr_type[1:0]
signal.
0 Normal operation is unspecified length incremental burst. It corresponds to INCR AHB burst mode.
33.5.249 AHB_DMA_START (HDMI_AHB_DMA_START)

The data_ buffer_ready bit field signals the AHB audio DMA to start accessing system
memory in order to fetch data samples to store in the FIFO. After the operation starts, a
new request for a DMA start is ignored until the DMA is stopped or it reaches the end
address. Only in one of these situations will a new start request be acknowledged.
The first DMA burst request after data_buffer_ready configuration uses the
initial_addr[31:0] as the ohaddr[31:0] and the MBURSTLENGTH[10:0] =
AUDIO_FIFO_DEPTH if AUDIO_FIFO_DEPTH < 1024 or MBURSTLENGTH[10:0]
= 1024 if AUDIO_FIFO_DEPTH >= 1024.
• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Read data_buffer_
Reserved
Write ready
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_START field descriptions

Field Description
- Reserved
0 Data buffer ready
data_buffer_
ready
33.5.250 Audio DMA Stop Register (HDMI_AHB_DMA_STOP)

The stop_dma_transaction bit field signals the AHB audio DMA to stop current memory
access. After it stops, if a new start DMA operation is requested, the DMA engine restarts
the memory access assuming the initial_addr[31:0] is programmed at
AHB_DMA_STRADDR0 to AHB_DMA_STRADDR3.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read stop_dma_
Reserved
Write transaction
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_STOP field descriptions

Field Description
- Reserved
0 Stop DMA transaction
stop_dma_
transaction

33.5.251 Audio DMA FIFO Threshold Register

(HDMI_AHB_DMA_THRSLD)
This register defines the FIFO medium threshold occupation value.
After the AHB master successfully completes a burst transaction, the FIFO may stay
remain full until the data fetch interface requests samples. The sample request from the
FIFO using the data fetch mechanism drops the number of samples stored in the audio
FIFO.
As soon as the number of samples in the FIFO drops lower than the fifo_threshold[7:0],
the DMA engine requests a new burst of samples to the AHB master with a size
(MBURSTLENGTH[10:0]) equal to AUDIO_FIFO_DEPTH minus fifo_threshold[7:0].
Therefore, the fifo_threshold[7:0] is the medium number of samples that should be
available in the audio FIFO across the DMA operation.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read fifo_threshold[7]
Write
Reset 0 0 0 1 0 0 0 0
HDMI_AHB_DMA_THRSLD field descriptions

Field Description
fifo_threshold[7] FIFO medium threshold occupation value
33.5.252 Audio DMA Start Address Register 0

(HDMI_AHB_DMA_STRADDR0)
These registers define the initial_addr[31:0] used to initiate the DMA burst read
transactions upon data_buffer_ready configuration.
• Size: 8 bits per register

Bit 7 6 5 4 3 2 1 0
Read initial_addr[7]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_STRADDR0 field descriptions

Field Description
initial_addr[7] Defines init_addr[7:0] for bits 7-0 to initiate DMA burst transactions

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description


Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
33.5.256 Audio DMA Stop Address Register 0

(HDMI_AHB_DMA_STPADDR0)
This registers define the final_addr[31:0] used as the final point to the DMA burst read
transactions.
Upon data_buffer_ready configuration, the DMA engine starts requesting burst reads
from the external system memory. Each burst read can have a maximum theoretical
length of 1024 words (due to the AMBA AHB specification restriction). As an example,
if the first burst transaction of the AHB audio DMA has a length of 16, then the second
burst starts at address ohaddr[31:0] = initial_addr[31:0] + 16 and has a length of
MBURSTLENGTH[10:0] = AUDIO_FIFO_DEPTH - fifo_threshold[7:0].
The DMA engine is responsible for incrementing the burst starting address and defining
its corresponding burst length to reach the final_addr[31:0] address. The last burst request
issued by the DMA engine takes into account that it should only request data until the
final_addr[31:0] address (included) and for that should calculate the correct burst length.
After reaching the final_addr[31:0] address, the done interrupt is active to signal
completion of DMA operation.
• Address Offset: 0x3608 to 0x360B

Bit 7 6 5 4 3 2 1 0
Read final_addr[7]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_STPADDR0 field descriptions

Field Description
final_addr[7] Defines final_addr[7:0] for bits 7-0 to initiate DMA burst transactions

Bit 7 6 5 4 3 2 1 0
Read final_addr[15]
Write
Reset 0 0 0 0 0 0 0 0

Field Description

Bit 7 6 5 4 3 2 1 0
Read final_addr[23]
Write
Reset 0 0 0 0 0 0 0 0

Field Description


Bit 7 6 5 4 3 2 1 0
Read final_addr[31]
Write
Reset 0 0 0 0 0 0 0 0

Field Description
33.5.260 Audio DMA Burst Start Address Register 0

(HDMI_AHB_DMA_BSTADDR0)
This read-only register composes the start address of the current burst operation. As an
example, if the first burst transaction of the AHB audio DMA as a length of 16, then the
second burst should start at address ohaddr[31:0] = initial_addr[31:0] + 16. While this
burst is being executed, burst_start_addr[31:0] = haddr[31:0] = initial_addr[31:0] + 16.
• Address Offset: 0x360C to 0x360F
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read burst_start[7]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_BSTADDR0 field descriptions

Field Description
burst_start[7] Start address for the current burst operation


Bit 7 6 5 4 3 2 1 0
Read burst_start[15]
Write
Reset 0 0 0 0 0 0 0 0

Field Description

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0


Field Description
33.5.264 Audio DMA Burst Length Register 0

(HDMI_AHB_DMA_MBLENGTH0)
These registers hold the length of the current burst operation. As an example, if the first
burst transaction of the AHB audio DMA is a length of 8, then the second burst should
start at address ohaddr[31:0] = initial_addr[31:0] + 8. It will also have length
MBURSTLENGTH[10:0] = AUDIO_FIFO_DEPTH - fifo_threshold[7:0] while this
burst is being executed, MBURSTLENGTH[10:0] = AUDIO_FIFO_DEPTH -
fifo_threshold[7:0].
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read MBURSTLENGTH7
Write
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_MBLENGTH0 field descriptions

Field Description
MBURSTLENGTH7 Requested burst length

33.5.265 Audio DMA Burst Length Register 1

(HDMI_AHB_DMA_MBLENGTH1)
Bit 7 6 5 4
Read
Reserved
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read MBURSTLENGTH10 MBURSTLENGTH9 MBURSTLENGTH8

Reserved
Write
Reset 0 0 0 0
HDMI_AHB_DMA_MBLENGTH1 field descriptions

Field Description
- Reserved
2 Requested burst length
MBURSTLENGTH10
MBURSTLENGTH9
MBURSTLENGTH8
33.5.266 Audio DMA Interrupt Status Register

(HDMI_AHB_DMA_STAT)
This register contains the status bits of the following interrupts:
• Access: Read
Bit 7 6 5 4
Read statdone statretrysplit statlostownership staterror
Write
Reset 0 0 0 0

Bit 3 2 1 0
Read statthrfifoempty statfifofull statfifoempty

Reserved
Write
Reset 0 0 0 0
HDMI_AHB_DMA_STAT field descriptions

Field Description
7 Status of DMA end of operation interrupt. Active when DMA engine reaches final_addr[15:0] or when
statdone stop DMA operation is activated.
6 Status of retry/split interrupt. Active when AHB master receives a RETRY or SPLIT response from
statretrysplit slave.
5 Status of master lost ownership when in burst transfer. Active when AHB master loses BUS ownership
statlostownership within the course of a burst transfer.
4 Status of error interrupt. Active when slave indicates error through the isresp[1:0].
staterror
- Reserved
2 Status of audio FIFO empty when audio FIFO has less than four samples.
statthrfifoempty
1 Status of audio FIFO full interrupt.
statfifofull
0 Status of audio FIFO empty interrupt.
statfifoempty
33.5.267 Audio DMA Interrupt Register (HDMI_AHB_DMA_INT)

This register contains the interrupt bits of the following interrupts:
• Access: Read
Bit 7 6 5 4
Read intdone intretrysplit intlostownership interror
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read intthrfifoempty intfifofull intfifoempty

Reserved
Write
Reset 0 0 0 0

HDMI_AHB_DMA_INT field descriptions

Field Description
7 DMA end of operation interrupt. Active when DMA engine reaches final_addr[15:0] or when stop DMA
intdone operation is activated.
6 Retry/split interrupt. Active when AHB master receives a RETRY or SPLIT response from slave.
intretrysplit
5 Master lost ownership interrupt when in burst transfer. Active when AHB master loses BUS ownership
intlostownership within the course of a burst transfer.
4 Error interrupt. Active when slave indicates error through the isresp[1:0].
interror
- Reserved
2 Audio FIFO empty interrupt when audio FIFO has less than four samples.
intthrfifoempty
1 Audio FIFO full interrupt.
intfifofull
0 Audio FIFO empty interrupt.
intfifoempty
33.5.268 Audio DMA Mask Interrupt Register

(HDMI_AHB_DMA_MASK)
Mask for each of the interrupts present in the AHB audio DMA module. For usage
information, see Audio DMA Interrupt Register (HDMI_AHB_DMA_INT) ."
Bit 7 6 5 4
Read done_mask retrysplit_mask lostownership_mask error_mask
Write
Reset 0 0 0 1
Bit 3 2 1 0
Read Reserved fifo_thrempty_mask fifo_full_mask fifo_empty_mask
Write
Reset 0 0 0 1
HDMI_AHB_DMA_MASK field descriptions

Field Description
7 DMA end of operation interrupt mask. Active when DMA engine reaches final_addr[15:0] or when stop
done_mask DMA operation is activated.

HDMI_AHB_DMA_MASK field descriptions (continued)

Field Description
6 Retry/split interrupt mask. Active when AHB master receives a RETRY or SPLIT response from slave.
retrysplit_mask
5 Master lost ownership interrupt mask when in burst transfer. Active when AHB master loses BUS
lostownership_ ownership within the course of a burst transfer.
mask
4 Error interrupt mask. Active when slave indicates error through the isresp[1:0].
error_mask
- Reserved
2 Audio FIFO empty interrupt mask when audio FIFO has less than four samples.
fifo_thrempty_
mask
1 Audio FIFO full interrupt mask.
fifo_full_mask
0 Audio FIFO empty interrupt mask.
fifo_empty_mask
33.5.269 Audio DMA Polarity Interrupt Register

(HDMI_AHB_DMA_POL)
Polarity for each of the interrupts present in the AHB audio DMA module. For usage
information, see Audio DMA Interrupt Register (HDMI_AHB_DMA_INT) ."
Bit 7 6 5 4
Read done_polarity retrysplit_polarity lostownership_polarity error_polarity
Write
Reset 0 0 0 1
Bit 3 2 1 0
Read fifo_thrfifoempty_
Reserved fifo_full_polarity fifo_empty_polarity
Write polarity
Reset 0 0 0 1
HDMI_AHB_DMA_POL field descriptions

Field Description
7 DMA end of operation interrupt mask. Active when DMA engine reaches final_addr[15:0] or when stop
done_polarity DMA operation is activated.

HDMI_AHB_DMA_POL field descriptions (continued)

Field Description
6 Retry/split interrupt mask. Active when AHB master receives a RETRY or SPLIT response from slave.
retrysplit_polarity
5 Master lost ownership interrupt mask when in burst transfer. Active when AHB master loses BUS
lostownership_ ownership within the course of a burst transfer.
polarity
4 Error interrupt mask. Active when slave indicates error through the isresp[1:0].
error_polarity
- Reserved
2 Audio FIFO empty interrupt mask when audio FIFO has less than four samples.
fifo_thrfifoempty_
polarity
1 Audio FIFO full interrupt mask.
fifo_full_polarity
0 Audio FIFO empty interrupt mask.
fifo_empty_
polarity
33.5.270 Audio DMA Channel Enable Configuration Register 1

(HDMI_AHB_DMA_CONF1)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read CH_IN_EN7 CH_IN_EN6 CH_IN_EN5 CH_IN_EN4 CH_IN_EN3 CH_IN_EN2 CH_IN_EN1 CH_IN_EN0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_CONF1 field descriptions

Field Description
7 Channel 7 enable bit
CH_IN_EN7
1 Channel enabled
0 Channel disabled
CH_IN_EN6
1 Channel enabled
0 Channel disabled

HDMI_AHB_DMA_CONF1 field descriptions (continued)

Field Description
CH_IN_EN5
1 Channel enabled
0 Channel disabled
CH_IN_EN4
1 Channel enabled
0 Channel disabled
CH_IN_EN3
1 Channel enabled
0 Channel disabled
CH_IN_EN2
1 Channel enabled
0 Channel disabled
1 Channel 1 is always enabled.
CH_IN_EN1
0 Channel 0 is always enabled.
CH_IN_EN0
33.5.271 Audio DMA Buffer Interrupt Status Register

(HDMI_AHB_DMA_BUFFSTAT)

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read buff_full buff_empty

Reserved
Write
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_BUFFSTAT field descriptions

Field Description
- Reserved
1 Buffer full flag status
buff_full

HDMI_AHB_DMA_BUFFSTAT field descriptions (continued)

Field Description
0 Buffer empty flag status
buff_empty
33.5.272 Audio DMA Buffer Interrupt Register

(HDMI_AHB_DMA_BUFFINT)

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
int_buff_
Read int_buff_full
Reserved empty
Write
Reset 0 0 0 0 0 0 0 0
HDMI_AHB_DMA_BUFFINT field descriptions

Field Description
- Reserved
1 Buffer full flag interrupt
int_buff_full
0 Buffer empty flag interrupt
int_buff_empty

33.5.273 Audio DMA Buffer Mask Interrupt Register

(HDMI_AHB_DMA_BUFFMASK)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read int_buff_
Reserved int_buff_full
Write empty
Reset 0 0 0 1 0 0 0 1
HDMI_AHB_DMA_BUFFMASK field descriptions

Field Description
- Reserved
1 Buffer full flag mask
int_buff_full
0 Buffer empty flag mask
int_buff_empty
33.5.274 Audio DMA Buffer Polarity Interrupt Register

(HDMI_AHB_DMA_BUFFPOL)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read int_buff_
Reserved int_buff_full
Write empty
Reset 0 0 0 1 0 0 0 1

HDMI_AHB_DMA_BUFFPOL field descriptions

Field Description
- Reserved
1 Buffer full flag polarity
int_buff_full
0 Buffer empty flag polarity
int_buff_empty
33.5.275 Main Controller Synchronous Clock Domain Disable

Register (HDMI_MC_CLKDIS)
Main controller synchronous disable control per clock domain. Upon release of
synchronous disable the corresponding sw reset NRZ request signal, to that domain, is
toggled asking to the output for a synchronized active low reset to be generated to that
domain.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read cecclk_ cscclk_ audclk_ prepclk_ tmdsclk_ pixelclk_
Reserved Reserved
Write disable disable disable disable disable disable
Reset 0 0 0 0 0 0 0 0
HDMI_MC_CLKDIS field descriptions

Field Description
- Reserved
hdcpclk_disable Reserved
5 CEC Engine clock synchronous disable signal.
cecclk_disable
4 Color Space Converter clock synchronous disable signal.
cscclk_disable
3 Audio Sampler clock synchronous disable signal.
audclk_disable
2 Pixel Repetition clock synchronous disable signal.
prepclk_disable

HDMI_MC_CLKDIS field descriptions (continued)

Field Description
1 TMDS clock synchronous disable signal.
tmdsclk_disable
0 Pixel clock synchronous disable signal.
pixelclk_disable
33.5.276 Main Controller Software Reset Register

(HDMI_MC_SWRSTZREQ)
Main controller software reset request per clock domain. Writing zero to a bit of this
register results in an NRZ signal toggle at sfrclk rate to an output signal that indicates a
software reset request. This toggle must be used to generate a synchronized reset to de
corresponding domain, with at least 1 clock cycle. Register defaults back to 0xFF.
• Size: 8 bits
Bit 7 6 5 4
Read Reserved cecswrst_req Reserved
Write
Reset 1 1 1 1
Bit 3 2 1 0
Read Reserved prepswrst_req tmdsswrst_req pixelswrst_req
Write
Reset 1 1 1 1
HDMI_MC_SWRSTZREQ field descriptions

Field Description
- Reserved
6 CEC software reset request. Defaults back to 1b after reset request.
cecswrst_req
- Reserved
2 Pixel Repetition clock synchronous disable signal.
prepswrst_req
1 TMDS software reset request. Defaults back to 1b after reset request.
tmdsswrst_req
0 Pixel software reset request. Defaults back to 1b after reset request.
pixelswrst_req

33.5.277 Main Controller Feed Through Control Register

(HDMI_MC_FLOWCTRL)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Feed_
Reserved
Write through_off
Reset 0 0 0 0 0 0 0 0
HDMI_MC_FLOWCTRL field descriptions

Field Description
- Reserved
0 Video path Feed Through enable bit:
Feed_through_off
1 Color Space Converter is in the video data path.
0 Color Space Converter is bypassed (not in the video data path).
33.5.278 Main Controller PHY Reset Register

(HDMI_MC_PHYRSTZ)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved phyrstz
Write
Reset 0 0 0 0 0 0 0 0

HDMI_MC_PHYRSTZ field descriptions

Field Description
- Reserved
0 HDMI Source PHY active low reset control.
phyrstz
33.5.279 Main Controller Clock Present Register

(HDMI_MC_LOCKONCLOCK)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read pclk tclktclk prepclk cecclk

Reserved Reserved
Reset 0 0 0 0 0 0 0 0
HDMI_MC_LOCKONCLOCK field descriptions

Field Description
- Reserved.
6 Pixel clock status. Indicates that the clock is present in the system. Cleared by WR 1 to this position.
pclk
5 TMDS clock status. Indicates that the clock is present in the system. Cleared by WR 1 to this position
tclktclk
4 Pixel repetition clock status. Indicates that the clock is present in the system. Cleared by WR 1 to this
prepclk position.
- Reserved.
0 CEC clock status. Indicates that the clock is present in the system. Cleared by WR 1 to this position.
cecclk

33.5.280 Main Controller HEAC PHY Reset Register

(HDMI_MC_HEACPHY_RST)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read
Reserved heacphyrst
Write
Reset 0 0 0 0 0 0 0 0
HDMI_MC_HEACPHY_RST field descriptions

Field Description
- Reserved
0 HEAC PHY reset (active high)
heacphyrst
33.5.281 Color Space Converter Interpolation and Decimation

Configuration Register (HDMI_CSC_CFG)
Color Space Conversion configuration register. Configures YCC422 to YCC444
interpolation mode and YCC444 to YCC422 decimation mode.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved INTMODE Reserved DECMODE
Write
Reset 0 0 0 0 0 0 0 0

HDMI_CSC_CFG field descriptions

Field Description
- Reserved
5–4 Chroma interpolation configuration:
INTMODE
00 interpolation disabled
01 H u (z) = 1 + z -1
10 H u (z)=1/2 + Z -1 +1/2 z -2
11 interpolation disabled.
- Reserved
DECMODE Chroma decimation configuration: DECMODE[1:0] Chroma decimation 00 decimation disabled 01 H d? z?
=1 10 H d? z?=1/ 4?1/ 2 z?1?1/4 z?2 11 H d? z?Þ211=?5?12 z?2?22 z?4?39 z?6?65 z?8?109 z?10?204
z?12?648 z?14?1024 z?15?648 z?16?204 z?18?109 z?20?65 z?22?39 z?24?22 z?26?12 z?28?5 z?30
00 decimation disabled
01 H d (z) = 1
10 H d (Z)=1/4 + 1/2z -1 1+1/4z -2
11H d (z)x2 11 =-5+12z -2 +22z -4 +39z -8 +109z -10 -204z -12 +648z -14 +1024z -15 +648z -16 -204z -18
+109z -20 -65z -22 +39z -24 -22z -26 +12z -28 -5z -30
33.5.282 Color Space Converter Scale and Deep Color

Configuration Register (HDMI_CSC_SCALE)
• Size: 8 bits
G A1 A2 A3 A4
R = 2 csc scale - 12 x B1 B2 B3 + 2 csc scale x B4
B C1 C2 C3 C4
Y A1 A2 A3 A4
Cb = 2 cscscale - 12 x B1 B2 B3 + 2 cscscale x B4
Cr C1 C2 C3 C4
Figure 33-17. CSC Conversion Functions

Bit 7 6 5 4 3 2 1 0
Read csc_colorde_pth[3:0] Reserved -
Write
Reset 0 0 0 0 0 0 0 1
HDMI_CSC_SCALE field descriptions

Field Description
7–4 Color space converter color depth configuration:
csc_colorde_
Other: Reserved.
pth[3:0]
0000 24 bit per pixel video (8 bit per component).
- Reserved
- Defines the cscscale[1:0] scale factor to apply to all coefficients in Color Space Conversion. This scale
factor is expressed in the number of left shifts to apply to each of the coefficients, ranging from 0 to 2.
33.5.283 CSC_COEF_A1_MSB (HDMI_CSC_COEF_A1_MSB)

Color Space Conversion A1 coefficient.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read CSC_COEF_A1_MSB
Write
Reset 0 0 1 0 0 0 0 0
HDMI_CSC_COEF_A1_MSB field descriptions

Field Description
CSC_COEF_A1_ Color Space Conversion A1 MSB coefficient.
MSB
33.5.284 CSC_COEF_A1_LSB (HDMI_CSC_COEF_A1_LSB)



• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read CSC_COEF_A1_LSB
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CSC_COEF_A1_LSB field descriptions

Field Description
CSC_COEF_A1_ Color Space Conversion A1 LSB coefficient
LSB

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
MSB

• Size: 8 bits


Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
CSC_COEF_A2_ Color Space Conversion A2 LSB coefficient.
LSB

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
MSB

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
LSB

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
MSB

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
LSB
33.5.291 CSC_COEF_B1_MSB (HDMI_CSC_COEF_B1_MSB)

Color Space Conversion B1 coefficient.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read CSC_COEF_B1_MSB
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CSC_COEF_B1_MSB field descriptions

Field Description
CSC_COEF_B1_ Color Space Conversion B1 MSB coefficient.
MSB
33.5.292 CSC_COEF_B1_LSB (HDMI_CSC_COEF_B1_LSB)

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Read CSC_COEF_B1_LSB
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CSC_COEF_B1_LSB field descriptions

Field Description
CSC_COEF_B1_ Color Space Conversion B1 LSB coefficient.
LSB

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 1 0 0 0 0 0

Field Description
MSB

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
LSB

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
MSB

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
LSB

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
MSB

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
LSB
33.5.299 CSC_COEF_C1_MSB (HDMI_CSC_COEF_C1_MSB)

Color Space Conversion C1 coefficient.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read CSC_COEF_C1_MSB
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CSC_COEF_C1_MSB field descriptions

Field Description
CSC_COEF_C1_ Color Space Conversion C1 MSB coefficient.
MSB
33.5.300 CSC_COEF_C1_LSB (HDMI_CSC_COEF_C1_LSB)

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Read CSC_COEF_C1_LSB
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CSC_COEF_C1_LSB field descriptions

Field Description
CSC_COEF_C1_ Color Space Conversion C1 LSB coefficient.
LSB

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
MSB

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
LSB

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 1 0 0 0 0 0

Field Description
MSB

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0

Field Description
LSB
33.5.305 CSC_COEFC4_MSB (HDMI_CSC_COEFC4_MSB)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read CSC_COEFC4_MSB
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CSC_COEFC4_MSB field descriptions

Field Description
CSC_COEFC4_ Color Space Conversion C4 MSB coefficient.
MSB
33.5.306 CSC_COEFC4_LSB (HDMI_CSC_COEFC4_LSB)

• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Read CSC_COEFC4_LSB
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CSC_COEFC4_LSB field descriptions

Field Description
CSC_COEFC4_ Color Space Conversion C4 LSB coefficient.
LSB
33.5.307 CEC_CTRL (HDMI_CEC_CTRL)

CEC registers control the CEC feature that is implemented in HDMI TX. They perform
various functions like controlling, monitoring, and buffering data for the transmitter and
the receiver.
This register handles the main control of the CEC initiator.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved STANDBY BC_NACK FRAME_TYP SEND
Write
Reset 0 0 0 0 0 0 1 0
HDMI_CEC_CTRL field descriptions

Field Description
- Reserved
4 Standby bit
STANDBY
0 CEC controller responds the ACK to all messages.
1 CEC controller responds with ACK to all ping messages (only when the EOM is received) and
responds with NACK to all other messages, generating wake-up status for selected opcodes.
Attention that the NACK will only be posted on the last block of a frame.
3 Broadcast NACK bit
BC_NACK
0 Reset by software to ACK the received broadcast message.
1 Set by software to NACK the received broadcast message. This bit holds till software resets. The
broadcasts will be answered with 1'b0. It means the follower reject the message.

HDMI_CEC_CTRL field descriptions (continued)

Field Description
2–1 Frame Type bit
FRAME_TYP
00 Signal Free Time = 3-bit periods. Previous attempt to send frame is unsuccessful.
01 Signal Free Time = 5-bit periods. New initiator wants to send a frame.
10 Signal Free Time = 7-bit periods. Present initiator wants to send another frame immediately after its
previous frame. (spec CEC 9.1)
11 Illegal value. If software write this value, hardware will set the value to the default 2'b01.
0 Send bit
SEND
0 Reset to 0 by hardware when the CEC transmission is done (no matter successful or failed). It can
also work as an indicator checked by software to see whether the transmission is finished.
1 Set by software to trigger CEC sending a frame as an initiator. This bit keeps at 1 while the
transmission is going on.
33.5.308 CEC_STAT (HDMI_CEC_STAT)

This register indicates the status of CEC line. All bits are read only. When an event
occurs, the corresponding bit will set to 1 for one SFR clock cycle only. Then, the bit
automatically resets to 0. No software reset is required. Software can read the "stable"
interrupts on IH_CEC_STAT0 register (this register has the same bit arrangement as
CEC_STAT register).
• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
ERROR_ ERROR_
Read WAKEUP ARB_LOST NACK EOM DONE
Reserved FOLL INIT
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CEC_STAT field descriptions

Field Description
- Reserved
6 Follower received wake-up command (for follower only).
WAKEUP
5 An error is notified by a follower. Abnormal logic data bit error (for follower).
ERROR_FOLL

HDMI_CEC_STAT field descriptions (continued)

Field Description
4 An error is detected on cec line (for initiator only).
ERROR_INIT
3 The initiator losses the CEC line arbitration to a second initiator. (specification CEC 9).
ARB_LOST
2 A frame is not acknowledged in a directly addressed message. Or a frame is negatively acknowledged in
NACK a broadcast message (for initiator only).
1 EOM is detected so that the received data is ready in the receiver data buffer (for follower only).
EOM
0 The current transmission is successful (for initiator only).
DONE
33.5.309 CEC_MASK (HDMI_CEC_MASK)

This read/write register masks/unmasks the interrupt events. When the bit is set to 1
(masked), the corresponding event will not trigger an interrupt signal at the system
interface. When the bit is reset to 0, the interrupt event is unmasked.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read ERROR_ ARB_
WAKEUP_ ERROR_ NACK_ DONE_
Reserved FOLL_ LOST_ EOM_MASK
Write MASK INIT_MASK MASK MASK
MASK MASK
Reset 0 0 0 0 0 0 0 0
HDMI_CEC_MASK field descriptions

Field Description
- Reserved
6 Follower wake-up signal mask
WAKEUP_MASK
5 An error is notified by a follower. Abnormal logic data bit error (for follower).
ERROR_FOLL_
MASK
4 An error is detected on cec line (for initiator only).
ERROR_INIT_
MASK

HDMI_CEC_MASK field descriptions (continued)

Field Description
3 The initiator losses the CEC line arbitration to a second initiator. (specification CEC 9).
ARB_LOST_
MASK
2 A frame is not acknowledged in a directly addressed message. Or a frame is negatively acknowledged in
NACK_MASK a broadcast message (for initiator only).
1 EOM is detected so that the received data is ready in the receiver data buffer (for follower only).
EOM_MASK
0 The current transmission is successful (for initiator only).
DONE_MASK
33.5.310 CEC_POLARITY (HDMI_CEC_POLARITY)

This register is readable and writable, which controls the polarity of the interrupt status
register as well as the polarity of the interrupt signals at system interface.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read WAKEUP_ ERROR_ ERROR_ ARB_
Reserved NACK_POL EOM_POL DONE_POL
Write POL FOLL_POL INIT_POL LOST_POL
Reset 0 1 1 1 1 1 1 1
HDMI_CEC_POLARITY field descriptions

Field Description
- Reserved
6 Follower wakeup signal polarity
WAKEUP_POL
5 CEC line error polarity (for follower only)
ERROR_FOLL_
POL
4 CEC line error polarity (for initiator only)
ERROR_INIT_
POL
3 Initiator Arbitration lost signal polarity
ARB_LOST_POL
2 Frame NACK signal polarity
NACK_POL

HDMI_CEC_POLARITY field descriptions (continued)

Field Description
1 EOM detect signal polarity (follower only)
EOM_POL
0 Current transmission success or not signal polarity
DONE_POL
33.5.311 CEC_INT (HDMI_CEC_INT)

This register is read only. Each bit of the register is output at the system interface. The
output signals hold the active interrupt state (high or low) for only one SFR clock cycle.
Then the hardware resets the bit to an inactive state. Software can read the "stable"
interrupts on the IH_CEC_STAT0 register at address 0x0106 (this register has the same
bit arrangement as the CEC_STAT register).
The functional formula for the interrupts is:
CEC_INT = (CEC_MASK == 0b) && (CEC_STATUS == CEC_POLARITY)
• Size: 8 bits
• Access: Read
Bit 7 6 5 4
Read WAKEUP_INT ERROR_FOLL_INT ERROR_INIT_INT

Reserved
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read ARB_LOST_INT NACK_INT EOM_INT DONE_INT
Write
Reset 0 0 0 0
HDMI_CEC_INT field descriptions

Field Description
- Reserved
6 Follower wakeup signal polarity
WAKEUP_INT

HDMI_CEC_INT field descriptions (continued)

Field Description
5 Follower wakeup interrupt
ERROR_FOLL_
INT
4 CEC line error interrupt (for follower only)
ERROR_INIT_
INT
3 CEC line error interrupt (for initiator only)
ARB_LOST_INT
2 Initiator Arbitration lost interrupt
NACK_INT
1 Frame NACK interrupt
EOM_INT
0 EOM detect interrupt (for follower only)
DONE_INT
33.5.312 CEC_ADDR_L (HDMI_CEC_ADDR_L)

CEC_ADDR_L and CEC_ADDR_H registers indicate the logical address(es) allocated to
the CEC device. The logical address mappings are shown in CEC_ADDR_L
(HDMI_CEC_ADDR_L) and CEC_ADDR_H (HDMI_CEC_ADDR_H) . This register is
written by software when the logical allocation is finished. Bit value 1 means the
corresponding logical address is allocated to this device. Bit value 0 means the
corresponding logical address is not allocated to this device.
• Size: 8 bits
Bit 7 6 5 4
Read CEC_ADDR_L7 CEC_ADDR_L6 CEC_ADDR_L5 CEC_ADDR_L4
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read CEC_ADDR_L3 CEC_ADDR_L2 CEC_ADDR_L1 CEC_ADDR_L0
Write
Reset 0 0 0 0

HDMI_CEC_ADDR_L field descriptions

Field Description
7 Logical address 7 - Tuner 3
CEC_ADDR_L7
CEC_ADDR_L6
5 Logical address 5 - Audio System
CEC_ADDR_L5
4 Logical address 4 - Playback Device 1
CEC_ADDR_L4
CEC_ADDR_L3
2 Logical address 2 - Recording Device 2
CEC_ADDR_L2
1 Logical address 1 - Recording Device 1
CEC_ADDR_L1
0 Logical address 0 - Device TV
CEC_ADDR_L0
33.5.313 CEC_ADDR_H (HDMI_CEC_ADDR_H)

CEC_ADDR_L and CEC_ADDR_H registers indicate the logical address(es) allocated to
the CEC device. The logical address mappings are shown in CEC_ADDR_L
(HDMI_CEC_ADDR_L) and CEC_ADDR_H (HDMI_CEC_ADDR_H) . This register is
written by software when the logical allocation is finished. Bit value 1 means the
corresponding logical address is allocated to this device. Bit value 0 means the
corresponding logical address is not allocated to this device.
• Size: 8 bits
Bit 7 6 5 4
Read CEC_ADDR_H7 CEC_ADDR_H6 CEC_ADDR_H5 CEC_ADDR_H4
Write
Reset 1 0 0 0
Bit 3 2 1 0
Read CEC_ADDR_H3 CCEC_ADDR_H2 CEC_ADDR_H1 CEC_ADDR_H0
Write
Reset 0 0 0 0

HDMI_CEC_ADDR_H field descriptions

Field Description
7 Logical address 15 - Unregistered (as initiator address), Broadcast (as destination address)
CEC_ADDR_H7
6 Logical address 14 - Free use
CEC_ADDR_H6
5 Logical address 13 - Reserved
CEC_ADDR_H5
4 Logical address 12 - Reserved
CEC_ADDR_H4
CEC_ADDR_H3
CCEC_ADDR_
H2
CEC_ADDR_H1
CEC_ADDR_H0
33.5.314 CEC_TX_CNT (HDMI_CEC_TX_CNT)

This register indicates the size of the frame in bytes (including header and data blocks),
which are available in the transmitter data buffer.
When the value is zero, the CEC controller ignores the send command triggered by
software. When the transmission is done (no matter success or not), the current value is
held until it is overwritten by software.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved CEC_TX_CNT
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CEC_TX_CNT field descriptions

Field Description
- Reserved

HDMI_CEC_TX_CNT field descriptions (continued)

Field Description
CEC_TX_CNT CEC Transmitter Counter register:
Value after Reset: 5'b00000
0 No data needs to be transmitted.

1 Frame size is 1 byte.
16 Frame size is 16 byte.
33.5.315 CEC_RX_CNT (HDMI_CEC_RX_CNT)

This register indicates the size of the frame in bytes (including header and data blocks),
which are available in the receiver data buffer.
Only after the whole receiving process is finished successfully, the counter is refreshed to
the value which indicates the total number of data bytes in the Receiver Data Register.
• Address Offset: 0x7d08
• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read - CEC_RX_CNT
Write -
Reset 0 0 0 0 0 0 0 0
HDMI_CEC_RX_CNT field descriptions

Field Description
7–5
-
CEC_RX_CNT CEC Receiver Counter register.
Value after Reset: 5‘b00000
0 No data received
1 1-byte data is received.
16 16-byte data is received.

33.5.316 CEC_TX_DATA (HDMI_CEC_TX_DATAn)

These registers (8 bit each) are the buffers used for storing the data waiting for
transmission(including header and data blocks).
• Address Offset: 0x7D10 .. 0x7D1F
• Size: 8 bits
• Access: Read
Address: 12_0000h base + 7D10h offset + (1d × i), where i=0d to 15d
Bit 7 6 5 4 3 2 1 0
Read CEC_TX_DATA
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CEC_TX_DATAn field descriptions

Field Description
CEC_TX_DATA Header block in CEC_TX_DATA0
Data blockn in CEC_TX_DATAn
33.5.317 CEC_RX_DATA (HDMI_CEC_RX_DATAn)

These registers (8 bit each) are the buffers used for storing the received data (including
header and data blocks).
• Address Offset: 0x7D20 .. 0x7D2F
• Size: 8 bits
• Access: Read
Address: 12_0000h base + 7D20h offset + (1d × i), where i=0d to 15d
Bit 7 6 5 4 3 2 1 0
Read CEC_RX_DATA
Write
Reset 0 0 0 0 0 0 0 0
HDMI_CEC_RX_DATAn field descriptions

Field Description
CEC_RX_DATA Header block in CEC_RX_DATA0
Data blockn in CEC_RX_DATAn

33.5.318 CEC_LOCK (HDMI_CEC_LOCK)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read LOCKED_
Reserved
Write BUFFER
Reset 0 0 0 0 0 0 0 0
HDMI_CEC_LOCK field descriptions

Field Description
- Reserved
0 When a frame is received, this bit would be active. The CEC controller answers to all the messages with
LOCKED_ NACK until the CPU writes it to '0'.
BUFFER
33.5.319 CEC_WKUPCTRL (HDMI_CEC_WKUPCTRL)

• Size: 8 bits
After receiving a message in the CEC_RX_DATA1 (OPCODE) registers, the CEC
engine verifies the message opcode[7:0] against one of the previously defined values to
generate the wake-up status:
Wakeupstatus is 1 when:
received opcode is 0x04 and opcode0x04en is 1 or received opcode is 0x0D and
opcode0x0Den is 1 or received opcode is 0x41 and opcode0x41en is 1 or received
opcode is 0x42 and opcode0x42en is 1 or received opcode is 0x44 and opcode0x44en is 1
or received opcode is 0x70 and opcode0x70en is 1 or received opcode is 0x82 and
opcode0x82en is 1 or received opcode is 0x86 and opcode0x86en is 1
Wakeupstatus is 0 when none of the previous conditions are true.

This formula means that the wake-up status (on CEC_STAT[6] register) is only '1' if the
opcode[7:0] received is equal to one of the defined values and the corresponding enable
bit of that defined value is set to '1'.
Bit 7 6 5 4
Read OPCODE0x86en OPCODE0x82en OPCODE0x70en OPCODE0x44en
Write
Reset 1 1 1 1
Bit 3 2 1 0
Read OPCODE0x42en OPCODE0x41en OPCODE0x0Den OPCODE0x04en
Write
Reset 1 1 1 1
HDMI_CEC_WKUPCTRL field descriptions

Field Description
7 OPCODE 0x86 wake up enable
OPCODE0x86en
OPCODE0x82en
OPCODE0x70en
OPCODE0x44en
OPCODE0x42en
OPCODE0x41en
1 OPCODE 0x0D wake up enable
OPCODE0x0Den
OPCODE0x04en
33.5.320 I2CM_SLAVE (HDMI_I2CM_SLAVE)

I2C Master Registers (E-DDC) registers are responsible for the Master's coordination
with the Slave, by coordinating the Slave address, data identification, transaction status,
acknowledgement, and reset functions.
• Size: 8 bits

Bit 7 6 5 4 3 2 1 0
Read Reserved slaveaddr[6:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_I2CM_SLAVE field descriptions

Field Description
- Reserved
slaveaddr[6:0] Slave address to be sent during read and write normal operations.
33.5.321 I2CM_ADDRESS (HDMI_I2CM_ADDRESS)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read address[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_I2CM_ADDRESS field descriptions

Field Description
address[7:0] Register address for read and write operations.
33.5.322 I2CM_DATAO (HDMI_I2CM_DATAO)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read datao[7:0]
Write
Reset 0 0 0 0 0 0 0 0

HDMI_I2CM_DATAO field descriptions

Field Description
datao[7:0] Data to be written on register pointed by address[7:0].
33.5.323 I2CM_DATAI (HDMI_I2CM_DATAI)

• Size: 8 bits
• Access: Read
Bit 7 6 5 4 3 2 1 0
Read datai[7:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_I2CM_DATAI field descriptions

Field Description
datai[7:0] Data read from register pointed by address[7:0].
33.5.324 I2CM_OPERATION (HDMI_I2CM_OPERATION)

Read and write operation request. This register can only be written, reading this register
will always result in 00h. Writing 1'b1 simultaneously to rd, rd_ext and wr requests is
considered as a read (rd) request.
• Size: 8 bits
• Access: Write
Bit 7 6 5 4 3 2 1 0
Read
Reserved Reserved
Write wr rd_ext rd
Reset 0 0 0 0 0 0 0 0

HDMI_I2CM_OPERATION field descriptions

Field Description
- Reserved
4 Write operation request.
wr
- Reserved
1 After writing 1'b1 to rd_ext bit a extended data read operation is started (E- DDC read operation).
rd_ext
0 Read operation request.
rd
33.5.325 I2CM_INT (HDMI_I2CM_INT)

This register contains and configures I2C master done interrupt.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read done_
Reserved done_pol done_mask done_status
Write interrupt
Reset 0 0 0 0 1 0 0 0
HDMI_I2CM_INT field descriptions

Field Description
- Reserved
3 Done interrupt polarity configuration.
done_pol
2 Done interrupt mask signal.
done_mask
1 Operation done interrupt bit. Only lasts for 1 SFR clock cycle and is auto cleaned after it.
done_interrupt
{done_interrupt = (done_mask==0b) && (done_status==done_pol)}.
0 Operation done status bit. Marks the end of a rd or write operation.
done_status

33.5.326 I2CM_CTLINT (HDMI_I2CM_CTLINT)

This register contains and configures I2C master arbitration error and not acknowledge
error interrupt.
• Size: 8 bits
Bit 7 6 5 4
Read nack_pol nack_mask nack_interrupt nack_status
Write
Reset 1 0 0 0
Bit 3 2 1 0
Read arbitration_pol arbitration_mask arbitration_interrupt arbitration_status
Write
Reset 1 0 0 0
HDMI_I2CM_CTLINT field descriptions

Field Description
7 Not acknowledge error interrupt polarity configuration.
nack_pol
6 Not acknowledge error interrupt mask signal.
nack_mask
5 Not acknowledge error interrupt bit. Only lasts for 1 SFR clock cycle and is auto cleaned after it.
nack_interrupt
{nack_interrupt = (nack_mask==0b) && (nack_status==nack_pol)}.
4 Not acknowledge error status bit. Error on I2C not acknowledge.
nack_status
3 Arbitration error interrupt polarity configuration.
arbitration_pol
2 Arbitration error interrupt mask signal.
arbitration_mask
1 Arbitration error interrupt bit. Only lasts for 1 SFR clock cycle and is auto cleaned after it.
arbitration_ {arbitration_interrupt = (arbitration_mask==0b) && (arbitration_status==arbitration_pol)}.
interrupt
0 Arbitration error status bit. Error on master I2C protocol arbitration.
arbitration_status
33.5.327 I2CM_DIV (HDMI_I2CM_DIV)

This register configures the division relation between master and scl clock.


• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read fast_std_
Reserved Reserved
Write mode
Reset 0 0 0 0 1 0 1 1
HDMI_I2CM_DIV field descriptions

Field Description
- Reserved
3 Sets the I2C Master to work in Fast Mode or Standard Mode:
fast_std_mode
1 Fast Mode
0 Standard Mode
Reserved
33.5.328 I2CM_SEGADDR (HDMI_I2CM_SEGADDR)

This register configures the segment address for extended RD/WR destination.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved SEGADDR
Write
Reset 0 0 0 0 0 0 0 0
HDMI_I2CM_SEGADDR field descriptions

Field Description
- Reserved
SEGADDR E-DDC Extended read segment address

33.5.329 I2CM_SOFTRSTZ (HDMI_I2CM_SOFTRSTZ)

This register resets the I2C master.
• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Read Reserved i2c_softrst
Write
Reset 0 0 0 0 0 0 0 1
HDMI_I2CM_SOFTRSTZ field descriptions

Field Description
- Reserved
0 I2C Master Software Reset. Active by writing a zero and auto cleared to one in the following cycle.
i2c_softrst
33.5.330 I2CM_SEGPTR (HDMI_I2CM_SEGPTR)

This register configures the segment pointer for extended RD/WR request.
• Address Offset: 0x7E0A
• Size: 8 bits
The following *CNT registers must be set before any I2C bus transaction can take place
to ensure proper I/O timing.
Address: 12_0000h base + 7E0Ah offset = 12_7E0Ah
Bit 7 6 5 4 3 2 1 0
Read I2CM_SEGPTR
Write
Reset 0 0 0 0 0 0 0 0

HDMI_I2CM_SEGPTR field descriptions

Field Description
I2CM_SEGPTR I2CM_SEGPTR is used for EDID reading operations, particularly for the Extended Data Read Operation
(See I2C Master Interface Extended Read Mode ") which is used for Enhanced DDC. This is all described
in the VESA Enhanced Display Data Channel Standard v1.1 spec. (addresses A0h/A1h pairs and a
segment pointer - 60h).
33.5.331 I2CM_SS_SCL_HCNT_1_ADDR
(HDMI_I2CM_SS_SCL_HCNT_1_ADDR)
• Address Offset: 0x7E0B

• Size: 8 bits
Address: 12_0000h base + 7E0Bh offset = 12_7E0Bh
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_I2CM_SS_SCL_HCNT_1_ADDR field descriptions

Field Description
hcnt[15:8]
33.5.332 I2CM_SS_SCL_HCNT_0_ADDR
(HDMI_I2CM_SS_SCL_HCNT_0_ADDR)
• Address Offset: 0x7E0C

• Size: 8 bits
• Value after Reset: 0x6C
Address: 12_0000h base + 7E0Ch offset = 12_7E0Ch
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 1 1 0 1 1 0 0

HDMI_I2CM_SS_SCL_HCNT_0_ADDR field descriptions

Field Description
i2cmp_ss_scl_ Value after Reset: 8'h6C
hcnt[7:0]
33.5.333 I2CM_SS_SCL_LCNT_1_ADDR
(HDMI_I2CM_SS_SCL_LCNT_1_ADDR)
• Address Offset: 0x7E0D

• Size: 8 bits
Address: 12_0000h base + 7E0Dh offset = 12_7E0Dh
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_I2CM_SS_SCL_LCNT_1_ADDR field descriptions

Field Description
lcnt[15:8]
33.5.334 I2CM_SS_SCL_LCNT_0_ADDR
(HDMI_I2CM_SS_SCL_LCNT_0_ADDR)
• Address Offset: 0x7E0E

• Size: 8 bits
Address: 12_0000h base + 7E0Eh offset = 12_7E0Eh
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 1 1 1 1 1 1 1

HDMI_I2CM_SS_SCL_LCNT_0_ADDR field descriptions

Field Description
i2cmp_ss_scl_ Value after Reset: 8'h7F
lcnt[7:0]
33.5.335 I2CM_FS_SCL_HCNT_1_ADDR
(HDMI_I2CM_FS_SCL_HCNT_1_ADDR)
• Address Offset: 0x7E0F

• Size: 8 bits
Address: 12_0000h base + 7E0Fh offset = 12_7E0Fh
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_I2CM_FS_SCL_HCNT_1_ADDR field descriptions

Field Description
hcnt[15:8]
33.5.336 I2CM_FS_SCL_HCNT_0_ADDR
(HDMI_I2CM_FS_SCL_HCNT_0_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 1 0 0 0 1

HDMI_I2CM_FS_SCL_HCNT_0_ADDR field descriptions

Field Description
hcnt[7:0]
33.5.337 I2CM_FS_SCL_LCNT_1_ADDR
(HDMI_I2CM_FS_SCL_LCNT_1_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0
HDMI_I2CM_FS_SCL_LCNT_1_ADDR field descriptions

Field Description
lcnt[15:8]
33.5.338 I2CM_FS_SCL_LCNT_0_ADDR
(HDMI_I2CM_FS_SCL_LCNT_0_ADDR)

• Size: 8 bits
Bit 7 6 5 4 3 2 1 0
Write
Reset 0 0 1 0 0 1 0 0

HDMI_I2CM_FS_SCL_LCNT_0_ADDR field descriptions

Field Description
lcnt[7:0]
33.5.339 BASE_POINTER_ADDR (HDMI_BASE_POINTER_ADDR)

The I2C Slave Registers allow register memory pagination, and function in the
incremental burst operation mode that increases the data throughput when consecutive
addressed registers need to be read or write.
The I2C base pointer operation mode is a aimed to allow register memory pagination. As
long as this operational mode is enabled the value written to this register will be used as
the seven most significant bits of the internal Special Function Register address interface
(sfraddr[14:8]) for all read or write operations. I2C data transfer protocol used shall be
the 7-bit addressed as defined in the section 9 of the I2C-bus Specification, version 2.1.
• Address Offset: 0x7F00
• Size: 8 bits
Address: 12_0000h base + 7F00h offset = 12_7F00h
Bit 7 6 5 4 3 2 1 0
Read en_base_
base_pointer_base_addr[6:0]
Write pointer_addr
Reset 0 0 0 0 0 0 0 0
HDMI_BASE_POINTER_ADDR field descriptions

Field Description
7 Enables the base pointer operation mode.
en_base_
pointer_addr
base_pointer_ Defines the base address for base pointer operation mode. They represent the address bits [14:8]
base_addr[6:0]


Chapter 34
HDMI 3D Tx PHY (HDMI_PHY)
34.1 Overview
34.1.1 General Description

The HDMI 3D Tx PHY (HDMI_PHY) is the physical layer of a single-link HDMI
transmitter interface and comprises three line drivers for data transmission and an
additional line driver for clock transmission. The HDMI_PHY is designed to perform the
serialization and transmission of video data and control information through an HDMI
interface. It interfaces with an HDMI Tx link controller through a common graphic
controller interface supporting 30- or 60-bit data transfers. A clock line driver is used for
reference clock transmission.
34.1.2 Applications
The HDMI_PHY is targeted to digital video/audio transmission for high resolution
display applications, supporting major display formats up to 1080 i/p in DTV
applications and QXGA in graphic display applications, with true-color or deep-color
resolutions. The HDMI_PHY supports 3D video formats. At maximum pixel rate, the
HDMI channel bit rate is 3.4 Gbps, providing a maximum throughput of 9.2 Gbps.
The HDMI_PHY is an ideal solution for implementing the physical layer of a high-
reliability digital video/audio interface based on HDMI technology, with reduced line
count and minimum cable-wire and EMI shielding requirements. The HDMI_PHY
delivers the bandwidth needed in every time mode that demands high resolution panels,
while keeping clock sources at a low frequency.
The figure below shows a typical application for HDMI_PHY.

Overview
DVD Player Plasma TV, LCD TV,

High-End CRT,LCD Monitor
HDMI 1.4 Tx HDMI 3D Tx PHY

Link Layer Layer
HDMI 1.4 Rx PHY + Link Layer
Figure 34-1. Typical Application for HDMI 3D Tx PHY
34.1.3 Standards Compliance

The HDMI_PHY is fully compliant with all the required specifications of the following
standards:
• High-Definition Multimedia Interface Specification, Version 1.4a
• Digital Visual Interface, Revision 1.0
• HDMI Compliance Test Specification, Version 1.4a
34.1.4 Features
The HDMI_PHY provides the following features:
• Support for up to 720p at 100 Hz and 720i at 200 Hz or 1080p at 60 Hz and 1080i/
720i at 120 Hz HDTV display resolutions and up to QXGA graphic display
resolutions
• Support for 3D video formats
• Link controller flexible interface with 30- or 60-bit SDR data access
• Up to 9.2 Gbps aggregate bandwidth
• Driver with pre-emphasis and edge rate control for extra-long cable support
• Programmable source terminations
• HPD input analog comparator
• Rx sensing
• 13.5-266 MHz input reference clock

Chapter 34 HDMI 3D Tx PHY (HDMI_PHY)
• 50% duty-cycle output clock

• Embedded Tx scope
• Embedded A/D converter and analog testbus for ATE testing
• Built-in pattern generator
• Small core area
• Low power consumption
34.1.5 HDMI 3D Tx PHY System-Level Overview

This section provides a system-level overview of the HDMI 3D Tx PHY.
34.1.5.1 System-Level Block Diagram

The figure below shows a system-level block diagram of the HDMI Tx System.
ASIC SOC
Control I/O HDMI video, audio, CEC

HDMI 3D
Tx PHY HDMI 1.4
SoC Logic HDMI 1.4 Tx Data HDMI Sink
Link Controller
Figure 34-2. HDMI Tx System-Level Block Diagram
The HDMI_PHY macro interfaces with the HDMI Tx link controller, which provides
control signals and video data to be transmitted through the TMDS lanes. Analog I/O's
interface with the external world.

Overview
34.1.5.2 HDMI 3D Tx PHY

The HDMI 3D Tx PHY is the physical layer of an HDMI/DVI-compliant digital
transmitter (source).
For a functional block diagram and a functional description of the HDMI 3D Tx PHY,
see Functional Description.
34.1.5.2.1 Interfaces
The HDMI interface on the HDMI_PHY block is defined by the TMDS differential lanes
and the HPD/DDCCEC connections. HDMI video data is provided through three
differential TMDS pairs for data and one TMDS differential pair for clock. HPD/
DDC_CEC enables detection of the HDMI sink. These signals interface the external
world and connect to the HDMI connector.
On the system interface, the HDMI_PHY connects to the HDMI Tx link controller. This
block provides an input reference clock to the PHY (pixel clock). Based on the defined
video mode, a pixel repetition clock and a TMDS word clock are output to the controller.
The controller then generates video data on this TMDS word clock and outputs both data
and clock to the HDMI_PHY. Data is then serialized and sent to the HDMI interface.
In addition, the system side includes one standard I2C interface for configuration and
testability of the PHY. Other signals correspond to control logic and are either input to
the PHY or provided by the PHY to the controller block for observability.
34.1.5.3 HDMI 1.4 I/O Pads

HDMI 3D Tx PHY provides a set of analog ESD pads for use.
34.1.5.3.1 I/O Pads Description

HDMI 3D Tx PHY I/O pads are provided as follows:
• Pad order: VPH, VP, GD, VPH, VP, GD, VPH, VP, GD, HDMI_TX_CLK_P,
HDMI_TX_CLK_N, GD, HDMI_TX_DATA0_N, HDMI_TX_DATA0_P, GD,
HDMI_TX_DATA1_N, HDMI_TX_DATA1_P, GD, HDMI_TX_DATA2_N,
HDMI_TX_DATA2_P, GD, VP, VPH, REXT, HDMI_TX_HPD,
HDMI_TX_DDC_CEC
As shown in the figure below, for maximum performance, HDMI 3D Tx PHY I/O pads
contain decoupling capacitance between VP and GD and a filter between VP and
VP_FILT (one for each VP_FILT signal).

Decoupling
VP Filter
VP
VP VP FILT
C_decoupling R_filter
C filter
GD GD
C_decoupling = 0.5 nF C_filter = 50 pF

R_filter = 57 Ω
Figure 34-3. I/O Pads: Decoupling Capacitance Between VP and GD, Filter Between VP
and VP_FILT

The table found here describes the external signals of HDMI.
Table 34-1. HDMI External Signals
HDMI_TX_CEC_LINE CEC line between source and sink EIM_A25 ALT6 I/O
(CEC_LINE) KEY_ROW2 ALT6
HDMI_TX_CLK_N Negative Clock Signal HDMI_CLKM No Muxing I
(CLK_N)
HDMI_TX_CLK_P Positive Clock Signal HDMI_CLKP No Muxing I
(CLK_P)
HDMI_TX_DATA0_N Negative Data Signal 0 HDMI_D0M No Muxing I/O
(DATA0_N)
HDMI_TX_DATA0_P Positive Data Signal 0 HDMI_D0P No Muxing I/O
(DATA0_P)
(DATA1_N)
(DATA1_P)
(DATA2_N)

External Signals
Table 34-1. HDMI External Signals (continued)

(DATA0_P)
HDMI_TX_DDC_CEC CEC Signal HDMI_DDCCEC No Muxing I/O
(DDC_CEC)
HDMI_TX_DDC_SCL SCL Signal EIM_EB2 ALT4 I/O
(DDC_SCL) KEY_COL3 ALT2
HDMI_TX_DDC_SDA SDA Signal EIM_D16 ALT4 I/O
(DDC_SDA) KEY_ROW3 ALT2
HDMI_TX_HPD (HPD) HPD Signal HDMI_HPD No Muxing I/O
34.2.1 Top-Level I/O Diagram

The figure below shows the HDMI 3D Tx PHY top-level signals.

HDMI 3D Tx PHY
SCANMODE VPH
SCANEN VP
SCANCLK VP_FILT0 Power Supply
Scan Signals Signals
SCANIN[4:0] VP_FILT1
SCANOUT[4:0] VP_FILT2
SCANRST GD
TX_READY HDMI_TX_DATA[2:0]_P
Transmitter DATA0[19:0] HDMI_TX_DATA[2:0]_N
TMDS Interface
Datapath Signals DATA1[19:0] HDMI_TX_CLK_P
DATA2[19:0] HDMI_TX_CLK_N
HDMI_TX_DDC_SCL PHY_RESET Reset Signals

HDMI_TX_DDC_SDA
I2C Interface SDA_PUL_DN_N PCLK
I2C_SLAVE_ADDR[6:0] TMDSCLKIN
TMDSCLKSRC System Clock
PREPCLK Signals
HDMI_TX_HPD WIDE_XFACE
Hot Plug Detect
SNKDET PDDQ Control Signals
Signals
HDMI_TX_DDC_CEC TX_PWRON
ENHPDRXSENSE
Rx Detection
RXSENSE
Signals
RESREF_S External
RESREF_F Component
Figure 34-4. Top-Level I/O Diagram
34.2.2 Top -Level Signal Descriptions

This section describes the top-level signals.
In addition to describing the function of each signal, the signal descriptions include the
following information:
• Voltage range: Describes the voltage range expected on this pin.
• Synchronous: Indicates that the signal is asserted or deasserted with respect to a
clock edge.
• Asynchronous: Indicates that the signal is not asserted or deasserted with respect to
a clock edge.

External Signals
34.2.2.1 TMDS Interface

The table below describes the Transmission Minimized Differential Signaling (TMDS)
interface signals.
Table 34-2. TMDS Interface

Signal I/O Description
HDMI_TX_DATA[2:0]_P O Function: Positive TMDS differential line driver data output for data channels 0,1, and
2.
Voltage range: For the permitted voltage range, refer to High-Definition Interface
Specification, Version 1.4, "Electrical Specification" section.
Active state: N/A
Synchronous to: N/A
HDMI_TX_DATA[2:0]_N O Function: Negative TMDS differential line driver data output for data channels 0,1, and
2.
Voltage range: For the permitted voltage range, refer to High-Definition Interface
Specification, Version 1.4, "Electrical Specification" section.
Active state: N/A
Synchronous to: N/A
HDMI_TX_CLK_P O Function: Positive TMDS differential line driver clock output
Voltage range: For the permitted voltage range, refer to High-Definition Multimedia
Interface Specification, Version 1.4, "Electrical Specification" section.
Active state: N/A
Synchronous to: N/A
HDMI_TX_CLK_N O Function: Negative TMDS differential line driver clock output
Voltagerange: For the permitted voltage range, refer to High-
DefinitionMultimediaInterfaceSpecification, Version 1.4, "Electrical Specification"
section.
Activestate: N/A
Synchronousto: N/A
34.2.2.2 Reset Signals

The table blow describes the reset signals.
Table 34-3. Reset Signals
PHY_RESET I Function: PHY reset. This signal places the digital section of the macro into a reset
state.
Voltagerange: 0-VP

Table 34-3. Reset Signals

Activestate: High
Synchronousto: Asynchronous
34.2.2.3 External Component

The table below describes the top-level signals that connect to an external component.
Table 34-4. External Component

RESREF_S I/O Function: 1600- precision resistor to ground. During resistor tuning, current is forced
through the external resistor using RESREF_F, while the induced voltage is sensed on
RESREF_S.
Voltage range: N/A
Active state: N/A
Synchronous to: Asynchronous
RESREF_F I/O Function: Reference resistor connection
Voltage range: N/A
Active state: N/A
Synchronous to: Asynchronous

This section describes the functional architecture of the HDMI 3D Tx PHY.
34.3.1 Functional Overview

The figure found in this section shows a functional block diagram of the HDMI_PHY.

tmdsclksrc
HDMI_TX_DATA2_P
DATA0[19:0] 10 Serializer Data
DRV
DATA1[19:0] PHY <-> Link sclk 1 HDMI_TX_DATA2_N
DATA2[19:0] Interface
TMDSCLKIN
tmdsclksrc
TMDSCLKSRC HDMI_TX_DATA1_P
10 Data
PREPCLK Main PHY Serializer DRV
PHY_RESET sclk 1 HDMI_TX_DATA1_N
PDDQ
WIDE_XFACE
tmdsclksrc
TX_PWRON HDMI_TX_DATA0_P
FSM 10 Data
TX_READY Serializer DRV
ENHPDRXSENSE sclk 1 HDMI_TX_DATA0_N
tmdsclk HDMI_TX_CLK_P
PCLK DRV
PLL / MPLL
HDMI_TX_CLK_N
HDMI_TX_DDC_SCL
HDMI_TX_DDC_SDA I2C IREF
SDA_PULL_DN_N RESREF_S
(TEST / CONF)
I2C_SLAV_ADDR[6:0] RESREF_F
RXSENSE RXSENSE Hot Plug

HDMI_TX_HPD
Detector
SNKDET
HDMI_TX_DDC_CEC
Figure 34-5. HDMI 3D Tx PHY Functional Block Diagram
The HDMI_PHY is the physical layer of an HDMI/DVI-compliant digital transmitter

(source), capable of encoding and transmitting high-speed data streams carrying RGB
video, audio, and control information. The HDMI Link Controller interface conforms to a
30- or 60-bit synchronous data interface (DATA0[19:0],DATA1[19:0],DATA2[19:0]).
The PHY includes two PLLs that synthesize the high-speed serial bit clock (required by
the transmitter) from a reference pixel clock with a frequency of 13.5-266 MHz, for a
transmitter capable of transmitting up to 9.2 Gbps using three lanes.

The HDMI_PHY drives audio and video across three TMDS data channels. Each serial
TMDS link has a data rate range of 0.25-3.4 Gbps. The HDMI_PHY also drives the
TMDS clock at 1/10th of the serial data rate with a frequency range of 25-266 MHz.
Within the HDMI_PHY, additional support blocks exist: the Bandgap block (for blocks
biasing), the Resistor Calibration block, the ADC, and the analog test bus.
The HDMI_PHY accepts an input pixel clock (PCLK) with a frequency range of
13.5-266 MHz and accepts three channels of parallel data (TXDATA0[19:0],
TXDATA1[19:0], TXDATA2[19:0]) that is synchronous with the TMDSCLKIN input
clock. The TMDSCLKIN clock has a frequency range of 12.5-266MHz.
The TMDSCLKSRC clock output should be used by the HDMI transmitter controller as
the source for TMDSCLKIN. The relation between TMDSCLKSRC and TMDSCLKIN
should be constant between resets.
The HDMI_PHY's status and configuration is accessed through its I2C interface. In Scan
mode of operation, SCANCLK is bypassed to all PHY output clocks.
PLL/MPLL Operation
The PLL/MPLL can be configured in Coherent mode or Non-Coherent mode (default). In
Coherent mode, the TMDS clock is the MPLL feedback clock, which is coherent with the
MPLL's high-speed output clock, because both clocks are shaped by the MPLL response.
In Non-Coherent mode, the TMDS clock is the MPLL reference clock, which is not
coherent with the MPLL's high-speed output clock.
Driver Operation
The driver differential source termination, edge rate, pre-emphasis, and voltage level can
be configured for maximum performance.

This section describes various operating modes of the HDMI_PHY.
The HDMI_PHY can be placed in two different operating modes: Power-Down and
Active.
The PHY_RESET signal is used to place the digital section of the IP in a well-defined
state. Reset is active when the PHY_RESET signal is asserted high. PHY_RESET
assertion also clears the configuration registers. Through the control registers, assertion
of a soft reset to the macro is possible. This soft reset clears all system FSMs except I2C
and control registers.

For each separate video mode in which the HDMI_PHY is set to transmit, due to
different operating frequency, color depth and pixel repetition that characterizes each
one, you might need to configure the PHY block for correct operation and optimized
performance. It is recommended that PHY configuration through the I2C interface be
done while the PHY is in Power-down mode. Configuration involves programming the
PLL/MPLL internal blocks as well as the analog drivers' source termination value and
edge rate control, for example. This programming is done through the I2C interface. For
more information about the I2C interface, see I2C Interface Signals, for information about
the PLL/MPLL configurations that must be made for each video mode of operation, see
PLL/MPLL Generic Configuration Settings , and for information about the driver
configurations, see Control Registers and Appendix A: Driver Voltage Level
Configuration.
34.3.2.1 Power-Down Mode

This mode is the lowest power consumption mode. The PHY enters this mode when the
TX_PWRON and ENHPDRXSENSE signals are set to 1'b0 and the PDDQ and
PHY_RESET signals are set to 1'b1.
This mode is characterized by having all analog blocks disabled and digital logic quiet.
Current consumption in this mode corresponds to the analog blocks standby current and
digital logic leakage current.
To enable the HDMI 3D Tx PHY to enter Power-down mode, after TX_PWRON is set to
1'b0, the PCLK input must continue toggling until the TX_READY output signal is set to
1'b0 (indicating that the PHY has been correctly set in Power-down mode). If this
sequence is not followed, TX_READY is not set to 1'b0, and the PHY remains in Active
mode.
During Power-down mode, the ENHPDRXSENSE control signal can be set to 1'b1,
enabling the HPD and RXSENSE-related circuitry. This setting enables the link
controller to observe when an HDMI Rx is connected to the Tx and to power up the
HDMI 3D Tx PHY after detecting the Rx.
During Power-down mode, if ENHPDRXSENSE is enabled, it is recommended that
source terminations on both data and clock lines are enabled by setting tx_rescal[6:0] and
ck_rescal[6:0] to 7'b1111111 on registers
0x04 and 0x05, respectively. Because the analog driver within the macro is disabled,
enabling the source terminations will help pull-down the floating TMDS data/clock lines
to a voltage level that will guarantee proper RXSENSE operation and output signaling
when the Rx connects/disconnects from the PHY.

34.3.2.2 Active Mode

Active mode is the normal operational mode. To start processing received data from the
link controller interface, the macro must first reach this state. The PHY is ready to
transmit when TX_READY is asserted high.
In this state, the interface signals (DATA0[19:0], DATA1[19:0], DATA2[19:0]) are sent
to the HDMI interface. Data is transferred according to the HDMI specification.
After entering Active mode, the HDMI Tx macro starts serially transmitting data received
from the link controller to the TMDS interface. The way in which input data is encoded
(depends on whether data corresponds to Video Data Period, Data Island Period, or
Control Periods) depends on the HDMI protocol sequence. Data encoding is performed
by the Link controller layer.
While operating in Active mode, the HDMI_PHY operates in one of the following modes
(as defined in the HDMI specification, and as shown in the figure below):
• Video Data Period
• Data Island Period
• Control Period

HORSYNC
Vertical blanking
V
S
Y
N
C
1,125 lines (total

Active lines
Active video
Horizontal blanking 1,920 active pixels

2,460 total pixels
Control Period
Video Data Period
Data Island Period
Figure 34-6. Active Mode
Video Data Period is used for the transmission of active pixel data. Transition Minimized
(TMDS) data coding (8B10B) is used for 8-bit data transfers. In Deep-color modes, pixel
data words are first packed in 8-bit multiple data groups. These groups are then
fragmented into 8-bit length words for TMDS encoding.
Data Island Period is used for audio or other auxiliary data information transmission.
Data is transferred in packet format using a similar Transition Minimized coding, in this
case a TMDS Error Reduction Coding (TERC4). This is a 4B10B code.
Finally, Control Period is used when non-active video/audio or other auxiliary
information needs to be transmitted. Only control information is transmitted in this mode.
In Control Periods, data is transferred using a Transition Maximized (also TMDS) data

coding, in a form of 2B10B code. This property is very useful to enable proper word
alignment on the sink (receiver) side. A Control Period is always entered between any
other two periods that are not Control Periods.
34.3.2.2.1 Wide Interface Mode

To support the full HDMI bandwidth requirement, each of the three channels accepts 9-
bit data and clock at a maximum rate of 340 MHz. In this case, the WIDE_XFACE input
is set to 1'b0.
When WIDE_XFACE is set to 1'b1, each channel accepts 20-bit data and clock at a
maximum rate of 170 MHz. This mode is meant to ease interface timing while
maintaining the maximum HDMI bandwidth requirement.
When WIDE_XFACE is set to 1'b1, the TMDSCLKSRC clock frequency is not reduced
to half simply through the WIDE_XFACE control. The frequency can be reduced to half
through the I2C interface, register 0x1E, cko_word_div_enb control bit. This control is
independent from the WIDE_XFACE selection.
34.3.2.3 Power Sequence

The HDMI_PHY power sequence implementation controls the PLL/MPLL start of
operation, resistor calibration, and clock alignment.
As shown in the figure below, during power-up, the Power Sequence finite state machine
(FSM) advances through the PLL and MPLL power-up states by loading a counter at the
beginning of each state (pwr_cnt) and advancing when the counter (pwr_cnt) decrements
to 0. After the Resistor Calibration FSM is enabled in the RES_CAL state, the FSM waits
for the assertion of rcal_adc_done before advancing. After the Clock Alignment FSM is
enabled in the TX_CLK_ALIGN state, the Power Sequence FSM waits for the assertion
of tx_ck_align_done before advancing to the TX_READY state. The TX_READY state
asserts the TX_READY output signal, which indicates that the HDMI_PHY is ready to
transmit the TMDS clock and data and that normal operation can begin.
If TX_PWRON is deasserted in the TX_READY state, the Power Sequence FSM moves
to the DISABLE_TX state. The power-down sequence is initiated. This state disables the
TMDS clock and data outputs. Next, the PWR_DN_PLL resets the PLL and MPLL
blocks. Finally, the FSM returns to the PWR_DN state and waits for TX_PWRON
assertion to begin the power-up sequence.
The HDMI_PHY enters Power-down mode only when the TX_READY output is
deasserted. To enable the power sequence to reach this state, when TX_PWRON is set to
1'b0 while the HDMI_PHY is in the "TX_READY" state, the PCLK input must continue

toggling until TX_READY is deasserted. This sequence is required to enable the Power
Sequence FSM to continue its execution and move from TX_READY to DISABLE_TX,
later to PWR_DN_PLL, and finally to PWR_DN that corresponds to the power-down
state.

reset/undetined states
PWR_DN
set ck_ref_enb_mux = 00
TX PWRON &&
bypass_ppII
TX PWRON && set pwr cnt =
! bypass ppII 'HDMI PLL PU TIME
PLL_PWR_ON PLL_DRV_ANA
set ck ref enb mux = 10 set ck ref enb mux = 10
set pII drv ana = 0
set pII pwr on = 1 set mpII pwr on = 1
pwr_cnt==0 set pwr_cnt = pwr_cnt==0 set pwr_cnt =
'HDMI PLL RST TIME 'HDMI MPLL RST TIME
PLL_RESET MPLL_RESET
set pII rst = 0 set mpII rst = 0

'HDMI_PLL_SHIFT_TIME 'HDMI MPLL SHIFT TIME
PLL_GEAR_SHIFT MPLL_GEAR_SHIFT
set pIl gear shift = 0 set mpII gear shift = 0

'HDMI_PLL_DRV_ANA_TIME 'HDMI MPLL DRV ANA TIME
MPLL_DRV_ANA
set ck_ref_enb_mux = 10
set cko_word_enb = 1 set
mpII_drv_ana = 1
set ser clk enb = 1
pwr_cnt==0 set pwr cnt =
TX PWRON 00 'HDMI_SER_ENB_TIME
!TX_PWRON 01 ck_ref_enb
1 1x TX_SER_ENB
set ck ref enb mux = 10
ck_ref_enb_mux[1:0]
pwr_cnt==0
RES_CAL
set rcal_enb=1
pwr_cnt==0
Resistor Calibration
State Machine
rcal_adc_done==1
PWR_DN_PLL
TX CLK ALIGN set ck ref enb mux = 10
set tx_ck_align_enb = 1
set_ck_ref_enb_mux = 10 set pII rst = 1
set mpll rst = 1
Clock Alignment set pwr_cnt =
State Machine pwr cnt==0 'HDMI HDMIPD TIME
tx_ck_align_done==1 TX_READY stDISABLE_TX

!TX PWRON set ser clk enb = 0
set TX READY = 1
set pwr_cnt =
'HDMI_DIS_TX_TIME
Figure 34-7. Power Sequence Finite State Machine

The following signals can be overridden through the control registers: bypass_ppll,
pll_pwr_on, pll_rst, pll_gear_shift, pll_drv_ana, mpll_rst, mpll_gear_shift,
cko_word_enb, mpll_drv_ana, ser_ckl_enb, rcal_enb, tx_clk_align_enb, ser_clk_enb, and
ck_ref_enb.
The rcal_adc_done and tx_ck_align_done signals can be observed through the control
registers or through the digital test bus (dtb[1:0], controlled through control registers).
The TX_PWRON and TX_READY signals belong to the HDMI 3D Tx PHY macro
interface.
The power sequence can also be started through control registers, using the tx_pwron0,
tx_pwron1, tx_pwron2, and ck_pwron signals.
TX_READY can also be overridden through control registers.
The clock source that clocks the Power Sequence FSM is controlled by the refclk_enb
signal. This signal is asserted when TX_PWRON is asserted or when the state machine is
in a state other than PWR_DN. This signal can be overridden through the control
registers.
NOTE
Due to a potential different state on some analog nodes, it is
recommended that the power-up sequence be run twice (after
the first TX_READY assertion, the PHY can be powered down,
then powered up again).
The clock alignment procedure can be done differently for each of the power-up
sequence runs. For the first run, the clock alignment can be set to be performed channel-
by-channel (tx_ck_align_mode = 1'b1, register 0x1C); for the second power-up, the clock
alignment can be set to be performed for all channels at the same time
(tx_ck_align_mode = 1'b0, register 0x1C) to ensure inter-pair skew close to 0 UI.
34.3.2.3.1 PLL/MPLL
During power-up, the PLL block and (optionally) MPLL block receive the pwron, rst,
gear_shift, and drv_ana signals, as shown in the figure below. The minimum and
maximum timing for these signals is listed in the table below. The power sequence then
initiates the resistor calibration and clock alignment steps.

Pll ck_ref_mpII
MPLL ck_ref_p/m
(prescaler)
pll_pwron mpll_pwron
pll_rst mpll_rst
pll_gear_shift mpll_gear_shift
mpll_drv_anapII_drv_ana
PCLK cko_word_enb MUX

DIV8 ck_ref
pll_pwron
Phese TMDSCLKSRC
Prequency acquisition acquisition
and lock
pll_rst
HDMI PLL PU TIME
pll_gear_shift
HDMI_PLL_RST_TIME
pll_drv_ana HDMI_PLL_SHIFT_TIME
mpll_pwron
Prequency Phese
acquisition acquisition
and lock
mpll_rst
HDMI PLL DRV ANA TIME
mpll_gear_shift
HDMI_MPLL_RST_TIME
mpll_drv_ana
HDMI MPLL SHIFT TIME
cko_word_enb HDMI_MPLL_DRV_ANA_TIME
Figure 34-8. PLL/MPLL Power-Up Sequence
The following signals can be overridden through the control registers: pll_pwron, pll_rst,
pll_gear_shift, pll_drv_ana, mpll_pwron, mpll_rst, mpll_gear_shift, mpll_drv_ana, and
cko_word_enb.
ck_ref, ck_ref_p/m, and ck_ref_mpll are internal signals, while PCLK and
TMDSCLKSRC belong to the HDMI 3D Tx PHY macro interface.
The table below provides the PLL/MPLL power-up times.

Table 34-5. PLL/MPLL Power-Up Time

Count Name Count Value Minimum Time (µs) Maximum Time (µs)
(T(refclk) = 0.00294 (T(refclk = 0.07407 µs)
µs)
HDMI_PLL_PU_TIME 125 2.294 74.074
HDMI_PLL_RST_TIME 1250 22.940 740.740
HDMI_PLL_SHIFT_TIME 50 0.918 29.630
HDMI_PLL_DRV_ANA_TIME 125 2.294 74.074
HDMI_MPLL_RST_TIME 2500 45.880 1481.480
HDMI_MPLL_SHIFT_TIME 1000 18.352 592.592
HDMI_MPLL_DRV_ANA_TIME 50 0.918 29.630
HDMI_SER_ENB_TIME 50 0.918 29.630
Total PLL and MPLL Power-up Time 94.513 3,051.849
34.3.2.3.2 Resistor, ADC Calibration

Users can set the single-ended source termination resistance via the d_tx_term[2:0]
control register bits, according to the table below.
Table 34-6. Single-Ended Source Termination Resistance Settings
N d_tx_term[2:0] R(Ω)
0 000 50
1 001 56.14
2 010 66.67
3 011 80
4 100 100
5 101 133.33
6 110 200
7 111 Open
To accurately set the specified termination, the resistor calibration measures the actual
resistance of the external resistor. The resistance is measured using successive
approximations of a 7-bit termination value by enabling each bit (one-hot) from MSB to
LSB.
Users select the termination value by setting the d_tx_term[2:0] control register bits. The
HDMI 3D Tx PHY includes differential source termination on the drivers.

rescal rep [6] [5] [4] [3] [2] [1] [0]
1:4
resistance ratio
Rext = 1.6kΩ
0
1
sup comp rt r
Comparator
sup comp rt result
Figure 34-9. External Resistor Measurement
The exact value of Rext is determined to create an exact termination.

The analog support block applies a current to the external resistor and compares the
resultant voltage. The result (sup_comp_rt_result) is registered by the Calibration block.
The source termination is then set according to the following equation:
tx_rescal = rescal_rep x ( 1 - 0.125 x N )
Instead of subtracting by (1/8th x rescal_rep x N), rescal_rep is initially multiplied by 8
(left shift by 3 bits), then tx_rescal is subtracted N number of times. N sets clk_cnt, which
sets the number of subtraction loops, as shown in the table below. This table represents
the clk_cnt required to trigger tx_rescal_done. The final result is divided by 8 (right shift
by 3 bits) and rounded up if necessary.
Table 34-7. clk_cnt Necessary to Trigger tx_rescal_done
N/d_tx_term clk_cnt to Trigger tx_rescal_done
0 <all>
1 0
2 1
3 2
4 3
5 4
6 5
7 <all>
The figure below shows the FSM for the resistor and ADC calibration.

Reset / undefined
states
rcal_trigger RCAL_IDLE
rcal_enb set initialize=1
if (rcal_enb) then bit_cnt=6
else bit_cnt=0
adc_trigger
adc_enb rcal_trigger or adc_trigger if (rcal_trigger) then sup_comp_mode=1
else sup_comp_mode=0
COMP_PU
ck_ref_g
set sup_comp_rt_pwron=1
ck_ref_s
39ck_ref cycles (3 stages of 13 clocks)
RCAL_ADC set rcal_adc_done=1
decrement bit_cnt
if bit cnt==0 and sup_comp_mode=0
if bit_cnt==0 and sup_comp_mode=1
TX_RESCAL set rcal_adc_done=1
set pll_gear_shift=0
Figure 34-10. Finite State Machine for the Resistor and ADC Calibration
The rcal_enb signal is asserted by the Power Sequence FSM, but this signal can be
overridden through the control registers.
The rescal_rep, sup_comp_mode, sup_comp_rt_r, sup_comp_rt_result, tx_rescal,
sup_comp_rt_pwron, and adc_enb signals can be overridden through the control
registers.
The rcal_adc_done signal can be observed through the control registers or through the
digital test bus (dtb[1:0], controlled through control registers).
34.3.2.3.3 Clock Alignment

There are two clocks in the transmit clock path, TMDSCLKIN (from the parallel HDMI
controller interface), and internal ck_tx_out (a divided-down clock, generated from the
MPLL clock). These two clocks must be properly synchronized, aligning them before
transmitting data through the HDMI 3D Tx PHY.
The alignment results in the internal tx_ser_clk (buffered version of TMDSCLKIN)
being delayed in the range of 0.6-0.8 UI with respect to the TMDSCLKIN clock.
The Clock Alignment module adjusts the alignment between TMDSCLKIN and
tx_ser_clk by generating internal clock kill signals called tx_ser_clk_kill[2:0]. On the
rising edge of each tx_ser_clk_kill[2:0] signal, the corresponding tx_ser_clk[2:0] is
delayed by 0.2 UI.

The clock alignment enable input, tx_ck_align_enb, is generated by the power sequence,
but this input can also be overridden through the control registers.
Because it is assumed that channel 1 (the middle channel) has the median delays among
the three channels, the state machine will compare TMDSCLKIN and tx_ser_clk[1] only
when the register bit, tx_ck_align_mode, is low (default). In this case,
tx_ser_clk_kill[2:0] is asserted simultaneously. When tx_ck_align_mode is high, each
channel is aligned individually. Channel 2 is aligned first, followed by channel 0 and
lastly channel 1. The tx_ck_align_mode signal is controlled through the control registers.
The internal clock kill signals, tx_ser_clk_kill2, tx_ser_clk_kill1, and tx_ser_clk_kill0,
are generated by the Clock Alignment state machine, but these signals can be overridden
through the control registers.
34.3.2.4 Color Depth and Color Mode Selection

This section describes HDMI 3D Tx PHY color depth and color mode selection.
34.3.2.4.1 Pixel Repetition Clock Generation Selection

For small displays operating a TMDS clock below 25 MHz or applications that require an
increase in available bandwidth for audio and auxiliary information transmission, the
HDMI_PHY can generate pixel repetition clocks.
Pixel repetition signals are dedicated to configure pixel repetition rates. These signals
affect only the relation between PCLK and PREPCLK.
PCLK 1 / (pixel repetition) x PREPCLK
34.3.3 Configuration and Test Mode

This section describes HDMI 3D Tx PHY configuration and test mode operation.
The HDMI 3D Tx PHY can be configured and set in test mode through the supported I2C
interface.
To avoid transient periods in the macro operation during reconfiguration procedures, it is
highly recommended that the I2C interface be used while the HDMI 3D Tx PHY is in
Power-down mode.
Control Registers describes all the registers and corresponding fields that are available
through the I2C interface.

34.3.3.1 Power-Up Configuration

Before powering up the HDMI 3D Tx PHY, configure the PHY for proper operation and
performance.
Configuring the PHY through the I2C interface is as follows.
NOTE
The recommended settings for the PLL/MPLL mode of
operation and driver configurations provided in this section are
presented as the default value that should be considered and
initially configured. Unless stated otherwise, these
recommended settings apply to all operating frequencies.
PLL/MPLL Mode of Operation
Configuration summary: Configure PLL/MPLL mode of operation as Single or Two-PLL
in Coherent or Non-Coherent mode. For more information about these modes of
operation, see Power-Up Requirements.
Table 34-8. PLL/MPLL Mode of Operation

Fields Bits Default
Register0x13
bypass_ppll 11 1'b0
Register0x17
cko_sel 2-1 2'b11
PLL/MPLL Clock Dividers and Analog Configuration

Configuration summary: Configured for each video mode. For information about the PLL
and MPLL divider settings, see Table B-2 .
Table 34-9. PLL/MPLL Clock Dividers and Analog Configuration

Fields Bits
Register 0x06
prep_div[1:0] 14-13
mpll_n_ctrl[1:0] 8-7
pll_n_ctrl[1:0] 6-5
pixel_rep[2:0] 4-2
clr_dpth[1:0] 1-0

Table 34-9. PLL/MPLL Clock Dividers and Analog Configuration

(continued)
Fields Bits
Register 0x10
mpll_prop_cntrl[2:0] 11-9
mpll_int_cntrl[2:0] 8-6
pll_prop_cntrl[2:0] 5-3
pll_int_cntrl[2:0] 2-0
Register 0x15
pll_gmp_cntrl[1:0] 3-2
mpll_gmp_cntrl[1:0] 1-0
Driver Edge Rate Control

Configuration summary: This bus controls the slew rate of the clock and data output
drivers.
Table 34-10. Driver Edge Rate Control
Fields Bits Default
Register 0x06
tx_edgerate[1:0] 12-11 2'b00
ck_edgerate[1:0] 10-9 2'b00
Driver Single-Ended Source Termination

Configuration summary: This bus controls the driver single-ended source termination.
Table 34-11. Driver Single-Ended Source Termination

d-tx_term R (ohm)
000 50
001 56.14
010 66.67
011 80
100 100
101 133.33
110 200
111 Open circuit

Fields Bits Default

Register 0x19
d_tx_term[2:0] 2-0 3'b101
Driver Voltage Level

Configuration summary: For information about the driver voltage level settings, see
Appendix A: Driver Voltage Level Configuration. Driver voltage level configuration is
dependent on driver differential source termination and driver pre-emphasis settings.
Table 34-12. Driver Voltage Level
Fields Bits Default
Register 0x0E
sup_tx_lvl[4:0] 9-5 25-148.5 MHz: 5'b10000
222.75-297 MHz: 5'b01111
340 MHz: 5'b01110
sup_ck_lvl[4:0] 4-0 25-148.5 MHz: 5'b10000
222.75-297 MHz: 5'b01111
340 MHz: 5'b01110
Driver Pre-Emphasis
Configuration summary: Enables trailer drivers to enable pre-emphasis operation. Pre-
emphasis is achieved by reducing the drive level of a non-transition bit with respect to a
transition bit. The following table summarizes the total output current configured with
pre-emphasis (I is current of unit current source).
Table 34-13. Driver Pre-Emphasis

Total Output Current tx_symon tx_traon tx_trbon
0*I 0 0 0
36 * I 1 0 0
36 * I + 3 * I 1 0 1
36 * I + 6 * I 1 1 0
36 * I + 6 * I + 3 * I 1 1 1
The amount of pre-emphasis is programmed through the tx_traon and tx_trbon signals in
the control register, address 0x09 as follows.
Field Bit Default

tx_trbon 1 25-148.5 MHz: 1'b0

222.75-340 MHz: 1'b1
tx_traon 2 1'b0
34.4 System-Level Implementation
34.4.1 System Operation

This section describes HDMI 3D Tx PHY system operation including power-up/power-
down and power- on reset.
34.4.1.1 Powering Up and Powering Down

To set the HDMI_PHY in Power-down mode, set the TX_PWRON signal to 1'b0 and the
PDDQ signal to 1'b1. To power up the HDMI 3D Tx PHY and place it in Active mode,
set TX_PWRON to 1'b1 and PDDQ to 1'b0.
Any configuration programmed on the HDMI_PHY must be done in Power-down mode.
To configure the PHY through the I2C interface, set PHY_RESET to 1'b0 (to move the
digital core from a reset state and to enable programming).
The figure below shows the power-down and power-up sequences.

System-Level Implementation
PDDQ
TX PWRON
PHY RESET
Power-down I2C configuration Power-up
Figure 34-11. Power-Down and Power-Up Sequence
The power-up sequence starts by advancing one finite state machine (FSM) through the
Phase-Locked Loop (PLL) and Multiplexed Phase-Locked Loop (MPLL) power-up
states. Afterwards, resistor calibration is performed and clock alignment is enabled.
When clock alignment is completed, the TX_READY signal is set to 1'b1 to indicate that
the PHY is ready to transmit the TMDS clock and that data transmission and normal
operation can start.
In Power-down mode, TMDS clock and data lines are disabled.
Power-Up Configuration
Before powering up the HDMI_ PHY, configure the PHY for proper operation and
performance. The following PHY characteristics can be configured:
• PLL/MPLL mode of operation: Configure PLL/MPLL mode of operation as Single
or Two-PLL in Coherent or Non-Coherent mode.
• PLL/MPLL clock dividers and analog configuration: Configure for each video mode.
• Driver edge rate control: Slew rate of clock and data output drivers
• Driver differential source termination: Differential source termination of clock and
data output drivers
• Driver voltage level: Voltage reference level for clock and data channels
• Driver pre-emphasis: Enable and control pre-emphasis operation
For more information about this configuration and the associated control registers and
signals, see Power-Up Configuration.

34.4.1.2 Active Mode Requirements

During normal operation, the RXSENSE circuitry must always be enabled
(ENHPDRXSENSE asserted high).
During normal operation, if ENHPDRXSENSE is deactivated (asserted low), the PHY's
analog portion is turned off.
34.4.1.3 Power-Up Requirements

Before setting the TX_PWRON signal high and the PDDQ signal low to power up the
HDMI 3D Tx PHY, the PCLK and TMDSCLKIN input reference clocks must be stable
and within their specified parameters, and power supply rails must be stable and within
the specifications.
34.4.1.4 Power Supply Sequence When the HDMI 3D Tx PHY is Not

Used
The HDMI 3D Tx PHY supports power collapsing.
There is no constraint on the power supply sequence when the HDMI 3D Tx PHY is not
used. However, it is recommended that you short the data/clock lines to ground (or leave
them floating). Activity at the data/clock lines or shorting the data/clock lines to the 3v3
rail (from Rx) should be avoided.
34.4.1.5 Power-Down Requirements

To enable the HDMI 3D Tx PHY to enter Power-down mode, after TX_PWRON is set to
1'b0, the PCLK input must continue toggling until the TX_READY output signal is set to
1'b0 (indicating that the PHY has been correctly set in Power-down mode). This
sequence is required to enable the power-sequence machine to continue its execution and
move from its states until the machine reaches the power-down state.
If this sequence is not followed, TX_READY is not set to 1'b0, and the HDMI 3D Tx
PHY remains in Active mode.

Control Registers
34.5 Reference Clock

This chapter describes the reference clock that the HDMI_PHY supports.
The HDMI_PHY system requires an input clock signal that must be applied to the PCLK
input with the following constraints:
• Minimum PCLK period/frequency (pixel repetition): 74 ns/13.5 MHz
• Minimum PCLK period/frequency (no pixel repetition): 39.7 ns/24.175 MHz
• PCLK duty cycle: 40-60%
• Maximum PCLK long-term RMS jitter: 100 ps
34.6 Control Registers
34.6.1 Control Registers Module Design Architecture

The Control Registers module is designed to provide the HDMI 3D Tx PHY with a file
register component (36 words where each word comprises 16 bits).
Each register is designed to correspond to one of the following access types.
• Read-only: The HDMI controller can only read from this register. No writing by the
HDMI controller is permitted.
• Read/write: The HDMI controller can read from and write to this register.
• Read/write/override: The HDMI controller can read from and write to this register.
However, if the MSB of the register is set to 0, the value read by the HDMI
controller will not be the value stored in the register; instead, the value will be the
internal value of the HDMI PHY. In particular, this event occurs for 0x14, 0x18,
0x0A, and 0x0F where the value is read from the I2C interface when PHY_RESET
and TX_PWRON are low.
• Read/write/asynchronous set-on-done: The HDMI controller can read from and
write to this register synchronously. However, three internal modules (Resistance
Calibration, Clock Alignment, and Tx Scope) can write to this register
asynchronously.

34.7 HDMI_PHY Memory Map/Register Definition
NOTE
HDMI_PHY registers are accessed through the I2C Master
Interface of the HDMI Controller. See HDMI Transmitter
(HDMI) for more information.
HDMI_PHY memory map
Absolute
Width Section/
(in bits) page
(hex)
0 Power Control (HDMI_PHY_PWRCTRL) 16 R/W 0000h 34.7.1/1638
1 Serializer Divider Control (HDMI_PHY_SERDIVCTRL) 16 R/W 0000h 34.7.2/1640
2 Serializer Clock Control (HDMI_PHY_SERCKCTRL) 16 R/W 0000h 34.7.3/1640
3 Serializer Clock Kill Control (HDMI_PHY_SERCKKILLCTRL) 16 R/W 0000h 34.7.4/1641
Transmitter and Resistance Calibration Control
4 16 R/W 0000h 34.7.5/1642
(HDMI_PHY_TXRESCTRL)
5 Clock Calibration Control (HDMI_PHY_CKCALCTRL) 16 R/W 0000h 34.7.6/1643
Color Depth, Pixel Repetition, Clock Divider for PLL and
6 16 R/W 0400h 34.7.7/1644
MPLL, and Edge Rate Control (HDMI_PHY_CPCE_CTRL)
Tx and Clock Measure Control
7 16 R/W 0000h 34.7.8/1646
(HDMI_PHY_TXCLKMEASCTRL)
8 Tx Measure Control (HDMI_PHY_TXMEASCTRL) 16 R/W 0000h 34.7.9/1647
Clock Symbol and Transmitter Control 34.7.10/
9 16 R/W 0000h
(HDMI_PHY_CKSYMTXCTRL) 1649
Comparator Sequence Control 34.7.11/
A 16 R/W 0000h
(HDMI_PHY_CMPSEQCTRL) 1650
34.7.12/
B Comparator Power Control (HDMI_PHY_CMPPWRCTRL) 16 R/W 0000h
1651
34.7.13/
C Comparator Mode Control (HDMI_PHY_CMPMODECTRL) 16 R/W 0000h
1651
34.7.14/
D Measure Control (HDMI_PHY_MEASCTRL) 16 R/W 0000h
1652
34.7.15/
E Voltage Level Control (HDMI_PHY_VLEVCTRL) 16 R/W 0000h
1653
34.7.16/
F Digital-to-Analog Control (HDMI_PHY_D2ACTRL) 16 R/W 0000h
1654
34.7.17/
10 Current Control (HDMI_PHY_CURRCTRL) 16 R/W 08ABh
1655
34.7.18/
11 Drive Analog Control (HDMI_PHY_DRVANACTRL) 16 R/W 0003h
1655
34.7.19/
12 PLL Measure Control (HDMI_PHY_PLLMEASCTRL) 16 R/W 0000h
1656
PLL Phase and Bypass Control 34.7.20/
13 16 R/W 0000h
(HDMI_PHY_PLLPHBYCTRL) 1658

HDMI_PHY Memory Map/Register Definition
HDMI_PHY memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
Gear Shift, Reset Mode, and Power State Control 34.7.21/
14 16 R/W 0000h
(HDMI_PHY_GRP_CTRL) 1659
34.7.22/
15 Gmp Control (HDMI_PHY_GMPCTRL) 16 R/W 0000h
1660
34.7.23/
16 MPLL Measure Control (HDMI_PHY_MPLLMEASCTRL) 16 R/W 0000h
1661
MPLL and PLL Phase, Scope Clock Select, and MUX Clock 34.7.24/
17 16 R/W 0000h
Control (HDMI_PHY_MSM_CTRL) 1663
Scope, Comparator Result and Power Bad Status 34.7.25/
18 16 R 0000h
(HDMI_PHY_SCRPB_STATUS) 1664
34.7.26/
19 Transmission Termination (HDMI_PHY_TXTERM) 16 R/W 0007h
1666
Power Sequence, TX Clock Alignment, Resistance
34.7.27/
1A Calibration, Pattern Generator Skip Bit, and TMDS Encoder 16 R/W 0000h
1667
Enable (HDMI_PHY_PTRPT_ENBL)
34.7.28/
1B Pattern Generator Mode (HDMI_PHY_PATTERNGEN) 16 R/W 0000h
1669
The Soft-Reset and DAC Enable, Clock Alignment and PG 34.7.29/
1C 16 R/W 0000h
Mode (HDMI_PHY_SDCAP_MODE) 1670
34.7.30/
1D Scope Mode register (HDMI_PHY_SCOPEMODE) 16 R/W 0000h
1672
34.7.31/
1E Digital Transmission Mode (HDMI_PHY_DIGTXMODE) 16 R/W 0000h
1673
Scope, Transmission Clock Alignment, and Resistance
34.7.32/
1F Calibration Set-on-Done Status 16 R/W 0000h
1677
(HDMI_PHY_STR_STATUS)
34.7.33/
20 Scope Counter on Channel 0 (HDMI_PHY_SCOPECNT0) 16 R 0000h
1679
34.7.34/
1679
34.7.35/
1680
Scope Counter on Clock Channel 34.7.36/
23 16 R 0000h
(HDMI_PHY_SCOPECNTCLK) 1680
Scope Sample Count MSB, Scope Sample Repetition 34.7.37/
24 16 R/W 13C0h
(HDMI_PHY_SCOPESAMPLE) 1681
Scope Counter MSB Channel 0 and Channel 1 34.7.38/
25 16 R 0000h
(HDMI_PHY_SCOPECNTMSB01) 1682
Scope Counter MSB Channel 2 and Clock Channel 34.7.39/
26 16 R 0000h
(HDMI_PHY_SCOPECNTMSB2CK) 1682
34.7.1 Power Control (HDMI_PHY_PWRCTRL)

Register name: PWRCTRL

Access type: Read/write/override

Address: 0x00
Value at reset: 0x0000
Address: 0h base + 0h offset = 0h
Bit 15 14 13 12 11 10 9 8
Read Override Reserved
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read Reserved tx_pwron tx_pwron0 tx_pwron1 tx_pwron2 ck_pwron
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_PWRCTRL field descriptions

Field Description
15 If the Override bit is set to 1, the working value is the Override bit value, not the registered value.
Override
- Reserved
4 Transmitter Power-On
tx_pwron
This bit enables users to power down the entire PHY through the I2C interface.
0 Power off the PHY, if the Override bit is 1.

1 Power on the PHY, if the Override bit is 1.
3 Transmitter Power-On 0
tx_pwron0
This bit powers on or powers off the transmitter driver for channel 0.
0 Power off the transmitter driver for the first channel, if the Override bit is 0.
1 Power on the transmitter driver for the first channel, if the Override bit is 0.
tx_pwron1
0 Power off the transmitter driver for the second channel, if the Override bit is 0.
1 Power on the transmitter driver for the second channel, if the Override bit is 0.
tx_pwron2
0 Power off the transmitter driver for the third channel, if the Override bit is 0.
1 Power on the transmitter driver for the third channel, if the Override bit is 0.
0 Clock Power-On
ck_pwron
This bit powers on or powers off the clock driver.
0 Power off the clock driver, if the Override bit is 0.

1 Power on the clock driver, if the Override bit is 0.

34.7.2 Serializer Divider Control (HDMI_PHY_SERDIVCTRL)

Register name: SERDIVCTRL
Address: 0x01
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read tx_ tx_ tx_

Overri ser_ ser_ ser_
Reserved
de div_ div_ div_
Write en0 en1 en2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_SERDIVCTRL field descriptions

Field Description
Override
- Reserved
2 Transmitter Serializer Divider Enable 0
tx_ser_div_en0
This bit enables or disables the low-speed clock in serializer 0.
0 Disable the low-speed clock in the first serializer, if the Override bit is 0.
1 Enable the low-speed clock in the first serializer, if the Override bit is 0.
tx_ser_div_en1
0 Disable the low-speed clock in the second serializer, if the Override bit is 0.
1 Enable the low-speed clock in the second serializer, if the Override bit is 0.
tx_ser_div_en2
0 Disable the low-speed clock in the third serializer, if the Override bit is 0.
1 Enable the low-speed clock in the third serializer, if the Override bit is 0.
34.7.3 Serializer Clock Control (HDMI_PHY_SERCKCTRL)

Register name: SERCKCTRL


Address: 0x02
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read tx_ tx_ tx_

Overri ser_ ser_ ser_
Reserved
de clk_ clk_ clk_
Write en0 en1 en2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_SERCKCTRL field descriptions

Field Description
Override
- Reserved
2 Transmitter Serializer Clock Enable 0
tx_ser_clk_en0
This bit enables or disables the high-speed clock in serializer 0.
0 Disable the high-speed clock in the first serializer, if the Override bit is 0.
1 Enable the high-speed clock in the first serializer, if the Override bit is 0.
tx_ser_clk_en1
This bit enables or disables the high-speed clock in serializer 1.
0 Disable the high-speed clock in the second serializer, if the Override bit is 0.
1 Enable the high-speed clock in the second serializer, if the Override bit is 0.
tx_ser_clk_en2
This bit enables or disables the high-speed clock in serializer two.
0 Disable the high-speed clock in the third serializer, if the Override bit is 0.
1 Enable the high-speed clock in the third serializer, if the Override bit is 0.
34.7.4 Serializer Clock Kill Control

(HDMI_PHY_SERCKKILLCTRL)
Register name: SERCKKILLCTRL
Address: 0x03

Bit 15 14 13 12 11 10 9 8
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read tx_ser_clk_ tx_ser_clk_ tx_ser_clk_
Reserved
Write kill0 kill1 kill2
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_SERCKKILLCTRL field descriptions

Field Description
Override
- Reserved
2 Transmitter Serializer Clock Kill 0
tx_ser_clk_kill0
This bit is used to delay the tx_ck_out0 sampling clock by a time tdelay, where tdelay equals one period of
refclk (340 MHz). This delay equals 0.2 UI of the tx_ck_out0 clock.
0 No effect, if the Override bit is 0.

1 Delay the tx_ck_out0 clock by 0.2 UI, if the Override bit is 0.
tx_ser_clk_kill1

tx_ser_clk_kill2

34.7.5 Transmitter and Resistance Calibration Control

(HDMI_PHY_TXRESCTRL)
Register name: TXRESCALCTRL
Address: 0x04

Bit 15 14 13 12 11 10 9 8
Read Override Reserved tx_rescal[6:0]
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read tx_
rescal_rep[6:0]
Write rescal[6:0]
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_TXRESCTRL field descriptions

Field Description
Override
- Reserved
13–7 Transmitter Resistance Calibration
tx_rescal[6:0]
This bus controls the parallel termination of the transmitter drivers and sets termination to a value based
on the calibration algorithm performed in the support resistance calibration module. tx_rescal[6:0] provides
64 termination levels; the specific values are defined from lab test results.
rescal_rep[6:0] Resistance Calibration Replica
This bus controls the bias voltage of the transmitter driver. rescal_rep[6:0]
provides 64 voltage levels; the specific values are defined from lab test results.
34.7.6 Clock Calibration Control (HDMI_PHY_CKCALCTRL)

Register name: CKCALCTRL
Address: 0x05
Bit 15 14 13 12 11 10 9 8
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read Reserved ck_rescal[6:0]
Write
Reset 0 0 0 0 0 0 0 0

HDMI_PHY_CKCALCTRL field descriptions

Field Description
Override
- Reserved
ck_rescal[6:0] Clock Resistance Calibration
This bus controls the termination of the clock driver and sets the termination to a value based on the
calibration algorithm performed in the support resistance calibration module. ck_rescal[6:0] provides 64
termination levels; the specific values are defined from lab test results.
34.7.7 Color Depth, Pixel Repetition, Clock Divider for PLL and
MPLL, and Edge Rate Control (HDMI_PHY_CPCE_CTRL)
Register name: -
Access type: Read/write
Address: 0x06
Bit 15 14 13 12 11 10 9 8
Read mpll_n_
Reserved prep_div[1:0] tx_edgerate[1:0] ck_edgerate[1:0]
Write cntrl[1:0]
Reset 0 0 0 0 0 1 0 0
Bit 7 6 5 4 3 2 1 0
Read mpll_n_
pll_n_cntrl[1:0] pixel_rep[2:0] clr_dpth[1:0]
Write cntrl[1:0]
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_CPCE_CTRL field descriptions

Field Description
- Reserved
14–13 Digital Pixel Repetition Divider Controls the ratio by which the internal TMDS clock is divided to generate
prep_div[1:0] PREPCLK.
00 Divide by 1 (8 bit).
01 Divide by 1.25 (10 bits).
10 Divide by 1.5 (12 bits).
11 Divide by 2 (16 bits).
12–11 Transmitter Edge Rate
tx_edgerate[1:0]

HDMI_PHY_CPCE_CTRL field descriptions (continued)

Field Description
This bus controls the slew rate of the transmitter output driver.
0 tx_edgerate[0]: Slow edges

1 tx_edgerate[0]: Fast edges
0 tx_edgerate[1]: Disable edge rate override.
1 tx_edgerate[1]: Enable edge rate override.
10–9 Clock Edge Rate
ck_edgerate[1:0]
This bus controls the slew rate of the clock output driver.
0 ck_edgerate[0]: Slow edges

1 ck_edgerate[0]: Fast edges
0 ck_edgerate[1]: Disable edge rate override.
1 ck_edgerate[1]: Enable edge rate override.
8–7 Programmable Divider Control
mpll_n_cntrl[1:0]
This bus controls the programmable divider modulus, which are set based on the ck_ref_mpll_p/m (TMDS
rate) input reference frequency to keep the ring oscillator within the required range (925 MHz through 1.85
GHz in MPLL).
00 N = 1 (for TMDS rate of 184.1-370 MHz)

10 N = 4 (for TMDS rate of 45.26-92.5 MHz)
11 N = 8 (for TMDS rate up to 45.25 MHz)
6–5 Programmable Divider Control
pll_n_cntrl[1:0]
This bus controls the programmable divider modules, which are set based on the refclk_p/m (pixel rate)
input reference frequency to keep the ring oscillator within the required range (740 MHz through 1.48 GHz
in PLL).

10 N = 4 (for TMDS rate of 45.26-92.5 MHz)
11 N = 8 (for TMDS rate (not the pixel rate) up to 45.25 MHz)
4–2 Pixel Repetition
pixel_rep[2:0]
This bus controls another factor by which to divide the input frequency (refclk) by the output TMDS rate
(ck_ref_mpll_p/m).
FTMDS/Fin = (clr_depth[1:0] x pixel_rep[2]) / (pixel_rep[1:0])
0 Pixel_rep[2] Divide by 1.
1 Pixel_rep[2]Divide by 2.
00 Pixel_rep[1:0]Divide by 4.
01 Pixel_rep[1:0]Divide by 2.
1x Pixel_rep[1:0]Divide by 1.
clr_dpth[1:0] Color Depth
This bus controls the factor by which to divide the reference clock (PCLK) by the output TMDS rate
(ck_ref_mpll_p/m).
00 Divide by 4.
01 Divide by 5.

HDMI_PHY_CPCE_CTRL field descriptions (continued)

Field Description
10 Divide by 6.
11 Divide by 8.
34.7.8 Tx and Clock Measure Control

(HDMI_PHY_TXCLKMEASCTRL)
Register name: TXCKMEASCTRL
Address: 0x07
Table 34-14. tx_meas_iv2[7:0]
Effective Bit Register Value Description
tx_meas_iv2[0] 00000001 Connect Vcm_p (common DC voltage of the positive side of scope) to the
analog test bus.
tx_meas_iv2[1] 00000010 Connect Vcm_m (common DC voltage of the negative side of scope) to the
analog test bus.
tx_meas_iv2[2] 00000100 Connect Vbg3by4_reg (output node of tx_vreg_vbgby2 block) to the analog
test bus.
tx_meas_iv2[3] 00001000 Connect tx_vref (reference voltage of tx_biasgen block) to the analog test
bus.
tx_meas_iv2[4] 00010000 Connect Vrep_fb (feedback voltage of the replica circuit of tx_biasgen block)
to the analog test bus.
tx_meas_iv2[5] 00100000 In the event that bleed current is too large, this bit can be used to force vb
closer to gnd and disable/reduce the bleed current. (This bit is a debug
feature, which does not pull vb to gnd properly.)
tx_meas_iv2[6] 01000000 Connect Vp (low power supply) to the analog test bus.
tx_meas_iv2[7] 10000000 Connect Vcm (common DC voltage of the scope) to the analog test bus.
Table 34-15. ck_meas_iv[7:0]

ck_meas_iv[0] 00000001 Connect Vcm_p (common DC voltage of the positive side of scope) to the
analog test bus.
ck_meas_iv[1] 00000010 Connect Vcm_m (common DC voltage of the negative side of scope) to the
analog test bus.
ck_meas_iv[2] 00000100 Connect Vbg3by4_reg (output node of tx_vreg_vbgby2 block) to the analog
test bus.

Table 34-15. ck_meas_iv[7:0] (continued)

ck_meas_iv[3] 00001000 Connect tx_vref (reference voltage of tx_biasgen block) to the analog test
bus.
ck_meas_iv[4] 00010000 Connect Vrep_fb (feedback voltage of the replica circuit of tx_biasgen block)
to the analog test bus.
ck_meas_iv[5] 00100000 In the event that bleed current is too large, this bit can be used to force vb
ck_meas_iv[6] 01000000 Connect Vp (low power supply) to the analog test bus.
ck_meas_iv[7] 10000000 Connect Vcm (common DC voltage of scope) to the analog test bus.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read tx_meas_iv2[7:0] ck_meas_iv[7:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_TXCLKMEASCTRL field descriptions

Field Description
15–8 Transmitter Measure Internal Voltage 2
tx_meas_iv2[7:0]
This bus is used to test specific voltages for third transmitter lane/channel by applying voltages on the
atb_sense port based on configured currents, as described in the tx_meas_iv2[7:0] table.
ck_meas_iv[7:0] Clock Measure Internal Voltage
This bus is used to test specific voltages for the clock lane/channel by applying voltages on the atb_sense
port based on configured currents, as described in the ck_meas_iv[7:0] table.
34.7.9 Tx Measure Control (HDMI_PHY_TXMEASCTRL)

Register name: TXMEASCTRL
Address: 0x08
tx_meas_iv1[0] 00000001 Connect Vcm_p (common DC voltage of positive side of scope) to the
analog test bus.
tx_meas_iv1[1] 00000010 Connect Vcm_m (common DC voltage of negative side of scope) to the
analog test bus.
test bus.

Table 34-16. tx_meas_iv1[7:0] (continued)

bus.
tx_meas_iv1[4] 00010000 Connect Vrep_fb (feedback voltage of replica circuit of tx_biasgen block) to
the analog test bus.
tx_meas_iv1[5] 00100000 In case bleed current is too large, this bit can be used to force vb closer to
gnd and disable/reduce the bleed current. (This bit is a debug feature,
which does not pull vb to gnd properly.)
tx_meas_iv1[7] 10000000 Connect Vcm (common DC voltage of scope) to the analog test bus.

tx_meas_iv0[0] 00000001 Connect Vcm_p (common DC voltage of positive side of scope) to the
analog test bus.
tx_meas_iv0[1] 00000010 Connect Vcm_m (common DC voltage of negative side of scope) to the
analog test bus.
test bus.
bus
tx_meas_iv0[4] 00010000 Connect Vrep_fb (feedback voltage of replica circuit of tx_biasgen block) to
the analog test bus.
tx_meas_iv0[5] 00100000 In the event that bleed current is too large, this bit can be used to force vb
tx_meas_iv0[7] 10000000 Connect Vcm (common DC voltage of scope) to the analog test bus.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read tx_meas_iv0[7:0] tx_meas_iv1[7:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_TXMEASCTRL field descriptions

Field Description
15–8 Transmitter Measure Internal Voltage 0
tx_meas_iv0[7:0]
This bus is used to test specific voltages for the first transmitter lane/channel by applying voltages on the
atb_sense port based on configured currents, as described in the tx_meas_iv0[7:0] table.
tx_meas_iv1[7:0] Transmitter Measure Internal Voltage 1
This bus is used to test specific voltages for the second transmitter lane/channel by applying voltages on
the atb_sense port based on configured currents, as described in the tx_meas_iv1[7:0] table.

34.7.10 Clock Symbol and Transmitter Control

(HDMI_PHY_CKSYMTXCTRL)
Register name: CKSYMTXCTRL
Address: 0x09
Bit 15 14 13 12 11 10 9 8
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read Reserved tx_symon tx_traon tx_trbon ck_symon
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_CKSYMTXCTRL field descriptions

Field Description
15 Writing a 0 to the override bit causes the register to set the value 0x0F, regardless of the other bit settings.
Override
Setting the override bit to 1 causes tx_symon, tx_traon, tx_trbon, and ck_symon bits to work per the
register settings. These bits must be set at the same time the override bit is set to 1, or while the override
bit remains at 1.
- Reserved
3 Transmitter Symbol On
tx_symon
This bit enables the transmitter symbol driver(s), To enable the transmitter driver(s), the tx_pwron bit for
each channel must be high.
0 Disable the transmitter symbol driver(s).

1 Enable the transmitter symbol driver(s).
2 Transmitter Trailer A On
tx_traon
This bit enables the transmitter trailer A driver(s). To enable the transmitter trailer A driver(s) and to enable
pre-emphasis, the tx_pwron bit for each channel must be high.
0 Disable the transmitter trailer A driver(s).

1 Enable the transmitter trailer A driver(s).
1 Transmitter Trailer B On
tx_trbon
This bit enables the transmitter trailer B driver(s). To enable the transmitter trailer B driver(s) and to enable
pre-emphasis, the tx_pwron bit for each channel must be high.
0 Disable the transmitter trailer B driver(s).

1 Enable the transmitter trailer B driver(s).

HDMI_PHY_CKSYMTXCTRL field descriptions (continued)

Field Description
0 Clock Symbol On
ck_symon
This bit enables the clock symbol driver. To enable the clock driver, the ck_powon bit must be high. In
addition, there is no pre-emphasis enable for the clock driver.
0 Disable the clock symbol driver.

1 Enable the clock symbol driver.
34.7.11 Comparator Sequence Control

(HDMI_PHY_CMPSEQCTRL)
Register name: CMPSEQCTRL
Address: 0x0A
Address: 0h base + Ah offset = Ah
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
sup_
Overri
Reserved comp
de
_rt_r
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_CMPSEQCTRL field descriptions

Field Description
Override
- Reserved
0 Support Comparator Resistance Termination
sup_comp_rt_r
This bit controls the comparator sequence.
0 Latch the first input, if the Override bit is 0.

1 Latch the second input, then set the comparator's output pin by the result of comparison, if the
Override bit is 0.

34.7.12 Comparator Power Control (HDMI_PHY_CMPPWRCTRL)

Register name: CMPPWRCTRL
Address: 0x0B
Address: 0h base + Bh offset = Bh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read sup_
Overri comp
Reserved
de _rt_
Write pwron
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_CMPPWRCTRL field descriptions

Field Description
Override
- Reserved
0 Support Comparator Resistance Termination Power-On
sup_comp_rt_
This bit powers on the Comparator module.
pwron
0 Power off the Comparator module and connect the comparator's output to ground, if the Override bit is
0.
1 Power on the Comparator module, if the Override bit is 0.
34.7.13 Comparator Mode Control (HDMI_PHY_CMPMODECTRL)

Register name: CMPMODECTRL
Address: 0x0C

Address: 0h base + Ch offset = Ch
Bit 15 14 13 12 11 10 9 8
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read sup_comp_
Reserved
Write mode
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_CMPMODECTRL field descriptions

Field Description
Override
- Reserved
0 Support Comparator Mode
sup_comp_mode
This bit selects the comparator mode.
0 Testing mode (ADC mode)

1 Calibration mode
34.7.14 Measure Control (HDMI_PHY_MEASCTRL)

Register name: MEASCTRL
Address: 0x0D
NOTE
Two or more of the previous register bits must not be set to 1
simultaneously; doing so can lead to a hardware problem.
Address: 0h base + Dh offset = Dh
Bit 15 14 13 12 11 10 9 8
Read Reserved
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read sup_atb_ sup_dac_
Reserved sup_por_meas_iv[1:0]
Write on_rext on_atb
Reset 0 0 0 0 0 0 0 0

HDMI_PHY_MEASCTRL field descriptions

Field Description
- Reserved
3 Support Analog Test Bus On External Calibration Resistance
sup_atb_on_rext
This bit connects or disconnects the Vrext node to/from the analog test bus.
0 Disconnect the Vrext node from the analog test bus.

1 Connect the Vrext node to the analog test bus.
2–1 Support Power Measure Internal Voltage
sup_por_meas_
This bus connects or disconnects a single output signal on the analog test bus to measure the voltage of
iv[1:0]
two nodes of the support power block.
01 Connect Vbe (Bipolar transistor voltage) to the analog test bus.

10 Connect Vbg (Band-gap voltage) to the analog test bus.
0 Support Digital-to-Analog Converter On Analog Test Bus
sup_dac_on_atb
This bit connects or disconnects the DAC's output on the analog test bus to test the performance of the
DAC through Integral Non-Linearity (INL) and Differential Non-Linearity (DNL).
0 Disconnect the DAC's output from the analog test bus.

1 Connect the DAC's output to the analog test bus.
34.7.15 Voltage Level Control (HDMI_PHY_VLEVCTRL)

Register name: VLEVCTRL
Address: 0x0E
Address: 0h base + Eh offset = Eh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read Reserved sup_tx_lvl[4:0] sup_ck_lvl[4:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_VLEVCTRL field descriptions

Field Description
- Reserved
9–5 Support Transmitter Level
sup_tx_lvl[4:0]
This bus controls the reference voltage level of the three transmitter channel modules. This voltage
reference has a direct relation with the output signal voltage level. For more information about the driver
voltage level configuration, see Appendix A: Driver Voltage Level Configuration.

HDMI_PHY_VLEVCTRL field descriptions (continued)

Field Description
sup_ck_lvl[4:0] Support Clock Level
This bus controls the reference voltage level of the Clock Channel module. This voltage reference has a
direct relation with the output signal voltage level. For more information about the driver voltage level
configuration, see Appendix A: Driver Voltage Level Configuration.
34.7.16 Digital-to-Analog Control (HDMI_PHY_D2ACTRL)

Register name: D2ACTRL
Address: 0x0F
Address: 0h base + Fh offset = Fh
Bit 15 14 13 12 11 10 9 8
Read Override Reserved sup_dac_n[7:0]
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read sup_dac_n[7:0] sup_dac_th_n[2:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_D2ACTRL field descriptions

Field Description
Override
- Reserved
10–3 Support Analog-to-Digital Inverted
sup_dac_n[7:0]
This bus represents the LSB's of the 9-bit DAC value.
sup_dac_th_ Support Digital-to-Analog Thermometer Inverted
n[2:0]
This bus value is inverted and defined in the thermometer code to represent the binary code of the two
MSB's of the 9-bit DAC value.
Note: To increase the stability of the DAC block, the two MSB's of the 9-bit DAC value are represented in
thermometer code, not in binary code. The MSB's of the 9-bit DAC value is split into two thermometer-
code bits. A transition from 0 to 1 of the 9-bit DAC value's MSB is represented by "00" -> "01" -> "11" in
thermometer code.

34.7.17 Current Control (HDMI_PHY_CURRCTRL)

Register name: CURRCTRL
Address: 0x10
Value at reset: 0x08AB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read Reserved mpll_prop_cntrl[2:0] mpll_int_cntrl[2:0] pll_prop_cntrl[2:0] pll_int_cntrl[2:0]
Write
Reset 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 1
HDMI_PHY_CURRCTRL field descriptions

Field Description
- Reserved
11–9 MPLL Proportional Control
mpll_prop_
This bus controls the MPLL charge pump proportional current. Eight levels of charge pump proportional
cntrl[2:0]
current value are possible. The specific values are defined in PLL/MPLL Generic Configuration Settings.
Default (reset) value of pll_prop_cntrl[1:0] is 100.
8–6 MPLL Integral Control
mpll_int_cntrl[2:0]
This bus controls the charge pump integral current. Eight levels of charge pump integral current value are
possible. The specific values are defined in PLL/MPLL Generic Configuration Settings.
Default (reset) value of pll_int_cntrl[1:0] is 100.
5–3 PLL Proportional Control
pll_prop_
This bus controls the PLL charge pump proportional current. Eight levels of charge pump proportional
cntrl[2:0]
current value are possible. The specific values are defined in PLL/MPLL Generic Configuration Settings.
Default (reset) value of pll_int_cntrl is 011.
pll_int_cntrl[2:0] PLL Charge Pump Integral Control
This bus controls the PLL charge pump integral current. Eight levels of charge pump integral current value
are possible. The specific values are defined in PLL/MPLL Generic Configuration Settings.
Default (reset) value of pll_int_cntrl[2:0] is 100.
34.7.18 Drive Analog Control (HDMI_PHY_DRVANACTRL)

Register name: DRVANACTRL
Address: 0x11


Bit 15 14 13 12 11 10 9 8
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read mpll_drv_
Reserved pll_drv_ana
Write ana
Reset 0 0 0 0 0 0 1 1
HDMI_PHY_DRVANACTRL field descriptions

Field Description
Override
- Reserved
1 PLL Drive Analog
pll_drv_ana
This bit enables or disables driving the ck_ref_mpll_p/m clocks to the MPLL
module.
Default (reset) value of pll_drv_ana is 1.
0 Set ck_ref_mpll low, if the Override bit is 0.

1 Enable 25-340 MHz output clock (ck_ref_mpll_p/m) to be driven to MPLL, if the Override bit is 0.
0 MPLL Drive Analog
mpll_drv_ana
This bit enables or disables driving the ck_ref_p/m clocks to all transmitters
(tx_topa).
Default (reset) value of mpll_drv_ana is 1.
0 Set ck_ref_p high; ck_ref_m low, if the Override bit is 0.

1 Enable ck_ref_mpll output clock (125-1700 MHz ck_ref_p/m) to be driven to all transmitters (tx_topa),
if the Override bit is 0.
34.7.19 PLL Measure Control (HDMI_PHY_PLLMEASCTRL)

Register name: PLLMEASCTRL
Address: 0x12

NOTE
With the exception of pll_atb_sense_sel and pll_meas_iv[9],
two or more of the previous register bits must not be set to 1
simultaneously; doing so can lead to a hardware problem.
The table below describes the pll_meas_iv[10:0] bit settings.
Table 34-18. pll_meas_iv[10:0]
Effective Bit Pll_meas_iv[10:0] Value Description
Pll_meas_iv[0] 00000000001 Not used.
Pll_meas_iv[1] 00000000010 Not used in pll_top. Connected to fast_tech pins of PLL and MPLL in
hdmi_topa.
Pll_meas_iv[2] 00000000100 Connects VP supply voltage to the atb_sense line.
Pll_meas_iv[3] 00000001000 Connects vp_cp to the atb_sense line.
Pll_meas_iv[4] 00000010000 Connects internal supply voltage of the VCO (ivco) to the atb_sense line.
Pll_meas_iv[5] 00000100000 Connects vp_cko voltage to the atb_sense line.
Pll_meas_iv[6] 00001000000 Connects node vpsf to the atb_sense line.
Pll_meas_iv[7] 00010000000 Connects vref to atb_sense line.
Pll_meas_iv[8] 00100000000 Connects vcntrl to atb_sense line.
Pll_meas_iv[9] 01000000000 Enables the phase mixer and pll_cko_pm_p/m.
Pll_meas_iv[10] 10000000000 Measures the voltage corresponding to the output phase of the clr_dpth
divider (fb_clk) with respect to refclk.
Bit 15 14 13 12 11 10 9 8
Read pll_atb_
Reserved pll_meas_iv[10:0]
Write sense_sel
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read pll_meas_iv[10:0] pll_meas_gd
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_PLLMEASCTRL field descriptions

Field Description
- Reserved
12 PLL Analog Test Bus Sense Select
pll_atb_sense_
This bit enables or disables internal signals of the PLL to be connected to the analog test bus. Without
sel
setting this bit, no measurements can be made on the atb_sense line.
Default (reset) value of pll_atb_sense_sel is 0.
0 Disable the ability to measure internal DC signals on the atb_sense line in the PLL.
1 Enable the ability to measure internal DC signals on the atb_sense line in the PLL.

HDMI_PHY_PLLMEASCTRL field descriptions (continued)

Field Description
11–1 PLL Measure Internal Voltage
pll_meas_iv[10:0]
This bus enables or disables measuring various PLL node voltages and branch currents.
For information about the bit settings, see the pll_meas_iv[10:0] table.
0 PLL Measure Ground
pll_meas_gd
This bit connects or disconnects the ground signal to the atb_sense (analog test bus) bus.
0 Disconnect the ground signal from the atb_sense bus.

1 Connect the ground signal to the atb_sense bus.
34.7.20 PLL Phase and Bypass Control

(HDMI_PHY_PLLPHBYCTRL)
Register name: PLLPHBYCTRL
Address: 0x13
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pll_ph_sel_ck
Read
bypass_ppll
Reserved pll_ph_sel[9:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_PLLPHBYCTRL field descriptions

Field Description
- Reserved
11 Bypass Pre-PLL
bypass_ppll
This bit enables or disables bypassing the pre-PLL.
0 Disable bypassing pll_top by forcing refclk_mpll_ref low.

1 Enable bypassing pll_top by buffering refclk to refclk_mpll_ref.
10 PLL Phase Select Clock
pll_ph_sel_ck
This bit enables or disables latching the ph_sel[9:0] into a 9-bit DAC used in the phase mixer.

HDMI_PHY_PLLPHBYCTRL field descriptions (continued)

Field Description
0 Disable latching the pll_ph_sel[9:0] into the 9-bit DAC.
1 Enable latching the pll_ph_sel[9:0] into the 9-bit DAC.
pll_ph_sel[9:0] PLL Phase Select
This bus is a control word for the PLL's phase mixer that enables the phase of pll_cko_pm_p/m to be
varied ± 0.5 UI of the VCO frequency, which is 740-1,480 MHz.
34.7.21 Gear Shift, Reset Mode, and Power State Control

(HDMI_PHY_GRP_CTRL)
Register name: -
Address: 0x14
Bit 15 14 13 12 11 10 9 8
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read pll_gear_ mpll_gear_
Reserved pll_pwr_on pll_rst mpll_pwr_on mpll_rst
Write shift shift
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_GRP_CTRL field descriptions

Field Description
Override
- Reserved
5 PLL Power-On
pll_pwr_on
This bit is used to power on/off the PLL module.
Note: If the Override bit is set to 1, the working value is the Override bit value, not the registered value.
0 Power off PLL and draw minimal current, if the Override bit is 0.
1 Power on PLL and enable it to operate normally, if the Override bit is 0.
4 PLL Reset
pll_rst
This bit is used to place the MPLL in Reset mode.

HDMI_PHY_GRP_CTRL field descriptions (continued)

Field Description
0 Enable PLL to operate normally, if the Override bit is 0.
1 Place the PLL in Reset mode, if the Override bit is 0.
3 MPLL Power-On
mpll_pwr_on
This bit is used to power-on/off the MPLL module.
0 Power on MPLL and set all output clocks to DC levels, if the Override bit is 0.
1 Power off MPLL and enable it to operate normally, if the Override bit is 0.
2 MPLL Reset
mpll_rst
This bit is used to place the MPLL in Reset mode.
0 Enable MPLL to operate normally, if the Override bit is 0.

1 Place the MPLL in Reset mode, if the Override bit is 0.
1 PLL Gear Shift
pll_gear_shift
This bit enables or disables Rapid Locking mode, where the pll_gear_shift bit is asserted for 25 µs when
coming out of reset, then deasserted before clocks are valid.
0 Disable Rapid Locking mode, if the Override bit is 0.

1 Enable Rapid Locking mode, if the Override bit is 0.
0 MPLL Gear Shift
mpll_gear_shift
This bit enables or disables Rapid Locking mode, where the mpll_gear_shift bit is asserted for 25 µs when
coming out of reset, then deasserted before clocks are valid.
0 Disable Rapid Locking mode, if the Override bit is 0.

1 Enable Rapid Locking mode, if the Override bit is 0.
34.7.22 Gmp Control (HDMI_PHY_GMPCTRL)

Register name: GMPCTRL
Address: 0x15
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read pll_gmp_ mpll_gmp_
Reserved
Write cntrl[1:0] cntrl[1:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDMI_PHY_GMPCTRL field descriptions

Field Description
- Reserved
3–2 PLL gmp Control
pll_gmp_cntrl[1:0]
This bus controls the effective loop-filter resistance (equal) to increase or decrease PLL bandwidth and to
compensate for changes in the Divider module (n_cntrl).
00 TMDS rate up to 45.25 MHz

01 TMDS rate of 45.26-92.5 MHz
10 TMDS rate of 92.51-185 MHz
mpll_gmp_ MPLL gmp Control
cntrl[1:0]
This bus controls the effective loop-filter resistance (= 1/gmp) to increase or decrease MPLL bandwidth
and to compensate for changes in the Divider module (n_cntrl).
00 TMDS rate up to 45.25 MHz

01 TMDS rate of 45.26-92.5 MHz
34.7.23 MPLL Measure Control (HDMI_PHY_MPLLMEASCTRL)

Register name: MPLLMEASCTRL
Address: 0x16
NOTE
With the exception of mpll_atb_sense_sel, mpll_meas_iv[9],
and mpll_meas_iv[11], two or more of the previous register bits
must not be set to 1 simultaneously, because doing so can lead
to a hardware problem.
The table below describes the mpll_meas_iv[11:0] bit settings.
Table 34-19. mpll_meas_iv[11:0]
Effective Bit mpll_meas_iv[11:0] Description
Value
mpll_meas_iv[0] 000000000001 Connects the internal positive DCC control line (vc0p) to the atb_sense
line.
mpll_meas_iv[1] 000000000010 Connects the internal negative DCC control line (vc0m) to the atb_sense
line.

Table 34-19. mpll_meas_iv[11:0] (continued)

Effective Bit mpll_meas_iv[11:0] Description
Value
mpll_meas_iv[2] 000000000100 Connects VP supply voltage to the atb_sense line.
mpll_meas_iv[3] 000000001000 Connects vp_cp to the atb_sense line.
mpll_meas_iv[4] 000000010000 Connects the internal supply voltage of the VCO (ivco) to the atb_sense
line through a low-pass filter.
mpll_meas_iv[5] 000000100000 Connects the vp_cko voltage to the atb_sense line.
mpll_meas_iv[6] 000001000000 Connects the vpsf node to the atb_sense line.
mpll_meas_iv[7] 000010000000 Connects vref to the atb_sense line.
mpll_meas_iv[8] 000100000000 Connects vcntrl to the atb_sense line.
mpll_meas_iv[9] 001000000000 Enables the phase mixer and cko_pm_p/m.
mpll_meas_iv[10] 010000000000 Measures the voltage corresponding to the phase of the divide-by-5 output
(fb_clk) with respect to the phase of the mpll_ana input (ck_refclk_p).
mpll_meas_iv[11] 100000000000 Forces div_x1 low; therefore, bitclk_p/m is multiplexed to ck_ref_p/m
(normally, if n_cntrl = 00, ck0_p/m is multiplexed to ck_ref_p/m and DCC
loop is enabled.
Bit 15 14 13 12 11 10 9 8
Read
mpll_atb_
Reserved mpll_meas_iv[11:0]
sense_sel
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
mpll_meas_gd
Read
mpll_meas_iv[11:0]
Write
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_MPLLMEASCTRL field descriptions

Field Description
- Reserved
13 MPLL Analog Test Bus Sense Select
mpll_atb_sense_
This bit enables or disables internal signals of the PLL to be connected to the analog test bus. Without
sel
setting this bit, no measurements can be made on the atb_sense line.
Default (reset) value of mpll_atb_sense_sel is 0.
0 Disable the ability to measure internal DC signals on the atb_sense line in the PLL.
1 Enable the ability to measure internal DC signals on the atb_sense line in the PLL.

HDMI_PHY_MPLLMEASCTRL field descriptions (continued)

Field Description
12–1 MPLL Measure Internal Voltage
mpll_meas_
This bus enables or disables measuring various PLL node voltages and branch currents.
iv[11:0]
For information about the bit settings, see the mpll_meas_iv[11:0] table.
0 MPLL Measure Ground
mpll_meas_gd
This bit connects or disconnects the ground signal to the atb_sense (analog test bus) bus.
0 Disconnect the ground signal from the atb_sense bus.

1 Connect the ground signal to the atb_sense bus.
34.7.24 MPLL and PLL Phase, Scope Clock Select, and MUX
Clock Control (HDMI_PHY_MSM_CTRL)
Register name: -
Address: 0x17
The table below describes the cko_sel[1:0] bit settings. (The cko_sel[1:0] default value is
00.)
Table 34-20. cko_sel[1:0]
cko_sel[1:0] TMDS Clock Mode PLL and MPLL Output TMDS Clock on TMDS Channel
Mode
00 Non-Coherent Normal ck_ref_mpll_p/m (Pre-PLL out)
01 Off (PLL and MPLL are both off) Normal Off (No output TMDS clock)
10 Test (PHY in test mode) Normal PCLK (Input reference clock to HDMI 3D Tx
PHY)
11 Coherent Normal fb_clk (MPLL feedback clock)
00 Off (PLL and MPLL are both off) Bypass Off (No output TMDS clock)
01 Off (PLL and MPLL are both off) Bypass Off (No output TMDS clock)
10 Non-Coherent Bypass PCLK (Input reference clock to HDMI 3D Tx
PHY)
11 Coherent Bypass fb_clk (MPLL feedback clock)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read mpll_
scope
ph_
Reserved mpll_ph_sel[9:0] cko_sel[1:0] _ck_
sel_
sel
Write ck
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_MSM_CTRL field descriptions

Field Description
- Reserved
13 MPLL Phase Select Clock
mpll_ph_sel_ck
This bit enables or disables latching ph_sel[9:0] into a 9-bit DAC used in the phase mixer.
0 Disable latching mpll_ph_sel[9:0] into the 9-bit DAC.

1 Enable latching mpll_ph_sel[9:0] into the 9-bit DAC.
12–3 MPLL Phase Select
mpll_ph_sel[9:0]
This bus is a control word for the MPLL's phase mixer and enables the phase of pll_cko_pm_p /m to be
varied ± 0.5 UI of the VCO frequency, which has a range of 925-1,850 MHz.
2–1 Clock Output Select
cko_sel[1:0]
This bus selects the clock to be connected to the output TMDS clock channel.
Notes:
• Normal mode: The color depth or pixel repetition is required, which means that the PLL is powered
on (pll_pwr_on bit is set to 1) and the bypass_ppll bit is set to 0.
• Bypass mode: The color depth and the pixel repetition is not required, which means that the PLL is
powered off (pll_pwr_on bit is set to 0) and the bypass_ppll bit is set to 1.
For information about the cko_sel[1:0] bit settings and corresponding PLL/MPLL
modes, see the cko_sel[1:0] table.
0 Scope Clock Select
scope_ck_sel
Selects the clock to connect to the scope clock signal: the differential pll_cko_p/m or the differential
mpll_cko_p/m.
0 Connect the mpll_cko_pm_p/m to the clock scope (this clock has a range of 23.125-45.25 MHz)
where the mpll_meas_iv[9] bit must be high.
1 Connect the pll_cko_pm_p/m to the clock scope (this clock has a range of 23.125-45.25 MHz) where
the pll_meas_iv[9] bit must be high.
34.7.25 Scope, Comparator Result and Power Bad Status

(HDMI_PHY_SCRPB_STATUS)
Register name: -
Access type: Read-only

Address: 0x18
Value at reset: N/A
Bit 15 14 13 12 11 10 9 8
Read adc_val[9:0]
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
sup_comp_rt_result
tx_scope_out0
tx_scope_out1
tx_scope_out2
ck_scope_out
Read adc_val[9:0]
Reserved
Write
Reset 0 0 0 0 0 0 0 0

HDMI_PHY_SCRPB_STATUS field descriptions

Field Description
15–6 ADC/DAC bit word (analog signal value)
adc_val[9:0]
- Reserved
4 Support Comparator Resistance Termination Result
sup_comp_rt_
This bit represents the result of the comparison process.
result
0 The first input is greater than or equal to the second input.
1 The first input is less than the second input.
3 Scoping Value for Lane 0
tx_scope_out0
0 The driver output of lane 0 is not differential.
1 The driver output of lane 0 is differential.
tx_scope_out1
tx_scope_out2
0 Clock Scope Output Signal
ck_scope_out
0 The clock driver output is not differential.
1 The clock driver output is differential.
34.7.26 Transmission Termination (HDMI_PHY_TXTERM)

Register name: TXTERM
Address: 0x19
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read Reserved d_tx_term[2:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

HDMI_PHY_TXTERM field descriptions

Field Description
- Reserved
d_tx_term[2:0] Digital Transmission Termination
This bus defines the transmission termination (resistance) value, which is set by the HDMI controller. The
formula for the resistance value is:
R = 50 / (1 - 0.125 x d_tx_term)
This equation is valid only when d_tx_term equals 0-6.
• 000: 50 Ω
• 001: 56.14 Ω
• 010: 66.67 Ω
• 011: 80 Ω
• 100: 100 Ω
• 101: 133.33 Ω
• 110: 200 Ω
• 111: Open circuit
34.7.27 Power Sequence, TX Clock Alignment, Resistance

Calibration, Pattern Generator Skip Bit, and TMDS
Encoder Enable (HDMI_PHY_PTRPT_ENBL)
Register name: -
Address: 0x1A
Address: 0h base + 1Ah offset = 1Ah
Bit 15 14 13 12 11 10 9 8
Read
Override Reserved pg_skip_bit2
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
cko_word_enb
Read
ck_ref_enb
refclk_enb
tx_ck_align_
pg_skip_bit1 pg_skip_bit0 rcal_enb tx_ready
enb
Write
Reset 0 0 0 0 0 0 0 0

HDMI_PHY_PTRPT_ENBL field descriptions

Field Description
Override
- Reserved
8 Pattern Generator Skip Bit 2
pg_skip_bit2
This bit enables or disables pattern generator skip bit feature for channel 2.
0 Disable the pattern generator skip bit feature for the third transmitting channel, if the Override bit is 0.
1 Enable the pattern generator skip bit feature for the third transmitting channel, if the Override bit is 0.
pg_skip_bit1
0 Disable the pattern generator skip bit feature for the second transmitting channel, if the Override bit is
0.
1 Enable the pattern generator skip bit feature for the second transmitting channel, if the Override bit is
0.
pg_skip_bit0
0 Disable the pattern generator skip bit feature for the first transmitting channel, if the Override bit is 0.
1 Enable the pattern generator skip bit feature for the first transmitting channel, if the Override bit is 0.
5 Clock Reference Enable
ck_ref_enb
This bit powers up the clock alignment and the resistance calibration modules.
0 Powers down the clock alignment and the resistance calibration modules, if the Override bit is 0.
1 Powers up the clock alignment and the resistance calibration modules, if the Override bit is 0.
4 Resistance Calibration Enable
rcal_enb
This bit enables or disables the resistance clock alignment process.
0 Disable the resistance calibration FSM, if the Override bit is 0.

1 Enable the resistance calibration FSM, if the Override bit is 0.
3 Transmission Clock Alignment Enable
tx_ck_align_enb
This bit disables or enables the clock alignment FSM.
0 Disable transmission clock alignment FSM, if the Override bit is 0.

1 Enable transmission clock alignment FSM, if the Override bit is 0.
2 Transmission Ready
tx_ready
This bit indicates whether the PHY transmit driver is ready to transmit data.
0 PHY transmit driver is not ready to transmit data, if the Override bit is 0.
1 PHY transmit driver is ready to transmit data, if the Override bit is 0.
1 Output Clock Word Enable
cko_word_enb
This bit enables the output word clock.
0 Disable the output clock word, if the Override bit is 0.

1 Enable the output clock word, if the Override bit is 0

HDMI_PHY_PTRPT_ENBL field descriptions (continued)

Field Description
0 Reference Clock Enable
refclk_enb
This bit enables or disables the input reference clock.
0 Disable the input reference clock, if the Override bit is 0.

1 Enable the input reference clock, if the Override bit is 0.
34.7.28 Pattern Generator Mode (HDMI_PHY_PATTERNGEN)

Register name: PATTERNGEN
Address: 0x1B
Address: 0h base + 1Bh offset = 1Bh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pg_insert_err2
pg_insert_err1
pg_insert_err0
Read
Reserved pg_pat[9:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_PATTERNGEN field descriptions

Field Description
- Reserved
12 Pattern Generator Insert Error Two
pg_insert_err2
This bit enables or disables error insertion inside the generated pattern for channel 2.
0 Do not insert error inside generated pattern for the third transmit channel.
1 Insert error inside generated pattern for the third transmit channel.
11 Pattern Generator Insert Error One
pg_insert_err1
0 Do not insert error inside generated pattern for the second transmit channel.
1 Insert error inside generated pattern for the second transmit channel.
10 Pattern Generator Insert Error Zero
pg_insert_err0

HDMI_PHY_PATTERNGEN field descriptions (continued)

Field Description
0 Do not insert error inside generated pattern for the first transmit channel.
1 Insert error inside generated pattern for the first transmit channel.
pg_pat[9:0] Pattern Generator Generated Pattern
This bus carries the generated pattern from the Pattern Generator module.
34.7.29 The Soft-Reset and DAC Enable, Clock Alignment and

PG Mode (HDMI_PHY_SDCAP_MODE)
Register name: -
Address: 0x1C
Address: 0h base + 1Ch offset = 1Ch
Bit 15 14 13 12 11 10 9 8
Read pg_
Reserved pg_mode2[2:0]
Write mode1[2:0]
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read tx_ck_align_
pg_mode1[2:0] pg_mode0[2:0] adc_enb soft_reset
Write mode
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_SDCAP_MODE field descriptions

Field Description
- Reserved
11–9 Pattern Generator Mode 2
pg_mode2[2:0]
This bus is used to select the mode of the Pattern Generator module for channel 2.
000 Disable the Pattern Generator module.

001 Enable the Pattern Generator module and generate a sequence of patterns for the third channel
using LFSR 15 equation (for example, x15 + x14 + 1).
with the fixed word, which is saved inside the pg_pat[9:0] field of the PATTERNGEN register.
with DC-balanced word (for example, 0's or 1's and their inverted values).

HDMI_PHY_SDCAP_MODE field descriptions (continued)

Field Description
with fixed pattern using word of 0's word, 1's word, random word, the saved pattern inside the
pg_pat[9:0] field of the PATTERNGEN register, and the inverted pg_pat[9:0] values (for example, 9
bits of 0's, 9 bits of 1's, 3FF, pg_pat[9:0], ~ pg_pat[9:0]).
110 Reserved
111 Reserved
pg_mode1[2:0]

001 Enable the Pattern Generator module and generate a sequence of patterns for the second channel
010 second the Pattern Generator module and generate a sequence of patterns for the first channel
with the fixed word, which is saved inside the pg_pat[9:0] field of the PATTERNGEN register.
with DC-balanced word (for example, 0's or 1's and their inverted values).
with fixed pattern using word of 0's word, 1's word, random word, the saved pattern inside the
110 Reserved
111 Reserved
pg_mode0[2:0]

001 Enable the Pattern Generator module and generate a sequence of patterns for the first channel
010 Enable the Pattern Generator module and generate a sequence of patterns for the first channel
011 Enable the Pattern Generator module and generate a sequence of patterns for the first channel with
the fixed word, which is saved inside the pg_pat[9:0] field of the PATTERNGEN register.
DC-balanced word (for example, 0's or 1's and their inverted values).
fixed pattern using word of 0's word, 1's word, random word, the saved pattern inside the
110 Reserved
111 Reserved
2 Transmission Clock Alignment Mode
tx_ck_align_
This bit selects the Transmission Clock Alignment mode.
mode
0 Align the three lanes based on lane 1.
1 Align each of the three lanes separately in the following order: lane 2, lane 0, then lane 1.
1 Analog-to-Digital Converter Enable
adc_enb
This bit enables or disables the analog-to-digital converter.

HDMI_PHY_SDCAP_MODE field descriptions (continued)

Field Description
0 Disable the analog-to-digital converter.
1 Enable the analog-to-digital converter, which is used in the Resistance Calibration module.
0 Soft Reset
soft_reset
This bit enables or disables the soft-reset feature.
0 Do not perform a soft reset.

1 Perform a soft reset by resetting all the system FSMs except the I2C and Control Register modules.
34.7.30 Scope Mode register (HDMI_PHY_SCOPEMODE)

Register name: SCOPEMODE
Address: 0x1D
Address: 0h base + 1Dh offset = 1Dh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ck_scope_enb
scope_enb2
scope_enb1
scope_enb0
Read
Reserved scope_sample_cnt[9:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_SCOPEMODE field descriptions

Field Description
- Reserved
13 Clock Scope Enable
ck_scope_enb
This bit enables or disables the tracing of 1's on the clock channel.
0 Disable the tracing of 1's on the clock.

1 Enable the tracing of 1's on the clock.
12 Scope Enable 2
scope_enb2
This bit enables or disables the tracing of 1's on channel 2.
0 Disable the tracing of 1's on the third channel.

1 Enable the tracing of 1's on the third channel.
11 Scope Enable 1
scope_enb1

HDMI_PHY_SCOPEMODE field descriptions (continued)

Field Description
0 Disable the tracing of 1's on the second channel.
1 Enable the tracing of 1's on the second channel.
10 Scope Enable 0
scope_enb0
0 Disable the tracing of 1's on the first channel.

1 Enable the tracing of 1's on the first channel.
scope_sample_ Scope Sample Counter
cnt[9:0]
Indicates the number of samples that will be counted (should be multiple of the LFSR length). This count
includes only the LSB bits; if the LFSR15 was used, you must program the new bits under the 0x24
register.
34.7.31 Digital Transmission Mode (HDMI_PHY_DIGTXMODE)

Register name: DIGTXMODE
Address: 0x1E
dtb_select[6:0]
The dtb_select[6:0] encodings for the bit pairs are as follows:
Power Sequence
• 0x00: dtb[1] = pll_pwr_on and dtb[0] = pll_rst
• 0x01: dtb[1] = pll_pwr_on and dtb[0] = pll_gear_shift
• 0x02: dtb[1] = pll_pwr_on and dtb[0] = pll_drv_ana
• 0x03: dtb[1] = pll_pwr_on and dtb[0] = cko_word_enb
• 0x04: dtb[1] = pll_pwr_on and dtb[0] = tx_ready
• 0x05: dtb[1] = mpll_pwr_on and dtb[0] = mpll_rst
• 0x06: dtb[1] = mpll_pwr_on and dtb[0] = mpll_gear_shift
• 0x07: dtb[1] = mpll_pwr_on and dtb[0] = mpll_drv_ana
• 0x08: dtb[1] = mpll_pwr_on and dtb[0] = cko_word_enb
• 0x09: dtb[1] = mpll_pwr_on and dtb[0] = tx_ready
• 0x0A: dtb[1] = mpll_pwr_on and dtb[0] = tx_ser_div_en1
• 0x0B: dtb[1] = mpll_pwr_on and dtb[0] = tx_ser_clk_en1
• 0x0C: dtb[1] = ck_ref_enb and dtb[0] = refclk_enb
• 0x0D: dtb[1] = cko_word_enb and dtb[0] = refclk_enb

Transmission Clock Alignment

• 0x0E: Reserved
• 0x0F: dtb[1] = tx_ck_align_enb and dtb[0] = tx_ser_clk_kill0
• 0x10: dtb[1] = tx_ck_align_enb and dtb[0] = tx_ser_clk_kill1
• 0x11: dtb[1] = tx_ck_align_enb and dtb[0] = tx_ser_clk_kill2
• 0x12: dtb[1] = tx_ck_align_enb and dtb[0] = tx_ck_align_done
Resistance Calibration and Analog-to-Digital Converter
• 0x13: Reserved
• 0x14: dtb[1] = ck_rescal[6] and dtb[0] = ck_rescal[5]
• 0x17: dtb[1] = ck_rescal[0] and dtb[0] = sup_comp_mode
• 0x18: dtb[1] = sup_comp_rt_result and dtb[0] = sup_comp_rt_r
• 0x19: dtb[1] = sup_dac_n[7] and dtb[0] = sup_dac_n[6]
• 0x1A: dtb[1] = sup_dac_n[5] and dtb[0] = sup_dac_n[4]
• 0x1B: dtb[1] = sup_dac_n[3] and dtb[0] = sup_dac_n[2]
• 0x1C: dtb[1] = sup_dac_n[1] and dtb[0] = sup_dac_n[0]
• 0x1D: dtb[1] = sup_dac_th_n[2] and dtb[0] = sup_dac_th_n[1]
• 0x1E: dtb[1] = sup_dac_th_n[0] and dtb[0] = rescal_rep[6]
• 0x1F: dtb[1] = rescal_rep[5] and dtb[0] = rescal_rep[4]
• 0x20: dtb[1] = rescal_rep[3] and dtb[0] = rescal_rep[2]
• 0x21: dtb[1] = rescal_rep[1] and dtb[0] = rescal_rep[0]
• 0x22: dtb[1] = rcal_enb and dtb[0] = rcal_adc_done
• 0x23: dtb[1] = sup_comp_rt_pwron and dtb[0] = rcal_adc_done
• 0x24: Reserved
• 0x25: Reserved
• 0x26: Reserved
• 0x27: Reserved
TMDS Data Pattern
• 0x28: dtb[1] = tmds_data2[9] and dtb[0] = tmds_data2[8]
• 0x2A: dtb[1] = tmds_data2[7] and dtb[0] = tmds_data2[6]
• 0x2B: dtb[1] = tmds_data2[6] and dtb[0] = tmds_data2[5]
• 0x2C: dtb[1] = tmds_data2[5] and dtb[0] = tmds_data2[4]
• 0x2D: dtb[1] = tmds_data2[4] and dtb[0] = tmds_data2[3]
• 0x2E: dtb[1] = tmds_data2[3] and dtb[0] = tmds_data2[2]
• 0x2F: dtb[1] = tmds_data2[2] and dtb[0] = tmds_data2[1]

• 0x3A: dtb[1] = tmds_data1[1] and dtb[0] = tmds_data1[0]
• 0x3B: dtb[1] = tmds_data1[0] and dtb[0] = tmds_data0[9]
• 0x3C: dtb[1] = tmds_data0[9] and dtb[0] = tmds_data0[8]
• 0x3D: dtb[1] = tmds_data0[8] and dtb[0] = tmds_data0[7]
• 0x3E: dtb[1] = tmds_data0[7] and dtb[0] = tmds_data0[6]
• 0x3F: dtb[1] = tmds_data0[6] and dtb[0] = tmds_data0[5]
• 0x45: dtb[1] = tmds_data0[0] and dtb[0] = tx_ready
Pattern Generator
• 0x46: dtb[1] = tmds_data2[0] and dtb[0] = pg_dtb2
• 0x49: dtb[1] = pg_dtb2 and dtb[0] = pg_dtb0
• 0x4A: dtb[1] = pg_dtb1 and dtb[0] = pg_dtb0
• 0x4B: Reserved
• 0x4C: Reserved
• 0x4D: Reserved
• 0x4E: Reserved
• 0x4F: Reserved
Scope
• 0x50: dtb[1] = scope_enb2 and dtb[0] = scope_done2
• 0x53: dtb[1] = ck_scope_enb and dtb[0] = ck_scope_done
• 0x54: dtb[1] = scope_enb2 and dtb[0] = tx_scope_out2

• 0x57: Reserved
• 0x58: Reserved
• 0x59: Reserved
I2C
• 0x5A: dtb[1] = start_cond and dtb[0] = cregs_write (Not stored in the control
register.)
• 0x5B: dtb[1] = sda_pull_dn_n and dtb[0] = cregs_ack (Not stored in the control
register.)
• 0x5C: dtb[1] = cregs_read and dtb[0] = cregs_rd_data[0] (Not stored in the control
register.)
• 0x5D: Reserved
• 0x5E: Reserved
• 0x5F: Reserved
• 0x60: Reserved
• 0x61: Reserved
• 0x62: Reserved
• 0x63: Reserved
Rx Sense
• 0x64: dtb[1] = rx_sense of clock driver and dtb[0] = rx_sense of CH2's driver
• 0x65: dtb[1] = rx_sense of CH1's driver and dtb[0] = rx_sense of CH0's driver
• 0x66: -
Address: 0h base + 1Eh offset = 1Eh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read cko_
invert invert invert
word_ skip_ skip_ skip_
Reserved dtb_select[6:0] _ _ _
div_ bit2 bit1 bit0
data2 data1 data0
Write enb
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_DIGTXMODE field descriptions

Field Description
- Reserved
12–7 Debug Test Bus Select
dtb_select[6:0]
This field determines the pair of bits placed on the dtb[1:0] bus. These selected pairs of bits come from the
control register. The values that appear on dtb[1:0] are the current values actually stored in the control
register (not the override values) with the exception of I2C values, which are not stored in the control
register.

HDMI_PHY_DIGTXMODE field descriptions (continued)

Field Description
For information about the bit pairs, see dtb_select[6:0] .
6 Inverter Data 2
invert_data2
This bit enables or disables the inverting feature for the transmitted pattern on channel 2.
0 Disable the inverting feature on the third channel.

1 Enable the inverting feature on the third channel.
5 Inverter Data 1
invert_data1
0 Disable the inverting feature on the second channel.

1 Enable the inverting feature on the second channel.
4 Inverter Data 0
invert_data0
0 Disable the inverting feature on the first channel.

1 Enable the inverting feature on the first channel.
3 Clock Output Word Divider Enable
cko_word_div_
This bit enables or disables the output clock word divider.
enb
0 Disable the output clock divider.
1 Enable the output clock divider.
2 Skip Bit 2
skip_bit2
This bit enables or disables skipping of the ninth bit of the transmitted pattern on channel 2.
0 Disable the skipping feature on the third channel.

1 Enable the skipping feature on the third channel.
1 Skip Bit 1
skip_bit1
0 Disable the skipping feature on the second channel.

1 Enable the skipping feature on the second channel.
0 Skip Bit 0
skip_bit0
0 Disable the skipping feature on the first channel.

1 Enable the skipping feature on the first channel.
34.7.32 Scope, Transmission Clock Alignment, and Resistance

Calibration Set-on-Done Status
(HDMI_PHY_STR_STATUS)
Register name: -
Access type: Read/write/asynchronous set-on-done

Address: 0x1F
Address: 0h base + 1Fh offset = 1Fh
Bit 15 14 13 12 11 10 9 8
Read Reserved
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read rcal_adc_ tx_ck_align_ ck_scope_ scope_ scope_ scope_
Reserved
Write done done done done2 done1 done0
Reset 0 0 0 0 0 0 0 0
HDMI_PHY_STR_STATUS field descriptions

Field Description
- Reserved
5 Resistance Calibration Analog-to-Digital Converter Done
rcal_adc_done
This bit indicates the status of completing the resistance calibration FSM.
0 The resistance calibration FSM is not complete.

1 The resistance calibration FSM is complete.
4 Transmission Clock Alignment Done
tx_ck_align_done
This bit indicates the status of completing the transmission clock alignment FSM.
0 The transmission clock alignment FSM is not complete.

1 The transmission clock alignment FSM is complete.
3 Clock Scope Done
ck_scope_done
This bit indicates the status of tracing of 1's on the clock channel.
0 The tracing process on the clock channel is not complete.

1 The tracing process on the clock channel is complete.
2 Scope Done 2
scope_done2
This bit indicates the status of tracing of 1's on channel 2.
0 The tracing process on channel 2 is not complete.

1 The tracing process on channel 2 is complete.
1 Scope Done 1
scope_done1

0 Scope Done 0
scope_done0


34.7.33 Scope Counter on Channel 0 (HDMI_PHY_SCOPECNT0)

Register name: SCOPECNT0
Address: 0x20
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read scope_ones_cnt0[15:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_SCOPECNT0 field descriptions

Field Description
scope_ones_ Scope 1's Counter 0
cnt0[15:0]
This register carries the number of counted 1's on channel 0. If the LFSR15 was used to generate the
scope patterns, you must read the MSB bits under 0x25 register.

Address: 0x21
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
cnt1[15:0]

HDMI_PHY_SCOPECNT1 field descriptions (continued)

Field Description

Address: 0x22
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Field Description
cnt2[15:0]
34.7.36 Scope Counter on Clock Channel

(HDMI_PHY_SCOPECNTCLK)
Register name: SCOPECNTCK
Address: 0x23

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read ck_scope_ones_cnt[15:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_SCOPECNTCLK field descriptions

Field Description
ck_scope_ones_ Clock Scope 1's Counter
cnt[15:0]
This register carries the number of counted 1's on the clock channel. If the LFSR15 was used to generate
the scope patterns, you must read the MSB bits under 0x26 register.
34.7.37 Scope Sample Count MSB, Scope Sample Repetition

(HDMI_PHY_SCOPESAMPLE)
Register name: SCOPESAMPLE
Address: 0x24
Value at reset: 0x13c0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read scope_sample_rep[6:0] scope_sample_cnt[15:9]

Reserved
Write
Reset 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0
HDMI_PHY_SCOPESAMPLE field descriptions

Field Description
- Reserved
12–6 Scope Sample Repetition
scope_sample_
Number of repetitions made by the scope FSM. The total samples captured is scope_sample_rep x
rep[6:0]
scope_sample_cnt.
scope_sample_ Scope Sample Counter
cnt[15:9]
Indicates the number of samples that will be counted (should be multiple of the
LFSR length). These samples are the MSB bits only.

34.7.38 Scope Counter MSB Channel 0 and Channel 1

(HDMI_PHY_SCOPECNTMSB01)
Register name: SCOPECNTMSB01
Address: 0x25
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read scope_ones_cnt1[21:18] scope_ones_cnt0[21:16]

Reserved
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_SCOPECNTMSB01 field descriptions

Field Description
- Reserved
12–8 Scope 1's Counter 1
scope_ones_
This register carries the number of counted 1's on channel 1. These 1's are the
cnt1[21:18]
MSB bits only.
cnt0[21:16]
MSB bits only.
34.7.39 Scope Counter MSB Channel 2 and Clock Channel

(HDMI_PHY_SCOPECNTMSB2CK)
Register name: SCOPECNTMSB2CK
Address: 0x26

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read ck_scope_ones_cnt[21:16] scope_ones_cnt2[21:16]

Reserved
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HDMI_PHY_SCOPECNTMSB2CK field descriptions

Field Description
- Reserved
12–6 Clock Scope 1's Counter
ck_scope_ones_
This register carries the number of counted 1's on the clock channel. These 1's are the MSB bits only.
cnt[21:16]
cnt2[21:16]
MSB bits only.
34.8 Appendix A: Driver Voltage Level Configuration

This appendix describes the driver voltage level configuration.
This configuration depends on the source termination value, the driver pre-emphasis
settings, and the target signal voltage level swing.
A correct configuration must be set to meet both eye diagram mask and the specified high
and low signal voltage levels.
To correctly configure the driver voltage level, the following parameters and signals
(represented through their symbol) must be taken into consideration:
• VPHRXTERM = 3.3 V -> 3.3-V supply rail connected to HDMI PHY sink termination
resistors
• RXTERM = 50 Ω -> HDMI PHY sink termination resistors
Control Register Signal Symbol
0x19 d_tx_temp[2:0] RTERM
0x0E sup_tx_lvl[4.:0] TXLVL
0x0E sup_ck_lvl[4.:0] CKLVL
0x09 tx_symon SYMON
0x09 tx_traon TRAON
0x09 tx_trbon TRBON

Appendix B
The following table defines the pre-emphasis factor (PREEMPH) to be used in the
information that follows.
SYMON TRAON TRBON PREEMPH
0 0 0 -
1 0 0 0.00
1 0 1 0.08
1 1 0 0.17
1 1 1 0.25
The following equations can be used to calculate-for a certain signal voltage swing
(VSWING) and PHY configuration (PREEMPH, RTERM)-the signal's high and low
voltage levels (VHI, VLO).
VHI = VLO + VSWING
TXLVL = CKLVL = [ 0.772 - ( VPHRXTERM - VLO ) ] / 0.01405
For a certain termination value and pre-emphasis configuration (factor), users input only
the VSWING value. With this data, users can obtain the respective VHI and VLO DC
levels and the TXLVL and CKLVL configuration to apply to the PHY.
Lower TXLVL/CKLVL values result in higher signal amplitudes, while higher TXLVL/
CKLVL values result in lower signal amplitudes.
Values for VSWING, VHI, and VLO must be within HDMI 1.4a specification limits. The
table below provides driver voltage level settings for some example scenarios.
Table 34-21. Example Driver Voltage Level Settings
RTERM SYMON TRAON TRBON VHI (V) VLO (V) VSWING TXLVL TXLVL CKLVL CKLVL
(V) (BIN) (BIN)
100 1'b1 1'b0 1'b0 3.200 2.800 0.400 19 10011 19 10011
100 1'b1 1'b0 1'b0 3.175 2.675 0.500 10 01010 10 01010
100 1'b1 1'b0 1'b1 3.107 2.607 0.500 6 00110 6 00110
133 1'b1 1'b0 1'b0 3.225 2.825 0.400 21 10101 21 10101
133 1'b1 1'b0 1'b0 3.206 2.706 0.500 13 01101 13 01101
133 1'b1 1'b0 1'b1 3.143 2.643 0.500 8 01000 8 01000
34.9 Appendix B
This appendix describes the PLL/MPLL configurations that must be made for each video
mode of operation.

The PLL/MPLL configurations are divided in two distinct sections. Power-Up

Requirements describes how to configure the PLL/MPLL mode of operation, and PLL/
MPLL Generic Configuration Settings describes all the settings required to configure the
PLL/MPLL for each specific video mode.
34.9.1 Single or Two-PLL in Coherent or Non-Coherent Mode of

Operation
Table 34-22. Single or Two-PLL in Coherent or Non-Coherent Mode of Operation
Mode of Operation bypass_ppll cko_sel<1> cko_sel<0>
Register address: Register address: Register address:
0013: Bit 11 0017: Bit 2 0017: Bit 1
Two-PLL Non-Coherent (default) 0 0 0
Two-PLL Coherent 0 1 1
Single-PLL Non-Coherent 1 1 0
Single-PLL Coherent 1 1 1
NOTE
Single-PLL Coherent and Non-Coherent modes can be set for
only video formats with no pixel repetition and color depth
equal to 8 bits.
34.9.2 PLL/MPLL Generic Configuration Settings

Each supported video format can be referred to by its input pixel clock frequency, pixel
repetition, and color depth in bits.
The table beblow provides all the PLL/MPLL settings necessary to completely configure
the blocks for any supported video format.
Table B-2 PLL/MPLL Generic Configuration Settings
Divider Settings

Appendix B
Table 34-23. PLL/MPLL Generic Configuration Settings

Divider Settings PLL Charge Pump Settings MPLL Charge Pump Settings
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 0: 0: 0: 0: 0: 0: 5: 5: 0: 0: 0: 0: 0: 0: 5: 5:
Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi
t t t t t t t t t t t t t t t t t t t t t t t t t t t
1 1 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 3 2 1 1 9 8 7 6 1 0
4 3 1 0
Pi Pi C pr pr m m pl pl pi pi pi cl cl pl pl pl pl pl pl pl pl m m m m m m m m
x x ol e e pl pl l_ l_ x x x r_ r_ l_ l_ l_ l_ l_ l_ l_ l_ pl pl pl pl pl pl pl pl
el el or p p l_ l_ n n el el el d d pr pr pr in in in g g l_ l_ l_ l_ l_ l_ l_ l_
Cl R D _ _ n n _ _ _r _r _r pt pt o o o t_ t_ t_ m m pr pr pr in in in g g
o e e di di _ _ c c e e e h h p p p c c c p p o o o t_ t_ t_ m m
c p pt v v c c nt nt p p p < < _ _ _ nt nt nt _ _ p p p c c c p p
k et h < < nt nt rl rl < < < 1 0 c c c rl rl rl c c _ _ _ nt nt nt _ _
( iti in 1 0 rl rl < < 2 1 0 > > nt nt nt < < < nt nt c c c rl rl rl c c
M o Bi > > < < 1 0 > > > rl rl rl 2 1 0 rl rl nt nt nt < < < nt nt
H n ts 1 0 > > < < < > > > < < rl rl rl 2 1 0 rl rl
z) > > 2 1 0 1 0 < < < > > > < <
> > > > > 2 1 0 1 0
> > > > >
13 2 8 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0
.5
13 2 10 0 1 1 1 1 1 1 0 0 0 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0
.5
13 2 12 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0
.5
13 2 16 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1
.5
13 4 8 0 0 1 0 1 1 0 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1
.5
13 4 10 0 1 1 0 1 1 1 0 1 0 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1
.5
13 4 12 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 1
.5
13 4 16 1 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 1 0
.5
18 3 8 0 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1
18 3 16 1 1 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 1 0
24 1 8 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0
.
17
5
24 1 10 0 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0
.
17
5


(continued)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 0: 0: 0: 0: 0: 0: 5: 5: 0: 0: 0: 0: 0: 0: 5: 5:
1 1 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 3 2 1 1 9 8 7 6 1 0
4 3 1 0
H n ts 1 0 > > < < < > > > < < rl rl rl 2 1 0 rl rl
z) > > 2 1 0 1 0 < < < > > > < <
> > > > > 2 1 0 1 0
> > > > >
24 1 12 1 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0
.
17
5
24 1 16 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1
.
17
5
27 1 8 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0
27 1 10 0 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0
27 1 12 1 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0
27 1 16 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1
27 2 8 0 0 1 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1
27 2 10 0 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1
27 2 12 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 1
27 2 16 1 1 0 1 1 0 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0
27 4 8 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0
27 4 10 0 1 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0 1 0
27 4 12 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 1 0
27 4 16 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1
36 1 8 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0
36 1 16 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1
50 1 8 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1
,
35

Appendix B

(continued)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 0: 0: 0: 0: 0: 0: 5: 5: 0: 0: 0: 0: 0: 0: 5: 5:
1 1 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 3 2 1 1 9 8 7 6 1 0
4 3 1 0
H n ts 1 0 > > < < < > > > < < rl rl rl 2 1 0 rl rl
z) > > 2 1 0 1 0 < < < > > > < <
> > > > > 2 1 0 1 0
> > > > >
50 1 10 0 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1
,
35
50 1 12 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1
,
35
50 1 16 1 1 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
,
35
50 2 8 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
,
35
50 2 10 0 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0
,
35
50 2 12 1 0 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0
,
35
50 2 16 1 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 1
,
35
54 1 8 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1
54 1 10 0 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1
54 1 12 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1
54 1 16 1 1 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
54 2 8 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
54 2 10 0 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0


(continued)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 0: 0: 0: 0: 0: 0: 5: 5: 0: 0: 0: 0: 0: 0: 5: 5:
1 1 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 3 2 1 1 9 8 7 6 1 0
4 3 1 0
H n ts 1 0 > > < < < > > > < < rl rl rl 2 1 0 rl rl
z) > > 2 1 0 1 0 < < < > > > < <
> > > > > 2 1 0 1 0
> > > > >
54 2 12 1 0 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0
54 2 16 1 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 1
58 1 8 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1
.4
58 1 10 0 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1
.4
58 1 12 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1
.4
58 1 16 1 1 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
.4
72 1 8 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1
72 1 10 0 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1
72 1 12 1 0 0 1 0 1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
72 1 16 1 1 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0
74 1 8 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1
.
25
74 1 10 0 1 0 1 0 1 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 1 1 0 1 1 0
.
25
74 1 12 1 0 0 1 0 1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
.
25
74 1 16 1 1 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0
.
25

Appendix B

(continued)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 0: 0: 0: 0: 0: 0: 5: 5: 0: 0: 0: 0: 0: 0: 5: 5:
1 1 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 3 2 1 1 9 8 7 6 1 0
4 3 1 0
H n ts 1 0 > > < < < > > > < < rl rl rl 2 1 0 rl rl
z) > > 2 1 0 1 0 < < < > > > < <
> > > > > 2 1 0 1 0
> > > > >
10 1 8 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
8
10 1 10 0 1 0 1 0 1 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
8
10 1 12 1 0 0 1 0 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0
8
10 1 16 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 1 0 0 1 0 0 1 1
8
11 1 8 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
8,
8
11 1 10 0 1 0 1 0 1 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0
8,
8
11 1 12 1 0 0 1 0 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0
8,
8
11 1 16 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 1 0 0 1 0 0 1 1
8,
8
14 1 8 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0
4
14 1 10 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 1 0 1 1 1
4
14 1 12 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 0 0 1 1
4
14 1 16 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1
4


(continued)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 6: 0: 0: 0: 0: 0: 0: 5: 5: 0: 0: 0: 0: 0: 0: 5: 5:
1 1 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 3 2 1 1 9 8 7 6 1 0
4 3 1 0
H n ts 1 0 > > < < < > > > < < rl rl rl 2 1 0 rl rl
z) > > 2 1 0 1 0 < < < > > > < <
> > > > > 2 1 0 1 0
> > > > >
14 1 8 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0
8.
5
14 1 10 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 1 0 1 1 1
8.
5
14 1 12 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 0 0 1 1
8.
5
14 1 16 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1
8.
5
21 1 8 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0
6
21 1 10 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 1 0 1 1 1
6
21 1 12 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 0 0 1 1
6
34.10 Appendix C: 3D Video Formats

3D video formats are created from any of the supported VICs. The 3D structure in which
the frames are organized determines the way data is transferred.

Appendix C: 3D Video Formats
The 3D video format is indicated using the VIC in the AVI InfoFrame (indicating one of
the 2D formats defined in the CEA-861-D standard) in conjunction with the 3D_Structure
field in the HDMI vendor-specific InfoFrame.
For Side-by-Side (Half) and Top-and-Bottom 3D structures, pixel clock frequency is
equal to the original VIC pixel clock frequency.
For the L+depth+GFX+GFX-depth 3D structure, pixel clock frequency is equal to 4x the
original VIC pixel clock frequency.
For other 3D structures, pixel clock frequency is equal to 2x the original VIC pixel clock
frequency.
The following table summarizes the original 2D VIC pixel clock frequencies required to
support the 3D structures.
Table 34-24. 2D VIC Pixel Clock Frequencies Required to Support 3D Structures
3D Structure 2D Pixel Clock Frequency
0000 (Frame Packing) 2x 2D pixel clock frequency
0001 (Field alternative) 2x 2D pixel clock frequency
0010 (Line alternative) 2x 2D pixel clock frequency
0011 (Side-by-Side (Full)) 2x 2D pixel clock frequency
0100 (L + depth) 2x 2D pixel clock frequency
0101 (L + depth + GPX + GFX-depth) 4x 2D pixel clock frequency
0110 (Top-and-Bottom) 2D pixel clock frequency
1000 (Side-by-Side (Half)) 2D pixel clock frequency
VIC-specific PLL/MPLL configurations apply to Side-by-Side (Half) and Top-and-

Bottom 3D structures. To obtain the PLL/MPLL configuration for a specific VIC used
within a 3D structure, see PLL/MPLL Generic Configuration Settings. Each
configuration corresponds to a specific video format's pixel clock, pixel repetition, and
color depth combination.
Example:
VIC 32: No pixel repetition, PCLK = 74.25 MHz, CD = 8,10,12,16
VIC 32 within 3D structure:
• Side-by-Side (Half) 3D structure (same pixel clock frequency): Same PLL/MPLL
configuration as for VIC 32.
• Frame Packing (doubled pixel clock frequency): PLL/MPLL configuration
corresponds to a row in Table 34-23 with the following: no pixel repetition, PCLK =
148.5 MHz, CD = 8,10,12,16.

For VICs where PCLK = 148.5 MHz, no color depth is supported for 3D video format,
because the pixel clock frequency would be greater than 340 MHz.
Table 34-25 provides examples of primary 3D video format timings, and Table 34-26
provides examples of other 3D video format timings. Secondary 3D video format timings
can be found in the HDMI specification.
Table 34-25. Primary 3D Video Format Timings
VIC Video Vertical Refresh 2D Pixel Clock 3D Structure 3D Pixel Clock
Rate (Hz) (MHz) (MHz)
4 1,280x720p 59.94/60 74.25 0000 (Frame Packing) 148.50
4 1,280x720p 59.94/60 74.25 0110 (Top-and-Bottom) 74.25
4 1,280x720p 59.94/60 74.25 1000 (Side-by-Side (Half)) 74.25
19 1,280x720p 50 74.25 0000 (Frame Packing) 148.50
19 1,280x720p 50 74.25 0110 (Top-and-Bottom) 74.25
19 1,280x720p 50 74.25 1000 (Side-by-Side (Half)) 74.25
60 1,280x720p 23.97/24 58.40 0000 (Frame Packing) 118.8
62 1,280x720p 29.97/30 74.25 0000 (Frame Packing) 148.50
5 1,920x1,080i 59.94/60 74.25 0000 (Frame Packing) 148.50
5 1,920x1,080i 59.94/60 74.25 1000 (Side-by-Side (Half)) 74.25
20 1,920x1,080i 50 74.25 0000 (Frame Packing) 148.50
20 1,920x1,080i 50 74.25 1000 (Side-by-Side (Half)) 74.25
32 1,920x1,080p 23.98/24 74.25 0000 (Frame Packing) 148.50
32 1,920x1,080p 23.98/24 74.25 0110 (Top-and-Bottom) 74.25
32 1,920x1,080p 23.98/24 74.25 1000 (Side-by-Side (Half)) 74.25
34 1,920x1,080p 29.98/30 74.25 0000 (Frame Packing) 148.50
34 1,920x1,080p 29.98/30 74.25 0110 (Top-and-Bottom) 74.25
16 1,920x1,080p 59.94/60 148.50 0110 (Top-and-Bottom) 148.50
31 1,920x1,080p 50 148.50 0110 (Top-and-Bottom) 148.50
Table 34-26. Examples of Other 3D Video Formats

VIC Video Vertical Refresh Rate 2D Pixel Clock 3D Structure 3D Pixel Clock
(Hz) (MHz) (MHz)
5 1,920x1,080i 59.94/60 74.25 0001 (Field alternative) 148.5
20 1,920x1,080i 50 74.25 0001 (Field alternative) 148.5
16 1,920x1,080p 59.94/60 148.50 0010 (Line alternative) 297
31 1.920x1,080p 50 148.50 0010 (Line alternative) 297
16 1,920x1,080p 59.94/60 148.50 0011 (Side-by-Side (Full)) 297
31 1,920x1,080p 50 148.50 0011 (Side-by-Side (Full)) 297
19 1,280x720p 50 74.25 0100 (L + depth) 148.5
19 1,280x720p 50 74.25 0101 (L + depth + GFX + 297
GFX-depth)

Appendix C: 3D Video Formats

Chapter 35
I2C Controller (I2C)
35.1 Overview
This chapter describes block-level operation and programming of I2C. The chapter is
intended for a block-driver software developer. To understand how the block is integrated
at the SoC level, a system software developer should see discussions of the block in the
appropriate SoC-level chapter(s).
References: This document assumes an understanding of the following document:
• The I2C Bus Specification, Version 2.1, by Philips Semiconductor
The Inter IC (I2C) provides functionality of a standard I2C slave and master. The I2C is
designed to be compatible with the standard NXP I2C bus protocol.
NOTE
Three independent I2C channels are available.
I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
exchange, minimizing the interconnection between devices. This bus is suitable for
applications requiring occasional communications over a short distance between many
devices. The flexible I2C standard allows additional devices to be connected to the bus
for expansion and system development. See the connection diagram in the figure below.

Overview
+Vdd
Pull-up
Rp resistors Rp
I2Cn_SDA (Serial Data line)
I2Cn_SCL (Serial Clock line)
I2Cn_SCL (output) I2Cn_SDA (output) I2Cn_SCL (output) I2Cn_SDA (output)
I2Cn_SCL (input) I2Cn_SDA (input) I2Cn_SCL (input) I2Cn_SDA (input)
Device 1 Device 2
Figure 35-1. Connection of devices to I2C bus
The I2C interface speed is dependent on the I2C bus loading and timing characteristics.
For pin requirement details, see The I2C Bus Specification. The I2C system is a true
multimaster bus including arbitration and collision detection that prevents data corruption
if multiple devices attempt to control the bus simultaneously. This feature supports
complex applications with multiprocessor control and can be used for rapid testing and
alignment of end products through external connections to an assembly-line computer.
The figure below shows the block diagram of I2C.

Chapter 35 I2C Controller (I2C)
Peripheral Bus
Interrupt Request Address Data
Peripheral Bus Clock Domain
Address Decode Data MUX
I2C Frequency I2C Control I2C Status I2C Data I2C Address
Divider Register Register Register I/O Register Register
(I2C_IFDR) (I2C_I2CR) (I2C_I2SR) (I2C_I2DR) (I2C_IADR)
In / Out
Clock Data
Control Shift
Start, Stop, Register
and
Arbitration
Control
Input Address
Sync Compare
Module Clock Domain
I2Cn_SCL I2Cn_SDA
Signals Connected Off-Chip
Figure 35-2. I2C block diagram
35.1.1 Features
The I2C has the following key features:
• Compatibility with I2C bus standard
• Multimaster operation
• Software programmability for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave

External Signals
• Calling address identification interrupt

• Start and stop signal generation/detection
• Repeated Start signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
35.1.2 Modes and operations

The I2C operates primarily in two functional modes: Standard mode and Fast mode.
• In Standard mode, I2C supports the data transfer rates up to 100 kbits/s.
• In Fast mode, data transfer rates up to 400 kbits/s can be achieved. Per block
operation, there is no special configuration required for Fast or Standard mode. It is
the data transfer rate that distinguishes Standard and Fast mode.
This section discusses I2C signals that connect off-chip.

For I2C compliance, all devices connected to the I2Cn_SCL and I2Cn_SDA signals must
have open-drain or open-collector outputs. The logic AND function is implemented on
both lines with external pull-up resistors.
Inputs of I2Cn_SCL and I2Cn_SDA also need to be manually enabled by setting the
SION bit in the IOMUX after the corresponding PADs are selected as I2C function.
The table below describes all I2C signals that connect off-chip.
Table 35-1. I2C External Signals
I2C1_SCL (SCL) Serial Clock CSI0_DAT9 ALT4 IO
EIM_D21 ALT6
I2C1_SDA (SDA) Serial Data CSI0_DAT8 ALT4 IO
EIM_D28 ALT1
I2C2_SCL (SCL) Serial Clock EIM_EB2 ALT6 IO
KEY_COL3 ALT4
I2C2_SDA (SDA) Serial Data EIM_D16 ALT6 IO
KEY_ROW3 ALT4
I2C3_SCL (SCL) Serial Clock EIM_D17 ALT6 IO
GPIO_3 ALT2

Table 35-1. I2C External Signals (continued)

GPIO_5 ALT6
I2C3_SDA (SDA) Serial Data EIM_D18 ALT6 IO
GPIO_6 ALT2
GPIO_16 ALT6
35.3 Clocks
There are two input clocks for I2C.
The following table describes the clock sources for I2C. Please see Clock Controller
Table 35-2. I2C Clocks
ipg_clk_patref perclk_clk_root Module clock
• Peripheral clock: This clock is used for peripheral bus register read/writes.
• Module clock: This is the functional clock of the I2C. The serial bit clock frequency
is derived from the module clock. The module clock and peripheral clocks are
synchronous with each other. The minimum frequency of the module clock should be
12.8 MHz for Fast mode to achieve 400-kbps operation.

35.4.1 I2C system configuration

After a reset, the I2C defaults to Slave Receive operations. Thus, when not operating as a
master or responding to a slave transmit address, the I2C defaults to the Slave Receive
state.
For exceptions, see Initialization sequence.

NOTE
The I2C is designed to be compatible with the PhilipsTM I2C
bus protocol. For information on system configuration,
protocol, and restrictions, see the I2C Bus Specification, version
2.1, by Philips Semiconductors. The I2C supports Standard and
Fast modes only.
35.4.2 Arbitration procedure

If multiple devices simultaneously request the bus, the bus clock is determined by a
synchronization procedure in which the low period equals the longest clock-low period
among the devices, and the high period equals the shortest. A data arbitration procedure
determines the relative priority of competing devices.
A device loses arbitration if it sends logic high while another sends logic low; it
immediately switches to Slave Receive mode and stops driving I2Cn_SDA. In this case,
the transition from master to Slave mode does not generate a Stop condition. Meanwhile,
hardware sets the arbitration lost bit in the I2C Status register (I2C_I2SR[IAL] to indicate
loss of arbitration).

35.4.3 Clock synchronization

Because wire-AND logic is used, a high-to-low transition on SCL affects devices
connected to the bus. Devices start counting their low period when the master drives SCL
low. When a device clock goes low, it holds SCL low until the Clock High state is
reached. However, the low-to-high change in this device clock may not change the state
of SCL if another device clock is still in its low period. Therefore, the device with the
longest low period holds the synchronized clock SCL low.
Devices with shorter low periods enter a High Wait state during this time (see Figure
35-3). When all devices involved have counted off their low periods, the synchronized
clock SCL is released and pulled high. There is then no difference between device clocks
and the state of SCL, so all of the devices start counting their high periods. The first
device to complete its high period pulls SCL low again.
Wait Start counting high period
SCL1
SCL2
SCL
Internal Counter Reset
Figure 35-3. Synchronized clock SCL
35.4.4 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfers. Slave
devices can hold SCL low after completing one byte transfer (9 bits). In such a case, the
clock mechanism halts the bus clock and forces the master clock into a Wait state until
the slave releases SCL.

35.4.5 Clock stretching

Slaves can use the clock synchronization mechanism to slow down the transfer bit rate.
After the master has driven SCL low, the slave can drive SCL low for the required period
and then release it. If the slave SCL low period is longer than the master SCL low period,
the resulting SCL bus signal low period is stretched.
35.4.6 Peripheral bus accesses

I2C is a 16-bit block. Only half-word accesses should be performed to the block.
35.4.7 Generation of transfer error on IP bus

If an address is received on the peripheral slave bus interface but it is not implemented,
an access error is generated.
35.4.8 Reset
The I2C can be reset in the following ways:
• Global reset: A hard asynchronous reset of the whole I2C
• Software reset: An internal reset for the whole I2C (except for I2C_IADR and
I2C_IFDR registers) initiated by deasserting the I2C_I2CR[IEN] bit
35.4.9 Interrupts
There is only one interrupt from the block, which is enabled by setting the
I2C_I2CR[IIEN] bit.
The interrupt is generated in any one of the following conditions:
• One byte transfer is completed (the interrupt is set at the falling edge of the ninth
clock).
• An address is received that matches its own specific address in Slave Receive mode.
• Arbitration is lost.

35.4.10 Byte order

The block only supports the Little-Endian mode.
35.5 Initialization
NOTE
Ensure the input select pins for IOMUXC are configured
correctly for I2C.
35.5.1 Initialization sequence

Before the interface can transfer serial data, registers must be initialized, as listed here.
1. Set the data sampling rate (I2C_IFDR[IC] to obtain SCL frequency from the system
bus clock.
2. Update the address in the (I2C_IADR) to define its slave address (address can range
from 0 to 0x7f).
3. Set the I2C enable bit (I2C_I2CR[IEN]) to enable the I2C bus interface system.
4. Modify the bits in the I2C_I2CR to select Master/Slave mode, Transmit/Receive
mode, and Interrupt-Enable or not.
35.5.2 Generation of Start

After completion of the initialization procedure, serial data can be transmitted by
selecting the Master Transmit mode. On a multimaster bus system, the busy bus
(I2C_I2SR[IBB]) must be tested to determine whether the serial bus is free. If the bus is
free (IBB = 0), the Start signal and the first byte (the slave address) can be sent. The data
written to the data register comprises the address of the desired slave and the LSB
indicates the transfer direction.
The free time between a Stop and the next Start condition is built into the hardware that
generates the Start cycle. Depending on the relative frequencies of the system clock and
the SCL period, it may be necessary to wait until the I2C is not busy after writing the
calling address to the data register (I2C_I2DR), before proceeding to load data into the
data register (I2C_I2DR).

Initialization
35.5.3 Post-transfer software response

Sending or receiving a byte sets the data transferring bit (I2C_I2SR[ICF]), which
indicates one byte of communication is finished. Upon completion, the interrupt status
(I2C_I2SR[IIF]) is also set. An external interrupt is generated if the interrupt enable
(I2C_I2CR[IIEN]) is set. The software must first clear the interrupt status
(I2C_I2SR[IIF]) in the interrupt routine.
See the flow chart in Figure 35-5.
The data transferring bit (I2C_I2SR[ICF]) is cleared either by reading from I2C_I2DR in
Receive mode or by writing to this register in Transmit mode.
The software can service the I2C I/O in the main program by monitoring the interrupt
status (I2C_I2SR[IIF]) if the interrupt enable is deasserted. In this case, the interrupt
status should be polled in the data transferring bit (I2C_I2SR[ICF]) because the operation
is different when arbitration is lost.
When an interrupt occurs at the end of the address cycle, the master is always in Transmit
mode; that is, the address is sent. If Master Receive mode is required, then
I2C_I2CR[MTX] should be toggled and a dummy read of the I2C_I2DR register must be
executed to trigger receive data.
During Slave-mode address cycles (I2C_I2SR[IAAS] = 1), the slave read/write bit
I2C_I2SR[SRW] is read to determine the direction of the next transfer. The transmit/
receive bit (I2C_I2CR[MTX]) should also be programmed accordingly. For Slave-mode
data cycles (IAAS = 0), SRW is invalid. MTX should be read to determine the current
transfer direction.
35.5.4 Generation of Stop

A data transfer ends when the master signals a Stop, which can occur after all data is sent.
For a master receiver to terminate a data transfer, it must inform the slave transmitter by
not acknowledging the last data byte. This is done by setting the transmit acknowledge
bit (I2C_I2CR[TXAK]) before reading the next-to-last byte. Before the last byte is read,
a Stop signal must be generated.
35.5.5 Generation of Repeated Start

After the data transfer, if the master still requires the bus, it can signal another Start
followed by another slave address without signaling a Stop.

35.5.6 Slave mode

In the slave interrupt service routine (see Figure 35-5), the block addressed as slave bit
(IAAS) should be tested to check if a calling of its own address has just been received. If
IAAS is set, software should set the Transmit/Receive mode select bit (I2C_I2CR[MTX])
according to the I2C_I2SR[SRW]. Writing to the I2C_I2CR clears the IAAS
automatically. The only time IAAS is read as set is from the interrupt at the end of the
address cycle where an address match occurred; interrupts resulting from subsequent data
transfers will have IAAS cleared. A data transfer can now be initiated by writing
information to I2C_I2DR for slave transmits, or read from I2C_I2DR in Slave Receive
mode. A dummy read of I2C_I2DR in Slave Receive mode releases SCL, allowing the
master to send data.
In the slave transmitter routine, the receive acknowledge bit (I2C_I2SR[RXAK]) must be
tested before sending the next byte of data. Setting RXAK means an end-of-data signal
from the master receiver, after which the software must switch it from Transmit to
Receiver mode. Reading the data register (I2C_I2DR) then releases SCL so the master
can generate a Stop signal.
35.5.7 Arbitration lost

If several devices try to engage the bus at the same time, one becomes master. Hardware
immediately switches devices that lose arbitration to Slave Receive mode. Data output to
12Cn_SDA stops, but 12Cn_SCL is still generated until the end of the byte during which
arbitration is lost. An interrupt occurs at the falling edge of the ninth clock of this transfer
if the arbitration is lost (I2C_I2SR[IAL] = 1), and the Slave mode is selected
(I2C_I2CR[MSTA] = 0).
See the flow chart in Figure 35-5.
If a device that is not a master tries to transmit or do a Start, hardware inhibits the
transmission, clears MSTA without signaling a Stop, generates an interrupt to the Arm
platform, and sets I2C_I2SR[IAL] to indicate a failed attempt to engage the bus. When
considering these cases, the slave service routine should first test I2C_I2SR[IAL], and the
software should clear it if it is set.
For Multimaster mode, when an I2C is enabled when the bus is busy and asserts Start, the
I2C_I2SR[IAL] bit gets set only for 12Cn_SDA=0, 12Cn_SCL=0/1, 12Cn_SDA=1, and
12Cn_SCL=0; but not for 12Cn_SDA=1 and I2Cn_SCL=1, which is the equivalent of
Bus Idle state.

Initialization
EXIT ENTER
ENABLE
IBB=0
IFDR IBB=0
I2SR=0
IEN=IIEN=1
START
MSTA=1
IBB=1 MTX=1
IBB=1
TIMEOUT
SEND
DATA
I2C Interrupt Handler
TIMEOUT I2DR
sr = I2SR (status)
IBB=1
ERROR cr = I2CR (control)
HANDLER Clear I2SR
If IAL=1 Then Arbitration Lost!
MSTA=0
MTX=0 If RXAK=0 Then TX Success
IIF=1
IBB=0 OR
TIMEOUT
IAL=1
INTERRUPT
=0
RXAK=1
AK
DISABLE
RX
ICF=1
I2CR=0
TX
COMPLETE
STOP
MSTA=0
MTX=0
No More Data
Figure 35-4. I2C Programming state diagram

Clear
IIF
Y Master N
Mode
TX RX Y Arbitration
TX / RX
Lost
Last Byte Y Clear IAL

Transmitted
N
Last
N Y N Y
RXAK = 0 Byte to be IAAS = 1 IAAS = 1
Read Address Data
Y N Cycle Y N Cycle
End of 2nd Last (READ) Y

Y ADDR Cycle
Y SRW = 1 TX/ RX RX
Byte to be
(Master RX) Read
N N N (WRITE) TX
Write Next Byte Generate Set TX Y ACK from

to I2C_I2DR Set TXAK =1 Mode
STOP Signal Receiver
N
Read Data
Write Data TX Next
Byte from I2C_I2DR
to I2C_I2DR
and Store
Switch to Set RX Switch to

RX Mode Mode RX Mode
Dummy Read Generate Read Data Dummy Read Dummy Read

from I2C_I2DR STOP Signal from I2C_I2DR from I2C_I2DR from I2C_I2DR
And Store
Return
Figure 35-5. Flowchart of typical I2C interrupt routine

Initialization
NOTE
For a Repeated Start only, the Stop-generation stage does not
occur in Master mode. A loop repeats itself without stopping
for the next start.
For Master Receive mode, I2C is programmed as Master
Transmit during Address mode and after slave address transfer;
the MTX bit should be cleared and a dummy read on the
I2C_I2DR register should be performed so I2C can read the
next receive data.

N
A1 IIF = 1?
Clear IIF
Y Master N
Mode?
TX RX Y Arbitration
TX/RX?
Lost?
N
Last Byte
Transmitted? Y
Clear IAL
N
Last
N Y
RXAK = 0? Byte to be Y
N IAAS =1
Read? IAAS =1
? ? Data
Y N
Address Cycle
Y N
Cycle
End of Y 2nd Last
Y ADDR Cycle (Read)Y SRW =1 RX
Byte to be TX/RX?
(Master RX) Read? ?
? N N(WRITE) TX
N
Y ACK from
Write Next Generate Set TX
Set TXAK =1 Mode Receiver
Byte to I2DR STOP Signal
?
N
Switch to Read Data

RX Mode Write Data Tx Next
from I2DR
to I2DR Byte
And Store
Read Data
Dummy Read Generate Set RX Switch to
from I2DR
From I2DR STOP Signal Mode RX Mode
And Store
Dummy Read Dummy Read

From I2DR From I2DR
A1
Figure 35-6. Flowchart for typical I2C polling routine

Initialization
NOTE
The timeout value depends on the bus frequency at which I2C
is operating. The minimum timeout for polling the IIF bit at a
maximum I2C bus frequency of 400 kHz is Tmin = 25 μs
(=2.5 x 10 μs). This value can be calculated for any bus
frequency. The formula is Tmin = 10/FSCL, where FSCL is the
frequency of the I2C clock (SCL).
Reset
Program IFDR
Enable I2C
(IEN = 1, IIEN = 1)
Program IADR
N
IBB=0?
Program MSTA and MTX

Interrupt Asserted
IAL=1
N
IBB=1?
C Y A
Write Slave Address

to I2DR
Interrupt Asserted
D
Data Transmission
Interrupt Asserted
Figure 35-7. Detailed flowchart of a typical I2C Master Transmit mode, part 1

Clear IIF
Y N
MSTA = 1?
N Clear IAL
RXAK = 0?
WriteNext
Byte to I2DR
Generate Generate RESTART

STOP Signal Signal
D B C B
Figure 35-8. Detailed flowchart of a typical I2C Master Transmit mode, part 2
Figure 35-7 and Figure 35-8 show the Master Transmit mode operation with interrupt
subroutine. If an interrupt is generated and the MSTA bit is 0, then bus arbitration is lost
and IAL is set. Software can clear the IAL bit and reprogram I2C. If the MSTA bit is 1,
then it is a transfer-generated interrupt. In this case, software can check the RXAK bit for
a data receive acknowledgement by the slave and, accordingly, decide to do one of the
following:
• Generate a STOP
• Generate a REPEATED START by writing to the I2C_I2CR register
• Perform the next data transfer by writing to the I2C_I2DR register
NOTE
The IBB bit is asserted by a Start condition on the bus, and it is
deasserted by a Stop condition on the bus. Therefore, if
arbitration is lost due to an unexpected Stop condition during
transfer, then IBB is cleared. If arbitration is lost due to a data
mismatch, then it is not cleared. Software should always clear
the IEN bit and then set it if arbitration is lost.

I2C Memory Map/Register Definition
35.6 Software restriction

Software should ensure that there is a delay of at least two module clock cycles after it
sets the I2C_I2CR[RSTA] bit and before writing to the I2C_I2DR register. The
maximum possible clock period of the module clock is 78 ns.
35.7 I2C Memory Map/Register Definition
The I2C contains five 16-bit registers.

NOTE
Registers at offsets 0x0002, 0x0006, 0x000A, and 0x000E are
reserved for future additions.
I2C memory map
Absolute
Width Section/
(in bits) page
(hex)
21A_0000 I2C Address Register (I2C1_IADR) 16 R/W 0000h 35.7.1/1713
21A_0004 I2C Frequency Divider Register (I2C1_IFDR) 16 R/W 0000h 35.7.2/1713
21A_0008 I2C Control Register (I2C1_I2CR) 16 R/W 0000h 35.7.3/1715
21A_000C I2C Status Register (I2C1_I2SR) 16 R/W 0081h 35.7.4/1716
21A_0010 I2C Data I/O Register (I2C1_I2DR) 16 R/W 0000h 35.7.5/1718

35.7.1 I2C Address Register (I2Cx_IADR)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0
ADR
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Cx_IADR field descriptions

Field Description
Reserved
7–1 Slave address. Contains the specific slave address to be used by the I2C. Slave mode is the default I2C
ADR mode for an address match on the bus.
NOTE: The I2C_IADR holds the address to which the I2C responds when addressed as a slave. The
slave address is not the address sent on the bus during the address transfer. The register is not
reset by a software reset.
Reserved
35.7.2 I2C Frequency Divider Register (I2Cx_IFDR)

The I2C_IFDR provides a programmable prescaler to configure the clock for bit-rate
selection. The register does not get reset by a software reset.
I2C clock is sourced from PERCLK_ROOT which is routed from IPG_CLK_ROOT. I2C
clock frequency can easily obtained by using the following formula:
I2C clock Frequency = (PERCLK_ROOT frequency)/(division factor corresponding
to IFDR)
By default, IPG_CLK_ROOT and PERCLK_ROOT frequencies are set to 49.5 MHz,
where the root clock is sourced from PLL2’s PFD2. Obtaining the frequencies can be
accomplished by:
PLL2 = 528 MHz
PLL2_PFD2 = 528 MHz * 18 / 24 = 396 MHz
IPG_CLK_ROOT = (PLL2_PFD2 / ahb_podf )/ ipg_podf = (396 MHz/4)/2 = 49.5
MHz
PER_CLK_ROOT = IPG_CLK_ROOT/perclk_podf = 49.5 MHz/1 = 49.5 MHz

NOTE
The above calculation assumes that the default CCM register
settings, routing, and division factors are used. If different
routing, PFD values, and/or division factors are used, the user
must adjust the parameters accordingly to calculate the correct
clock frequency.
The following table describes the divider and register values for the register field "IC."
Table 35-3. I2C_IFDR Register Field Values
IC Divider IC Divider IC Divider IC Divider
0x00 30 0x10 288 0x20 22 0x30 160
0x01 32 0x11 320 0x21 24 0x31 192
0x02 36 0x12 384 0x22 26 0x32 224
0x03 42 0x13 480 0x23 28 0x33 256
0x04 48 0x14 576 0x24 32 0x34 320
0x05 52 0x15 640 0x25 36 0x35 384
0x06 60 0x16 768 0x26 40 0x36 448
0x07 72 0x17 960 0x27 44 0x37 512
0x08 80 0x18 1152 0x28 48 0x38 640
0x09 88 0x19 1280 0x29 56 0x39 768
0x0A 104 0x1A 1536 0x2A 64 0x3A 896
0x0B 128 0x1B 1920 0x2B 72 0x3B 1024
0x0C 144 0x1C 2304 0x2C 80 0x3C 1280
0x0D 160 0x1D 2560 0x2D 96 0x3D 1536
0x0E 192 0x1E 3072 0x2E 112 0x3E 1792
0x0F 240 0x1F 3840 0x2F 128 0x3F 2048

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 IC
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Cx_IFDR field descriptions

Field Description
Reserved
IC I2C clock rate. Prescales the clock for bit-rate selection. Due to potentially slow I2Cn_SCL and I2Cn_SDA
rise and fall times, bus signals are sampled at the prescaler frequency. The serial bit clock frequency may
be lower than IPG_CLK_ROOT divided by the divider shown in the I2C Data I/O Register.
NOTE: The IC value should not be changed during the data transfer, however, it can be changed before
a Repeat Start or Start programming sequence in I2C. The I2C protocol supports bit rates of up to
400 kbps. The IC bits need to be programmed in accordance with this constraint.

35.7.3 I2C Control Register (I2Cx_I2CR)
The I2C_I2CR is used to enable the I2C and the I2C interrupt. It also contains bits that
govern operation as a slave or a master.
Bit 15 14 13 12 11 10 9 8
Read 0
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read 0 0
IEN IIEN MSTA MTX TXAK
Write RSTA
Reset 0 0 0 0 0 0 0 0
I2Cx_I2CR field descriptions

Field Description
Reserved
7 I2C enable. Also controls the software reset of the entire I2C. Resetting the bit generates an internal reset
IEN to the block. If the block is enabled in the middle of a byte transfer, Slave mode ignores the current bus
transfer and starts operating when the next Start condition is detected. Master mode is not aware that the
bus is busy, so initiating a start cycle may corrupt the current bus cycle, ultimately causing either the
current master or the I2C to lose arbitration. Subsequently, bus operation returns to normal.
0 The block is disabled, but registers can still be accessed.

1 The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect.
6 I2C interrupt enable.
IIEN
NOTE: If data is written during the Start condition, that is, just after setting the I2C_I2CR[MSTA] and
I2C_I2CR[MTX] bits, then the ICF bit is cleared at the falling edge of SCLK after Start. If data is
written after the Start condition and falling edge of SCLK, then the ICF bit is cleared as soon as
data is written.
0 I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt
condition occurs.
1 I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set.
5 Master/Slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a Stop
MSTA signal.
NOTE: The module clock should be on for writing to the MSTA bit.
NOTE: The MSTA bit is cleared by software to generate a Stop condition; it can also be cleared by
hardware when the I2C loses the bus arbitration.

I2Cx_I2CR field descriptions (continued)

Field Description
0 Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode.
1 Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode.
4 Transmit/Receive mode select bit. Selects the direction of master and slave transfers.
MTX
0 Receive.
When a slave is addressed, the software should set MTX according to the slave read/write bit in the
I2C status register (I2C_I2SR[SRW]).
1 Transmit.
In Master mode, MTX should be set according to the type of transfer required. Therefore, for address
cycles, MTX is always 1.
3 Transmit acknowledge enable. Specifies the value driven onto I2Cn_SDA during acknowledge cycles for
TXAK both master and slave receivers.
NOTE: Writing TXAK applies only when the I2C bus is a receiver.
0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
1 No acknowledge signal response is sent (that is, the acknowledge bit = 1).
2 Repeat start. Always reads as 0. Attempting a repeat start without bus mastership causes loss of
RSTA arbitration.
0 No repeat start
1 Generates a Repeated Start condition
35.7.4 I2C Status Register (I2Cx_I2SR)
The I2C_I2SR contains bits that indicate transaction direction and status.
Bit 15 14 13 12 11 10 9 8
Read 0
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read ICF IAAS IBB 0 SRW RXAK

IAL IIF
Write
Reset 1 0 0 0 0 0 0 1

I2Cx_I2SR field descriptions

Field Description
Reserved
7 Data transferring bit. While one byte of data is transferred, ICF is cleared.
ICF
0 Transfer is in progress.
1 Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer.
6 I2C addressed as a slave bit. The Arm platform is interrupted if the interrupt enable (I2C_I2CR[IIEN]) is
IAAS set. The Arm platform must check the slave read/write bit (SRW) and set its Transfer/Receive mode
accordingly. Writing to I2C_I2CR clears this bit.
0 Not addressed
1 Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address.
5 I2C bus busy bit. Indicates the status of the bus.
IBB
NOTE: When I2C is enabled (I2C_I2CR[IEN] = 1), it continuously polls the bus data (SDA) and clock
(SCL) signals to determine a Start or Stop condition.
0 Bus is idle. If a Stop signal is detected, IBB is cleared.

1 Bus is busy. When Start is detected, IBB is set.
4 Arbitration lost. Set by hardware in the following circumstances (IAL must be cleared by software by
IAL writing a "0" to it at the start of the interrupt service routine):
• I2Cn_SDA input samples low when the master drives high during an address or data-transmit cycle.
• I2Cn_SDA input samples low when the master drives high during the acknowledge bit of a data-
receive cycle.
For the above two cases, the bit is set at the falling edge of the ninth I2Cn_SCL clock during the ACK
cycle.
• A Start cycle is attempted when the bus is busy.
• A Repeated Start cycle is requested in Slave mode.
• A Stop condition is detected when the master did not request it.
NOTE: Software cannot set the bit.
0 No arbitration lost.
1 Arbitration is lost.
Reserved
2 Slave read/write. When the I2C is addressed as a slave, IAAS is set, and the slave read/write bit (SRW)
SRW indicates the value of the R/W command bit of the calling address sent from the master. SRW is valid only
when a complete transfer has occurred, no other transfers have been initiated, and the I2C is a slave and
has an address match.
0 Slave receive, master writing to slave

1 Slave transmit, master reading from slave
1 I2C interrupt. Must be cleared by the software by writing a "0" to it in the interrupt routine.
IIF
NOTE: The software cannot set the bit.
0 No I2C interrupt pending.

1 An interrupt is pending.

I2Cx_I2SR field descriptions (continued)

Field Description
This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt
is set when one of the following occurs:
• One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock).
• An address is received that matches its own specific address in Slave Receive mode.
• Arbitration is lost.
0 Received acknowledge. This is the value received from the I2Cn_SDA input for the acknowledge bit
RXAK during a bus cycle.
0 An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus.
1 A "No acknowledge" signal was detected at the ninth clock.
35.7.5 I2C Data I/O Register (I2Cx_I2DR)
In Master Receive mode, reading the data register allows a read to occur and initiates the
next byte to be received. In Slave mode, the same function is available after it is
addressed.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 DATA
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Cx_I2DR field descriptions

Field Description
Reserved
DATA Data Byte. Holds the last data byte received or the next data byte to be transferred. Software writes the
next data byte to be transmitted or reads the data byte received.
NOTE: The core-written value in I2C_I2DR cannot be read back by the core. Only data written by the I2C
bus side can be read.

Chapter 36
IOMUX Controller (IOMUXC)
36.1 Overview
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC to share
one pad to several functional blocks. This sharing is done by multiplexing the pad's input
and output signals.
Every module requires a specific pad setting (such as pull up or keeper), and for each
pad, there are up to 8 muxing options (called ALT modes). The pad settings parameters
are controlled by the IOMUXC.
The IOMUX consists only of combinatorial logic combined from several basic IOMUX
cells. Each basic IOMUX cell handles only one pad signal's muxing.
Figure 36-1 illustrates the IOMUX/IOMUXC connectivity in the system.

Overview
PAD Settings
PAD Settings
Registers
MUX Control
Registers
IOMUXC
. .
IOMUX IO Pad
Cells
. Cells
.
. .
IPMUX
HW
signal
moduleY
CFG
AIPS Reg
moduleX IOMUX IORING
Arm PLATFORM + AHBMAX module module module

#1 #2 #N
Figure 36-1. IOMUX SoC Level Block Diagram

Chapter 36 IOMUX Controller (IOMUXC)
36.1.1 Features
The IOMUXC features are:
• 32-bit software mux control registers (IOMUXC_SW_MUX_CTL_PAD_<PAD
NAME> or IOMUXC_SW_MUX_CTL_GRP_<GROUP NAME>) to configure 1 of
8 alternate (ALT) MUX_MODE feilds of each pad or a predefined group of pads and
to enable the forcing of an input path of the pad(s) (SION bit).
• 32-bit software pad control registers
(IOMUXC_SW_PAD_CTL_PAD_<PAD_NAME> or
IOMUXC_SW_PAD_CTL_GRP_<GROUP NAME>) to configure specific pad
settings of each pad, or a predefined group of pads.
• 32-bit general purpose registers - several (GPR0 to GPRn) 32-bit registers according
to SoC requirements for any usage.
• 32-bit input select control registers to control the input path to a module when more
than one pad drives this module input.
Each SW MUX/PAD CTL IOMUXC register handles only one pad or one pad's group.
Only the minimum number of registers required by software are implemented by
hardware. For example, if only ALT0 and ALT1 modes are used on Pad x then only one
bit register will be generated as the MUX_MODE control field in the software mux
control register of Pad x.
The software mux control registers may allow the forcing of pads to become input (input
path enabled) regardless of the functional direction driven. This may be useful for
loopback and GPIO data capture.
36.2 Clocks
The table found here describes the clock sources for IOMUXC.
information.
Table 36-1. IOMUXC Clocks
ipt_clk_io enfc_clk_root IO clock


The IOMUXC consists of two sub-blocks:
• IOMUXC_REGISTERS includes all of the IOMUXC registers (see Features).
• IOMUXC_LOGIC includes all of the IOMUXC combinatorial logic (IP interface
controls, address decoder, observability muxes).
The IOMUX consists of a number (about the number of pads in the SoC) of basic
iomux_cell units. If only one functional mode is required for a specific pad, there is no
need for IOMUX and the signals can be connected directly from the module to the I/O.
The IOMUX cell is required whenever two or more functional modes are required for a
specific pad or when one functional mode and the one test mode are required.
The basic iomux_cell design, which allows two levels of HW signal control (in ALT6
and ALT7 modes - ALT7 gets highest priority) is shown in Figure 36-2.
IOMUXC_SW_MUX_CTRL_<PAD>[MUX_MODE]
SW_PAD_CTL
ALT0
ALT1
: PAD0
ALTn
ALT0
ALT1
<SOURCE>_SELECT_INPUT :
ALTn
Peripheral1 DATA_IN IOMUXC_SW_MUX_CTRL_<PAD>[MUX_MODE]
SW_PAD_CTL
ALT0
ALT1
:
PAD1
ALTn
ALT0
ALT1
:
ALTn
Figure 36-2. IOMUX Cell Block Diagram

36.3.1 ALT6 and ALT7 extended muxing modes

The ALT7 and ALT6 extended muxing modes allow any signal in the system (such as
fuse, pad input, JTAG, or software register) to override any software configuration and to
force the ALT6/ALT7 muxing mode.
It also allows an IOMUX software register to control a group of pads.
36.3.2 SW Loopback through SION bit

A limited option exists to override the default pad functionality and force the input path
to be active (ipp_ibe==1'b1) regardless of the value driven by the corresponding module.
This can be done by setting the SION (Software Input On) bit in the
IOMUXC_SW_MUX_CTL register (when available) to "1".
Uses include:
• LoopBack - Module x drives the pad and also receives pad value as an input.
• GPIO Capture - Module x drives the pad and the value is captured by GPIO.

IOMUXC Memory Map/Register Definition
36.3.3 Daisy chain - multi pads driving same module input pin
In some cases, more than one pad may drive a single module input pin. Such cases
require the addition of one more level of IOMUXing; all of these input signals are
muxed, and a dedicated software controlled register controls the mux in order to select
the required input path.
A module port involved in "daisy chain" requires two software configuration commands,
one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers).
This means that a module port involved in "daisy chain" requires two software
configuration commands, one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers). The daisy chain is illustrated in the figure below.
IOMUX IORING
IOMUX Cells
To module D
To module F
A
To module X
ALT x select
To module G
To module X
Module X B
To module H
ALT x select
Daisy Chain
To module X
select
To module M
C
To module N
ALT x select
Figure 36-3. Daisy chain illustration

36.4 IOMUXC Memory Map/Register Definition
The main groups of IOMUXC registers are:

The General Purpose Registers IOMUXC_GPR[13:0] are used to select operating modes
for general features in the SoC, usually not related to the IOMUX itself.
The Software MUX Control Registers are used to configure the IOMUX muxing, and
"connect" the pad to a given port in a module.
The PAD Settings Registers are used to control the pad settings configuration. For some
pads (in order to save chip route) the pad settings are grouped in one register; changing
the group register will affect the settings for all pads in the group.
The following table shows the IOMUXC register summary.
NOTE
The operational frequency on GPIO pads is dependent on slew
rate (SRE), speed (SPEED), and supply voltage (OVDD). See
Operating Frequency for more details.
IOMUXC memory map
Absolute
Width Section/
(in bits) page
(hex)
20E_0000 GPR (IOMUXC_GPR0) 32 R/W 0000_0000h 36.4.1/1752
20E_000C GPR (IOMUXC_GPR3) 32 R/W 01E0_0000h 36.4.4/1760
20E_001C GPR (IOMUXC_GPR7) 32 R/W 2222_2222h 36.4.8/1769
36.4.10/
20E_0024 GPR (IOMUXC_GPR9) 32 R/W 0000_0000h
1771
36.4.11/
20E_0028 GPR (IOMUXC_GPR10) 32 R/W 0000_3800h
1772
36.4.12/
20E_002C GPR (IOMUXC_GPR11) 32 R/W 0000_3800h
1774
36.4.13/
20E_0030 GPR (IOMUXC_GPR12) 32 R/W 0F00_0000h
1774
36.4.14/
20E_0034 GPR (IOMUXC_GPR13) 32 R/W 0591_24C4h
1776

IOMUXC memory map (continued)

Absolute
Width Section/
(in bits) page
(hex)
Pad Mux Register 36.4.15/
20E_004C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1) 1779
20E_0050 32 R/W 0000_0005h
20E_0054 32 R/W 0000_0005h
20E_0058 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC) 1782
20E_005C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0) 1783
20E_0060 32 R/W 0000_0005h
20E_0064 32 R/W 0000_0005h
20E_0068 32 R/W 0000_0005h
20E_006C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL) 1787
20E_0070 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0) 1788
20E_0074 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL) 1789
20E_0078 32 R/W 0000_0005h
20E_007C 32 R/W 0000_0005h
20E_0080 32 R/W 0000_0005h
20E_0084 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC) 1793
20E_0088 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25) 1794
20E_008C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B) 1795
20E_0090 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16) 1796
20E_0094 32 R/W 0000_0005h
20E_0098 32 R/W 0000_0005h
20E_009C 32 R/W 0000_0005h
20E_00A0 32 R/W 0000_0005h


Absolute
Width Section/
(in bits) page
(hex)
20E_00A4 32 R/W 0000_0005h
20E_00A8 32 R/W 0000_0005h
20E_00AC 32 R/W 0000_0005h
20E_00B0 32 R/W 0000_0005h
20E_00B4 32 R/W 0000_0005h
20E_00B8 32 R/W 0000_0005h
20E_00BC 32 R/W 0000_0005h
20E_00C0 32 R/W 0000_0005h
20E_00C4 32 R/W 0000_0005h
20E_00C8 32 R/W 0000_0005h
20E_00CC 32 R/W 0000_0005h
20E_00D0 32 R/W 0000_0005h
20E_00D4 32 R/W 0000_0000h
20E_00D8 32 R/W 0000_0000h
20E_00DC 32 R/W 0000_0000h
20E_00E0 32 R/W 0000_0000h
20E_00E4 32 R/W 0000_0000h
20E_00E8 32 R/W 0000_0000h
20E_00EC 32 R/W 0000_0000h
20E_00F0 32 R/W 0000_0000h
20E_00F4 32 R/W 0000_0000h
20E_00F8 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B) 1822


Absolute
Width Section/
(in bits) page
(hex)
20E_00FC 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B) 1823
20E_0100 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B) 1824
20E_0104 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_EIM_RW) 1825
20E_0108 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B) 1826
20E_010C 32 R/W 0000_0000h
20E_0110 32 R/W 0000_0000h
20E_0114 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_EIM_AD00) 1829
20E_0118 32 R/W 0000_0000h
20E_011C 32 R/W 0000_0000h
20E_0120 32 R/W 0000_0000h
20E_0124 32 R/W 0000_0000h
20E_0128 32 R/W 0000_0000h
20E_012C 32 R/W 0000_0000h
20E_0130 32 R/W 0000_0000h
20E_0134 32 R/W 0000_0000h
20E_0138 32 R/W 0000_0000h
20E_013C 32 R/W 0000_0000h
20E_0140 32 R/W 0000_0000h
20E_0144 32 R/W 0000_0000h
20E_0148 32 R/W 0000_0000h
20E_014C 32 R/W 0000_0000h
20E_0150 32 R/W 0000_0000h


Absolute
Width Section/
(in bits) page
(hex)
20E_0154 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B) 1845
20E_0158 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK) 1846
20E_015C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK) 1847
20E_0160 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15) 1848
20E_0164 32 R/W 0000_0005h
20E_0168 32 R/W 0000_0005h
20E_016C 32 R/W 0000_0005h
20E_0170 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00) 1852
20E_0174 32 R/W 0000_0005h
20E_0178 32 R/W 0000_0005h
20E_017C 32 R/W 0000_0005h
20E_0180 32 R/W 0000_0005h
20E_0184 32 R/W 0000_0005h
20E_0188 32 R/W 0000_0005h
20E_018C 32 R/W 0000_0005h
20E_0190 32 R/W 0000_0005h
20E_0194 32 R/W 0000_0005h
20E_0198 32 R/W 0000_0005h
20E_019C 32 R/W 0000_0005h
20E_01A0 32 R/W 0000_0005h
20E_01A4 32 R/W 0000_0005h
20E_01A8 32 R/W 0000_0005h


Absolute
Width Section/
(in bits) page
(hex)
20E_01AC 32 R/W 0000_0005h
20E_01B0 32 R/W 0000_0005h
20E_01B4 32 R/W 0000_0005h
20E_01B8 32 R/W 0000_0005h
20E_01BC 32 R/W 0000_0005h
20E_01C0 32 R/W 0000_0005h
20E_01C4 32 R/W 0000_0005h
20E_01C8 32 R/W 0000_0005h
20E_01CC 32 R/W 0000_0005h
20E_01D0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO) 1876
20E_01D4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK) 1877
20E_01D8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER) 1878
20E_01DC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV) 1879
20E_01E0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1) 1880
20E_01E4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0) 1881
20E_01E8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN) 1882
20E_01EC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1) 1883
20E_01F0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0) 1884
20E_01F4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_MDC) 1885
20E_01F8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_KEY_COL0) 1886
20E_01FC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0) 1887
20E_0200 32 R/W 0000_0005h


Absolute
Width Section/
(in bits) page
(hex)
20E_0204 32 R/W 0000_0005h
20E_0208 32 R/W 0000_0005h
20E_020C 32 R/W 0000_0005h
20E_0210 32 R/W 0000_0005h
20E_0214 32 R/W 0000_0005h
20E_0218 32 R/W 0000_0005h
20E_021C 32 R/W 0000_0005h
20E_0220 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_GPIO00) 1896
20E_0224 32 R/W 0000_0005h
20E_0228 32 R/W 0000_0005h
20E_022C 32 R/W 0000_0005h
20E_0230 32 R/W 0000_0005h
20E_0234 32 R/W 0000_0005h
20E_0238 32 R/W 0000_0005h
20E_023C 32 R/W 0000_0005h
20E_0240 32 R/W 0000_0005h
20E_0244 32 R/W 0000_0005h
20E_0248 32 R/W 0000_0005h
20E_024C 32 R/W 0000_0005h
20E_0250 32 R/W 0000_0005h
20E_0254 32 R/W 0000_0005h
20E_0258 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK) 1910


Absolute
Width Section/
(in bits) page
(hex)
20E_025C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC) 1911
20E_0260 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN) 1912
20E_0264 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC) 1913
20E_0268 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04) 1914
20E_026C 32 R/W 0000_0005h
20E_0270 32 R/W 0000_0005h
20E_0274 32 R/W 0000_0005h
20E_0278 32 R/W 0000_0005h
20E_027C 32 R/W 0000_0005h
20E_0280 32 R/W 0000_0005h
20E_0284 32 R/W 0000_0005h
20E_0288 32 R/W 0000_0005h
20E_028C 32 R/W 0000_0005h
20E_0290 32 R/W 0000_0005h
20E_0294 32 R/W 0000_0005h
20E_0298 32 R/W 0000_0005h
20E_029C 32 R/W 0000_0005h
20E_02A0 32 R/W 0000_0005h
20E_02A4 32 R/W 0000_0005h
20E_02A8 32 R/W 0000_0005h
20E_02AC 32 R/W 0000_0005h
20E_02B0 32 R/W 0000_0005h


Absolute
Width Section/
(in bits) page
(hex)
20E_02B4 32 R/W 0000_0005h
20E_02B8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD3_CMD) 1934
20E_02BC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD3_CLK) 1935
20E_02C0 32 R/W 0000_0005h
20E_02C4 32 R/W 0000_0005h
20E_02C8 32 R/W 0000_0005h
20E_02CC 32 R/W 0000_0005h
20E_02D0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD3_RESET) 1939
20E_02D4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE) 1940
20E_02D8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE) 1941
20E_02DC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B) 1942
20E_02E0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B) 1943
20E_02E4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B) 1944
20E_02E8 32 R/W 0000_0005h
20E_02EC 32 R/W 0000_0005h
20E_02F0 32 R/W 0000_0005h
20E_02F4 32 R/W 0000_0005h
20E_02F8 32 R/W 0000_0005h
20E_02FC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00) 1949
20E_0300 32 R/W 0000_0005h
20E_0304 32 R/W 0000_0005h
20E_0308 32 R/W 0000_0005h


Absolute
Width Section/
(in bits) page
(hex)
20E_030C 32 R/W 0000_0005h
20E_0310 32 R/W 0000_0005h
20E_0314 32 R/W 0000_0005h
20E_0318 32 R/W 0000_0005h
20E_031C 32 R/W 0000_0005h
20E_0320 32 R/W 0000_0005h
20E_0324 32 R/W 0000_0005h
20E_0328 32 R/W 0000_0005h
20E_032C 32 R/W 0000_0005h
20E_0330 32 R/W 0000_0005h
20E_0334 32 R/W 0000_0005h
20E_0338 32 R/W 0000_0005h
20E_033C 32 R/W 0000_0005h
20E_0340 32 R/W 0000_0005h
20E_0344 32 R/W 0000_0005h
20E_0348 32 R/W 0000_0005h
20E_034C 32 R/W 0000_0005h
20E_0350 32 R/W 0000_0005h
20E_0354 32 R/W 0000_0005h
20E_0358 32 R/W 0000_0005h
20E_035C 32 R/W 0000_0005h
Pad Control Register 36.4.212/
20E_0360 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1) 1973


Absolute
Width Section/
(in bits) page
(hex)
20E_0364 32 R/W 0001_B0B0h
20E_0368 32 R/W 0001_B0B0h
20E_036C 32 R/W 0001_3030h
(IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC) 1978
20E_0370 32 R/W 0001_B030h
(IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0) 1979
20E_0374 32 R/W 0001_B030h
20E_0378 32 R/W 0001_B030h
20E_037C 32 R/W 0001_B030h
20E_0380 32 R/W 0001_3030h
(IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL) 1986
20E_0384 32 R/W 0001_B030h
(IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0) 1988
20E_0388 32 R/W 0001_3030h
(IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL) 1989
20E_038C 32 R/W 0001_B030h
20E_0390 32 R/W 0001_B030h
20E_0394 32 R/W 0001_B030h
20E_0398 32 R/W 0001_3030h
(IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC) 1996
20E_039C 32 R/W 0000_B0B1h
(IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25) 1998
20E_03A0 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B) 1999
20E_03A4 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16) 2001
20E_03A8 32 R/W 0001_B0B0h
20E_03AC 32 R/W 0001_B0B0h
20E_03B0 32 R/W 0001_B0B0h
20E_03B4 32 R/W 0001_B0B0h
20E_03B8 32 R/W 0001_B0B0h


Absolute
Width Section/
(in bits) page
(hex)
20E_03BC 32 R/W 0001_B0B0h
20E_03C0 32 R/W 0001_B0B0h
20E_03C4 32 R/W 0001_B0B0h
20E_03C8 32 R/W 0001_B0B0h
20E_03CC 32 R/W 0001_B0B0h
20E_03D0 32 R/W 0001_B0B0h
20E_03D4 32 R/W 0001_B0B0h
20E_03D8 32 R/W 0001_B0B0h
20E_03DC 32 R/W 0001_B0B0h
20E_03E0 32 R/W 0001_B0B0h
20E_03E4 32 R/W 0001_B0B0h
20E_03E8 32 R/W 0000_B0B1h
20E_03EC 32 R/W 0000_B0B1h
20E_03F0 32 R/W 0000_B0B1h
20E_03F4 32 R/W 0000_B0B1h
20E_03F8 32 R/W 0000_B0B1h
20E_03FC 32 R/W 0000_B0B1h
20E_0400 32 R/W 0000_B0B1h
20E_0404 32 R/W 0000_B0B1h
20E_0408 32 R/W 0000_B0B1h
20E_040C 32 R/W 0000_B0B1h
(IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B) 2044
20E_0410 32 R/W 0000_B0B1h
(IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B) 2046


Absolute
Width Section/
(in bits) page
(hex)
20E_0414 32 R/W 0000_B0B1h
(IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B) 2048
20E_0418 32 R/W 0000_B0B1h
(IOMUXC_SW_PAD_CTL_PAD_EIM_RW) 2049
20E_041C 32 R/W 0000_B0B1h
(IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B) 2051
20E_0420 32 R/W 0000_B0B1h
20E_0424 32 R/W 0000_B0B1h
20E_0428 32 R/W 0000_B0B1h
(IOMUXC_SW_PAD_CTL_PAD_EIM_AD00) 2056
20E_042C 32 R/W 0000_B0B1h
20E_0430 32 R/W 0000_B0B1h
20E_0434 32 R/W 0000_B0B1h
20E_0438 32 R/W 0000_B0B1h
20E_043C 32 R/W 0000_B0B1h
20E_0440 32 R/W 0000_B0B1h
20E_0444 32 R/W 0000_B0B1h
20E_0448 32 R/W 0000_B0B1h
20E_044C 32 R/W 0000_B0B1h
20E_0450 32 R/W 0000_B0B1h
20E_0454 32 R/W 0000_B0B1h
20E_0458 32 R/W 0000_B0B1h
20E_045C 32 R/W 0000_B0B1h
20E_0460 32 R/W 0000_B0B1h
20E_0464 32 R/W 0000_B0B1h
20E_0468 32 R/W 0000_B060h
(IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B) 2083


Absolute
Width Section/
(in bits) page
(hex)
20E_046C 32 R/W 0000_B0B1h
(IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK) 2084
20E_0470 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK) 2086
20E_0474 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15) 2088
20E_0478 32 R/W 0001_B0B0h
20E_047C 32 R/W 0001_B0B0h
20E_0480 32 R/W 0001_B0B0h
20E_0484 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00) 2094
20E_0488 32 R/W 0001_B0B0h
20E_048C 32 R/W 0001_B0B0h
20E_0490 32 R/W 0001_B0B0h
20E_0494 32 R/W 0001_B0B0h
20E_0498 32 R/W 0001_B0B0h
20E_049C 32 R/W 0001_B0B0h
20E_04A0 32 R/W 0001_B0B0h
20E_04A4 32 R/W 0001_B0B0h
20E_04A8 32 R/W 0001_B0B0h
20E_04AC 32 R/W 0001_B0B0h
20E_04B0 32 R/W 0001_B0B0h
20E_04B4 32 R/W 0001_B0B0h
20E_04B8 32 R/W 0001_B0B0h
20E_04BC 32 R/W 0001_B0B0h
20E_04C0 32 R/W 0001_B0B0h


Absolute
Width Section/
(in bits) page
(hex)
20E_04C4 32 R/W 0001_B0B0h
20E_04C8 32 R/W 0001_B0B0h
20E_04CC 32 R/W 0001_B0B0h
20E_04D0 32 R/W 0001_B0B0h
20E_04D4 32 R/W 0001_B0B0h
20E_04D8 32 R/W 0001_B0B0h
20E_04DC 32 R/W 0001_B0B0h
20E_04E0 32 R/W 0001_B0B0h
20E_04E4 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO) 2134
20E_04E8 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK) 2136
20E_04EC 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER) 2138
20E_04F0 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV) 2139
20E_04F4 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1) 2141
20E_04F8 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0) 2143
20E_04FC 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN) 2144
20E_0500 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1) 2146
20E_0504 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0) 2148
20E_0508 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_ENET_MDC) 2149
20E_050C 32 R/W 0000_2030h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P) 2152
20E_0510 32 R/W 0000_8030h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5) 2154
20E_0514 32 R/W 0000_8030h
20E_0518 32 R/W 0000_2030h


Absolute
Width Section/
(in bits) page
(hex)
20E_051C 32 R/W 0000_2030h
20E_0520 32 R/W 0000_8030h
20E_0524 32 R/W 0000_2030h
20E_0528 32 R/W 0000_8030h
20E_052C 32 R/W 0000_8000h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00) 2168
20E_0530 32 R/W 0000_8000h
20E_0534 32 R/W 0000_8000h
20E_0538 32 R/W 0000_8000h
20E_053C 32 R/W 0000_8000h
20E_0540 32 R/W 0000_8000h
20E_0544 32 R/W 0000_8000h
20E_0548 32 R/W 0000_8000h
20E_054C 32 R/W 0000_8000h
20E_0550 32 R/W 0000_8000h
20E_0554 32 R/W 0000_8000h
20E_0558 32 R/W 0000_8000h
20E_055C 32 R/W 0000_8000h
20E_0560 32 R/W 0000_8000h
20E_0564 32 R/W 0000_8000h
20E_0568 32 R/W 0000_8000h
20E_056C 32 R/W 0000_8030h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B) 2200
20E_0570 32 R/W 0000_8000h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B) 2202


Absolute
Width Section/
(in bits) page
(hex)
20E_0574 32 R/W 0000_8000h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B) 2204
20E_0578 32 R/W 0000_8030h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B) 2206
20E_057C 32 R/W 0008_3030h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET) 2208
20E_0580 32 R/W 0000_8000h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0) 2210
20E_0584 32 R/W 0000_8000h
20E_0588 32 R/W 0000_8030h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P) 2214
20E_058C 32 R/W 0000_B000h
20E_0590 32 R/W 0000_3000h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0) 2218
20E_0594 32 R/W 0000_8030h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P) 2220
20E_0598 32 R/W 0000_3000h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1) 2222
20E_059C 32 R/W 0000_3030h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0) 2224
20E_05A0 32 R/W 0000_3030h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1) 2226
20E_05A4 32 R/W 0000_8000h
(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B) 2228
20E_05A8 32 R/W 0000_2030h
20E_05AC 32 R/W 0000_8030h
20E_05B0 32 R/W 0000_2030h
20E_05B4 32 R/W 0000_8030h
20E_05B8 32 R/W 0000_2030h
20E_05BC 32 R/W 0000_8030h
20E_05C0 32 R/W 0000_2030h
20E_05C4 32 R/W 0000_8030h
20E_05C8 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_KEY_COL0) 2246


Absolute
Width Section/
(in bits) page
(hex)
20E_05CC 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0) 2247
20E_05D0 32 R/W 0001_B0B0h
20E_05D4 32 R/W 0001_B0B0h
20E_05D8 32 R/W 0001_B0B0h
20E_05DC 32 R/W 0001_B0B0h
20E_05E0 32 R/W 0001_B0B0h
20E_05E4 32 R/W 0001_B0B0h
20E_05E8 32 R/W 0001_B0B0h
20E_05EC 32 R/W 0001_B0B0h
20E_05F0 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_GPIO00) 2262
20E_05F4 32 R/W 0001_B0B0h
20E_05F8 32 R/W 0001_B0B0h
20E_05FC 32 R/W 0001_B0B0h
20E_0600 32 R/W 0001_B0B0h
20E_0604 32 R/W 0001_B0B0h
20E_0608 32 R/W 0001_B0B0h
20E_060C 32 R/W 0001_B0B0h
20E_0610 32 R/W 0001_B0B0h
20E_0614 32 R/W 0001_B0B0h
20E_0618 32 R/W 0001_B0B0h
20E_061C 32 R/W 0001_B0B0h
20E_0620 32 R/W 0001_B0B0h


Absolute
Width Section/
(in bits) page
(hex)
20E_0624 32 R/W 0001_B0B0h
20E_0628 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK) 2286
20E_062C 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC) 2287
20E_0630 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN) 2289
20E_0634 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC) 2291
20E_0638 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04) 2292
20E_063C 32 R/W 0001_B0B0h
20E_0640 32 R/W 0001_B0B0h
20E_0644 32 R/W 0001_B0B0h
20E_0648 32 R/W 0001_B0B0h
20E_064C 32 R/W 0001_B0B0h
20E_0650 32 R/W 0001_B0B0h
20E_0654 32 R/W 0001_B0B0h
20E_0658 32 R/W 0001_B0B0h
20E_065C 32 R/W 0001_B0B0h
20E_0660 32 R/W 0001_B0B0h
20E_0664 32 R/W 0001_B0B0h
20E_0668 32 R/W 0001_B0B0h
20E_066C 32 R/W 0001_B0B0h
20E_0670 32 R/W 0001_B0B0h
20E_0674 32 R/W 0001_B0B0h
20E_0678 32 R/W 0000_7060h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS) 2319


Absolute
Width Section/
(in bits) page
(hex)
20E_067C 32 R/W 0000_B060h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD) 2321
20E_0680 32 R/W 0000_7060h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB) 2322
20E_0684 32 R/W 0000_7060h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI) 2324
20E_0688 32 R/W 0000_7060h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK) 2326
20E_068C 32 R/W 0000_90B1h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO) 2327
20E_0690 32 R/W 0001_B0B0h
20E_0694 32 R/W 0001_B0B0h
20E_0698 32 R/W 0001_B0B0h
20E_069C 32 R/W 0001_B0B0h
20E_06A0 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_SD3_CMD) 2336
20E_06A4 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_SD3_CLK) 2337
20E_06A8 32 R/W 0001_B0B0h
20E_06AC 32 R/W 0001_B0B0h
20E_06B0 32 R/W 0001_B0B0h
20E_06B4 32 R/W 0001_B0B0h
20E_06B8 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_SD3_RESET) 2346
20E_06BC 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_NAND_CLE) 2347
20E_06C0 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_NAND_ALE) 2349
20E_06C4 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B) 2351
20E_06C8 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B) 2352
20E_06CC 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B) 2354
20E_06D0 32 R/W 0001_B0B0h


Absolute
Width Section/
(in bits) page
(hex)
20E_06D4 32 R/W 0001_B0B0h
20E_06D8 32 R/W 0001_B0B0h
20E_06DC 32 R/W 0001_B0B0h
20E_06E0 32 R/W 0001_B0B0h
20E_06E4 32 R/W 0001_B0B0h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00) 2364
20E_06E8 32 R/W 0001_B0B0h
20E_06EC 32 R/W 0001_B0B0h
20E_06F0 32 R/W 0001_B0B0h
20E_06F4 32 R/W 0001_B0B0h
20E_06F8 32 R/W 0001_B0B0h
20E_06FC 32 R/W 0001_B0B0h
20E_0700 32 R/W 0001_B0B0h
20E_0704 32 R/W 0001_B0B0h
20E_0708 32 R/W 0001_B0B0h
20E_070C 32 R/W 0001_B0B0h
20E_0710 32 R/W 0001_B0B0h
20E_0714 32 R/W 0001_B0B0h
20E_0718 32 R/W 0001_B0B0h
20E_071C 32 R/W 0001_B0B0h
20E_0720 32 R/W 0001_B0B0h
20E_0724 32 R/W 0001_B0B0h
20E_0728 32 R/W 0001_B0B0h


Absolute
Width Section/
(in bits) page
(hex)
20E_072C 32 R/W 0001_B0B0h
20E_0730 32 R/W 0001_B0B0h
20E_0734 32 R/W 0001_B0B0h
20E_0738 32 R/W 0001_B0B0h
20E_073C 32 R/W 0001_B0B0h
20E_0740 32 R/W 0001_B0B0h
20E_0744 32 R/W 0001_B0B0h
Pad Group Control Register 36.4.462/
20E_0748 32 R/W 0000_0030h
(IOMUXC_SW_PAD_CTL_GRP_B7DS) 2406
20E_074C 32 R/W 0000_0030h
(IOMUXC_SW_PAD_CTL_GRP_ADDDS) 2406
20E_0750 32 R/W 0000_0000h
(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL) 2407
20E_0754 32 R/W 0000_0000h
(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0) 2408
20E_0758 32 R/W 0000_1000h
(IOMUXC_SW_PAD_CTL_GRP_DDRPKE) 2409
20E_075C 32 R/W 0000_0000h
20E_0760 32 R/W 0000_0000h
20E_0764 32 R/W 0000_0000h
20E_0768 32 R/W 0000_2000h
(IOMUXC_SW_PAD_CTL_GRP_DDRPK) 2412
20E_076C 32 R/W 0000_0000h
20E_0770 32 R/W 0000_0000h
(IOMUXC_SW_PAD_CTL_GRP_DDRHYS) 2413
20E_0774 32 R/W 0000_0000h
(IOMUXC_SW_PAD_CTL_GRP_DDRMODE) 2414
20E_0778 32 R/W 0000_0000h
20E_077C 32 R/W 0000_0000h
20E_0780 32 R/W 0000_0000h


Absolute
Width Section/
(in bits) page
(hex)
20E_0784 32 R/W 0000_0030h
20E_0788 32 R/W 0000_0030h
20E_078C 32 R/W 0000_0030h
(IOMUXC_SW_PAD_CTL_GRP_CTLDS) 2418
20E_0790 32 R/W 0008_0000h
(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII) 2419
20E_0794 32 R/W 0000_0030h
20E_0798 32 R/W 0008_0000h
(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE) 2421
20E_079C 32 R/W 0000_0030h
20E_07A0 32 R/W 0000_0030h
20E_07A4 32 R/W 0000_0030h
20E_07A8 32 R/W 0000_0030h
20E_07AC 32 R/W 0000_0000h
(IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM) 2424
Select Input Register 36.4.488/
20E_07B0 32 R/W 0000_0000h
(IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT) 2425
20E_07B4 32 R/W 0000_0000h
(IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT) 2426
20E_07B8 32 R/W 0000_0000h
(IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT) 2427
20E_07BC 32 R/W 0000_0000h
(IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT) 2428
20E_07C0 32 R/W 0000_0000h
(IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT) 2429
20E_07C4 32 R/W 0000_0000h
(IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT) 2430
20E_07C8 32 R/W 0000_0000h
(IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT) 2431
20E_07CC 32 R/W 0000_0000h
(IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT) 2432
20E_07D0 32 R/W 0000_0000h
(IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT) 2433
20E_07D4 32 R/W 0000_0000h
(IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT) 2434
20E_07D8 32 R/W 0000_0000h
(IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT) 2435


Absolute
Width Section/
(in bits) page
(hex)
20E_07DC 32 R/W 0000_0000h
(IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT) 2436
20E_07E0 32 R/W 0000_0000h
(IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT) 2437
20E_07E4 32 R/W 0000_0000h
(IOMUXC_FLEXCAN1_RX_SELECT_INPUT) 2437
20E_07E8 32 R/W 0000_0000h
(IOMUXC_FLEXCAN2_RX_SELECT_INPUT) 2438
20E_07F0 32 R/W 0000_0000h
(IOMUXC_CCM_PMIC_READY_SELECT_INPUT) 2439
20E_07F4 32 R/W 0000_0000h
(IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT) 2439
20E_07F8 32 R/W 0000_0000h
(IOMUXC_ECSPI1_MISO_SELECT_INPUT) 2440
20E_07FC 32 R/W 0000_0000h
(IOMUXC_ECSPI1_MOSI_SELECT_INPUT) 2441
20E_0800 32 R/W 0000_0000h
(IOMUXC_ECSPI1_SS0_SELECT_INPUT) 2441
20E_0804 32 R/W 0000_0000h
20E_0808 32 R/W 0000_0000h
20E_080C 32 R/W 0000_0000h
20E_0810 32 R/W 0000_0000h
20E_0814 32 R/W 0000_0000h
20E_0818 32 R/W 0000_0000h
20E_081C 32 R/W 0000_0000h
20E_0820 32 R/W 0000_0000h
20E_0824 32 R/W 0000_0000h
20E_0828 32 R/W 0000_0000h
20E_082C 32 R/W 0000_0000h
20E_0830 32 R/W 0000_0000h
20E_0834 32 R/W 0000_0000h


Absolute
Width Section/
(in bits) page
(hex)
20E_0838 32 R/W 0000_0000h
20E_083C 32 R/W 0000_0000h
(IOMUXC_ENET_REF_CLK_SELECT_INPUT) 2454
20E_0840 32 R/W 0000_0000h
(IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT) 2455
20E_0844 32 R/W 0000_0000h
(IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT) 2456
20E_0848 32 R/W 0000_0000h
(IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT) 2457
20E_084C 32 R/W 0000_0000h
20E_0850 32 R/W 0000_0000h
20E_0854 32 R/W 0000_0000h
20E_0858 32 R/W 0000_0000h
(IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT) 2461
20E_085C 32 R/W 0000_0000h
(IOMUXC_ESAI_RX_FS_SELECT_INPUT) 2462
20E_0860 32 R/W 0000_0000h
(IOMUXC_ESAI_TX_FS_SELECT_INPUT) 2463
20E_0864 32 R/W 0000_0000h
(IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT) 2464
20E_0868 32 R/W 0000_0000h
(IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT) 2465
20E_086C 32 R/W 0000_0000h
(IOMUXC_ESAI_RX_CLK_SELECT_INPUT) 2466
20E_0870 32 R/W 0000_0000h
(IOMUXC_ESAI_TX_CLK_SELECT_INPUT) 2467
20E_0874 32 R/W 0000_0000h
(IOMUXC_ESAI_SDO0_SELECT_INPUT) 2468
20E_0878 32 R/W 0000_0000h
(IOMUXC_ESAI_SDO1_SELECT_INPUT) 2469
20E_087C 32 R/W 0000_0000h
(IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT) 2470
20E_0880 32 R/W 0000_0000h
20E_0884 32 R/W 0000_0000h
20E_0888 32 R/W 0000_0000h
20E_088C 32 R/W 0000_0000h
(IOMUXC_HDMI_ICECIN_SELECT_INPUT) 2474


Absolute
Width Section/
(in bits) page
(hex)
20E_0890 32 R/W 0000_0000h
(IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT) 2475
20E_0894 32 R/W 0000_0000h
(IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT) 2476
20E_0898 32 R/W 0000_0000h
(IOMUXC_I2C1_SCL_IN_SELECT_INPUT) 2477
20E_089C 32 R/W 0000_0000h
(IOMUXC_I2C1_SDA_IN_SELECT_INPUT) 2478
20E_08A0 32 R/W 0000_0000h
20E_08A4 32 R/W 0000_0000h
20E_08A8 32 R/W 0000_0000h
20E_08AC 32 R/W 0000_0000h
20E_08B0 32 R/W 0000_0000h
(IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT) 2482
20E_08B4 32 R/W 0000_0000h
20E_08B8 32 R/W 0000_0000h
20E_08BC 32 R/W 0000_0000h
20E_08C0 32 R/W 0000_0000h
20E_08C4 32 R/W 0000_0000h
20E_08C8 32 R/W 0000_0000h
20E_08CC 32 R/W 0000_0000h
20E_08D0 32 R/W 0000_0000h
20E_08D4 32 R/W 0000_0000h
20E_08D8 32 R/W 0000_0000h
(IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT) 2492
20E_08DC 32 R/W 0000_0000h
(IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT) 2493
20E_08E0 32 R/W 0000_0000h
(IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT) 2494
20E_08E4 32 R/W 0000_0000h
(IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT) 2495


Absolute
Width Section/
(in bits) page
(hex)
20E_08E8 32 R/W 0000_0000h
(IOMUXC_KEY_COL5_SELECT_INPUT) 2495
20E_08EC 32 R/W 0000_0000h
20E_08F0 32 R/W 0000_0000h
20E_08F4 32 R/W 0000_0000h
(IOMUXC_KEY_ROW5_SELECT_INPUT) 2497
20E_08F8 32 R/W 0000_0000h
20E_08FC 32 R/W 0000_0000h
20E_0900 32 R/W 0000_0000h
(IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT) 2499
20E_0904 32 R/W 0000_0000h
(IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT) 2500
20E_0908 32 R/W 0000_0000h
(IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT) 2501
20E_090C 32 R/W 0000_0000h
(IOMUXC_SDMA_EVENTS14_SELECT_INPUT) 2502
20E_0910 32 R/W 0000_0000h
(IOMUXC_SDMA_EVENTS15_SELECT_INPUT) 2503
20E_0914 32 R/W 0000_0000h
(IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT) 2503
20E_0918 32 R/W 0000_0000h
(IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT) 2504
20E_091C 32 R/W 0000_0000h
(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT) 2505
20E_0920 32 R/W 0000_0000h
(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT)

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Document Number: IMX6DQRM

1.3 Target Applications.......................................................................................................................................................31

1.5 Architectural Overview.................................................................................................................................................35

2.2 Arm Platform Memory Map......................................................................................................................................... 41

2.3 DDR mapping to MMDC controller ports....................................................................................................................46

2.4 DMA memory map....................................................................................................................................................... 47

3.2 Cortex A9 interrupts..................................................................................................................................................... 49

3.3 SDMA event mapping.................................................................................................................................................. 53

5.2 Fusemap Description Table.......................................................................................................................................... 173

i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 6, 05/2020

6.3 Raw NAND flash controller overview......................................................................................................................... 183

6.4 EIM-PSRAM/NOR flash controller overview..............................................................................................................186

7.2 Chip and Arm Platform Debug Architecture................................................................................................................ 189

7.3 Smart DMA (SDMA) core............................................................................................................................................199

7.4 Miscellaneous............................................................................................................................................................... 201

7.5 Supported tools............................................................................................................................................................. 202

8.2 Boot modes................................................................................................................................................................... 205

8.3 Device configuration.....................................................................................................................................................210

8.4 Device initialization...................................................................................................................................................... 214

8.5 Boot devices (internal boot)..........................................................................................................................................220

8.6 Program image.............................................................................................................................................................. 259

8.7 Plugin image................................................................................................................................................................. 267

8.8 Serial Downloader........................................................................................................................................................ 267

8.9 Recovery devices.......................................................................................................................................................... 276

8.10 USB low-power boot.................................................................................................................................................... 276

8.11 High-Assurance Boot (HAB)........................................................................................................................................278

9.2 Image Processing Unit (IPU)........................................................................................................................................ 289

9.3 LVDS Display Bridge (LDB)....................................................................................................................................... 300

9.4 Video Data Order Adapter (VDOA).............................................................................................................................302

9.5 Display Content Integrity Checker (DCIC).................................................................................................................. 304

9.6 Video Processing Unit (VPUv6)...................................................................................................................................306

i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 6, 05/2020

9.7 OpenGL ES 3D Graphics Processing Unit (GPU3Dv4)...............................................................................................310

9.8 2D Graphics Processing Unit (GPU2Dv2)................................................................................................................... 312

9.9 Vector Graphics Processing Unit (GPUVGv2)............................................................................................................ 314

9.10 HDMI TX - HD Multimedia Interface transmitter....................................................................................................... 315

9.11 Display / Sensor MIPI interfaces.................................................................................................................................. 318

9.12 Audio subsystem...........................................................................................................................................................322

10.2 Device Power Management Architecture Components................................................................................................335

10.3 Clock Management....................................................................................................................................................... 338

10.4 Power management.......................................................................................................................................................347

10.5 ONOFF (Button)...........................................................................................................................................................369

11.2 Central Security Unit (CSU).........................................................................................................................................372

11.3 Cryptographic Acceleration and Assurance Module (CAAM).................................................................................... 374

11.4 Secure Non-Volatile Storage (SNVS).......................................................................................................................... 375

11.5 Data Co-Processor (DCP)............................................................................................................................................. 376

11.6 High-Assurance Boot (HAB)........................................................................................................................................377

11.7 System JTAG Controller (SJC).................................................................................................................................... 377

12.2 External Signals............................................................................................................................................................ 379

12.3 Platform configuration.................................................................................................................................................. 380

12.4 Performance and Power................................................................................................................................................ 382

12.5 Core Platform Sub-Blocks details.................................................................................................................................384

12.6 Debug and Trace Sub-blocks (CoreSight components)................................................................................................387

i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 6, 05/2020

13.2 Clocks........................................................................................................................................................................... 391

13.3 Functional Description..................................................................................................................................................392

13.4 Access Protections........................................................................................................................................................ 393

13.5 Access Support..............................................................................................................................................................393

13.6 Initialization Information.............................................................................................................................................. 394