UNIT-2

Instructions: Language of the Computer

Instruction Set
o To command a computer’s hardware, you must speak its language. The words of a
computer’s language are called instructions, and its vocabulary is called instruction
set.
o Different computers have different instruction sets
Instruction set: The vocabulary of commands understood by a given architecture.

1. Operations of the Computer Hardware

Every computer must be able to perform arithmetic. The MIPS assembly language notation
add a, b, c instructs a computer to add the two variables b and c and to put their sum in a.
This notation is rigid in that each MIPS arithmetic instruction performs only one operation
and must always have exactly three variables. For example, suppose we want to place the
sum of four variables b, c, d, and e into variable a.

The following sequence of instructions adds the four variables:

add a, b, c # The sum of b and c is placed in a
add a, a, d # The sum of b, c, and d is now in a
add a, a, e # The sum of b, c, d, and e is now in a

Fig: MIPS assembly language

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 The relationship of programs written in higher-level programming languages to MIPS.
Example 1: Compiling Two C Assignment Statements into MIPS
This segment of a C program contains the five variables a, b, c, d, and e.
a = b + c;
d = a – e;
The translation from C to MIPS assembly language instructions is performed by the compiler.
Show the MIPS code produced by a compiler.

Answer: A MIPS instruction operates on two source operands and places the result in one
destination operand. Hence, the two simple statements above compile directly into these two
MIPS assembly language instructions:
add a, b, c
sub d, a, e

Example 2: Compiling a Complex C Assignment into MIPS

A somewhat complex statement contains the five variables f, g, h, i, and j:
f = (g + h) – (i + j);
What might a C compiler produce?

Answer: The compiler must break this statement into several assembly instructions, since
only one operation is performed per MIPS instruction.
The first MIPS instruction calculates the sum of g and h. We must place the result
somewhere, so the compiler creates a temporary variable, called t0:
add t0,g,h # temporary variable t0 contains g + h
The second instruction places the sum of i and j in another temporary variable created by the
compiler, called t1:
add t1,i,j # temporary variable t1 contains i + j
Finally, the subtract instruction subtracts the second sum from the first and places the
difference in the variable f, completing the compiled code:
sub f,t0,t1 # f gets t0 – t1, which is (g + h) – (i + j)

2. Operands of the Computer Hardware

 Unlike programs in high-level languages, the operands of arithmetic instructions are
restricted; they must be from a limited number of special locations built directly in hardware
called registers. Arithmetic instructions use register operands.
 Word: The natural unit of access in a computer, usually a group of 32 bits;
corresponds to the size of a register in the MIPS architecture. 32-bit data called a “word”
 One major difference between the variables of a programming languages and registers is
the limited number of register, typically 32 on current computers, like MIPS.
 MIPS has a 32 × 32-bit register file
 The size of a register in the MIPS architecture is 32 bits.
 Numbered 0 to 31: $0, $1, … $31
 Assembler names
o $t0, $t1, …, $t9 for temporary values
o $s0, $s1, …, $s7 for saved variables

Example: Compiling a C Assignment using Registers

C code:
f = (g + h) - (i + j);
The variables f, g, h, i, and j are assigned to the register in $s0, $s1, $s2, $s3, and $s4,
respectively. What is the compiled MIPS code?

Compiled MIPS code:

add $t0, $s1, $s2 #$t0 contains g + h
add $t1, $s3, $s4 #$t1 contains i + j
sub $s0, $t0, $t1 # f gets $t0 - $t1, which is (g + h) – (i + j)

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 Memory Operands
Data transfer instruction: A command that moves data between memory and registers.
Address: A value used to define the location of a specific data element within a memory
array. To access a word in memory, the instruction must supply the memory address.
 Memory is just a large, single-dimensional array, with the address acting as the index to
that array, starting at 0.
For example, in Figure, the address of the third data element is 2, and the value of Memory
[2] is 10.

Fig: Memory addresses and contents of memory at those locations.

 The data transfer instruction that copies data from memory to a register is traditionally
called load. The actual MIPS name for this instruction is lw, standing for load word.
lw $s1,20($s2) # $s1=Memory[$s2+20]
 The instruction complementary to load is traditionally called store; it copies data from a
register to memory. The actual MIPS name is sw, standing for store word.
sw $s1,20($s2) # Memory[$s2+20]=$s1

For example, Figure shows the actual MIPS addresses for the words in Figure the byte
address of the third word is 8.
 Alignment restriction: A requirement that data be aligned in memory on natural
boundaries.
 In MIPS, words must start at address that is multiples of 4. This requirement is called an
alignment restriction.

Fig: Actual MIPS memory addresses and contents of memory for those words.

Example: Compiling and Assignment When an Operand is in Memory

Let’s assume that A is an array of 100 words and that the compiler has associated the variable
g and h with the registers $s1 and $s2. Let’s also assume that the starting address, or base
address of the array is in $s3. Compile this C ass statement:
g = h + A[8];
Answer: Compiled MIPS code:
 g in $s1, h in $s2, base address of A in $s3
 Index 8 requires offset of 32 (4 bytes per word)

lw $t0, 32($s3) # $t0 get A[8] (base register $s3 + 4 × 8)

add $s1, $s2, $t0 # g = h + A[8]

Example: Compiling Using Load and Store

Assume variable h is associated with register $s2 and the base address of the array A is in
$s3. What is the MIPS assembly code for the C assignment statement below?
A[12] = h + A[8];
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Answer: Compiled MIPS code:
 h in $s2, base address of A in $s3
 Index 8 requires offset of 32
lw $t0, 32($s3) # $t0 gets A[8]
add $t0, $s2, $t0 # $t0 gets h + A[8]
sw $t0, 48($s3) # Stores h + A[8] back into A[12]

 Registers vs. Memory

 Registers are faster to access than memory
 Operating on memory data requires loads and stores
 Compiler must use registers for variables as much as possible
 The process of putting less commonly used variables (or those needed later) into memory
is called spilling registers.

 Constant or Immediate Operands

Many times, a program will use a constant in an operation—for example, incrementing an
index to point to the next element of an array.

The arithmetic instructions in which one operand is a constant. This quick add instruction
with one constant operand is called add immediate or addi. To add 4 to register $s3, we just
write
addi $s3,$s3,4 # $s3 = $s3 + 4
For example, add instruction where one operand is zero. Hence, MIPS dedicates a register
$zero to be hard-wired to the value zero.
add $t2, $s1, $zero # $t2 gets $s1

3. Signed and Unsigned Numbers

Numbers are kept in computer hardware as a series of high and low electronic signals, and so
they are considered base 2 numbers.
Binary digit: Also called binary bit. One of the two numbers in base 2, 0 or 1, which are the
components of information.

Generalizing the point, in any number base, the value of ith digit d is
d ×Basei

We subscript decimal numbers with ten and binary numbers with two. For example,1011two
represents
(1 x 23) + (0 x 22) + (1 x 21) + (1 x 20)ten
= (1 x 8) + (0 x 4) + (1 x 2) + (1 x 1)ten
= 8 + 0 + 2 + 1ten
= 11ten

We number the bits 0, 1, 2, 3, . . . from right to left in a word. The drawing below shows the
numbering of bits within a MIPS word and the placement of the number 1011two:

 Least Significant Bit: The Rightmost Bit in a MIPS word. Most Significant Bit: The
Left most bit in a MIPS word.
 Hence, the phrase least significant bit is used to refer to the rightmost bit (bit 0 above)
and most significant bit to the left most bit (bit 31).
 The MIPS word is 32 bits long, so we can represent 2 32 different 32-bit patterns. It is
natural to let these combinations represent the numbers from 0 to 232-1(4,294,967,295ten).

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That is, 32-bit binary numbers can be represented in terms of the bit value times a power of 2
(here xi means the ith bit of x):

These positive numbers are called unsigned numbers.

 Signed Numbers
Computer programs calculate both positive and negative numbers, so we need a
representation that distinguishes the positive from the negative.
The most obvious solution is to add a separate sign, which conveniently can be represented in
a single bit; the name for this representation is sign and magnitude.
 Leading 0s mean positive, and
 Leading 1s mean negative.
This convention for representing signed binary numbers is called two’s complement
representation.

0000 0000 0000 0000 0000 0000 0000 0000two = 0ten

0000 0000 0000 0000 0000 0000 0000 0001two = 1ten
... ...
1111 1111 1111 1111 1111 1111 1111 1101two = –3ten
1111 1111 1111 1111 1111 1111 1111 1110two = –2ten
1111 1111 1111 1111 1111 1111 1111 1111two = –1ten

The positive half of the numbers, from 0 to 2,147,483,647 ten (231-1), use the same
representation as before. The following bit pattern (1000 . . . 0000 two) represents the most
negative number -2,147,483,648ten(-231).

 Two’s complement representation

 Every computer today uses two’s complement binary representations for signed
numbers.
 Two’s complement representation has the advantage that all negative numbers have a 1
in the most significant bit.
 Consequently, hardware needs to test only this bit to see if a number is positive or
negative (with the number 0 considered positive). This bit is often called the sign bit.

By recognizing the role of the sign bit, we can represent positive and negative 32-bit numbers
in terms of the bit value times a power of 2:

The sign bit is multiplied by -2 31, and the rest of the bits are then multiplied by positive
versions of their respective base values.

Binary to Decimal Conversion

What is the decimal value of this 32-bit two’s complement number?

1111 1111 1111 1111 1111 1111 1111 1100two

Answer: Substituting the number’s bit values into the formula above:

 Two useful shortcuts when working with two’s complement numbers. The first shortcut is
a quick way to negate a two’s complement binary number. Simply invert every 0 to 1 and
every 1 to 0, then add one to the result.

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 Negation Shortcut
Negate 2ten, and then check the result by negating -2ten.
2ten = 0000 0000 0000 0000 0000 0000 0000 0010two
Negating this number by inverting the bits and adding one,

1111 1111 1111 1111 1111 1111 1111 1101two

+ 1two
= 1111 1111 1111 1111 1111 1111 1111 1110two
= –2ten

Going the other direction,

1111 1111 1111 1111 1111 1111 1111 1110two
is first inverted and then incremented:
0000 0000 0000 0000 0000 0000 0000 0001two
+ 1two
= 0000 0000 0000 0000 0000 0000 0000 0010two
= 2ten

4. Representing Instructions in the Computer

Instructions are kept in the computer as a series of high and low electronic signals and may
be represented as numbers.
Since registers are referred to in instructions, there must be a convention to map register
names into numbers.
In MIPS assembly language,
 registers $s0 to $s7 map onto registers 16 to 23,
 registers $t0 to $t7 map onto registers 8 to 15.
Hence, $s0 means register 16, $s1 means register 17, $s2 means register 18, . . . , $t0 means
register 8, $t1 means register 9, and so on.
Instruction format: A form of representation of an instruction composed of fields of binary
numbers.
 All MIPS instructions are 32 bits long. Machine Language: Binary representation used
for communication within a computer system. The numeric version of instructions machine
language and a sequence of such instructions machine code.
 All computer data sizes are multiples of 4, hexadecimal (base 16) numbers are popular.
we can convert by replacing each group of four binary digits by a single hexadecimal digit.

Fig: The hexadecimal-binary conversion table.

Example: Binary to Hexadecimal and Back Convert the following hexadecimal and binary
numbers into the other base:
eca8 6420hex
0001 0011 0101 0111 1001 1011 1101 1111two
Answer:

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 MIPS Fields
 R-type (for register) or R-format

Here is the meaning of each name of the fields in MIPS instructions:

 op: Basic operation of the instruction, traditionally called the opcode.
 rs: The first register source operand.
 rt: The second register source operand.
 rd: The register destination operand. It gets the result of the operation.
 shamt: Shift amount. (The field contains zero in this section.)
 funct: Function. This field, often called the function code, selects the specific variant
of the operation in the op field.
Example: MIPS R-format
add $t0,$s1,$s2

 I-type (for immediate) or I-format: Second type of instruction format is called I-type
(for immediate) or I-format.
It is used by the immediate and data transfer instructions. The fields of I-format are

 rt: destination or source register number

 Constant: –215 to +215 – 1
 Address: offset added to base address in rs
The 16-bit address means a load word instruction can load any word within a region of ±2 15
or 32,768 bytes of the address in the base register rs.

Example: MIPS I-format

lw $t0,32($s3) # Temporary reg $t0 gets A[8]
Here, 19 (for $s3) is placed in the rs field, 8 (for $t0) is placed in the rt field, and 32 is placed
in the address field.
35 19 8 32

Figure shows the numbers used in each field for the MIPS instructions covered so far.

Fig: MIPS instruction encoding.

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In the table above, “reg” means a register number between 0 and 31, “address” means a 16-
bit address, and “n.a.” (not applicable) means this field does not appear in this format.
Note that add and sub instructions have the same value in the op field; the hardware uses the
funct field to decide the variant of the operation: add (32) or subtract (34).

Example: We can now take an example all the way from what the programmer writes to
what the computer executes. If $t1 has the base of the array A and $s2 corresponds to h, the
assignment statement
A[3000] = h + A[300];
Compiled MIPS code:
lw $t0, 1200($t1) # $t0 gets A[300]
add $t0, $s2, $t0 # $t0 get h + h + A[300]
sw $t0, 1200($t1) # stores h + A[300] back to A[300]

We can determine the three machine language instructions.

Figure summarized the portion of MIPS machine language in this section

5. Logical Operations
 Logical Operations are instructions for bitwise manipulation. Useful for extracting and
inserting groups of bits in a word
Figure show logical operations in C, Java, and MIPS

Fig: C and Java logical operators and their corresponding MIPS instructions.
MIPS implements NOT using a NOR with one operand being zero.

 Shift Operations
They move all the bits in a word to the left or right, filling the emptied bits with 0s.
The actual name of the two MIPS shift instructions are called shift left logical (sll) and shift
right logical (srl).

sll $t2,$s0,4 # reg $t2 = reg $s0 << 4 bits

0 0 16 10 4 0

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shamt: it stands for shift amount.It defines how many positions to shift.
o Shift left logical
 Shift left and fill with 0 bits
 sll by i bits multiplies by 2i
o Shift right logical
 Shift right and fill with 0 bits
 srl by i bits divides by 2i (unsigned only)

Example: Assuming that the original value was in register $s0 and the result should go in
register $t2:
sll $t2,$s0,4 # reg $t2 = reg $s0 << 4 bits

if register $s0 contained

0000 0000 0000 0000 0000 0000 0000 1001two = 9ten
and the instruction to shift left by 4 was executed, the $t2 would be:
0000 0000 0000 0000 0000 0000 1001 0000two = 144ten

 AND Operation
AND is a bit-by-bit operation that leaves a 1 in the result only if both bits of the operands are
1.
For example, if register $t2 contains
0000 0000 0000 0000 0000 1101 1100 0000two
and register $t1 contains
0000 0000 0000 0000 0011 1100 0000 0000two
then, after executing the MIPS instruction
and $t0,$t1,$t2 # reg $t0 = reg $t1 & reg $t2
the value of register $t0 would be
0000 0000 0000 0000 0000 1100 0000 0000two

 OR Operations
It is a bit-by-bit operation that places a 1 in the result if either operand bit is a 1.
For example, if register $t2 contains
0000 0000 0000 0000 0000 1101 1100 0000two
and register $t1 contains
0000 0000 0000 0000 0011 1100 0000 0000two
then, after executing the MIPS instruction
or $t0,$t1,$t2 # reg $t0 = reg $t1 | reg $t2
the value of register $t0 would be
0000 0000 0000 0000 0011 1101 1100 0000two

 NOT Operation
NOT takes one operand and places a 1 in the result if one operand bit is a 0, and vice versa.
In three-operand format, the designers of MIPS decided to include the instruction NOR (NOT
OR) instead of NOT.
If one operand is zero, then it is equivalent to NOT: A NOR 0 = NOT (A OR 0) = NOT (A).
Example: If the register $t1 is
0000 0000 0000 0000 0011 1100 0000 0000two
and register $t3 has the value 0, the result of the MIPS instruction
nor $t0,$t1,$t3 # reg $t0 = ~ (reg $t1 | reg $t3)
is this value in register $t0:
1111 1111 1111 1111 1100 0011 1111 1111two

6. Instructions for Making Decisions

 Conditional Branch: MIPS assembly language includes two decision-making
instructions, similar to an if statement with a go to.
The first instruction is

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 beq register1, register2, L1
This instruction means go to the statement labeled L1 if the value in register1 equals the
value in register2. The mnemonic beq stands for branch if equal.

The second instruction is

bne register1, register2, L1
It means go to the statement labeled L1 if the value in register1 does not equal the value in
register2. The mnemonic bne stands for branch if not equal.
These two instructions are traditionally called conditional branches.

Conditional Branch: An instruction that requires the comparison of two values and that
allows for a subsequent transfer of control to a new address in the program based on the
outcome of the comparison.

 Unconditional Branch:The MIPS name for this type of instruction is jump, abbreviated
as j
j L1 # Unconditional jump to instruction labeled L1

Example: Compiling if-then-else into Conditional Branches

o C code:
if (i==j) f = g + h; else f = g - h;
f, g, h, i, and j in $s0, $s1, $s2, $s3, $s4
o Compiled MIPS code:
bne $s3, $s4, Else # go to Else if i≠ j
add $s0, $s1, $s2 # f = g + h (sipped if i≠ j)
j Exit # go to Exit
Else: sub $s0, $s1, $s2 # f = g – h (skipped if i = j)
Exit:

Fig: Illustration of the options in the if statement above

 Loops
Decisions are important both for choosing between two alternatives—found in if statements
—and for iterating a computation—found in loops.

Example: Compiling a while Loop in C

loop in C:
while (save[i] == k)
i += 1;
Assume that i and k correspond to registers $s3 and $s5 and the base of the array save is in
$s6. What is the MIPS assembly code corresponding to this C segment?

MIPS Code:
Loop: sll $t1,$s3,2 # Temp reg $t1 = i * 4
add $t1,$t1,$s6 # $t1 = address of save[i]
Lw $t0,0($t1) # Temp reg $t0 = save[i]
bne $t0,$s5, Exit # go to Exit if save[i] ≠ k
addi $s3,$s3,1 #i=i+1
j Loop # go to Loop
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 Exit:
 set on less than comparisons
 MIPS offer two versions of the set on less than comparison to handle signed and
unsigned numbers.
o Set on less than (slt) and set on less than immediate (slti) work signed integers.
o Unsigned integers are compared using set on less than unsigned (sltu) and set on less than
immediate unsigned (sltiu)
slt rd, rs, rt # if (rs< rt) rd = 1; else rd = 0;
slti rt, rs, constant # if (rs< constant) rt = 1; else rt = 0;
o Use in combination with beq, bne
slt $t0, $s1, $s2 # if ($s1 < $s2)
bne $t0, $zero, L # branch to L

Example: Signed versus Unsigned Comparison

$s0 = 1111 1111 1111 1111 1111 1111 1111 1111two
$s1 = 0000 0000 0000 0000 0000 0000 0000 0001two
slt $t0, $s0, $s1 # signed
$s0 (–1) < $s1 (+1)  $t0 = 1
sltu $t0, $s0, $s1 # unsigned
$s0 ( +4,294,967,295) < $s1 (+1)  $t0 = 0

 Case/Switch Statement
A case or switch statement that allows the programmer to select one of many alternatives
depending on a single value. The simplest way to implement switch is via a sequence of
conditional tests, turning the switch statement into a chain of if-then-else statements.

7. Supporting Procedures in Computer Hardware

A procedure or function is one tool programmers use to structure programs, both to make
them easier to understand and to allow code to be reused.

Similarly, in the execution of a procedure, the program must follow these six steps:
1. Put parameters in a place where the procedure can access them.
2. Transfer control to the procedure.
3. Acquire the storage resources needed for the procedure.
4. Perform the desired task.
5. Put the result value in a place where the calling program can access it.
6. Return control to the point of origin, since a procedure can be called from several points in
a program.

 MIPS software follows the following convention for procedure calling in allocating its
32 registers:
■ $a0–$a3: four argument registers in which to pass parameters
■ $v0–$v1: two value registers in which to return values
■ $ra: one return address register to return to the point of origin

 Procedure Call Instructions: jal and jr

MIPS assembly language includes an instruction just for the procedures: it jumps to an
address and simultaneously saves the address of the following instruction in register $ra. The
jump-and-link instruction (jal) is simply written

Jal ProcedureAddress
Return address: A link to the calling site that allows a procedure to return to the proper
address; in MIPS it is stored in register $ra.

 MIPS use jump register instruction (jr) to allow the procedure to return to the proper
address. An unconditional jump to the address specified in a register:

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 Jr $ra
The jump register instruction jumps to the address stored in register $ra— which is just what
we want.

Caller: The program that instigates a procedure and provides the necessary parameter values.
Callee: A procedure that executes a series of stored instructions based on parameters
provided by the caller and then returns control to the caller.
Program counter (PC): The register containing the address of the instruction in the program
being executed.

 The calling program, or caller, puts the parameter values in $a0–$a3 and uses jal X to
jump to procedure X (sometimes named the callee). The callee then performs the
calculations, places the results in $v0 and $v1, and returns control to the caller using jr $ra.

 The jal instruction actually saves PC + 4 in register $ra to link to the following
instruction to set up the procedure return.

 Using More Registers

The ideal data structure for spilling registers is a stack—a last-in-first-out queue.
 A stack need a pointer to the most recently allocated address in the stack to show where
the next procedure should place the registers to be spilled or where old register values are
found. The stack pointer is adjusted by one word for each register that is saved or restored.
 MIPS software reserves register 29 for the stack pointer, giving it the obvious name $sp.
 Placing data onto the stack is called a push, and removing data from the stack is called a
pop.

Example: Compiling a C Procedure That Doesn’t Call Another Procedure

o C code:
int leaf_example (int g, h, i, j) {
int f;
f = (g + h) - (i + j);
return f;
}
 The parameter variables g, h, i, and j correspond to the argument registers $a0, $a1, $a2,
$a3, and f correspond to $s0.
 Result in $v0

o Compiled MIPS code:

leaf_example:
addi $sp, $sp, –12 # adjust stack to make room for 3 items
sw $t1, 8($sp) # save register $t1 for use afterwards
sw $t0, 4($sp) # save register $t0 for use afterwards
sw $s0, 0($sp) # save register $s0 for use afterwards

add $t0,$a0,$a1 # register $t0 contains g + h

add $t1,$a2,$a3 # register $t1 contains i + j
sub $s0,$t0,$t1 # f = $t0 – $t1, which is (g + h)–(i + j)
add $v0,$s0,$zero # returns f ($v0 = $s0 + 0)

lw $s0, 0($sp) # restore register $s0 for caller

lw $t0, 4($sp) # restore register $t0 for caller
lw $t1, 8($sp) # restore register $t1 for caller

addi $sp,$sp,12 # adjust stack to delete 3 items

jr $ra # jump back to calling routine

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Fig: The values of the stack pointer and the stack (a) before, (b) during, and (c) after the procedure
call.The stack pointer always points to the “top” of the stack, or the last word in the stack in this
drawing.

MIPS software separates 18 of the registers into two groups:

■ $t0–$t9: temporary registers that are not preserved by the callee (called procedure) on a
procedure call
■ $s0–$s7: saved registers that must be preserved on a procedure call (if used, the callee
saves and restores them)

 Nested Procedures
Procedure that do not calls others are called leaf procedure. Nested Procedures call other
procedures.
For nested call, caller needs to save on the stack:
o Its return address $ra
o Any arguments ($a0 - $a3) and temporaries ($t0 =$t9) needed after the call
o Restore from the stack after the call

Example: Compiling a Recursive C Procedure, Showing Nest Procedure Linking.

o C code: recursive procedure that calculates factorial
int fact (int n) {
if (n < 1) return (1);
else
return n * fact (n - 1);
}
 Argument n in $a0
 Result in $v0

o Compiled MIPS code:

fact:
addi $sp, $sp, –8 # adjust stack for 2 items
sw $ra, 4($sp) # save the return address
sw $a0, 0($sp) # save the argument n

slti $t0,$a0,1 # test for n < 1

beq $t0,$zero,L1 # if n >= 1, go to L1
addi $v0,$zero,1 # return 1
addi $sp,$sp,8 # pop 2 items off stack
jr $ra # return to caller
L1:
addi $a0,$a0,–1 # n >= 1: argument gets (n – 1)
jal fact # call fact with (n –1)
lw $a0, 0($sp) # return from jal: restore argument n
lw $ra, 4($sp) # restore the return address
addi $sp, $sp, 8 # adjust stack pointer to pop 2 items
mul $v0,$a0,$v0 # return n * fact (n – 1)
jr $ra # return to the caller

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Figure summaries that is preserved across a procedure call.

 Allocating Space for New Data on the Stack

The segment of the stack containing a procedure’s saved registers and local variables is called
a procedure frame or activation record.

Figure shows the state of the stack before, during, and after the procedure call.
 Some MIPS software uses a frame pointer ($fp) to point to the first word of the frame of
a procedure.
Frame pointer: A value denoting the location of the saved registers and local variables for a
given procedure.
 A stack pointer ($sp) might change during the procedure, and so references to a local
variable in memory might have different offset depending on where they are in the procedure.

Fig: Illustration of the stack allocation (a) before, (b) during, and (c) after the procedure call.

 Allocating Space for New Data on the Heap

In addition to automatic variables that are local to procedures, C programmers need space in
memory for static variables and for dynamic data structures. Figure shows the MIPS
convention for allocation of memory.
 The stack starts in the high end of memory (7fff fffchex) and grow down.
 The first part of the low end of memory is reserved, followed by home of the MIPS
machine code, called the text segment (0040 0000hex).
 Static data segment (1000 0000hex), which is the place for constants and other static
variables. The global pointer ($gp), is set to an address to make it easy to access data.
 Dynamic data segment (1001 0000hex): C allocates and free space on heap with explicit
functions. malloc() allocates space on the heap and returns a pointer to it, and free() releases
space on the heap to which the pointer points.

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 Fig: The MIPS memory allocation for program and data.

 MIPS Register Conventions

Figure summarizes the register conventions for the MIPS assembly language. Procedures can
be satisfied with up to 4 arguments, 2 registers for a return value, 8 saved registers, and 10
temporary registers without ever going to memory.

8. Communicating with People

Most computers today offer 8-bit bytes to represent characters, with the American Standard
Code for Information Interchange (ASCII) being the representation that nearly everyone
follows. Figure summarizes ASCII.

Fig: ASCII representation of characters.

A series of instructions can extract a byte from a word, MIPS provides instructions to move
bytes.
 Load byte (lb) loads a byte from memory, placing it in the rightmost 8 bits of a register.
 Store byte (sb) takes a byte from the rightmost 8 bits of a register and writes it to memory.
Thus, we copy a byte with the sequence.
lb $t0,0($sp) # Read byte from source
sb $t0,0($gp) # Write byte to destination
Characters are normally combined into strings, which have a variable number of characters.

Example: Compiling a String Copy Procedure, Showing How to Use C Strings

C code:
void strcpy (char x[ ], char y[ ]) {
int i; i = 0;
while ((x[i] = y[i]) != ‘\0’) /* copy & test byte */
i += 1;
}
MIPS assembly code:
strcpy: addi $sp, $sp, -4 # adjust stack for 1 item
sw $s0, 0($sp) # save $s0
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 add $s0, $zero, $zero #i=0
L1: add $t1, $s0, $a1 # address of y[i] in $t1
lbu $t2, 0($t1) # $t2 = y[i]
add $t3, $s0, $a0 # address of x[i] in $t3
sb $t2, 0($t3) # x[i] = y[i]
beq $t2, $zero, L2 # exit loop if y[i] == 0
addi $s0, $s0, 1 #i=i+1
j L1 # next iteration of loop
L2: lw $s0, 0($sp) # restore saved $s0
addi $sp, $sp, 4 # pop 1 item from stack
jr $ra # and return

The MIPS instruction set has explicit instructions to load and store such 16- bit quantities,
called halfwords.
 Load half (lh) loads a halfword from memory, placing it in the rightmost 16 bits of a
register. Load halfword unsigned (lhu) works with unsigned integers.
 Store half (sh) takes a halfword from the rightmost 16 bits of a register and writes it to
memory. We copy a halfword with the sequence
lhu $t0,0($sp) # Read halfword (16 bits) from source
sh $t0,0($gp) # Write halfword (16 bits) to destination

9. MIPS Addressing for 32-Bit Immediates and Addresses

All MIPS instructions 32 bits long simplifies the hardware, where it would be convenient to
have a 32-bit constant or 32-bit address.

 32-Bit Immediate Operands

Although constants are frequently short and fit into the 16-bit field, sometimes they are
bigger. The MIPS instruction set includes the instruction load upper immediate (lui)
specifically to set the upper 16 bits of a constant in a register

Example: Loading a 32-Bit Constant

What is the MIPS assembly code to load this 32-bit constant into register $s0?
0000 0000 0011 1101 0000 1001 0000 0000

First, we would load the upper 16 bits, which is 61 in decimal, using lui:
lui $s0, 61 # 61 decimal = 0000 0000 0011 1101 binary

The value of register $s0 afterward is

0000 0000 0011 1101 0000 0000 0000 0000

The next step is to insert the lower 16 bits, whose decimal value is 2304:
ori $s0, $s0, 2304 # 2304 decimal = 0000 1001 0000 0000

The final value in register $s0 is the desired value:

0000 0000 0011 1101 0000 1001 0000 0000

Fig: The effect of the lui instruction.

The instruction lui transfers the 16-bit immediate constant field value into the left most 16
bits of the register, filling the lower 16 bits with 0s.
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 Addressing in Branches and Jumps
 The MIPS jump instructions have the simplest addressing. They use the final MIPS
instruction format, called the J-type, which consists of 6 bits for the operation field and the
rest of the bits for the address field. Thus,
j 10000 # go to location 10000

where the value of the jump opcode is 2 and the jump address is 10000.
 Target address = PC31…28 : (address × 4)

 The conditional branch instruction must specify two operands in addition to the branch
address. Thus,
bne $s0,$s1,Exit # go to Exit if $s0 ≠ $s1
is assembled into this instruction, leaving only 16 bits for the branch address:

 Target address = PC + offset × 4

PC-relative addressing: An addressing regime in which the address is the sum of the
program counter (PC) and a constant in the instruction.

Example: Showing Branch Offset in Machine Language

The while loop was compiled into this MIPS assembler code:
Loop: sll $t1,$s3,2 # Temp reg $t1 = 4 * i
add $t1,$t1,$s6 # $t1 = address of save[i]
lw $t0,0($t1) # Temp reg $t0 = save[i]
bne $t0,$s5, Exit # go to Exit if save[i] ≠ k
addi $s3,$s3,1 #i=i+1
j Loop # go to Loop
Exit:

If we assume we place the loop starting at location 80000 in memory.

The assembled instructions and their addresses are:

 MIPS Addressing Mode Summary

Multiple forms of addressing are generically called addressing modes.

The MIPS addressing modes are the following:

1. Immediate addressing: the operand is a constant within the instruction itself.
2. Register addressing: the operand is a register
3. Base or displacement addressing: the operand is at memory location whose address is the
sum of a register and a constant in the instruction
4. PC-relative addressing: the branch address is the sum of the PC and a constant in the
instruction
5. Pseudodirect addressing: the jump address is the 26 bits of the instruction concatenated
with the upper bits of the PC

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 Fig: Illustration of the five MIPS addressing modes.

Figure shows all the MIPS instruction formats

Fig: MIPS instruction formats

10.Parallelism and Instructions: Synchronization

Parallel execution is easier when tasks are independent, but often they need to cooperate.
Cooperation usually means some tasks are writing new values that others must read.

 To know when a task is finished writing so that it is safe for another to read, the tasks
need to synchronize. If they don’t synchronize, there is a danger of a data race.
 Data Race: Two memory accesses form a data race if they are from different threads to
same location, at least one is a write, and they occur one after another.
 We focus on the implementation of lock and unlock synchronization operations. Lock and
unlock can be used straightforwardly to create regions where only a single processor can
operate, called a mutual exclusion.
 We require to implement synchronization in a multiprocessor is a set of hardware
primitives with the ability to atomically read and modify a memory location.
 One such hardware primitive and show how it can be used to build a basic
synchronization primitive. One typical operation for building synchronization operations is
the atomic exchange or atomic swap, which inter-changes a value in a register for a value in
memory.
 To build a basic synchronization primitive, assume that we want to build a simple lock,
where the value 0 is used to indicate that the lock is free and 1 is used to indicate that the lock
is unavailable.
 For example, consider two processors that each try to do the exchange simultaneously:
this race is broken, since exactly one of the processors will perform the exchange first,
returning 0, and the second processor will return 1 when it does the exchange.

In MIPS this pair of instructions includes a special load called a load linked and a special
store called a store conditional.
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 These instructions are used in sequence: if the contents of the memory location specified
by the load linked are changed before the store conditional to the same address occurs, then
the store conditional fails.
 The store conditional is defined to both store the value of a register in memory and to
change the value of that register to a 1 if it succeeds and to a 0 if it fails.
 The following sequence implements an atomic exchange on the memory location
specified by the contents of $s1:
again: addi $t0,$zero,1 ;copy locked value
ll $t1,0($s1) ; load linked
sc $t0,0($s1) ; store conditional
beq $t0,$zero,again ;branch if store fails
add $s4,$zero,$t1 ;put load value in $s4

11.Translating and Starting a Program

In this describes the four steps in transforming a C program in a file on disk into a program
running on a computer. Figure shows the translation hierarchy.

Fig: A translation hierarchy for C.

i) Compiler: The compiler transforms the C program into an assembly language program, a
symbolic form of what the machine understands. High-level language programs take many
fewer lines of code than assembly language, so programmer productivity is much higher.
Assembly Language: A symbolic language that can be translated into binary machine
language

ii) Assembler: The assembler converts this assembly language instruction into the machine
language.
Pseudoinstruction: A common variation of assembly language instruction often treated as if it
were an instruction in its own right.

Thus, the MIPS assembler accepts the instruction even though it is not found in the MIPS
architecture:
move $t0,$t1 # register $t0 gets register $t1
The assembler converts this assembly language instruction into the machine language
equivalent of the following instruction:
add $t0,$zero,$t1 # register $t0 gets 0 + register $t1

The MIPS assembler also converts blt (branch on less than) into the two instructions slt and
bne.
blt $t0, $t1, L → slt $at, $t0, $t1
bne $at, $zero, L

 Pseudoinstructions give MIPS a richer set of assembly language instructions than those
implemented by the hardware.
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 The primary task of an assembler is assembly into machine code. The assembler turns the
assembly language program into an object file, which is a combination of machine language
instructions, data, and information needed to place instructions properly in memory.
 To produce the binary version of each instruction in the assembly language program, the
assembler must determine the addresses corresponding to all labels. Assemblers keep track of
labels used in branches and data transfer instructions in a symbol table.
Symbol Table: A table that matches names of labels to the addresses of the memory words
that instructions occupy.

iii) Linker: Also called link editor. A systems program that combines independently
assembled machine language programs and resolves all undefined labels into an executable
file.
 Executable file: A functional program in the format of an object file that contains no
unresolved references. It can contain symbol tables and debugging information.
There are three steps for the linker:
1. Place code and data modules symbolically in memory.
2. Determine the addresses of data and instruction labels.
3. Patch both the internal and external references.

iv) Loader: A systems program that places an object program in main memory so that it is
ready to execute.
The executable file is on disk the operating system reads it to memory and start it.

 Dynamically Linked Libraries (DLL)

Dynamically Linked Libraries (DLLs): Library routines that are linked to a program during
execution.
Both the program and library routines keep extra information on the location of nonlocal
procedures and their names. In the initial version of DLLs, the loader ran a dynamic linker,
using the extra information in the file to find the appropriate libraries and to update all
external references.

 Starting a Java Program

 Figure shows the typical translation and execution steps for Java. Rather than compile to
the assembly language of a target computer, Java is compiled first to instructions that are easy
to interpret: the Java bytecode instruction set.
 Java bytecode: Instruction from an instruction set designed to interpret Java programs.

Fig: A translation hierarchy for Java.

 The Java compiler checks the types of data and produces the proper operation for each
type.
 Java programs are distributed in the binary version of these bytecodes. A software
interpreter, called a Java Virtual Machine (JVM), can execute Java bytecodes. An
interpreter is a program that simulates an instruction set architecture.
 Just In Time compiler (JIT): The name commonly given to a compiler that operates at
runtime, translating the interpreted code segments into the native code of the computer.

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12.A C Sort Example to Put It All Together
The MIPS code from two procedures written in C: one to swap array elements and one to sort
them.

 Example1: The Full swap Procedure

 C code: A C procedure that swaps two locations in memory.
void swap(int v[ ], int k)
{
Int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}

 MIPS Assembly Language:

 The Procedure swap: The code for the procedure swap. This procedure simply swaps
two locations in memory.
 Register Allocation for swap: The MIPS convention on parameter passing is to use
registers $a0, $a1, $a2, and $a3.
Swap has just two parameters, v and k, they will be found in registers $a0 and $a1. The only
other variable is temp, which we associate with register $t0.
 Code for the Body of the Procedure swap:
the first step is to get the address of v[k] by multiplying k by 4 via a shift left by 2:
sll $t1, $a1,2 # reg $t1 = k * 4
add $t1, $a0,$t1 # reg $t1 = v + (k * 4)
# reg $t1 has the address of v[k]
Now we load v[k] using $t1, and then v[k+1] by adding 4 to $t1:
lw $t0, 0($t1) # reg $t0 (temp) = v[k]
lw $t2, 4($t1) # reg $t2 = v[k + 1]
# refers to next element of v
Next we store $t0 and $t2 to the swapped addresses:
sw $t2, 0($t1) # v[k] = reg $t2
sw $t0, 4($t1) # v[k+1] = reg $t0 (temp)

 The Full swap Procedure: MIPS assembly code of the procedure swap

 Example 2:The Procedure sort

 C version of the program:
void sort (int v[ ], int n)
{
int i, j;
for (i = 0; i< n; i += 1)
{
for (j = i – 1; j >= 0 && v[j] >v[j + 1]; j =1)
{
swap(v,j);

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 }
}
}

 MIPS assembly version of procedure sort: v in $a0, n in $a1, i in $s0, j in $s1

13.Arrays versus Pointers

This section shows C and MIPS assembly versions of two procedures to clear a sequence of
words in memory: one using array indices and one using pointer.
 Array Version of Clear
 C procedure for setting an array to all zeros.
clear1 (int array[ ], int size)
{
Int i;
for (i = 0; i< size; i += 1)
array[i] = 0;
}

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 MIPS Assembly Language:
Let’s start with the array version clear1. We assume that the two parameters array and size
are found in the registers $a0 and $a1, and that i is allocated to register $t0.
clear1:
move $t0,$zero #i=0
loop1: sll $t1,$t0,2 # $t1 = i * 4
add $t2,$a0,$t1 # $t2 = address of array[i]
sw $zero, 0($t2) # array[i] = 0
addi $t0,$t0,1 #i=i+1
slt $t3,$t0,$a1 # $t3 = (i< size)
bne $t3,$zero,loop1 # if (i< size) go to loop1

 Pointer Version of Clear

clear2(int *array, int size)
{
int *p;
for (p = &array[0]; p <&array[size]; p = p + 1)
*p = 0;
}
 MIPS Assembly Language:
The procedure that uses pointers allocates the two parameters array and size to the registers
$a0 and $a1 and allocates p to register $t0.
clear2:
move $t0, $a0 # p = &array[0]
sll $t1, $a1, 2 # $t1 = size * 4
add $t2, $a0, $t1 # $t2 = &array[size]
loop2: sw $zero, 0($t0) # Memory[p] = 0
addi $t0, $t0, 4 #p=p+4
slt $t3, $t0, $t2 # $t3 = (p<&array[size])
bne $t3, $zero, loop2 # if (p<&array[size]) goto loop2
jr $ra # return to calling routine

14.ARMv7 (32-bit) Instructions

ARM is the most popular instruction set architecture for embedded devices, with more than 9
billion devices in 2011 using ARM, and recent growth has been 2 billion per year.
Standing originally for the Acorn RISC Machine, later changed to Advanced RISC Machine,
ARM came out the same year at MIPS and followed similar philosophies. Figure lists the
similarities.
 The principal difference is the MIPS has more registers and ARM has more addressing
modes.

Fig: Similarities in ARM and MIPS instruction sets.

There is a similar core of instruction sets for arithmetic-logical and data transfer instructions
for MIPS and ARM, as Figure shows.

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 Fig: ARM register-register and data transfer instructions equivalent to MIPS core.

 Addressing Modes
Figure shows the data addressing modes supported by ARM. Unlike MIPS, ARM does not
reserve a register to contain 0. Although MIPS has just three simple data addressing modes,
ARM has nine.

Fig: Summary of data addressing modes.

Figure shows the instruction formats for ARM and MIPS. The principal differences are the
4-bit conditional execution field in every instruction and the smaller register field, because
ARM has half the number of registers.

Fig: Instruction formats, ARM and MIPS.

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 Unique Features of ARM
Figure shows a few arithmetic-logical instructions not found in MIPS. Since ARM does not
have a dedicated register for 0, it has separate opcodes to perform some operations that MIPS
can do with $zero. In addition, ARM has support for multiword arithmetic.

Fig: ARM arithmetic/logical instructions not found in MIPS.

15.x86 Instructions
 x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set
computer (CISC) instruction set architectures[a] initially developed by Intel based on the Intel
8086 microprocessor and its 8088 variant.
 x86 started out as a 16-bit instruction set for 16-bit processors (the 8086 and 8088
processors), then was extended to a 32-bit instruction set for 32-bit processors (80386 and
80486), and now has been extended to a 64-bit instruction set for 64-bit processors.

 x86 Registers and Data Addressing Modes

 Basic x86 Registers
 The 80386 extended all 16-bit registers (except the segment registers) to 32 bits, prefixing
an E to their name to indicate the 32-bit version.
 The 80386 contains only eight GPRs (general-purpose registers). This means MIPS
programs can use four times (32 registers) as many and ARMv7 twice (16 registers) as
many.
 The 8086 provides support for both 8-bit (byte) and 16-bit (word) data type.
 The 80386 add 32-bit address and data (double words) in the x86.

Fig: The 80386-register set.

Starting with the 80386, the top eight registers were extended to 32 bits and could also be
used as general-purpose registers.
25
 x86instructions
Figure shows the arithmetic, logical, and data transfer instructions are two-operand
instructions.
There are two important differences here.
 The x86 arithmetic and logical instructions must have one operand act as both a
source and a destination; ARMv7 and MIPS allow separate registers for source and
destination.
 The second important difference is that one of the operands can be in memory. Thus,
virtually any instruction may have one operand in memory, unlike ARMv7 and MIPS.

Fig: Instruction types for the arithmetic, logical, and data transfer instructions.

 x86 addressing modes

Figure shows the x86 addressing modes and which GPRs cannot be used with each mode, as
well as how to get the same effect using MIPS instructions.

Fig: x86 32-bit addressing modes and the equivalent MIPS code.
 x86 Integer Operations
The 8086 provides support for both 8-bit (byte) and 16-bit (word) data types. Th e 80386
adds 32-bit addresses and data (double words) in the x86. (AMD64 adds 64-bit addresses and
data, called quad words).
 The x86 integer operations can be divided into four major classes:
1. Data movement instructions, including move, push, and pop
2. Arithmetic and logic instructions, including test, integer, and decimal arithmetic operations
3. Control flow, including conditional branches, unconditional jumps, calls, and returns
4. String instructions, including string move and string compare

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 x86 Instruction Encoding
The encoding of instructions in the 80386 is complex, with many different instruction
formats. Instructions for the 80386 may vary from 1 byte up to 15 bytes.

Fig: Typical x86 instruction formats.

16.ARMv8 (64-bit) Instructions

ARM architects could see the writing on the wall of their 32-bit address computer, and began
design of the 64-bit address version of ARM in 2007. It was finally revealed in 2013.
The good news is that if you know MIPS it will be very easy to pick up ARMv8, as the 64-bit
version is called
First, as compared to MIPS, ARM dropped virtually all of the unusual features of v7:
■ There is no conditional execution field, as there was in nearly every instruction in v7.
■ The immediate field is simply a 12 bit constant, rather than essentially an input to a
function that produces a constant as in v7.
■ ARM dropped Load Multiple and Store Multiple instructions.
■ The PC is no longer one of the registers, which resulted in unexpected branches if you
wrote to it.
Second, ARM added missing features that are useful in MIPS
■ V8 has 32 general-purpose registers, which compiler writers surely love. Like MIPS, one
register is hardwired to 0, although in load and store instructions it instead refers to the stack
pointer.
■ Its addressing modes work for all word sizes in ARMv8, which was not the case in
ARMv7.
■ It includes a divide instruction, which was omitted from ARMv7.
■ It adds the equivalent of MIPS branch if equal and branch if not equal. As the philosophy
of the v8 instruction set is much closer to MIPS than it is to v7, our conclusion is that the
main similarity between ARMv7 and ARMv8 is the name.
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