CSE231 – Digital Logic Design

Lecture – 6 Lesson Outcomes

Latches,
Flip-Flops After completing this lecture, students will be able to
• Use logic gates to construct basic latches

and Their • Recognize the difference between a latch and a flip-flop

• Understand the significance of propagation delays, set-
up time, hold time, maximum operating frequency,

Applications
minimum clock pulse widths, and power dissipation in
the application of flip-flops
• Apply flip-flops in basic applications

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 Key Terms

 Astable Having no stable state. An astable multivibrator oscillates between two quasi-
stable states.
 Bistable Having two stable states. Flip-flops and latches are bistable multivibrators.
 Clock The triggering input of a flip-flop.
 D flip-flop A type of bistable multivibrator in which the output assumes the state of
the D input on the triggering edge of a clock pulse.
 Edge-triggered flip-flop A type of flip-flop in which the data are entered and appear
on the output on the same clock edge.
 Hold time The time interval required for the control levels to remain on the inputs to a
flip-flop after the triggering edge of the clock in order to reliably activate the device.
 J-K flip-flop A type of flip-flop that can operate in the SET, RESET, no-change, and
toggle modes.
 Latch A bistable digital circuit used for storing a bit.

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 Key Terms

 Monostable Having only one stable state. A monostable multivibrator, commonly called a
oneshot, produces a single pulse in response to a triggering input.
 One-shot A monostable multivibrator.
 Preset An asynchronous input used to set a flip-flop (make the Q output 1).
 Propagation delay time The interval of time required after an input signal has been
applied for the resulting output change to occur.
 RESET The state of a flip-flop or latch when the output is 0; the action of producing a
RESET state.
 SET The state of a flip-flop or latch when the output is 1; the action of producing a SET
state.
 Set-up time The time interval required for the control levels to be on the inputs to a
digital circuit, such as a flip-flop, prior to the triggering edge of a clock pulse.
 Synchronous Having a fixed time relationship.
 Timer A circuit that can be used as a one-shot or as an oscillator.
 Toggle The action of a flip-flop when it changes state on each clock pulse.
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 Latch (NAND latch, NOR latch)

 The latch is a type of temporary storage device that has two stable states (bistable)
and is normally placed in a category separate from that of flip-flops.
 Latches are similar to flip-flops because they are bistable devices that can reside in
either of two states using a feedback arrangement, in which the outputs are
connected back to the opposite inputs.
 The main difference between latches and flip-flops is in the method used for changing
their state.

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 S-R Latch
 A latch is a type of bistable logic device or multivibrator.
 An active-HIGH input S-R (SET-RESET) latch is formed with two cross-coupled NOR
gates, as shown in Figure (a); an active-LOW input S R latch is formed with two cross-
coupled NAND gates, as shown in Figure (b).
 The outputs of a latch are always complements of each other.

Negative-OR
equivalent
of S R latch

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 S-R latch

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 Gated S-R Latch

 A gated latch requires an enable input, EN (G is also used to designate an enable

input). The logic diagram and logic symbol for a gated S-R latch are shown in Figure.
The S and R inputs control the state to which the latch will go when a HIGH level is
applied to the EN input.

 The latch will not change until EN is HIGH; but as long as it remains HIGH, the output is
controlled by the state of the S and R inputs.

 The gated latch is a level-

sensitive device. In this
circuit, the invalid state
occurs when both S and R
are simultaneously HIGH
and EN is also HIGH.

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 Gated S-R Latch

 PROBLEM. Determine the Q output

waveform if the inputs shown in
Figure 7–9(a) are applied to a gated
S-R latch that is initially RESET.

SOLUTION:
 When S is HIGH and R is LOW, a
HIGH on the EN input sets the latch.
When S is LOW and R is HIGH, a
HIGH on the EN input resets the
latch.
 When both S and R are LOW, the Q
output does not change from its
present state.
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 Flip-Flops

 Flip-flops are synchronous bistable devices,

also known as bistable multivibrators.
 In this case, the term synchronous means
that the output changes state only at a
specified point (leading or trailing edge) on
the triggering input called the clock (CLK),
which is designated as a control input, C;
that is, changes in the output occur in
synchronization with the clock.
 Flip-flops are edge-triggered or edge-
sensitive whereas gated latches are level-
sensitive.

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 Edge-triggered Flip-Flops

 An edge-triggered flip-flop changes state either at the positive edge (rising edge) or at
the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at
this transition of the clock.
 Two types of edge-triggered flip-flops are: D and J-K.
 The key to identifying an edge-triggered flip-flop by its logic symbol is the small
triangle inside the block at the clock (C) input. This triangle is called the dynamic input
indicator.

Positive edge-triggered flip-flops Negative edge-triggered flip-flops

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 D Flip-Flops

 The D input of the D flip-flop is a synchronous input because data on the input are
transferred to the flip-flop’s output only on the triggering edge of the clock pulse.
 When D is HIGH, the Q output goes HIGH on the triggering edge of the clock pulse,
and the flip-flop is SET.
 When D is LOW, the Q output goes LOW on the triggering edge of the clock pulse, and
the flip-flop is RESET.

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 D Flip-Flops

 This basic operation of a positive edge-

triggered D flip-flop is illustrated in Figure
7–14, and Table 7–2 is the truth table for this
type of flip-flop.

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 D Flip-Flops

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 J-K Flip-Flops

 The J and K inputs of the J-K flip-

flop are synchronous inputs because
data on these inputs are transferred to
the flip-flop’s output only on the
triggering edge of the clock pulse.
 When J is HIGH and K is LOW, the Q
output goes HIGH on the triggering
edge of the clock pulse, and the flip-
flop is SET.
 When J is LOW and K is HIGH, the Q
output goes LOW on the triggering
edge of the clock pulse, and the flip-
flop is RESET.
 When both J and K are LOW, the
output does not change from its prior
state. When J and K are both HIGH,
the flip-flop changes state. This called
the toggle mode.

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 J-K Flip-Flops
 This basic operation of a positive edge-triggered flip-flop is illustrated in Figure 7–17, and Table
7–3 is the truth table for this type of flip-flop.
 The flip-flop cannot change state except on the triggering edge of a clock pulse.
 The J and K inputs can be changed at any time when the clock input is LOW or HIGH (except for
a very short interval around the triggering transition of the clock) without affecting the output.

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 J-K Flip-Flops

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 Edge triggering

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 Edge-triggered D flip-flops (RESET to SET)

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 Edge-triggered D flip-flops (SET to RESET)

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 Propagation delays, set-up time, hold-time

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 Maximum clock frequency, pulse width and power dissipation

 The maximum clock frequency (fmax) is the highest rate at which a flip-flop can be
reliably triggered. At clock frequencies above the maximum, the flip-flop would be
unable to respond quickly enough, and its operation would be impaired.

 Minimum pulse widths (tW) for reliable operation are usually specified by the
manufacturer for the clock, preset, and clear inputs. Typically, the clock is specified
by its minimum HIGH time and its minimum LOW time.

 The power dissipation of any digital circuit is the total power consumption of the
device. For example, if the flip-flop operates on a +5 V dc source and draws 5 mA of
current, the power dissipation is

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 Flip-Flops applications – parallel data transfer

 Flip-flops are used in

 parallel data transfer / storage,
 frequency division and
 basic counter applications.

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 Flip-Flops applications – data storage
 Flip-flops are used in data storage, frequency
division and basic counter applications.

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 Flip-Flops applications – serial data transfer

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 Serial data transfer between registers

 Figure shows two three-bit shift

registers using D flip-flops. Contents of
the X register will be serially transferred
(shifted) into register Y.

 Notice how X0, the last FF of register X,

is connected to the D input of Y2, the
first FF of register Y.

 The shift pulses are applied, the

information transfer takes place as
follows: X2X1X0Y2Y1Y0.

 Flip-flop X2 will go to a state

determined by its D input. For now, D
will be held LOW, so that X2 will go LOW
on the first pulse and will remain there.

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 Flip-Flops applications – frequency division

 When a pulse waveform is applied to the clock input of a D or J-K flip-flop that is
connected to toggle (D = Q or J = K = 1), the Q output is a square wave with one-half
the frequency of the clock input.
 Thus, a single flip-flop can be applied as a divide-by-2 device.

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 Flip-flop application – frequency division

PROBLEM. Determine the output

waveforms in relation to the clock for QA,
QB, and QC in the circuit of Fig. and show
the binary sequence represented by
these waveforms.
SOLUTION:

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 Flip-flops applications – counting (2-bit)

 Another important application of flip-flops is in digital counters.

 Negative edge trigger is considered. Both flip-flops are initially RESET.
 Flip-flop A toggle on the negative-going transition of each clock pulse.

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 Flip-flops applications – counting (3-bit)

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 References

1. Digital Fundamentals by Thomas Floyd, Pearson International Edition,

11th Edition, Chapter 7, Page 387-448.

2. Digital Systems: Principles and Applications by Ronald Tocci, Neal

Widmer and Greg Moss, Pearson International Edition, 12th Edition,
Chapter 5, Page 236-339.

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 Next class

Register

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