CS1104 Computer Organization

http://www.comp.nus.edu.sg/~cs1104

Aaron Tan Tuck Choy

School of Computing
National University of Singapore

Lecture 11: Sequential Logic

Latches & Flip-flops
Introduction
Memory Elements
Pulse-Triggered Latch
S-R Latch
Gated S-R Latch
Gated D Latch

Edge-Triggered Flip-flops

S-R Flip-flop
D Flip-flop
J-K Flip-flop
T Flip-flop

Asynchronous Inputs
CS1104-11

Lecture 11: Sequential Logic:

Latches & Flip-flops

Introduction
A sequential circuit consists of a feedback path, and
employs some memory elements.
Combinational
outputs

Memory outputs

Combinational
logic

Memory
elements

External inputs

Sequential circuit = Combinational logic + Memory Elements

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Introduction

Introduction
There are two types of sequential circuits:
synchronous: outputs change only at specific time
asynchronous: outputs change at any time

Multivibrator: a class of sequential circuits. They

can be:
bistable (2 stable states)
monostable or one-shot (1 stable state)
astable (no stable state)

Bistable logic devices: latches and flip-flops.

Latches and flip-flops differ in the method used for
changing their state.
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Introduction

Memory Elements
Memory element: a device which can remember
value indefinitely, or change value on command
from its inputs.
Q

Memory
element

command

stored value

Characteristic table:

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Command
(at time t)

Q(t)

Q(t+1)

Set

Reset

Memorise /
No Change

0
1

0
1

Q(t): current state

Q(t+1) or Q+: next state

Memory Elements

Memory Elements
Memory element with clock. Flip-flops are memory
elements that change state on clock signals.
Memory
element

command

stored value

clock

Clock is usually a square wave.

Positive pulses

Positive edges
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Negative edges
Memory Elements

Memory Elements
Two types of triggering/activation:
pulse-triggered
edge-triggered

Pulse-triggered
latches
ON = 1, OFF = 0

Edge-triggered
flip-flops
positive edge-triggered (ON = from 0 to 1; OFF = other

time)
negative edge-triggered (ON = from 1 to 0; OFF = other
time)
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Memory Elements

S-R Latch
Complementary outputs: Q and Q'.
When Q is HIGH, the latch is in SET state.
When Q is LOW, the latch is in RESET state.
For active-HIGH input S-R latch (also known as NOR
gate latch),
R=HIGH (and S=LOW) RESET state
S=HIGH (and R=LOW) SET state
both inputs LOW no change
both inputs HIGH Q and Q' both LOW (invalid)!

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S-R Latch

S-R Latch
For active-LOW input S'-R' latch (also known as NAND
gate latch),
R'=LOW (and S'=HIGH) RESET state
S'=LOW (and R'=HIGH) SET state
both inputs HIGH no change
both inputs LOW Q and Q' both HIGH (invalid)!

Drawback of S-R latch: invalid condition exists and

must be avoided.

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S-R Latch

S-R Latch
Characteristics table for active-high input S-R latch:
S

Q'

NC

NC

1
0
1

0
1
1

1
0
0

0
1
0

No change. Latch
remained in present state.
Latch SET.
Latch RESET.
Invalid condition.

Q'

Characteristics table for active-low input S'-R' latch:

S'

R'

Q'

NC

NC

0
1
0

1
0
0

1
0
1

0
1
1

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No change. Latch
remained in present state.
Latch SET.
Latch RESET.
Invalid condition.

S-R Latch

Q'

10

S-R Latch
Active-HIGH input S-R latch
10 100 R

Q 11000

10 001 S

Q' 0 0 1 1 0

S
1
0
0
0
1

R
0
0
1
0
1

Q Q'
1 0
initial
1 0 (afer S=1, R=0)
0 1
0 1 (after S=0, R=1)
0 0
invalid!

Active-LOW input S-R latch

S'
R'

Q
Q'

S'

R'
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Q
Q'
S-R Latch

S' R'
1 0
1 1
0 1
1 1
0 0

Q Q'
0 1
initial
0 1 (afer S'=1, R'=0)
1 0
1 0 (after S'=0, R'=1)
1 1
invalid!
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Gated S-R Latch

S-R latch + enable input (EN) and 2 NAND gates
gated S-R latch.
S

EN

EN

Q'

Q'

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Gated S-R Latch

12

Gated S-R Latch

Outputs change (if necessary) only when EN is
HIGH.

Under what condition does the invalid state occur?

Characteristic table:
EN=1
Q(t)

Q(t+1)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
1
indeterminate
1
0
1
indeterminate

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S R
0
0
1
1

Gated S-R Latch

0
1
0
1

Q(t+1)
No change
Q(t)
0
Reset
1
Set
indeterminate

Q(t+1) = S + R'.Q
S.R = 0
13

Gated D Latch
Make R input equal to S' gated D latch.
D latch eliminates the undesirable condition of invalid
state in the S-R latch.
D

EN

EN

Q'

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Gated D Latch

Q'

14

Gated D Latch
When EN is HIGH,
D=HIGH latch is SET
D=LOW latch is RESET

Hence when EN is HIGH, Q follows the D (data)

input.

Characteristic table:
EN

Q(t+1)

1
1
0

0
1
X

0
1
Q(t)

Reset
Set
No change

When EN=1, Q(t+1) = D

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Gated D Latch

15

Latch Circuits: Not Suitable

Latch circuits are not suitable in synchronous logic
circuits.

When the enable signal is active, the excitation

inputs are gated directly to the output Q. Thus, any

change in the excitation input immediately causes a
change in the latch output.

The problem is solved by using a special timing

control signal called a clock to restrict the times at

which the states of the memory elements may
change.

This leads us to the edge-triggered memory

elements called flip-flops.

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Gated D Latch

16

Edge-Triggered Flip-flops
Flip-flops: synchronous bistable devices
Output changes state at a specified point on a
triggering input called the clock.

Change state either at the positive edge (rising edge)

or at the negative edge (falling edge) of the clock
signal.
Clock signal
Positive edges

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Negative edges

Edge-Triggered Flip-flops

17

Edge-Triggered Flip-flops
S-R, D and J-K edge-triggered flip-flops. Note the >
symbol at the clock input.
S

C
R

C
Q'

C
Q'

Q'

Positive edge-triggered flip-flops

S

C
R

C
Q'

C
Q'

Q'

Negative edge-triggered flip-flops

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Edge-Triggered Flip-flops

18

S-R Flip-flop
S-R flip-flop: on the triggering edge of the clock pulse,

S=HIGH (and R=LOW) SET state

R=HIGH (and S=LOW) RESET state
both inputs LOW no change
both inputs HIGH invalid

Characteristic table of positive edge-triggered S-R flipflop:

CLK

Q(t+1)

Comments

0
0
1
1

0
1
0
1

Q(t)
0
1
?

No change
Reset
Set
Invalid

X = irrelevant (dont care)

= clock transition LOW to HIGH
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SR Flip-flop

19

S-R Flip-flop
It comprises 3 parts:
a basic NAND latch
a pulse-steering circuit
a pulse transition detector (or edge detector) circuit

The pulse transition detector detects a rising (or

falling) edge and produces a very short-duration
spike.

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SR Flip-flop

20

S-R Flip-flop
The pulse transition detector.
S

Pulse
transition
detector

CLK

Q'

CLK'
CLK

CLK'
CLK*

CLK*

CLK

CLK

CLK'

CLK'

CLK*

CLK*

Positive-going transition
(rising edge)
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CLK

Negative-going transition
(falling edge)
SR Flip-flop

21

D Flip-flop
D flip-flop: single input D (data)
D=HIGH SET state
D=LOW RESET state

Q follows D at the clock edge.

Convert S-R flip-flop into a D flip-flop: add an inverter.
D
CLK

C
R

CLK

Q(t+1)

1
0

1
0

Comments
Set
Reset

Q'
= clock transition LOW to HIGH

A positive edge-triggered D flipflop formed with an S-R flip-flop.

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D Flip-flop

22

D Flip-flop
Application: Parallel data transfer.
To transfer logic-circuit outputs X, Y, Z to flip-flops Q1,
Q2 and Q3 for storage.
D
CLK
X

Combinational
logic circuit

CLK

D
Transfer

CLK

Q1 = X*

Q'
Q

Q2 = Y*

Q'
Q

Q3 = Z*

Q'

* After occurrence of negative-going transition

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D Flip-flop

23

J-K Flip-flop
J-K flip-flop: Q and Q' are fed back to the pulsesteering NAND gates.

No invalid state.
Include a toggle state.
J=HIGH (and K=LOW) SET state
K=HIGH (and J=LOW) RESET state
both inputs LOW no change
both inputs HIGH toggle

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J-K Flip-Ffop

24

J-K Flip-flop
J-K flip-flop.
J
Q

Pulse
transition
detector

CLK

Q'

Characteristic table.
J

CLK

Q(t+1)

Comments

0
0
1
1

0
1
0
1

Q(t)
0
1
Q(t)'

No change
Reset
Set
Toggle

Q(t+1) = J.Q' + K'.Q

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J-K Flip-flop

J K

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Q(t+1)
0
0
1
1
1
0
1
0
25

T Flip-flop
T flip-flop: single-input version of the J-K flip flop,
formed by tying both inputs together.
T
Pulse
transition
detector

CLK

CLK
Q'

Q'

Characteristic table.
T

CLK

Q(t+1)

Comments

Q T

0
1

Q(t)
Q(t)'

No change
Toggle

0
0
1
1

0
1
0
1

Q(t+1)
0
1
1
0

Q(t+1) = T.Q' + T'.Q

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T Flip-flop

26

T Flip-flop
Application: Frequency division.
High

High
J

CLK

High

CLK

K
CLK

CLK

QA

QA

QB

QB

Divide clock frequency by 2.

Divide clock frequency by 4.

Application: Counter (to be covered in Lecture 13.)

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T Flip-flop

27

Asynchronous Inputs
S-R, D and J-K inputs are synchronous inputs, as

data on these inputs are transferred to the flip-flops

output only on the triggered edge of the clock pulse.

Asynchronous inputs affect the state of the flip-flop

independent of the clock; example: preset (PRE) and

clear (CLR) [or direct set (SD) and direct reset (RD)]

When PRE=HIGH, Q is immediately set to HIGH.

When CLR=HIGH, Q is immediately cleared to LOW.
Flip-flop in normal operation mode when both PRE
and CLR are LOW.

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Asynchronous Inputs

28

Asynchronous Inputs
A J-K flip-flop with active-LOW preset and clear inputs.
PRE

PRE
J

CLK

Q'

Q
Pulse
transition
detector
Q'

K
CLR

CLR
CLK
PRE
CLR

J = K = HIGH
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Preset
Asynchronous Inputs

Toggle

Clear
29

End of segment