Sequential Circuits

Sequential Circuits
Present Output Depends on the Present Input, as well as past output/outputs.
Memory Element
Device which can remember value indefinitely, or change value on command from its inputs
Q(t) or Q : Current State
Q(t + 1) or Q+ : Next State
Command (at time t) Q(t) Q(t+1)

Set X 1
Reset X 0
Memorise / No Change 0 0
1 1
 Memory Element with Clock
 Two types of triggering/activation

o Pulse Triggered
 Latches
 ON = 1, OFF = 0
o Edge Triggered
 Flip Flops
 Positive edge triggered (ON = from 0 to 1; OFF = other time)
 Negative edge-triggered (ON = from 1 to 0; OFF = other time(
S (Set) -R (Reset) Latch
The basic storage element is called Latch. It latches “0” or “1”.
 Two Complementary Outputs: Q and Q’

 When Q = 1 (High), Latch is in Set state
 When Q = 0 (Low), Latch is in Reset State
 NOR Gate Latch
o R = 1, S = 0 -> Q = 0
o R = 0 , S = 1 -> Q = 1
o R = 0, S = 0 -> No Change in Q
o Both R and S are High -> Both Q and Q’ are both Low (Invalid Case)
Gated S-R Latch
S-R Latch + Enable Input (EN) and 2 NAND gates

Gated D-Latch
Makes input R equal to S’
 D Latch eliminates the undesirable condition of invalid state in the S-R latch
 When EN is high
o D = High -> latch is Set
o D = LOW -> latch is RESET
Flip-Flops
Flip-Flops are Synchronous bistable Devices.
 Output changes state at a specified point on a triggering input called the clock.
 Changes state either at the positive (rising) edge, or at the negative (falling) edge of the clock
signal
 Types of flip-flops
oS-R Flip-Flop
oD Flip-Flop
oJ-K Flip-Flop
S-R Flip Flop
On the triggering edge of the click pulse
 R = 1, S = 0 -> Q = 0
 R = 0, S = 1 -> Q = 1
 R = 0 , S = 0 -> No Change
 R and S are High -> Invalid
D Flip Flop
D Flip-Flop: Single Input D. On the triggering edge of the clock pulse
 D = 1 -> Q = 1
 D = 0 -> Q = 0
 To convert S-R flip-flop into a D flip-flop, add an inverter.
JK Flip Flop
Q and Q’ are fed back to the pulse steering NAND Gates
 Has no invalid state
Toggle Flip Flop
Single Input Version of the J-K Flip Flop.

Analysis of Sequential Circuits
Given a sequential circuit diagram, we can analyse its behaviour by deriving its state table and hence
its state diagram
 Requires state equations to be derived for the flip-flop inputs, as well as output functions for
the circuit outputs other than the flip-flops (if any)
 We use A(t) and A(t+1) to represent the present state and next state, respectively of a flip-
flop represented by A
State Table
 Similar to truth table

 Inputs and present state on the left side
 Outputs and next state on the right side
 m flip-flops and n inputs = 2m + n rows
State Diagram
 Each state is denoted by a circle.

 Each arrow denotes a transition of the sequential circuit.
 A label of the form a/b is attached to each arrow where a denotes the inputs while b denotes
the outputs of the circuit in that transition.
 Each combination of flip-flop values represents a state. Hence, m flip-flops -> up to 2m states
Flip-Flop Excitation Tables
Given the required transition from present state to next state, determine the flip-flop inputs
Sequential Circuits: Design
Design Procedure:
 Start with circuit specifications

 Derive the state table
 Perform state reduction if necessary
 Perform state assignment
 Determine number of flip-flops and label them
 Chose the type of flip-flop to be used
 Derive circuit excitation and output tables from the state table
 Derive circuit output functions and flip-flop input functions
 Draw the logic diagram
Augmented State Table
Memory
Memory stores programs and data

Read/Write Operations
Write Operation
 Transfers address of desired word to address lines

 Transfers data bits to be stored in memory to the data input lines
 Activates the Write control line
Read Operation
 Transfers the address of the desired word to the address lines

 Activates the Read control line
Memory Cell
Two Types of RAM
 Static RAMS use flip-flops as the memory cells

 Dynamic RAMS use capacitor charges to represent data. Though simpler in circuitry, they
have to be constantly refreshed

Sequential Circuits

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Sequential Circuits

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Sequential Circuits

Present Output Depends on the Present Input, as well as past output/outputs.

Q(t) or Q : Current State

Q(t + 1) or Q+ : Next State

Command (at time t) Q(t) Q(t+1)

 Memory Element with Clock

 Two types of triggering/activation

S (Set) -R (Reset) Latch

The basic storage element is called Latch. It latches “0” or “1”.

 Two Complementary Outputs: Q and Q’

S-R Latch + Enable Input (EN) and 2 NAND gates

Makes input R equal to S’

Flip-Flops are Synchronous bistable Devices.

S-R Flip Flop

On the triggering edge of the click pulse

Q and Q’ are fed back to the pulse steering NAND Gates

 Has no invalid state

Toggle Flip Flop

Single Input Version of the J-K Flip Flop.

 Similar to truth table

 Each state is denoted by a circle.

Flip-Flop Excitation Tables

 Start with circuit specifications

Augmented State Table

Memory stores programs and data

 Transfers address of desired word to address lines

 Transfers the address of the desired word to the address lines

Two Types of RAM

 Static RAMS use flip-flops as the memory cells

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