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FAN5069 PWM and LDO Controller Combo
September 2006

FAN5069
PWM and LDO Controller Combo
Features Description
■ General Purpose PWM Regulator and LDO Controller The FAN5069 combines a high-efficiency Pulse-Width-
■ Input Voltage Range: 3V to 24V Modulated (PWM) controller and an LDO (Low DropOut)
■ Output Voltage Range: 0.8V to 15V linear regulator controller. Synchronous rectification pro-
– VCC vides high efficiency over a wide range of load currents.
Efficiency is further enhanced by using the low-side
– 5V
MOSFET’s RDS(ON) to sense current.
■ Shunt Regulator for 12V Operation
■ Support for Ceramic Cap on PWM Output Both the linear and PWM regulator soft-start are con-
trolled by a single external capacitor, to limit in-rush cur-
■ Programmable Current Limit for PWM Output
rent from the supply when the regulators are first
■ Programmable Switching Frequency (200KHz to
enabled. Current limit for PWM is also programmable.
600KHz)
■ RDS(ON) Current Sensing The PWM regulator employs a summing-current-mode
■ Internal Synchronous Boot Diode control with external compensation to achieve fast load
transient response and provide design optimization.
■ Soft-Start for both PWM and LDO
■ Multi-Fault Protection with Optional Auto-restart FAN5069 is offered in both industrial temperature grade
■ 16-pin TSSOP Package (-40°C to +85°C) as well as commercial temperature
grade (-10°C to +85°C).
Applications
■ PC/Server Motherboard Peripherals
– VCC_MCH (1.5V), VDDQ (1.5V) and
VTT_GTL (1.25V)
■ Power Supply for
– FPGA, DSP, Embedded Controllers, Graphic Card
Processor, and Communication Processors
■ Industrial Power Supplies
■ High-Power DC-to-DC Converters

Ordering Information
Part Number Operating Temp. Range Pb-Free Package Packing Method Qty./Reel
FAN5069MTCX -10°C to +85°C Yes 16-Lead TSSOP Tape and Reel 2500
FAN5069EMTCX -40°C to +85°C Yes 16-Lead TSSOP Tape and Reel 2500

Note: Contact Fairchild sales for availability of other package options.

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5
FAN5069 PWM and LDO Controller Combo
Typical Application
RVCC
+12V 3 TO 24V
VCC R8
15 FAN5069 R(RAMP)
14
+5V C9
BOOT
EN 11
7
C3 SS C5 Q1
4
C4 C7
R4 ILIM
3 HDRV
PWM 10
R5 R(T) L1 PWM OUT
SW
2 9
AGND Q2
8
LDRV C6
PWM OUT 13 R1
PGND
12
Q3
GLDO FB
16 6
ULDO C2 C1
LDO OUT R7 FBLDO CONTROL R3 R2
1 COMP
5
C8
R6

Figure 1. Typical Application Diagram

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 2
FAN5069 PWM and LDO Controller Combo
Pin Assignment
FBLDO 1 16 GLDO
R(T ) 2 15 VCC
ILIM 3 14 R(RAMP)
SS 4 13 LDRV
FAN5069
COMP 5 12 PGND
FB 6 11 BOOT
EN 7 10 HDRV
AGND 8 9 SW

Figure 2. Pin Assignment

Pin Description
Pin # Name Description
1 FBLDO LDO Feedback. This node is regulated to VREF.
2 R(T) Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By plac-
ing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased.
3 ILIM Current Limit. A resistor from this pin to GND sets the current limit.
4 SS Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the
LDO during initialization. It also sets the time by which the converter delays when restarting
after a fault occurs. SS has to reach 1.2V before fault shutdown feature is enabled. The LDO
is enabled when SS reaches 2.2V.
5 COMP COMP. The output of the error amplifier drives this pin.
6 FB Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combi-
nation with the COMP pin, to compensate the feedback loop of the converter.
7 EN Enable. Enables operation when pulled to logic high. Toggling EN resets the regulator after a
latched fault condition. This is a CMOS input whose state is indeterminate if left open and
needs to be properly biased at all times.
8 AGND Analog Ground. The signal ground for IC. All internal control voltages are referred to this pin.
Tie this pin to the ground island/plane through the lowest impedance connection available.
9 SW Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect
to source of high-side MOSFET and drain of low-side MOSFET.
10 HDRV High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This
pin is also monitored by the adaptive shoot-through protection circuitry to determine when the
high-side MOSFET is turned off.
11 BOOT Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver.
Connect to bootstrap capacitor as shown in Figure 1.
12 PGND Power Ground. The return for the low-side MOSFET driver. Connect to the source of the low-
side MOSFET.
13 LDRV Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin
is also monitored by the adaptive shoot-through protection circuitry to determine when the
lower MOSFET is turned off.
14 R(RAMP) Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage
feed-forward.
15 VCC VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic
capacitor as close to this pin as possible. This pin has a shunt regulator which draws current
when the input voltage is above 5.6V.
16 GLDO Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V.

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 3
FAN5069 PWM and LDO Controller Combo
Absolute Maximum Ratings
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are
not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the condi-
tions for actual device operation. (1)

Parameter Min. Max. Unit


VCC to PGND 6.0 V
BOOT to PGND 33.0 V
SW to PGND Continuous -0.5 33.0 V
Transient (t < 50nS, F < 500kHz) -3.0 33.0 V
HDRV (VBOOT- – VSW) 6.0 V
LDRV -0.5 6.0 V
All Other Pins -0.3 VCC + 0.3 V
Maximum Shunt Current for VCC 150 mA
Electrostatic Discharge Protection (ESD) HBM 3.5 kV
Level(2) CDM 1.8

Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are referenced to AGND.
2. Using Mil Std. 883E, method 3015.7(Human Body Model) and EIA/JESD22C101-A (Charge Device Model).

Thermal Information
Symbol Parameter Min. Typ. Max. Unit
TSTG Storage Temperature -65 150 °C
TL Lead Soldering Temperature, 10 Seconds 300 °C
Vapor Phase, 60 Seconds 215 °C
Infrared, 15 Seconds 220 °C
PD Power Dissipation, TA = 25°C 715 mW
θJC Thermal Resistance, Junction-to-Case 37 °C/W
θJA Thermal Resistance, Junction-to-Ambient (3)
100 °C/W

Notes:
3. Junction-to-ambient thermal resistance, θJA, is a strong function of PCB material, board thickness, thickness and
number of copper planes, number of vias used, diameter of vias used, available copper surface, and attached heat
sink characteristics.

Recommended Operating Conditions


Symbol Parameter Conditions Min. Typ. Max. Unit
VCC Supply Voltage VCC to GND 4.5 5.0 5.5 V
Commercial -10 85 °C
TA Ambient Temperature
Industrial -40 85 °C
TJ Junction Temperature 125 °C

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 4
FAN5069 PWM and LDO Controller Combo
Electrical Characteristics
Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.

Symbol Parameter Conditions Min. Typ. Max. Unit


Supply Current
IVCC VCC Current (Quiescent) HDRV, LDRV Open • 2.6 3.2 3.8 mA
IVCC(SD) VCC Current (Shutdown) EN = 0V, VCC = 5.5V • 200 400 μA
IVCC(OP) VCC Current (Operating) EN = 5V, VCC = 5.0V, 10 15 mA
QFET = 20nC, FSW = 200kHz
VSHUNT VCC Voltage(6) Sinking 1mA to 100mA at VCC 5.5 5.9 V
Pin
Under-Voltage Lockout (UVLO)
UVLO(H) Rising VCC UVLO Threshold • 4.00 4.25 4.50 V
UVLO(L) Falling VCC UVLO Threshold • 3.60 3.75 4.00 V
VCC UVLO Threshold 0.50 V
Hysteresis
Soft-Start
ISS Current 10 μA
VLDOSTART LDO Start Threshold 2.2 V
VSSOK PWM Protection Enable 1.2 V
Threshold
Oscillator
FOSC Frequency R(T) = 56KΩ ± 1% 240 300 360 KHz
R(T) = Open 160 200 240 KHz
Frequency Range 160 600 KHz
ΔVRAMP Ramp Amplitude R(RAMP) = 330KΩ 0.4 V
(Peak-to-Peak)
Minimum ON Time F = 200kHz 200 nS.
Reference
VREF Reference Voltage TA = 0°C to 70°C • 790 800 810 mV
(Measured at FB Pin) TA = -40°C to 85°C • 788 800 812 mV
Current Amplifier Reference 160 mV
(at SW node)
Error Amplifier
DC Gain 80 dB
GBWP Gain-BW Product 25 MHz
S/R Slew Rate 10pF across COMP to GND 8 V/μS.
Output Voltage Swing No Load • 0.5 4.0 V
IFB FB Pin Source Current 1 μA
Gate Drive
RHUP HDRV Pull-up Resistor Sourcing • 1.8 3.0 Ω
RHDN HDRV Pull-down Resistor Sinking • 1.8 3.0 Ω
RLUP LDRV Pull-up Resistor Sourcing • 1.8 3.0 Ω
RLDN LDRV Pull-down Resistor Sinking • 1.2 2.0 Ω

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 5
FAN5069 PWM and LDO Controller Combo
Electrical Characteristics (Continued)
Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.

Symbol Parameter Conditions Min. Typ. Max. Unit


Protection/Disable
ILIM ILIMIT Source Current 9 10 11 μA
ISWPD SW Pull-down Current SW = 1V, EN = 0V 2 mA
VUV Under-Voltage Threshold As % of set point; 2μS noise fil- • 65 75 80 %
ter
VOV Over-Voltage Threshold As % of set point; 2μS noise fil- • 110 115 120 %
ter
TSD Thermal Shutdown 160 °C
Enable Threshold Voltage Enable Condition • 2.0 V
Enable Threshold Voltage Disable Condition • 0.8 V
Enable Source Current VCC = 5V 50 μA
(7)
LDO
VLDOREF Reference Voltage (mea- TA = 0°C to 70°C • 775 800 825 mV
sured at FBLDO pin) TA = -40°C to 85°C • 770 800 830 mV
Regulation 0A ≤ ILOAD ≤ 5A • 1.17 1.2 1.23 V
VLDO_DO Drop out Voltage ILOAD ≤ 5A and RDS-ON < 50mΩ 0.3 V
External Gate Drive VCC = 4.75V • 4.5 V
VCC = 5.6V • 5.3 V
Gate Drive Source Current 1.2 mA
Gate Drive Sink Current 400 μA

Notes:
4. All limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality
control.
5. AC specifications guaranteed by design/characterization (not production tested).
6. For a case when VCC is higher than the typical 5V VCC; voltage observed at VCC pin when the internal shunt
regulator is sinking current to keep voltage on VCC pin constant.
7. Test Conditions: VLDO_IN = 1.5V and VLDO_OUT = 1.2V

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 6
FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics

Figure 3. Dead Time Waveform Figure 6. PWM Load Transient (0 to 15A)

Figure 4. PWM Load Transient (0 to 5A) Figure 7. LDO Load Transient (0 to 2A)

Figure 5. PWM Load Transient (0 to 10A) Figure 8. LDO Load Transient (0 to 5A)

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 7
FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Continued)

Figure 9. PWM/LDO Power Up Figure 12. Enable ON (IPWM = 5A)

Figure 10. PWM/LDO Power Down Figure 13. Enable OFF (IPWM = 5A)

Figure 11. Auto Restart

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 8
FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Continued)

PWM Line Regulation (VOUT = 1.5V) LDO Load Regulation (VOUT = 1.203V)
1.210
1.54
IL = 0A
IL = 5A
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)


IL = 10A
1.205
1.52

1.50 1.200

1.48 VIN = 8V
1.195
VIN = 12V
VIN = 15V
1.46 VIN = 20V
1.190
6 8 10 12 14 16 18 20 0 1 2 3 4 5
INPUT VOLTAGE (V) LOAD CURRENT (A)

Figure 14. PWM Line Regulation Figure 17. LDO Load Regulation

Load Line Regulation (VOUT = 1.203V) Master Clock Frequency


1.210 700
IL = 0A
IL = 2A
IL = 5A
600
OUTPUT VOLTAGE (V)

1.205
FREQUENCY (kHz)

500

1.200 400

300
1.195
200

1.190 100
8 10 12 14 16 18 20 0 100 200 300 400
INPUT VOLTAGE (V) RT (kΩ)

Figure 15. LDO Line Regulation Figure 18. RT vs. Frequency

PWM Load Regulation (VOUT = 1.50V) Efficiency vs. Input Voltage


1.510 100
VIN = 8V
VIN = 12V
VIN = 15V 80
OUTPUT VOLTAGE (V)

1.505 VIN = 20V


VIN = 8V
EFFICIENCY (%)

VIN = 12V
60 VIN = 15V
VIN = 20V
1.500
40

1.495
20

1.490 0
0 2 4 6 8 10 0 2 4 6 8 10
LOAD CURRENT (A) LOAD CURRENT (A)

Figure 16. PWM Load Regulation Figure 19. 1.5V PWM Efficiency

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 9
FAN5069 PWM and LDO Controller Combo
Block Diagram
CBOOT
Internal Vcc 5.6V Max.
Vcc BOOT
Shunt Reg Internal
10μA Boot Diode

RILIM Current Limit


ILIM Comparator
VIN

COMP PW M
Error PWM
Amplifier R Q
Comparator
FB
HDRV
S Adaptive
Vref Gate Drive
Vcc Circuit LO Vout
10μA OSC SW CO
SS
Current
Sense LDRV
VIN Summing Amplifier
RRAMP
Ramp
Generator
Σ
R(RAMP) Amplifier PGND
Enable
EN

Figure 20. Block Diagram

Detailed Operation Description Choose a resistor such that:


FAN5069 combines a high-efficiency, fixed-frequency ■ It is rated to handle the power dissipation.
PWM controller designed for single-phase synchronous ■ Current sunk within the controller is minimized to
buck Point-Of-Load converters with an integrated LDO prevent IC temperature rise.
controller to support GTL-type loads. This controller is
ideally suited to deliver low-voltage, high-current power
RVCC Selection (IC)
supplies needed in desktop computers, notebooks, The selection of RVCC is dependent on:
workstations, and servers. The controller comes with an ■ Variation of the 12V supply
integrated boot diode which helps reduce component
■ Gate charge of the top and bottom FETs (QFET)
cost and increase space savings. With this controller, the
■ Switching frequency (FSW)
input to the power supply can be varied from 3V to 24V
and the output voltage can be set to regulate at 0.8V to ■ Shunt regulator minimum current (1mA)
15V on the switcher output. The LDO output can be con- ■ Quiescent current of the IC (IQ)
figured to regulate between 0.8V to 3V and the input to
the LDO can be from 1.5V to 5V, respectively. An internal Calculate RVCC based on the minimum input voltage for
shunt regulator at the VCC pin facilitates the controller the VCC:
operation from either a 5V or 12V power source. Vin MIN – 5.6 (EQ. 1)
R VCC = -----------------------------------------------------------------------------------------
-
VCC Bias Supply –3
( I Q + 1 • 10 + Q FET • F SW • 1.2 )
FAN5069 can be configured to operate from 5V or 12V
For a typical example, where: VinMIN = 11.5V, IQ = 3mA,
for VCC. When 5V supply is used for VCC, no resistor is
QFET = 30nC, FSW = 300KHz, RVCC is calculated to be
required to be connected between the supply and the
398.65Ω.
VCC. When the 12V supply is used, a resistor RVCC is
connected between the 12V supply and the VCC, as PWM Section
shown in Figure 1. The internal shunt regulator at the
The FAN5069’s PWM controller combines the conven-
VCC pin is capable of sinking 150mA of current to
tional voltage mode control and current sensing through
ensure that the controller’s internal VCC is maintained at
lower MOSFET RDS_ON to generate the PWM signals.
5.6V maximum.
This method of current sensing is loss-less and cost
effective. For more accurate current sense requirements,
an optional external resistor can be connected with the
bottom MOSFET in series.

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 10
FAN5069 PWM and LDO Controller Combo
PWM Operation age varies. The RRAMP also has an effect on the current
limit, as can be seen in the RLIM equation (EQ. 5). The
Refer to Figure 20 for the PWM control mechanism. The
RRAMP value can be approximated using the following
FAN5069 uses the summing mode method of control to
equation:
generate the PWM pulses. The amplified output of the
current-sense amplifier is summed with an internally
V IN – 1.8
generated ramp and the combined signal is amplified R RAMP = --------------------------------------------- KΩ
–8
and compared with the output of the error amplifier to get 6.3 • 10 • Fosc (EQ. 4)
the pulse width to drive the high-side MOSFET. The
sensed current from the previous cycle is used to modu-
late the output of the summing block. The output of the where FOSC is in Hz. For example, for FOSC = 300kHz
summing block is also compared against the voltage and VIN = 12V, RRAMP ≈ 540KΩ.
threshold set by the RLIM resistor to limit the inductor cur-
Gate Drive Section
rent on a cycle-by-cycle basis. The controller facilitates
external compensation for enhanced flexibility. The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals
Initialization and provides necessary amplification, level shifting, and
When the PWM is disabled, the SW node is connected shoot-through protection. It also has functions that help
to GND through an internal 500Ω MOSFET to slowly dis- optimize the IC performance over a wide range of oper-
charge the output. As long as the PWM controller is ating conditions. Since the MOSFET switching time can
enabled, this internal MOSFET remains OFF. vary dramatically from device to device and with the
input voltage, the gate control logic provides adaptive
Soft-Start (PWM and LDO) dead time by monitoring the gate-to-source voltages of
When VCC exceeds the UVLO threshold and EN is high, both upper and lower MOSFETs. The lower MOSFET
the circuit releases SS and enables the PWM regulator. drive is not turned on until the gate-to-source voltage of
The capacitor connected to the SS pin and GND is the upper MOSFET has decreased to less than approxi-
charged by a 10µA internal current source, causing the mately 1V. Similarly, the upper MOSFET is not turned on
voltage on the capacitor to rise. When this voltage until the gate-to-source voltage of the lower MOSFET
exceeds 1.2V, all protection circuits are enabled. When has decreased to less than approximately 1V. This
this voltage exceeds 2.2V, the LDO output is enabled. allows a wide variety of upper and lower MOSFETs to be
The input to the error amplifier at the non-inverting pin is used without a concern for simultaneous conduction, or
clamped by the voltage on the SS pin until it crosses the shoot-through.
reference voltage. A low impedance path between the driver pin and the
The time it takes the PWM output to reach regulation MOSFET gate is recommended for the adaptive dead-
(TRise) is calculated using the following equation: time circuit to work properly. Any delay along this path
–2 reduces the delay generated by the adaptive dead-time
T RISE = 8 × 10 × C SS (CSS is in μf) (EQ. 2) circuit, thereby increasing the chances for shoot-through.
Oscillator Clock Frequency (PWM) Protection
The clock frequency on the oscillator is set using an In the FAN5069, the converter is protected against
external resistor, connected between R(T) pin and extreme overload, short-circuit, over-voltage, and under-
ground. The frequency follows the graph, as shown in voltage conditions. All of these conditions generate an
Figure 18. The minimum clock frequency is 200KHz, internal “fault latch” which shuts down the converter. For
which is when R(T) pin is left open. Select the value of all fault conditions both the high-side and the low-side
R(T) as shown in the equation below. This equation is drives are off except in the case of OVP where the low-
valid for all FOSC > 200kHz. side MOSFET is turned on until the voltage on the FB pin
9
goes below 0.4V. The fault latch can be reset either by
5 × 10 toggling the EN pin or recycling VCC to the chip.
R ( T ) = --------------------------------------------------
-Ω (EQ. 3)
( F OSC – 200 × 10 3 )
Over Current Limit (PWM)
where FOSC is in Hz. The PWM converter is protected against overloading
For example, for FOSC = 300kHz, R(T) = 50KΩ. through a cycle-by-cycle current limit set by selecting
RILIM resistor. An internal 10µA current source sets the
threshold voltage for the output of the summing amplifier.
RRAMP Selection and Feed-Forward Operation When the summing amplifier output exceeds this thresh-
old level, the current limit comparator trips and the PWM
The FAN5069 provides for input voltage feed-forward
starts skipping pulses. If the current limit tripping occurs
compensation through RRAMP. The value of RRAMP effec-
for 16 continuous clock cycles, a fault latch is set and the
tively changes the slope of the internal ramp, minimizing
controller shuts down the converter. This shutdown fea-
the variation of the PWM modulator gain when input volt-

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 11
FAN5069 PWM and LDO Controller Combo
ture is disabled during the start-up until the voltage on
EN Pin PWM/Restart
the SS capacitor crosses 1.2V.
Pull to GND OFF
To achieve current limit, the FAN5069 monitors the
inductor current during the OFF time by monitoring and VCC No restart after fault
holding the voltage across the lower MOSFET. The volt- Cap to GND Restart after TDELAY (Sec.) =
age across the lower MOSFET is sensed between the 0.85 x C where C is in μF
PGND and the SW pins.
The output of the summing amplifier is a function of the The fault latch can also be reset by recycling the VCC to
inductor current, RDS_ON of the bottom FET and the gain the controller.
of the current sense amplifier. With the RDS_ON method Under Voltage Protection (PWM)
of current sensing, the current limit can vary widely from
unit to unit. RDS_ON not only varies from unit to unit, but The PWM converter output is monitored constantly for
also has a typical junction temperature coefficient of under voltage at the FB pin. If the voltage on the FB pin
about 0.4%/°C (consult the MOSFET datasheet for stays lower than 75% of internal Vref for 16 clock cycles,
actual values). The set point of the actual current limit the fault latch is set and the converter shuts down. This
decreases in proportion to increase in MOSFET die tem- shutdown feature is disabled during startup until the volt-
perature. A factor of 1.6 in the current limit set point typi- age on the SS capacitor reaches 1.2V.
cally compensates for all MOSFET RDS_ON variations, Over Voltage Protection (PWM)
assuming the MOSFET's heat sinking keeps its operat-
ing die temperature below 125°C. The PWM converter output voltage is monitored con-
stantly at the FB pin for over voltage. If the voltage on the
For more accurate current limit setting, use resistor FB pin stays higher than 115% of internal VREF for two
sensing. In a resistor sensing scheme, an appropriate clock cycles, the controller turns OFF the upper MOS-
current sense resistor is connected between the source FET and turns ON the lower MOSFET. This crowbar
terminal of the bottom MOSFET and PGND. action stops when the voltage on the FB pin reaches
Set the current limit by choosing RILIM as follows: 0.4V to prevent the output voltage from becoming nega-
tive. This over-voltage protection (OVP) feature is active
3
as soon as the voltage on the EN pin becomes high.
K1 • I MAX • R DSON • 10 ⎛ Vout • 33.32 • 10 ⎛
11
- + ⎜ ⎛ 1 – ---------⎞ • ---------------------------------------------------- ⎜
1.8
R ILIM = 128 + ----------------------------------------------------------------- Turning ON the low-side MOSFETs on an OVP condition
1.43 ⎝ ⎝ Vin ⎠ F SW • R RAMP ⎝
pulls down the output, resulting in a reverse current,
(EQ. 5) which starts to build up in the inductor. If the output over-
where RILIM is in KΩ. voltage is due to failure of the high-side MOSFET, this
crowbar action pulls down the input supply or blows its
IMAX is the maximum load current.
fuse, protecting the system, which is very critical.
K1 is a constant to accommodate for the variation of
During soft-start, if the output overshoots beyond 115%
MOSFET RDS(ON) (typically 1.6).
of VREF, the output voltage is brought down by the low-
With K1 = 1.6, IMAX = 20A, RDS(ON) = 7mΩ, VIN = 24V, side MOSFET until the voltage on the FB pin goes below
VOUT = 1.5V, FSW = 300 KHz, RRAMP = 400 KΩ, RILIM 0.4V. The fault latch is NOT set until the voltage on the
calculates to be 323.17KΩ. SS pin reaches 1.2V. Once the fault latch is set, the con-
verter shuts down.
Auto Restart (PWM) 115% Vref
ILIM
UV
OV S Fault
The FAN5069 supports two modes of response when the Q Latch
Delay V SS >1.2V
internal fault latch is set. The user can configure it to FB 2 Clks
EN R
keep the power supply latched in the OFF state OR in S
the Auto Restart mode. When the EN pin is tied to VCC, Q
0.4V R LS Drive
the power supply is latched OFF. When the EN pin is ter-
minated with a 100nF to GND, the power supply is in
Auto Restart mode. The table below describes the rela- Figure 21. Over-Voltage Protection
tionship between PWM restart and setting on EN pin. Do
not leave the EN pin open without any capacitor. Thermal Fault Protection
The FAN5069 features thermal protection where the IC
temperature is monitored. When the IC junction temper-
ature exceeds +160°C, the controller shuts down and
when the junction temperature gets down to +125°C, the
converter restarts.

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 12
FAN5069 PWM and LDO Controller Combo
LDO Section operate at the boundary of continuous and discontinuous
conduction modes.
The LDO controller is designed to provide ultra low volt-
ages, as low as 0.8V for GTL-type loads. The regulating Setting the Output Voltage (PWM)
loop employs a very fast response feedback loop and
The internal reference for the PWM controller is at 0.8V.
small capacitors can be used to keep track of the chang-
The output voltage of the PWM regulator can be set in
ing output voltage during transients. For stable opera-
the range of 0.8V to 90% of its power input by an exter-
tion, the minimum capacitance on the output needs to be
nal resistor divider. The output is divided down by an
100µF and the typical ESR needs to be around 100mΩ.
external voltage divider to the FB pin (for example, R1
The maximum voltage at the gate drive for the MOSFET and RBIAS as in Figure 24). The output voltage is given
can reach close to 0.5V below the VCC of the controller. by the following equation:
For example, for a 1.2V output, the minimum enhance-
V OUT = 0.8V × ⎛⎝ 1 + ----------------⎞⎠
ment voltage required with 4.75V on VCC is 3.05V R1 (EQ. 6)
(4.75V-0.5V-1.2V = 3.05V). The drop-out voltage for the R BIAS
LDO is dependent on the load current and the MOSFET
To minimize noise pickup on this node, keep the resistor
chosen. It is recommended to use low enhancement
to GND (RBIAS) below 10KΩ.
voltage MOSFETs for the LDO. In applications where
LDO is not needed, pull up the FBLDO pin (Pin #1) Inductor Selection (PWM)
higher than 1V to disable the LDO.
When the ripple current, switching frequency of the con-
The soft-start on the LDO output (ramp) is controlled by verter, and the input-output voltages are established,
the capacitor on the SS pin to GND. The LDO output is select the inductor using the following equation:
enabled only when the voltage on the SS pin reaches
V OUT 2
2.2V. Refer to Figure 9 for start-up waveform. ⎛V – -------------- ⎞
⎝ OUT V IN ⎠
L MIN = --------------------------------------------
Design Section I Ripple × F SW
(EQ. 7)
General Design Guidelines where IRipple is the ripple current.
Establishing the input voltage range and maximum cur- This number typically varies between 20% to 50% of the
rent loading on the converter before choosing the switch- maximum steady-state load on the converter.
ing frequency and the inductor ripple current is highly
recommended. There are design trade-offs in choosing When selecting an inductor from the vendors, select the
an optimum switching frequency and the ripple current. inductance value which is close to the value calculated at
the rated current (including half the ripple current).
The input voltage range should accommodate the worst-
case input voltage with which the converter may ever Input Capacitor Selection (PWM)
operate. This voltage needs to account for the cable drop The input capacitors must have an adequate RMS cur-
encountered from the source to the converter. Typically, rent rating to withstand the temperature rise caused by
the converter efficiency tends to be higher at lower input the internal power dissipation. The combined RMS cur-
voltage conditions. rent rating for the input capacitor should be greater than
When selecting maximum loading conditions, consider the value calculated using the following equation:
the transient and steady-state (continuous) loading sep-
arately. The transient loading affects the selection of the ⎛ V OUT V OUT 2⎞
I INPUT ( RMS ) = I LOAD ( MAX ) × ⎜ -------------- – ⎛ --------------⎞ ⎟ (EQ. 8)
inductor and the output capacitors. Steady state loading ⎝ V IN ⎝ V IN ⎠ ⎠
affects the selection of MOSFETs, input capacitors, and
other critical heat-generating components.
Common capacitor types used for such application
The selection of switching frequency is challenging. include aluminum, ceramic, POS CAP, and OSCON.
While higher switching frequency results in smaller com-
ponents, it also results in lower efficiency. Ideal selection Output Capacitor Selection (PWM)
of switching frequency takes into account the maximum The output capacitors chosen must have low enough
operating voltage. The MOSFET switching losses are ESR to meet the output ripple and load transient require-
directly proportional to FSW and the square function of ments. The ESR of the output capacitor should be lower
the input voltage. than both of the values calculated below to satisfy both
When selecting the inductor, consider the minimum and the transient loading and steady-state ripple conditions
maximum load conditions. Lower inductor values pro- as given by the following equation:
duce better transient response, but result in higher ripple V STEP V Ripple (EQ. 9)
and lower efficiency due to high RMS currents. Optimum ESR ≤ ---------------------------------- and ESR ≤ -------------------
ΔI LOAD ( MAX ) I Ripple
minimum inductance value enables the converter to

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 13
FAN5069 PWM and LDO Controller Combo
In the case of aluminum and polymer based capacitors,
the output capacitance is typically higher than normally VIN
required to meet these requirements. While selecting the 5V
ceramic capacitors for the output; although lower ESR CGD
can be achieved easily, higher capacitance values are
RD RGATE
required to meet the VOUT(MIN) restrictions during a load HDRV
G
transient. From the stability point of view, the zero
caused by the ESR of the output capacitor plays an CGS
important role in the stability of the converter. SW

Output Capacitor Selection (LDO)


Figure 23. Drive Equivalent Circuit
For stable operation, the minimum capacitance of 100µF
with ESR around 100mΩ is recommended. For other val- The upper graph in Figure 22 represents Drain-to-
ues, contact the factory. Source Voltage (VDS) and Drain Current (ID) waveforms.
The lower graph details Gate-to-Source Voltage (VGS)
Power MOSFET Selection (PWM) vs. time with a constant current charging the gate. The x-
The FAN5069 is capable of driving N-Channel MOSFETs axis is representative of Gate Charge (QG). CISS = CGD
as circuit switch elements. For better performance, + CGS and it controls t1, t2, and t4 timing. CGD receives
MOSFET selection must address these key parameters: the current from the gate driver during t3 (as VDS is fall-
ing). Obtain the gate charge (QG) parameters shown on
■ The maximum Drain-to-Source Voltage (VDS) should the lower graph from the MOSFET datasheets.
be at least 25% higher than worst-case input voltage.
Assuming switching losses are about the same for both
■ The MOSFETs should have low QG, QGD, and QGS.
the rising edge and falling edge, Q1's switching losses
■ The RDS_ON of the MOSFETs should be as low as possible.
occur during the shaded time when the MOSFET has
In typical applications for a buck converter, the duty voltage across it and current through it.
cycles are lower than 20%. To optimize the selection of
MOSFETs for both the high-side and low-side, follow dif- Losses are given by (EQ. 10), (EQ. 11), and (EQ. 12):
ferent selection criteria. Select the high-side MOSFET to PUPPER = PSW + PCOND (EQ. 10)
minimize the switching losses and the low-side MOSFET
to minimize the conduction losses due to the channel V DS × I L (EQ. 11)
P SW = ⎛ --------------------- × 2 × t s⎞ F SW
and the body diode losses. Note that the gate drive ⎝ 2 ⎠
losses also affect the temperature rise on the controller. V OUT
P COND = ⎛ --------------⎞ × I OUT 2 × R DS ( ON ) (EQ. 12)
For loss calculation, refer to Fairchild's Application Note ⎝ V IN ⎠
AN-6005 and the associated spreadsheet.
where PUPPER is the upper MOSFET's total losses and
High-Side Losses PSW and PCOND are the switching and conduction losses
for a given MOSFET. RDS(ON) is at the maximum junction
Losses in the MOSFET can be understood by following
temperature (TJ) and tS is the switching period (rise or
the switching interval of the MOSFET in Figure 22. MOS-
fall time) and equals t2+t3 (Figure 22.).
FET gate drive equivalent circuit is shown in Figure 23.
CISS CGD CISS
The driver's impedance and CISS determine t2 while t3's
VDS period is controlled by the driver's impedance and QGD.
Since most of tS occurs when VGS = VSP, assume a con-
stant current for the driver to simplify the calculation of tS
using the following equation:
Q G ( SW ) Q G ( SW )
t s = -------------------- ≈ ---------------------------------------------- (EQ. 13)
I Driver ⎛ V CC – V SP ⎞
----------------------------------------
ID ⎝ R Driver + R Gate⎠

Most MOSFET vendors specify QGD and QGS. QG(SW)


can be determined as:
QGS QGD
4.5V
QG(SW) = QGD + QGS – QTH where QTH is the gate
charge required to reach the MOSFET threshold (VTH).
VSP
VTH Note that for the high-side MOSFET, VDS equals VIN,
QG(SW)
which can be as high as 20V in a typical portable appli-
VGS
cation. Include the power delivered to the MOSFET's
t1 t2 t3 t4 t5
(PGATE) in calculating the power dissipation required for
the FAN5069.
Figure 22. Switching Losses and QG

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 14
FAN5069 PWM and LDO Controller Combo
PGATE is determined by the following equation: R-C components for the snubber are selected as follows:
(EQ. 14)
P Gate = Q G × V CC × F SW a) Measure the SW node ringing frequency (Fring) with a
low capacitance scope probe.
where QG is the total gate charge to reach VCC.
b) Connect a capacitor (CSNUB) from SW node to GND
Low-Side Losses so that it reduces this ringing by half.
Q2 switches on or off with its parallel schottky diode c) Place a resistor (RSNUB) in series with this capacitor.
simultaneously conducting, so the VDS ≈ 0.5V. Since RSNUB is calculated using the following equation:
PSW is proportional to VDS, Q2's switching losses are
2
negligible and Q2 is selected based on RDS(ON) alone. R SNUB = ----------------------------------------------- (EQ. 17)
π × F ring × C SNUB
Conduction losses for Q2 are given by the equation:
2
P COND = ( 1 – D ) × I OUT × R DS ( ON ) (EQ. 15) d) Calculate the power dissipated in the snubber resistor
where RDS(ON) is the RDS(ON) of the MOSFET at the as shown in the following equation:
highest operating junction temperature and D=VOUT/VIN 2
P R ( SNUB ) = C SNUB × V IN ( MAX ) × F SW (EQ. 18)
is the minimum duty cycle for the converter.
where, VIN(MAX) is the maximum input voltage and FSW
Since DMIN < 20% for portable computers, (1-D) ≈ 1 pro- is the converter switching frequency.
duces a conservative result, simplifying the calculation.
The snubber resistor chosen should be de-rated to han-
The maximum power dissipation (PD(MAX)) is a function dle the worst-case power dissipation. Do not use wire-
of the maximum allowable die temperature of the low- wound resistors for RSNUB.
side MOSFET, the θJA, and the maximum allowable
ambient temperature rise. PD(MAX) is calculated using Loop Compensation
the following equation: Typically, the closed loop crossover frequency (Fcross),
T J ( MAX ) – T A ( MAX ) where the overall gain is unity, should be selected to
P D ( MAX ) = ------------------------------------------------- achieve optimal transient and steady-state response to
θ JA (EQ. 16)
disturbances in line and load conditions. It is recom-
θJA depends primarily on the amount of PCB area mended to keep Fcross below fifth of the switching fre-
devoted to heat sinking. quency of the converter. Higher phase margin tends to
Selection of MOSFET Snubber Circuit have a more stable system with more sluggish response
to load transients. Optimum phase margin is about 60°, a
The Switch node (SW) ringing is caused by fast switch- good compromise between steady state and transient
ing transitions due to the energy stored in the parasitic responses. A typical design should address variations
elements. This ringing on the SW node couples to other over a wide range of load conditions and over a large
circuits around the converter if they are not handled sample of devices.
properly. To dampen this ringing, an R-C snubber is con-
nected across the SW node and the source of the low-
side MOSFET.

VIN

Current
Sense
Amplifier Q1
VIN
RRAMP
Ramp
Generator L
PWM RDC VOUT
Summing
&
Σ DRIVER C
RL
Amplifier Q2
RES

C2
C1 R2
C3 R3
RBIAS
R1
Reference

Figure 24. Closed-Loop System with Type-3 Network

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 15
FAN5069 PWM and LDO Controller Combo
FAN5069 has a high gain error amplifier around which For further information about Type-2 compensation
the loop is closed. Figure 24 shows a Type-3 compensa- networks, refer to:
tion network. For Type-2 compensation, R3 and C3 are
■ Venable, H. Dean, "The K factor: A new mathematical
not used. Since the FAN5069 architecture employs sum-
tool for stability analysis and synthesis,” Proceedings
ming current mode, Type-2 compensation can be used
of Powercon, March 1983.
for most applications.
Note: For critical applications requiring wide loop
bandwidth using very low ESR output capacitors,
use Type-3 compensation.

Type 3 Feedback Component Calculations


Use the following steps to calculate feedback components:
Notation:
C 0 = Net Output Filter capacitance
G p ( s ) = Net Gain of Plant = control-to-output transfer function
L = Inductor Value
R DSON = ON-state Drain-to Source Resistance of Low-side MOSFET
R es = Net ESR of the Output Filter Capacitors
R L = Load Resistance

T s = Switching Period

V IN = Input Voltage

F SW = Switching Frequency

Equations:
Effective current sense resistance = R i = 7 × R DSON (EQ. 19)

RL
Current modulator DC gain = M i = ------- (EQ. 20)
Ri

( V IN – 1.8 ) × T s
Effective ramp amplitude = V m = 3.33 × 10 10 × ----------------------------------------
-
R ramp
(EQ. 21)
V IN
Voltage modulator DC gain = M v = --------- (EQ. 22)
Vm

Mv × Mi
Plant DC gain = M o = M v || M i = -------------------- (EQ. 23)
Mv + Mi

π
Sampling gain natural frequency = ω n = ------ (EQ. 24)
Ts

–2
Sampling gain quality factor (damping) = Q z = ------ (EQ. 25)
π

MO Mv × Ri
Effective inductance = L e = -------- × ⎛ L + --------------------⎞ (EQ. 26)
Mv ⎝ ω n × Q z⎠

Mv × Ri × RL
R p = --------------------------------- = ( M v × R i ) || R L (EQ. 27)
Mv × Ri + RL

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 16
FAN5069 PWM and LDO Controller Combo
Poles and Zeros of Plant Transfer Function:
1
Plant zero frequency = f z = ------------------------------------------ (EQ. 28)
2 × π × C o × R es

1
Plant 1st pole frequency = f p1 = ----------------------------------------------------------- (EQ. 29)
Le
2 × π × ⎛⎝ C o × R p + -------⎞⎠
RL

Rp
Plant 2nd pole frequency = f p2 = ------------ × ⎛ -------------------- + -------⎞
1 1
(EQ. 30)
2×π ⎝ Co × RL Le ⎠
2
ωn × Le
Plant 3rd pole frequency = f p3 = -------------------------- (EQ. 31)
2 × π × Rp

Plant gain (magnitude) response:


f 2
1 + ⎛ ----⎞
⎝ f z⎠
G p (f) = 20 × log M 0 + 10 × log ---------------------------------------------------------------------------------------------------------
- (EQ. 32)
f 2 f 2 f 2
1 + ⎛⎝ -------⎞⎠ × 1 + ⎛⎝ -------⎞⎠ × 1 + ⎛⎝ -------⎞⎠
f p1 f p2 f p3

Plant phase response:

∠G P (f) = tan ⎛ ----⎞ – tan ⎛ -------⎞ – tan ⎛ -------⎞ – – tan ⎛ -------⎞


–1 f –1 f –1 f –1 f
(EQ. 33)
⎝ f z⎠ ⎝ f p1⎠ ⎝ f p2⎠ ⎝ f p3⎠

Choose R1, RBIAS to set the output voltage using EQ.6. Choose the zero crossover frequency Fcross of the overall
loop. Typically Fcross should be less than fifth of Fsw. Choose the desired phase margin; typically between 60° to 90°.
Calculate plant gain at Fcross using EQ.34 by substituting Fcross in place of f. The gain that the amplifier needs to pro-
vide to get the required crossover is given by:
1
G AMP = -------------------------------- (EQ. 34)
G p (F cross )

The phase boost required is calculated as given in (EQ. 35)


Phase Boost = M – ∠G P (F cross ) – 90° (EQ. 35)
where M is the desired phase margin in degrees.
The feedback component values are calculated as given in equations below:
2
⎧ ⎫
K = ⎨ Tan ⎛ ----------------⎞ + 45 ⎬
Boost
⎝ 4 ⎠
⎩ ⎭ (EQ. 36)

1
C2 = ------------------------------------------------------------------------
2 × π × F cross × G AMP × R1
(EQ. 37)
C1 = C2 × ( K – 1 ) (EQ. 38)
1
C3 = ---------------------------------------------------------------- (EQ. 39)
2 × π × F cross × K × R3

K
R2 = -------------------------------------------------- (EQ. 40)
2 × π × F cross × C1
R1
R3 = ------------------ (EQ. 41)
(K – 1)

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 17
FAN5069 PWM and LDO Controller Combo
Design Tools Layout Considerations
Fairchild application note AN-6010 provides a PSPICE The switching power converter layout needs careful
model and spreadsheet calculator for the PWM regula- attention and is critical to achieving low losses and clean
tor, simplifying external component selections and verify- and stable operation. Below are specific recommenda-
ing loop stability. The topics covered provide an tions for good board layout:
understanding of the calculations in the spreadsheet.
■ Keep the high-current traces and load connections as
The spreadsheet calculator, which is part of AN-6010, short as possible.
can be used to calculate all external component values ■ Use thick copper boards whenever possible to
for designing around FAN5069. The spreadsheet pro- achieve higher efficiency.
vides optimized compensation components and gener- ■ Keep the loop area between the SW node, low-side
ates a Bode Plot to ensure loop stability. MOSFET, inductor, and the output capacitor as small
Based on the input values entered, AN-6010’s PSPICE as possible.
model can be used to simulate Bode Plots (for loop sta- ■ Route high dV/dt signals, such as SW node, away
bility) as well as transient analysis to help customize the from the error amplifier input/output pins. Keep com-
design for a wide range of applications. ponents connected to these pins close to the pins.
■ Place ceramic de-coupling capacitors very close to the
Use Fairchild Application Note AN-6005 for prediction of
the losses and die temperatures for the power semicon- VCC pin.
ductors used in the circuit. ■ All input signals are referenced with respect to AGND
pin. Dedicate one layer of the PCB for a GND plane.
AN-6010 and AN-6005 can be downloaded from Use at least four layers for the PCB.
www.fairchildsemi.com/apnotes/.
■ Minimize GND loops in the layout to avoid EMI-related
issues.
■ Use wide traces for the lower gate drive to keep the
drive impedances low.
■ Connect PGND directly to the lower MOSFET source
pin.
■ Use wide land areas with appropriate thermal vias to
effectively remove heat from the MOSFETs.
■ Use snubber circuits to minimize high-frequency ring-
ing at the SW nodes.
■ Place the output capacitor for the LDO close to the
source of the LDO MOSFET.

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 18
FAN5069 PWM and LDO Controller Combo
Application Board Schematic
VIN = 3 to 24V; VOUT =1.5V at 20A.
+5V or +12V
Vcc J1

R9
220

U1
PWM OUT C7
3-24V
0.22µF
J2
15 14 R6 453K
VCC R(RAMP) VIN
C6 C10 + C11 +
FDD6296
Q1
FDD6530A Q2 0.1µF 820µF 820µF J3
LDO 16 10
GLDO HDRV GND

J7 R8
LDO_Out 1 11 PWM OUT
FBLDO BOOT
C17 5K
+ C8
C4
R7 10K 0.22µF
0.1µF L1 1.8µH J4
R4 2 9
J6 560µF R(T) SW SW_Out
GND 50K FDD6606 FDD6606
R11 C12 C13 C14
2.2 + + + C15
Q3 Q4
R5 3 13
IL IM LDRV
560µF 560µF 560µF 0.1µF
243K
TP1 C16
C5 3.3nF
J5
4 12
SS PGND GND
0.1µF C1
1500pF C3
TP2 7 5 R2 R3
EN COMP
12.7k
825
3300pF
C9 0.01µF C2
220pF R1
8 6
AGND FB
5.11K

FAN5069 R10
5.83K

Figure 25. Application Board Schematic

Bill of Materials
Part Description Quantity Designator Vendor Vendor Part #
Capacitor, 1500pF, 20%, 25V, 0603,X7R 1 C1 Panasonic PCC1774CT-ND
Capacitor, 220pF, 5%, 50V, 0603,NPO 1 C2 Panasonic PCC221ACVCT-ND
Capacitor, 3300pF, 10%, 50V, 0603,X7R 1 C3 Panasonic PCC1778CT-ND
Capacitor, 0.1µF, 10%, 25V, 0603,X7R 4 C4, C5, C6, C15 Panasonic PCC2277CT-ND
Capacitor, 0.22µF, 20%, 25V, 0603,X7R 2 C7, C8 Panasonic PCC1767CT-ND
Capacitor, 0.01µF, 10%, 50V, 0603,X7R 1 C9 Panasonic PCC1784CT-ND
Capacitor, 820µF, 20%, 10X20, 25V,20mOhm,1.96A 2 C10, C11 Nippon-Chemicon KZH25VB820MHJ20
Capacitor, 820µF, 20%, 8X8, 2.5V,7mOhm,6.1A 1 C17 Nippon-Chemicon PSC2.5VB820MH08
Capacitor, 560µF, 20%, 8X11.5, 4V,7mOhm,5.58A 3 C12, C13, C14 Nippon-Chemicon PSA4VB560MH11
Capacitor, 3300pF, 10%, 50V, 0603,X7R 1 C16 Panasonic PCC332BNCT-ND
Connector Header 0.100 Vertical, Tin - 2 Pin 1 J1 Molex WM6436-ND
Terminal Quickfit Male .052"Dia.187" Tab 6 J2 - J7 Keystone 1212K-ND
Inductor, 1.8µH, 20%, 26Amps Max, 3.24mOhm 1 L1 Inter-Technical SC5018-1R8M
MOSFET N-CH, 32 mΩ, 20V, 21A, D-PAK, FSID: FDD6530A 1 Q1 Fairchild Semiconductor FDD6530A
MOSFET N-CH, 8.8 mΩ, 30V, 50A, D-PAK, FSID: FDD6296 1 Q2 Fairchild Semiconductor FDD6296
MOSFET N-CH, 6 mΩ, 30V, 75A, D-PAK, FSID: FDD6606 2 Q3, Q4 Fairchild Semiconductor FDD6606
Resistor, 5.11K, 1%, 1/16W 1 R1 Panasonic P5.11KHCT-ND
Resistor, 12.7K, 1%, 1/16W 1 R2 Panasonic P12.7KHCT-ND
Resistor, 825Ω, 1%, 1/16W 1 R3 Panasonic P825HCT-ND
Resistor, 49.9K, 1%, 1/16W 1 R4 Panasonic P49.9KHCT-ND
Resistor, 243K, 1%, 1/16W 1 R5 Panasonic P243KHCT-ND
Resistor,453K, 1%, 1/16W 1 R6 Panasonic P453KHCT-ND
Resistor,10K, 1%, 1/16W 1 R7 Panasonic P10.0KHCT-ND
Resistor, 4.99K, 1%, 1/16W 1 R8 Panasonic P4.99KHCT-ND
Resistor, 220Ω, 1%, 1/4W 1 R9 Panasonic P200FCT-ND
Resistor, 5.90K, 1%, 1/16W 1 R10 Panasonic P5.90KHCT-ND
Resistor, 2.2Ω, 1%, 1/4W 1 R11 Panasonic P2.2ECT-ND
Connector Header 0.100 Vertical, Tin - 1 Pin 3 TP1,TP2, Vcc Molex WM6436-ND
IC, System Regulator, TSSOP16, FSID: FAN5069 1 U1 Fairchild Semiconductor FAIRCHILD

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 19
FAN5069 PWM and LDO Controller Combo
Typical Application Board Layout

Figure 26. Assembly Diagram Figure 29. Mid Layer 2

Figure 27. Top Layer Figure 30. Bottom Layer

Figure 28. Mid Layer 1

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com


FAN5069 Rev. 1.1.5 20
5.10
4.90 A
4.55
16 9 B

6.4 4.50 5.90 4.45 7.35


4.30

3.2 0.65

1.45
1 PIN #1 8 0.2 C B A
0.11 IDENT ALL LEAD TIPS 5.00
TOP VIEW
LAND PATTERN RECOMMENDATION
1.10 MAX 0.15 A
0.05 0.20
0.09
0.90 ALL LEAD TIPS
0.1 C
0.30
C 0.19 SIDE VIEW
0.65 0.13 M A BS CS
NOTES:
FRONT VIEW
12° A. CONFORMS TO JEDEC REGISTRATION
MO-153, VARIATION AB
TOP & BOTTOM B. ALL DIMENSIONS ARE IN MILLIMETERS
GAGE C. DIMENSIONS ARE EXCLUSIVE OF
PLANE BURRS, MOLD FLASH, AND TIE BAR
0.25 EXTRUSIONS
8° D. DIMENSIONS AND TOLERANCES
0° PER ASME Y14.5M, 2009
E. LAND PATTERN RECOMMENDATION
PER IPC7351 - ID# TSOP65P640X110-16N
0.70 F. DRAWING FILENAME: MKT-MTC16rev5
0.50 SEATING PLANE
DETAIL A
SCALE 3:1
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