Quartus

Laboratory Exercise Manual

for
Introduction to Verilog
Exercises Introduction to Verilog

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Copyright © 2001 Altera Corporation
Introduction to Verilog Exercises

Introduction to Verilog Lab Overview

Objective: Build a sequential 8 X 8 multiplier

The objective of the following exercises is to build an 8 X 8 multiplier. The input to the multiplier consists
of two 8-bit multiplicands (a[7..0], b[7..0]) and the output from the multiplier is a 16-bit result
(result[15..0]). Additional outputs are a done bit (DONE_FLAG) and seven signals to drive a seven
segment display, (A,B,C,D,E,F,G).

There are several methods of implementing a multiplier, the method chosen for the Verilog labs is the
sequential multiplier method. This 8 X 8 multiplier requires four clock cycles to perform the full
multiplication. During each cycle, a pair of 4-bit portion of the multiplicands are multiplied in a 4 X 4
multiplier. The multiplication result of these 4 bit slices are then accumulated. At the end of the four
cycles, the full composed 16-bit result can be read at the output.

The following equations illustrate the mathematical principles supporting this implementation:

result[15..0] = a[7..0] * b[7..0]

= ( ( a[7..4] * 2 ^ 4) + a[3..0] * 2 ^ 0 )
* ( ( b[7..4] * 2 ^ 4) + b[3..0] * 2 ^ 0 )

= ( ( a[7..4] * b[7..4] ) * 2 ^ 8 )
+ ( ( a[7..4] * b[3..0] ) * 2 ^ 4 )
+ ( ( a[3..0] * b[7..4] ) * 2 ^ 4 )
+ ( ( a[3..0] * b[3..0] ) * 2 ^ 0 )

Figure 1 in the following page illustrates the top level block diagram of the 8 X 8 multiplier.

The labs are structured as a bottom-up design approach. In each of the first four exercises, you will use
targeted features of the Verilog language to build the individual components of the 8 X 8 multiplier. Then,
in exercise five you will put everything together in a top level design. You will then compile and simulate
to verify the completeness of your design.

Important: Please use lower case alphabet letters for your source codes.

Good luck and have fun going through the exercises!

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Exercises Introduction to Verilog

Figure 1 - 8 X 8 multiplier top level design block diagram

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Introduction to Verilog Exercises

Exercise 1

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Exercises Introduction to Verilog

Exercise 1

Objective: Two-part exercise:

Part A - Build a 16-bit adder

Part B - Build a 4x4 multiplier

Part A

Figure 1-1.

Step 1 (Ask the instructor for the <pathname>)

1. <pathname> is________________________________

2. Use this <pathname> pathname for this Lab

Step 2 (Create new project and open Verilog text editor file)

Create a project by using the New Project Wizard. To create a project using the New Project Wizard, please
follow the following steps:

1. Select the New Project Wizard from the File menu. The first time you open the New Project Wizard,
it shows the introduction page; you can click Next to proceed to the first page of the wizard.

2. Type the directory name or select the directory with Browse . The directory name has been
provided by the instructor in step1.

3. Type a name for the project in the project name box. For this lab, type adder.

4. Type adder as the name of the top-level design entity of the project in the top-level design entry box.

5. Click Next. The second page of the New Project Wizard appears.

6. At this point, there is no file to add because we will create the adder source file.

7. Click Next. The summary page appears. The summary page gives information about your project.
8. Click Finish. You have just finished the project creation. You should see the top-level entity (adder) in
the Compilation Hierarchies tab of the Project Navigator window.

9. From the File menu, select New or click on . The New file dialog box will appear; select Verilog
HDL File then click OK.
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Introduction to Verilog Exercises

10. The Verilog text editor will appear.

11. Write your source code.
Remember to use the same input and output port names as shown in Figure 1-1.

12. Save new Verilog text file to <pathname>\verilog\lab1a\adder.v.

Go to File menu and Choose Save.

Step 3 (Save and check design)

Save and check adder.v.

‘Save and check’ checks for syntax and semantic errors. Click OK when the analysis is complete.

Step 4 (Do a functional compilation)

1. From the Processing menu select Compiler Settings. In the dialog box select the Mode tab and Click on
Netlist extraction and synthesis only, including estimated timing. Leave other settings as defaults.

Figure 1-2.

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Exercises Introduction to Verilog

2. Click OK to close the Compiler Settings Dialog Box.

3. From the Processing menu, Select Start Compilation or Click on . Click OK when synthesis is

complete.

Step 5 (Do a functional simulation)

1. The stimulus file has been created for you to verify the functionality of your design. If you are
interested in learning how to create your own stimulus file, please go to the Appendix of this manual.

2. From the Processing menu, Select Simulate Mode or Click on from toolbar.
3. From the Processing menu, Select Simulator Settings. Once the Simulator Settings Dialog Box has
appeared, Click on the Time/Vectors tab to browse to the vector stimuli file (Adder.vwf which is given
to you.).

To browse to the adder.vwf file Click on . <pathname>\verilog\lab1a\adder.vwf

Figure 1-3.

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Introduction to Verilog Exercises

4. Click on Apply.
5. In the Simulator Settings Dialog Box, click on the Mode tab. Change the simulation mode to be
Functional. Click OK to close the Simulator Settings Dialog Box.

Figure 1-4.

6. From the Processing menu Select Run Simulation or Click on . Click OK when the simulation is
complete.
7. Check to see if you get the same results as shown in Figure 1-5.

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Exercises Introduction to Verilog

Figure 1-5.

Step 6 (Close the simulation waveform)

1. Close the Simulation Waveform window.
2. Switch back to the Compile Mode

Step 7 (Close the project)

1. From the File menu select the Close Project option to close the project.

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Introduction to Verilog Exercises

Part B

Figure 1-6.

Step 1 (Ask the instructor for the <pathname>)

1. <pathname> is________________________________

2. Use this <pathname> pathname for this Lab

Step 2 (Create new project and open Verilog text editor file)

Create a project by using the New Project Wizard. To create a project using the New Project Wizard, please
follow the following steps:

1. Select the New Project Wizard from the File menu. The first time you open the New Project Wizard,
it shows the introduction page; you can click Next to proceed to the first page of the wizard.

2. Type the directory name or select the directory with Browse . The directory name has been
provided by the instructor in step1.

3. Type a name for the project in the project name box. For this lab, type mult4x4.
4. Type mult4x4 as the name of the top-level design entity of the project in the top-level design entry
box.

5. Click Next. The second page of the New Project Wizard appears.

6. At this point, there is no file to add because we will create the multiplier source file.
7. Click Next. The summary page appears. The summary page gives information about your project.

8. Click Finish. You have just finished the project creation. You should see the top-level entity (mult4x4)
in the Compilation Hierarchies tab of the Project Navigator window.

9. From the File menu, select New or click on . The New file dialog box will appear; select Verilog

HDL File then click OK.

10. The Verilog text editor will appear.
11. Write your source code.
Remember to use the same input and output port names as shown in Figure 1-6

12. Save new Verilog text file to <pathname>\verilog\lab1b\mult4x4.v.

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Go to File menu and Choose Save.

Step 3 (Save and check design)

Save and check mult4x4.v.

‘Save and check’ checks for syntax and semantic errors. Click OK when the analysis is complete.

Step 4 (Do a functional compilation)

1. From the Processing menu select Compiler Settings. In the dialog box select the Mode tab and Click on
Netlist extraction and synthesis only, including estimated timing. Leave other settings as defaults.

Figure 1-7.

2. Click OK to close the Compiler Settings Dialog Box.

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Introduction to Verilog Exercises

3. From the Processing menu, Select Start Compilation or Click on . Click OK when synthesis is

complete.

Step 5 (Do a functional simulation)

1. The stimulus file has been created for you to verify the functionality of your design. If you are
interested in learning how to create your own stimulus file, please go to the Appendix of this manual.

2. From the Processing menu, Select Simulate Mode or Click on from toolbar.

3. From the Processing menu, Select Simulator Settings. Once the Simulator Settings Dialog Box has
appeared, Click on the Time/Vectors tab to browse to the vector stimuli file (mult4x4.vwf which is
given to you.).

To browse to the adder.vwf file Click on . <pathname>\verilog\lab1a\mult4x4.vwf

Figure 1-8.

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Exercises Introduction to Verilog

4. Click on Apply.
5. In the Simulator Settings Dialog Box, click on the Mode tab. Change the simulation mode to be
Functional. Click OK to close the Simulator Settings Dialog Box.

Figure 1-9.

6. From the Processing menu Select Run Simulation or Click on . Click OK when the simulation is
complete.
7. Check to see if you get the same results as shown in Figure 1-10.

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Introduction to Verilog Exercises

Figure 1-10.

Step 6 (Close the simulation waveform)

1. Close the Simulation Waveform window.
2. Switch back to the Compile Mode

Step 7 (Close the project)

1. From the File menu select the Close Project option to close the project.

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Exercises Introduction to Verilog

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Introduction to Verilog Exercises

Exercise 2

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Exercises Introduction to Verilog

Exercise 2

Objective: Two-part exercise:

Part A - Build a 4-input 2:1 multiplexer

Part B – Build an 8-bit to 16-bit shifter

PART A
Objective: Build a four-input 2:1 multiplexer using IF-THEN statement.

The input to the multiplexer consists of two 4-bit data buses (a[3..0] and b[3..0]). The output (y[3..0]) is
a[3..0] if the select control (sel) is low (0). The output is b[3..0] if sel is high (1).

The four-input 2:1 multiplexer will be used in the top level design for selecting the 4-bit slices a[7..4],
a[3..0], b[7..4], and b[3..0] as inputs to the 4 X 4 multiplier.

Figure 2-1.

Step 1 (Ask the instructor for the <pathname>)

1. <pathname> is________________________________

2. Use this <pathname> pathname for this Lab

Step 2 (Create new project and open Verilog text editor file)

Create a project by using the New Project Wizard. To create a project using the New Project Wizard, please
follow the following steps:

1. Select New Project Wizard from the File menu. The first time you open the New Project Wizard, it
shows the introduction page; you can click Next to proceed to the first page of the wizard.

2. Type the directory name or select the directory with Browse . The directory name has been
provided by the instructor in step 1.

3. Type a name for the project in the project name box. For this lab, type mux4.

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4. Type mux4 as the name of the top-level design entity of the project in the top-level design entry box.

5. Click Next. The second page of the New Project Wizard appears.

6. At this point, there is no file to add because we will create the mux4 source file.

7. Click Next. The summary page appears. The summary page gives information about your project.

8. Click Finish. You have just finished the project creation. You should see the top-level entity (mux4) in
the Compilation Hierarchies tab of the Project Navigator window.

9. From the File menu select New or click on . The New file dialog box will appear; select Verilog

HDL File then click on OK.

10. The Verilog text editor will appear.
11. Write your source code.
Remember to use the same input and output port names as shown in Figure 2-1.

12. Save new Verilog text file to <pathname>\verilog\lab2a\mux4.v.

Go to File menu and Choose Save.

Step 3 (Save and check design)

Save and check mux4.v . Click OK when the analysis is complete.

‘Save and check’ checks for syntax and semantic errors.

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Step 4 (Do a functional compilation)

1. From the Processing menu select Compiler Settings. In the dialog box select the Mode tab and Click on
Netlist extraction and synthesis only, including estimated timing. Leave other settings as defaults.

Figure 2-2.
2. Click OK to close the Compiler Settings Dialog Box.

3. From the Processing menu, Select Start Compilation or Click on . Click OK when synthesis is

complete.

Step 5 (Do a functional simulation)

1. The stimulus file has been created for you to verify the functionality of your design. If you are
interested in learning how to create your own stimulus file, please go to the Appendix of this manual.

2. From the Processing menu, Select Simulate Mode or Click on from toolbar.

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Introduction to Verilog Exercises

3. From the Processing menu, Select Simulator Settings. Once the Simulator Settings Dialog Box has
appeared, Click on the Time/Vectors tab to browse to the vector stimuli file (mux4.vwf which is given
to you.).

To browse to the mux4.vwf file Click on . <pathname>\verilog\lab2a\mux4.vwf .

4. Click on Apply.

Figure 2-3.

5. In the Simulator Settings Dialog Box, click on the Mode tab. Change the simulation mode to be
Functional. Click OK to close the Simulator Settings Dialog Box.

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Figure 2-4.

6. From the Processing menu Select Run Simulation or Click on . Click OK when the simulation is
complete.
7. Check to see if you get the same results as shown in Figure 2-5.

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Introduction to Verilog Exercises

Figure 2-5.

Step 6 (Close the simulation waveform)

1. Close the Simulation Waveform window.
2. Switch back to the Compile Mode

Step 7 (Close the project)

1. From the File menu select the Close Project option to close the project.

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Part B

Objective: Build an 8-bit to 16-bit shifter using IF-ELSE statement and

shifting operators

In this exercise, you will build an 8-bit to 16-bit shifter using IF-ELSE statements and the shift-left operator
(<<). This shifter will be capable of performing three types of shifter operations: no shift, left shift by 4 bit
positions, and left shift by 8 bit positions.

The input to the shifter consists of a single 8-bit data bus (in[7:0]). The shift operation is controlled by the
control signal cnt[1:0].

When cnt[1:0] == 0, the ‘no shift’ operation will be selected.

When cnt[1:0] == 1, the ‘left shift by 4’ operation will be selected.

When cnt[1:0] == 2, the ‘left shift by 8’ operation will be selected.

When cnt[1:0] == 3, the ‘no shift’ operation will be selected.

This 8-bit to 16-bit shifter will be used to perform the * 2 ^ 0 (no shift), * 2 ^ 4 (left shift by 4 bit positions),
and * 2 ^ 8 (left shift by 8 bit positions) operations of the following equation:

result[15:0] = a[7:0] * b[7:0]

= ( ( a[7:4] * 2 ^ 4) + a[3:0] * 2 ^ 0 )
* ( ( b[7:4] * 2 ^ 4) + b[3:0] * 2 ^ 0 )

= ( ( a[7:4] * b[7:4] ) * 2 ^ 8 )
+ ( ( a[7:4] * b[3:0] ) * 2 ^ 4 )
+ ( ( a[3:0] * b[7:4] ) * 2 ^ 4 )
+ ( ( a[3:0] * b[3:0] ) * 2 ^ 0 )

Figure 2-6.

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Introduction to Verilog Exercises

Step 1 (Ask the instructor for the <pathname>)

1. <pathname> is________________________________

2. Use this <pathname> pathname for this Lab

Step 2 (Create new project and open Verilog text editor file)

Create a project by using the New Project Wizard. To create a project using the New Project Wizard, please
follow the following steps:

1. Select New Project Wizard from File menu. The first time you open the New Project Wizard, it shows
the introduction page; you can click Next to proceed to the first page of the wizard.

2. Type the directory name or select the directory with Browse . The directory name has been
provided by the instructor in step 1.

3. Type a name for the project in the project name box. For this lab, type shifter.
4. Type shifter as the name of the top-level design entity of the project in the top-level design entry box.

5. Click Next. The second page of the New Project Wizard appears.

6. At this point, there is no file to add because we will create the shifter source file.

7. Click Next. The summary page appears. The summary page gives information about your project.
8. Click Finish. You have just finished the project creation. You should see the top-level entity (shifter)
in the Compilation Hierarchies tab of the Project Navigator window.

9. From the File menu, select New or click on . The New file dialog box will appear; select Verilog

HDL File, then click OK.

10. The Verilog text editor will appear.
11. Write your source code.
Remember to use the same input and output port names as shown in Figure 2-6.

12. Save new Verilog text file to <pathname>\verilog\lab2b\shifter.v.

Go to File menu and Choose Save.

Step 3 (Save and check design)

Save and check shifter.v . Click OK when analysis is complete.

‘Save and check’ checks for syntax and semantic errors.

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Exercises Introduction to Verilog

Step 4 (Do a functional compilation)

1. From the Processing menu select Compiler Settings. In the dialog box select the Mode tab and Click on
Netlist extraction and synthesis only, including estimated timing. Leave other settings as defaults.

Figure 2-7.

2. Click OK to close the Compiler Settings Dialog Box.

3. From the Processing menu, Select Start Compilation or Click on . Click OK when synthesis is

complete.

Step 5 (Do a functional simulation)

1. The stimulus file has been created for you to verify the functionality of your design. If you are
interested in learning how to create your own stimulus file, please go to the Appendix of this manual.

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Introduction to Verilog Exercises

2. From the Processing menu, Select Simulate Mode or Click on from toolbar.

3. From the Processing menu, Select Simulator Settings. Once the Simulator Settings Dialog Box has
appeared, Click on the Time/Vectors tab to browse to the vector stimuli file (shifter.vwf which is given
to you.).

To browse to the shifter.vwf file Click on . <pathname>\verilog\lab2a\shifter.vwf

Figure 2-8.

4. Click on Apply.
5. In the Simulator Settings Dialog Box, Click on the Mode tab. Change the simulation mode to be
Functional. Click OK to close the Simulator Settings Dialog Box.

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Exercises Introduction to Verilog

Figure 2-9.

6. From the Processing menu Select Run Simulation or Click on . Click OK when the simulation is
complete.
7. Check to see if you get the same results as shown in Figure 2-10.

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Introduction to Verilog Exercises

Figure 2-10.

Step 6 (Close the simulation waveform)

1. Close the Simulation Waveform window.
2. Switch back to the Compile Mode

Step 7 (Close the project)

1. From the File menu select the Close Project option to close the project.

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Introduction to Verilog Exercises

Exercise 3

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Exercises Introduction to Verilog

Exercise 3

Objective: Build a 7-segment display using CASE statement.

The 7-segment display shall display 0, 1, 2, 3, and E.

INPUTS OUTPUTS
INP2 INP1 INP0 a b c d e f g DISPLAY
0 0 0 1 1 1 1 1 1 0 0
0 0 1 0 1 1 0 0 0 0 1
0 1 0 1 1 0 1 1 0 1 2
0 1 1 1 1 1 1 0 0 1 3
1 X X 1 0 0 1 1 1 1 E

Figure 3-1.

Step 1 (Ask the instructor for the <pathname>)

1. <pathname> is________________________________

2. Use this <pathname> pathname for this Lab

Step 2 (Create new project and open Verilog text editor file)

Create a project by using the New Project Wizard. To create a project using the New Project Wizard, please
follow the following steps:

1. Select the New Project Wizard from the File menu. The first time you open the New Project Wizard,
it shows the introduction page; you can click Next to proceed to the first page of the wizard.

2. Type the directory name or select the directory with Browse . The directory name has been
provided by the instructor in step 1.
3. Type a name for the project in the project name box. For this lab, type seven.

4. Type seven as the name of the top-level design entity of the project in the top-level design entry box.

5. Click Next. The second page of the New Project Wizard appears.

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6. At this point, there is no file to add because we will create the seven source file.

7. Click Next. The summary page appears. The summary page gives information about your project.

8. Click Finish. You have just finished the project creation. You should see the top-level entity (seven) in
the Compilation Hierarchies tab of the Project Navigator window.

9. From the File menu, select New or click on . The New file dialog box will appear; select Verilog

HDL File then clock OK.

10. The Verilog text editor will appear.
11. Write your source code.
Remember to use the same input and output port names as shown in Figure 3-1.
12. Save new Verilog text file to <pathname>\verilog\lab3\seven.v.
Go to File menu and Choose Save.

Step 3 (Save and check design)

Save and check seven.v . Click OK when analysis is complete.

‘Save and check’ checks for syntax and semantic errors.

Step 4 (Do a functional compilation)

1. From the Processing menu select Compiler Settings. In the dialog box select the Mode tab and Click on
Netlist extraction and synthesis only, including estimated timing. Leave other settings as defaults.

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Exercises Introduction to Verilog

Figure 3-2.

2. Click OK to close the Compiler Settings Dialog Box.

3. From the Processing menu, Select Start Compilation or Click on . Click OK when synthesis is

complete.

Step 5 (Do a functional simulation)

1. The stimulus file has been created for you to verify the functionality of your design. If you are
interested in learning how to create your own stimulus file, please go to the Appendix of this manual.

2. From the Processing menu, Select Simulate Mode or Click on from toolbar.

3. From the Processing menu, Select Simulator Settings. Once the Simulator Settings Dialog Box has
appeared, Click on the Time/Vectors tab to browse to the vector stimuli file (seven.vwf which is given
to you.).

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Introduction to Verilog Exercises

To browse to the seven.vwf file Click on . <pathname>\verilog\lab3\seven.vwf .

Figure 3-3.

4. In the Simulator Settings Dialog Box, click on the Mode tab. Change the simulation mode to be
Functional. Click OK to close the Simulator Settings Dialog Box.

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Exercises Introduction to Verilog

Figure 3-4.

5. From the Processing menu Select Run Simulation or Click on . Click OK when the simulation is
complete.

6. Check to see if you get the same results as shown in Figure 3-5.

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Introduction to Verilog Exercises

Figure 3-5.

Step 6 (Close the simulation waveform)

1. Close the Simulation Waveform window.
2. Switch back to the Compile Mode

Step 7 (Close the project)

1. From the File menu select the Close Project option to close the project.

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Exercises Introduction to Verilog

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Exercise 4

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Exercises Introduction to Verilog

Exercise 4

Objective: Two-part exercise:

Part A - Build a 16-bit register with synchronous operation

Part B - Build a 2 bit counter with asynchronous operation

Part A
Functionality of the 16-bit register:
If clr=’1’ AND clken=’0’, then in_reg will be loaded into register at the rising edge of clock.
Otherwise, if clr=’0’, then the register is cleared at the rising edge of clock.
Note: This is a synchronous clear and clock enable register. Therefore, the IF-THEN
that checks for clear and clock enable should be inside the IF-THEN statement that
checks for the clock condition.

Figure 4-1.

Step 1 (Ask the instructor for the <pathname>)

1. <pathname> is________________________________

2. Use this <pathname> pathname for this Lab

Step 2 (Create new project and open Verilog text editor file)

Create a project by using the New Project Wizard. To create a project using the New Project Wizard, please
follow the following steps:

1. Select the New Project Wizard from the File menu. The first time you open the New Project Wizard,
it shows the introduction page; you can click Next to proceed to the first page of the wizard.

2. Type the directory name or select the directory with Browse . The directory name has been
provided by the instructor in step 1.
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Introduction to Verilog Exercises

3. Type a name for the project in the project name box. For this lab, type reg16.

4. Type reg16 as the name of the top-level design entity of the project in the top-level design entry box.

5. Click Next. The second page of the New Project Wizard appears.

6. At this point, there is no file to add because we will create the reg16 source file.
7. Click Next. The summary page appears. The summary page gives information about your project.

8. Click Finish. You have just finished the project creation. You should see the top-level entity (reg16) in
the Compilation Hierarchies tab of the Project Navigator window.

9. From the File menu, select New or click on . The New file dialog box will appear; select Verilog

HDL File then click OK.

10. The Verilog text editor will appear.
11. Write your source code.
Remember to use the same input and output port names as shown in Figure 4-1.
12. Save new Verilog text file to <pathname>\verilog\lab4a\reg16.v.
Go to File menu and Choose Save.

Step 3 (Save and check design)

Save and check reg16.v . Click OK when analysis is complete.

‘Save and check’ checks for syntax and semantic errors.

Step 4 (Do a functional compilation)

1. From the Processing menu select Compiler Settings. In the dialog box select the Mode tab and Click on
Netlist extraction and synthesis only, including estimated timing. Leave other settings as defaults.

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Figure 4-2.

2. Click OK to close the Compiler Settings Dialog Box.

3. From the Processing menu, Select Start Compilation or Click on . Click OK when synthesis is

complete.

Step 5 (Do a functional simulation)

1. The stimulus file has been created for you to verify the functionality of your design. If you are
interested in learning how to create your own stimulus file, please go to the Appendix of this manual.

2. From the Processing menu, Select Simulate Mode or Click on from toolbar.

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Introduction to Verilog Exercises

3. From the Processing menu, Select Simulator Settings. Once the Simulator Settings Dialog Box has
appeared, Click on the Time/Vectors tab to browse to the vector stimuli file (reg16.vwf which is given
to you.).

To browse to the reg16.vwf file Click on . <path>\verilog\lab4a\reg16.vwf .

Figure 4-3.

4. Click on Apply.
5. In the Simulator Settings Dialog Box, click on the Mode tab. Change the simulation mode to be
Functional. Click OK to close the Simulator Settings Dialog Box.

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Exercises Introduction to Verilog

Figure 4-4

6. From the Processing menu Select Run Simulation or Click on . Click OK when the simulation is
complete.

7. Check to see if you get the same results as shown in Figure 4-5

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Introduction to Verilog Exercises

Figure 4-5.
Step 6 (Close the simulation waveform)
1. Close the Simulation Waveform window.
2. Switch back to the Compile Mode

Step 7 (Close the project)

1. From the File menu select the Close project option to close the project.

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Exercises Introduction to Verilog

Part B
The 2-bit counter can be constructed using the +1 operation. It is used to help the state machine track the
cycles of the sequential multiplication.

Functionality of the 2-bit counter:

If clr=’1’, then the count increments by 1 at the rising edge of clock.
Otherwise, if clr=’0’, then the counter is cleared.
Note: This is an asynchronous clear.

Figure 4-6.

Step 1 (Ask the instructor for the <pathname>)

1. <pathname> is________________________________

2. Use this <pathname> pathname for this Lab

Step 2 (Create new project and open Verilog text editor file)

Create a project by using the New Project Wizard. To create a project using the New Project Wizard, please
follow the following steps:

1. Select the New Project Wizard from the File menu. The first time you open the New Project Wizard,
it shows the introduction page; you can click Next to proceed to the first page of the wizard.

2. Type the directory name r select the directory with Browse . The directory name has been
provided by the instructor in step 1.

3. Type a name for the project in the project name box. For this lab, type counter.
4. Type counter as the name of the top-level design entity of the project in the top-level design entry box.

5. Click Next. The second page of the New Project Wizard appears.

6. At this point, there is no file to add because we will create the counter source file.

7. Click Next. The summary page appears. The summary page gives information about your project.

8. Click Finish. You have just finished the project creation. You should see the top-level entity (counter)
in the Compilation Hierarchies tab of the Project Navigator window.

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9. From the File menu, select New or click on . The New file dialog box will appear; select Verilog

HDL File then click OK.

10. The Verilog text editor will appear.
11. Write your source code.
Remember to use the same input and output port names as shown in Figure 4-6.
12. Save new Verilog text file to <pathname>\verilogl\lab4b\counter.v.
Go to File menu and Choose Save.

Step 3 (Save and check design)

Save and check counter.v . Click OK when analysis is complete.

‘Save and check’ checks for syntax and semantic errors.

Step 4 (Do a functional compilation)

1. From the Processing menu select Compiler Settings. In the dialog box select the Mode tab and Click on
Netlist extraction and synthesis only, including estimated timing. Leave other settings as defaults.

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Figure 4-7.

2. Click OK to close the Compiler Settings Dialog Box.

3. From the Processing menu, Select Start Compilation or Click on . Click OK when synthesis is

complete.

Step 5 (Do a functional simulation)

1. The stimulus file has been created for you to verify the functionality of your design. If you are
interested in learning how to create your own stimulus file, please go to the Appendix of this manual.

2. From the Processing menu, Select Simulate Mode or Click on from toolbar.

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3. From the Processing menu, Select Simulator Settings. Once the Simulator Settings Dialog Box has
appeared, Click on the Time/Vectors tab to browse to the vector stimuli file (counter.vwf which is
given to you.).

To browse to the counter.vwf file Click on . <pathname>\verilog\lab4b\counter.vwf .

Figure 4-8.

4. In the Simulator Settings Dialog Box. Click on Mode tab. Change the simulation mode to be
Functional. Click OK to close the Simulator Settings Dialog Box.

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Figure 4-9.

5. From the Processing menu Select Run Simulation or Click on . Click OK when the simulation is
complete.

6. Check to see if you get the same results as shown in Figure 4-10.

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Figure 4-10.

Step 6 (Close the simulation waveform)

1. Close the Simulation Waveform window.
2. Switch back to the Compile Mode

Step 7 (Close the project)

1. From the File menu select the Close project option to close the project.

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Exercise 5

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Exercise 5

Objective: Two-part exercise:

Part A – Examine the controlling state machine

Part B – Putting it all together by declaring and instantiating the

lower-level components

Part A
You have now completed building all of the components necessary to build the 8x8 multiplier, except for
the controlling state machine and the 4x4 multiplier (Part B). Due to time constraints, the controlling state
machine has been written for you and is located in <pathname>\verilog\lab5a\control.v.

This state machine will manage all the operation that occurs within the 8x8 multiplier.

The state machine will perform the ( (a[3..0] * b[3..0] ) * 2 ^ 0 ) multiplication in the first cycle (LSB state)
after the input signal start becomes a ‘1’. This intermediate result is saved in an accumulator.

In the second clock cycle (MID state), the ( ( a[3..0] * b[7..4] ) * 2 ^ 4 ) multiplication is performed. The
multiplication result is added with the content of the accumulator and clocked back into the accumulator.

In the third clock cycle (MID state), the ( ( a[7..4] * b[3..0] ) * 2 ^ 4 ) multiplication is performed. The
multiplication result is added with the content of the accumulator and clocked back into the accumulator.

In the fourth clock cycle (MSB state), the ( (a[7..4] * b[7..4] ) * 2 ^ 8 ) multiplication is performed. The
multiplication result is added with the content of the accumulator and clocked back into the accumulator.
This result is the final result:

result[15..0] = a [7..0] * b[7..0]

= ( ( a[7..4] * b[7..4] ) * 2 ^ 8 )
+ ( ( a[7..4] * b[3..0] ) * 2 ^ 4 )
+ ( ( a[3..0] * b[7..4] ) * 2 ^ 4 )
+ ( ( a[3..0] * b[3..0] ) * 2 ^ 0 )

NOTE: There are two inputs to the state machine start and count[1..0]. The start signal is a single cycle
high-true signal. When start becomes a ‘1’, it indicates that multiplication can begin at next clock cycle.
The start signal can only be asserted for one clock cycle. The start signal shall stay a ‘0’ until next 8x8
multiplication is to be performed. The count[1..0] signal is the output of a free running 2-bit counter. The
count[1..0] signal is synchronously initialized by the start signal. Count[1..0] is used by the state machine
to track the cycles of the multiplication.

Please also note that this is NOT the optimal design. The state machine design as you see it is intended for
exercising your Verilog skills and not the ability to perform optimum solution.

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Figure 5-1.

START=0
COUNT=X
---------------
in_sel[1..0]=X
shif[1..0]=x
done=0
clken=1
regclr=1
IDLE
START=0 state_out[2..0]=000
COUNT=3 START=1
--------------- COUNT=X
in_sel[1..0]=3 ---------------
shif[1..0]=2 in_sel[1..0]=X
START=1
done=1 shif[1..0]=x
COUNT=x
clken=0 done=0
---------------
regclr=1 in_sel[1..0]=x clken=1
regclr=0
shif[1..0]=x
others done=0
--------------- clken=1
in_sel[1..0]=x regclr=0
shif[1..0]=x
done=0
clken=1
regclr=1 others
ERR ---------------
state_out[2..0]=100 in_sel[1..0]=x
shif[1..0]=x LSB
MSB done=0 state_out[2..0]=001
state_out[2..0]=011 clken=1
others
--------------- regclr=1
in_sel[1..0]=x
shif[1..0]=x others
done=0 ---------------
clken=1 in_sel[1..0]=x
regclr=1 shif[1..0]=x
done=0 START=0
clken=1 COUNT=0
START=0 regclr=1 ---------------
COUNT=2 in_sel[1..0]=0
--------------- shif[1..0]=0
in_sel[1..0]=2 done=0
shif[1..0]=1 clken=0
done=0 regclr=1
clken=0 MID
regclr=1 state_out[2..0]=010

START=0
COUNT=1
---------------
in_sel[1..0]=1
shif[1..0]=1
done=0
clken=0
regclr=1

X means a “don’t care” in this state diagram.

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Part B
You have now completed building all of the components necessary to build the 8x8 multiplier.

Making use of the knowledge you have gained up to this point, you should instantiate each component in a
top-level design and connect all signal as shown in Figure 5-2. You have successfully completed the
Introduction to Verilog class once your top-level design is compiled and simulated correctly.

Congratulations!

You have completed the implementation of the following 8x8 multiplier.

result[15..0] = a [7..0] * b[7..0]

= ( ( a[7..4] * b[7..4] ) * 2 ^ 8 )
+ ( ( a[7..4] * b[3..0] ) * 2 ^ 4 )
+ ( ( a[3..0] * b[7..4] ) * 2 ^ 4 )
+ ( ( a[3..0] * b[3..0] ) * 2 ^ 0 )

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Figure 5-2.

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Step 1 (Ask the instructor for the <pathname>)

1. <pathname> is________________________________

2. Use this <pathname> pathname for this Lab

Step 2 (Create new project and open Verilog text editor file)

Create a project by using the New Project Wizard. To create a project using the New Project Wizard, please
follow the following steps:

1. Select the New Project Wizard from the File menu. The first time you open the New Project Wizard,
it shows the introduction page; you can click Next to proceed to the first page of the wizard.

2. Type the directory name or select the directory with Browse . The directory name has been
provided by the instructor in step 1.

3. Type a name for the project in the project name box. For this lab, type mult8x8.
4. Type mult8x8 as the name of the top-level design entity of the project in the top-level design entry
box.

5. Click Next. The second page of the New Project Wizard appears.

6. At this point, there is no file to add because we will create the mult8x8 source file
7. Click Next. The summary page appears. The summary page gives information about your project.

8. Click Finish. You have just finished the project creation. You should see the top-level entity (mult8x8)
in the Compilation Hierarchies tab of the Project Navigator window.

9. From the File menu, select New or click on . The New file dialog box will appear; select Verilog

HDL File then click OK.

10. The Verilog text editor will appear.
11. Write your source code.
Remember to use the same input and output port names as shown in Figure 5-2.

12. Save new Verilog text file to <pathname>\verilog\lab5b\mult8x8.v.

Go to File menu and Choose Save.

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13. The lower-level components have been created in different directories than the current directory. In
order for Quartus to find these lower-level components, it must have a search path. Therefore, you
must do the following:
Go to the Project menu and Choose General Settings. From General Settings Choose User

Libraries tab. Browse the file locations:

a) Choose the directory structure <path>\verilog\lab1a. Click on open.
b) Choose the directory structure <path>\verilog\lab1b. Click on open.
c) Choose the directory structure <path>\verilog\lab2a. Click on open.
d) Choose the directory structure <path>\verilog\lab2b. Click on open.
e) Choose the directory structure <path>\verilog\lab3. Click on open.
f) Choose the directory structure <path>\verilog\lab4a. Click on open.
g) Choose the directory structure <path>\verilog\lab4b. Click on open.
h) Choose the directory structure <path>\verilog\lab5a. Click on open.
i) Choose the directory structure <path>\verilog\lab5b. Click on open.
j) Click OK.

Step 3 (Save and check design)

Save and check mult8x8.v . Click OK when analysis is complete.

‘Save and check’ checks for syntax and semantic errors.

Step 4 (Do a functional compilation)

1. From the Processing menu select Compiler Settings. In the dialog box select the Mode tab and Click on
Netlist extraction and synthesis only, including estimated timing. Leave other settings as defaults.

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Figure 5-3.

2. Click OK to close the Compiler Settings Dialog Box.

3. From the Processing menu, Select Start Compilation or Click on . Click OK when synthesis is

complete.

Step 5 (Do a functional simulation)

1. The stimulus file has been created for you to verify the functionality of your design. If you are
interested in learning how to create your own stimulus file, please go to the Appendix of this manual.

2. From the Processing menu, Select Simulate Mode or Click on from toolbar.

3. From the Processing menu, Select Simulator Settings. Once the Simulator Settings Dialog Box has
appeared, Click on the Time/Vectors tab to browse to the vector stimuli file (mult8x8.vwf which is
given to you).
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To browse to the mult8x8.vwf file Click on . <pathname>\verilog\lab5b\mult8x8.vwf .

Figure 5-4.

4. Click on Apply.
5. In the Simulator Settings Dialog Box, click on the Mode tab. Change the simulation mode to be
Functional. Click OK to close the Simulator Settings Dialog Box.

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Figure 5-5.

6. From the Processing menu Select Run Simulation or Click on . Click OK when the simulation is
complete

7. Check to see if you get the same results as shown in Figure 5-6.

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Figure 5-6.

Step 6 (Close the simulation waveform)

1. Close the Simulation Waveform window.
2. Switch back to the Compile Mode

Step 7 (Close the project)

1. From the File menu select the Close Project option to close the project.

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APPENDIX

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How to create a stimulus file:

1. Create a new waveform stimulus for simulation. Click on

2. Under Other Files tab: Choose Vector Waveform File

3. Click OK.
4. Enter nodes into the waveform file. Insert menu -> Enter Node or Bus
5. Set the inputs to the appropriate values.
6. Save the file.

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