SRP 1 All computers logic is based on logic gates

A
A
A B A.B A+B A’ (A.B)’ (A + B)’ XNOR
 Digital logic : basis for digital computing and provides XOR B
B
a fundamental understanding on how circuits and
hardware communicate within a computer. 0 0 0 0 1 1 1 0 1
0 1 0 1 1 1 0 1 0
 Digital circuits are made from a large collection of 1 0 0 1 0 1 0 1 0
logic gates
1 1 1 1 0 0 0 0 1
 Logic Gates : Logic gates are the basic building blocks
of any digital circuit.
Universal logic gates
They are called as “Universal Gates” because-

•They can realize all the binary operations.

•All the basic logic gates can be derived from them.

They have the following properties-

•Universal gates are not associative in nature.
•Universal gates are commutative in nature.
 BUBBLED GATE OR
ALTERNATIVE GATE

Steps for flip flop conversions : SRP 2

1. Identify available and required flip flop
2. Make characteristic table for required flip flop
CASCADED XOR 3. Make excitation table for available flip flop
Output of odd no. of gates = output of 1st XOR 4. Write Boolean expression for available flip flop
Out of even no. of gates = output of 2nd xor gate 5. Draw the circuit
 Properties of Boolean Algebra
•Commutative law – SOP = Minterms = Product Terms (Number of 1’s in Kmap)

•Annulment law – •A + B = B + A
A.B = B.A POS = Maxterms = Sum terms (Number of 0’s in Kmap)
•A.0 = 0
A+1=1
•Associative law –
•Identity law – •A+(B+C) = (A+B)+C
•A.1 = A A.(B.C) = (A.B).C
A+0=A
•Distributive law –
•Idempotent law – •A.(B+C) = (A.B)+(A.C)
•A + A = A A+(B.C) = (A+B).(A+C)
A.A = A
•Absorption law –:-
•Complement law – •A.(A+B) = A
•A + A’ = 1 A + AB = A
A.A’ = 0
•De Morgan law –
•Double negation law – ((A)’)’=A •(A.B)’ = A’ + B’
USED IN ALGEBRAIC MANIPULATION
(A+B)’ = A’.B

For n variable function , we have 2n literals

Literal count no. of times variable appearing

F(A,B,C,D) = AB + BC + C’D
SRP 3
LC = 6
Minimization of Boolean Expression :
1. Algebraic Manipulation (Tedious)
2. Kmap (Cool!)
SRP 4
 SRP 5 Canonical form is more complex while standard form is
simple.

HAZARD FREE EXPRESSION

Sequential circuit = Combinational Ckt + Memory +

Feedback
Present O/P = Present Input + Past O/p

Ex : Counter , Flip Flops , Registers

Flip Flop = Latch + Clock

Both Flip flops and Latch are m/m elements , difference
only latch contain no clock
SRP 6
 SRP 7 UP COUNTER :
Different signs
Synchronous Counter : Common Clock
Based on next state equation
ASYNCHRONOUS DOWN COUNTER :
SAME SIGN Asynchronous counter : No common clock
UP COUNTER Based on toggling operations – JK and T f/f

Using CLR and CLR’ ASYNCHRONOUS DOWN COUNTER

Using PRE and PRE’
PROBLEM WITH RING AND Applications of shift Registers –
•The shift registers are used for temporary data storage.
JOHNSON COUNTER •used for data transfer and data manipulation.
•The serial-in serial-out and parallel-in parallel-out shift registers
Ring Counter : Using n Flip Flop , maximum n counting possible are used to produce time delay to digital circuits.
Johnson Counter : Using n flip flops maximum 2n counting •The serial-in parallel-out shift register is used to convert serial
possible data into parallel data thus they are used in communication lines
where demultiplexing of a data line into several parallel line is
But for n inputs there are 2 n possibilities therefore need required.
asynchronous counter •A Parallel in Serial out shift register us used to convert parallel
data to serial data.
Why Ripple named so ?
Because delay depends on total no. of states or flip flops. Flip flops can be used to store a single bit of
binary data (1or 0). However, in order to store
multiple bits of data, we need multiple flip flops.
Johnson Counter If ASYNCHRONOUS CLR Input = Mod N flip flops are to be connected in an order to
SI = Q0’ 8 counter
store n bits of data. A Register is a device which is
Mod 2n Counter Then SYNCHRONOUS CLR Input =
Mod 9 counter
used to store such information. It is a group of flip
flops connected in series used to store multiple
Ring Counter SI = Q0 If ASYNCHRONOUS PRE Input = Mod bits of data.
Mod n Counter 8 counter The information stored within these registers can
Then SYNCHRONOUS PRE Input = be transferred with the help of shift registers.
Mod 9 counter Shift Register is a group of flip flops used to store
SRP 8 multiple bits of data.
Combinational circuits are defined as the time independent circuits Combinational Circuit Features –
which do not depends upon previous inputs to generate any output
are termed as combinational circuits. 1.In this output depends only upon present input.
2.Speed is fast.
EXAMPLES OF COMBINATIONAL CIRCUITS :
SRP 9 3.It is designed easy.
4.There is no feedback between input and output.
1. Multiplexer : Many to One 5.This is time independent.
2. Demultiplexer : One to many 6.Combinational circuits don’t have capability to store any
3. Encoder : convert 2N lines of input into a code of N bits state.
4. Decoder : decode the N bits into 2 N lines 7.As combinational circuits don’t have clock, they don’t
5. Seven Segment Decoder : electronic device which consists of seven require triggering.
Light Emitting Diodes (LEDs) arranged in a some definite pattern 8.These circuits do not have any memory element.
(common cathode or common anode type), which is used to display
Hexadecimal numerals HALF ADDER
6. Half Adder : Addition of 2 bits Sum = A'B + AB' = A XOR B (minterm = 1,2) & (maxterm = 0,3)
7. Full Adder : adds three inputs and produces two outputs Carry = AB = A AND B (minterm = 3) & (maxterm = 0,1,2)
8. Binary Adder : performs the arithmetic sum of two binary numbers GATES = 1 XOR & 1 AND
provided with any length
9. Half Subtractor : subtraction of 2 bits FULL ADDER
10. Full Subtractor : 3 Inputs and 2 outputs for subtraction SUM = C-IN XOR (A XOR B)= (1,2,4,7)

Logical Expression for C-OUT

Steps to construct combinational circuit : APPLICATIONS : = A B + B C-IN + A C-IN
1. Identify number of inputs and outputs 1. Arithmetic & Logical = (3,5,6,7)
2. Creating the truth table Functions
3. Simplify the Boolean expression 2. Data Transmission COUT = AB + C-IN (A EX – OR B) - IMPLEMENTATION
4. Construct the circuit 3. Code Converters
•Half subtractors have no scope of taking Half Subtractor can be Half Adder can be implemented using 5 NAND
into account “Borrow-in” from the previous implemented using 5 Half Adder can be implemented using 5 NOR
circuit. NAND
•To overcome this drawback, full subtractor Half Subtractor can be
comes into play. Full Adder can be implemented using 2 Half
implemented using 5 NOR
Diff(A,B) = A XOR B = (1,2)
Borrow = A’B = (1)
SRP 10 adders and 1 OR Gate.

Full Subtractor can be Full Adder can be implemented using 9 NAND

FULL SUBTRACTOR implemented using 2 Half Full Adder can be implemented using 9 NOR
SUM = C-IN XOR (A XOR B)= (1,2,4,7) subtractor and 1 OR Gate.
Logical Expression for B-OUT
Full Subtractor can be
= = A’Bin + A’B + BBin
= (1,2,3,7) implemented using 9 NAND
Full Subtractor can be
BOUT = Bin (A XOR B)’ + A’B - IMPLEMENTATION implemented using 9 NOR

D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
Binary code of N digits can be One limitation of this encoder is 0 0 0 0 0 0 0 1 0 0 0
used to store 2N distinct that only one input can be
0 0 0 0 0 0 1 0 0 0 1
elements of coded information. active at any given time.
0 0 0 0 0 1 0 0 0 1 0
This is what encoders and To overcome this, we use 0 0 0 0 1 0 0 0 0 1 1
decoders are used for. Priority Encoders.
Encoders convert 2N lines of 0 0 0 1 0 0 0 0 1 0 0
Another ambiguity arises when
input into a code of N bits all inputs are 0. In this case, 0 0 1 0 0 0 0 0 1 0 1
and Decoders decode the N bits encoder outputs 000 which 0 1 0 0 0 0 0 0 1 1 0
into 2N lines. actually is the output for D0 1 0 0 0 0 0 0 0 1 1 1
active.
Priority Encoder – D3 D2 D1 D0 X Y V Using 4x 1 MUX we can
A priority encoder is an encoder
0 0 0 0 x x 0 implement ALL the
circuit in which inputs are given functions of 3 variables
priorities. When more than one 0 0 0 1 0 0 1 and 1 inverter.
inputs are active at the same time,
the input with higher priority takes 0 0 1 x 0 1 1 Using 8 x 1 MUX , we
precedence and the output can implement ALL the
0 1 x x 1 0 1
corresponding to that is generated. functions of 4 variables
1 x x x 1 1 1 and 1 inverter.
Multiplexers in Digital Logic
Multiplexer can act as universal combinational circuit.
Many input to one output.
(NOT, AND,OR,NAND,NOR,EXOR,EXNOR)
For N input lines, log n (base2) selection lines.
Multiplexers are also known as “Data n
All the standard logic gates can be implemented with
SRP 11
selector, parallel to serial convertor, many to
one circuit, universal logic circuit​”. multiplexers

MUX Implementation : Implement 4 x 1 MUX = 3 MUX ( 2 x 1)

1. NOT – Only 1 (2:1 MUX) N1/N2 until 1
2. AND – Only 1 (2:1 MUX)
3. OR – Only 1 (2:1 MUX) Implement 8x1 MUX =7 MUX (2X1 )
4. NOR – Only 2 (2:1 MUX)
5. NAND – Only 2 (2:1 MUX) Implement 8x1 MUX = 2 MUX (4X1) and Enable
6. EXOR – Only 2 (2:1 MUX)
7. EXNOR – Only 2 (2:1 MUX) Implement 16x1 MUX = 5 MUX (4x1)
 •Worst case delay of a ripple carry adder is the time
Ripple Carry Adder- SRP 12 after which the output sum bit and carry bit becomes
available from the last full adder.
It is used for the purpose of adding two n-bit binary numbers.
•It is also known as n-bit parallel adder. Time after which output carry bit becomes available from the
•After giving Cin to full adder , it comes into operation. last full adder
•S0 = A0 ⊕ B0 ⊕ Cin = Total number of full adders X Carry propagation delay of full
•C0 = A0B0 ⊕ B0Cin ⊕ CinA0 adder
= Total number of full adders X { Propagation delay of AND
•Let, The two 4-bit numbers are 0101 (A3A2A1A0) and 1010 gate + Propagation delay of OR gate }
(B3B2B1B0).
Time after which output sum bit becomes available from the
last full adder
= Time taken for its carry in to become available + Sum
propagation delay of full adder
= { Total number of full adders before last full adder X Carry
propagation delay of full adder } + Propagation delay of XOR
gate
Carry Look Ahead Adder-
•Carry Look Ahead Adder is an improved version of the ripple
carry adder.
DISADV : •It generates the carry-in of each full adder simultaneously
•Ripple Carry Adder does not allow to use all the full adders without causing any delay.
simultaneously.
•Each full adder has to necessarily wait until the carry bit The carry-in of any stage full adder depends
becomes available from its adjacent full adder. only on the following two parameters-
•This increases the propagation time. •Bits being added in the previous stages
•Due to this reason, ripple carry adder becomes extremely •Carry-in provided in the beginning
slow.
 DISADV :
•It involves complex hardware and List - I List - II
costly
•It gets more complicated as the number (a)Decoder (i)1 line to 2n lines
of bits increases
(b)Multiplexer (ii)n lines to 2n lines
(c)De multiplexer (iii)2n lines to 1 line

DEMUX = Data Distributor (EN = 1)

•C
Finally, we have the following equations-
1 = C0P0 + G0
•C1 = C0P0 + G0
•C = C P P + G0P1 + G1
•C22 = C00P00P11+ G0P
•C
•C3 = C0P0P1P2 + G0P0P
3 = C 0 P 0 P1 P 2 + 1 + G1
G 1P2 + G1P2 + G2
1 P 2 + G1 P 2 + G2
SRP 13
•C
•C44=C=C00PP00P
P11PP22P3
P3++GG P P P + GPP3 2+PG3 2+P3G+2P3 +
0P01P12P23 +3G1P21
GG3 3
FORMULA :
For a n-bit carry look ahead adder to evaluate all
the carry bits, it requires-
•Number of AND gates = n(n+1) / 2
•Number of OR gates = n
Decimal to Binary = Divide by 2 & print result in Binary to Decimal = Multiply 2 with powers.
reverse. Binary to Octal = Make group of 3 bits and add zero if
Decimal to Octal = Divide by 8 and print result in required
reverse. Binary to hexadecimal = Make group of 4 bits and add
Decimal to Hexadecimal = Divide by 16 & print result in zero if required.
reverse. Octal to Binary = Make group of 3 bits in binary and
remove zeroes
For Decimal value (0.25) = Multiply 2 (B), 8(O), 16 (H) Octal to Decimal = Multiply 8 with powers
Octal to Hexadecimal = Convert to Binary in 3 bits and
make it 4 bits from RHS
Hexadecimal to Binary = Convert into binary in 4
754
bits and remove extra zeroes
Hexadecimal to Decimal = Multiply 16 SRP 14
Hexadecimal to Octal = Convert to binary in 4
bits and then 3 bits from RHS
SRP 15
Half Adder = Add 2 “1” bit numbers
Sum = A xor B UNSIGNED 0 to 2n - 1 0 to 7
MAGNITUDE
Carry = AB
Using 5 NAND , 5 NOR SIGNED −(2N−1 − 1) to (2N−1 − 1) -3 to +3
MAGNITUDE
Half Subtractor = Subtract 2 “1” bit numbers 1’S −(2N−1 − 1) to (2N−1 − 1) -3 to +3
Difference = A xor B COMPLEMENT
Borrow = A’B
Using 5 NAND , 5 NOR 2’S −(2N−1 ) to (2N−1 − 1) -4 to +3
COMPLEMENT

Let X be the number of distinct 16-bit integers in 2’s

SRP 16 complement representation. Let Y be the number of distinct

16-bit integers in sign magnitude representation. Then X −Y
is 1
FULL SUBTRACTOR = Subtract 3 bit numbers
Difference = A xor B xor C = min(1,2,4,7) = max (0,3,5,6) FULL ADDER = Add 3 bit numbers
Borrow = A’B + BC +A’C OR = min(1,2,3,7) Sum = A xor B xor C = min(1,2,4,7) = max (0,3,5,6)
A’B + (A xor B)’C Carry1 = AB + BC + AC = min(3,5,6,7) = max (0,1,2,4)
Carry2 = AB + (A xor B)C Carry2 = AB + (A xor B)C
Using 9 NAND , 9 NOR Using 9 NAND , 9 NOR
Using 2 Half subtractor and 1 OR GATE Using 2 Half adders and 1 OR GATE
A XOR B = AB’ + A’B
Demorgan’s law
(Inequality Detector) Minimum NAND : SOP
(AB)’=A’+B’ AB + CD , A+ B, A+ BC = 3
A XNOR B = AB +A’B’
(A+B)’ = A’.B’ AB + CD + EF = 6
(Equality Detector) AB + BC + CD + DA = 6
NOR GATE : POS Form Commutative law = All logic gates
(A+B)(C+D) = 3 minimum Associative law = Only NAND , NOR Not Follows
(B’+D)(B+D’) = 3 minimum Distributive law : A(B+C) = AB+AC
A+BC = (A+B)(A+C)
A.B = (A+A)(B+B) = 3 Consensus theorem :
A(B+C) = (A+A)(B+C) = 3 AB + BC + A’C = AB +A’C
When XOR = XNOR’ (Even inputs)
XOR = Odd number of 1’s Detector When XOR = XNOR (Odd inputs)
XNOR = Odd and even no. of 1’s Detector SRP 17