Two Mark Questions 1
Two Mark Questions 1
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CS3351-DIGITAL
DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION
EPC-II
II YEAR CSE, IT/III RD SEMESTER
PART-A
1. How many bits are required to represent the decimal numbers in the range 0 to 999
using straight binary code? Using BCD codes?
(999) 10 = (1001 1001 1001) BCD → 12 bits are required using BCD code
3. A bulb in a staircase has two switches, one switch being at the ground floor and the
other one at the first floor. The bulb can be turned ON and also can be turned OFF by
any one of the switches irrespective of the state of the other switch.
switc
Which logic gate does the logic of switching of the bulb resembles?
XOR gate
4. Design the combinational circuit with 3 inputs and 1 output. The output is 1 when the
binary value of thee input is less than 3.
A priority encoder is an encoder circuit that includes the priority function. The operation
of the priority encoder is such that if two or more inputs are activated at the same time,
the output binary code will be generated to the highest-numbered
highest input.
A combinational circuit consists of logical gates whose outputs at any time are determined
from the present combination of
o inputs.
9. Draw the circuit for 2 to 1 multiplexer circuit. and Give functional block
b diagram of
2 * 1 MUX.
Karnaugh map is a map method that provides a simple, straightforward procedure for
minimizing Boolean functions in canonical form.
i. Generally, it is limited to six variable map (i.e.) more than six variable involving
expressions are not reduced.
ii. The map method is restricted in its capability since they are useful for simplifying only
Boolean expression represented in standard form.
(i)Any large decimal number can be easily converted into corresponding binary number
(ii)A person needs to remember only the binary equivalents of decimal number from 0 to 9.
(iii)Conversion from BCD into to decimal is also very easy.
The disadvantages of BCD code are
(i.) The code is least efficient. It requires several symbols to represent even small
numbers.
(ii) Binary addition and subtraction can lead to wrong answer.
(iii) Special codes are required for arithmetic operations.
(iv) This is not a self-complementing
complementing code.
(v) Conversion into other coding schemes requires special methods
PART-B
F(w,x,y,z) = ∑ (2,3,5,6,11,14,15)
(ii).Implement
Implement the Boolean function F ( x,y,z) =∑
=∑ (1,2,6,7 ) using multiplexer
5. Simplify the following Boolean into (i) SOP form and (ii) POS form and implement the
simplified functions using AND, OR gates.
F(A,B,C,D) = ∑(0,1,2,5,8,9,10)
6. Design a combinational circuit with 4 inputs, w, x, y and z and 3 outputs, a, b and c. When
the binary input is 0, 1, 2, 3, 4, 5, 6, 7 the any of the 2 output is one. When the binary input is
8 to 14, the any of the one output is one and if all inputs is 1, all outputs are 1.
PART-A
A race
ace occurs with more than one bit change in state transitions because two bits are
"racing" to be the other. for example 00 ->> 11. it can be 01 first, or 10 first, and this may
cause problems. When this leads to problems, it's called a critical race. but if i this race
condition eventually leads to the final or intended state anyway, it's ok. for example, with
an input of 1, 00->11
>11 is expected. but with an input of 1, the state 10 leads to next state 11,
and the same is with 01 leading to next state 11. so you
yo have no problem.
An edge-triggered flip-flop
flop changes states either at the positive edge (rising edge) or at the
th
negative edge (falling edge) of the clock pulse on the control input. The three basic types
are introduced here: S-R, J-K
K and D.
A Mealy Machine changes its output on the basis of its present state and current input.
Mealy machines react faster to inputs. They generally react in the same clock cycle.
A Moore Machine’s output depends only on the current state. It does not depend on the
current input. In Moore machines, more logic is required to decode the outputs resulting
resul in
more circuit delays. They generally react one clock cycle later.
(i) State diagram is the graphical representation of state table of sequential logic circuits.
(ii)In the state diagram, a state is represented by a circle and the transition betwee
between states is
indicated by directed lines connecting the circles.
(iii)The directed lines are labeled with two binary numbers separated by a slash. The input
value during the present state is labeled first and the number after the slash gives the
output during
ing the present state.
Flip-flop
flop is a sequential circuit which is used to store single bit of information at a time
i.e. either 1 or 0 at a time. It has two stable output states. It can stay in one of the two
stable states unless state is changed by applying external inputs. Thus, it as a basic memory
element for storage of data in binary form. There are various types of flip-
flip-flops. 1.S-R flip
flop 2.J-K flip-flop 3.D-flip
flip flop 4.T
4.T-flip-flop.
Race around condition can be eliminated in JK latch by two ways 1. Using the edge
triggered J-K flip-flop.
flop. 2. Using the master slave J-K
J flip-flop.
14. If a serial-in-serial-out
out shift register has N stages and
and if the clock frequency is f,
what will be the time delay between input and output?
In a counter if the next state of some unused state is again an unused state
sta and if by
chance the counter happens to find itself in the unused states and never arrived at a used
state then the counter is said to be in the lockout conditions.
PART-B
2.What are registers ? Construct a 4 bit register using D flip flops and explain the
operations on types of register
register.
5.Analyze
Analyze the synchronous Moore circuit and obtain its state diagram.
6.A
A sequential circuit with two ‘D’ Flip-Flops
Flip Flops A and B, one input (x) and one output (y).
The Flip-Flop
Flop input functions are: DA= Ax+ Bx DB= A’x and the circuit output function
is, Y= (A+ B) x’.
PART-A
Operands are definite elements of computer instruction that show what information
is to be operated on. The most important general categories of data are
1. Addresses
2. Numbers
3. Characters
4. Logical data
5. Define Instruction set completeness.
Types
es of Addressing Modes
• Immediate Addressing
• Register Addressing.
• Indirect Addressing.
• Indexed Addressing.
• Based Addressing.
9. Define ISA and their types.
The Instruction Set Architecture (ISA) is the part of the processor that is visible to the
programmer or compiler writer. The ISA serves as the boundary between software and
hardware.
The 3 most common types of ISAs are:
Stack - The operands are implicitly on top of the stack.
Accumulator - One operand is implicitly the accumulator.
General Purposeose Register (GPR) - All operands are explicitely mentioned, they are
either registers or memory locations.
The Opcode shown above determines the nature of the operation to be performed.
The operands,, Operand 1 and operand 2 identify the data on which operation has to be
performed. The operand can be a memory location, a processor register,
regist immediate
value or logical data.
1. Instructions that transfers the data between the memory of the computer and
processor register.
2. Instructions that can perform arithmetic and logical operations on the data.
3. Instructions
ctions controlling the sequencing of execution of instructions, like branch
instruction.
4. Instructions performing the I/O transfer i.e. transferring the data from internal storage
to the external storage or device.
PART-B
3. What are addressing modes? Explain the various addressing modes with examples.
5.Write any program and show the interaction between assembly and high level language.
UNIT-IV PROCESSOR
A data hazard is any condition in which either the source or the destination
destination operands of an
instruction are not available at the time expected in the pipeline. A data hazard is a
situation in which the pipeline is stalled because the data to be operated on are delayed for
some reason.
A unit used to operate on or hold data within a processor. In the MIPS Implementation,
the data path elements include the instruction and data memories,
memories, the register file, the
ALU, and adders.
4. List the five stages of instruction execution.
1. IF: Instruction fetch
2. ID: Instruction decode and register file read
3. EX: Execution or address calculation
4. MEM: Data memory access
5. WB: Write back
5. How data hazard can be prevented in pipelining?
Data hazards in the instruction pipelining can prevented by the following techniques.
6. Define Pipelining.
A pipeline may also be stalled because of the delayed in the availability of an instruction.
This may be a result
sult of a miss in the catch, requiring the instruction to be fetched from the
main memory. Such hazard are often called control hazard..
1. Processor clock
2. Basic Performance Equation
3. Pipelining
4. Clock rate
5. Instruction set
6. Compiler
PART-B
1. Describe the data path and control considerations for pipelining.
2. Describe in detail about micro programmed control.
3. Describe about pipelining
pipelining?
4. Explain in detail about how a control unit is designed in a processor.
processor
5. Write a short note on Data hazard and Control hazards
6. With neat example explain about an instruction execution.
PART-A
The time that elapses between the initiation of an operation and the completion of that
operation is called memory access time. e.g.: time between the read and the MFC signal.
Memory cycle time is the minimum time delay required between the initiation of two
successive memory operations.eg: time between two successive read operations.
Cache memory is a small, fast memory that is inserted between th thee larger, slower main
memory and the processor.
It holds the currently active segments of a program and their data.
4. What are the uses of memory management unit?
The virtual address space is mapped onto the physical memory where data are actually
stored.
A special memory control circuit, often called the memory management unit, implements
the mapping function.
The term memory latency is used to refer to the amount of time it takes to transfer a word
of data to or from the memory. If the performance measure is defined in terms of the
number of bits or bytes that can be transferred in one second, then the measure is called
memory bandwidth.
-Rotational
Rotational or latency time is the amount of time that elapses after the head is positioned
over the correct track until the starting position of the address sector passes under the
read/write head. The sum of these above two delays is called the disk access time.
We consider a unit of memory called page. A page is typically rather large, for example 4
KB (4096 bytes). A page is the unit of memory that is transferred between disk and main
memory. A virtual page is either in memory or on disk. Example: 32-bit
32 bit virtual address
space Pages that aree 4 KB large (4 KB = 212 bytes) 16 MB main memory (16 MB = 224
bytes)
Rotational latency, also called rotational delay, is the time required for the desired sector
of a disk to rotate under the read/write head, usually assumed
assumed to be half the rotation time.
9. What is direct-mapped
mapped cache?
Direct-mapped
mapped cache is a cache structure in which each memory location is mapped to
exactly one location in the cache. For example, almost all directmapped caches use
this mapping to find a block, (Block address) modulo (Number of blocks in the cache).
10. What are the writing strategies in cache memory?
Write-through
through is a scheme in which writes always update both the cache and the next
lower level of the memory hierarchy, ensuring that data
data is always consistent between the
two. Write-back
back is a scheme that handles writes by updating values only to the block in the
cache, then writing the modified block to the lower level of the hierarchy when the block is
replaced.
11. What are the various block placement schemes in cache memory?
Direct-mapped
mapped cache is a cache structure in which each memory location is mapped to
exactly one location in the cache. Fully associative cache is a cache structure in which a
block can be placed in any location in
i the cache. Set-associative
associative cache is a cache that has a
fixed number of locations (at least two
two) where each block can be placed.
A USB-A port refers to a port in a host device that allows it to connect with a receptor
device, either
ither through a USB cable or by plugging in the receptor device directly (as with a
USB flash drive). USB drives are commonly used for storage, data backup and
transferring files between devices.
devices. USB drives come in multiple storage capacities and
different
ent ports, each having a unique shape.
Serial communication transfers data one bit at a time, rather than in several parallel
streams.
Programmers want memory to be fast, large, and cheap. The hierarchical arrangeme
arrangement of
storage in current computer architectures is called the memory hierarchy.
PART-B