NCV5700

High Current IGBT Gate

Driver
The NCV5700 is a high−current, high−performance stand−alone
IGBT driver for high power applications that include solar inverters,
motor control and uninterruptable power supplies. The device offers a
cost−effective solution by eliminating many external components. www.onsemi.com
Device protection features include Active Miller Clamp, accurate
UVLO, EN input, DESAT protection and Active Low FAULT output.
MARKING
The driver also features an accurate 5.0 V output and separate high and DIAGRAM
low (VOH and VOL) driver outputs for system design convenience.
The driver is designed to accommodate a wide voltage range of bias
supplies including unipolar and bipolar voltages. It is available in a SOIC−16 NCV5700DR2G
D SUFFIX AWLYWW
16−pin SOIC package.
CASE 751B
Features
• High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages A = Assembly Location
• Low Output Impedance of VOH & VOL for Enhanced IGBT Driving WL = Wafer Lot
• Short Propagation Delays with Accurate Matching Y
WW
= Year
= Work Week
• Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer G = Pb−Free Package
for Isolated Drive, Logic Compatibility for Non−isolated Drive
• Active Miller Clamp to Prevent Spurious Gate Turn−on
PIN CONNECTIONS
• DESAT Protection with Programmable Delay
• Enable Input for Independent Driver Control EN 1 16 CLAMP

• Tight UVLO Thresholds for Bias Flexibility VIN 2 15 VEEA

• Wide Bias Voltage Range including Negative VEE Capability VREF 3 14 VEE
• NCV Prefix for Automotive and Other Applications Requiring FLT 4 13 GND
Unique Site and Control Change Requirements; AEC−Q100 GNDA 5 12 VOL
Qualified and PPAP Capable, Grade 1 NC 6 11 VOH
• This Device is Pb−Free, Halogen−Free and RoHS Compliant RSVD 7 10 VCC
Typical Applications NC 8 9 DESAT
• Motor Control
(Top View)
• Uninterruptible Power Supplies (UPS)
• Automotive Power Supplies
• HEV/EV Powertrain ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
• HEV/EV PTC Heaters this data sheet.

VREF DESAT

VCC VCC
EN
VOH
VOL
CLAMP
VIN GND
VEE VEE

FLT

Figure 1. Simplified Application Schematic

© Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:

September, 2017 − Rev. 0 NCV5700/D
 NCV5700

Q
SET
S
TSD
Q CLR R
VREF
FLT
I DESAT-CHG DELAY R EN-H
+
VDESAT-THR SET
Q
DESAT - S
EN
R CLR Q
VCC
VREF

RIN-H

VIN VOH

VOL
DELAY
Bandgap
VREF
VUVLO VEE
-
+
VCC S SET
Q

R CLR Q

-
+ VMC-THR CLAMP

GND VEE VEEA

Figure 2. Detailed Block Diagram

VREF
EN CLAMP
VREF
CLAMP
VIN VEEA

VCC

VREF LDO VEE

Logic Unit

FLT GND

GNDA VOL

NC VOH

TSD
RSVD VCC VCC

UVLO
NC DESAT DESAT

Figure 3. Simplified Block Diagram

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 NCV5700

Table 1. PIN FUNCTION DESCRIPTION

Pin Name No. I/O/x Description
EN 1 I Enable input allows additional gating of VOH and VOL, and can be used when the driver output
needs to be turned off independent of the Microcontroller input.

VIN 2 I Input signal to control the output. In applications which require galvanic isolation, VIN is generated
at the opto output, the pulse transformer secondary or the digital isolator output. There is a signal
inversion from VIN to VOH/VOL. VIN is internally clamped to 5.5 V and has a pull−up resistor of
1 MW to ensure that output is low in the absence of an input signal. A minimum pulse−width is re-
quired at VIN before VOH/VOL are activated.
VREF 3 O 5 V Reference generated within the driver is brought out to this pin for external bypassing and for
powering low bias circuits (such as digital isolators).

FLT 4 O Fault output (active low) that allows communication to the main controller that the driver has en-
countered a fault condition and has deactivated the output. Truth Table is provided in the datasheet
to indicate conditions under which this signal is asserted. Capable of driving optos or digital isolators
when isolation is required.
GNDA 5 x This pin provides a convenient connection point for bypass capacitors (e.g REF) on the left side of
the package.

NC 6,8 x Pins not internally connected.

RSVD 7 x Reserved. No connection is allowed.
DESAT 9 I Input for detecting the desaturation of IGBT due to a fault condition. A capacitor connected to this
pin allows a programmable blanking delay every ON cycle before DESAT fault is processed, thus
preventing false triggering.
VCC 10 x Positive bias supply for the driver. The operating range for this pin is from UVLO to the maximum. A
good quality bypassing capacitor is required from this pin to GND and should be placed close to the
pins for best results.
VOH 11 O Driver high output that provides the appropriate drive voltage and source current to the IGBT gate.
VOL 12 O Driver low output that provides the appropriate drive voltage and sink current to the IGBT gate. VOL
is actively pulled low during start−up and under Fault conditions.

GND 13 x This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors
should be referenced to this pin and kept at a short distance from the pin.

VEE 14 x A negative voltage with respect to GND can be applied to this pin and that will allow VOL to go to a
negative voltage during OFF state. A good quality bypassing capacitor is needed from VEE to GND.
If a negative voltage is not applied or available, this pin must be connected to GND.
VEEA 15 x Analog version of the VEE pin for any signal trace connection. VEE and VEEA are internally con-
nected.

CLAMP 16 I/O Provides clamping for the IGBT gate during the off period to protect it from parasitic turn−on. To be
tied directly to IGBT gate with minimum trace length for best results.

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 NCV5700

Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1)

Parameter Symbol Minimum Maximum Unit
Differential Power Supply VCC−VEE (Vmax) 0 36 V
Positive Power Supply VCC−GND −0.3 22 V
Negative Power Supply VEE−GND −18 0.3 V
Gate Output High VOH−GND VCC + 0.3 V
Gate Output Low VOL−GND VEE − 0.3 V
Input Voltage VIN−GND −0.3 5.5 V
Enable Voltage VEN−GND −0.3 5.5 V
DESAT Voltage VDESAT−GND −0.3 VCC + 0.3 V
FLT Current mA
Sink IFLT−SINK 20
Source IFLT−SRC 25
Power Dissipation PD mW
SO−16 package 900

Maximum Junction Temperature TJ(max) 150 °C

Storage Temperature Range TSTG −65 to 150 °C
ESD Capability, Human Body Model (Note 2) ESDHBM 4 kV
ESD Capability, Machine Model (Note 2) ESDMM 200 V
Moisture Sensitivity Level MSL 1 −
Lead Temperature Soldering Reflow TSLD 260 °C
(SMD Styles Only), Pb−Free Versions (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 125°C
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

Table 3. THERMAL CHARACTERISTICS

Parameter Symbol Value Unit
Thermal Characteristics, SOIC−16 (Note 4) °C/W
Thermal Resistance, Junction−to−Air (Note 5) RθJA 145
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.

Table 4. OPERATING RANGES (Note 6)

Parameter Symbol Min Max Unit
Differential Power Supply VCC−VEE (Vmax) 30 V
Positive Power Supply VCC UVLO 20 V
Negative Power Supply VEE −15 0 V
Input Voltage VIN 0 5 V
Enable Voltage VEN 0 5 V
Input Pulse Width ton 40 ns
Ambient Temperature TA −40 125 °C
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

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 NCV5700

Table 5. ELECTRICAL CHARACTERISTICS VCC = 15 V, VEE = 0 V, Kelvin GND connected to VEE. For typical values TA = 25°C,
for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Parameter Test Conditions Symbol Min Typ Max Unit
LOGIC INPUT and OUTPUT
Input Threshold Voltages Pulse−Width = 150 ns, VEN = 5 V V
High−state (Logic 1) Required Voltage applied to get output to go low VIN−H1 4.3
Low−state (Logic 0) Required Voltage applied to get output to go high VIN−L1 0.75
No state change Voltage applied without change in output state VIN−NC 1.2 3.7

Enable Threshold Voltages VIN = 0 V V

High−state Voltage applied to get output to go high VEN−H 4.3
Low−state Voltage applied to get output to go low VEN−L 0.75
Input/Enable Internal Pull−Up RIN−H/ 1 MW
Resistance to VREF REN−H

Input/Enable Current mA
High−state VIN−H/VEN−H = 4.5 V IIN−H/IEN−H 1
Low−state VIN−L/VEN−L = 0.5 V IIN−L/IEN−L 10
Input Pulse−Width Voltage thresholds consistent with input ns
No Response at the Output specs ton−min1 10
Guaranteed Response at the ton−min2 30
Output
FLT Threshold Voltage V
Low State (IFLT−SINK = 15 mA) VFLT−L 0.5 1.0
High State (IFLT−SRC = 20 mA) VFLT−H 12 13.9
DRIVE OUTPUT
Output Low State V
Isink = 200 mA, TA = 25°C VOL1 0.1 0.2
Isink = 200 mA, TA = −40°C to 125°C VOL2 0.2 0.5
Isink = 1.0 A, TA = 25°C VOL3 0.8 1.2

Output High State V

Isrc = 200 mA, TA = 25°C VOH1 14.5 14.8
Isrc = 200 mA, TA = −40°C to 125°C VOH2 14.2 14.7
Isrc = 1.0 A, TA = 25°C VOH3 13.8 14.1

Peak Driver Current, Sink RG = 0.1 W, VCC = 15 V, VEE = −8 V A

(Note 7) VO = 13 V IPK−snk1 6.8
VO = 9 V (near Miller Plateau) IPK−snk2 6.1
Peak Driver Current, Source RG = 0.1 W, VCC = 15 V, VEE = −8 V A
(Note 7) VO = −5 V IPK−src1 7.8
VO = 9 V (near Miller Plateau) IPK−src2 4.0
DYNAMIC CHARACTERISTICS
Turn−on Delay Negative input pulse width = 10 ms tpd−on 45 56 75 ns
(see timing diagram)

Turn−off Delay Positive input pulse width = 10 ms tpd−off 45 63 75 ns

(see timing diagram)

Propagation Delay Distortion For input or output pulse width > 150 ns, ns
(=tpd−on− tpd−off) TA = 25°C tdistort1 −15 −7 5
TA = −40°C to 125°C tdistort2 −25 25
Prop Delay Distortion between tdistort −tot −30 0 30 ns
Parts (Note 7)

Rise Time (Note 7) Cload = 1.0 nF trise 9.2 ns

(see timing diagram)

Fall Time (Note 7) Cload = 1.0 nF tfall 7.9 ns

(see timing diagram)
7. Values based on design and/or characterization.

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 NCV5700

Table 5. ELECTRICAL CHARACTERISTICS VCC = 15 V, VEE = 0 V, Kelvin GND connected to VEE. For typical values TA = 25°C,
for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Parameter Test Conditions Symbol Min Typ Max Unit
DYNAMIC CHARACTERISTICS
Delay from FLT under UVLO/ td1−OUT 9 12 15 ms
TSD to VOL

Delay from DESAT to VOL td2−OUT 220 ns

(Note 7)

Delay from UVLO/TSD to FLT td3−FLT 7.3 ms

(Note 7)

MILLER CLAMP
Clamp Voltage Isink = 500 mA, TA = 25°C Vclamp 1.2 1.4 V
Isink = 500 mA, TA = −40°C to 125°C 2.2
Clamp Activation Threshold VMC−THR 1.8 2.0 2.2 V
DESAT PROTECTION
DESAT Threshold Voltage VDESAT−THR 6.0 6.35 7.0 V
Blanking Charge Current IDESAT−CHG 0.20 0.24 0.28 mA
Blanking Discharge Current IDESAT−DIS 30 mA
UVLO
UVLO Startup Voltage VUVLO−OUT−ON 13.2 13.5 13.8 V
UVLO Disable Voltage VUVLO−OUT−OFF 12.2 12.5 12.8 V
UVLO Hysteresis VUVLO−HYST 1.0 V
VREF
Voltage Reference IREF = 10 mA VREF 4.85 5.00 5.15 V
Reference Output Current IREF 20 mA
(Note 7)

Recommended Capacitance CVREF 100 nF

SUPPLY CURRENT
Current Drawn from VCC VCC = 15 V ICC−SB 0.9 1.5 mA
Standby (No load on output, FLT, VREF)

Current Drawn from VEE VEE = −10 V IEE−SB −0.2 −0.14 mA

Standby (No load on output, FLT, VREF)

THERMAL SHUTDOWN
Thermal Shutdown Temperature TSD 188 °C
(Note 7)

Thermal Shutdown Hysteresis TSH 33 °C

(Note 7)

7. Values based on design and/or characterization.

ORDERING INFORMATION
Device Package Shipping†
NCV5700DR2G SO−16 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 NCV5700

TYPICAL CHARACTERISTICS

80 80

ENABLE TO OUTPUT LOW DELAY (ns)

PROPAGATION DELAY (ns)

70 70

tpd−off

60 60

tpd−on

50 50

40 40
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 4. Propagation Delay vs. Temperature Figure 5. Enable to Output Low Delay

15 20
FAULT TO OUTPUT DELAY (ms)

14
15
RISE/FALL TIME (ns)

13
tfall
10
12
trise
5
11

10 0
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 6. Fault to Output Low Delay Figure 7. Output Rise/Fall Time

8 8

7 7

6 6

5 5
IO (A)

IO (A)

4 4

3 3

2 2

1 1
0 0
−5 0 5 10 15 −5 0 5 10 15
VO (V, VCC = 15 V, VEE = −8 V) VO (V, VCC = 15 V, VEE = −8 V)
Figure 8. Output Source Current vs. Output Figure 9. Output Sink Current vs. Output
Voltage Voltage

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 NCV5700

TYPICAL CHARACTERISTICS

5.05 5.05
5.04 5.04
5.03 5.03
5.02 5.02
5.01 5.01 VREF @ IREF = 0 mA
VREF (V)

VREF (V)
5.00 5.00
4.99 4.99
4.98 4.98
VREF @ IREF = 10 mA
4.97 4.97
4.96 4.96
4.95 4.95
0 2 4 6 8 10 −40 −20 0 20 40 60 80 100 120
IREF (mA) TEMPERATURE (°C)
Figure 10. VREF Voltage vs. Current Figure 11. VCLAMP at 0.5 A

260 6.5
IDESET−CHG (mA)

6.4
VDESAT (V)

250

6.3

240 6.2
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 12. DESAT Charge Current vs. Figure 13. DESAT Threshold Voltage vs.
Temperature Temperature

15 20
VO, OUTPUT VOLTAGE (V)

15

10
10
VO (V)

UVLO−OUT−OFF UVLO−OUT−ON 5
5

0 −5
10 11 12 13 14 15 0 1 2 3 4 5
VCC, SUPPLY VOLTAGE (V) VIN (V)
Figure 14. UVLO Threshold Voltages Figure 15. VO vs. VIN at 255C
(VCC = 15 V, VEE = 0 V)

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 NCV5700

TYPICAL CHARACTERISTICS

15 1.0
VFLT−H (V)

VFLT−L (V)
14 0.5

13 0
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 16. Fault Output, Sourcing 20 mA Figure 17. Fault Output, Sinking 15 mA

2.5 1.4

1.2
ICC
SUPPLY CURRENT (mA)

2.0
1.0
VCLAMP (V)

0.8
1.5
0.6

0.4
1.0
IEE
0.2

0.5 0
−40 −20 0 20 40 60 80 100 120 0 20 40 60 80 100
TEMPERATURE (°C) FREQUENCY (kHz)
Figure 18. VCLAMP at 0.5 A Figure 19. Supply Current vs. Switching
Frequency (VCC = 15 V, VEE = −10 V, 255C)

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 NCV5700

Applications and Operating Information

This section lists the details about key features and

operating guidelines for the NCV5700.

High Drive Current Capability

The NCV5700 driver family is equipped with many
features which facilitate a superior performance IGBT
driving circuit. Foremost amongst these features is the high
drive current capability. The drive current of an IGBT driver
is a function of the differential voltage on the output pin
(VCC−VOH for source current, VOL−VEE for sink current)
as shown in Figure 20. Figure 20 also indicates that for a
given VOH/VOL value, the drive current can be increased
by using higher VCC/VEE power supply). The drive current
Figure 20. Output Current vs. Output Voltage Drop
tends to drop off as the output voltage goes up (for turn−on
event) or goes down (for turn−off event). As explained in
When driving larger IGBTs for higher current
many IGBT application notes, the most critical phase of
applications, the drive current requirement is higher, hence
IGBT switching event is the Miller plateau region where the
lower RG is used. Larger IGBTs typically have high input
gate voltage remains constant at a voltage (typically in 9−11
capacitance. On the other hand, if the NCV5700 is used to
V range depending on IGBT design and the collector
drive smaller IGBT (lower input capacitance), the drive
current), but the gate drive current is used to
current requirement is lower and a higher RG is used. Thus,
charge/discharge the Miller capacitance (CGC). By
for most typical applications, the driver load RC time
providing a high drive current in this region, a gate driver can
constant remains fairly constant. Caution must be exercised
significantly reduce the duration of the phase and help
when using the NCV5700 with a very low load RC time
reducing the switching losses. The NCV5700 addresses this
constant. Such a load may trigger internal protection
requirement by providing and specifying a high drive
circuitry within the driver and disable the device. Figure 21
current in the Miller plateau region. Most other gate driver
shows the recommended minimum gate resistance as a
ICs merely specify peak current at the start of switching –
function of IGBT gate capacitance and gate drive trace
which may be a high number, but not very relevant to the
inductance.
application requirement. It must be remembered that other
considerations such as EMI, diode reverse recovery
performance, etc., may lead to a system level decision to
trade off the faster switching speed against low EMI and
reverse recovery. However, the use of NCV5700 does not
preclude this trade−off as the user can always tune the drive
current by employing external series gate resistor. Important
thing to remember is that by providing a high internal drive
current capability, the NCV5700 facilitates a wide range of
gate resistors. Another value of the high current at the Miller
plateau is that the initial switching transition phase is shorter
and more controlled. Finally, the high gate driver current
(which is facilitated by low impedance internal FETs),
ensures that even at high switching frequencies, the power
dissipation from the drive circuit is primarily in the external Figure 21. Recommended Minimum Gate Resistance
series resistor and more easily manageable. Experimental as a Function of IGBT Gate Capacitance
results have shown that the high current drive results in
reduced turn−on energy (EON) for the IGBT switching.

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 NCV5700

Gate Voltage Range controller to initiate a more orderly/sequenced shutdown. In

The negative drive voltage for gate (with respect to GND, case the controller fails to do so, the driver output shutdown
or Emitter of the IGBT) is a robust way to ensure that the gate ensures IGBT protection after td1−OUT.
voltage does not rise above the threshold voltage due to the
Miller effect. In systems where the negative power supply is
available, the VEE option offered by NCV5700 allows not
only a robust operation, but also a higher drive current for
turn−off transition. Adequate bypassing between VEE pin
and GND pin is essential if this option is used.
The VCC range for the NCV5700 is quite wide and allows
the user the flexibility to optimize the performance or use
available power supplies for convenience.

Under Voltage Lock Out (UVLO)

This feature ensures reliable switching of the IGBT
connected to the driver output. At the start of the driver’s
operation when VCC is applied to the driver, the output
remains turned−off. This is regardless of the signals on VIN
until the VCC reaches the UVLO Output Enabled
(VUVLO−OUT−ON) level. After the VCC rises above the
VUVLO−OUT−ON level, the driver is in normal operation. The
state of the output is controlled by signal at VIN.
If the VCC falls below the UVLO Output Disabled
(VUVLO−OUT−OFF) level during the normal operation of the
driver, the Fault output is activated and the output is shut−down
(after a delay) and remains in this state. The driver output
does not start to react to the input signal on VIN until the VCC
Figure 22. UVLO Function and Limits
rises above the VUVLO−OUT−ON again. The waveform
showing the UVLO behavior of the driver is in Figure 22.
In an IGBT drive circuit, the drive voltage level is Timing Delays and Impact on System Performance
important for drive circuit optimization. If VUVLO−OUT−OFF The gate driver is ideally required to transmit the input
is too low, it will lead to IGBT being driven with insufficient signal pulse to its output without any delay or distortion. In
gate voltage. A quick review of IGBT characteristics can the context of a high−power system where IGBTs are
reveal that driving IGBT with low voltage (in 10−12 V typically used, relatively low switching frequency (in tens of
range) can lead to a significant increase in conduction loss. kHz) means that the delay through the driver itself may not
So, it is prudent to guarantee VUVLO−OUT−OFF at a be as significant, but the matching of the delay between
reasonable level (above 12 V), so that the IGBT is not forced different drivers in the same system as well as between
to operate at a non−optimum gate voltage. On the other hand, different edges has significant importance. With reference to
having a very high drive voltage ends up increasing Figure 23(a), two input waveforms are shown. They are
switching losses without much corresponding reduction in typical complementary inputs for high−side (HS) and
conduction loss. So, the VUVLO−OUT−ON value should not low−side (LS) of a half−bridge switching configuration. The
be too high (generally, well below 15 V). These conditions dead−time between the two inputs ensures safe transition
lead to a tight band for UVLO enable and disable voltages, between the two switches. However, once these inputs are
while guaranteeing a minimum hysteresis between the two through the driver, there is potential for the actual gate
values to prevent hiccup mode operation. The NCV5700 voltages for HS and LS to be quite different from the
meets these tight requirements and ensures smooth IGBT intended input waveforms as shown in Figure 23(a). The end
operation. It ensures that a 15 V supply with ±8% tolerance result could be a loss of the intended dead−time and/or
will work without degrading IGBT performance, and pulse−width distortion. The pulse−width distortion can
guarantees that a fault will be reported and the IGBT will be create an imbalance that needs to be corrected, while the loss
turned off when the supply voltage drops below 12.2 V. of dead−time can eventually lead to cross−conduction of the
A UVLO event (VCC voltage going below VUVLO−OUT−OFF) switches and additional power losses or damage to the
also triggers activation of FLT output after a delay of td3−FLT. system.
This indicates to the controller that the driver has The NCV5700 driver is designed to address these timing
encountered an issue and corrective action needs to be taken. challenges by providing a very low pulse−width distortion
However, a nominal delay td1−OUT = 12 ms is introduced and excellent delay matching. As an example, the delay
between the initiation of the FLT output and actual turning matching is guaranteed to tDISTORT2 = ±25 ns while many
off of the output. This delay provides adequate time for the of competing driver solutions can be >250 ns.

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 NCV5700

Figure 23(a). Timing Waveforms (Other Drivers) Figure 23(b). NCV5700 Timing Waveforms

Active Miller Clamp Protection An alternative way is to provide an additional path from
This feature is a cost savvy alternative to a negative gate gate to GND with very low impedance. This is exactly what
voltage. The main requirement is to hold the gate of the Active Miller Clamp protection does. Additional trace from
turned−off (for example low−side) IGBT below the the gate of the IGBT to the Clamp pin of the gate driver is
threshold voltage during the turn−on of the opposite−side (in introduced. After the VO output has gone below the Active
this example high−side) IGBT in the half bridge. The Miler Clamp threshold VMC−THR the Clamp pin is shorted
turn−on of the high−side IGBT causes high dv/dt transition to GND and thus prevents the voltage on the gate of the
on the collector of the turned−off low−side IGBT. This high IGBT to rise above the threshold voltage as shown in
dv/dt then induces current (Miller current) through the CGC Figure 25. The Clamp pin is disconnected from GND as
capacitance (Miller capacitance) to the gate capacitance of soon as the signal to turn on the IGBT arrives to the gate
the low−side IGBT as shown in Figure 24. If the path from driver input. The fact that the Clamp pin is engaged only
gate to GND has critical impedance (caused by RG) the after the gate voltage drops below the VMC−THR threshold
Miller current could rise the gate voltage above the threshold ensures that the function of this pin does not interfere with
level. As a consequence the low−side IGBT could be turned the normal turn−off switching performance that is user
on for a few tens or hundreds of nanoseconds. This causes controllable by choice of RG.
higher switching losses. One way to avoid this situation is to
use negative gate voltage, but this requires second DC
source for the negative gate voltage.

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 NCV5700

Figure 24. Current Path without Miller Clamp Figure 25. Current Path with Miller Clamp Protection
Protection

Desaturation Protection (DESAT) At the turned−on output state of the driver, the current
This feature monitors the collector−emitter voltage of the IDESAT−CHG from current source starts to flow to the
IGBT in the turned−on state. When the IGBT is fully turned blanking capacitor CBLANK, connected to DESAT pin.
on, it operates in a saturation region. Its collector−emitter Appropriate value of this capacitor has to be selected to
voltage (called saturation voltage) is usually low, well below ensure that the DESAT pin voltage does not rise above the
3 V for most modern IGBTs. It could indicate an overcurrent threshold level VDESAT−THR before the IGBT fully turns on.
or similar stress event on the IGBT if the collector−emitter The blanking time is given by following expression.
voltage rises above the saturation voltage, after the IGBT is According to this expression, a 47 pF CBLANK will provide
fully turned on. Therefore the DESAT protection circuit a blanking time of (47p *6.5/0.25m =) 1.22 ms.
compares the collector−emitter voltage with a voltage level V DESAT−THR
VDESAT−THR to check if the IGBT didn’t leave the saturation t BLANK + C BLANK @
I DESAT−CHG
region. It will activate FLT output and shut down driver
output (thus turn−off the IGBT), if the saturation voltage After the IGBT is fully turned−on, the IDESAT−CHG flows
rises above the VDESAT−THR. This protection works on through the DESAT pin to the series resistor RS−DESAT and
every turn−on phase of the IGBT switching period. through the high voltage diode and then through the
At the beginning of turning−on of the IGBT, the collector and IGBT to the emitter. Care must be taken to
collector−emitter voltage is much higher than the saturation select the resistor RS−DESAT value so that the sum of the
voltage level which is present after the IGBT is fully turned saturation voltage, drop on the HV diode and drop on the
on. It takes almost 1 ms between the start of the IGBT turn−on RS−DESAT caused by current IDESAT−CHG flowing from
and the moment when the collector−emitter voltage falls to DESAT source current is smaller than the DESAT threshold
the saturation level. Therefore the comparison is delayed by voltage. Following expression can be used:
a configurable time period (blanking time) to prevent false V DESAT−THR u
triggering of DESAT protection before the IGBT R S−DESAT @ I DESAT−CHG ) V F_HV diode ) V CESAT_IGBT
collector−emitter voltage falls below the saturation level.
Blanking time is set by the value of the capacitor CBLANK. Important part for DESAT protection to work properly is
The exact principle of operation of DESAT protection is the high voltage diode. It must be rated for at least same
described with reference to Figure 26. voltage as the low side IGBT. The safety margin is
At the turned−off output state of the driver, the DESAT pin application dependent.
is shorted to ground via the discharging transistor (QDIS). The typical waveforms for IGBT overcurrent condition
Therefore, the inverting input holds the comparator output are outlined in Figure 27.
at low level.

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13
 NCV5700

Figure 26. Desaturation Protection Schematic

Figure 27. Desaturation Protection Waveforms

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14
 NCV5700

Input Signal
The input signal controls the gate driver output. Figure 28 applications where the input is coming through an
shows the typical connection diagrams for isolated opto−coupler or a pulse transformer.

Figure 28. Opto−coupler or Pulse Transformer At Input

The relationship between gate driver input signal from a delay times are defined from 50% of input transition to first
pulse transformer (Figure 29) or opto−coupler (Figure 30) 10% of the output transition to eliminate the load
and the output is defined by many time and voltage values. dependency. The input voltage parameters include input
The time values include output turn−on and turn−off delays high (VIN−H1) and low (VIN−L1) thresholds as well as the
(tpd−on and tpd−off), output rise and fall times (trise and tfall) input range for which no output change is initiated
and minimum input pulse−width (ton−min). Note that the (VIN−NC).

VIN−H1

VIN−NC

VIN

VIN−L1

tpd−off trise
tfall tpd−on ton−min

VOUT
90%

10%

Figure 29. Input and Output Signal Parameters for Pulse Transformer

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15
 NCV5700

VIN−H1

VIN−NC
VIN
VIN−L1
tpd−off trise ton−min
tfall tpd−on

VOUT 90%

10%

Figure 30. Input and Output Signal Parameters for Opto−coupler

Use of VREF Pin

The NCV5700 provides an additional 5.0 V output highly stable over temperature and line/load variations (see
(VREF) that can serve multiple functions. This output is characteristics curves for details)
capable of sourcing up to 10 mA current for functions such
as opto−coupler interface or external comparator interface. Fault Output Pin
The VREF pin should be bypassed with at least a 100 nF This pin provides the feedback to the controller about the
capacitor (higher the better) irrespective of whether it is driver operation. The situations in which the FLT signal
being utilized for external functionality or not. VREF is becomes active (low value) are summarized in the Table 6.

Table 6. FLT LOGIC TRUTH TABLE

VIN ENABLE UVLO DESAT Internal TSD VOUT FLT Notes
L H Inactive L L H H Normal operation − Output High
H H Inactive L L L H Normal operation − Output Low
X L Inactive X L L H Disabled − Output Low, FLT High
X X Active X L L L UVLO activated − FLT Low (td3-FLT),
Output Low (td3-FLT + td1−OUT)
L H Inactive H L L L DESAT activated (only when VIN is low)
− Output Low (td2_OUT), FLT Low

X X Inactive X H L L Internal Thermal Shutdown − FLT Low

(td3-FLT ), Output Low (td3-FLT + td1−OUT)

Thermal Shutdown
The NCV5700 also offers thermal shutdown function that Additional Use of Enable Pin
is primarily meant to self−protect the driver in the event that For some applications, Enable is a useful feature as it
the internal temperature gets excessive. Once the provides the ability to shut down the power stage without
temperature crosses the TSD threshold, the FLT output is involving the controls such as DSP. It can also be used along
activated after a delay of td3-FLT. After a delay of td1−OUT with the VREF pin and a comparator to provide local
(12 ms), the output is pulled low and many of the internal shutdown protection at fault conditions such as over
circuits are turned off. The 12 ms delay is meant to allow the temperature or over current, as illustrated in Figure 31.
controller to perform an orderly shutdown sequence as
appropriate. Once the temperature goes below the second
threshold, the part becomes active again.

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 NCV5700

+V
VREF
Vcc
DESAT
VIN
-
NCV5700
EN
+
VOH
VREF
OT OC VOL
GND FLT VEE
VEEA
-V
CLAMP CT
GND

GND
GND

Figure 31. Additional Over Temperature and/or Over Current Shutdown Protection

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17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−16
CASE 751B−05
ISSUE K
SCALE 1:1 DATE 29 DEC 2006

−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
−B− P 8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
1 8
0.25 (0.010) M B S SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F
K R X 45 _
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
C K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
−T− SEATING P 5.80 6.20 0.229 0.244
PLANE
M J R 0.25 0.50 0.010 0.019
D 16 PL

0.25 (0.010) M T B S A S

STYLE 1: STYLE 2: STYLE 3: STYLE 4:

PIN 1. COLLECTOR PIN 1. CATHODE PIN 1. COLLECTOR, DYE #1 PIN 1. COLLECTOR, DYE #1
2. BASE 2. ANODE 2. BASE, #1 2. COLLECTOR, #1
3. EMITTER 3. NO CONNECTION 3. EMITTER, #1 3. COLLECTOR, #2
4. NO CONNECTION 4. CATHODE 4. COLLECTOR, #1 4. COLLECTOR, #2
5. EMITTER 5. CATHODE 5. COLLECTOR, #2 5. COLLECTOR, #3
6. BASE 6. NO CONNECTION 6. BASE, #2 6. COLLECTOR, #3
7. COLLECTOR 7. ANODE 7. EMITTER, #2 7. COLLECTOR, #4
8. COLLECTOR 8. CATHODE 8. COLLECTOR, #2 8. COLLECTOR, #4
9. BASE 9. CATHODE 9. COLLECTOR, #3 9. BASE, #4
10. EMITTER 10. ANODE 10. BASE, #3 10. EMITTER, #4
11. NO CONNECTION 11. NO CONNECTION 11. EMITTER, #3 11. BASE, #3
12. EMITTER 12. CATHODE 12. COLLECTOR, #3 12. EMITTER, #3
13. BASE 13. CATHODE 13. COLLECTOR, #4 13. BASE, #2 RECOMMENDED
14.
15.
COLLECTOR
EMITTER
14.
15.
NO CONNECTION
ANODE
14.
15.
BASE, #4
EMITTER, #4
14.
15.
EMITTER, #2
BASE, #1
SOLDERING FOOTPRINT*
16. COLLECTOR 16. CATHODE 16. COLLECTOR, #4 16. EMITTER, #1 8X
6.40
STYLE 5: STYLE 6: STYLE 7:
PIN 1. DRAIN, DYE #1 PIN 1. CATHODE PIN 1. SOURCE N‐CH 16X 1.12
2. DRAIN, #1 2. CATHODE 2. COMMON DRAIN (OUTPUT)
3. DRAIN, #2 3. CATHODE 3. COMMON DRAIN (OUTPUT) 1 16
4. DRAIN, #2 4. CATHODE 4. GATE P‐CH
5. DRAIN, #3 5. CATHODE 5. COMMON DRAIN (OUTPUT)
6. DRAIN, #3 6. CATHODE 6. COMMON DRAIN (OUTPUT) 16X
7. DRAIN, #4 7. CATHODE 7. COMMON DRAIN (OUTPUT) 0.58
8. DRAIN, #4 8. CATHODE 8. SOURCE P‐CH
9. GATE, #4 9. ANODE 9. SOURCE P‐CH
10. SOURCE, #4 10. ANODE 10. COMMON DRAIN (OUTPUT)
11. GATE, #3 11. ANODE 11. COMMON DRAIN (OUTPUT)
12. SOURCE, #3 12. ANODE 12. COMMON DRAIN (OUTPUT)
13. GATE, #2 13. ANODE 13. GATE N‐CH
14. SOURCE, #2 14. ANODE 14. COMMON DRAIN (OUTPUT)
1.27
15. GATE, #1 15. ANODE 15. COMMON DRAIN (OUTPUT) PITCH
16. SOURCE, #1 16. ANODE 16. SOURCE N‐CH

8 9

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and sol-

dering details, please download the onsemi Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42566B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−16 PAGE 1 OF 1

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