ETA6953

I2C Controlled 13.5V/3A, 1-Cell Battery Charger with Power Path Management
DESCRIPTION FEATURES
The ETA6953 is a highly-integrated 3.0-A switch-mode battery  High-Efficiency, 1.5MHz, Synchronous Switching Buck
charge management and system power path management Charger
device for single cell Li-Ion and Li-polymer battery. It features fast  90% Charge Efficiency at 2A from 5V Input

charging with high input voltage support for a wide range of smart  Programmable PFM Mode for Light Load Conditions

phones, tablets and portable devices. Its low impedance power  Supports USB On-The-Go (OTG)
path optimizes switch-mode operation efficiency, reduces battery  Programmable Current Limit Boost Converter with

charging time and extends battery life during discharging phase. Up to 1.2A Output
Its input voltage and current regulation deliver maximum charging  91% Boost Efficiency at 1A Output

power to battery. The solution is highly integrated with input  Output Short Circuit Protection

reverse-blocking FET (RBFET, Q1), high-side switching FET  Programmable PFM Mode for Light Load Conditions

(HSFET, Q2), low-side switching FET (LSFET, Q3), and battery  Wide Range Single Input to Support both USB Input and
FET (BATFET, Q4) between system and battery. It also High Voltage Adapters
integrates the bootstrap diode for the high-side gate drive for  Support 3.9V to 13.5V Input Voltage Range With

simplified system design. The I2C serial interface with charging 30V Absolute Maximum Input Voltage Rating
and system settings makes the device a truly flexible solution.  Programmable Input Current Limit (100mA to 3.2A

With 100mA Resolution) to Support USB 2.0, USB

The device supports a wide range of input sources: standard USB 3.0 Standards and High Voltage Adaptors (IINDPM)
host port, USB charging port, and USB compliant high voltage  High Battery Discharge Efficiency With 27mΩ Battery
adapter. To support fast charging using high voltage adapter, the Discharge MOSFET
ETA6953 provides PSEL pin for USB switch control. To set the  Narrow VDC (NVDC) Power Path Management
default input current limit, device takes the result from detection  BATFET Control to Support Ship Mode, Wake Up and Full
circuit in the system, such as USB PHY device. The device is System Reset
compliant with USB 2.0 and USB 3.0 power spec with input  Flexible Autonomous and I2C Mode for Optimal System
current and voltage regulation. The device also meets USB On- Performance
the-Go (OTG) operation power rating specification by supplying  High Integration Includes All MOSFETs, Current Sensing
5.15 V on VBUS with constant current limit up to 1.2-A. and Loop Compensation
 26uA Low Battery Leakage Current to Support Ship Mode
The power path management regulates the system slightly above  Safety
battery voltage but does not drop below 3.5 V minimum system  Battery Temperature Sensing for Charge and Boost

voltage (programmable). With this feature, the system maintains Mode

operation even when the battery is completely depleted or  Thermal Regulation and Thermal Shutdown

removed. When the input current limit or voltage limit is reached,  Input UVLO and Overvoltage Protection
the power path management automatically reduces the charge
current to zero. As the system load continues to increase, the
power path discharges the battery until the system power APPLICATIONS
requirement is met. This Supplement Mode prevents overloading  Tablet PC, Smart Phone, Internet Devices
the input source.  Portable Audio Speaker
 Handheld Computers, PDA, POS
The ETA6953 is available in a QFN4x4-24L package.

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ETA6953
TYPICAL APPLICATION

1 VAC BST 21
VBUS
24 VBUS SW 19
VSYS
VIO 23 PMID SW 20

SYS 15
7 nINT
SYS 16
3 nPG
ETA 6953 STAT 4
HOST
6 SDA
BAT 13
5 SCL
BAT 14
9 nCE
VLDO 22
USB
2 PSEL
PHY
12 nQON TS 11
GND GND
17 18

ORDERING INFORMATION PART No. PACKAGE TOP MARK Pcs/Reel

ETA6953Q4Y QFN4x4-24 ETA6953 5000
YWW2L

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

(Note: Exceeding these limits may damage the device. Exposure to absolute maximum rating
conditions for long periods may affect device reliability.)
VBUS

VLDO
PMID

BST

SW

SW

24 23 22 21 20 19 VAC, VBUS, PMID to GND Voltage .........................–2V to 30V

SW to GND Voltage...............................................–0.3V to 20V
VAC 1 18 GND
nPG, STAT to GND Voltage ..................................–0.3V to 12V
PSEL 2 17 GND
SYS, BAT to GND Voltage.......................................–0.3V to 6V
nPG 3 16 SYS BST to SW Voltage .................................................–0.3V to 6V
STAT 4
ETA6953 15 SYS All Other Pin to GND Voltage................................. –0.3V to 6V
SCL 5 14 BAT SW, VBUS, BAT, SYS to PGND current...........Internally limited
GND Operating Temperature Range...........................–40°C to 85°C
SDA 6 13 BAT
Storage Temperature Range............................–55°C to 150°C
7 8 9 10 11 12 Thermal Resistance θJA θJC
QFN4x4–24pin...................35................10...................... °C/W
TS
nINT

nCE

NC
NC

nQON

Lead Temperature (Soldering,10sec) .............................260°C

QFN4 x 4 - 24

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ETA6953
ELECTRICAL CHARACTERISTICS
(Vbat = 3.6V, unless otherwise specified. Typical values are at TA = 25°C.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

QUIESCENT CURRENTS
Battery discharge current (BAT, SW, SYS) VBAT = 4.5V, VVBUS < VBUS-UVLOZ,
5 µA
in buck mode leakage between BAT and VBUS, TJ< 85°C
VBAT = 4.5V, HIZ Mode and BATFET_DIS = 1 or
Battery discharge current (BAT) in buck
No VBUS, I2C disabled, BATFET Disabled. 26 50 µA
mode
TJ < 85°C
VBAT = 4.5V, HIZ Mode and OVPFET_DIS = 1
Battery discharge current (BAT, SW, SYS) or No VBUS, I2C Disabled, BATFET Enabled. 100 180 µA
TJ < 85°C
VVBUS > VBUS_UVLO, VBUS > VBAT, converter
Input supply current (VBUS) in buck mode 5 mA
switching, VBAT = 3.8V, ISYS = 0A
VBAT = 4.2V, boost mode, IVBUS = 0A, converter
Battery Discharge Current in boost mode 2 mA
switching
VBUS, VAC AND BAT PIN POWER-UP
VBUS operating range VVBUS rising 3.9 13.5 V
VBUS for active I2C, no battery Sense
VVBUS rising 3.3 3.6 V
VBUS pin voltage
I2C active hysteresis VVBUS falling from above VVBUS_UVLO 300 mV
One of the conditions to turn on VLDO VVBUS rising 3.65 3.9 V
One of the conditions to turn on VLDO VVBUS falling 500 mV
(VVBUS–VBAT ), VBUSMIN_FALL ≤ VBAT ≤ VREG, VVBUS
Sleep mode falling threshold 15 60 110 mV
falling
(VVAC–VVBAT ), VBUSMIN_FALL ≤ VBAT
Sleep mode rising threshold 110 220 330 mV
≤ VREG, VAC rising
VBUS 6.5V Overvoltage rising threshold VVBUS rising, OVP<1:0> = '01’ 6 6.5 7 V
VBUS 11V Overvoltage rising threshold VVBUS rising, OVP<1:0> = '10' 10 11 12 V
VBUS 14V Overvoltage rising threshold VVBUS rising, OVP<1:0> = '11' 13 14 15 V
VBUS 6.5V Overvoltage hysteresis VVBUS falling, OVP<1:0> = '01’ 220 mV
VAC 11V Overvoltage hysteresis VVBUS falling, OVP<1:0> = '10' 400 mV
VAC 14V Overvoltage hysteresis VVBUS falling, OVP<1:0> = '11' 500 mV
BAT for active I2C, no adapter VBAT rising 2.5 2.7 V
Battery Depletion Threshold VBAT falling 2.2 2.4 2.6 V
Battery Depletion Threshold VBAT rising 2.35 2.58 2.8 V
Battery Depletion rising hysteresis VBAT rising 180 mV
Bad adapter detection falling threshold VBUS falling 3.7 3.9 4.1 V
Bad adapter detection hysteresis 80 mV
Bad adapter detection current source Sink current from VBUS to GND 30 mA

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ETA6953
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER-PATH
VBAT < SYS_MIN[2:0] = 101,
System regulation voltage 3.68 V
BATFET Disabled (REG07[5] = 1)
ISYS = 0A, VBAT > VSYS_MIN, VBAT = 4.400V, VBAT+7
System Regulation Voltage
BATFET disabled (REG07[5] = 1) 0mV
ISYS = 0A, Q4 off, VBAT≤ 4.400V,
Maximum DC system voltage output 4.47 V
VBAT > VSYSMIN = 3.5V
Top reverse blocking MOSFET on-
-40°C≤ TA ≤ 125°C 20 40 60 mΩ
resistance between VBUS and PMID - Q1
Top switching MOSFET on-
VVLDO = 5 V , -40°C≤ TA ≤ 125°C 35 70 105 mΩ
resistance between PMID and SW - Q2
Bottom switching MOSFET on-resistance
VVLDO = 5 V , -40°C≤ TA ≤ 125°C 21 43 65 mΩ
between SW and GND - Q3
QFN package, Measured from BAT
SYS-BAT MOSFET on-resistance – Q4 13 27 40 mΩ
to SYS, VBAT = 4.2V, TJ = –40 - 125°C
BATFET forward voltage in supplement
30 mV
mode
BATTERY CHARGER
Change voltage program range 3.856 4.624 V
Charge voltage step 32 mV
VREG (REG04[7:3]) = 4.208 V
Charge voltage setting 4.187 4.208 4.229 V
(01011), V, –40 ≤ TJ ≤ 85°C
VBAT = 4.208 V or VBAT = 4.352 V,
Charge voltage setting accuracy -0.5 +0.5 %
–40 ≤ TJ ≤ 85°C
Charge current regulation range 0 3000 mA
Charge current regulation step 60 mA
Charge current regulation setting ICHG = 1980mA, VVBAT = 3.1V or VVBAT = 3.8V 1980 mA
Charge current regulation accuracyICHG = 1980mA, VVBAT = 3.1V or VVBAT = 3.8V -10 +10 %
Battery LOWV falling threshold ICHG = 1980mA 2.6 2.8 3 V
Battery LOWV rising threshold Pre-charge to fast charge 2.9 3.1 3.3 V
Precharge current regulation IPRECHG[3:0] = '0010' = 180mA 144 180 216 mA
ICHG >780 mA, ITERM[3:0] = '0010'
Termination current regulation 144 180 216 mA
VVBAT = 4.208V
Battery short voltage VVBAT falling 1.8 2 2.2 V
Battery short voltage VVBAT rising 2.05 2.25 2.45 V
Battery short current VVBAT =1V 145 mA
Recharge Threshold below VBAT_REG VBAT falling, REG04[0] = 0 70 120 170 mV
Recharge Threshold below VBAT_REG VBAT falling, REG04[0] = 1 190 240 290 mV
INPUT VOLTAGE AND CURRENT REGULATION
Input voltage regulation limit VINDPM[3:0] = 0110 = 4.5 V 4.32 4.5 4.68 V

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ETA6953
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input voltage regulation accuracy -4 4 %
Input voltage regulation limit tracking VINDPM[3:0] = 3.9V, VDPM_VBAT_TRACK =
4.13 4.3 4.47 V
VBAT 300mV, VBAT = 4.0V
VVBUS = 5V, current pulled from SW,
USB input current regulation limit IINDPM [4:0] = 10111 = 2.4 A, 2.16 2.4 2.64 A
–40 ≤ TJ ≤ 85°C
Input current limit during system start-up
200 mA
sequence
BAT PIN OVERVOLTAGE PROTECTION
Battery overvoltage threshold VBAT rising, as percentage of VBAT_REG 108 %
Battery overvoltage threshold Hysteresis VBAT falling, as percentage of VBAT_REG 103 %
THERMAL REGULATION AND THERMAL SHUTDOWN
Junction Temperature Regulation
Temperature Increasing, TREG = 1 110 °C
Threshold
Junction Temperature Regulation
Temperature Increasing, TREG = 0 90 °C
Threshold
Thermal Shutdown Rising Temperature 160 °C
Thermal Shutdown Hysteresis 30 °C
JEITA Thermistor Comparator (BUCK MODE)
T1 (0°C) threshold, Charge suspended T1 Charger suspends charge. As Percentage to
73.3 %
below this temperature. VLDO
Falling As Percentage to VLDO 71.5 %
T2 (10°C) threshold, Charge back to
As Percentage to VLDO 68 %
ICHG/2 and 4.2 V below this temperature
Falling As Percentage to VLDO 66.8 %
T3 (45°C) threshold, charge back to ICHG Charger suspends charge. As Percentage to
44.7 %
and 4.05V above this temperature. VLDO
Falling As Percentage to VLDO 45.7
T5 (60°C) threshold, charge suspended
As Percentage to VLDO 34.2 %
above this temperature.
Falling As Percentage to VLDO 35.3 %
COLD OR HOT THERMISTER COMPARATOR (BOOST MODE)
Cold Temperature Threshold, TS pin As Percentage to VLDO (Approx. -20°C w/
78 80.0 82 %
Voltage Rising Threshold 103AT), TJ = –20°C - 125°C
Falling TJ = –20°C - 125°C 77 79.0 81 %
Hot Temperature Threshold, TS pin As Percentage to VLDO (Approx. 60°C w/
29.2 31.2 33.2 %
Voltage falling Threshold 103AT), TJ = –20°C - 125°C
Rising TJ = –20°C - 125°C 32.4 34.4 36.4 %
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)

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ETA6953
PARAMETER CONDITIONS MIN TYP MAX UNITS
HSFET cycle-by-cycle over-current
4.8 5.8 7.5 A
threshold
System over load threshold 4.7 5.2 5.7 A
CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
LSFET under-current falling threshold From sync mode to non-sync mode 250 mA
PWM
PWM switching frequency Oscillator frequency 1500 kHz
Maximum PWM duty cycle 97 %
BOOST MODE OPERATION
Boost mode regulation voltage VVBAT = 3.8 V, I(PMID) = 0 A, BOOSTV[1:0] = '10' 5 5.15 5.3 V
Boost mode regulation voltage accuracy VVBAT = 3.8 V, I(PMID) = 0 A, BOOSTV[1:0] = '10' -3 3 %
VVBAT falling, MIN_VBAT_SEL = 0 2.6 2.8 3.0 V
VVBAT rising, MIN_VBAT_SEL =0 2.8 3 3.2 V
Battery voltage exiting boost mode
VVBAT falling, MIN_VBAT_SEL = 1 2.3 2.5 2.7 V
VVBAT rising, MIN_VBAT_SEL = 1 2.6 2.8 3.0 V
OTG mode output current BOOST_LIM = 1 1.2 1.4 A
BOOST_LIM = 0 0.5 0.7 A
OTG overvoltage threshold Rising threshold 5.6 6 6.4 V
HSFET under current falling threshold 100 mA
Hiccup Retrying timer 7 ms
Hiccup Off timer 28 ms
After the last retry, part clear OTG_CONFIG
Maximum retry allowed 7 Time
bit to disable Boost
VLDO REGULATION
LDO output voltage VVBUS = 9V, ILDO = 40mA 5 V
LDO output current limit VVBUS = 9V, VLDO = 4V 80 mA
LOGIC I/O PIN CHARACTERISTICS (nCE, PSEL, SCL, SDA)
Input low threshold 0.4 V
Input high threshold 1.3 V
High-level leakage current Pull up rail 1.8 V 1 µA
LOGIC I/O PIN CHARACTERISTICS (nPG, STAT, nINT)
Low-level output voltage 0.4 V
VBUS/BAT POWER UP
Bad adapter detection duration 30.0 ms
BATTERY CHARGER
Deglitch time for charge Termination 7 s
Deglitch time for recharge 32 ms
System over-current deglitch time to turn
1 ms
off Q4

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ETA6953
PARAMETER CONDITIONS MIN TYP MAX UNITS
Battery over-voltage deglitch time to
10 µs
disable charge
Typical Charge Safety Timer Range CHG_TIMER = 1 10 Hr
Typical Top-Off Timer Range TOP_OFF_TIMER[1:0] = 10 (30 min) 30 min
nQON TIMING
nQON low time to turn on BATFET and
–10oC ≤ TJ ≤ 60oC 1.15 s
exit ship mode
nQON low time to reset BATFET –10oC ≤ TJ ≤ 60oC 10 s
BATFET off time during full system reset –10oC ≤ TJ ≤ 60oC 320 ms
Enter ship mode delay –10 oC ≤ TJ ≤ 60oC 12 s
DIGITAL CLOCK AND WATCHDOG TIMER
REG05[4]=01 40 s

PIN DESCRIPTION
PIN NAME PIN # DESCRIPTION
VAC 1 Charger input voltage sense. This pin must be connected to VBUS pin.
Charger input voltage. Bypass it with a 10-μF ceramic capacitor from VBUS to PGND. The capacitor
VBUS 24
should be close to the VBUS pin.
Power source selection input. Set 500 mA input current limit by pulling this pin high and set 2.4A
PSEL 2 input current limit by pulling this pin low. Once the device gets into host mode, the host can program
different input current limits to IINDPM register.
Open drain active low power good indicator. Connect to the pull up rail through 10-kΩ resistor. LOW
nPG 3 indicates a good input source if the input voltage is between VBUSUVLO and VBUS_OV, above SLEEP
mode threshold, and current limit is above 30 mA.
Open-drain charge status output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT
pin indicates charger status. Connect a current limit resistor and a LED from a rail to this pin.
STAT 4 Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response)or No bat: 1-Hz, 50% duty cycle Pulses
SCL 5 I2C interface clock. Connect a 10-kΩ pull up resistor to the logic rail.
SDA 6 I2C interface data. Connect a 10-kΩ pull up resistor to the logic rail.
Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin
nINT 7
sends an active low, 256-µs pulse to host to report charger device status and fault.
NC 8 No Connect. Keep the pin float
nCE 9 Charge disable control pin. nCE=0, charge is enabled. nCE=1, charge is disabled.
NC 10 No Connect. Keep the pin float
Temperature qualification voltage input to support JEITA profile. Connect a negative temperature
TS 11
coefficient thermistor. Program temperature window with a resistor divider from VLDO to TS to GND.

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ETA6953
PIN NAME PIN # DESCRIPTION
Charge suspends when either TS pin is out of range. When TS pin is not used, connect a 10-kΩ
resistor from VLDO to TS and connect a 10-kΩ resistor from TS to GND. It is recommended to use
a 103AT-2 thermistor.
BATFET enable/reset control input. When BATFET is in ship mode, a logic low of tSHIPMODE (typical
1.15s) duration turns on BATFET to exit shipping mode. When VBUS is not plugged-in, a logic low
nQON 12 of tQON_RST (minimum 8s) duration resets SYS (system power) by turning BATFET off for tBATFET_RST
(minimum 250 ms) and then re-enable BATFET to provide full system power reset. The pin contains
an internal pull-up to maintain default high logic.
Positive battery terminal. The internal BATFET and current sensing is connected between SYS and
BAT 13, 14
BAT. Connect a 10 μF close to the BAT pin.
Converter output connection point. The internal current sensing network is connected between SYS
SYS 15, 16
and BAT. Connect a 20 μF close to the SYS pin.
GND 17, 18 Power Ground
Switching node output. Connected to output inductor. Connect the 10nF bootstrap capacitor from
SW 19, 20
SW to BTST
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 10nF ceramic capacitor
BST 21
from BST pin to SW pin.
LDO Output Voltage. Bypass the pin with 4.7μF (10V rating) capacitor from VLDO to GND. The
VLDO 22
capacitor should be closed to the pin
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a
PMID 23
minimum of 10μF capacitor from PMID to PGND. This capacitor should be close to the PMID pin.
Thermal pad and ground reference. This pad is ground reference for the device and it is also the
EP EP thermal pad used to conduct heat from the device. This pad should be tied externally to a ground
plane through PCB vias under the pad.

TYPICAL PERFORMANCE CHARACTERISTICS

(Typical values are at TA = 25oC unless otherwise specified.)

OTG Vout Vs. Iout OTG Eff. Vs. Iout

5.5 100%

5.4 Vout=5.1V 95% Vout=5.1V

5.3 90%

5.2 85%
Efficiency (%)

5.1 80%
Vout (V)

Vbat=3.3V
5 Vbat=3.3V 75%
Vbat=3.6V
4.9 Vbat=3.6V 70%

4.8 65% Vbat=3.8V

Vbat=3.8V
4.7 Vbat=4.2V 60% Vbat=4.2V
4.6 55% Vbat=4.35V
Vbat=4.35V
4.5 50%
0 0.2 0.4 0.6 0.8 1 1.2 0.01 0.1 1

Iout (A) Iout (A)

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ETA6953
TYPICAL PERFORMANCE CHARACTERISTICS cont’
(Typical values are at TA = 25oC unless otherwise specified.)

Charger Eff. Vs. Iout Charger Eff. Vs. Iout

100% 100%

95% Vbat=3.8V 95% Vbat=3.3V

90% 90%

85% 85%

Efficiency (%)
Efficiency (%)

80% 80%

75% 75%

70% 70%
Vin=5V Vin=5V
65% 65%

60%
Vin=9V 60% Vin=9V
55% Vin=12V 55% Vin=12V
50% 50%
0.1 1 0.1 1

Iout (A) Iout (A)

Charger Vterm Vs. Temp Iindpm Vs. Temp.

4.4 1.20

Vbus=5V 1.15 Vbus=5V, Iindpm set as 1A

4.35 1.10

1.05
Iindpm (A)
Vterm (V)

4.3 1.00

0.95

4.25 0.90

Vterm 0.85 Iindpm

4.2 0.80
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100

Temperature (°C) Temperature (°C)

Vindpm Vs. Temp Icharge Vs. Temp.

4.6 1600
Vbat=5V Vbus=5V, Vbat=3.3V
1400
4.5
1200
4.4
Icharge (mA)

1000
Vindpm (V)

4.3 800

600
4.2
400
Treg[]=1, REG05=9F
4.1 Vindpm 200
Treg[]=0, REF05=9D
4 0
-40 -20 0 20 40 60 80 100 0 20 40 60 80 100 120 140

Temperature (°C) Temperature (°C)

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FUNCTION DESCRIPTION
The ETA6953 device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-Ion and Li-polymer battery. It includes the
input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET
(BATFET, Q4), and bootstrap diode for the high-side gate drive

POWER UP FROM BATTERY WITHOUT INPUT SOURCE

When a battery is applied without other input, the device checks the battery voltage to turn on BATFET but not VLDO to minimize the
supply current, especially for NTC resistor network. All supply will be directly from battery. VLDO is disabled until BOOST is enabled.
Anyway, in order to optimize the discharge current from battery at light load, BATFET gate charge pump operates with lower frequency.

POWER UP WITH INPUT SOURCE

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the bias circuits. It detects
and sets the input current limit before the buck converter is started. The power up sequence from input source is as listed:
1. Power up VLDO
2. Poor Source Qualification
3. Input Source Type Detection based on PSEL to set default input Current Limit (IINDPM) register or input source type
4. Input Voltage Limit Threshold Setting (VINDPM threshold)
5. Converter Power-up

VLDO POWER UP
VLDO is enabled when the below conditions are met:
1. VAC is above 3.65V
2. VAC is above VBAT + VSLEEP (200mV)in Buck mode or VAC below VBAT + VSLEEP in Boost mode
Right after two above conditions are valid, VLDO is powered up right away

POWER SOURCE QUALIFICATION

After VLDO powers up, the device checks the current capability of the input source. The input source has to meet the following
requirements in order to start the buck converter.
1. 200mS delay after VLDO enable
2. VAC voltage below the VAC_OVP threshold
3. VAC voltage above 3.8V when pulling down 30mA at VAC
If the device fails the poor source detection in 30ms, it repeats poor source qualification every 2 seconds. Once the input source passes
all the conditions above, the status register bit VBUS_GD is set high and the nINT pin is pulsed to signal to the host.

INPUT SOURCE TYPE DETECTION

After the VBUS_GD bit is set, the device will run input source detection through the PSEL pin. The ETA6953 sets input current limit through
PSEL pin. And after input type detection is completed, Input Current limit register is changed to set current limit; PG_STAT bit and
VBUS_STAT bits are updated.

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ETA6953
PSEL PIN SET INPUT CURRENT LIMIT
The ETA6953 has a PSEL pin for input current limit setting. When the device works in default mode, the input current limit will be either
0.5A (PSEL High) or 2.4A (PSEL Low). When device operates in host mode, the input current limit will follow IINDPM register setting. But
if it works in the host mode, then the host write IINDET_EN bit to 1, it will force current limit to follow PSEL pin and then updates IINDPM
register. After that, the IINDET_EN bit is auto clear to 0, the IINDPM register will hold the PSEL current limit setting either 0.5A or 2.4A.

BUCK POWER UP
After the input current is set, the device starts Buck converter and allow HSFET and LSFET switching. The ETA6953 provide soft-start
time, VSYS short protection to avoid overshoot current. When switching is over the soft-start time, the BATFET starts turning on then
allows charging progress.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input current limit is set to the lower
of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the device limits input current to the value of IINDPM register.
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed frequency oscillator keeps
tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying
output filter design.
In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage
setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the voltage ratio of SYS and VBUS. The
PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.

BOOST POWER UP
ETA6953 provide boost converter up to 1.2A output current. The boost is enabled when the below conditions are valid:
1. VBAT above the battery voltage exiting boost mode threshold
2. VBUS is less than VBAT+VSLEEP (200mV)
3. OTG_CONFIG bit=1
4. TS pin is within acceptable range (VBHOT<VTS<VBCOLD)
During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5.15 V by default and 1.5MHz Frequency. The
output current can reach up to 1.2 A, selected through I2C (BOOST_LIM bit). The boost output is maintained when BAT is above
VOTG_BAT threshold. When OTG is enabled, the device starts up with PFM and later transits to PWM to minimize the overshoot. The
PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.

HOST MODE AND DEFAULT MODE

The ETA6953 is a host controlled charger, but it can operate in default mode without host management. In default mode, the device can
be used as an autonomous charger with no host or while host is in sleep mode. When the charger is in default mode, WATCHDOG_FAULT
bit is Logic High. When the charger is in host mode, WATCHDOG_FAULT bit is Logic Low.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the registers are in the default
settings. During default mode, any change on PSEL pin will make real time IINDPM register changes.
In default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end of the 10-hour, the

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ETA6953
charging is stopped and the buck converter continues to operate to supply system load.
Writing a ‘1’ to the WD_RST bit transitions the charger from default mode to host mode. All the device parameters can be programmed by
the host. To keep the device in host mode, the host has to reset the watchdog timer by writing ‘1’ to WD_RST bit before the watchdog
timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.
When the watchdog timer expires (WATCHDOG_FAULT bit = 1), the device returns to default mode and all registers are reset to default
values except IINDPM, VINDPM, BATFET_RST_EN, BATFET_DLY, and BATFET_DIS bits.

Host Mode
POR Start Watchdog
Timer
Program Registers

Default Mode
Reset Watchdog
Y
Timer WD _ RST [ ] = 1
Reset Registers
N

N 2 Y Y Watchdog N
I C WRITE Timer
Expired

Figure 1: Watchdog Timer Flow Chart

AUTONOMOUS BATTERY CHARGER

The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 27mΩ BATFET improves
charging efficiency and minimize the voltage drop during discharging.
With battery charging is enabled (CHG_CONFIG bit = 1 and nCE pin is LOW), the device autonomously completes a charging cycle
without host involvement. The host can always control the charging operations and optimize the charging parameters by writing to the
corresponding registers through I2C.
A new charge cycle starts when the following conditions are valid:
• Converter starts
• Battery charging is enabled (CHG_CONFIG bit = 1 and ICHG register is not 0 mA and CE is low)
• No thermistor fault on TS
• No safety timer fault
• BATFET is not forced to turn off (BATFET_DIS bit = 0)

Table 1: Charging Parameter Default Setting

Default Mode ETA6953
Charging Voltage 4.208V
Charging Current 2.048A
Pre-charge Current 180mA
Termination Current 180mA
Temperature Profile JEITA
Safety Timer 10 hours

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ETA6953
The charger device automatically terminates the charging cycle when the charging current is below termination threshold, charge voltage
is above recharge threshold, and device not is in DPM mode or thermal regulation.
When a full battery voltage is discharged below recharge threshold (selectable through VRECHG bit), the device automatically starts a
new charging cycle. After the charge is done, toggle nCE pin or CHG_CONFIG bit can initiate a new charging cycle.
The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking).
The STAT output can be disabled by setting EN_ICHG_MON bits = 11. In addition, the status register (CHRG_STAT) indicates the different
charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done.
Once a charging cycle is completed, an INT is asserted to notify the host.

BATTERY CHARGER PROFILE

The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage and top-off trickle charging
(optional). At the beginning of a charging cycle, the device checks the battery voltage and regulates current and voltage accordingly.
If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the
programmed value. in this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate.

VREG = VREG[ 5:0]

SYS Pin Voltage
BAT Pin Voltage
Battery Charge Current
I CHG_ REG = ICHG[ 5:0]

VSYS_ MIN = SYS_MIN[ 2:0]

VBAT_ LOWV =3. 12V

V SHORTZ =2. 25V

I PRECHG = IPRECHG[ 3:0]

ITERM = ITERM[ 3:0]
I SHORT = 145 mA

Trickle Charge Precondition Fast Charge Voltage Topoff - Total timer

Charge Regulation Timer Expiration

Figure 2: Battery Charger Profile

CHARGE TERMINATION CONFIGURATION
When battery voltage reach regulation level set by VREG[4:0], the device allow charger enter termination if EN_TERM[ ] = 1. In this state,
when charge current falls below ITERM level, charger will be terminated after TTOPOFF. After the charging cycle is completed, the BATFET
turns off. The converter keeps running to power the system, and BATFET can turn on again to engage Supplement Mode.
When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host. Termination is temporarily
disabled when the charger device is in input current, voltage or thermal regulation. Termination can be disabled by writing 0 to EN_TERM
bit prior to charge termination.
At low termination currents, due to the comparator offset, the actual termination current may be higher than the termination target. In order
to compensate for comparator offset, a programmable top-off timer can be applied after termination is detected. The termination timer will

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ETA6953
follow safety timer constraints, such that if safety timer is suspended, so will the termination timer. Similarly, if safety timer is doubled, so
will the termination timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The host can read CHRG_STAT and
TOPOFF_ACTIVE to find out the termination status.
Top off timer gets reset at one of the following conditions:
1. Charge disable to enable
2. Termination status low to high
3. REG_RST register bit is set
The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer value after termination will
have no effect unless a recharge cycle is initiated. An INT is asserted to the host when entering top-off timer segment as well as when
top-off timer expires.

CHARGE SAFETY TIMER

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 2 hours
when the battery is below VBATLOWV threshold. The user can program fast charge safety timer through I2C (CHG_TIMER bits). When
safety timer expires, the fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be
disabled through I2C by setting EN_TIMER bit.
During input voltage, current, JEITA cool or thermal regulation, the safety timer counts at half clock rate as the actual charge current is
likely to be below the register setting. For example, if the charger is in input current regulation (IDPM_STAT = 1) throughout the whole
charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This half clock rate feature can be disabled
by writing 0 to TMR2X_EN bit.
During the fault, timer is suspended. Once the fault goes away, fault resumes. If user stops the current charging cycle, and start again,
timer gets reset (toggle nCE pin or CHRG_CONFIG bit).

MINIMUM SYS VOLTAGE

Because the rail that provide power to system is SYS voltage, so to make
sure the system always has enough voltage, ETA6953 provide minimum SYS
voltage selection. The minimum system voltage is set by SYS_MIN[2:0] bits.
4.5
Even with a fully depleted battery, the system is regulated above the minimum Minimum System Voltage
4.3
system voltage (default 3.5 V). Charge Disabled
Charge Enabled
4.1
When the battery is below minimum system voltage setting, the BATFET 3.9
operates in linear mode (LDO mode), and the system is typically 180 mV 3.7
above the minimum system voltage setting. As the battery voltage rises above 3.5
the minimum system voltage, BATFET is fully on and the voltage difference 3.3
between the system and battery is the VDS of BATFET. 3.1
2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
When the battery charging is disabled and above minimum system voltage
setting or charging is terminated, the system is always regulated at typically Figure 3: System Voltage vs Battery Voltage
70mV above battery voltage. The status register VSYS_STAT bit goes high
when the system is in minimum system voltage regulation.

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ETA6953
DYNAMIC POWER MANAGEMENT
To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic Power management (DPM),
which continuously monitors the input current and input voltage. When input source is over-loaded, either the current exceeds the input
current limit (IINDPM) or the voltage falls below the input voltage limit (VINDPM). The device then reduces the charge current until the
input current falls below the input current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system
voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery
starts discharging so that the system is supported from both the input source and battery.
During DPM mode, the status register bits VDPM_STAT (VINDPM) or IDPM_STAT (IINDPM) goes high.

SUPPLEMENT MODE
When the system voltage falls 10 mV (VBAT > VSYSMIN when Q4 is full on. In this condition, discharge current is almost 1A.) or 20mV (VBAT
< VSYSMIN when Q4 is in regulation. In this condition, gate of Q4 is regulated at about only threshold voltage of the FET, then discharge
current is almost zero.) below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so
that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the supplement
mode.
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full
conduction. At this point onwards, the BATFET VDS linearly increases with discharge current. Following figure shows the V-I curve of the
BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold.

Figure 4: BATFET Current at Entering Supplement Mode

SHIPPING MODE AND nQON PIN

BATFET DISALBE MODE (SHIPPING MODE)
To extend battery life and minimize power when system is powered off during system idle, shipping, or storage, the device can turn off
BATFET so that the system voltage is zero to minimize the battery leakage current. When the host set BATFET_DIS bit, the charger can
turn off BATFET immediately or delay by tSM_DLY as configured by BATFET_DLY bit.

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ETA6953
BATFET ENABLE (EXIT SHIPPING MODE)
When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following events can enable BATFET
to restore system power:
1. Plug in adapter
2. Clear BATFET_DIS bit
3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
4. A logic high to low transition on nQON pin with tSHIPMODE deglitch time (1.15s typical) to enable BATFET to exit shipping mode

BATFET FULL SYSTEM RESET

The BATFET functions as a load switch between battery and system when input source is not plugged-in. By changing the state of BATFET
from on to off, systems connected to SYS can be effectively forced to have a power-on-reset. The QON pin supports push-button interface
to reset system power without host by changing the state of BATFET.
When the QON pin is driven to logic low for tQON_RST while input source is not plugged in and BATFET is enabled (BATFET_DIS = 0), the
BATFET is turned off for tBATFET_RST and then it is re-enabled to reset system power. This function can be disabled by setting
BATFET_RST_EN bit to 0.

nQON PIN OPERATION

Internally, there is a 500K pull up resistor from nQON pin to VDD(maximum of VBAT and VLDO).So default, nQON will be high. Then
nQON logic low and high voltage threshold are 0.68V and 0.88V respectively. The nQON pin incorporates two functions to control BATFET.
1. BATFET Enable: A nQON logic transition from high to low with longer than tSHIPMODE deglitch turns on BATFET and exit shipping
mode
2. BATFET Reset: When nQON is driven to logic low by at least tQON_RST (12s typical) while adapter is not plugged in (and
BATFET_DIS = 0), the BATFET is turned off for tBATFET_RST (10s typical). The BATFET is re-enabled after tBATFET_RST duration. This
function allows systems connected to SYS to have power-on-reset. This function can be disabled by setting BATFET_RST_EN
bit to 0.

Press Press
nQON Button Button

TSHIPMODE TQON_RST TBATFET_RST

BATFET
Status
Q4 disabled by host
Q4 enabled Q4 enabled
Or overload

Q4 Disabled

a, turn on BATFET when BATFET_DIS[ ] =1 b, Reset BATFET when BATFET_DIS[ ] =0

Figure 5: nQON Timing

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ETA6953
THERMISTOR QUALIFICATION DURING
CHARGING MODE BAT
The charger device provides a single thermistor VLDO
input for battery temperature monitor. RTS1
TS Battery
RTS2 10k Pack

Figure 6: Thermistor Configuration

To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline emphasized the
importance of avoiding a high charge current and high charge voltage at certain low and high temperature ranges.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds the T1-T5 range, the
controller suspends charging and waits until the battery temperature is within the T1 to T5 range.
At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge current or lower. At warm
temperature (T3-T5), JEITA recommends charge voltage less than 4.1V.
The charger provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at warm temperature (T3-T5)
can be VREG or 4.1V (configured by JEITA_VSET). The current setting at cool temperature (T1-T2) can be further reduced to 20% of fast
charge current (JEITA_ISET).

100 VREG
90
80
70 JEITA_VSET= 0
Charge Voltage (V )
Charging Current (%)

60
JEITA _ISET = 0
50 4.1
40
JEITA_VSET= 1
30 JEITA_ ISET = 1
20
10
0 0
-5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
T1 T2 T3 T5 T1 T2 T3 T5
o o
Junction Temperature( C) Junction Temperature( C)

Figure 7: JEITA Profile: Charging Current Figure 8: JEITA Profile: Charging Voltage

The resistor bias network has been updated as below.

VLDO 1 1
-1) ( VLDO×RTHCOLD ×RTHHOT ×( - )
RTS1= 1 VT1 1 RTS2= VLDO
VT1 VT5
VLDO
+
RTS2 RTHCOLD
RTHHOT × �
VT5
-1� -RTHCOLD ×(
VT1
-1)

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ETA6953
THERMISTOR QUALIFICATION DURING BATTERY DISCHARGE MODE

For battery protection during boost mode, the device VLDO BCOLD BHOT
monitors the battery temperature to be within the VBCOLD
to VBHOT thresholds. When temperature is outside of the

BOOST Enable

DISABLE

DISABLE
temperature thresholds, the boost mode is suspended. in
additional, VBUS_STAT bits are set to 000 and
NTC_FAULT is reported. Once temperature returns within
0
thresholds, the boost mode is recovered and NTC_FAULT - 40 - 30 - 20 - 10 0 10 20 30 40 50 60 70 80 90 100
is cleared. o
Junction Temperature( C)

Figure 9: TS Pin Thermistor Sense Threshold in Boost Mode

INDICATION OUTPUT

POWER GOOD INDICATION ON nPG PIN OR PG_STAT BIT

The PG_STAT bit goes HIGH and nPG pin goes LOW to indicate a good input source when:
 VBUS Pass Poor Source Detection
 Completed input Source Type Detection

CHARGING STATUS INDICATION ON STAT PIN

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin function can be disabled by
setting the STAT_CONFIG[1:0] = 11. When STAT_CONFIG[1:0] = 00, STAT indication operates as shown as in below table.
Table 2: STAT Indication table
CHARGE STATE STAT INDICATION
Charging in progress (including recharge) LOW

Charging complete HIGH

Sleep mode, charge disable HIGH

Charge suspend (input overvoltage, TS fault, timer fault or system Blinking at 1Hz
overvoltage) (0.5s LOW / 0.5s HIZ)
Boost Mode suspend (due to TS fault)

HOST INTERRUPT ON nINT PIN

ETA6953 provides a comfortable feature that host does not need to always monitor the charger operation. The nINT pulse notifies the
system on the device operation. The following events will generate 256-μs INT pulse.
 Input Source Type Detection Completed (through PSEL detection)
 VBUS Pass Poor Source Detection
 Input removed
 Charge Complete
 Any FAULT event in REG09
 VINDPM event detected. Masked by VINDPM_INT_ MASK = 1.
 IINDPM event detected. Masked by IINDPM_INT_ MASK = 1.

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When a fault occurs, the charger device sends out nINT and keeps the fault state in REG09 until the host reads the fault register. Before
the host reads REG09 and all the faults are cleared, the charger device would not send any INT upon new faults. To read the current fault
status, the host has to read REG09 two times consecutively. The first read reports the pre-existing fault register status and the second
read reports the current fault register status.

INPUT OVERVOLTAGE PROTECTION IN CHARGE MODE (ACOV)

If VBUS voltage exceeds the VBUS over voltage threshold VBUS_OV (programmable via OVP[1:0] bits) the device stops switching
immediately. During input overvoltage event, the fault register CHRG_FAULT bits are set to 01. An INT pulse is asserted to the host. The
device will automatically resume normal operation once the input voltage drops back below the OVP threshold.
SYSTEM OVERVOLTAGE PROTOECTION IN CHARGE MODE (SYSOVP)
The charger device clamps the system voltage during load transient so that the components connect to system would not be damaged
due to high voltage. SYSOVP threshold is 14% above system regulation voltage. Upon SYSOVP, converter stops immediately to clamp
the overshoot.

VBUS OUTPUT SHORT PROTECTION IN BOOST MODE

The device monitors boost output voltage and other conditions to provide output short circuit and overvoltage protection. The Boost build-
in accurate constant current regulation to allow OTG to adaptive to various types of load. If short circuit is detected on VBUS, the Boost
turns off and retry 7 times. If retries are not successful, OTG is disabled with OTG_CONFIG bit cleared. In addition, the BOOST_FAULT
bit is set and INT pulse is generated. The BOOST_FAULT bit can be cleared by host by re-enabling boost mode

VBUS OVERVOLTAGE PROTECTION IN BOOST MODE

When the VBUS voltage rises above regulation target and exceeds the over voltage threshold VOTG_OVP, the device enters overvoltage
protection which stops switching, clears OTG_CONFIG bit and exits boost mode. At Boost overvoltage duration, the fault register bit
(BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also asserted to the host.

THERMAL REGULATION IN BUCK MODE

The ETA6953 monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature at 110oC in
buck mode. When the internal junction temperature exceeds thermal regulation limit (110°C), the device lowers down the charge current.
During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination
is disabled, the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes high.
Thermal limit is programmable to 90oC by programming TREG bit.

THERMAL SHUTDOWN
The device monitors the internal junction temperature to provide thermal shutdown during any mode. When IC surface temperature
exceeds TSHUT (160oC) BATFET and Converter are disabled. OTG_CONFIG bit is cleared if in BOOST mode and BOOST_FAULT bit is
set. In Charge mode, CHARGE_FAULT bit is set. An nINT pulse is asserted to the host.
When IC temperature is TSHUT_HYS (30oC) below TSHUT (160oC), The BATFET and charger are enabled following enable condition, Boost
can be enabled by host.

BATTERY OVER-VOLTAGE PROTECTION

The battery overvoltage limit is clamped at 7% above the battery regulation voltage. When battery over voltage occurs, the charger device
immediately disables charge. The fault register BAT_FAULT bit goes high and an INT is asserted to the host

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ETA6953
BATTERY OVER-DISCHARGE PROTECTION
When battery is discharged below the battery depletion falling threshold VBAT_DPL_FALL, the BATFET is turned off to protect battery from over
discharge. To recover from over-discharge, an input source is required at VBUS. When an input source is plugged in, the BATFET turns
on. The battery is charged with ISHORT (typically 150 mA) current when the VBAT is smaller than the trickle charge voltage threshold VSHORT,
or pre-charge current as set in IPRECHG register when the battery voltage is between VSHORT and the pre-charge voltage threshold VBAT_LOWV.

SYSTEM OVER-CURRENT PROTECTION

When the system is shorted or significantly overloaded (IBAT > IBATOP) so that its current exceeds the overcurrent limit, the device latches
off BATFET. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off condition and turn on BATFET.

I2C COMMUNICATION
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2CTM
is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required:
a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A
master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any
device addressed is considered a slave.
The device operates as a slave device with address D6H, receiving control inputs from the master device like micro controller or a digital
signal processor through REG00-REG0C. The I2C interface supports both standard mode (up to 100kbits), and fast mode (up to 400kbits),
connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and
SCL pins are open drain.
A [0]= 0

RA[6: 3 ]
A[6: 3 ]

D[6: 3]
RA[6 ]

RA[1 ]

RA[0 ]
RA[ 7 ]
A [7 ]

A [ 6]

A [ 1]

D [ 6]

D [ 1]
D [7 ]

D [ 0]
SDA
START (S)

STOP (P)
3- 6

3- 6
3- 6

SCL
ACK

ACK
ACK
1

Slave Address Register Address Write Data

Figure 10: Single Write

A [ 0]= 0

D [6 : 3 ]
A [ 0 ]=1
RA [ 6:3]
A [6 : 3 ]

A [6]
RA[ 6 ]

RA[1 ]

RA[0 ]

A [7]

A [6 : 3 ]

D[1 ]

D[ 0]
A[6]

A[1]
A[7]

RA[7]

A [1 ]

SDA
D[ 7 ]

D[ 6 ]
3-6

ACK
START

START

SCL
3- 6

NCK
ACK

ACK
3-6

STOP
3 -6

(P)
(S )

(S)
1

Slave Address Register Address Slave Address Read Data

Figure 11: Singe Read

Device address is understood value of A[7:0] while A[0] is “0”. This is also the address to write the data to the device registers. To read
data from register, sending the command to address with A[0] is “1”. Register address are in RA[7:0]. Data to or from register are D[7:0].

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ETA6953
REGISTER MAP

Table 3: REG00
BIT NAME POR TYPE RESET BY DESCRIPTION NOTE
7 EN_HIZ 0 R/W by REG_RST 0-Disable, 1-Enable Enable HIZ Mode
by Watchdog 0-Disable (default)
1-Enable
6 EN_ICHG_MON[1] 0 R/W by REG_RST 00 - Enable STAT
5 EN_ICHG_MON[0] 0 pin function(default)
01 - Reserved
10 - Reserved
11 - Disable STAT
pin function(float pin)
4 IINDPM[4] 1 R/W by REG_RST 1600 mA Input Current Limit
3 IINDPM[3] 0 R/W by REG_RST 800 mA Offset: 100 mA
2 IINDPM[2] 1 R/W by REG_RST 400 mA Range: 100 mA (000000) – 3.2 A (11111)
1 IINDPM[1] 1 R/W by REG_RST 200 mA Default:2400 mA (10111),
0 IINDPM[0] 1 R/W by REG_RST 100 mA maximum input current limit, not typical.
IINDPM bits are changed
automatically after input source detection
is completed
PSEL = Hi = 500 mA
PSEL = Lo = 2.4 A
Host can over-write IINDPM register bits
after input source detection is completed.

Table 4: REG01
BIT NAME POR TYPE RESET BY DESCRIPTION NOTE
7 PFM _DIS 0 R/W by REG_RST 0 – Enable PFM Default: 0 - Enable
1 – Disable PFM
6 WD_RST 0 R/W by REG_RST I2C Watchdog Timer Reset Default: Normal (0) Back to 0 after
by Watchdog 0 –Normal; 1 – Reset watchdog timer reset
5 OTG_CONFIG 0 R/W by REG_RST 0 – OTG Disable Default: OTG disable (0)
by Watchdog 1 – OTG Enable Note:
1. OTG_CONFIG would over-ride
Charge Enable Function in
CHG_CONFIG
4 CHG_CONFIG 1 R/W by REG_RST 0 - Charge Disable Default: Charge Battery (1)
by Watchdog 1- Charge Enable Note:
1. Charge is enabled when both CE pin is
pulled low AND
CHG_CONFIG bit is 1.

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ETA6953
Table 4: REG01
BIT NAME POR TYPE RESET BY DESCRIPTION NOTE
3 SYS_Min[2] 1 R/W by REG_RST System Minimum Voltage 000: 2.6 V 001: 2.8 V
2 SYS_Min[1] 0 R/W by REG_RST 010: 3 V 011: 3.2 V
1 SYS_Min[0] 1 R/W by REG_RST 100: 3.4 V 101: 3.5 V
110: 3.6 V 111: 3.7 V
Default: 3.5 V (101)
0 Min_VBAT_SEL 0 R/W by REG_RST 0 – 2.8 V BAT falling, Minimum battery voltage for OTG mode.
1 – 2.5 V BAT falling Default falling 2.8 V (0); Rising threshold
3.0 V (0)

Table 5: REG02
BIT NAME POR TYPE RESET BY DESCRIPTION NOTE
7 BOOST_LIM 1 R/W by REG_RST 0 = 0.5 A Default: 1.2 A (1)
by Watchdog 1 = 1.2 A Note:
The current limit options listed are
minimum current limit specs.
6 Q1_FULLON 0 R/W by REG_RST 0 – Use higher Q1 RDSON In boost mode, full FET is always
when programmed IINDPM < used and this bit has no effect
700mA (better accuracy)
1 – Use lower Q1 RDSON
always (better efficiency)
5 ICHG[5] 1 R/W by REG_RST 1920 mA Fast Charge Current
by Watchdog Default: 2040mA (100010)
4 ICHG[4] 0 R/W by REG_RST 960 mA Range: 0 mA (0000000) – 3000mA
by Watchdog (110010)
3 ICHG[3] 0 R/W by REG_RST 480 mA Note:
by Watchdog ICHG = 0 mA disables charge.
ICHG > 3000 mA (110010) clamped
to register value 3000 mA (110010)

2 ICHG[2] 0 R/W by REG_RST 240mA

by Watchdog
1 ICHG[1] 1 R/W by REG_RST 120mA
by Watchdog
0 ICHG[0] 0 R/W by REG_RST 60mA
by Watchdog

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ETA6953
Table 6: REG03
BIT NAME POR TYPE RESET BY DESCRIPTION NOTE
7 IPRECHG[3] 0 R/W by REG_RST 480mA Precharge Current
by Watchdog Default: 180 mA (0010)
6 IPRECHG[2] 0 R/W by REG_RST 240mA Offset: 60 mA
by Watchdog Note: IPRECHG > 780 mA
5 IPRECHG[1] 1 R/W by REG_RST 120mA clamped to 780 mA (1100)
by Watchdog
4 IPRECHG[0] 0 R/W by REG_RST 60mA
by Watchdog
3 ITERM[3] 0 R/W by REG_RST 480mA Termination Current
by Watchdog Default: 180 mA (0010)
2 ITERM[2] 0 R/W by REG_RST 240mA Offset: 60 mA
by Watchdog
1 ITERM[1] 1 R/W by REG_RST 120mA
by Watchdog
0 ITERM[0] 0 R/W by REG_RST 60mA
by Watchdog

Table 7: REG04
BIT NAME POR TYPE RESET BY DESCRIPTION NOTE
7 VREG[4] 0 R/W by REG_RST 512mV Charge Voltage Offset: 3.856 V
by Watchdog Range: 3.856 V to 4.624 V (11000)
6 VREG[3] 1 R/W by REG_RST 256mV Default: 4.208 V (01011)
by Watchdog Special Value:
5 VREG[2] 0 R/W by REG_RST 128mV (01111): 4.336 V
by Watchdog Note: Value above 11000 (4.624V) is
4 VREG[1] 1 R/W by REG_RST 64mV clamped to register value 11000 (4.624 V)
by Watchdog
3 VREG[0] 1 R/W by REG_RST 32mV
by Watchdog
2 TOPOFF_TIMR 0 R/W by REG_RST 00 – Disabled (Default) The extended time following the termination
[1] by Watchdog 01 – 15 minutes condition is met. When disabled, charge
1 TOPOFF_TIMR 0 R/W by REG_RST 10 – 30 minutes terminated when termination conditions are
[0] by Watchdog 11 – 45 minutes met.
0 VREGCHG 0 R/W by REG_RST 0 – 120 mV Recharge threshold Default: 120mV (0)
by Watchdog 1 – 240 mV

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ETA6953
Table 8: REG05
BIT NAME POR TYPE RESET BY DESCRIPTION NOTE
7 EN_TERM 1 R/W by REG_RST 0 – Disable Default:
by Watchdog 1 - Enable Enable termination (1)
6 Reserved 0 R/W by REG_RST Reserved Reserved
by Watchdog
5 WATCHDOG[1] 0 R/W by REG_RST 00 – Disable timer Default: 40s (01)
by Watchdog 01 – 40s
4 WATCHDOG[0] 1 R/W by REG_RST 10 – 80s
by Watchdog 11 – 160s
3 EN_TIMER 1 R/W by REG_RST 0 – Disable Default: Enable (1)
by Watchdog 1 – Enable both fast charge and precharge
timer
2 CHG_TIMER 1 R/W by REG_RST 0 – 5 hrs Default: 10 hours (1)
by Watchdog 1 – 10 hrs
1 TREG 1 R/W by REG_RST Thermal Regulation Threshold: Default: 110°C (1)
by Watchdog 0 - 90°C
1 - 110°C
0 JEITA_ISET 1 R/W by REG_RST 0 – 50% of ICHG Default: 20% (1)
(0°C-10°C) by Watchdog 1 – 20% of ICHG

Table 9: REG06
BIT NAME POR TYPE RESET BY DESCRIPTION NOTE
7 OVP[1] 0 R/W by REG_RST Default: 6.5v VAC OVP threshold:
6 OVP[0] 1 R/W by REG_RST (01) 00 - 5.5 V 01 – 6.5 V (5-V input)
10 – 10.5 V (9-V input) 11 – 14 V (12-V input)
5 BOOSTV[1] 1 R/W by REG_RST Default: 5.15v Boost Regulation Voltage:
4 BOOSTV[0] 0 R/W by REG_RST (10) 00 - 4.85V 01 - 5.00V
10 - 5.15V 11 - 5.30V
3 VINDPM[3] 0 R/W by REG_RST 800mV Absolute VINDPM Threshold Offset: 3.9 V
2 VINDPM[2] 1 R/W by REG_RST 400mV Range: 3.9 V (0000) – 5.4 V (1111)
1 VINDPM[1] 1 R/W by REG_RST 200mV Default: 4.5V (0110)
0 VINDPM[0] 0 R/W by REG_RST 100mV

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ETA6953
Table 10: REG07
BIT NAME POR TYPE RESET BY DESCRIPTION NOTE
7 IINDET_EN 0 R/W by REG_RST 0 - Not in input current limit detection Returns to 0 after input
by Watchdog 1 - Force input current limit detection detection is complete
when VBUS is present
6 TMR2X_EN 1 R/W by REG_RST 0 – Disable
by Watchdog 1 – Safety timer slowed by 2X during
input DPM (both V and I) or JEITA cool,
or thermal regulation
5 BATFET_DIS 0 R/W by REG_RST 0 – Allow Q4 turn on, 1 – Turn off Q4 with Default: Allow Q4 turn on (0)
TBATFET_DLY delay time (REG07[3])
4 JEITA_VSET 0 R/W by REG_RST 0 – Set Charge Voltage to 4.1V (max),
(45°C-60°C) by Watchdog 1 – Set Charge Voltage to VREG
3 BATFET_DLY 1 R/W by REG_RST 0 – Turn off BATFET immediately when Default: 1
BATFET_DIS bit is set Turn off BATFET after
1 –Turn off BATFET after TBATFET_DLY TBATFET_DLY (typ. 10s)
(typ. 10s) when BATFET_DIS bit is set when BATFET_DIS bit is set
2 BATFET_RST_EN 1 R/W by REG_RST 0 – Disable BATFET reset function Default: 1
by Watchdog 1 – Enable BATFET reset function Enable BATFET reset function
1 VDPM_BAT_TRA 0 R/W by REG_RST 00 - Disable function (VINDPM set by Sets VINDPM to track BAT
CK[1] register) voltage. Actual VINDPM is
0 VDPM_BAT_TRA 0 R/W by REG_RST 01 - VBAT + 200mV higher of register value and
CK[0] 10 - VBAT + 250mV VBAT + VDPM_BAT_TRACK
11 - VBAT + 300mV

Table 11: REG08

BIT NAME POR TYPE RESET BY DESCRIPTION
7 VBUS_STAT[2] X R NA VBUS Status register
6 VBUS_STAT[1] X R NA 000: No input 001: USB Host SDP (500 mA) → PSEL HIGH
5 VBUS_STAT[0] X R NA 010: Adapter 2.4A → PSEL LOW 111: OTG
Software current limit is reported in IINDPM register
4 CHRG_STAT[1] X R NA Charging status:
3 CHRG_STAT[0] X R NA 00 – Not Charging 01 – Pre-charge (< VBATLOWV)
10 – Fast Charging 11 – Charge Termination
2 PG_STAT X R NA Power Good status:
0 – Power Not Good 1 – Power Good
1 THERM_STAT X R NA 0 – Not in thermal regulation 1 – in thermal regulation
0 VSYS_STAT X R NA 0 – Not in VSYSMin regulation (BAT > VSYSMin)
1 – in VSYSMin regulation (BAT < VSYSMin)

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ETA6953
Table 12: REG09
BIT NAME POR TYPE RESET BY DESCRIPTION
7 WATCHDOG_FAU X R NA 0 – Normal, 1- Watchdog timer expiration
LT
6 BOOST_FAULT X R NA 0 – Normal, 1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low
(any conditions that we cannot start boost function)
5 CHRG_FAULT[1] X R NA 00 – Normal, 01 – input fault (VAC OVP or VBAT < VBUS < 3.8 V)
4 CHRG_FAULT[0] X R NA 10 -Thermal shutdown, 11 – Charge Safety Timer Expiration
3 BAT_FAULT X R NA 0 – Normal, 1 – BATOVP
2 NTC_FAULT[2] X R NA JEITA
1 NTC_FAULT[1] X R NA 000 – Normal, 010 – Warm, 011 – Cool, 101 – Cold, 110 – Hot (Buck mode)
0 NTC_FAULT[0] X R NA 000 – Normal, 101 – Cold, 110 – Hot (Boost mode)

Table 13: REG0A

BIT NAME POR TYPE RESET BY DESCRIPTION
7 VBUS_GD X R NA 0 – Not VBUS attached 1 – VBUS Attached
6 VINDPM_STAT X R NA 0 – Not in VINDPM 1 – in VINDPM
5 IINDPM_STAT X R NA 0 – Not in IINDPM 1 – in IINDPM
4 Reserved X R NA Reserved Reserved
3 TOPOFF_ACTIVE X R NA 0 – Top off timer not counting 1 – Top off timer counting
2 ACOV_STAT X R NA 0 – Device is NOT in ACOV 1 – Device is in ACOV
1 VINDPM_INT_ 0 R/W by REG_RST 0 - Allow VINDPM INT pulse 1 - Mask VINDPM INT pulse
MASK
0 VINDPM_INT_ 0 R/W by REG_RST 0 - Allow IINDPM INT pulse 1 - Mask IINDPM INT pulse
MASK

Table 14: REG0B

BIT NAME POR TYPE RESET BY DESCRIPTION
7 REG_RST X R/W NA Register reset
0 – Keep current register setting
1 – Reset to default register value and reset safety timer
Note: Bit resets to 0 after register reset is completed
6 PIN[3] 0 R NA ETA6953: 0010
5 PIN[2] 0 R NA
4 PIN[1] 1 R NA
3 PIN[0] 0 R NA
2 ETA_PART ID 1 R NA ETA Part ID for recognition
1 DEV_REV[1] X R NA
0 DEV_REV[0] X R NA

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ETA6953
Table 15: REG0C
BIT NAME POR TYPE RESET BY DESCRIPTION
7 Reserved 0 R NA Reserved
6 Reserved 0 R NA Reserved
5 Reserved 0 R NA Reserved
4 Reserved 0 R NA Reserved
3 Reserved 0 R NA Reserved
2 Reserved 0 R NA Reserved
1 Reserved 0 R NA Reserved
0 Reserved 0 R NA Reserved

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ETA6953
FUNCTION BLOCK DIAGRAM

Q1-BRFET
VBUS PMID
VBUS

BST_ ILIM
V BUS_ UVLO
LDO Q1 GATE
IVBUS V ACOV
EN_HIZ CONTROL
VBUS
VLDO
VBAT
V BAT_ UVLO
OTG _ CONFIG[ ]=1
VDD

ECOMP BST

VBUS I BAT EN_ HIZ PWM / PFM

Q2- HSFET
V INDPM I CHG CONTROL SW
EN_ BOOST VLDO
EN_ BUCK
I INDPM BAT
I VBUS EN_CHARGER
VREG Q3 - LSFET
GND

IC TJ
SYS
TJREG
I BAT

Q 4 GATE
CONTROL
nCE
Q4- BATFET BAT
DIGITAL
IBADSRSC BADSOURCE
CONTROL VDD
I DC

TEMP_BAD
IC TJ
TSHUT nQON

BAT RECHRG OVER - DISCHARGE I BAT

VREG - VRECHG
I BATFET_OCP
BAT PRECOND
V BATLOWV SUSPEND
CHARGE BATTERY
CONTROL THERMISTOR TS
BAT TRICKLE MODE
V SHORT SENSE

I BAT TERMINATION

ITERM nINT
nPG
INPUT STAT
PSEL SOURCE
DETECTION

SCL
I2 C
SDA

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ETA6953
PCB DESIGN GUIDELINE
In order to have as clean as possible supply for converter, please follow following suggestion:
1. Place the VBUS, PMID, BAT, SYS, VLDO capacitor as close as possible to the pins and wide bottom layer for PGND
connections. Also add as much as possible vias for PGND to minimize copper resistance added to PMID capacitor.
2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic
field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this
connection. Minimize parasitic capacitance from this area to any other trace or plane.
3. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC ground with a short
copper trace connection or GND plane.
4. Use thermal pad as the single ground connection point.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the device. Use ground
copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB ground. Ensure that
there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
8. Ensure that the number and sizes of vias allow enough copper for a given current path.
9. Ensure almost the bottom layer be ground unless bridge connection.

GND
4.7uF

10uF

10nF
1uH
10uF

1uF

VBUS

ETA6953 10uF 10uF

GND VSYS

VBAT

10uF GND

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ETA6953
PACKAGE OUTLINE

QFN4x4-24

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ETA6953
TAPE AND REEL INFORMATION

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