AMD Am79C971

Am79C971
PCnet™-FAST
Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
DISTINCTIVE CHARACTERISTICS
■ Single-chip Fast Ethernet controller for the — Includes intelligent on-chip Network Port
Peripheral Component Interconnect (PCI) local Manager that provides auto-port selection
bus between MII, on-chip 10BASE-T port, and AUI
— 32-bit glueless PCI host interface without software support
— Supports PCI clock frequency from DC to — Supports both auto-negotiable and non
33 MHz independent of network clock auto-negotiable external PHYs
— Supports network operation with PCI clock — Supports 10BASE-T, 100BASE-TX/FX,
from 15 MHz to 33 MHz 100BASE-T4, and 100BASE-T2 IEEE 802.3-
compliant MII PHYs at full- or half-duplex
— High performance bus mastering
architecture with integrated Direct Memory ■ Internal/external loopback capabilities on all
Access (DMA) Buffer Management Unit for ports
low CPU and bus utilization ■ Supports patented External Address Detection
— PCI specification revision 2.1 compliant Interface (EADI)
— Supports PCI Subsystem/Subvendor ID/ — Receive frame tagging support for inter-
Vendor ID programming through the networking applications
EEPROM interface ■ Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
— Supports both PCI 5.0-V and 3.3-V signaling Media Access Controller (MAC) compliant with
environments IEEE/ANSI 802.3 and Blue Book Ethernet
standards
— Plug and Play compatible
— Supports an unlimited PCI burst length ■ Full-duplex operation supported in AUI,
10BASE-T, MII, and GPSI ports with
— Big endian and little endian byte alignments independent Transmit (TX) and Receive (RX)
supported channels
■ Integrated 10BASE-T and 10BASE-2/5 (AUI)
■ Flexible buffer architecture
Physical Layer Interface
— Large independent internal TX and RX FIFOs
— Single-chip IEEE/ANSI 802.3, IEC/ISO 8802-3
and Blue Book Ethernet-compliant solution — SRAM-based FIFO buffer extension
supporting up to 128 kilobytes (Kbytes)
— Automatic Twisted-Pair receive polarity
detection and correction — 1/2 Gigabit per second (Gbps) internal data
bandwidth
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted-Pair medium — Programmable FIFO watermarks for both TX
and RX operations
— IEEE 802.3-compliant auto-negotiable
10BASE-T interface — RX frame queuing for high latency PCI bus
host operation
■ Supports General Purpose Serial Interface
(GPSI) — Programmable allocation of buffer space
between RX and TX queues
■ Media Independent Interface (MII) for
connecting external 10- or 100-Megabit per ■ EEPROM interface supports jumperless design
second (Mbps) transceivers and provides through-chip programming
— IEEE 802.3-compliant MII — Supports full programmability of half-/full-

duplex operation for external 100 Mbps PHYs
— Intelligent Auto-Poll™ external PHY status through EEPROM mapping
monitor and interrupt
■ Extensive LED status support
Publication# 20550 Rev: E Amendment: /0

Issue Date: May 2000
■ Supports up to 1 Megabyte (Mbyte) optional mode for board-level production connectivity
Boot PROM and Flash for diskless node test
application ■ Implements low-power management for critical
■ Look-Ahead Packet Processing (LAPP) data battery powered application and green PCs
handling technique reduces system overhead — Includes two power-saving sleep modes
by allowing protocol analysis to begin before (sleep and snooze)
the end of a receive frame
— Integrated Magic Packet™ technology
■ Includes Programmable Inter Packet Gap (IPG) support for remote power of networked PCs
to address less network aggressive MAC
■ Software compatible with AMD PCnet Family
controllers
and LANCE/C-LANCE register and descriptor
■ Offers the Modified Back-Off algorithm to architecture
address the Ethernet Capture Effect
■ Compatible with the existing PCnet Family
■ IEEE 1149.1-compliant JTAG Boundary Scan driver/diagnostic software
test access port interface and NAND tree test
■ Available in 160-pin TQFP and 176-pin TQFP
packages
GENERAL DESCRIPTION
The Am79C971 controller is a single-chip 32-bit full-du- LANCE (Am79C90) Ethernet controller, and all Ether-
plex, 10/100-Megabit per second (Mbps) highly- net controllers in the PCnet Family except ILACC
integrated Ethernet system solution, designed to (Am79C900), including the PCnet-ISA controller
address high-performance system application require- (Am79C960),PCnet-ISA+ controller (Am79C961),
ments. It is a flexible bus mastering device that can be PCnet-ISA II controller (Am79C961A), PCnet-32 con-
used in any application, including network-ready PCs troller (Am79C965), PCnet-PCI controller
and bridge/router designs. The bus master architecture (Am79C970), and PCnet-PCI II controller
provides high data throughput in the system and low (Am79C970A). The Buffer Management Unit supports
CPU and system bus utilization. The Am79C971 con- the LANCE and PCnet descriptor software models.
troller is fabricated with AMD’s advanced low-power
The 32-bit multiplexed bus interface unit provides a
Complementary Metal Oxide Semiconductor (CMOS)
direct interface to the PCI local bus, simplifying the
process to provide low operating and standby current
design of an Ethernet node in a PC system. The
for power sensitive applications.
Am79C971 controller provides the complete interface
The Am79C971 controller is a complete Ethernet node to an Expansion ROM or Flash device allowing add-on
integrated into a single VLSI device. It contains a bus card designs with only a single load per PCI bus inter-
interface unit, a Direct Memory Access (DMA) Buffer face pin. With its built-in support for both little and big
Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)- endian byte alignment, this controller also addresses
compliant Media Access Controller (MAC), a large non-PC applications. The Am79C971 controller’s ad-
Transmit FIFO and a large Receive FIFO, SRAM- vanced CMOS design allows the bus interface to be
based FIFO extension with support for up to 128K connected to either a +5-V or a +3.3-V signaling envi-
bytes of external frame buffering, an IEEE 802.3u-com- ronment. A compliant IEEE 1149.1 JTAG test interface
pliant MII, an IEEE 802.3-compliant Twisted-Pair Trans- for board-level testing is also provided, as well as a
ceiver Media Attachment Unit (10BASE-T MAU), and NAND tree test structure for those systems that cannot
an IEEE 802.3-compliant Attachment Unit Interface support the JTAG interface.
(AUI). Both proprietary full-duplex and IEEE 802.3
The Am79C971 controller supports auto-configuration
compliant half-duplex operation are supported on the
in the PCI configuration space. Additional Am79C971
MII, AUI, GPSI, and 10BASE-T MAU interfaces. 10-
controller configuration parameters, including the
Mbps operation is supported through the MII, AUI, and
unique IEEE physical address, can be read from an ex-
10BASE-T MAU interfaces, and 100 Mbps operation is
ternal non-volatile memory (EEPROM) immediately fol-
supported through the MII. The 10BASE-T MAU inter-
lowing system reset.
face includes an IEEE 802.3-compliant auto-negotia-
tion implementation, which will automatically negotiate The integrated Manchester encoder/decoder (MEN-
between half- and full-duplex with another IEEE 802.3- DEC) eliminates the need for an external Serial Inter-
compliant auto-negotiation 10BASE-T device. face Adapter (SIA) in the system. The built-in GPSI
allows the MENDEC to be bypassed.
The Am79C971 controller is register compatible with
the LANCE (Am7990) Ethernet controller, the C-
2 Am79C971
In addition, the device provides programmable on-chip can be guaranteed during frame transmission and
LED drivers for transmit, receive, collision, receive po- reception.
larity, link integrity, activity, link active, address match,
In highly loaded 10-Mbps systems, such as servers or
full-duplex, MII select, 100 Mbps, or jabber status. The
when using the controller in a 100-Mbps environment,
Am79C971 controller also provides an EADI to allow
the additional frame buffering capability provided by a
external hardware address filtering in internetworking
16-bit wide SRAM interface provides high performance
applications and a receive frame tagging feature.
and high latency tolerance on the system bus and net-
For power sensitive applications where low standby work.
current is desired, the device incorporates two sleep
The Am79C971 controller can use up to 128 Kbytes of
functions to reduce overall system power consumption,
SRAM as an extension of its dual Transmit and Receive
excellent for notebooks and green PCs. In conjunction
FIFOs. When no SRAM is used, the Am79C971 con-
with these low power modes, the PCnet-FAST control-
troller’s FIFOs are programmed to bypass the SRAM
ler also has integrated functions to support Magic
interface.
Packet technology, an inexpensive technology that al-
lows remote wake up of networked PCs. IMPORTANT NOTE: A “No SRAM configuration” is only
valid for 10Mb mode. In 100Mb mode, SRAM is man-
The controller has the capability to automatically select
datory and must always be used.
either the MII, AUI, or Twisted-Pair transceiver. Only
one interface is active at any one time. Any of the net- ISO/IEC 8802-3 and IEEE 802.3 will be used inter-
work interfaces can be programmed to operate in either changeably when referring to half-duplex 10 Mbps net-
half-duplex or full-duplex mode (AUI full-duplex only works. IEEE 802.3 or IEEE 802.3u will be used
supports the 10BASE-F standard). interchangeably only when referring to half-duplex 100-
Mbps Ethernet networks, since the IEEE standard is
The dual Transmit and Receive FIFOs optimize system not ISO approved yet. Full-duplex is a proprietary stan-
overhead, providing sufficient latency tolerance at 10 dard and is not approved by IEEE or ISO.
Mbps and for 100-Mbps systems where low latencies
Am79C971 3
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am79C971 C
K\V \W
ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray
TEMPERATURE RANGE
C = Commercial (0° C to +70° C)
PACKAGE TYPE
K = Plastic Quad Flat Pack (PQR160)
V = Thin Quad Flat Pack (PQL176)
SPEED OPTION
Not applicable
DEVICE NUMBER/DESCRIPTION
Am79C971
Single-Chip Full-Duplex 10/100 Mbps Ethernet
Controller for PCI Local Bus
Valid Combinations Valid Combinations

Valid Combinations list configurations planned to be
Am79C971 KC\W, supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
VC\W
valid combinations and to check on newly released
combinations.
4 Am79C971
BLOCK DIAGRAM
EBUA_EBA[7:0]
EBDA[15:8]
EBD[7:0]
EROMCS
ERAMCS
AS_EBOE
EBWE
EBCLK
TXEN
TXCLK
Expansion Bus Interface TXDAT
GPSI RXEN
Port
RXCLK
RXDAT
CLK CLSN
TX_E
RST
TXD[3:0]
AD[31:00]
TX_EN
C/BE[3:0]
TX_CLK
PAR COL
Bus MAC
FRAME Rcv Rcv MII RXD[3:0]
TRDY PCI Bus FIFO FIFO Port RX_ER
IRDY Interface RX_CLK
STOP Unit RX_DV
IDSEL 802.3 CRS
DEVSEL MAC MDC
REQ Core MDIO
GNT SRDCLK
PERR SRD
Bus MAC EADI
Xmt SF/BD
SERR Xmt Port EAR
INTA FIFO FIFO
RXFRTGD/MIIRXFRTGD
SLEEP
RXFRTGE/MIIRXFRTGE
Manchester XTAL1
Encoder/ XTAL2
Network Decoder DO+/-
Port (PLS) &
Manager DI+/-
AUI Port
CI+/-
Buffer
Management FIFO TXD+/-
Unit Control Auto 10BASE-T TXP+/-
Negotiation MAU RXD+/-
EECS
93C46
EESK
TCK EEPROM
JTAG Interface EEDI
TMS
Port EEDO
TDI
Control LED0
TDO
LED LED1
Control LED2
LED3
20550D-1
Am79C971 5
TABLE OF CONTENTS
AM79C971 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CONNECTION DIAGRAM (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CONNECTION DIAGRAM (PQL176) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PIN DESIGNATIONS (PQL176). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PIN DESIGNATIONS (PQR160, PQL176). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Listed By Driver Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
AD[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
C/BE[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DEVSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
FRAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
GNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
IDSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
INTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
IRDY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
LED0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
LED1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
LED2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
LED3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
EECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
EEDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
EEDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
EESK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
EBUA_EBA[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
EBDA[15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
EBD[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
EROMCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ERAMCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
AS_EBOE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
EBWE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
EBCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6 Am79C971
TX_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
TXD[3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
TX_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
TX_ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
COL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RX_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RXD[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RX_DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RX_ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
MDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Attachment Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CI±. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DI±. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DO±. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
RXD± . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TXD±. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TXP± . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CLSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
RXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
RXDAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
RXEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
TXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
TXDAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
TXEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SFBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SRDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
RXFRTGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
RXFRTGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MIIRXFRTGD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MIIRXFRTGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
AVDDB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
AVSSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
VDD_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
VSS_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
VDDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
VSSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
VDD_PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Am79C971 7
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Slave I/O Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Manchester Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Attachment Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Twisted-Pair Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
External Address Detection Interface (EADI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Power Savings Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
The contents of the Device ID register is the same as the contents of CSR88. . . . . . . . . . . . . .100
NAND Tree Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
REGISTER PROGRAMMING SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Am79C971 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE
SPECIFIED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
SWITCHING CHARACTERISTICS: BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
SWITCHING CHARACTERISTICS: ATTACHMENT UNIT INTERFACE. . . . . . . . . . . . . . . . . . . . . .207
SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . .208
SWITCHING CHARACTERISTICS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . . .209
SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . .210
KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
SWITCHING WAVEFORMS: 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
SWITCHING WAVEFORMS: ATTACHMENT UNIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . .221
SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . .224
8 Am79C971
SWITCHING WAVEFORMS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . .226
SWITCHING WAVEFORMS: EXTERNAL ADDRESS DETECTION INTERFACE. . . . . . . . . . . . . .227
SWITCHING WAVEFORMS: RECEIVE FRAME TAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
PQR160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
PQL176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
AM79C971 COMPATIBLE MEDIA INTERFACE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
RECOMMENDATION FOR POWER AND GROUND DECOUPLING. . . . . . . . . . . . . . . . . . . . . . . .B-1
ALTERNATIVE METHOD FOR INITIALIZATION* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-1
LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-1
AUTO-NEGOTIATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
AM79C971A PCNET-FAST 10/100 MBPS PCI ETHERNET CONTROLLER REV A.6 ERRATA . . F-1
Am79C971 9
RELATED AMD PRODUCTS
Part No. Description
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am79865 100 Mbps Physical Data Transmitter (PDT)
An79866A 100 Mbps Physical Data Receiver (PDR)
Am79C870 Quad 100BASE-X Transceiver
Am79C871 Quad 100BASE-X Repeater Transceiver
Am79C940 Media Access Controller for Ethernet (MACE™)
Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft® Plug n' Play support)
Am79C961A PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft® Plug n' Play support)
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses)
Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus
Am79C981 Integrated Multiport Repeater Plus™ (IMR+™)
Am79C987 Hardware Implemented Management Information Base™ (HIMIB™)
10 Am79C971
CONNECTION DIAGRAM (PQR160)
EEDO/LED3/SRD/MIIRXFRTGD
LED2/SRDCLK/MIIRXFRTGE
EESK/LED1/SFBD
EEDI/LED0
VDD_PLL
VDD_PCI
VDD_PCI
AVDDB
AVSSB
C/BE3
VDDB
VSSB
EECS
VSSB
VSSB
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
INTA
TDO
TMS
REQ
DO+
VDD
TCK
GNT
RST
VSS
CLK
DO-
TDI
CI+
DI+
CI-
DI-
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
IDSEL 1 120 XTAL2
VDD 2 119 VSS_PLL
AD23 3 118 XTAL1
AD22 4 117 AVDDB
VSS 5 116 TXD+
AD21 6 115 TXP+
AD20 7 114 TXD-
VDD_PCI 8 113 TXP-
AD19 9 112 AVDDB
AD18 10 111 RXD+
VSSB 11 110 RXD-
AD17 12 109 VSS
AD16 13 108 MDIO
C/BE2 14 107 MDC
FRAME 15 106 SLEEP/EAR
IRDY 16 105 RXD3
TRDY 17 104 RXD2
DEVSEL 18 103 RXD1
STOP 19 PCnet™-FAST 102 RXD0/RXFRTGD
VSSB 20 101 VDDB
PERR 21 Am79C971
Am79C971KC/W 100 RX_DV/RXFRTGE
SERR 22 99 RX_CLK/RXCLK
VDD_PCI 23 98 RX_ER/RXDAT
PAR 24 97 VSSB
C/BE1 25 96 TX_ER
AD15 26 95 TX_CLK/TXCLK
AD14 27 94 TX_EN/TXEN
AD13 28 93 VDDB
AD12 29 92 TXD0/TXDAT
VSSB 30 91 TXD1
AD11 31 90 TXD2
AD10 32 89 TXD3
VDD 33 88 COL/CLSN
AD9 34 87 CRS/RXEN
AD8 35 86 VSSB
VSS 36 85 EBD0
C/BE0 37 84 EBD1
AD7 38 83 EBD2
AD6 39 82 EBD3
VSSB 40 81 EBD4
58
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
AD1
EBD5
VSS
VSSB
AD5
AD4
AD3
AD2
VDD_PCI
AD0
VSSB
ERAMCS
EBROMCS
EBWE
AS_EBOE
EBCLK
EBUA_EBA0
EBUA_EBA1
EBUA_EBA2
EBUA_EBA3
VSSB
EBUA_EBA4
VDDB
EBUA_EBA5
EBUA_EBA6
EBUA_EBA7
EBDA8
EBDA9
EBDA10
EBDA11
VSSB
EBDA12
EBDA13
EBDA14
EBDA15
EBD7
EBD6
VSS
VDDB
VDD
2055A-2
Pin 1 is marked for orientation.

20550D-2
Am79C971 11
CONNECTION DIAGRAM (PQL176)
EEDO/LED3/SRD/MIIRXFRTGD
LED2/SRDCLK/MIIRXFRTGE
EESK/LED1/SFBD
EEDI/LED0
VDD_PLL
VDD_PCI
VDD_PCI
AVDDB
AVSSB
C/BE3
VDDB
EECS
VSSB
VSSB
VSSB
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
INTA
REQ
VDD
GNT
TDO
TMS
DO+
VSS
RST
TCK
CLK
DO-
TDI
CI+
DI+
NC
NC
NC
NC
CI-
DI-
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
NC 1 132 NC
NC 2 131 NC
IDSEL 3 130 XTAL2
VDD 4 129 VSS_PLL
AD23 5 128 XTAL1
AD22 6 127 AVDDB
VSS 7 126 TXD+
AD21 8 125 TXP+
AD20 9 124 TXD-
VDD_PCI 10 123 TXP-
AD19 11 122 AVDDB
AD18 12 121 RXD+
VSSB 13 120 RXD-
AD17 14 119 VSS
AD16 15 118 MDIO
C/BE2 16 117 MDC
FRAME 17 116 SLEEP/EAR
IRDY 18 115 RXD3
TRDY 19 114 RXD2
DEVSEL 20 113 RXD1
STOP 21 PCnetª- FAST 112 RXD0/RXFRTGD
VSSB 22 Am79C971 VC/W
Am79C971 VC/W 111 VDDB
PERR 23 110 RX_DV/RXFRTGE
SERR 24 109 RX_CLK/RXCLK
VDD_PCI 25 108 RX_ER/RXDAT
PAR 26 107 VSSB
C/BE1 27 106 TX_ER
AD15 28 105 TX_CLTXCLK
AD14 29 104 TX_EN/TXEN
AD13 30 103 VDDB
AD12 31 102 TXD0/TXDAT
VSSB 32 101 TXD1
AD11 33 100 TXD2/RXEN
AD10 34 99 TXD3
VDD 35 98 COL/CLSN
AD9 36 97 CRS/RXEN
AD8 37 96 VSSB
VSS 38 95 EBD0
C/BE0 39 94 EBD1
AD7 40 93 EBD2
AD6 41 92 EBD3
VSSB 42 91 EBD4
NC 43 90 NC
NC 44 89 NC
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
NC
NC
AD5
AD4
AD3
AD2
VDD_PCI
AD1
AD0
VSSB
ERAMCS
EBROMCS
EBWE
AS_EBOE
EBCLK
VSS
EBUA_EBA0
EBUA_EBA1
EBUA_EBA2
EBUA_EBA3
VSSB
EBUA_EBA4
VDDB
EBUA_EBA5
EBUA_EBA6
EBUA_EBA7
VDDB
EBDA8
EBDA9
EBDA10
EBDA11
VSSB
EBDA12
EBDA13
VDD
EBDA14
EBDA15
EBD7
EBD6
VSSB
EBD5
VSS
NC
NC
20550D-3
Pin 1 is marked for orientation.
12 Am79C971
PIN DESIGNATIONS (PQR160)
Listed By Pin Number
Pin Pin Pin Pin Pin Pin Pin

No. Name No. Name No. Name Pin No. Name
1 IDSEL 41 AD5 81 EBD4 121 AVSSB
2 VDD 42 AD4 82 EBD3 122 DO-
3 AD23 43 AD3 83 EBD2 123 DO+
4 AD22 44 AD2 84 EBD1 124 AVDDB
5 VSS 45 VDD_PCI 85 EBD0 125 DI-
6 AD21 46 AD1 86 VSSB 126 DI+
7 AD20 47 AD0 87 CRS/RXEN 127 CI-
8 VDD_PCI 48 VSSB 88 COL/CLSN 128 CI+
9 AD19 49 ERAMCS 89 TXD3 129 VDD_PLL
10 AD18 50 EROMCS 90 TXD2 130 VDDB
EEDO/LED3/SRD/
11 VSSB 51 EBWE 91 TXD1 131
MIIRXFRTGD
12 AD17 52 AS_EBOE 92 TXD0/TXDAT 132 EED1/LED0
LED2/SRDCLK/
13 AD16 53 EBCLK 93 VDDB 133
MIIRXFRTGE
14 C/BE2 54 VSS 94 TX_EN/TXEN 134 EESK/LED1/SFBD
15 FRAME 55 EBUA_EBA0 95 TX_CLK/TXCLK 135 VSSB
16 IRDY 56 EBUA_EBA1 96 TX_ER 136 EECS
17 TRDY 57 EBUA_EBA2 97 VSSB 137 TCK
18 DEVSEL 58 EBUA_EBA3 98 RX_ER/RXDAT 138 TMS
19 STOP 59 VSSB 99 RX_CLK/RXCLK 139 TDO
20 VSSB 60 EBUA_EBA4 100 RX_DV/RXFRTGE 140 TDI
21 PERR 61 VDDB 101 VDDB 141 VDD_PCI
22 SERR 62 EBUA_EBA5 102 RXD0/RXFRTGD 142 INTA
23 VDD_PCI 63 EBUA_EBA6 103 RXD1 143 RST
24 PAR 64 EBUA_EBA7 104 RXD2 144 VSS
25 C/BE1 65 VDDB 105 RXD3 145 CLK
26 AD15 66 EBDA8 106 SLEEP/EAR 146 VSSB
27 AD14 67 EBDA9 107 MDC 147 GNT
28 AD13 68 EBDA10 108 MDIO 148 REQ
29 AD12 69 EBDA11 109 VSS 149 AD31
30 VSSB 70 VSSB 110 RXD- 150 VDD
31 AD11 71 EBDA12 111 RXD+ 151 AD30
32 AD10 72 EBDA13 112 AVDDB 152 AD29
33 VDD 73 VDD 113 TXP- 153 AD28
34 AD9 74 EBDA14 114 TXD- 154 AD27
35 AD8 75 EBDA15 115 TXP+ 155 AD26
36 VSS 76 EBD7 116 TXD+ 156 VDD_PCI
37 C/BE0 77 EBD6 117 AVDDB 157 AD25
38 AD7 78 VSSB 118 XTAL1 158 VSSB
39 AD6 79 EBD5 119 VSS_PLL 159 C/BE3
40 VSSB 80 VSS 120 XTAL2 160 AD24
Am79C971 13
PIN DESIGNATIONS (PQL176)
Listed By Pin Number
Pin Pin Pin Pin Pin Pin Pin

No. Name No. Name No. Name Pin No. Name
1 NC 45 NC 89 NC 133 NC
2 NC 46 NC 90 NC 134 NC
3 IDSEL 47 AD5 91 EBD4 135 AVSSB
4 VDD 48 AD4 92 EBD3 136 DO-
5 AD23 49 AD3 93 EBD2 137 DO+
6 AD22 50 AD2 94 EBD1 138 AVDDB
7 VSS 51 VDD_PCI 95 EBD0 139 DI-
8 AD21 52 AD1 96 VSSB 140 DI+
9 AD20 53 AD0 97 CRS/RXEN 141 CI-
10 VDD_PCI 54 VSSB 98 COL/CLSN 142 CI+
11 AD19 55 ERAMCS 99 TXD3 143 VDD_PLL
12 AD18 56 EROMCS 100 TXD2/RXEN 144 VDDB
EEDO/LED3/SRD/
13 VSSB 57 EBWE 101 TXD1 145
MIIRXFRTGD
14 AD17 58 AS_EBOE 102 TXD0/TXDAT 146 EED1/LED0
LED2/SRDCLK/
15 AD16 59 EBCLK 103 VDDB 147
MIIRXFRTGE
16 C/BE2 60 VSS 104 TX_EN/TXEN 148 EESK/LED1/SFBD
17 FRAME 61 EBUA_EBA0 105 TX_CLK/TXCLK 149 VSSB
18 IRDY 62 EBUA_EBA1 106 TX_ER 150 EECS
19 TRDY 63 EBUA_EBA2 107 VSSB 151 TCK
20 DEVSEL 64 EBUA_EBA3 108 RX_ER/RXDAT 152 TMS
21 STOP 65 VSSB 109 RX_CLK/RXCLK 153 TDO
22 VSSB 66 EBUA_EBA4 110 RX_DV/RXFRTGE 154 TDI
23 PERR 67 VDDB 111 VDDB 155 VDD_PCI
24 SERR 68 EBUA_EBA5 112 RXD0/RXFRTGD 156 INTA
25 VDD_PCI 69 EBUA_EBA6 113 RXD1 157 RST
26 PAR 70 EBUA_EBA7 114 RXD2 158 VSS
27 C/BE1 71 VDDB 115 RXD3 159 CLK
28 AD15 72 EBDA8 116 SLEEP/EAR 160 VSSB
29 AD14 73 EBDA9 117 MDC 161 GNT
30 AD13 74 EBDA10 118 MDIO 162 REQ
31 AD12 75 EBDA11 119 VSS 163 AD31
32 VSSB 76 VSSB 120 RXD- 164 VDD
33 AD11 77 EBDA12 121 RXD+ 165 AD30
34 AD10 78 EBDA13 122 AVDDB 166 AD29
35 VDD 79 VDD 123 TXP- 167 AD28
36 AD9 80 EBDA14 124 TXD- 168 AD27
37 AD8 81 EBDA15 125 TXP+ 169 AD26
38 VSS 82 EBD7 126 TXD+ 170 VDD_PCI
39 C/BE0 83 EBD6 127 AVDDB 171 AD25
40 AD7 84 VSSB 128 XTAL1 172 VSSB
41 AD6 85 EBD5 129 VSS_PLL 173 C/BE3
42 VSSB 86 VSS 130 XTAL2 174 AD24
43 NC 87 NC 131 NC 175 NC
44 NC 88 NC 132 NC 176 NC
14 Am79C971
PIN DESIGNATIONS (PQR160, PQL176)
Listed By Group
Pin Name Pin Function Type1 Driver No. of Pins
PCI Bus Interface
AD[31:0] Address/Data Bus IO TS3 32
C/BE[3:0] Bus Command/Byte Enable IO TS3 4
CLK Bus Clock I NA 1
DEVSEL Device Select IO STS6 1
FRAME Cycle Frame IO STS6 1
GNT Bus Grant I NA 1
IDSEL Initialization Device Select I NA 1
INTA Interrupt O OD6 1
IRDY Initiator Ready IO STS6 1
PAR Parity IO TS3 1
PERR Parity Error IO STS6 1
REQ Bus Request O TS3 1
RST Reset I NA 1
SERR System Error IO OD6 1
STOP Stop IO STS6 1
TRDY Target Ready IO STS6 1
Board Interface
LED0 LED0 O LED 1
LED1 LED1 O LED 1
LED2 LED2 O LED 1
LED3 LED3 O LED 1
SLEEP Sleep Mode I NA 1
XTAL1 Crystal Input I NA 1
XTAL2 Crystal Output O XTAL 1
EEPROM Interface
EECS Serial EEPROM Chip Select O O6 1
EEDI Serial EEPROM Data In O LED 1
EEDO Serial EEPROM Data Out I NA 1
EESK Serial EEPROM Clock IO LED 1
Expansion ROM Interface
AS_EBOE Address Strobe/Expansion Bus Output Enable O O6 1
EBCLK Expansion Bus Clock I NA 1
EBD[7:0] Expansion Bus Data [7:0] IO TS6 8
EBDA[15:8] Expansion Bus Data/Address [15:8] IO TS6 8
Expansion Bus Upper Address /Expansion Bus Address
EBUA_EBA[7:0] O O6 8
[7:0]
EBWE Expansion Bus Write Enable O O6 1
ERAMCS Expansion Bus RAM Chip Select O O6 1
EROMCS Expansion Bus ROM Chip Select O O6 1
Note:
1. Not including test features
Am79C971 15
PIN DESIGNATIONS
Listed By Group

Media Independent Interface (MII)
COL Collision I NA 1
CRS Carrier Sense I NA 1
MDC Management Data Clock O OMII2 1
MDIO Management Data I/O IO TSMII 1
RX_CLK Receive Clock I NA 1
RXD[3:0] Receive Data I NA 4
RX_DV Receive Data Valid I NA 1
RX_ER Receive Error I NA 1
TX_CLK Transmit Clock I NA 1
TXD[3:0] Transmit Data O OMII1 4
TX_EN Transmit Data Enable O OMII1 1
TX_ER Transmit Error O OMII1 1
Attachment Unit Interface (AUI)
CI± AUI Collision I NA 1
DI± AUI Data In I NA 1
DO± AUI Data Out O DO 1
10BASE-T Interface
RXD+/RXD- Receive Differential Pair I NA 2
TXD+/TXD- Transmit Differential Pair O TDO 2
TXP+/TXP- Transmit Pre-distortion Differential Pair O TPO 2
General Purpose Serial Interface (GPSI)
CLSN Collision IO NA 1
RXCLK Receive Clock I NA 1
RXDAT Receive Data I NA 1
RXEN Receive Enable I NA 1
TXCLK Transmit Clock I NA 1
TXDAT Transmit Data O O6 1
TXEN Transmit Enable O O6 1
External Address Detection Interface (EADI)
EAR External Address Reject Low I NA 1
SFBD Start Frame Byte Delimiter O LED 1
SRD Serial Receive Data IO LED 1
SRDCLK Serial Receive Data Clock IO LED 1
Receive Frame Tag Data/MII Receive Frame
RXFRTGD/MIIRXFRTGD I NA 1
Tag Data
Receive Frame Tag Enable/MII Receive Frame
RXFRTGE/MIIRXFRTGE I NA 1
Tag Enable
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK Test Clock I NA 1
TDI Test Data In I NA 1
TDO Test Data Out O TS6 1
TMS Test Mode Select I NA 1
Note:
1. Not including test features.
16 Am79C971
PIN DESIGNATIONS
Listed By Group

Power Supplies
AVDDB Analog I/O Buffer Power P NA 3
AVSSB Analog I/O Buffer Ground P NA 1
VDD_PLL Analog PLL Power P NA 1
VSS_PLL Analog PLL Ground P NA 1
VDD Digital Power P NA 4
VSS Digital Ground P NA 6
VDDB I/O Buffer Power P NA 5
VSSB I/O Buffer Ground P NA 13
VDD_PCI PCI I/O Buffer Power P NA 5
Note:
1. Not including test features.
Listed By Driver Type A sustained tri-state signal is a low active signal that is
driven high for one clock period before it is left floating.
The following table describes the various types of out-
DO, TDO, and TPO are differential output drivers. Their
put drivers used in the Am79C971 controller. All IOL and
characteristics and the one of the XTAL output are de-
IOH values shown in the table apply to 5 V signaling.
scribed in the DC Characteristics section.
See the DC Characteristics section for the values ap-
plying to 3.3 V signaling.
Name Type IOL (mA) IOH (mA) Load (pF)

LED LED 12 -0.4 50
OMII1 Totem Pole 4 -4 50
OMII2 Totem Pole 4 -4 390
O6 Totem Pole 6 -0.4 50
OD6 Open Drain 6 NA 50
STS6 Sustained Tri-State 6 -2 50
TS3 Tri-State 3 -2 50
TS6 Tri-State 6 -2 50
TSMII Tri-State 4 -4 470
Am79C971 17
PIN DESCRIPTIONS eration section for details. The Am79C971 controller
will support a clock frequency of 0 MHz after certain
PCI Interface precautions are taken to ensure data integrity. This
AD[31:0] clock or a derivation is not used to drive any network
functions.
Address and Data Input/Output
Address and data are multiplexed on the same bus in- When RST is active, CLK is an input for NAND tree
terface pins. During the first clock of a transaction, testing.
AD[31:0] contain a physical address (32 bits). During DEVSEL
the subsequent clocks, AD[31:0] contain data. Byte or-
dering is little endian by default. AD[07:0] are defined Device Select Input/Output
as the least significant byte (LSB) and AD[31:24] are The Am79C971 controller drives DEVSEL when it de-
defined as the most significant byte (MSB). For FIFO tects a transaction that selects the device as a target.
data transfers, the Am79C971 controller can be pro- The device samples DEVSEL to detect if a target
grammed for big endian byte ordering. See CSR3, bit 2 claims a transaction that the Am79C971 controller has
(BSWP) for more details. initiated.
During the address phase of the transaction, when the When RST is active, DEVSEL is an input for NAND tree
Am79C971 controller is a bus master, AD[31:2] will ad- testing.
d r e s s t h e a c t i ve D o u bl e Wo r d ( DWo r d ) . Th e
Am79C971 controller always drives AD[1:0] to ’00’ dur- FRAME
ing the address phase indicating linear burst order. Cycle Frame Input/Output
When the Am79C971 controller is not a bus master, the FRAME is driven by the Am79C971 controller when it
AD[31:0] lines are continuously monitored to determine is the bus master to indicate the beginning and duration
if an address match exists for slave transfers. of a transaction. FRAME is asserted to indicate a bus
During the data phase of the transaction, AD[31:0] are transaction is beginning. FRAME is asserted while
driven by the Am79C971 controller when performing data transfers continue. FRAME is deasserted before
bus master write and slave read operations. Data on the final data phase of a transaction. When the
AD[31:0] is latched by the Am79C971 controller when Am79C971 controller is in slave mode, it samples
performing bus master read and slave write operations. FRAME to determine the address phase of a transac-
tion.
When RST is active, AD[31:0] are inputs for NAND tree
testing. When RST is active, FRAME is an input for NAND tree
testing.
C/BE[3:0]
GNT
Bus Command and Byte Enables Input/Output
Bus Grant Input
Bus command and byte enables are multiplexed on the
same bus interface pins. During the address phase of This signal indicates that the access to the bus has
the transaction, C/BE[3:0] define the bus command. been granted to the Am79C971 controller.
During the data phase, C/BE[3:0] are used as byte en- The Am79C971 controller supports bus parking. When
ables. The byte enables define which physical byte the PCI bus is idle and the system arbiter asserts GNT
lanes carry meaningful data. C/BE0 applies to byte 0 without an active REQ from the Am79C971 controller,
(AD[07:0]) and C/BE3 applies to byte 3 (AD[31:24]). the device will drive the AD[31:0], C/BE[3:0] and PAR
The function of the byte enables is independent of the lines.
byte ordering mode (BSWP, CSR3, bit 2).
When RST is active, GNT is an input for NAND tree
When RST is active, C/BE[3:0] are inputs for NAND testing.
tree testing.
IDSEL
CLK
Initialization Device Select Input
Clock Input
This signal is used as a chip select for the Am79C971
This clock is used to drive the system bus interface and controller during configuration read and write transac-
the internal buffer management unit. All bus signals are tions.
sampled on the rising edge of CLK and all parameters
are defined with respect to this edge. The Am79C971 When RST is active, IDSEL is an input for NAND tree
controller normally operates over a frequency range of testing.
10 to 33 MHz on the PCI bus due to networking de- 1. Not including test features.
mands. See the Frequency Demands for Network Op-
18 Am79C971
INTA Table 1. Interrupt Flags
Interrupt Request Output Name Description Mask Bit Interrupt Bit
An attention signal which indicates that one or more of MII Auto-Poll
MAPINT CSR7, bit 6 CSR7, bit 7
the following status flags is set: BABL, EXDINT, IDON, Interrupt
JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, MII
SINT, SLPINT, TINT, TXSTRT, UINT, MCCIINT, MC- Management
MREINT CSR7, bit 8 CSR7, bit 9
CINT, MPDTINT, MAPINT, MREINT, and STINT. Each Frame Read
status flag has either a mask or an enable bit which al- Error Interrupt
lows for suppression of INTA assertion. Table 1 shows Software Timer
STINT CSR7, bit 10 CSR7, bit 11
the flag meanings. Interrupt
By default INTA is an open-drain output. For applica-
tions that need a high-active edge-sensitive interrupt
Table 1. Interrupt Flags signal, the INTA pin can be configured for this mode by
Name Description Mask Bit Interrupt Bit setting INTLEVEL (BCR2, bit 7) to 1.
BABL Babble CSR3, bit 14 CSR0, bit 14 When RST is active, INTA is the output for NAND tree
Excessive testing.
EXDINT CSR5, bit 6 CSR5, bit 7
Deferral
Initialization
IRDY
IDON CSR3, bit 8 CSR0, bit 8
Done Initiator Ready Input/Output
JAB Jabber CSR4, bit 0 CSR4, bit 1 IRDY indicates the ability of the initiator of the transac-
MERR Memory Error CSR3, bit 11 CSR0, bit 11 tion to complete the current data phase. IRDY is used
MISS Missed Frame CSR3, bit 12 CSR0, bit 12 in conjunction with TRDY. Wait states are inserted until
Missed Frame both IRDY and TRDY are asserted simultaneously. A
MFCO Count Over- CSR4, bit 8 CSR4, bit 9 data phase is completed on any clock when both IRDY
flow and TRDY are asserted.
Magic Packet When the Am79C971 controller is a bus master, it as-
MPINT CSR5, bit 3 CSR5, bit 4
Interrupt serts IRDY during all write data phases to indicate that
Receive valid data is present on AD[31:0]. During all read data
RCVCCO Collision Count CSR4, bit 4 CSR4, bit 5 phases, the device asserts IRDY to indicate that it is
Overflow ready to accept the data.
Receive
RINT CSR3, bit 10 CSR0, bit 10 When the Am79C971 controller is the target of a trans-
Interrupt
action, it checks IRDY during all write data phases to
SLPINT Sleep Interrupt CSR5, bit 8 CSR5, bit 9
determine if valid data is present on AD[31:0]. During
SINT System Error CSR5, bit 10 CSR5, bit 11 all read data phases, the device checks IRDY to deter-
Transmit mine if the initiator is ready to accept the data.
TINT CSR3, bit 9 CSR0, bit 9
Interrupt
When RST is active, IRDY is an input for NAND tree
TXSTRT Transmit Start CSR4, bit 2 CSR4, bit 3
testing.
UINT User Interrupt CSR4, bit 7 CSR4, bit 6
Internal MII PAR
Management Parity Input/Output
MCCIINT Command CSR7, bit 2 CSR7, bit 3
Complete Parity is even parity across AD[31:0] and C/BE[3:0].
Interrupt When the Am79C971 controller is a bus master, it gen-
MII erates parity during the address and write data phases.
Management It checks parity during read data phases. When the
MCCINT Command CSR7, bit 4 CSR7, bit 5 Am79C971 controller operates in slave mode, it checks
Complete parity during every address phase. When it is the target
Interrupt of a cycle, it checks parity during write data phases and
MII PHY Detect it generates parity during read data phases.
MPDTINT Transition CSR7, bit 0 CSR7, bit 1
When RST is active, PAR is an input for NAND tree
Interrupt
testing.
Am79C971 19
PERR controller checks STOP to determine if the target wants
to disconnect the current transaction.
Parity Error Input/Output
During any slave write transaction and any master read When RST is active, STOP is an input for NAND tree
transaction, the Am79C971 controller asserts PERR testing.
when it detects a data parity error and reporting of the TRDY
error is enabled by setting PERREN (PCI Command
register, bit 6) to 1. During any master write transaction, Target Ready Input/Output
the Am79C971 controller monitors PERR to see if the TRDY indicates the ability of the target of the transac-
target reports a data parity error. tion to complete the current data phase. Wait states are
inserted until both IRDY and TRDY are asserted simul-
When RST is active, PERR is an input for NAND tree
taneously. A data phase is completed on any clock
testing.
when both IRDY and TRDY are asserted.
REQ When the Am79C971 controller is a bus master, it
Bus Request Input/Output checks TRDY during all read data phases to determine
The Am79C971 controller asserts REQ pin as a signal if valid data is present on AD[31:0]. During all write data
that it wishes to become a bus master. REQ is driven phases, the device checks TRDY to determine if the
high when the Am79C971 controller does not request target is ready to accept the data.
the bus. During Magic Packet mode, the REQ pin will When the Am79C971 controller is the target of a trans-
not be driven. action, it asserts TRDY during all read data phases to
When RST is active, REQ is an input for NAND tree indicate that valid data is present on AD[31:0]. During
testing. all write data phases, the device asserts TRDY to indi-
cate that it is ready to accept the data.
RST
When RST is active, TRDY is an input for NAND tree
Reset testing.
Input
When RST is asserted low, then the Am79C971 con- Board Interface
troller performs an internal system reset of the type Note: Before programming the LED pins, see the
H_RESET (HARDWARE_RESET, see section on RE- description of LEDPE in BCR2, bit 12 first.
SET). RST must be held for a minimum of 30 clock pe-
riods. While in the H_RESET state, the Am79C971
LED0
controller will disable or deassert all outputs. RST may LED0 Output
be asynchronous to clock when asserted or deas- This output is designed to directly drive an LED. By de-
serted. fault, LED0 indicates an active link connection on the
When RST is active, NAND tree testing is enabled. 10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR4). The LED0
SERR pin polarity is programmable, but by default it is active
System Error Input/Output LOW. When the LED0 pin polarity is programmed to
active LOW, the output is an open drain driver. When
During any slave transaction, the Am79C971 controller
the LED0 pin polarity is programmed to active HIGH,
asserts SERR when it detects an address parity error,
the output is a totem pole driver.
and reporting of the error is enabled by setting PER-
REN (PCI Command register, bit 6) and SERREN (PCI Note: The LED0 pin is multiplexed with the EEDI pin.
Command register, bit 8) to 1. When RST is active, LED0 is an input for NAND tree
By default SERR is an open-drain output. For compo- testing.
nent test, it can be programmed to be an active-high LED1
totem-pole output.
LED1 Output
When RST is active, SERR is an input for NAND tree
This output is designed to directly drive an LED. By de-
testing.
fault, LED1 indicates receive activity on the network.
STOP This pin can also be programmed to indicate other net-
work status (see BCR5). The LED1 pin polarity is pro-
Stop Input/Output
grammable, but by default, it is active LOW. When the
In slave mode, the Am79C971 controller drives the LED1 pin polarity is programmed to active LOW, the
STOP signal to inform the bus master to stop the cur- output is an open drain driver. When the LED1 pin po-
rent transaction. In bus master mode, the Am79C971
20 Am79C971
larity is programmed to active HIGH, the output is a LED while an EEPROM is used in the system, then
totem pole driver. buffering is required between the LED3 pin and the
LED circuit. If an LED circuit were directly attached to
Note: The LED1 pin is multiplexed with the EESK and
this pin, it would create an IOL requirement that could
SFBD pins.
not be met by the serial EEPROM attached to this pin.
The LED1 pin is also used during EEPROM Auto- If no EEPROM is included in the system design, then
Detection to determine whether or not an EEPROM is the LED3 signal may be directly connected to an LED
present at the Am79C971 controller interface. At the without buffering. For more details regarding LED con-
last rising edge of CLK while RST is active LOW, LED1 nection, see the section on LED Support.
is sampled to determine the value of the EEDET bit in
BCR19. It is important to maintain adequate hold time Note: The LED3 pin is multiplexed with the EEDO,
around the rising edge of the CLK at this time to ensure SRD, MIIRXFRTGD pins.
a correctly sampled value. A sampled HIGH value When RST is active, LED3 is an input for NAND tree
means that an EEPROM is present, and EEDET will be testing.
set to 1. A sampled LOW value means that an EE-
PROM is not present, and EEDET will be set to 0. See SLEEP
the EEPROM Auto-Detection section for more details. Sleep Input
If no LED circuit is to be attached to this pin, then a pull When SLEEP is asserted, the Am79C971 controller
up or pull down resistor must be attached instead in performs an internal system reset of the H_RESET
order to resolve the EEDET setting. type and then proceeds into a power savings mode. All
Am79C971 controller outputs will be placed in their
When RST is active, LED1 is an input for NAND tree normal reset condition. All Am79C971 controller inputs
testing. will be ignored except for the SLEEP pin itself. The sys-
WARNING: The input signal level of LED1 must be tem must refrain from starting the network operations
insured for correct EEPROM detection before the of the Am79C971 controller for 0.5 seconds following
deassertion of RST. the deassertion of the SLEEP pin in order to allow in-
ternal analog circuits to stabilize.
LED2
For effects with the Magic Packet™ modes, see the
LED2 Output Magic Packet section.
This output is designed to directly drive an LED. By de-
Both CLK and XTAL1 inputs must have valid clock sig-
fault, LED2 indicates correct receive polarity on the
nals present in order for the SLEEP command to take
10BASE-T interface. This pin can also be programmed
effect.
to indicate other network status (see BCR6). The LED2
pin polarity is programmable, but by default it is active The SLEEP pin should not be asserted during power
LOW. When the LED2 pin polarity is programmed to supply ramp up. If it is desired that SLEEP be asserted
active LOW, the output is an open drain driver. When at power supply ramp up, then the system must delay
the LED2 pin polarity is programmed to active HIGH, the assertion of SLEEP until three clock cycles after the
the output is a totem pole driver. completion of hardware reset.
Note: The LED2 pin is multiplexed with the SRDCLK WARNING: The SLEEP pin must not be left uncon-
pin and the MIIRXFRTGE pins. nected. It should be tied to VDD if the power saving
When RST is active, LED2 is an input for NAND tree mode is not used.
testing. Note: The SLEEP pin is multiplexed with the EAR pin.
LED3 When RST is active, SLEEP is an input for NAND tree
testing.
LED3 Output
This output is designed to directly drive an LED. By de- XTAL1
fault, LED3 indicates transmit activity on the network. Crystal Oscillator In Input
This pin can also be programmed to indicate other net-
The internal clock generator uses a 20-MHz crystal that
work status (see BCR7). The LED3 pin polarity is pro-
is attached to the pins XTAL1 and XTAL2. The network
grammable, but by default it is active LOW. When the
data rate is one-half of the crystal frequency. XTAL1
LED3 pin polarity is programmed to active LOW, the
may alternatively be driven using an external 20-MHz
output is an open drain driver. When the LED3 pin po-
CMOS level clock signal. Refer to the section on Exter-
larity is programmed to active HIGH, the output is a
nal Crystal Characteristics for more details. This clock
totem pole driver.
is always required whether or not the inter nal
Special attention must be given to the external circuitry 10BASE-T/AUI ports are enabled. If the internal PHY is
attached to this pin. When this pin is used to drive an
Am79C971 21
not used, ±10% accuracy is sufficient for the clock Note: The EEDO pin is multiplexed with the LED3,
source. MIIRXFRTGD, and SRD pins.
Note: When the Am79C971 controller is in coma When RST is active, EEDO is an input for NAND tree
mode, there is an internal 22 kΩ resistor from XTAL1 to testing.
ground. If an external source drives XTAL1, some
EESK
power consumption will be consumed driving this resis-
tor. If XTAL1 is driven LOW at this time, power con- EEPROM Serial clock Input/Output
sumption will be minimized. In this case, XTAL1 must This pin is designed to directly interface to a serial
remain active for at least 30 cycles after the assertion EEPROM that uses the 93C46 EEPROM interface pro-
of SLEEP and deassertion of REQ. tocol. EESK is connected to the EEPROM’s clock pin.
XTAL2 It is controlled by either the Am79C971 controller di-
rectly during a read of the entire EEPROM, or indirectly
Crystal Oscillator Out Output by the host system by writing to BCR19, bit 1.
The internal clock generator uses a 20-MHz crystal that
Note: The EESK pin is multiplexed with the LED1 and
is attached to the pins XTAL1 and XTAL2. The network
SFBD pins.
data rate is one-half of the crystal frequency. If an ex-
ternal clock source is used on XTAL1, then XTAL2 The EESK pin is also used during EEPROM Auto-
should be left unconnected. Detection to determine whether or not an EEPROM is
present at the Am79C971 controller interface. At the
EEPROM Interface rising edge of the last CLK edge while RST is asserted,
EECS EESK is sampled to determine the value of the EEDET
bit in BCR19. A sampled HIGH value means that an
EEPROM Chip Select Output EEPROM is present, and EEDET will be set to 1. A
This pin is designed to directly interface to a serial EE- sampled LOW value means that an EEPROM is not
PROM that uses the 93C46 EEPROM interface proto- present, and EEDET will be set to 0. See the EEPROM
col. EECS is connected to the EEPROM’s chip select Auto-Detection section for more details.
pin. It is controlled by either the Am79C971 controller
If no LED circuit is to be attached to this pin, then a pull
during command portions of a read of the entire EE-
up or pull down resistor must be attached instead to re-
PROM, or indirectly by the host system by writing to
solve the EEDET setting.
BCR19, bit 2.
When RST is active, EESK is an input for NAND tree
When RST is active, EECS is an input for NAND tree
testing.
testing.
WARNING: The input signal level of EESK must be
EEDI valid for correct EEPROM detection before the
EEPROM Data In Output deassertion of RST.
This pin is designed to directly interface to a serial
Expansion Bus Interface
EEPROM that uses the 93C46 EEPROM interface pro-
tocol. EEDI is connected to the EEPROM’s data input EBUA_EBA[7:0]
pin. It is controlled by either the Am79C971 controller Expansion Bus Upper Address/
during command portions of a read of the entire Expansion Bus Address [7:0] Output
EEPROM, or indirectly by the host system by writing to
The EBUA_EBA[7:0] pins provide the least and most
BCR19, bit 0.
significant bytes of address on the Expansion Bus. The
Note: The EEDI pin is multiplexed with the LED0 pin. most significant address byte (address bits [15:8] dur-
When RST is active, EEDI is an input for NAND tree ing SRAM accesses; address bits [19:16] during boot
testing. device accesses) is valid on these pins at the beginning
of an SRAM or boot device access, at the rising edge
EEDO of AS_EBOE. This upper address byte must be stored
EEPROM Data Out Input externally in a D flip-flop. During subsequent cycles of
an SRAM or boot device access, address bits [7:0] are
This pin is designed to directly interface to a serial
present on these pins.
EEPROM that uses the 93C46 EEPROM interface pro-
tocol. EEDO is connected to the EEPROM’s data out- All EBUA_EBA[7:0] outputs are forced to a constant
put pin. It is controlled by either the Am79C971 level to conserve power while no access on the Expan-
controller during command portions of a read of the en- sion Bus is being performed.
tire EEPROM, or indirectly by the host system by read-
ing from BCR19, bit 0.
22 Am79C971
EBDA[15:8] clock used to drive the Expansion Bus cycles depends
on the values of the EBCS and CLK_FAC settings in
Expansion Bus Data/Address [15:8] Input/Output
BCR27. Refer to the SRAM Interface Bandwidth Re-
When ERAMCS is asserted, EBDA[15:8] contain the quirements section for details on determining the re-
data bits [15:8] for SRAM accesses. When EROMCS is quired EBCLK frequency. If a clock source other than
asserted low, EBDA[15:8] contain address bits [15:8] the EBCLK pin is programmed (BCR27, bits 5:3) to be
for boot device accesses. used to run the Expansion Bus interface, this input
The EBDA[15:8] signals are driven to a constant level should be tied to VDD through a 4.7 kΩ resistor.
to conserve power while no access on the Expansion EBCLK is not used to drive the bus interface, internal
Bus is being performed. buffer management unit, or the network functions.
EBD[7:0] Media Independent Interface
Expansion Bus Data [7:0] Input/Output TX_CLK
The EBD[7:0] pins provide data bits [7:0] for RAM/ROM
Transmit Clock Input
accesses. The EBD[7:0] signals are internally forced to
a constant level to conserve power while no access on TX_CLK is a continuous clock input that provides the
the Expansion Bus is being performed. timing reference for the transfer of the TX_EN,
TXD[3:0], and TX_ER signals out of the Am79C971
EROMCS device. TX_CLK must provide a nibble rate clock (25%
Expansion ROM Chip Select Output of the network data rate). Hence, an MII transceiver op-
erating at 10 Mbps must provide a TX_CLK frequency
EROMCS serves as the chip select for the boot device.
of 2.5 MHz and an MII transceiver operating at 100
It is asserted low during the data phases of boot device
Mbps must provide a TX_CLK frequency of 25 MHz.
accesses.
Note: The TX_CLK pin is multiplexed with the TXCLK
ERAMCS pin.
Expansion RAM Chip Select Output When RST is active, TX_CLK is an input for NAND tree
ERAMCS is asserted during SRAM read and write op- testing.
erations on the expansion bus.
If the MII port is not selected, the TX_CLK pin can be
AS_EBOE left floating.
Address Strobe/Expansion Bus TXD[3:0]
Output Enable Output
Transmit Data Output
AS_EBOE functions as the address strobe for the
upper address bits on the EBUA_EBA[7:0] pins and as TXD[3:0] is the nibble-wide MII transmit data bus. Valid
the output enable for the Expansion Bus. data is generated on TXD[3:0] on every TX_CLK rising
edge while TX_EN is asserted. While TX_EN is de-
As an address strobe, a rising edge on AS_EBOE is asserted, TXD[3:0] values are driven to a 0. TXD[3:0]
supplied at the beginning of SRAM and boot device transitions synchronous to TX_CLK rising edges.
accesses. This rising edge provides a clock edge for a
‘374 D-type edge-triggered flip-flop which must store Note: The TXD[0] pin is multiplexed with the TXDAT
the upper address byte during Expansion Bus ac- pin.
cesses for EPROM/Flash/SRAM. When RST is active, TXD[3:0] are inputs for NAND tree
testing.
AS_EBOE is asserted active LOW during boot device
and SRAM read operations on the expansion bus and If the MII port is not selected, the TXD[3:0] pins can be
is deasserted during boot device and SRAM write left floating.
operations.
TX_EN
EBWE Transmit Enable Output
Expansion Bus Write Enable Output TX_EN indicates when the Am79C971 device is pre-
EBWE provides the write enable for write accesses to senting valid transmit nibbles on the MII. While TX_EN
the SRAM devices and/or Flash device. is asserted, the Am79C971 device generates TXD[3:0]
and TX_ER on TX_CLK rising edges. TX_EN is as-
EBCLK serted with the first nibble of preamble and remains as-
Expansion Bus Clock Input serted throughout the duration of a packet until it is
EBCLK may be used as the fundamental clock to drive deasserted prior to the first TX_CLK following the final
the Expansion Bus access cycles. The actual internal
Am79C971 23
nibble of the frame. TX_EN transitions synchronous to nal PHY switches the RX_CLK and TX_CLK, it must
TX_CLK rising edges. provide glitch-free clock pulses.
Note: The TX_EN pin is multiplexed with the TXEN Note: The RX_CLK pin is multiplexed with the RXCLK
pin. pin.
When RST is active, TX_EN is an input for NAND tree When RST is active, RX_CLK is an input for NAND tree
testing. testing.
If the MII port is not selected, the TX_EN pin can be left If the MII port is not selected, the RX_CLK pin can be
floating. left floating.
TX_ER RXD[3:0]
Transmit Error Output Receive Data Input
TX_ER is an output that, if asserted while TX_EN is as- RXD[3:0] is the nibble-wide MII receive data bus. Data
serted, instructs the MII PHY device connected to the on RXD[3:0] is sampled on every rising edge of
Am79C971 device to transmit a code group error. RX_CLK while RX_DV is asserted. RXD[3:0] is ignored
TX_ER is unused and is reserved for future use and will while RX_DV is de-asserted.
always be driven to a logical zero.
When the EADI is enabled (EADISEL, BCR2, bit 3) and
When RST is active, TX_ER is an input for NAND tree the Receive Frame Tagging is enabled (RXFRTG,
testing. CSR7, bit 14) and the MII is not selected, the RXD[0]
pin becomes a data input pin for the Receive Frame
If the MII port is not selected, the TX_ER pin can be left
Tag (RXFRTGD). See the Receive Frame Tagging sec-
floating.
tion for details.
COL Note: The RXD[0] pin is multiplexed with the
Collision Input RXFRTGD pin.
COL is an input that indicates that a collision has been When RST is active, RXD[3:0] are inputs for NAND tree
detected on the network medium. testing.
Note: The COL pin is multiplexed with the CLSN pin. If the MII port is not selected, the RXS[3:0] pin can be
When RST is active, COL is an input for NAND tree left floating.
testing. RX_DV
If the MII port is not selected, the COL pin can be left Receive Data Valid Input
floating.
RX_DV is an input used to indicate that valid received
CRS data is being presented on the RXD[3:0] pins and
RX_CLK is synchronous to the receive data. In order
Carrier Sense Input
for a frame to be fully received by the Am79C971 de-
CRS is an input that indicates that a non-idle medium, vice on the MII, RX_DV must be asserted prior to the
due either to transmit or receive activity, has been de- RX_CLK rising edge, when the first nibble of the Start
tected. of Frame Delimiter is driven on RXD[3:0], and must re-
Note: The CRS pin is multiplexed with the RXEN pin. main asserted until after the rising edge of RX_CLK,
when the last nibble of the CRC is driven on RXD[3:0].
When RST is active, CRS is an input for NAND tree RX_DV must then be deasserted prior to the RX_CLK
testing. rising edge which follows this final nibble. RX_DV tran-
If the MII port is not selected, the CRS pin can be left sitions are synchronous to RX_CLK rising edges.
floating. When the EADI is enabled (EADISEL, BCR2, bit 3), the
RX_CLK Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is not selected, the RX_DV pin be-
Receive Clock Input comes a data input enable pin for the Receive Frame
RX_CLK is a clock input that provides the timing refer- Tag (RXFRTGE). See the Receive Frame Tagging sec-
ence for the transfer of the RX_DV, RXD[3:0], and tion for details.
RX_ER signals into the Am79C971 device. RX_CLK
must provide a nibble rate clock (25% of the network Note: The RX_DV pin is multiplexed with the
data rate). Hence, an MII transceiver operating at 10 RXFRTGE pin.
Mbps must provide an RX_CLK frequency of 2.5 MHz When RST is active, RX_DV is an input for NAND tree
and an MII transceiver operating at 100 Mbps must pro- testing.
vide an RX_CLK frequency of 25 MHz. When the exter-
24 Am79C971
If the MII port is not selected, the RX_DV pin can be left Attachment Unit Interface
floating.
CI±
RX_ER Collision In Input
Receive Error Input CI± is a differential input pair signaling the Am79C971
RX_ER is an input that indicates that the MII trans- controller that a collision has been detected on the net-
ceiver device has detected a coding error in the receive work media, indicated by the CI± inputs being driven
frame currently being transferred on the RXD[3:0] pins. with a 10-MHz pattern of sufficient amplitude and pulse
When RX_ER is asserted while RX_DV is asserted, a width to meet ISO 8802-3 (IEEE/ANSI 802.3) stan-
CRC error will be indicated in the receive descriptor for dards. CI± operates at pseudo ECL levels.
the incoming receive frame. RX_ER is ignored while
If the CI± pins are not used, they should be tied to-
RX_DV is deasserted. Special code groups generated
gether.
on RXD while RX_DV is deasserted are ignored (e.g.,
Bad SSD in TX and IDLE in T4). RX_ER transitions are DI±
synchronous to RX_CLK rising edges.
Data In Input
Note: The RX_ER pin is multiplexed with the RXDAT DI± is a differential input pair to the Am79C971 control-
pin. ler carrying Manchester encoded data from the net-
When RST is active, RX_ER is an input for NAND tree work. DI± operates at pseudo ECL levels.
testing.
If the DI± pins are not used, they should be tied to-
If the MII port is not selected, the RX_ER pin can be left gether.
floating.
DO±
MDC Data Out Output
Management Data Clock Output DO± is a differential output pair from the Am79C971
MDC is a non-continuous clock output that provides a controller for transmitting Manchester encoded data to
timing reference for bits on the MDIO pin. During MII the network. DO± operates at pseudo ECL levels.
management port operations, MDC runs at a nominal
If the AUI is not used, DO± should be left floating for
frequency of 2.5 MHz. When no management opera-
minimum power consumption.
tions are in progress, MDC is driven LOW. The MDC is
derived from the external 20-MHz crystal. 10BASE-T Interface
If the MII port is not selected, the MDC pin can be left RXD±
floating.
10BASE-T Receive Data Input
MDIO RXD± are 10BASE-T port differential receivers. If the
Management Data I/O Input/Output 10BASE-T interface is not used in a design, RXD+ and
RXD- should be connected to each other.
MDIO is the bidirectional MII management port data
pin. MDIO is an output during the header portion of the TXD±
management frame transfers and during the data por-
10BASE-T Transmit Data Output
tions of write transfers. MDIO is an input during the
data portions of read data transfers. When an operation TXD± are 10BASE-T port differential drivers.
is not in progress on the management port, MDIO is not TXP±
driven. MDIO transitions from the Am79C971 controller
are synchronous to MDC Falling edges. 10BASE-T Pre-Distortion Control Output
These outputs provide transmit pre-distortion control in
If the PHY is attached through an MII physical connec-
conjunction with the 10BASE-T port differential drivers.
tor, then the MDIO pin should be externally pulled down
to V SS with a 10-kΩ ±5% resistor. If the PHY is on General Purpose Serial Interface
board, then the MDIO pin should be externally pulled
up to VCC with a 10-kΩ ±5% resistor.
CLSN
Collision Input
When RST is active, MDIO is an input for NAND tree
testing. CLSN is an input that indicates a collision has occurred
on the network.
Note: The CLSN pin is multiplexed with the COL pin.
When RST is active, CLSN is an input for NAND tree
testing.
Am79C971 25
RXCLK TXEN
Receive Clock Input Transmit Enable Output
RXCLK is an input. The rising edges of the RXCLK sig- TXEN is an output that provides an enable signal for
nal are used to sample the data on the RXDAT input transmission. Data on the TXDAT pin is not valid unless
whenever the RXEN input is HIGH. the TXEN signal is HIGH.
Note: The RXCLK pin is multiplexed with the RX_CLK Note: The TXEN pin is multiplexed with the TX_EN
pin. pin.
When RST is active, RXCLK is an input for NAND tree When RST is active, TXEN is an input for NAND tree
testing. testing.
RXDAT External Address Detection Interface
Receive Data Input EAR
RXDAT is an input. The rising edges of the RXCLK sig- External Address Reject Low Input
nal are used to sample the data on the RXDAT input
The incoming frame will be checked against the inter-
whenever the RXEN input is HIGH.
nally active address detection mechanisms and the re-
Note: The RXDAT pin is multiplexed with the RX_ER sult of this check will be OR’d with the value on the EAR
pin. pin. The EAR pin is defined as REJECT. The pin value
When RST is active, RXDAT is an input for NAND tree is OR’d with the internal address detection result to de-
testing. termine if the current frame should be accepted or re-
jected.
RXEN
The EAR pin must not be left unconnected, it should
Receive Enable Input be tied to VDD through a resistor.
RXEN is an input. When this signal is HIGH, it indicates
Note: The EAR pin is multiplexed with the SLEEP pin.
to the core logic that the data on the RXDAT input pin
is valid. When RST is active, EAR is an input for NAND tree
testing.
Note: The RXEN pin is multiplexed with the CRS pin.
When RST is active, RXEN is an input for NAND tree
SFBD
testing. Start Frame-Byte Delimiter Output
For the Internal PHY during External Address
TXCLK
Detection:
Transmit Clock Input
An initial rising edge on the SFBD signal indicates that
TXCLK is an input that provides a clock signal for MAC a start of frame delimiter has been detected. The serial
activity, both transmit and receive. The rising edges of bit stream will follow on the SRD signal, commencing
the TXCLK can be used to validate TXDAT output data. with the destination address field. SFBD will go high for
Note: The TXCLK pin is multiplexed with the TX_CLK 4 bit times (400 ns when operating at 10 Mbps) after
pin. detecting the second “1” in the SFD (Start of Frame De-
limiter) of a received frame. SFBD will subsequently
When RST is active, TXCLK is an input for NAND tree
toggle every 4 bit times (1.25 MHz frequency when op-
testing.
erating at 10 Mbps) with each rising edge indicating the
TXDAT first bit of each subsequent byte of the received serial
bit stream. See the EADI Rejection Timing with Internal
Transmit Data Output
PHY timing diagram for details. SFBD will be active
TXDAT is an output that provides the serial bit stream only during frame reception.
for transmission, including preamble, SFD, data, and
FCS field, if applicable. For the External PHY attached to the Media Inde-
pendent Interface during External Address Detec-
Note: The TXDAT pin is multiplexed with the TXD[0] tion:
pin.
An initial rising edge on the SFBD signal indicates that
When RST is active, TXDAT is an input for NAND tree
a start of valid data is present on the RXD[3:0] pins.
testing.
SFBD will go high for one nibble time (400 ns when op-
erating at 10 Mbps and 40 ns when operating at 100
Mbps) one RX_CLK period after RX_DV has been as-
serted and RX_ER is deasserted and the detection of
26 Am79C971
the SFD (Start of Frame Delimiter) of a received frame. Note also that the SRDCLK pin is multiplexed with the
Data on the RXD[3:0] will be the start of the destination LED2 pin.
address field. SFBD will subsequently toggle every nib-
When RST is active, SRDCLK is an input for NAND
ble time (1.25 MHz frequency when operating at 10
tree testing.
Mbps and 12.5 MHz frequency when operating at 100
Mbps) indicating the first nibble of each subsequent RXFRTGD
byte of the received nibble stream. The RX_CLK
Receive Frame Tag Data Input
should be used in conjunction with the SFBD to latch
the correct data for external address matching. SFBD When the EADI is enabled (EADISEL, BCR2, bit 3), the
will be active only during frame reception. Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is not selected, the RXFRTGD pin
Note: The SFBD pin is multiplexed with the EESK and becomes a data input pin for the Receive Frame Tag.
LED1 pins. See the Receive Frame Tagging section for details.
When RST is active, SFBD is an input for NAND tree Note: The RXFRTGD pin is multiplexed with the
testing. RXD[0] pin.
SRD When RST is active, RXFRTGD is an input for NAND
Serial Receive Data Input/Output tree testing.
SRD is the decoded NRZ data from the network. This RXFRTGE
signal can be used for external address detection.
Receive Frame Tag Enable Input
When the 10BASE-T port is selected, transitions on
SRD will only occur during receive activity. When the When the EADI is enabled (EADISEL, BCR2, bit 3), the
AUI port is selected, transitions on SRD will occur dur- Receive Frame Tagging is enabled (RXFRTG, CSR7,
ing both transmit and receive activity. bit 14), and the MII is not selected, the RXFRTGE pin
becomes a data input enable pin for the Receive Frame
When the EADI is enabled (EADISEL, BCR2, bit 3) and Tag. See the Receive Frame Tagging section for de-
the Receive Frame Tagging is enabled (RXFRTG, tails.
CSR7, bit 14) and the MII is selected, the SRD pin be-
comes a data input pin for the Receive Frame Tag (MI- Note: The RXFRTGE pin is multiplexed with the
IRXFRTGD). See the Receive Frame Tagging section RX_DV pin.
for details. When RST is active, RXFRTGE is an input for NAND
tree testing.
Note: When the MII port is selected, SRD will not gen-
erate transitions and receive data must be derived from MIIRXFRTGD
the Media Independent Interface RXD[3:0] pins.
MII Receive Frame Tag Enable Input/Output
Note also that the SRD pin is multiplexed with the
When the EADI is enabled (EADISEL, BCR2, bit 3), the
EEDO and LED3 pins.
Receive Frame Tagging is enabled (RXFRTG, CSR7,
When RST is active, SRD is an input for NAND tree bit 14), and the MII is selected, the MIIRXFRTGD pin
testing. becomes a data input pin for the Receive Frame Tag.
See the Receive Frame Tagging section for details.
SRDCLK
Note: The MIIRXFRTGD pin is multiplexed with the
Serial Receive Data Clock Input/Output
SRD pin.
Serial Receive Data is synchronous with reference to
SRDCLK. When the 10BASE-T port is selected, transi- When RST is active, MIIRXFRTGD is an input for
tions on SRDCLK will only occur during receive activity. NAND tree testing.
When the AUI port is selected, transitions on SRDCLK MIIRXFRTGE
will occur during both transmit and receive activity.
MII Receive Frame Tag Enable Input/Output
When the EADI is enabled (EADISEL, BCR2, bit 3), the When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7, Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is selected, the SRDCLK pin be- bit 14), and the MII is selected, the MIIRXFRTGE pin
comes a data input enable pin for the Receive Frame becomes a data input enable pin for the Receive Frame
Tag (MIIRXFRTGE). See the Receive Frame Tagging Tag. See the Receive Frame Tagging section for de-
section for details. tails.
Note: When the MII port is selected, SRDCLK will not Note: The MIIRXFRTGE pin is multiplexed with the
generate transitions and the receive clock must be de- SRDCLK pin.
rived from the MII RX_CLK pin.
Am79C971 27
When RST is active, MIIRXFRTGE is an input for VDD_PLL
NAND tree testing.
PLL Power (1 Pin) Power
IEEE 1149.1 (1990) Test Access Port There is one analog PLL +5 V supply pin. Special at-
Interface tention should be paid to the printed circuit board layout
to avoid excessive noise on this line. Refer to Appendix
TCK B, Recommendation for Power and Ground Decou-
Test Clock Input pling, for details.
TCK is the clock input for the boundary scan test mode
VSS_PLL
operation. It can operate at a frequency of up to 10
MHz. TCK has an internal pull up resistor. PLL Ground (1 Pin) Power
There is one analog PLL ground pin. Special attention
TDI should be paid to the printed circuit board layout to
Test Data In Input avoid excessive noise on this line. Refer to Appendix B,
TDI is the test data input path to the Am79C971 con- Recommendation for Power and Ground Decoupling,
troller. The pin has an internal pull up resistor. for details.
TDO VDDB
Test Data Out Output I/O Buffer Power (5 Pins) Power
TDO is the test data output path from the Am79C971 There are five power supply pins that are used by the
controller. The pin is tri-stated when the JTAG port is in- input/output buffer drivers. All VDDB pins must be con-
active. nected to a +5 V supply.
TMS VSSB
Test Mode Select Input I/O Buffer Ground (13 Pins) Power
A serial input bit stream on the TMS pin is used to de- There are thirteen ground pins that are used by the PCI
fine the specific boundary scan test to be executed. bus input/output buffer drivers.
The pin has an internal pull up resistor.
VDD_PCI
Power Supply Pins PCI I/O Buffer Power (5 Pins) Power
AVDDB There are five power supply pins that are used by the
Analog Power (3 Pins) Power PCI input/output buffer drivers. In a system with +5 V
signaling environment, all VDD_PCI pins must be con-
There are three analog +5 V supply pins that provide nected to a +5 V supply. In a system with +3.3 V signal-
power for the Twisted Pair and AUI drivers. Hence, they ing environment, all VDD_PCI pins must be connected
are very noisy. Special attention should be paid to the to a +3.3 V supply.
printed circuit board layout to avoid excessive noise on
these lines. Refer to Appendix B, Recommendation for VDD
Power and Ground Decoupling, for details. Digital Power (4 Pins) Power
AVSSB There are four power supply pins that are used by the
Analog Ground (1 Pins) Power internal digital circuitry. All VDD pins must be con-
nected to a +5 V supply.
There is one analog ground pin that provides ground
for the Twisted Pair and AUI drivers. Hence, it is very VSS
noisy. Special attention should be paid to the printed Digital Ground (6 Pins) Power
circuit board layout to avoid excessive noise on these
lines. Refer to Appendix B, Recommendation for Power There are six ground pins that are used by the internal
and Ground Decoupling, for details. digital circuitry.
28 Am79C971
BASIC FUNCTIONS ing status, and to request particular functions to be ex-
ecuted by the Am79C971 controller.
System Bus Interface
The third portion of the software interface is the de-
The Am79C971 controller is designed to operate as a
scriptor and buffer areas that are shared between the
bus master during normal operations. Some slave I/O
software and the Am79C971 controller during normal
accesses to the Am79C971 controller are required in
network operations. The descriptor area boundaries
nor mal operations as well. Initialization of the
are set by the software and do not change during nor-
Am79C971 controller is achieved through a combina-
mal network operations. There is one descriptor area
tion of PCI Configuration Space accesses, bus slave
for receive activity and there is a separate area for
accesses, bus master accesses, and an optional read
transmit activity. The descriptor space contains relocat-
of a ser ial EEPROM that is perfor med by the
able pointers to the network frame data, and it is used
Am79C971 controller. The EEPROM read operation is
to transfer frame status from the Am79C971 controller
performed through the 93C46 EEPROM interface. The
to the software. The buffer areas are locations that hold
ISO 8802-3 (IEEE/ANSI 802.3) Ethernet Address may
frame data for transmission or that accept frame data
reside within the serial EEPROM. Some Am79C971
that has been received.
controller configuration registers may also be pro-
grammed by the EEPROM read operation. Network Interfaces
The Address PROM, on-chip board-configuration reg- The Am79C971 controller can be connected to an
isters, and the Ethernet controller registers occupy 32 IEEE 802.3 or proprietary network via one of four net-
bytes of address space. I/O and memory mapped I/O work interfaces. The Media Independent Interface (MII)
accesses are supported. Base Address registers in the provides an IEEE 802.3-compliant nibble-wide inter-
PCI configuration space allow locating the address face to an external 100- and/or 10-Mbps transceiver
space on a wide variety of starting addresses. device. The Attachment Unit Interface (AUI) provides
an ISO 8802-3 (IEEE/ANSI 802.3) defined differential
For diskless stations, the Am79C971 controller sup-
interface. On-board MAU and or off-board MAU con-
ports a ROM or Flash-based (both referred to as the
nection with or without an AUI cable is supported. The
Expansion ROM throughout this specification) boot de-
10BASE-T interface provides a twisted-pair Ethernet
vice of up to 1 Mbyte in size. The host can map the boot
port, which is ISO 8802-3 (IEEE/ANSI 802.3)-compli-
device to any memory address that aligns to a 1-Mbyte
ant, and contains the auto-negotiation capability, which
boundary by modifying the Expansion ROM Base Ad-
is IEEE 802.3u-compliant. The General Purpose Serial
dress register in the PCI configuration space.
Interface (GPSI) allows bypassing the Manchester
Software Interface Encoder/Decoder (MENDEC) and is functionally equiv-
alent to the GPSI found on the LANCE.
The software interface to the Am79C971 controller is
divided into three parts. One part is the PCI configura- While in auto-selection mode, the interface in use is de-
tion registers used to identify the Am79C971 controller termined by the Network Port Manager. If the quiescent
and to setup the configuration of the device. The setup state of the MII MDIO pin is HIGH, the MII is activated.
information includes the I/O or memory mapped I/O If the MII MDIO pin is LOW, the Am79C971 device
base address, mapping of the Expansion ROM, and checks the link status on the 10BASE-T port. If the
the routing of the Am79C971 controller interrupt chan- 10BASE-T link status is good, the 10BASE-T port is se-
nel. This allows for a jumperless implementation. lected. If there is no active link status, then the device
assumes an AUI connection. The 10BASE-T port will
The second portion of the software interface is the di-
continue to monitor the link status while the AUI is ac-
rect access to the I/O resources of the Am79C971 con-
tive. The software driver can override this automatic
troller. The Am79C971 controller occupies 32 bytes of
configuration at anytime by disabling the auto-selection
address space that must begin on a 32-byte block
and forcing a network port to be attached to the internal
boundary. The address space can be mapped into I/O
MAC. The GPSI port can only be enabled by disabling
or memory space (memory mapped I/O). The I/O Base
the auto-selection and manually selecting the GPSI as
Address Register in the PCI Configuration Space con-
the network port.
trols the start address of the address space if it is
mapped to I/O space. The Memory Mapped I/O The Am79C971 controller supports half-duplex and
Base Address Register controls the start address of full-duplex operation on all four network interfaces (i.e.,
the address space if it is mapped to memory space. AUI, 10BASE-T, GPSI, and MII).
The 32-byte address space is used by the software to
program the Am79C971 controller operating mode, to
enable and disable various features, to monitor operat-
Am79C971 29
DETAILED FUNCTIONS select the DWord location in the configuration space.
The Am79C971 controller ignores AD[10:8], because it
Slave Bus Interface Unit is a single function device. AD[31:11] are don’t care.
The slave bus interface unit (BIU) controls all accesses
AD31 AD10 AD7
to the PCI configuration space, the Control and Status AD1 AD0
AD11 AD8 AD2
Registers (CSR), the Bus Configuration Registers
DWord
(BCR), the Address PROM (APROM) locations, and Don’t care Don’t care 0 0
index
the Expansion ROM. Table 2 shows the response of
the Am79C971 controller to each of the PCI commands The active bytes within a DWord are determined by the
in slave mode. byte enable signals. Eight-bit, 16-bit, and 32-bit trans-
fers are supported. DEVSEL is asserted two clock cy-
c le s af ter t he ho s t h as as s e r te d F R AM E . A ll
Table 2. Slave Commands c on fi gu rat io n c y c l es a re o f fi xe d le ng th . T h e
Am79C971 controller will assert TRDY on the third
C[3:0] Command Use
clock of the data phase.
Interrupt
0000 Not used The Am79C971 controller does not support burst trans-
Acknowledge
fers for access to configuration space. When the host
0001 Special Cycle Not used keeps FRAME asserted for a second data phase, the
Read of CSR, BCR, APROM, Am79C971 controller will disconnect the transfer.
0010 I/O Read
and Reset registers When the host tries to access the PCI configuration
Write to CSR, BCR, and space while the automatic read of the EEPROM after
0011 I/O Write H_RESET (see section on RESET) is on-going, the
APROM
Am79C971 controller will terminate the access on the
0100 Reserved PCI bus with a disconnect/retry response.
0101 Reserved The Am79C971 controller supports fast back-to-back
Memory mapped I/O read of transactions to different targets. This is indicated by the
CSR, BCR, APROM, and Fast Back-To-Back Capable bit (PCI Status register, bit
0110 Memory Read
Reset registers 7), which is hardwired to 1. The Am79C971 controller
Read of the Expansion Bus is capable of detecting a configuration cycle even when
its address phase immediately follows the data phase
Memory mapped I/O write of
0111 Memory Write of a transaction to a different target without any idle
CSR, BCR, and APROM
state in-between. There will be no contention on the
1000 Reserved DEVSEL, TRDY, and STOP signals, since the
1001 Reserved Am79C971 controller asserts DEVSEL on the second
clock after FRAME is asserted (medium timing).
Configuration Read of the Configuration
1010 Slave I/O Transfers
Read Space
Configuration Write to the Configuration After the Am79C971 controller is configured as an I/O
1011 device by setting IOEN (for regular I/O mode) or
Write Space
MEMEN (for memory mapped I/O mode) in the PCI
Memory Read Command register, it starts monitoring the PCI bus for
1100 Aliased to Memory Read
Multiple
access to its CSR, BCR, or APROM locations. If con-
Dual Address figured for regular I/O mode, the Am79C971 controller
1101 Not used
Cycle will look for an address that falls within its 32 bytes of I/
O address space (starting from the I/O base address).
Memory Read
1110 Aliased to Memory Read The Am79C971 controller asserts DEVSEL if it detects
Line
an address match and the access is an I/O cycle. If
Memory Write configured for memor y mapped I/O mode, the
1111 Aliased to Memory Write
Invalidate Am79C971 controller will look for an address that falls
within its 32 bytes of memory address space (starting
Slave Configuration Transfers from the memory mapped I/O base address). The
The host can access the Am79C971 PCI configuration Am79C971 controller asserts DEVSEL if it detects an
space with a configuration read or write command. The address match and the access is a memory cycle.
Am79C971 controller will assert DEVSEL during the DEVSEL is asserted two clock cycles after the host has
address phase when IDSEL is asserted, AD[1:0] are asserted FRAME. See Figure 1 and Figure 2.
both 0, and the access is a configuration cycle. AD[7:2]
30 Am79C971
since the internal Buffer Management Unit clock is a di-
vide-by-two version of the CLK signal.
CLK
The Am79C971 controller does not support burst trans-
1 2 3 4 5 6 7 fers for access to its I/O resources. When the host
keeps FRAME asserted for a second data phase, the
FRAME
Am79C971 controller will disconnect the transfer.
AD ADDR DATA
C/BE 1010 BE
CLK
PAR PAR PAR 1 2 3 4 5 6 7
FRAME
IRDY
AD ADDR DATA
TRDY
C/BE 1011 BE
DEVSEL
PAR PAR PAR

STOP
IRDY
IDSEL
TRDY
DEVSEL is sampled
20550D-4 DEVSEL
STOP
Figure 1. Slave Configuration Read
IDSEL
The Am79C971 controller will not assert DEVSEL if it

detects an address match, but the PCI command is not 20550D-5
of the correct type. In memory mapped I/O mode, the
Figure 2. Slave Configuration Write
Am79C971 controller aliases all accesses to the I/O re-
sources of the command types Memory Read Multiple
and Memory Read Line to the basic Memory Read The Am79C971 controller supports fast back-to-back
command. All accesses of the type Memory Write and transactions to different targets. This is indicated by the
Invalidate are aliased to the basic Memory Write com- Fast Back-To-Back Capable bit (PCI Status register, bit
mand. Eight-bit, 16-bit, and 32-bit non-burst transac- 7), which is hardwired to 1. The Am79C971 controller
tions are suppor ted. The Am79C971 controller is capable of detecting an I/O or a memory-mapped
decodes all 32 address lines to determine which I/O re- I/O cycle even when its address phase immediately fol-
source is accessed. lows the data phase of a transaction to a different tar-
get, without any idle state in-between. There will be no
The typical number of wait states added to a slave I/O
contention on the DEVSEL, TRDY, and STOP signals,
or memory mapped I/O read or write access on the part
since the Am79C971 controller asserts DEVSEL on
of the Am79C971 controller is six to seven clock cycles,
the second clock after FRAME is asserted (medium
depending upon the relative phases of the internal
timing) See Figure 3 and Figure 4.
Buffer Management Unit clock and the CLK signal,
Am79C971 31
CLK
1 2 3 4 5 6 7 8 9 10 11
FRAME
AD ADDR DATA
C/BE 0010 BE
PAR PAR PAR
IRDY
TRDY
DEVSEL
STOP
20550D-6
Figure 3. Slave Read Using I/O Command
CLK
1 2 3 4 5 6 7 8 9 10 11
FRAME
AD ADDR DATA
C/BE 0011 BE
PAR PAR PAR
IRDY
TRDY
DEVSEL
STOP
20550D-7
Figure 4. Slave Write Using Memory Command
32 Am79C971
Expansion ROM Transfers not be asserted until all four bytes are loaded into an in-
The host must initialize the Expansion ROM Base Ad- ternal scratch register. The cycle TRDY is asserted de-
dress register at offset 30H in the PCI configuration pends on the programming of the Expansion ROM
space with a valid address before enabling the access interface timing. The following figure (Figure 5) as-
to the device. The Am79C971 controller will not react to sumes that ROMTMG (BCR18, bits 15-12) is at its de-
any access to the Expansion ROM until both MEMEN fault value.
(PCI Command register, bit 1) and ROMEN (PCI Ex- Note: The Expansion ROM should be read only during
pansion ROM Base Address register, bit 0) are set to 1. PCI configuration time for the PCI system.
After the Expansion ROM is enabled, the Am79C971
When the host tries to write to the Expansion ROM, the
controller will assert DEVSEL on all memory read ac-
Am79C971 controller will claim the cycle by asserting
cesses with an address between ROMBASE and
DEVSEL. TRDY will be asserted one clock cycle later.
ROMBASE + 1M - 4. The Am79C971 controller aliases
The write operation will have no effect. Writes to the Ex-
all accesses to the Expansion ROM of the command
pansion ROM are done through the BCR30 Expansion
types Memory Read Multiple and Memory Read Line to
Bus Data Port. See the section on the Expansion Bus
the basic Memory Read command. Eight-bit, 16-bit,
Interface for more details.
and 32-bit read transfers are supported.
The Am79C971 controller supports fast back-to-back
Since setting MEMEN also enables memory mapped
transactions to different targets. This is indicated by the
access to the I/O resources, attention must be given
Fast Back-To-Back Capable bit (PCI Status register, bit
the PCI Memory Mapped I/O Base Address register
7), which is hardwired to 1. The Am79C971 controller
before enabling access to the Expansion ROM. The
is capable of detecting a memory cycle even when its
host must set the PCI Memory Mapped I/O Base Ad-
address phase immediately follows the data phase of a
dress register to a value that prevents the Am79C971
transaction to a different target without any idle state in-
controller from claiming any memory cycles not in-
between. There will be no contention on the DEVSEL,
tended for it.
TRDY, and STOP signals, since the Am79C971 con-
The Am79C971 controller will always read four bytes troller asserts DEVSEL on the second clock after
for every host Expansion ROM read access. TRDY will FRAME is asserted (medium timing). See Figure 5.
CLK
1 2 3 4 5 42 43 44 45
FRAME
AD ADDR DATA
C/BE CMD BE
PAR PAR PAR
IRDY
TRDY
DEVSEL
STOP
DEVSEL is sampled 20550D-8
Figure 5. Expansion ROM Read
Am79C971 33
During the boot procedure, the system will try to find an
Expansion ROM. A PCI system assumes that an Ex-
pansion ROM is present when it reads the ROM signa-
ture 55H (byte 0) and AAH (byte 1). A design without CLK
Expansion ROM can guarantee that the Expansion 1 2 3 4 5
ROM detection fails by connecting two adjacent EBD
pins together. FRAME
Slave Cycle Termination

AD ADDR DATA
There are three scenarios besides normal completion
of a transaction where the Am79C971controller is the
target of a slave cycle and it will terminate the access. C/BE CMD BE
Disconnect When Busy

PAR PAR PAR
The Am79C971controller cannot service any slave ac-
cess while it is reading the contents of the EEPROM.
Simultaneous access is not possible to avoid conflicts, IRDY
since the EEPROM is used to initialize some of the PCI
configuration space locations and most of the BCRs. TRDY
The EEPROM read operation will always happen auto-
matically after the deassertion of the RST pin. In addi-
tion, the host can start the read operation by setting the DEVSEL
PREAD bit (BCR19, bit 14). While the EEPROM read
is on-going, the Am79C971controller will disconnect STOP
any slave access where it is the target by asserting
STOP together with DEVSEL, while driving TRDY high.
STOP will stay asserted until the end of the cycle.
20550D-9
Note that I/O and memory slave accesses will only be
disconnected if they are enabled by setting the IOEN or Figure 6. Disconnect Of Slave Cycle When Busy
MEMEN bit in the PCI Command register. Without the
enable bit set, the cycles will not be claimed at all.
Since H_RESET clears the IOEN and MEMEN bits for
the automatic EEPROM read after H_RESET, the dis- CLK
1 2 3 4 5
connect only applies to configuration cycles.
FRAME
A second situation where the Am79C971controller will
generate a PCI disconnect/retry cycle is when the host
tries to access any of the I/O resources right after hav- AD ADDR DATA
ing read the Reset register. Since the access gener-
ates an internal reset pulse of about 1 µs in length, all
C/BE CMD BE
further slave accesses will be deferred until the internal
reset operation is completed. See Figure 6.
PAR PAR PAR
Disconnect Of Burst Transfer
The Am79C971controller does not support burst ac-
IRDY
cess to the configuration space, the I/O resources, or to
the Expansion Bus. The host indicates a burst transac-
tion by keeping FRAME asserted during the data TRDY
phase. When the Am79C971controller sees FRAME
and IRDY asserted in the clock cycle before it wants to
DEVSEL
assert TRDY, it also asserts STOP at the same time.
The transfer of the first data phase is still successful,
STOP
since IRDY and TRDY are both asserted. See Figure 7.
20550D-10
Figure 7. Disconnect Of Slave Burst Transfer - No
Host Wait States
34 Am79C971
If the host is not yet ready when the Am79C971 control- an address parity error when PERREN and SERREN
ler asserts TRDY, the device will wait for the host to as- are set to 1. See Figure 9.
sert IRDY. When the host asserts IRDY and FRAME is
still asserted, the Am79C971controller will finish the
first data phase by deasserting TRDY one clock later.
At the same time, it will assert STOP to signal a discon-
nect to the host. STOP will stay asserted until the host
CLK
removes FRAME. See Figure 8. 1 2 3 4 5
FRAME
AD ADDR 1st DATA

CLK
1 2 3 4 5 6
C/BE CMD BE
FRAME
PAR PAR PAR

AD 1st DATA DATA
C/BE BE BE SERR
PAR PAR PAR DEVSEL
IRDY
20550D-12
TRDY Figure 9. Address Parity Error Response
DEVSEL
During the data phase of an I/O write, memory-mapped
I/O write, or configuration write command that selects
STOP
the Am79C971controller as target, the device samples
the AD[31:0] and C/BE[3:0] lines for parity on the clock
edge, and data is transferred as indicated by the asser-
20550D-11 tion of IRDY and TRDY. PAR is sampled in the following
Figure 8. Disconnect Of Slave Burst Transfer - clock cycle. If a parity error is detected and reporting of
Host Inserts Wait States that error is enabled by setting PERREN (PCI Com-
mand register, bit 6) to 1, PERR is asserted one clock
later. The parity error will always set PERR (PCI Status
Parity Error Response register, bit 15) set to 1 even when PERREN is cleared
When the Am79C971controller is not the current bus to 0. The Am79C971controller will finish a transaction
master, it samples the AD[31:0], C/BE[3:0], and the that has a data parity error in the normal way by assert-
PAR lines during the address phase of any PCI coming TRDY. The corrupted data will be written to the ad-
mand for a parity error. When it detects an address par- dressed location.
ity error, the controller sets PERR (PCI Status register, Figure 10 shows a transaction that suffered a parity
bit 15) to 1. When reporting of that error is enabled by error at the time data was transferred (clock 7, IRDY
setting SERREN (PCI Command register, bit 8) and and TRDY are both asserted). PERR is driven high at
PERREN (PCI Command register, bit 6) to 1, the the beginning of the data phase and then drops low due
Am79C971controller also drives the SERR signal low to the parity error on clock 9, two clock cycles after the
for one clock cycle and sets SERR (PCI Status register, data was transferred. After PERR s driven low, the
bit 14) to 1. The assertion of SERR follows the address Am79C971controller drives PERR high for one clock
phase by two clock cycles. The Am79C971controller cycle, since PERR is a sustained tri-state signal.
will not assert DEVSEL for a PCI transaction that has
Am79C971 35
CLK
1 2 3 4 5 6 7 8 9 10
FRAME
AD ADDR DATA
C/BE CMD BE
PAR PAR PAR
PERR
IRDY
TRDY
DEVSEL
20550D-13
Figure 10. Slave Cycle Data Parity Error Response
Master Bus Interface Unit Table 3. Master Commands (Continued)

The master Bus Interface Unit (BIU) controls the acqui- C[3:0] Command Use
sition of the PCI bus and all accesses to the initializa- Write to the descriptor
tion block, descriptor rings, and the receive and 0111 Memory Write rings and to the receive
transmit buffer memory. Table 3 shows the usage of buffer
PCI commands by the Am79C971controller in master 1000 Reserved
mode.
1001 Reserved
1010 Configuration Read Not used
Table 3. Master Commands 1011 Configuration Write Not used
C[3:0] Command Use Memory Read Read of the transmit
1100
Multiple buffer in burst mode
Interrupt Not used
0000 1101 Dual Address Cycle Not used
Acknowledge
Read of the transmit
0001 Special Cycle Not used 1110 Memory Read Line
buffer in burst mode
0010 I/O Read Not used
Memory Write
0011 I/O Write Not used 1111 Not used
Invalidate
0100 Reserved Bus Acquisition
0101 Reserved
The Am79C971microcode will determine when a DMA
Read of the initialization transfer should be initiated. The first step in any
block and descriptor Am79C971bus master transfer is to acquire ownership
rings of the bus. This task is handled by synchronous logic
0110 Memory Read Read of the transmit
within the BIU. Bus ownership is requested with the
buffer in non-burst mode
REQ signal and ownership is granted by the arbiter
through the GNT signal.
36 Am79C971
Figure 11 shows the Am79C971controller bus acquisi- controller non-burst read accesses are of the PCI
tion. REQ is asserted and the arbiter returns GNT while command type Memory Read (type 6). Note that during
an othe r bu s m as te r i s tran sfer r i ng dat a. Th e a non-burst read operation, all byte lanes will always be
Am79C971 controller waits until the bus is idle (FRAME active. The Am79C971 controller will internally discard
and IRDY deasserted) before it starts driving AD[31:0] unneeded bytes.
and C/BE[3:0] on clock 5. FRAME is asserted at clock
The Am79C971 controller typically performs more than
5 indicating a valid address and command on AD[31:0]
one non-burst read transactions within a single bus
and C/BE[3:0]. The Am79C971 controller does not use
mastership period. FRAME is dropped between con-
address stepping which is reflected by ADSTEP (bit 7)
secutive non-burst read cycles. REQ however stays as-
in the PCI Command register being hardwired to 0.
serted until FRAME is asserted for the last transaction.
The Am79C971 controller supports zero wait state
read cycles. It asserts IRDY immediately after the ad-
dress phase and at the same time starts sampling
DEVSEL. Figure 12 shows two non-burst read transac-
CLK
1 2 3 4 5
tions. The first transaction has zero wait states. In the
second transaction, the target extends the cycle by as-
FRAME serting TRDY one clock later.
Basic Burst Read Transfer
AD ADDR The Am79C971 controller supports burst mode for all
bus master read operations. The burst mode must be
C/BE CMD enabled by setting BREADE (BCR18, bit 6). To allow
burst transfers in descriptor read operations, the
Am79C971 controller must also be programmed to use
IRDY
SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses
to the initialization block and descriptor ring are of the
REQ
PCI command type Memory Read (type 6). Burst read
accesses to the transmit buffer typically are longer than
GNT two data phases. When MEMCMD (BCR18, bit 9) is
cleared to 0, all burst read accesses to the transmit
buffer are of the PCI command type Memory Read Line
20550D-14 (type 14). When MEMCMD (BCR18, bit 9) is set to1, all
Figure 11. Bus Acquisition burst read accesses to the transmit buffer are of the
PCI command type Memory Read Multiple (type 12).
AD[1:0] will both be 0 during the address phase indicat-
In burst mode, the deassertion of REQ depends on the ing a linear burst order. Note that during a burst read
setting of EXTREQ (BCR18, bit 8). If EXTREQ is operation, all byte lanes will always be active. The
cleared to 0, REQ is deasserted at the same time as Am79C971 controller will internally discard unneeded
FRAME is asserted. (The Am79C971 controller never bytes.
performs more than one burst transaction within a sin-
The Am79C971 controller will always perform only a
gle bus mastership period.) If EXTREQ is set to 1, the
single burst read transaction per bus mastership pe-
Am79C971 controller does not deassert REQ until it
riod, where transaction is defined as one address
starts the last data phase of the transaction.
ph as e an d o ne or mul ti pl e da ta p ha s es. Th e
Once asserted, REQ remains active until GNT has be- Am79C971 controller supports zero wait state read cy-
come active and independent of subsequent setting of cles. It asserts IRDY immediately after the address
STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser- phase and at the same time starts sampling DEVSEL.
tion of H_RESET or S_RESET, however, will cause FRAME is deasserted when the next to last data phase
REQ to go inactive immediately. is completed. Figure 13 shows a typical burst read ac-
cess. The Am79C971 controller arbitrates for the bus,
Bus Master DMA Transfers
is granted access, reads three 32-bit words (DWord)
There are four primary types of DMA transfers. The from the system memory, and then releases the bus. In
Am79C971 controller uses non-burst as well as burst the example, the memory system extends the data
cycles for read and write access to the main memory. phase of the each access by one wait state. The exam-
Basic Non-Burst Read Transfer ple assumes that EXTREQ (BCR18, bit 8) is cleared to
0, therefore, REQ is deasserted in the same cycle as
By default, the Am79C971 controller uses non-burst FRAME is asserted.
cycles in all bus master read operations. All Am79C971
Am79C971 37
CLK
1 2 3 4 5 6 7 8 9 10 11
FRAME
AD ADDR DATA ADDR DATA
C/BE 0110 0000 0110 0000
PAR PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT3
DEVSEL is sampled
20550D-15
Figure 12. Non-Burst Read Transfer
CLK
1 2 3 4 5 6 7 8 9 10 11
FRAME
AD ADDR DATA DATA DATA
C/BE 1110 0000
PAR PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-16
Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)
38 Am79C971
Basic Non-Burst Write Transfer Basic Burst Write Transfer
By default, the Am79C971 controller uses non-burst The Am79C971 controller supports burst mode for all
cy cles i n a ll bus ma ster wr ite operations. All bus master write operations. The burst mode must be
Am79C971 controller non-burst write accesses are of enabled by setting BWRITE (BCR18, bit 5). To allow
the PCI command type Memory Write (type 7). The burst transfers in descriptor write operations, the
byte enable signals indicate the byte lanes that have Am79C971 controller must also be programmed to use
valid data.The Am79C971 controller typically performs SWSTYLE 3 (BCR20, bits 7-0). All Am79C971 control-
more than one non-burst write transaction within a sin- ler burst write transfers are of the PCI command type
gle bus mastership period. FRAME is dropped be- Memory Write (type 7). AD[1:0] will both be 0 during the
tween consecutive non-burst write cycles. REQ, address phase indicating a linear burst order. The byte
however, stays asserted until FRAME is asserted for enable signals indicate the byte lanes that have valid
the last transaction. The Am79C971 supports zero wait data.
state write cycles except with descriptor write transfers.
The Am79C971 controller will always perform a single
(See the section Descriptor DMA Transfers for the only
burst write transaction per bus mastership period,
exception.) It asserts IRDY immediately after the ad-
where transaction is defined as one address phase and
dress phase.
one or multiple data phases. The Am79C971 controller
Figure 14 shows two non-burst write transactions. The supports zero wait state write cycles except with the
first transaction has two wait states. The target inserts case of descriptor write transfers. (See the section De-
one wait state by asserting DEVSEL one clock late and scriptor DMA Transfers for the only exception.) The de-
another wait state by also asserting TRDY one clock vice asserts IRDY immediately after the address phase
late. The second transaction shows a zero wait state and at the same time star ts sampling DEVSEL.
write cycle. The target asserts DEVSEL and TRDY in FRAME is deasserted when the next to last data phase
the same cycle as the Am79C971 controller asserts is completed.
IRDY.
CLK
1 2 3 4 5 6 7 8 9 10
FRAME
AD ADDR DATA ADDR DATA
C/BE 0111 BE 0111 BE
PAR PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-17
Figure 14. Non-Burst Write Transfer
Am79C971 39
Figure 15 shows a typical burst write access. The Disconnect With Data Transfer
Am79C971 controller arbitrates for the bus, is granted Figure 16 shows a disconnection in which one last data
access, and writes four 32-bit words (DWords) to the transfer occurs after the target asserted STOP. STOP
system memory and then releases the bus. In this ex- is asserted on clock 4 to start the termination se-
ample, the memory system extends the data phase of quence. Data is still transferred during this cycle, since
the first access by one wait state. The following three both IRDY and TRDY are asserted. The Am79C971
data phases take one clock cycle each, which is deter- controller terminates the current transfer with the deas-
mined by the timing of TRDY. The example assumes sertion of FRAME on clock 5 and of IRDY one clock
that EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ later. It finally releases the bus on clock 7. The
is not deasserted until the next to last data phase is fin- Am79C971 controller will again request the bus after
ished. two clock cycles, if it wants to transfer more data. The
Target Initiated Termination starting address of the new transfer will be the address
of the next non-transferred data.
When the Am79C971 controller is a bus master, the cy-
cles it produces on the PCI bus may be terminated by
the target in one of three different ways.
CLK
1 2 3 4 5 6 7 8 9
FRAME
AD ADDR DATA DATA DATA DATA
C/BE 0111 BE
PAR PAR PAR PAR PAR PAR
IRDY
TRDY
EVSEL
REQ
GNT
DEVSEL is sampled
20550D-18
Figure 15. Burst Write Transfer (EXTREQ = 1)
40 Am79C971
CLK
1 2 3 4 5 6 7 8 9 10 11
FRAME
AD ADDRi DATA DATA ADDRi+8
C/BE 0111 0000 0111
PAR PAR PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
DEVSEL is sampled
20550D-19
Figure 16. Disconnect With Data Transfer
Disconnect Without Data Transfer about the success of the previous data transfers in the
Figure 17 shows a target disconnect sequence during current transaction. The Am79C971 controller termi-
which no data is transferred. STOP is asserted on clock nates the current transfer with the deassertion of
4 without TRDY being asserted at the same time. The FRAME on clock 5 and of IRDY one clock cycle later.
Am79C971 controller terminates the access with the It finally releases the bus on clock 6.
deassertion of FRAME on clock 5 and of IRDY one Since data integrity is not guaranteed, the Am79C971
clock cycle later. It finally releases the bus on clock 7. controller cannot recover from a target abort event. The
The Am79C971 controller will again request the bus Am79C971 controller will reset all CSR locations to
after two clock cycles to retry the last transfer. The their STOP_RESET values. The BCR and PCI config-
starting address of the new transfer will be the address uration registers will not be cleared. Any on-going net-
of the last non-transferred data. wor k transmission is ter minated in an order ly
Target Abort sequence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
Figure 18 shows a target abort sequence. The target immediately, generating a runt packet. If 512 bits or
asserts DEVSEL for one clock. It then deasserts more have been transmitted, the message will have the
DEVSEL and asserts STOP on clock 4. A target can current FCS inverted and appended at the next byte
use the target abort sequence to indicate that it can- boundary to guarantee an FCS error is detected at the
not service the data transfer and that it does not want receiving station.
the transaction to be retr ied. Additionally, the
Am79C971 controller cannot make any assumption
Am79C971 41
CLK
1 2 3 4 5 6 7 8 9 10 11
FRAME
AD ADDRi DATA ADDRi
C/BE 0111 0000 0111
PAR PAR PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
DEVSEL is sampled
20550D-20
Figure 17. Disconnect Without Data Transfer
RTABORT (PCI Status register, bit 12) will be set to last transaction, REQ will remain asserted to regain
indicate that the Am79C971 controller has received a bus ownership as soon as possible. See Figure 19.
target abort. In addition, SINT (CSR5, bit 11) will be set
Preemption During Burst Transaction
to 1. When SINT is set, INTA is asserted if the enable
bit SINTE (CSR5, bit 10) is set to 1. This mechanism When the Am79C971 controller operates in burst
can be used to inform the driver of the system error. The mode, it only performs a single transaction per bus
host can read the PCI Status register to determine the mastership period, where transaction is defined as one
exact cause of the interrupt. address phase and one or multiple data phases. The
central arbiter can remove GNT at any time during the
Master Initiated Termination transaction. The Am79C971 controller will ignore the
There are three scenarios besides normal completion deassertion of GNT and continue with data transfers,
of a transaction where the Am79C971 controller will as long as the PCI Latency Timer is not expired. When
terminate the cycles it produces on the PCI bus. the Latency Timer is 0 and GNT is deasserted, the
Am79C971 controller will finish the current data phase,
Preemption During Non-Burst Transaction
deassert FRAME, finish the last data phase, and re-
When the Am79C971 controller performs multiple non- lease the bus. If EXTREQ (BCR18, bit 8) is cleared to
burst transactions, it keeps REQ asserted until the as- 0, it will immediately assert REQ to regain bus owner-
sertion of FRAME for the last transaction. When GNT ship as soon as possible. If EXTREQ is set to 1, REQ
is removed, the Am79C971 controller will finish the cur- will stay asserted.
rent transaction and then release the bus. If it is not the
42 Am79C971
The Am79C971 controller will reset all CSR locations
to their STOP_RESET values. The BCR and PCI con-
figuration registers will not be cleared. Any on-going
CLK
network transmission is terminated in an orderly se-
1 2 3 4 5 6 7 quence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
FRAME
immediately, generating a runt packet. If 512 bits or
more have been transmitted, the message will have the
AD ADDR DATA
current FCS inverted and appended at the next byte
boundary to guarantee an FCS error is detected at the
C/BE 0111 0000
receiving station.
PAR PAR PAR

RMABORT (in the PCI Status register, bit 13) will be set
to indicate that the Am79C971 controller has termi-
nated its transaction with a master abort. In addition,
IRDY
SINT (CSR5, bit 11) will be set to 1. When SINT is set,
INTA is asserted if the enable bit SINTE (CSR5, bit 10)
TRDY
is set to 1. This mechanism can be used to inform the
driver of the system error. The host can read the PCI
DEVSEL
Status register to determine the exact cause of the in-
terrupt. See Figure 21.
STOP
Parity Error Response
REQ
During every data phase of a DMA read operation,
when the target indicates that the data is valid by as-
GNT
serting TRDY, the Am79C971 controller samples the
AD[31:0], C/BE[3:0] and the PAR lines for a data parity
error. When it detects a data parity error, the controller
DEVSEL is sampled
sets PERR (PCI Status register, bit 15) to 1. When re-
20550D-21
porting of that error is enabled by setting PERREN
(PCI Command register, bit 6) to 1, the Am79C971
Figure 18. Target Abort controller also drives the PERR signal low and sets
DATAPERR (PCI Status register, bit 8) to 1. The asser-
tion of PERR follows the corrupted data/byte enables
When the preemption occurs after the counter has by two clock cycles and PAR by one clock cycle.
counted down to 0, the Am79C971 controller will finish
the current data phase, deassert FRAME, finish the Figure 22 shows a transaction that has a parity error in
last data phase, and release the bus. Note that it is im- the data phase. The Am79C971 controller asserts
portant for the host to program the PCI Latency Timer PERR on clock 8, two clock cycles after data is valid.
according to the bus bandwidth requirement of the The data on clock 5 is not checked for parity, since on
Am79C971 controller. The host can determine this bus a read access PAR is only required to be valid one
bandwidth requirement by reading the PCI MAX_LAT clock after the target has asser ted TRDY. The
and MIN_GNT registers. Am79C971 controller then drives PERR high for one
clock cycle, since PERR is a sustained tri-state signal.
Figure 20 assumes that the PCI Latency Timer has
counted down to 0 on clock 7. During every data phase of a DMA write operation, the
Am79C971 controller checks the PERR input to see if
Master Abort the target reports a parity error. When it sees the PERR
The Am79C971 controller will terminate its cycle with a input asserted, the controller sets PERR (PCI Status
Master Abort sequence if DEVSEL is not asserted register, bit 15) to 1. When PERREN (PCI Command
within 4 clocks after FRAME is asserted. Master Abort register, bit 6) is set to 1, the Am79C971 controller also
is treated as a fatal error by the Am79C971 controller. sets DATAPERR (PCI Status register, bit 8) to 1.
Am79C971 43
CLK
1 2 3 4 5 6 7
FRAME
AD ADDR DATA
C/BE 0111 BE
PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-22
Figure 19. Preemption During Non-Burst Transaction
CLK
1 2 3 4 5 6 7 8 9
FRAME
AD ADDR DATA DATA DATA DATA DATA
C/BE 0111 BE
PAR PAR PAR PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-23
Figure 20. Preemption During Burst Transaction
44 Am79C971
CLK
1 2 3 4 5 6 7 8 9
FRAME
AD ADDR DATA
C/BE 0111 0000
PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-24
Figure 21. Master Abort
CLK
1 2 3 4 5 6 7 8 9
FRAME
AD ADDR DATA
C/BE 0111 BE
PAR PAR PAR
PERR
IRDY
TRDY
DEVSEL
DEVSEL is sampled
20550D-25
Figure 22. Master Cycle Data Parity Error Response
Am79C971 45
Whenever the Am79C971 controller is the current bus Am79C971 controller to use 32-bit software structures.
master and a data parity error occurs, SINT (CSR5, bit The Am79C971 controller will react in the following way
11) will be set to 1. When SINT is set, INTA is asserted when a data parity error occurs:
if the enable bit SINTE (CSR5, bit 10) is set to 1. This
■ Initialization block read: STOP (CSR0, bit 2) is set to
mechanism can be used to inform the driver of the sys-
1 and causes a STOP_RESET of the device.
tem error. The host can read the PCI Status register to
determine the exact cause of the interrupt. The setting ■ Descriptor ring read: Any on-going network activity
of SINT due to a data parity error is not dependent on is terminated in an orderly sequence and then STOP
the setting of PERREN (PCI Command register, bit 6). (CSR0, bit 2) is set to 1 to cause a STOP_RESET
of the device.
By default, a data parity error does not affect the state
of the MAC engine. The Am79C971 controller treats the ■ Descriptor ring write: Any on-going network activity
data in all bus master transfers that have a parity error is terminated in an orderly sequence and then STOP
as if nothing has happened. All network activity contin- (CSR0, bit 2) is set to 1 to cause a STOP_RESET
ues. of the device.
■ Transmit buffer read: BPE (TMD1, bit 23) is set in
Advanced Parity Error Handling
the current transmit descriptor. Any on-going net-
For all DMA cycles, the Am79C971 controller provides work transmission is terminated in an orderly se-
a second, more advanced level of parity error handling. quence.
This mode is enabled by setting APERREN (BCR20, bit
■ Receive buffer write: BPE (RMD1, bit 23) is set in
10) to 1. When APERREN is set to 1, the BPE bits
the last receive descriptor associated with the frame.
(RMD1 and TMD1, bit 23) are used to indicate parity
error in data transfers to the receive and transmit buff- Terminating on-going network transmission in an order-
ers. Note that since the advanced parity error handling ly sequence means that if less than 512 bits have been
uses an additional bit in the descriptor, SWSTYLE transmitted onto the network, the transmission will be
(BCR20, bits 7-0) must be set to 2 or 3 to program the terminated immediately, generating a runt packet.
CLK
1 2 3 4 5 6 7 8 9 10
FRAME
AD IADDi DATA IADDi+4 DATA
C/BE 0110 0000 0110 0000
PAR PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-26
Figure 23. Initialization Block Read In Non-Burst Mode
46 Am79C971
If 512 bits or more have been transmitted, the message some of the bytes not be needed, then the Am79C971
will have the current FCS inverted and appended at the controller will internally discard the extraneous informa-
next byte boundary to guarantee an FCS error is de- tion that was gathered during such a read.
tected at the receiving station.
The settings of SWSTYLE (BCR20, bits 7-0) and
APERREN does not affect the reporting of address BREADE (BCR18, bit 6) affect the way the Am79C971
parity errors or data parity errors that occur when the controller performs descriptor read operations.
Am79C971 controller is the target of the transfer.
When SWSTYLE is set to 0 or 2, all descriptor read op-
Initialization Block DMA Transfers erations are performed in non-burst mode. The setting
During execution of the Am79C971 controller bus mas- of BREADE has no effect in this configuration. See Fig-
ter initialization procedure, the Am79C971 microcode ure 25.
will repeatedly request DMA transfers from the BIU. When SWSTYLE is set to 3, the descriptor entries are
During each of these initialization block DMA transfers, ordered to allow burst transfers. The Am79C971 con-
the BIU will perform two data transfer cycles reading troller will perform all descriptor read operations in
one DWord per transfer and then it will relinquish the burst mode, if BREADE is set to 1. See Figure 26.
bus. When SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the
initialization block is organized as 32-bit software struc- Table 4 shows the descriptor read sequence.
tures), there are seven DWords to transfer during the During descriptor write accesses, only the byte lanes
bus master initialization procedure, so four bus master- which need to be written are enabled.
ship periods are needed in order to complete the initial-
ization sequence. Note that the last DWord transfer of
the last bus mastership period of the initialization se- Table 4. Descriptor Read Sequence
quence accesses an unneeded location. Data from this
transfer is discarded internally. When SSIZE32 is SWSTYLE BREADE
BCR20[7:0] BCR18[6] AD Bus Sequence
cleared to 0 (i.e., the initialization block is organized as
16-bit software structures), then three bus mastership Address = XXXX XX00h
periods are needed to complete the initialization se- Turn around cycle
quence. Data = MD1[31:24],
MD0[23:0]
The Am79C971 supports two transfer modes for read- 0 X
ing the initialization block: non-burst and burst mode, Idle
with burst mode being the preferred mode when the Address = XXXX XX04h
Am79C971 controller is used in a PCI bus application. Turn around cycle
See Figure 23 and Figure 24. Data = MD2[15:0], MD1[15:0]
When BREADE is cleared to 0 (BCR18, bit 6), all initial- Address = XXXX XX04h
ization block read transfers will be executed in non- Turn around cycle
burst mode. There is a new address phase for every Data = MD1[31:0]
data phase. FRAME will be dropped between the two 2 X Idle
transfers. The two phases within a bus mastership pe-
Address = XXXX XX00h
riod will have addresses of ascending contiguous or-
der. Turn around cycle
Data = MD0[31:0]
When BREADE is set to 1 (BCR18, bit 6), all initializa-
tion block read transfers will be executed in burst mode.
AD[1:0] will be 0 during the address phase indicating a Turn around cycle
linear burst order. Data = MD1[31:0]
3 0 Idle
Descriptor DMA Transfers
Am79C971 microcode will determine when a descrip-
Turn around cycle
tor access is required. A descriptor DMA read will con-
sist of two data transfers. A descriptor DMA write will Data = MD0[31:0]
consist of one or two data transfers. The descriptor Address = XXXX XX04h
DMA transfers within a single bus mastership period Turn around cycle
3 1
will always be of the same type (either all read or all Data = MD1[31:0]
write). Data = MD0[31:0]
During descriptor read accesses, the byte enable sig-
nals will indicate that all byte lanes are active. Should
Am79C971 47
CLK
1 2 3 4 5 6 7
FRAME
AD IADDi DATA DATA
C/BE 0110 0000
PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-27
Figure 24. Initialization Block Read In Burst Mode
CLK
1 2 3 4 5 6 7 8 9 10
FRAME
AD MD1 DATA MD0 DATA
C/BE 0110 0000 0110 0000
PAR PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled 20550C-28
Figure 25. Descriptor Ring Read In Non-Burst Mode
48 Am79C971
If buffer chaining is used, accesses to the descriptors When SWSTYLE is set to 0 or 2, all descriptor write op-
of all intermediate buffers consist of only one data erations are performed in non-burst mode. The setting
transfer to return ownership of the buffer to the system. of BWRITE has no effect in this configuration.
When SWSTYLE (BCR20, bits 7-0) is cleared to 0 (i.e.,
When SWSTYLE is set to 3, the descriptor entries are
the descriptor entries are organized as 16-bit software
ordered to allow burst transfers. The Am79C971 con-
structures), the descriptor access will write a single
troller will perform all descriptor write operations in
byte. When SWSTYLE (BCR20, bits 7-0) is set to 2 or
burst mode, if BWRITE is set to 1. See Table 5 for the
3 (i.e., the descriptor entries are organized as 32-bit
descriptor write sequence.
software structures), the descriptor access will write a
single word. On all single buffer transmit or receive de- A write transaction to the descriptor ring entries is the
scriptors, as well as on the last buffer in chain, writes to only case where the Am79C971 controller inserts a
the descriptor consist of two data transfers. wait state when being the bus master. Every data
phase in non-burst and burst mode is extended by one
The first data transfer writes a DWord containing status
clock cycle, during which IRDY is deasserted.
information. The second data transfer writes a byte
(SWSTYLE cleared to 0), or otherwise a word contain- Note that Figure 26 assumes that the Am79C971 con-
ing additional status and the ownership bit (i.e., troller is programmed to use 32-bit software structures
MD1[31]). (SWSTYLE = 2 or 3). The byte enable signals for the
second data transfer would be 0111b, if the device was
The settings of SWSTYLE (BCR20, bits 7-0) and
programmed to use 16-bit software structures (SW-
BWRITE (BCR18, bit 5) affect the way the Am79C971
STYLE = 0).
controller performs descriptor write operations.
CLK
1 2 3 4 5 6 7
FRAME
AD MD1 DATA DATA
C/BE 0110 0000
PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-29
Figure 26. Descriptor Ring Read In Burst Mode
Am79C971 49
Table 5. Descriptor Write Sequence Non-Burst FIFO DMA Transfers
SWSTYLE BWRITE In the default mode, the Am79C971 controller uses
BCR20[7:0] BCR18[5] AD Bus Sequence non-burst transfers to read and write data when ac-
Address = XXXX XX04h cessing the FIFOs. Each non-burst transfer will be per-
formed sequentially with the issue of an address and
Data = MD2[15:0],
MD1[15:0] the transfer of the corresponding data with appropriate
0 X output signals to indicate selection of the active data
Idle
bytes during the transfer.
Data = MD1[31:24] FRAME will be deasserted after every address phase.
Several factors will affect the length of the bus master-
ship period. The possibilities are as follows:
Data = MD2[31:0]
2 X Idle Bus cycles will continue until the transmit FIFO is filled
to its high threshold (read transfers) or the receive FIFO
is emptied to its low threshold (write transfers). The
Data = MD1[31:16] exact number of total transfer cycles in the bus master-
Address = XXXX XX00h ship period is dependent on all of the following vari-
Data = MD2[31:0] ables: the settings of the FIFO watermarks, the
3 0 Idle conditions of the FIFOs, the latency of the system bus
Address = XXXX XX04h to the Am79C971 controller’s bus request, the speed of
bus operation and bus preemption events. The TRDY
Data = MD1[31:16]
response time of the memory device will also affect the
Address = XXXX XX00h number of transfers, since the speed of the accesses
3 1 Data = MD2[31:0] will affect the state of the FIFO. During accesses, the
Data = MD1[31:16] FIFO may be filling or emptying on the network end. For
example, on a receive operation, a slower TRDY re-
FIFO DMA Transfers sponse will allow additional data to accumulate inside
Am79C971 microcode will determine when a FIFO of the FIFO. If the accesses are slow enough, a com-
DMA transfer is required. This transfer mode will be plete DWord may become available before the end of
used for transfers of data to and from the Am79C971 the bus mastership period and, thereby, increase the
FIFOs. Once the Am79C971 BIU has been granted bus number of transfers in that period. The general rule is
mastership, it will perform a series of consecutive that the longer the Bus Grant latency, the slower the
transfer cycles before relinquishing the bus. All trans- bus transfer operations; the slower the clock speed, the
fers within the master cycle will be either read or write higher the transmit watermark; or the higher the re-
cycles, and all transfers will be to contiguous, ascend- ceive watermark, the longer the bus mastership period
ing addresses. Both non-burst and burst cycles are will be.
used, with burst mode being the preferred mode when
Note: The PCI Latency Timer is not significant during
the device is used in a PCI bus application.
non-burst transfers.
50 Am79C971
CLK
1 2 3 4 5 6 7 8 9 10
FRAME
AD MD2 DATA MD1 DATA
C/BE 0111 0000 0111 0011
PAR PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-30
Figure 27. Descriptor Ring Write In Non-Burst Mode
CLK
1 2 3 4 5 6 7 8
FRAME
AD MD2 DATA DATA
C/BE 0110 0000 0011
PAR PAR PAR PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
20550D-31
Figure 28. Descriptor Ring Write In Burst Mode
Am79C971 51
Burst FIFO DMA Transfers
Bursting is only performed by the Am79C971 controller
if the BREADE and/or BWRITE bits of BCR18 are set.
These bits individually enable/disable the ability of the
Am79C971 controller to perform burst accesses during
master read operations and master write operations, CLK
1 2 3 4 5 6
respectively.
FRAME
A burst transaction will start with an address phase, fol-
lowed by one or more data phases. AD[1:0] will always
be 0 during the address phase indicating a linear burst AD ADD DATA DATA DATA
order.
During FIFO DMA read operations, all byte lanes will C/BE 0111 0001 0000
always be active. The Am79C971 controller will inter-
nally discard unused bytes. During the first and the last PAR PAR PAR PAR
data phases of a FIFO DMA burst write operation, one
or more of the byte enable signals may be inactive. All
IRDY
other data phases will always write a complete DWord.
Figure 29 shows the beginning of a FIFO DMA write
TRDY
with the beginning of the buffer not aligned to a DWord
boundary. The Am79C971 controller starts off by writ-
ing only three bytes during the first data phase. This op- DEVSEL
eration aligns the address for all other data transfers to
a 32-bit boundary so that the Am79C971 controller can REQ
continue bursting full DWords.
If a receive buffer does not end on a DWord boundary, GNT
the Am79C971 controller will perform a non-DWord
write on the last transfer to the buffer. Figure 30 shows
DEVSEL is sampled
the final three FIFO DMA transfers to a receive buffer.
Since there were only nine bytes of space left in the re- 20550D-32
ceive buffer, the Am79C971 controller bursts three data
phases. The first two data phases write a full DWord, Figure 29. FIFO Burst Write At Start Of Unaligned
the last one only writes a single byte. Buffer
Note that the Am79C971 controller will always perform

a DWord transfer as long as it owns the buffer space, In a PCI bus application, the Am79C971 controller
even when there are less then four bytes to write. For should be set up to have the length of a bus mastership
example, if there is only one byte left for the current re- period be controlled only by the PCI Latency Timer.
ceive frame, the Am79C971 controller will write a full The Timer bit (CSR4, bit 13) should remain at its de-
DWord, containing the last byte of the receive frame in fault value of 0. In this mode, the Am79C971 controller
the least significant byte position (BSWP is cleared to will continue transferring FIFO data until the transmit
0, CSR3, bit 2). The content of the other three bytes is FIFO is filled to its high threshold (read transfers) or the
undefined. The message byte count in the receive de- receive FIFO is emptied to its low threshold (write
scriptor always reflects the exact length of the received transfers), or the Am79C971 controller is preempted,
frame. and the PCI Latency Timer is expired. The host should
If the end of a receive buffer is not aligned to a DWord use the values in the PCI MIN_GNT and MAX_LAT reg-
boundary, IWAIT (BCR18, bit 10) must stay at its de- isters to determine the value for the PCI Latency Timer.
fault value of 0. This will result in one wait state added In applications that do not use the PCI Latency Timer
to every data phase in a burst write transaction. When or that do not support preemption, the following rules
the software ensures that all receive buffers end on a apply to limit the time the Am79C971 controller takes
DWord boundary, IWAIT can be set to 1. In this mode, on the bus:
the Am79C971 controller will only insert a wait state in
the first data phase of the burst write transaction.
52 Am79C971
Buffer Management Unit
The Buffer Management Unit (BMU) is a microcoded
state machine which implements the initialization pro-
CLK cedure and manages the descriptors and buffers. The
1 2 3 4 5 6 7
buffer management unit operates at half the speed of
FRAME the CLK input.
Initialization
AD ADD DATA DATA DATA
Am79C971 initialization includes the reading of the ini-
C/BE 0111 0000 1110 tialization block in memory to obtain the operating pa-
rameters. The initialization block can be organized in
PAR PAR PAR PAR PAR
two ways. When SSIZE32 (BCR20, bit 8) is at its de-
fault value of 0, all initialization block entries are logi-
cally 16-bits wide to be backwards compatible with the
IRDY
Am79C90 C-LANCE and Am79C96x PCnet-ISA family.
When SSIZE32 (BCR20, bit 8) is set to 1, all initializa-
TRDY
tion block entries are logically 32-bits wide. Note that
the Am79C971 controller always performs 32-bit bus
DEVSEL
transfers to read the initialization block entries. The ini-
tialization block is read when the INIT bit in CSR0 is set.
REQ
The INIT bit should be set before or concurrent with the
STRT bit to insure correct operation. Once the initial-
GNT ization block has been completely read in and internal
registers have been updated, IDON will be set in
DEVSEL is sampled CSR0, generating an interrupt (if IENA is set).
20550D-33
The Am79C971 controller obtains the start address of
the initialization block from the contents of CSR1 (least
Figure 30. FIFO Burst Write At End Of Unaligned significant 16 bits of address) and CSR2 (most signifi-
Buffer cant 16 bits of address). The host must write CSR1 and
CSR2 before setting the INIT bit. The initialization block
contains the user defined conditions for Am79C971 op-
The exact number of total transfer cycles in the bus eration, together with the base addresses and length
mastership period is dependent on all of the following information of the transmit and receive descriptor rings.
variables: the settings of the FIFO watermarks, the
conditions of the FIFOs, the latency of the system bus There is an alter nate method to initial ize the
to the Am79C971 controller’s bus request, and the Am79C971 controller. Instead of initialization via the
speed of bus operation. The TRDY response time of initialization block in memory, data can be written di-
the memory device will also affect the number of trans- rectly into the appropriate registers. Either method or a
fers, since the speed of the accesses will affect the combination of the two may be used at the discretion of
state of the FIFO. During accesses, the FIFO may be the programmer. Please refer to Appendix C, Alterna-
filling or emptying on the network end. For example, on tive Method for Initialization for details on this alternate
a receive operation, a slower TRDY response will allow method.
additional data to accumulate inside of the FIFO. If the Re-Initialization
accesses are slow enough, a complete DWord may be-
come available before the end of the bus mastership The transmitter and receiver sections of the Am79C971
period and, thereby, increase the number of transfers in controller can be turned on via the initialization block
that period. The general rule is that the longer the Bus (DTX, DRX, CSR15, bits 1-0). The states of the trans-
Grant latency, the slower the bus transfer operations; mitter and receiver are monitored by the host through
the slower the clock speed, the higher the transmit wa- CSR0 (RXON, TXON bits). The Am79C971 controller
termark; or the lower the receive watermark, the longer should be re-initialized if the transmitter and/or the re-
the total burst length will be. ceiver were not turned on during the original initializa-
tion, and it was subsequently required to activate them
When a FIFO DMA burst operation is preempted, the or if either section was shut off due to the detection of
Am79C971 controller will not relinquish bus ownership an error condition (MERR, UFLO, TX BUFF error).
until the PCI Latency Timer expires.
Re-initialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
to CSR15, and then setting the START bit in CSR0.
Am79C971 53
Note that this form of restart will not perform the same packet if it had already begun. The Am79C971 control-
in the Am79C971 controller as in the C-LANCE device. ler will not receive any new packets after the comple-
In particular, upon restart, the Am79C971 controller re- tion of the current reception. Additionally, all transmit
loads the transmit and receive descriptor pointers with packets stored in the transmit FIFOs and the transmit
their respective base addresses. This means that the buffer area in the external SRAM (if one is present) will
software must clear the descriptor OWN bits and reset be transmitted, and all receive packets stored in the re-
its descriptor ring pointers before restar ting the ceive FIFOs and the receive buffer area in the external
Am79C971 controller. The reload of descriptor base SRAM (if one is present) will be transferred into system
addresses is performed in the C-LANCE device only memory. Since the FIFO and external SRAM contents
after initialization, so that a restart of the C-LANCE are flushed, it may take much longer before the
without initialization leaves the C-LANCE pointing at Am79C971 controller enters the suspend mode. The
the same descriptor locations as before the restart. amount of time that it takes depends on many factors
including the size of the external SRAM, bus latency,
Suspend
and network traffic level.
The Am79C971 controller offers two suspend modes
that allows easy updating of the CSR registers without Upon completion of the described operations, the
going through a full re-initialization of the device. The Am79C971 controller sets the read-version of SPND to
suspend modes also allow stopping the device with or- 1 and enters the suspend mode. In suspend mode, all
derly termination of all network activity. of the CSR and BCR registers are accessible. As long
as the Am79C971 controller is not reset while in sus-
The host requests the Am79C971 controller to enter pend mode (by H_RESET, S_RESET, or by setting the
the suspend mode by setting SPND (CSR5, bit 0) to 1. STOP bit), no re-initialization of the device is required
The host must poll SPND until it reads back 1 to deter- after the device comes out of suspend mode. When
mine that the Am79C971 controller has entered the SPND is set to 0, the Am79C971 controller will leave
suspend mode. When the host sets SPND to 1, the pro- the suspend mode and will continue at the transmit and
cedure taken by the Am79C971 controller to enter the receive descriptor ring locations, where it had been
suspend mode depends on the setting of the fast sus- when it entered the suspend mode.
pend enable bit (FASTSPND, CSR7, bit 15).
See the section on Magic Packet™ technology for de-
When a fast suspend is requested (FASTSPND is set tails on how that affects suspension of the Am79C971
to 1), the Am79C971 controller performs a quick entry controller.
into the suspend mode. At the time the SPND bit is set,
the Am79C971 controller will continue the DMA pro- Buffer Management
cess of any transmit and/or receive packets that have Buffer management is accomplished through message
already begun DMA activity until the network activity descriptor entries organized as ring structures in mem-
has been completed. In addition, any transmit packet ory. There are two descriptor rings, one for transmit and
that had started transmission will be fully transmitted one for receive. Each descriptor describes a single
and any receive packet that had begun reception will be buffer. A frame may occupy one or more buffers. If mul-
fully received. However, no additional packets will be tiple buffers are used, this is referred to as buffer chain-
transmitted or received and no additional transmit or re- ing.
ceive DMA activity will begin after network activity has
Descriptor Rings
ceased. Hence, the Am79C971 controller may enter
the suspend mode with transmit and/or receive packets Each descriptor ring must occupy a contiguous area of
still in the FIFOs or external SRAM. This offers a worst memory. During initialization, the user-defined base
case suspend time of a maximum length packet over address for the transmit and receive descriptor rings,
the possibility of completely emptying the external as well as the number of entries contained in the de-
SRAM. Care must be exercised in this mode, because scriptor rings are set up. The programming of the soft-
the entire memory subsystem of the Am79C971 con- ware style (SWSTYLE, BCR20, bits 7-0) affects the
troller is suspended. Any changes to either the descrip- way the descriptor rings and their entries are arranged.
tor r ings or the exter nal SRAM can cause the When SWSTYLE is at its default value of 0, the de-
Am79C971 controller to start up in an unknown condi- scriptor rings are backwards compatible with the
tion and could cause data corruption. Am79C90 C-LANCE and the Am79C96x PCnet-ISA
When FASTSPNDE is 0 and the SPND bit is set, the family. The descriptor ring base addresses must be
Am79C971 controller may take longer before entering aligned to an 8-byte boundary and a maximum of 128
the suspend mode. At the time the SPND bit is set, the ring entries is allowed when the ring length is set
Am79C971 controller will complete the DMA process of through the TLEN and RLEN fields of the initialization
a transmit packet if it had already begun and the block. Each ring entry contains a subset of the three
Am79C971 controller will completely receive a receive 32-bit transmit or receive message descriptors (TMD,
RMD) that are organized as four 16-bit structures
54 Am79C971
(SSIZE32 (BCR20, bit 8) is set to 0). Note that even To permit the queuing and de-queuing of message
though the Am79C971 controller treats the descriptor buffers, ownership of each buffer is allocated to either
entries as 16-bit structures, it will always perform 32-bit the Am79C971 controller or the host. The OWN bit
bus transfers to access the descriptor entries. The within the descriptor status information, either TMD or
value of CSR2, bits 15-8, is used as the upper 8-bits for RMD, is used for this purpose.
all memory addresses during bus master transfers.
When OWN is set to 1, it signifies that the Am79C971
When SWSTYLE is set to 2 or 3, the descriptor ring controller currently has ownership of this ring descrip-
base addresses must be aligned to a 16-byte bound- tor and its associated buffer. Only the owner is permit-
ary, and a maximum of 512 ring entries is allowed when ted to relinquish ownership or to write to any field in the
the ring length is set through the TLEN and RLEN fields descriptor entry. A device that is not the current owner
of the initialization block. Each ring entry is organized of a descriptor entry cannot assume ownership or
as three 32-bit message descriptors (SSIZE32 change any field in the entry. A device may, however,
(BCR20, bit 8) is set to 1). The fourth DWord is reread from a descriptor that it does not currently own.
served. When SWSTYLE is set to 3, the order of the Software should always read descriptor entries in se-
message descriptors is optimized to allow read and quential order. When software finds that the current de-
write access in burst mode. scriptor is owned by the Am79C971 controller, then the
software must not read ahead to the next descriptor.
For any software style, the ring lengths can be set be-
The software should wait at a descriptor it does not own
yond this range (up to 65535) by writing the transmit
until the Am79C971 controller sets OWN to 0 to release
and receive ring length registers (CSR76, CSR78) di-
ownership to the software. (When LAPPEN (CSR3, bit
rectly.
5) is set to 1, this rule is modified. See the LAPPEN de-
Each ring entry contains the following information: scription. At initialization, the Am79C971 controller
reads the base address of both the transmit and re-
■ The address of the actual message data buffer in
ceive descriptor rings into CSRs for use by the
user or host memory
Am79C971 controller during subsequent operations.
■ The length of the message buffer
Figure 31 illustrates the relationship between the initial-
■ Status information indicating the condition of the ization base address, the initialization block, the re-
buffer ceive and transmit descriptor ring base addresses, the
receive and transmit descriptors, and the receive and
transmit data buffers, when SSIZE32 is cleared to 0.
Am79C971 55
N N N
N
•
•
•
Rcv Descriptor
Ring
1st 2nd
CSR2 CSR1 desc. desc.
IADR[31:16] IADR[15:0]
RMD RMD0
RMD RMD RMD
Initialization
Block
MOD Data Data Data

PADR[15:0] Rcv
Buffer Buffer Buffer
PADR[31:16] Buffers 1 2 N
PADR[47:32]
LADRF[15:0]
M M M
LADRF[31:16] M
LADRF[47:32] •
•
LADRF[63:48] •
RDRA[15:0] Xmt Descriptor
RLE RES RDRA[23:16] Ring
TDRA[15:0]
1st 2nd
TLE RES TDRA[23:16] desc. desc.
TMD TMD
TMD TMD TMD
Xmt Data Data Data

Buffers 1 2 M
20550D-34
Figure 31. 16-Bit Software Model
Note that the value of CSR2, bits 15-8, is used as the the appropriate Receive Descriptor Table Entry
upper 8-bits for all memory addresses during bus mas- (RDTE). It will then use the current transmit descriptor
ter transfers. address (stored internally) to vector to the appropriate
Transmit Descriptor Table Entry (TDTE). The accesses
Figure 32 illustrates the relationship between the initial-
will be made in the following order: RMD1, then RMD0
ization base address, the initialization block, the re-
of the current RDTE during one bus arbitration, and
ceive and transmit descriptor ring base addresses, the
after that, TMD1, then TMD0 of the current TDTE dur-
receive and transmit descriptors, and the receive and
ing a second bus arbitration. All information collected
transmit data buffers, when SSIZE32 is set to 1.
during polling activity will be stored internally in the ap-
Polling propriate CSRs, if the OWN bit is set (i.e., CSR18,
If there is no network channel activity and there is no CSR19, CSR20, CSR21, CSR40, CSR42, CSR50,
pre- or post-receive or pre- or post-transmit activity CSR52).
being performed by the Am79C971 controller, then the A typical receive poll is the product of the following con-
Am79C971 controller will periodically poll the current ditions:
receive and transmit descriptor entries in order to as-
certain their ownership. If the TXDPOLL bit in CSR4 is 1. Am79C971 controller does not own the current
set, then the transmit polling function is disabled. RDTE and the poll time has elapsed and
RXON = 1 (CSR0, bit 5), or
A typical polling operation consists of the following se-
2. Am79C971 controller does not own the next RDTE
quence. The Am79C971 controller will use the current
and there is more than one receive descriptor in the
receive descriptor address stored internally to vector to
ring and the poll time has elapsed and RXON = 1.
56 Am79C971
N N N
N
•
•
•
Rcv Descriptor
1st Ring 2nd
desc. desc.
CSR2 CSR1 start start
IADR[31:16] IADR[15:0]
RMD RMD
RMD RMD RMD
Initialization
Block
TLE RES RLE RES MODE
Rcv Data Data Data
PADR[31:0] Buffer Buffer Buffer
RES PADR[47:32] Buff 1 2 N
LADRF[31:0]
LADRF[63:32]
M M M
RDRA[31:0] M
TDRA[31:0] •
•
•
Xmt Descriptor
1st
Ring 2nd
desc. desc.
start start
TMD0 TMD0
TMD1 TMD2 TMD3
Xmt Data Data Data

Buff 1 2 M
20550D-35
Figure 32. 32-Bit Software Model
If RXON is cleared to 0, the Am79C971 controller will Setting the TDMD bit of CSR0 will cause the microcode
never poll RDTE locations. controller to exit the poll counting code and immedi-
ately perform a polling operation. If RDTE ownership
In order to avoid missing frames, the system should
has not been previously established, then an RDTE
have at least one RDTE available. To minimize poll ac-
poll will be performed ahead of the TDTE poll. If the mi-
tivity, two RDTEs should be available. In this case, the
crocode is not executing the poll counting code when
poll operation will only consist of the check of the status
the TDMD bit is set, then the demanded poll of the
of the current TDTE.
TDTE will be delayed until the microcode returns to the
A typical transmit poll is the product of the following poll counting code.
conditions:
The user may change the poll time value from the de-
1. Am79C971 controller does not own the current fault of 65,536 clock periods by modifying the value in
TDTE and TXDPOLL = 0 (CSR4, bit 12) and the Polling Interval register (CSR47).
TXON = 1 (CSR0, bit 4) and
Transmit Descriptor Table Entry
the poll time has elapsed, or
If, after a Transmit Descriptor Table Entry (TDTE) ac-
2. Am79C971 controller does not own the current
cess, the Am79C971 controller finds that the OWN bit
TDTE and TXDPOLL = 0 and TXON = 1 and
of that TDTE is not set, the Am79C971 controller re-
a frame has just been received, or
sumes the poll time count and re-examines the same
3. Am79C971 controller does not own the current TDTE at the next expiration of the poll time count.
TDTE and TXDPOLL = 0 and TXON = 1 and
a frame has just been transmitted.
Am79C971 57
If the OWN bit of the TDTE is set, but the Start of transmission the Am79C971 controller will read in buff-
Packet (STP) bit is not set, the Am79C971 controller ers for the next frame and clear their OWN bits for all
will immediately request the bus in order to clear the but the last one. The first and all intermediate buffers of
OWN bit of this descriptor. (This condition would nor- the second frame can have their OWN bits cleared be-
mally be found following a late collision (LCOL) or retry fore the Am79C971 controller returns ownership for the
(RTRY) error that occurred in the middle of a transmit last buffer of the first frame.
frame chain of buffers.) After resetting the OWN bit of
If an error occurs in the transmission before all of the
this descriptor, the Am79C971 controller will again im-
bytes of the current buffer have been transferred, trans-
mediately request the bus in order to access the next
mit status of the current buffer will be immediately up-
TDTE location in the ring.
dated. If the buffer does not contain the end of packet,
If the OWN bit is set and the buffer length is 0, the OWN the Am79C971 controller will skip over the rest of the
bit will be cleared. In the C-LANCE device, the buffer frame which experienced the error. This is done by re-
length of 0 is interpreted as a 4096-byte buffer. A zero turning to the polling microcode where the Am79C971
length buffer is acceptable as long as it is not the last controller will clear the OWN bit for all descriptors with
buffer in a chain (STP = 0 and ENP = 1). OWN = 1 and STP = 0 and continue in like manner until
a descriptor with OWN = 0 (no more transmit frames in
If the OWN bit and STP are set, then microcode control
the ring) or OWN = 1 and STP = 1 (the first buffer of a
proceeds to a routine that will enable transmit data
new frame) is reached.
transfers to the FIFO. The Am79C971 controller will
look ahead to the next transmit descriptor after it has At the end of any transmit operation, whether success-
performed at least one transmit data transfer from the ful or with errors, immediately following the completion
first buffer. of the descriptor updates, the Am79C971 controller will
always perform another polling operation. As described
If the Am79C971 controller does not own the next
earlier, this polling operation will begin with a check of
TDTE (i.e., the second TDTE for this frame), it will com-
the current RDTE, unless the Am79C971 controller al-
plete transmission of the current buffer and update the
ready owns that descriptor. Then the Am79C971 con-
status of the current (first) TDTE with the BUFF and
troller will poll the next TDTE. If the transmit descriptor
UFLO bits being set. If DXSUFLO (CSR3, bit 6) is
OWN bit has a 0 value, the Am79C971 controller will
cleared to 0, the underflow error will cause the transmit-
resume incrementing the poll time counter. If the trans-
ter to be disabled (CSR0, TXON = 0). The Am79C971
mit descriptor OWN bit has a value of 1, the Am79C971
controller will have to be re-initialized to restore the
controller will begin filling the FIFO with transmit data
transmit function. Setting DXSUFLO to 1 enables the
and initiate a transmission. This end-of-operation poll
Am79C971 controller to gracefully recover from an un-
coupled with the TDTE lookahead operation allows the
derflow error. The device will scan the transmit descrip-
Am79C971 controller to avoid inserting poll time counts
tor ring until it finds either the start of a new frame or a
between successive transmit frames.
TDTE it does not own. To avoid an underflow situation
in a chained buffer transmission, the system should al- By default, whenever the Am79C971 controller com-
ways set the transmit chain descriptor own bits in re- pletes a transmit frame (either with or without error) and
verse order. writes the status information to the current descriptor,
then the TINT bit of CSR0 is set to indicate the comple-
If the Am79C971 controller does own the second TDTE
tion of a transmission. This causes an interrupt signal if
in a chain, it will gradually empty the contents of the first
the IENA bit of CSR0 has been set and the TINTM bit
buffer (as the bytes are needed by the transmit opera-
of CSR3 is cleared. The Am79C971 controller provides
tion), perform a single-cycle DMA transfer to update the
two modes to reduce the number of transmit interrupts.
status of the first descriptor (clear the OWN bit in
The interrupt of a successfully transmitted frame can
TMD1), and then it may perform one data DMA access
be suppressed by setting TINTOKD (CSR5, bit 15) to
on the second buffer in the chain before executing an-
1. Another mode, which is enabled by setting LTINTEN
other lookahead operation. (i.e., a lookahead to the
(CSR5, bit 14) to 1, allows suppression of interrupts for
third descriptor.)
successful transmissions for all but the last frame in a
It is imperative that the host system never reads the sequence.
TDTE OWN bits out of order. The Am79C971 controller
Receive Descriptor Table Entry
normally clears OWN bits in strict FIFO order. However,
the Am79C971 controller can queue up to two frames If the Am79C971 controller does not own both the cur-
in the transmit FIFO. When the second frame uses rent and the next Receive Descriptor Table Entry
buffer chaining, the Am79C971 controller might return (RDTE), then the Am79C971 controller will continue to
ownership out of normal FIFO order. The OWN bit for poll according to the polling sequence described
last (and maybe only) buffer of the first frame is not above. If the receive descriptor ring length is one, then
cleared until transmission is completed. During the there is no next descriptor to be polled.
58 Am79C971
If a poll operation has revealed that the current and the date the current RDTE status with the end of frame
next RDTE belong to the Am79C971 controller, then (ENP) indication set, write the message byte count
additional poll accesses are not necessary. Future poll (MCNT) for the entire frame into RMD2, and overwrite
operations will not include RDTE accesses as long as the “current” entries in the CSRs with the “next” entries.
the Am79C971 controller retains ownership of the cur-
Receive Frame Queuing
rent and the next RDTE.
The Am79C971 controller supports the lack of RDTEs
When receive activity is present on the channel, the when external SRAM (SRAM SIZE in BCR 25, bits 7-0)
Am79C971 controller waits for the complete address of is present through the Receive Frame Queuing mech-
the message to arrive. It then decides whether to ac- anism. When the SRAM SIZE = 0, then the Am79C971
cept or reject the frame based on all active addressing controller reverts back to the PCnet PCI II mode of op-
schemes. If the frame is accepted, the Am79C971 con- eration. This operation is automatic and does not re-
troller checks the current receive buffer status register quire any programming by the host. When SRAM is
CRST (CSR41) to determine the ownership of the cur- present, the Receive Frame Queuing mechanism
rent buffer. allows a slow protocol to manage more frames without
If ownership is lacking, the Am79C971 controller will the high frame loss rate normally attributed to FIFO
immediately perform a final poll of the current RDTE. If based network controllers.
ownership is still denied, the Am79C971 controller has The Am79C971 controller will store the incoming
no buffer in which to store the incoming message. The frames in the extended FIFOs until polling takes place;
MISS bit will be set in CSR0 and the Missed Frame if enabled, it discovers it owns an RDTE. The stored
Counter (CSR112) will be incremented. Another poll of frames are not altered in any way until written out into
the current RDTE will not occur until the frame has fin- system buffers. When the receive FIFO overflows, fur-
ished. ther incoming receive frames will be missed during that
If the Am79C971 controller sees that the last poll (ei- time. As soon as the network receive FIFO is empty, in-
ther a normal poll, or the final effort described in the coming frames are processed as normal. Status on a
above paragraph) of the current RDTE shows valid per frame basis is not kept during the overflow process.
ownership, it proceeds to a poll of the next RDTE. Fol- Statistic counters are maintained and accurate during
lowing this poll, and regardless of the outcome of this that time.
poll, transfers of receive data from the FIFO may begin. During the time that the Receive Frame Queuing mech-
Regardless of ownership of the second receive de- anism is in operation, the Am79C971 controller relies
scriptor, the Am79C971 controller will continue to per- on the Receive Poll Time Counter (CSR 48) to control
form receive data DMA transfers to the first buffer. If the the worst case access to the RDTE. The Receive Poll
frame length exceeds the length of the first buffer, and Time Counter is programmed through the Receive Poll-
the Am79C971 controller does not own the second ing Interval (CSR49) register. The Received Polling In-
buffer, ownership of the current descriptor will be terval defaults to approximately 2 ms. The Am79C971
passed back to the system by writing a 0 to the OWN controller will also try to access the RDTE during nor-
bit of RMD1. Status will be written indicating buffer mal descriptor accesses whether they are transmit or
(BUFF = 1) and possibly overflow (OFLO = 1) errors. receive accesses. The host can force the Am79C971
controller to immediately access the RDTE by setting
If the frame length exceeds the length of the first (cur- the RDMD (CSR 7, bit 13) to 1. Its operation is similar
rent) buffer, and the Am79C971 controller does own to the transmit one. The polling process can be dis-
the second (next) buffer, ownership will be passed back abled by setting the RXDPOLL (CSR7, bit 12) bit. This
to the system by writing a 0 to the OWN bit of RMD1 will stop the automatic polling process and the host
when the first buffer is full. The OWN bit is the only bit must set the RDMD bit to initiate the receive process
modified in the descriptor. Receive data transfers to the into host memory. Receive frames are still stored even
second buffer may occur before the Am79C971 con- when the receive polling process is disabled.
troller proceeds to look ahead to the ownership of the
third buffer. Such action will depend upon the state of Software Interrupt Timer
the FIFO when the OWN bit has been updated in the The Am79C971 controller is equipped with a software
first descriptor. In any case, lookahead will be per- programmable free-running interrupt timer. The timer is
formed to the third buffer and the information gathered constantly running and will generate an interrupt STINT
will be stored in the chip, regardless of the state of the (CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to
ownership bit. 1. After generating the interrupt, the software timer will
This activity continues until the Am79C971 controller load the value stored in STVAL and restart. The timer
recognizes the completion of the frame (the last byte of value STVAL (BCR31, bits 15-0) is interpreted as an
this receive message has been removed from the unsigned number with a resolution of 12.8 µs. For in-
FIFO). The Am79C971 controller will subsequently up- stance, a value of 122 ms would be programmed with
Am79C971 59
a value of 9531 (253Bh). The default value of STVAL is automatically strip pad bytes from the received mes-
FFFFh which yields the approximate maximum 838 ms sage by observing the value in the length field and by
timer duration. A write to STVAL restarts the timer with stripping excess bytes if this value is below the mini-
the new contents of STVAL. mum data size (46 bytes). Both features can be inde-
pendently over-ridden to allow illegally short (less than
Media Access Control 64 bytes of frame data) messages to be transmitted
The Media Access Control (MAC) engine incorporates and/or received. The use of this feature reduces bus
the essential protocol requirements for operation of an utilization because the pad bytes are not transferred
Ethernet/IEEE 802.3-compliant node, and provides the into or out of main memory.
interface between the FIFO subsystem and the
Framing
Manchester Encoder/Decoder (MENDEC) or the MII.
The MAC engine has been changed from a single-bit The MAC engine will autonomously handle the con-
wide engine into a 4-bit (nibble) wide engine. This was struction of the transmit frame. Once the transmit FIFO
done to accommodate the nibble wide MII. has been filled to the predetermined threshold (set by
XMTSP in CSR80) and access to the channel is cur-
This section describes operation of the MAC engine rently permitted, the MAC engine will commence the 7-
when operating in half-duplex mode. When operating in byte preamble sequence (10101010b, where first bit
half-duplex mode, the MAC engine is fully compliant to transmitted is a 1). The MAC engine will subsequently
Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard append the Star t Frame Delimiter (SFD) byte
1990 Second Edition) and ANSI/IEEE 802.3 (1985). (10101011b) followed by the serialized data from the
When operating in full-duplex mode, the MAC engine transmit FIFO. Once the data has been completed, the
behavior changes as described in the section Full- MAC engine will append the FCS (most significant bit
Duplex Operation. first) which was computed on the entire data portion of
The MAC engine provides programmable enhanced the frame. The data portion of the frame consists of
features designed to minimize host supervision, bus destination address, source address, length/type, and
utilization, and pre- or post-message processing. frame data. The user is responsible for the correct or-
These features include the ability to disable retries after dering and content in each of these fields in the frame.
a collision, dynamic FCS generation on a frame-by- The MAC does not use the content in the length/type
frame basis, automatic pad field insertion and deletion field unless APAD_XMT (CSR4, bit 11) is set and the
to enforce minimum frame size attributes, automatic re- data portion of the frame is shorter than 60 bytes.
transmission without reloading the FIFO, and auto- The receive section of the MAC engine will detect an in-
matic deletion of collision fragments. coming preamble sequence and lock to the encoded
The two primary attributes of the MAC engine are: clock. The internal MENDEC will decode the serial bit
stream and present this to the MAC engine. The MAC
■ Transmit and receive message data encapsulation will discard the first 8 bits of information before search-
— Framing (frame boundary delimitation, frame ing for the SFD sequence. Once the SFD is detected,
synchronization) all subsequent bits are treated as part of the frame.
— Addressing (source and destination address During MII operation, the MAC engine will detect the in-
handling) coming preamble sequence when the RX_DV signal is
activated by the external PHY. The MAC will discard the
— Error detection (physical medium transmission preamble and begin searching for the SFD except in
errors) the case of 100BASE-T4. In that case, the SFD will be
■ Media access management the first nibble across the MII interface. Once the SFD
is detected, all subsequent nibbles are treated as part
— Medium allocation (collision avoidance, except of the frame. The MAC engine will inspect the length
in full-duplex operation) field to ensure minimum frame size, strip unnecessary
— Contention resolution (collision handling, except pad characters (if enabled), and pass the remaining
in full-duplex operation) bytes through the receive FIFO to the host. If pad strip-
ping is performed, the MAC engine will also strip the re-
Transmit and Receive Message Data Encapsulation
ceived FCS bytes, although normal FCS computation
The MAC engine provides minimum frame size en- and checking will occur. Note that apart from pad strip-
forcement for transmit and receive frames. When ping, the frame will be passed unmodified to the host.
APAD_XMT (CSR, bit 11) is set to 1, transmit mes- If the length field has a value of 46 or greater, all frame
sages will be padded with sufficient bytes (containing bytes including FCS will be passed unmodified to the
00h) to ensure that the receiving station will observe an receive buffer, regardless of the actual frame length.
information field (destination address, source address,
length/type, data, and FCS) of 64 bytes. When If the frame terminates or suffers a collision before 64
ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will bytes of information (after SFD) have been received,
60 Am79C971
the MAC engine will automatically delete the frame is either sent as a runt packet (which will be deleted by
from the receive FIFO, without host intervention. The the receiving station) or as an invalid FCS (which will
Am79C971 controller has the ability to accept runt also cause the receiver to reject the message).
packets for diagnostic purposes and proprietary net-
The status of each receive message is available in the
works.
appropriate Receive Message Descriptor (RMD) and
Destination Address Handling CSR areas. All received frames are passed to the host
The first 6 bytes of information after SFD will be inter- regardless of any error. The FRAM error will only be re-
preted as the destination address field. The MAC engine ported if an FCS error is detected and there is a non-
provides facilities for physical (unicast), logical (multi- integral number of bytes in the message.
cast), and broadcast address reception. During the reception, the FCS is generated on every
Error Detection nibble (including the dribbling bits) coming from the ca-
ble, although the internally saved FCS value is only up-
The MAC engine provides several facilities which re- dated on the eighth bit (on each byte boundary). The
port and recover from errors on the medium. In addi- MAC engine will ignore up to 7 additional bits at the end
tion, it protects the network from gross errors due to of a message (dribbling bits), which can occur under
inability of the host to keep pace with the MAC engine normal network operating conditions. The framing error
activity. is reported to the user as follows:
On completion of transmission, the following transmit ■ If the number of dribbling bits are 1 to 7 and there is
status is available in the appropriate Transmit Message no FCS error, then there is no Framing error (FRAM
Descriptor (TMD) and Control and Status Register = 0).
(CSR) areas:
■ If the number of dribbling bits are 1 to 7 and there is
■ The number of transmission retry attempts (1, a FCS error, then there is also a Framing error
MORE, RTRY, and TRC). (FRAM = 1).
■ Whether the MAC engine had to Defer (DEF) due to ■ If the number of dribbling bits is 0, then there is no
channel activity. Framing error. There may or may not be a FCS er-
■ Excessive deferral (EXDEF), indicating that the ror.
transmitter experienced Excessive Deferral on this ■ If the number of dribbling bits is EIGHT, then there
transmit frame, where Excessive Deferral is defined is no Framing error. FCS error will be reported and
in the ISO 8802-3 (IEEE/ANSI 802.3) standard. the receive message count will indicate one extra
■ Loss of Carrier (LCAR), indicating that there was an byte.
interruption in the ability of the MAC engine to mon- Note that if the MAC engine detects a received frame
itor its own transmission. Repeated LCAR errors in- which has a 00b pattern in the preamble (after the first
dicate a potentially faulty transceiver or network 8-bits which are ignored), the entire frame will be ig-
connection. nored. The MAC engine will wait for the network to go
■ Late Collision (LCOL) indicates that the transmis- inactive before attempting to receive additional frames.
sion suffered a collision after the slot time. This is in-
Media Access Management
dicative of a badly configured network. Late
collisions should not occur in a normal operating The basic requirement for all stations on the network is
network. to provide fairness of channel allocation. The IEEE
802.3/Ethernet protocols define a media access mech-
■ Collision Error (CERR) indicates that the trans-
anism which permits all stations to access the channel
ceiver did not respond with an SQE Test message
with equality. Any node can attempt to contend for the
within the first 4 µs after a transmission was com-
channel by waiting for a predetermined time (Inter
pleted. This may be due to a failed transceiver, dis-
Packet Gap) after the last activity, before transmitting
connected or faulty transceiver drop cable, or
on the media. The channel is a multidrop communica-
because the transceiver does not support this fea-
tions media (with various topological configurations
ture (or it is disabled). SQE Test is only valid for 10-
permitted), which allows a single station to transmit and
Mbps networks.
all other stations to receive. If two nodes simulta-
In addition to the reporting of network errors, the MAC neously contend for the channel, their signals will inter-
engine will also attempt to prevent the creation of any act causing loss of data, defined as a collision. It is the
network error due to the inability of the host to service responsibility of the MAC to attempt to avoid and
the MAC engine. During transmission, if the host fails recover from a collision, to guarantee data integrity for
to keep the transmit FIFO filled sufficiently, causing an the end-to-end transmission to the receiving station.
underflow, the MAC engine will guarantee the message
Am79C971 61
Medium Allocation that the Am79C971 controller will not attempt to receive
The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990) the receive frame, since it will start to transmit and gen-
requires that the CSMA/CD MAC monitor the medium erate a collision at 9.6 µs. The Am79C971 controller
for traffic by watching for carrier activity. When carrier is will complete the preamble (64-bit) and jam (32-bit) se-
detected, the media is considered busy, and the MAC quence before ceasing transmission and invoking the
should defer to the existing message. random backoff algorithm.
The ISO 8802-3 (IEEE/ANSI 802.3) standard also al- The Am79C971 controller allows the user to program
lows optionally a two-part deferral after a receive mes- the IPG and the first par t deferral (InterFrame-
sage. SpacingPart1 - IFS1) through CSR125. By changing
the IPG default value of 96 bit times (60h), the user can
See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1: a dj u s t th e fa ir ne s s o r ag gr e s s ive n es s o f t h e
Note: It is possible for the PLS carrier sense indication Am79C971 MAC on the network. By programming a
to fail to be asserted during a collision on the media. If lower number of bit times than the ISO/IEC 8802-3
the deference process simply times the inter-Frame standard requires, the Am79C971 MAC engine will be-
gap based on this indication, it is possible for a short in- come more aggressive on the network. This aggressive
terFrame gap to be generated, leading to a potential re- nature will give rise to the Am79C971 controller possi-
ception failure of a subsequent frame. To enhance bly capturing the network at times by forcing other less
system robustness, the following optional measures, aggressive compliant nodes to defer. By programming
as specified in 4.2.8, are recommended when Inter- a larger number of bit times, the Am79C971 MAC will
Frame-SpacingPart1 is other than 0: become less aggressive on the network and may defer
more often than normal. The performance of the
1. Upon completing a transmission, start timing the in- Am79C971 controller may decrease as the IPG value
terrupted gap, as soon as transmitting and carrier is increased from the default value, but the resulting be-
sense are both false. havior may improve network performance by reducing
2. When timing an inter-frame gap following reception, collisions. The Am79C971 controller uses the same
reset the inter-frame gap timing if carrier sense be- IPG for back-to-back transmits and receive-to-transmit
comes true during the first 2/3 of the inter-frame gap accesses. Changing IFS1 will alter the period for which
timing interval. During the final 1/3 of the interval, the Am79C971 MAC engine will defer to incoming re-
the timer shall not be reset to ensure fair access to ceive frames.
the medium. An initial period shorter than 2/3 of the
CAUTION: Care must be exercised when altering
interval is permissible including 0.
these parameters. Adverse network activity could
The MAC engine implements the optional receive two result!
part deferral algorithm, with an InterFrameSpacing-
This transmit two-part deferral algorithm is imple-
Part1 time of 6.0 µs. The InterFrameSpacingPart 2 in-
mented as an option which can be disabled using the
terval is, therefore, 3.4 µs.
DXMT2PD bit in CSR3. The IFS1 programming will
The Am79C971 controller will perform the two-part have no effect when DXMT2PD is set to 1, but the IPG
deferral algorithm as specified in Section 4.2.8 (Pro- programming value is still valid. Two part deferral after
cess Deference). The Inter Packet Gap (IPG) timer will transmission is useful for ensuring that severe IPG
start timing the 9.6 µs InterFrameSpacing after the re- shrinkage cannot occur in specific circumstances,
ceive carrier is deasserted. During the first part deferral causing a transmit message to follow a receive mes-
(InterFrameSpacingPart1 - IFS1), the Am79C971 con- sage so closely as to make them indistinguishable.
troller will defer any pending transmit frame and re-
During the time period immediately after a transmission
spond to the receive message. The IPG counter will be
has been completed, the external transceiver (in the
cleared to 0 continuously until the carrier deasserts, at
case of a standard AUI connected device) should gen-
which point the IPG counter will resume the 9.6 µs
erate the SQE Test message (a nominal 10-MHz burst
count once again. Once the IFS1 period of 6.0 µs has
of 5 to 15 bit times duration) on the CI± pair (within 0.6
elapsed, the Am79C971 controller will begin timing the
to 1.6 µs after the transmission ceases). During the
second part deferral (InterFrameSpacingPart2 - IFS2)
time period in which the SQE Test message is ex-
of 3.4 µs. Once IFS1 has completed and IFS2 has com-
pected, the Am79C971 controller will not respond to re-
menced, the Am79C971 controller will not defer to a re-
ceive carrier sense.
ceive frame if a transmit frame is pending. This means
62 Am79C971
See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1): and the transmit message will be flushed from the
FIFO.
“At the conclusion of the output function, the DTE
opens a time window during which it expects to see If a collision is detected after 512 bit times have been
the signal_quality_error signal asserted on the transmitted, the collision is termed a late collision. The
Control In circuit. The time window begins when MAC engine will abort the transmission, append the
the CARRIER_STATUS becomes jam sequence, and set the LCOL bit. No retry attempt
CARRIER_OFF. If execution of the output function will be scheduled on detection of a late collision, and
does not cause CARRIER_ON to occur, no SQE the transmit message will be flushed from the FIFO.
test occurs in the DTE. The duration of the window
The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires
shall be at least 4.0 µs but no more than 8.0 µs.
use of a “truncated binary exponential backoff” algo-
During the time window the Carrier Sense Function
rithm, which provides a controlled pseudo random
is inhibited.”
mechanism to enforce the collision backoff interval,
The Am79C971 controller implements a carrier sense before retransmission is attempted.
“blinding” period of 4.0 µ s length starting from the See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
deassertion of carrier sense after transmission. This ef-
fectively means that when transmit two part deferral is “At the end of enforcing a collision (jamming), the
enabled (DXMT2PD is cleared), the IFS1 time is from CSMA/CD sublayer delays before attempting to re-
4 µs to 6 µs after a transmission. However, since IPG transmit the frame. The delay is an integer multiple
shrinkage below 4 µs will rarely be encountered on a of slot time. The number of slot times to delay be-
correctly configured network, and since the fragment fore the nth retransmission attempt is chosen as a
size will be larger than the 4 µs blinding window, the uniformly distributed random integer r in the range:
IPG counter will be reset by a worst case IPG shrink-
0 ≤ r < 2k where k = min (n,10).”
age/fragment scenario and the Am79C971 controller
will defer its transmission. If carrier is detected within The Am79C971 controller provides an alternative algo-
the 4.0 to 6.0 µs IFS1 period, the Am79C971 controller rithm, which suspends the counting of the slot time/IPG
will not restart the “blinding” period, but only restart during the time that receive carrier sense is detected.
IFS1. This aids in networks where large numbers of nodes
Collision Handling are present, and numerous nodes can be in collision. It
effectively accelerates the increase in the backoff time
Collision detection is performed and reported to the
in busy networks and allows nodes not involved in the
MAC engine by the integrated Manchester Encoder/
collision to access the channel, while the colliding
Decoder (MENDEC) and through the MII via the COL
nodes await a reduction in channel activity. Once chan-
input pin. Both are functionally equivalent in operation.
nel activity is reduced, the nodes resolving the collision
If a collision is detected before the complete preamble/ time-out their slot time counters as normal.
SFD sequence has been transmitted, the MAC engine
This modified backoff algorithm is enabled when EMBA
will complete the preamble/SFD before appending the
(CSR3, bit 3) is set to 1.
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits Transmit Operation
being transmitted, the MAC engine will abort the trans-
The transmit operation and features of the Am79C971
mission and append the jam sequence immediately.
controller are controlled by programmable options. The
The jam sequence is a 32-bit all zeros pattern.
Am79C971 controller offers a large transmit FIFO to
The MAC engine will attempt to transmit a frame a total provide frame buffering for increased system latency,
of 16 times (initial attempt plus 15 retries) due to nor- automatic retransmission with no FIFO reload, and au-
mal collisions (those within the slot time). Detection of tomatic transmit padding.
collision will cause the transmission to be rescheduled
Transmit Function Programming
to a time determined by the random backoff algorithm.
If a single retry was required, the 1 bit will be set in the Automatic transmit features such as retry on collision,
transmit frame status. If more than one retry was re- FCS generation/transmission, and pad field insertion
quired, the MORE bit will be set. If all 16 attempts ex- can all be programmed to provide flexibility in the (re-)
perienced collisions, the RTRY bit will be set (1 and transmission of messages.
MORE will be clear), and the transmit message will be Disable retry on collision (DRTY) is controlled by the
flushed from the FIFO. If retries have been disabled by DRTY bit of the Mode register (CSR15) in the initializa-
setting the DRTY bit in CSR15, the MAC engine will tion block.
abandon transmission of the frame on detection of the
first collision. In this case, only the RTRY bit will be set Automatic pad field insertion is controlled by the
APAD_XMT bit in CSR4.
Am79C971 63
The disable FCS generation/transmission feature can IEEE 802.3/Ethernet to be guaranteed with no software
be programmed as a static feature or dynamically on a intervention from the host/controlling process. Setting
frame-by-frame basis. the APAD_XMT bit in CSR4 enables the automatic
padding feature. The pad is placed between the LLC
Transmit FIFO Watermark (XMTFW) in CSR80 sets the
data field and FCS field in the IEEE 802.3 frame. FCS
point at which the BMU requests more data from the
is always added if the frame is padded, regardless of
transmit buffers for the FIFO. A minimum of XMTFW
the state of DXMTFCS (CSR15, bit 3) or ADD_FCS/
empty spaces must be available in the transmit FIFO
NO_FCS (TMD1, bit 29). The transmit frame will be
before the BMU will request the system bus in order to
padded by bytes with the value of 00H. The default
transfer transmit frame data into the transmit FIFO.
value of APAD_XMT is 0, which will disable automatic
Transmit Start Point (XMTSP) in CSR80 sets the point pad generation after H_RESET.
when the transmitter actually attempts to transmit a
It is the responsibility of upper layer software to cor-
frame onto the media. A minimum of XMTSP bytes
rectly define the actual length field contained in the
must be written to the transmit FIFO for the current
message to correspond to the total number of LLC
frame before transmission of the current frame will be-
Data bytes encapsulated in the frame (length field as
gin. (When automatically padded packets are being
defined in the ISO 8802-3 (IEEE/ANSI 802.3) stan-
sent, it is conceivable that the XMTSP is not reached
dard). The length value contained in the message is not
when all of the data has been transferred to the FIFO.
used by the Am79C971 controller to compute the ac-
In this case, the transmission will begin when all of the
tual number of pad bytes to be inser ted. The
frame data has been placed into the transmit FIFO.)
Am79C971 controller will append pad bytes dependent
The default value of XMTSP is 01b, meaning there has
on the actual number of bits transmitted onto the net-
to be 64 bytes in the transmit FIFO to start a transmis-
work. Once the last data byte of the frame has com-
sion.
pleted, prior to appending the FCS, the Am79C971
Automatic Pad Generation controller will check to ensure that 544 bits have been
Transmit frames can be automatically padded to extend transmitted. If not, pad bytes are added to extend the
them to 64 data bytes (excluding preamble). This al- frame size to this value, and the FCS is then added.
lows the minimum frame size of 64 bytes (512 bits) for See Figure 33.
.
.
Preamble SFD Destination Source LLC

1010....1010 10101011 Address Address Length Data Pad FCS
56 8 6 6 2 4
Bits Bits Bytes Bytes Bytes Bytes
46 – 1500 20550D-36
Bytes
Figure 33. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
The 544 bit count is derived from the following: A minimum length transmit frame from the Am79C971
controller, therefore, will be 576 bits, after the FCS is
Minimum frame size (excluding preamble/SFD,
appended.
including FCS) 64 bytes 512 bits
Transmit FCS Generation
Preamble/SFD size 8 bytes 64 bits
Automatic generation and transmission of FCS for a
FCS size 4 bytes 32 bits transmit frame depends on the value of DXMTFCS
At the point that FCS is to be appended, the transmitted (CSR15, bit 3). If DXMTFCS is cleared to 0, the trans-
frame should contain: mitter will generate and append the FCS to the trans-
mitted frame. If the automatic padding feature is
Preamble/SFD + (Min Frame Size - FCS) invoked (APAD_XMT is set in CSR4), the FCS will be
64 + (512-32) = 544 bits appended to frames shorter than 64 bytes by the
Am79C971 controller regardless of the state of DXMT-
FCS or ADD_FCS/NO_FCS (TMD1, bit 29). Note that
the calculated FCS is transmitted most significant bit
64 Am79C971
first. The default value of DXMTFCS is 0 after descriptor(s) will be cleared until the STP (the next
H_RESET. frame) is found.
ADD_FCS (TMD1, bit 29) allows the automatic gener- Loss of Carrier
ation and transmission of FCS on a frame-by-frame When operating in half-duplex mode, a loss of carrier
basis. DXMTFCS should be set to 1 in this mode. To condition will be reported if the Am79C971 controller
generate FCS for a frame, ADD_FCS must be set in the cannot observe receive activity while it is transmitting
first descriptor of a frame (STP is set to 1). Note that bit on the AUI or GPSI por t. In AUI mode, after the
29 of TMD1 has the function of ADD_FCS if SWSTYLE Am79C971 controller initiates a transmission, it will ex-
(BCR20, bits 7-0) is programmed to 0, 2, or 3. pect to see data “looped-back” on the DI± pair. This will
Transmit Exception Conditions internally generate a “carrier sense,” indicating that the
integrity of the data path to and from the MAU is intact,
Exception conditions for frame transmission fall into
and that the MAU is operating correctly. This “carrier
two distinct categories: those conditions which are the
sense” signal must be asserted before the last bit is
result of normal network operation, and those which
transmitted on DO±. If “carrier sense” does not become
occur due to abnormal network and/or host related
active in response to the data transmission, or be-
events.
comes inactive before the end of transmission, the loss
Normal events which may occur and which are handled of carrier (LCAR) error bit will be set in TMD2 after the
autonomously by the Am79C971 controller include col- frame has been transmitted. The frame will not be re-
lisions within the slot time with automatic retry. The tried on the basis of an LCAR error. In GPSI mode,
Am79C971 controller will ensure that collisions which LCAR will be asserted if RXEN does not go active dur-
occur within 512 bit times from the start of transmission ing the transmission.
(including preamble) will be automatically retried with
When the internal 10BASE-T port is selected, LCAR
no host intervention. The transmit FIFO ensures this by
will be reported for every frame transmitted while the
guaranteeing that data contained within the FIFO will
network interface is in the Link Fail state.
not be overwritten until at least 64 bytes (512 bits) of
preamble plus address, length, and data fields have Late Collision
been transmitted onto the network without encounter- A late collision will be reported if a collision condition
ing a collision. Note that if DRTY (CSR15, bit 5) is set occurs after one slot time (512 bit times) after the trans-
to 1 or if the network interface is operating in full-duplex mit process was initiated (first bit of preamble com-
mode, no collision handling is required, and any byte of menced). The Am79C971 controller will abandon the
frame data in the FIFO can be overwritten as soon as it transmit process for that frame, set Late Collision
is transmitted. (LCOL) in the associated TMD2, and process the next
If 16 total attempts (initial attempt plus 15 retries) fail, transmit frame in the ring. Frames experiencing a late
the Am79C971 controller sets the RTRY bit in the cur- collision will not be retried. Recovery from this condi-
rent transmit TDTE in host memory (TMD2), gives up tion must be performed by upper layer software.
ownership (resets the OWN bit to 0) for this frame, and SQE Test Error
processes the next frame in the transmit ring for trans-
mission. During the IPG time following the completion of a trans-
mitted message, the AUI CI± pair is asserted by some
Abnormal network conditions include: transceivers as a self-test. The integral MENDEC will
■ Loss of carrier expect the SQE Test Message (nominal 10-MHz se-
quence) to be returned via the CI± pair within a 40-net-
■ Late collision work bit-time period after DI± goes inactive (this does
■ SQE Test Error (Does not apply to 10BASE-T port not apply if the 10BASE-T port is selected). If the CI±
or 100-Mbps networks.) input is not asserted within the 40 network bit-time pe-
riod following the completion of transmission, then the
These conditions should not occur on a correctly con-
Am79C971 controller will set the CERR bit in CSR0. In
figured IEEE 802.3 network operating in half-duplex
GPSI mode, CLSN must be asserted after the trans-
mode. If they do, they will be reported. None of these
mission or otherwise CERR will be set. CERR will be
conditions will occur on a network operating in full-
asserted in 10BASE-T mode, or in the 10BASE-T
duplex mode. (See the section Full-Duplex Operation
mode through the MII after transmit, if the network port
for more detail.)
is in Link Fail state. CERR will never cause INTA to be
When an error occurs in the middle of a multi-buffer activated. It will, however, set the ERR bit CSR0.
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
Am79C971 65
Receive Operation byte ordering is such that the first byte received from
the network (after the SFD) must match the least signif-
The receive operation and features of the Am79C971
icant byte of CSR12 (PADR[7:0]), and the sixth byte re-
controller are controlled by programmable options. The
ceived must match the most significant byte of CSR14
Am79C971 controller offers a large receive FIFO to
(PADR[47:40]).
provide frame buffering for increased system latency,
automatic flushing of collision fragments (runt packets), When DRCVPA (CSR15, bit 13) is set to 1, the
automatic receive pad stripping, and a variety of ad- Am79C971 controller will not accept unicast frames.
dress match options.
If the incoming frame is multicast, the Am79C971 con-
Receive Function Programming troller performs a calculation on the contents of the
Automatic pad field stripping is enabled by setting the destination address field to determine whether or not to
ASTRP_RCV bit in CSR4. This can provide flexibility in accept the frame. This calculation is explained in the
the reception of messages using the IEEE 802.3 frame section that describes the Logical Address Filter
format. (LADRF).
All receive frames can be accepted by setting the When all bits of the LADRF registers are 0, no multicast
PROM bit in CSR15. Acceptance of unicast and broad- frames are accepted, except for broadcast frames.
cast frames can be individually turned off by setting the Although broadcast frames are classified as special
DRCVPA or DRCVBC bits in CSR15. The Physical Ad- multicast frames, they are treated differently by the
dress register (CSR12 to CSR14) stores the address Am79C971 controller hardware. Broadcast frames are
that the Am79C971 controller compares to the destina- always accepted, except when DRCVBC (CSR15, bit
tion address of the incoming frame for a unicast ad- 14) is set.
dress match. The Logical Address Filter register
(CSR8 to CSR11) serves as a hash filter for multicast None of the address filtering described above applies
address match. when the Am79C971 controller is operating in the pro-
miscuous mode. In the promiscuous mode, all properly
The point at which the BMU will start to transfer data formed packets are received, regardless of the con-
from the receive FIFO to buffer memory is controlled by tents of their destination address fields. The promiscu-
the RCVFW bits in CSR80. The default established ous mode overrides the Disable Receive Broadcast bit
during H_RESET is 01b, which sets the watermark flag (DRCVBC bit l4 in the MODE register) and the Disable
at 64 bytes filled. Receive Physical Address bit (DRCVPA, CSR15, bit
For test purposes, the Am79C971 controller can be 13).
programmed to accept runt packets by setting RPA in The Am79C971 controller operates in promiscuous
CSR124. mode when PROM (CSR15, bit 15) is set.
Address Matching In addition, the Am79C971 controller provides the Ex-
The Am79C971 controller supports three types of ad- ternal Address Detection Interface (EADI) to allow ex-
dress matching: unicast, multicast, and broadcast. The ternal address filtering. See the section External
normal address matching procedure can be modified Address Detection Interface for further detail.
by programming three bits in CSR15, the mode register The receive descriptor entry RMD1 contains three bits
(PROM, DRCVPA, and DRCVBC). that indicate which method of address matching
If the first bit received after the SFD (the least signifi- caused the Am79C971 controller to accept the frame.
cant bit of the first byte of the destination address field) Note that these indicator bits are only available when
is 0, the frame is unicast, which indicates that the frame the Am79C971 controller is programmed to use 32-bit
is meant to be received by a single node. If the first bit structures for the descriptor entries (BCR20, bit 7-0,
received is 1, the frame is multicast, which indicates SWSTYLE is set to 2 or 3).
that the frame is meant to be received by a group of PAM (RMD1, bit 22) is set by the Am79C971 controller
nodes. If the destination address field contains all 1s, when it accepted the received frame due to a match of
the frame is broadcast, which is a special type of multi- the frame’s destination address with the content of the
cast. Frames with the broadcast address in the destina- physical address register.
tion address field are meant to be received by all nodes
on the local area network. LAFM (RMD1, bit 21) is set by the Am79C971 control-
ler when it accepted the received frame based on the
When a unicast frame arrives at the Am79C971 con- value in the logical address filter register.
troller, the controller will accept the frame if the destina-
tion address field of the incoming frame exactly BAM (RMD1, bit 20) is set by the Am79C971 controller
matches the 6-byte station address stored in the Phys- when it accepted the received frame because the
ical Address registers (PADR, CSR12 to CSR14). The frame’s destination address is of the type ’Broadcast’.
66 Am79C971
If DRCVBC (CSR15, bit 14) is cleared to 0, only BAM, Table 6. Receive Address Match
but not LAFM will be set when a Broadcast frame is re-
ceived, even if the Logical Address Filter is pro- PAM LAF BAM DRC Comment
grammed in such a way that a Broadcast frame would M VBC
pass the hash filter. If DRCVBC is set to 1 and the Log- 0 0 0 X Frame accepted due
ical Address Filter is programmed in such a way that a to PROM = 1 or no
Broadcast frame would pass the hash filter, LAFM will EADI reject
be set on the reception of a Broadcast frame. 1 0 0 X Physical address
When the Am79C971 controller operates in promiscu- match
ous mode and none of the three match bits is set, it is 0 1 0 0 Logical address filter
an indication that the Am79C971 controller only ac- match;
cepted the frame because it was in promiscuous mode. frame is not of type
broadcast
When the Am79C971 controller is not programmed to
be in promiscuous mode, but the EADI interface is en- 0 1 0 1 Logical address filter
abled, then when none of the three match bits is set, it match;
frame can be of type
is an indication that the Am79C971 controller only ac-
broadcast
cepted the frame because it was not rejected by driving
the EAR pin LOW within 64 bytes after SFD. 0 0 1 0 Broadcast frame
See Table 6 for receive address matches. The number of bytes to be stripped is calculated from
the embedded length field (as defined in the ISO 8802-
Automatic Pad Stripping
3 (IEEE/ANSI 802.3) definition) contained in the frame.
During reception of an IEEE 802.3 frame, the pad field The length indicates the actual number of LLC data
can be stripped automatically. Setting ASTRP_RCV bytes contained in the message. Any received frame
(CSR4, bit 0) to 1 enables the automatic pad stripping which contains a length field less than 46 bytes will have
feature. The pad field will be stripped before the frame the pad field stripped (if ASTRP_RCV is set). Receive
is passed to the FIFO, thus preserving FIFO space for frames which have a length field of 46 bytes or greater
additional frames. The FCS field will also be stripped, will be passed to the host unmodified.
since it is computed at the transmitting station based on
the data and pad field characters, and will be invalid for Figure 34 shows the byte/bit ordering of the received
a receive frame that has had the pad characters length field for an IEEE 802.3-compatible frame format.
stripped.
46 – 1500
Bytes
56 8 6 6 2 4
Bits Bits Bytes Bytes Bytes Bytes
Preamble SFD Destination Source LLC

Length Pad FCS
1010....1010 10101011 Address Address Data
1 – 1500 45 – 0
Bytes Bytes
Start of Frame
at Time = 0
Bit Bit Bit Bit
0 7 0 7
Increasing Time
Most Least
Significant Significant
Byte Byte 20550D-37
Figure 34. IEEE 802.3 Frame And Length Field Transmission Order
Am79C971 67
Since any valid Ethernet Type field value will always be mode, the transmitted data is looped back to the re-
greater than a normal IEEE 802.3 Length field (≥46), ceiver inside the controller without actually transmitting
the Am79C971 controller will not attempt to strip valid any data to the external network. The receiver will
Ethernet frames. Note that for some network protocols, move the received data to the next receive buffer,
the value passed in the Ethernet Type and/or IEEE where it can be examined by software. Alternatively, in
802.3 Length field is not compliant with either standard external loopback mode, data can be transmitted to
and may cause problems if pad stripping is enabled. and received from the external network.
Receive FCS Checking Loopback operation is enabled by setting LOOP
Reception and checking of the received FCS is per- (CSR15, bit 2) to 1. The mode of loopback operation is
formed automatically by the Am79C971 controller. dependent on the active network port and on the set-
Note that if the Automatic Pad Stripping feature is en- tings of the control bits INTL (CSR15, bit 6), MENDECL
abled, the FCS for padded frames will be verified (CSR15, bit 10), and TMAULOOP (BCR2, bit 14). The
against the value computed for the incoming bit stream setting of the full-duplex control bits in BCR9 has no ef-
including pad characters, but the FCS value for a pad- fect on the loopback operation.
ded frame will not be passed to the host. If an FCS GPSI Loopback Modes
error is detected in any frame, the error will be reported
When GPSI is the active network port, there are only
in the CRC bit in RMD1.
two modes of loopback operation: internal and external
Receive Exception Conditions loopback. The settings of MENDECL and TMAULOOP
Exception conditions for frame reception fall into two have no effect for this port.
distinct categories, i.e., those conditions which are the When INTL is set to 1, internal loopback is selected.
result of normal network operation, and those which Data coming out of the transmit FIFO is fed directly to
occur due to abnormal network and/or host related the receive FIFO. All GPSI outputs are inactive; inputs
events. are ignored.
Normal events which may occur and which are handled External loopback operation is selected by setting INTL
autonomously by the Am79C971 controller are basi- to 0. Data is transmitted to the network and is expected
cally collisions within the slot time and automatic runt to be looped back to the GPSI receive pins outside the
packet rejection. The Am79C971 controller will ensure chip. Collision detection is active in this mode.
that collisions that occur within 512 bit times from the
start of reception (excluding preamble) will be automat- AUI Loopback Modes
ically deleted from the receive FIFO with no host inter- When AUI is the active network port, there are three
vention. The receive FIFO will delete any frame that is modes of loopback operation: internal with and without
composed of fewer than 64 bytes provided that the MENDEC and external loopback. The setting of TMAU-
Runt Packet Accept (RPA bit in CSR124) feature has LOOP has no effect for this port.
not been enabled and the network interface is operat-
When INTL and MENDECL are set to 1, internal loop-
ing in half-duplex mode. This criterion will be met re-
back without MENDEC is selected. Data coming out of
gardless of whether the receive frame was the first (or
the transmit FIFO is fed directly to the receive FIFO.
only) frame in the FIFO or if the receive frame was
The AUI transmitter is disabled and signals on the re-
queued behind a previously received message.
ceive and collision inputs are ignored.
Abnormal network conditions include:
When INTL is set to 1 and MENDECL is cleared to 0,
■ FCS errors internal loopback including the MENDEC is selected.
■ Late collision Data is routed from the transmit FIFO through the
MENDEC back to the receive FIFO. No data is trans-
Host related receive exception conditions include mitted to the network. All signals on the receive and
MISS, BUFF, and OFLO. These are described in the collision inputs are ignored.
section, Buffer Management Unit.
External loopback operation is selected by setting INTL
Loopback Operation to 0. The programming of MENDECL has no effect in
Loopback is a mode of operation intended for system this mode. The AUI transmitter is enabled and data is
diagnostics. In this mode, the transmitter and receiver transmitted to the network. The Am79C971 controller
are both operating at the same time so that the control- expects data to be looped back to the receive inputs
ler receives its own transmissions. The controller pro- outside the chip. Collision detection is active in this
vides two basic types of loopback. In internal loopback mode.
68 Am79C971
T-MAU Loopback Modes ther, the MII loopback requires that the MII port be
When T-MAU is the active network port there are four manually configured through software using ASEL
modes of loopback operation: internal loopback with (BCR 2, bit 1) and PORTSEL (CSR 15, bits 8-7).
and without MENDEC and two external loopback The external loopback through the MII requires a two-
modes. step operation. The external PHY must be placed into
When INTL and MENDECL are set to 1, internal loop- a loopback mode by writing to the MII Control Register
back without MENDEC is selected. Data coming out of (BCR33, BCR34). Then the Am79C971 controller must
the transmit FIFO is fed directly to the receive FIFO. be placed into an external loopback mode. All other
The T-MAU does not transmit any data to the network, loopback modes have no meaning during MII opera-
but it continues to send link pulses. All signals on the tion.
receive inputs are ignored. LCAR (TMD2, bit 27) will al- The internal loopback through the MII is controlled by
ways read zero, regardless of the link state. The pro- MIIILP (BCR32, bit 1). When set to 1, this bit will cause
gramming of TMAULOOP has no effect. the internal portion of the MII data port to loopback on
When INTL is set to 1 and MENDECL is cleared to 0, itself. The MII management port (MDC, MDIO) is unaf-
internal loopback including the MENDEC is selected. fected by the MIILP bit. The internal MII interface is
Data is routed from the transmit FIFO through the mapped in the following way:
MENDEC back to the receive FIFO. The T-MAU does ■ The TXD[3:0] nibble data path is looped back onto
not transmit any data to the network, but it continues to the RXD[3:0] nibble data path;
send link pulses. All signals on the receive inputs are
■ TX_CLK is looped back as RX_CLK;
ignored. LCAR (TMD2, bit 27) will always read zero, re-
gardless of the link state. The programming of TMAU- ■ TX_EN is looped back as RX_DV.
LOOP has no effect. ■ CRS is correctly OR’d with TX_EN and RX_DV and
External loopback operation works slightly different always encompasses the transmit frame.
when the T-MAU is the active network port. In a ■ TX_ER is not driven by the Am79C971 and there-
10BASE-T network, the hub does not generate a re- fore not looped back.
ceive carrier back to the Am79C971 controller while the
During the internal loopback, the TXD, TX_CLK, and
chip is transmitting. The T-MAU provides this function
TX_EN pins will toggle appropriately with the correct
internally. A true external loopback covering all the
data.
components on the printed circuit board can only be
performed by using a special connector (with pin 1 jum- Miscellaneous Loopback Features
pered to pin 3 and pin 2 jumpered to pin 6) that con- All transmit and receive function programming, such as
nects the transmit pins of the RJ-45 jack to its receive automatic transmit padding and receive pad stripping,
pins. When INTL is cleared to 0 and TMAULOOP is set operates identically in loopback as in normal operation.
to 1, data is transmitted to the network and is expected
to be routed back to the chip. Collision detection is dis- Loopback mode can be performed with any frame size
abled in this mode. The link state machine is forced into except in the MII loopback mode. Runt Packet Accept
the link pass state. LCAR will always read zero. The is internally enabled (RPA bit in CSR124 is not af-
programming of MENDECL has no effect in this mode. fected) when any loopback mode is invoked. This is to
be backwards compatible to the C-LANCE (Am79C90)
The Am79C971 Am79C971 controller provides a spe- software.
cial external loopback mode that allows the device to
be connected to a live 10BASE-T network. The virtual Since the Am79C971 controller has two FCS genera-
external loopback mode is invoked by setting INTL and tors, there are no more restrictions on FCS generation
TMAULOOP to 0. In this mode, data coming out of the or checking, or on testing multicast address detection
transmit FIFO is fed directly into the receive FIFO. Ad- as they exist in the half-duplex PCnet family devices
ditionally, all transmit data is output to the network. The and in the C-LANCE. On receive, the Am79C971 con-
link state machine is active as is the collision detection troller now provides true FCS status. The descriptor for
logic. The programming of MENDECL has no effect in a frame with an FCS error will have the FCS bit (RMD1,
this mode. bit 27) set to 1. The FCS generator on the transmit side
can still be disabled by setting DXMTFCS (CSR15, bit
Media Independent Interface Loopback Features 3) to 1.
Loopback through the MII can be handled in two ways.
In internal loopback operation, the Am79C971 control-
The Am79C971 controller supports an internal MII
ler provides a special mode to test the collision logic.
loopback and an external MII loopback. The MII loop-
When FCOLL (CSR15, bit 4) is set to 1, a collision is
back is completely separate from other network port
forced during every transmission attempt. This will re-
loopback and requires that the other loopback modes
sult in a Retry error.
be disengaged while the MII loopback is running. Fur-
Am79C971 69
Manchester Encoder/Decoder Table 8. External Clock Source Characteristics
The integrated Manchester Encoder/Decoder (MEN- Clock Frequency: 20 MHz ±0.01%
DEC) provides the PLS (Physical Layer Signaling) <= 6 ns from 0.5 V to VDD
Rise/Fall Time (tR/tF):
functions required for a fully compliant ISO 8802-3 -0.5 V
(IEEE/ANSI 802.3) station. The MENDEC provides the XTAL1 HIGH/LOW Time
encoding function for data to be transmitted on the net- 20 ns min.
(tHIGH/tLOW):
work using the high accuracy on-board oscillator,
XTAL1 Falling Edge to < ±0.2 ns at 2.5 V input
driven by either the crystal oscillator or an external Falling Edge Jitter: (VDD/2)
CMOS-level compatible clock. The MENDEC also pro-
vides the decoding function from data received from MENDEC Transmit Path
the network. The MENDEC contains a Power On Reset The transmit section encodes separate clock and NRZ
(POR) circuit, which ensures that all analog portions of data input signals into a standard Manchester encoded
the Am79C971 controller are forced into their correct serial bit stream. The transmit outputs (DO±) are de-
state during power up, and prevents erroneous data signed to operate into terminated transmission lines.
transmission and/or reception during this time. When operating into a 78-Ω terminated transmission
External Crystal Characteristics line, the transmit signaling meets the required output
levels and skew for Cheapernet, Ethernet, and IEEE-
When using a crystal to drive the oscillator, the follow-
802.3.
ing crystal specification (Table 7) may be used to en-
sure less than ±0.5 ns jitter at DO±. Transmitter Timing and Operation
A 20-MHz fundamental mode crystal oscillator pro-
vides the basic timing reference for the MENDEC por-
Table 7. Crystal Characteristics
tion of the Am79C971 controller. The crystal frequency
Parameter Min Nom Max Units is divided by two to create the internal transmit clock
reference. Both the 10-MHz and 20-MHz clocks are fed
1. Parallel Resonant
20 MHz into the Manchester Encoder. The internal transmit
Frequency
clock is used by the MENDEC to synchronize the Inter-
2. Resonant nal Transmit Data (ITXDAT) and Internal Transmit En-
-50 +50 PPM
Frequency Error able (ITXEN) from the controller. The internal transmit
3. Change in clock is also used as a stable bit rate clock by the re-
Resonant Frequency ceive section of the MENDEC and controller.
With Respect To -40 +40 PPM
Temperature The oscillator requires an external 0.01% timing refer-
(0 - 70 C)* ence. If an external crystal is used, the accuracy re-
4. Crystal Load quirements are tighter because allowance for the on-
20 50 pF board parasitics must be made to deliver a final accu-
Capacitance
racy of 0.01%.
5. Motional Crystal
0.022 pF
Capacitance (C1) Transmission is enabled by the controller. As long as
6. Internal Equivalent the ITXEN request remains active, the serial output of
35 ohm the controller will be Manchester encoded and appear
Series Resistance
7. Shunt at DO±. When the internal request is dropped by the
7 pF controller, the differential transmit outputs go to one of
Capacitance
two idle states, dependent on TSEL in the Mode Reg-
Note: ister (CSR15, bit 9).
*Requires trimming specification; not trim is 50 PPM total.
Table 9. TSEL Effect

External Clock Drive Characteristics
The idle state of DO± yields 0 differential
When driving the oscillator from a CMOS-level external TSEL LOW:
to operate transformer-coupled loads.
clock source, XTAL2 must be left floating (uncon-
In this idle state, DO+ is positive with
nected). An external clock having the following charac- TSEL HIGH:
respect to DO- (logical HIGH).
teristics must be used to ensure less than ±0.5 ns jitter
at DO±. See Table 8.
70 Am79C971
Receiver Path phase locked to it. As a result, the MENDEC acquires
The principal functions of the receiver are to signal the the clock from the incoming Manchester bit pattern in 4
Am79C971 controller that there is information on the bit times with a 1010b Manchester bit pattern.
receive pair and to separate the incoming Manchester IRXCLK and IRXDAT are enabled 1/4 bit time after
encoded data stream into clock and NRZ data. clock acquisition in bit cell 5. IRXDAT is at a HIGH state
The receiver section consists of two parallel paths (see when the receiver is idle (no IRXCLK). IRXDAT, how-
Figure 35). The receive data path is a zero threshold, ever, is undefined when clock is acquired and may re-
wide bandwidth line receiver. The carrier path is an off- main HIGH or change to LOW state whenever IRXCLK
set threshold, bandpass detecting line receiver. Both is enabled. At 1/4 bit time into bit cell 5, the controller
receivers share common bias networks to allow opera- portion of the Am79C971 controller sees the first IRX-
tion over a wide input common mode range. CLK transition. This also strobes in the incoming fifth bit
to the MENDEC as Manchester 1. IRXDAT may make
Input Signal Conditioning a transition after the IRXCLK rising edge in bit cell 5,
Transient noise pulses at the input data stream are re- but its state is still undefined. The Manchester 1 at bit 5
jected by the Noise Rejection Filter. Pulse width rejec- is clocked to IRXDAT output at 1/4 bit time in bit cell 6.
tion is proportional to transmit data rate. PLL Tracking
The Carrier Detection circuitry detects the presence of After clock acquisition, the phase-locked clock is com-
an incoming data frame, by discerning and rejecting pared to the incoming transition at the bit cell center
noise from expected Manchester data, and controls the (BCC) and the resulting phase error is applied to a cor-
stop and start of the phase-lock loop during clock ac- rection circuit. This circuit ensures that the phase-
quisition. Clock acquisition requires a valid Manchester locked clock remains locked on the received signal. In-
bit pattern of 1010b to lock onto the incoming message. dividual bit cell phase corrections of the Voltage Con-
When input amplitude and pulse width conditions are trolled Oscillator (VCO) are limited to 10% of the phase
met at DI±, the internal enable signal from the MEN- difference between BCC and phase-locked clock.
DEC to controller (IRXEN) is asserted and a clock ac- Hence, input data jitter is reduced in IRXCLK by 10
quisition cycle is initiated. to 1.
Clock Acquisition Carrier Tracking and End of Message
When there is no activity at DI± (receiver is idle), the re- The carrier detection circuit monitors the DI± inputs
ceive oscillator is phase locked to the internal transmit after IRXEN is asserted for an end of message. IRXEN
clock. The first negative clock transition (bit cell center deasserts 1 to 2 bit times after the last positive transi-
of first valid Manchester 0) after IRXEN is asserted in- tion on the incoming message. This initiates the end of
terrupts the receive oscillator. The oscillator is then re- reception cycle.
started at the second Manchester 0 (bit time 4) and is
IRXDAT*
Data Manchester
DI±
Receiver Decoder
IRXCLK*
Noise Carrier
Reject Detect IRXEN*
Filter Circuit
*Internal signal 20550D-38
Figure 35. Receiver Block Diagram
Am79C971 71
The time delay from the last rising edge of the message the common-mode input impedance, ZICM, are speci-
to IRXEN deassert allows the last bit to be strobed by fied so that the Ethernet specification for cable termina-
IRXCLK and transferred to the controller section, but tion impedance is met using standard 1% resistor
prevents any extra bit(s) at the end of message. terminators. If SIP devices are used, 39 ohms is also a
suitable value. The CI± differential inputs are termi-
Data Decoding
nated in exactly the same way as the DI± pair.
The data receiver is a comparator with clocked output
to minimize noise sensitivity to the DI± inputs. Input
error is less than ±35 mV to minimize sensitivity to input AUI Isolation
rise and fall time. IRXCLK strobes the data receiver Transformer
DI+
output at 1/4 bit time to determine the value of the
Am79C971
Manchester bit, and clocks the data out on IRXDAT on
the following IRXCLK. The data receiver also gener- DI-
ates the signal used for phase detector comparison to

the internal MENDEC VCO. 40.2 Ω 40.2 Ω
Jitter Tolerance Definition

0.01 µF
The MENDEC utilizes a clock capture circuit to align its to
0.1 µF
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with
the values 1010b. The clock is phase-locked to the neg- 20550D-39
ative transition at the bit cell center of the second zero
in the pattern. Figure 36. AUI Differential Input Termination
Since data is strobed at 1/4 bit time, Manchester tran-

sitions which shift from their nominal placement Collision Detection
through 1/4 bit time will result in improperly decoded
A MAU detects the collision condition on the network
data. With this as the criterion for an error, a definition
and generates a 10-MHz differential signal at the CI±
of Jitter Handling is:
inputs. This collision signal passes through an input
The peak deviation approaching or crossing 1/4 bit stage which detects signal levels and pulse duration.
cell position from nominal input transition, for which When the signal is detected by the MENDEC, it sets the
the MENDEC section will properly decode data. ICLSN line HIGH. The condition continues for approxi-
mately 1.5 bit times after the last LOW-to-HIGH transi-
Attachment Unit Interface tion on CI±.
The Attachment Unit Interface (AUI) is the PLS (Physi-
cal Layer Signaling) to PMA (Physical Medium Attach-
Twisted-Pair Transceiver
ment) interface which effectively connects the DTE to a This section describes operation of the Twisted-Pair
MAU. The differential interface provided by the Transceiver (T-MAU) when operating in half-duplex
Am79C971 controller is fully compliant to Section 7 of mode. When in half-duplex mode, the T-MAU imple-
ISO 8802-3 (ANSI/IEEE 802.3) standard. ments the MAU functions for the Twisted Pair Medium
as specified by the supplement to the IEEE 802.3 stan-
After the Am79C971 controller initiates a transmission
dard (Type 10BASE-T). When operating in full-duplex
it will expect to see data “looped-back” on the DI± pair
mode, the MAC engine behavior changes as described
(when the AUI port is selected). This will internally gen-
in the section Full-Duplex Operation.
erate a “carrier sense,” indicating that the integrity of
the data path to and from the MAU is intact, and that the The T-MAU provides twisted pair driver and receiver cir-
MAU is operating correctly. This “carrier sense” signal cuits, including on-board transmit digital predistortion
must be asserted before end of transmission. If “carrier and receiver squelch, and a number of additional fea-
sense” does not become active in response to the data tures including Link Status indication, Automatic
transmission, or becomes inactive before the end of Twisted Pair Receive Polarity Detection/Correction and
transmission, the loss of carrier (LCAR) error bit will be Indication, Receive Carrier Sense, Transmit Active, and
set in the transmit descriptor ring (TMD2, bit 27) after Collision Present indication.
the frame has been transmitted.
Twisted Pair Transmit Function
Differential Input Termination The differential driver circuitry in the TXD± and TXP±
The differential input for the Manchester data (DI±) is pins provides the necessary electrical driving capability
externally terminated by two 40.2-Ω resistors and one and the pre-distortion control for transmitting signals
optional common-mode bypass capacitor, as shown in over maximum length Twisted Pair cable, as specified
Figure 36. The differential input impedance, ZIDF, and by the 10BASE-T supplement to the ISO 8802-3 (IEEE/
72 Am79C971
ANSI 802.3) Standard. The transmit function for data collision detection functions are disabled and remain
output meets the propagation delays and jitter speci- disabled until valid data or more than five consecutive
fied by the standard. link pulses appear on the RXD± pair. During Link Fail,
the Link Status signal is inactive. When the link is iden-
Twisted Pair Receive Function
tified as functional, the Link Status signal is asserted.
The receiver complies with the receiver specifications The LED0 pin displays the Link Status signal by default.
of the ISO 8802-3 (IEEE/ANSI 802.3) 10BASE-T Stan-
dard, including noise immunity and received signal re- The T-MAU will power up in the Link Fail state and the
jection criteria (Smart Squelch). Signals meeting these normal algorithm will apply to allow it to enter the Link
criteria appearing at the RXD± differential input pair are Pass state. If T-MAU is selected using the PORTSEL
routed to the MENDEC. The receiver function meets bits in CSR15, the T-MAU will be forced into the Link
the propagation delays and jitter requirements speci- Fail state when moving from AUI to T-MAU selection.
fied by the standard. The receiver squelch level drops Transmission attempts during Link Fail state will pro-
to half its threshold value after unsquelch to allow reduce no network activity and will produce LCAR and
ception of minimum amplitude signals and to offset car- CERR error indications.
rier fade in the event of worst case signal attenuation
and crosstalk noise conditions. In order to interoperate with systems which do not im-
plement Link Test, this function can be disabled by set-
Note that the 10BASE-T Standard defines the receive ting the DLNKTST bit in CSR15. With link test disabled,
input amplitude at the external Media Dependent Inter- the data driver, receiver and loopback functions, as well
face (MDI). Filter and transformer loss are not speci- as collision detection, remain enabled irrespective of
fied. The T-MAU receiver squelch levels are defined to the presence or absence of data or link pulses on the
account for a 1-dB insertion loss at 10 MHz, which is RXD± pair. Link Test pulses continue to be sent regard-
typical for the type of receive filters/transformers em- less of the state of the DLNKTST bit.
ployed.
Polarity Detection and Reversal
Normal 10BASE-T compatible receive thresholds are
The T-MAU receive function includes the ability to invert
employed when the LRT bit (CSR15, bit 9) is cleared to
the polarity of the signals appearing at the RXD± pair if
0. When the LRT bit is set to 1, the Low Receive
the polarity of the received signal is reversed (such as
Threshold option is invoked, and the sensitivity of the T-
in the case of a wiring error). This feature allows data
MAU receiver is increased. This allows longer line
frames received from a reverse wired RXD± input pair
lengths to be employed, exceeding the 100-meter (m)
to be corrected in the T-MAU prior to transfer to the
target distance of normal 10BASE-T (assuming typical
MENDEC. The polarity detection function is activated
24 AWG cable). The increased receiver sensitivity
following H_RESET or Link Fail, and it will reverse the
compensates for the increased signal attenuation
receive polarity based on both the polarity of any previ-
caused by the additional cable distance.
ous link beat pulses and the polarity of subsequent
However, making the receiver more sensitive means frames with a valid End Transmit Delimiter (ETD).
that it is also more susceptible to extraneous noise, pri-
When in the Link Fail state, the T-MAU will recognize
marily caused by coupling from co-resident services
link beat pulses of either positive or negative polarity.
(crosstalk). For this reason, it is recommended that
Exit from the Link Fail state is made due to the recep-
when using the Low Receive Threshold option that the
tion of 5 to 6 consecutive link beat pulses of identical
service should be installed on 4-pair cable only. Multi-
polarity. On entry to the Link Pass state, the polarity of
pair cables within the same outer sheath have lower
the last five link beat pulses is used to determine the
crosstalk attenuation and may allow noise emitted from
initial receive polarity configuration, and the receiver is
adjacent pairs to couple into the receive pair, being of
reconfigured to subsequently recognize only link beat
sufficient amplitude to falsely unsquelch the T-MAU.
pulses of the previously recognized polarity.
Link Test Function
Positive link beat pulses are defined as received signal
The Link Test Function is implemented as specified by with a positive amplitude greater than 585 mV (LRT =
the 10BASE-T standard. During periods of transmit 1) with a pulse width of 60 ns to 200 ns. This positive
pair inactivity, link beat pulses will be periodically sent excursion may be followed by a negative excursion.
over the twisted pair medium to constantly monitor me- This definition is consistent with the expected received
dium integrity. signal at a correctly wired receiver, when a link beat
When the link test function is enabled (DLNKTST bit in pulse, which fits the template of Figure 14-12 of the
CSR15 is cleared), the absence of link beat pulses and 10BASE-T Standard, is generated at a transmitter and
receive data on the RXD± pair will cause the T-MAU to passed through 100 m of twisted pair cable.
go into a Link Fail state. In the Link Fail state, data Negative link beat pulses are defined as received sig-
transmission, data reception, data loopback and the nals with a negative amplitude greater than 585 mV
Am79C971 73
with a pulse width of 60 to 200 ns. This negative excur- Signal Quality Error Test Function
sion may be followed by a positive excursion. This def- The Signal Quality Error (SQE) test function (also
inition is consistent with the expected received signal at called Heartbeat) is disabled when the 10BASE-T port
a reverse wired receiver, when a link beat pulse, which is selected.
fits the template of Figure 14-12 in the 10BASE-T Stan-
dard, is generated at a transmitter and passed through Jabber Function
100 m of twisted pair cable. The Jabber function prevents the twisted pair transmit
The polarity detection/correction algorithm will remain function of the T-MAU TXD± from being active for an ex-
armed until two consecutive frames with valid ETD of cessive period of time (20 ms to 150 ms). This prevents
identical polarity are detected. When armed, the re- any one node from disrupting the network due to a
ceiver is capable of changing the initial or previous po- stuck-on or faulty transmitter. If this maximum transmit
larity configuration based on the ETD polarity. time is exceeded, the T-MAU transmitter circuitry is dis-
abled, the JAB bit is set (CSR4, bit 1) and the COL sig-
On receipt of the first frame with valid ETD following nal is asserted. Once the transmit data stream is
H_RESET or Link Fail, the T-MAU will utilize the in- removed, the T-MAU waits an unjab time of 250 ms to
ferred polarity information to configure its RXD± input, 750 ms before it deasserts COL and re-enables the
regardless of its previous state. On receipt of a second transmit circuitry.
frame with a valid ETD with correct polarity, the detec-
tion/ correction algorithm will lock-in the received po- Power Down
larity. If the second (or subsequent) frame is not The T-MAU circuitry can be made to go into a power
detected as confirming the previous polarity decision, savings mode. The T-MAU will go into the power down
the most recently detected ETD polarity will be used as mode when H_RESET is active, when coma mode is
the default. Note that frames with invalid ETD have no active, or when the T-MAU is not selected. Refer to the
effect on updating the previous polarity decision. Once Power Savings Modes section for descriptions of the
two consecutive frames with valid ETD have been re- various power down modes.
ceived, the T-MAU will disable the detection/correction
Any of the three conditions listed above resets the in-
algorithm until either a Link Fail condition occurs or
ternal logic of the T-MAU and places the device into
H_RESET is activated.
power down mode. In this mode, the Twisted Pair driver
During polarity reversal, an internal POL signal will be pins (TXD±, TXP±) are driven LOW, and the internal
active. During normal polarity conditions, this internal T-MAU status signals (LED0, RCVPOL, XMT, RCV and
POL signal is inactive. The state of this signal can be COL) signals are inactive.
read by software and/or displayed by LED when en-
After coming out of the power down mode, the T-MAU
abled by the LED control bits in the Bus Configuration
will remain in the reset state for an additional 10 µs. Im-
Registers (BCR4 to BCR7).
mediately after the reset condition is removed, the T-
Twisted Pair Interface Status MAU will be forced into the Link Fail state. The T-MAU
When the T-MAU is in Link Pass state, three signals will move to the Link Pass state only after 5 to 6 link
(XMT, RCV and COL) indicate whether the T-MAU is beat pulses and/or a single received message is de-
transmitting, receiving, or in a collision state with both tected on the RD± pair.
functions active simultaneously. These signals are in- In snooze mode, the T-MAU receive circuitry will remain
ternal signals that can be programmed to appear on enabled even while the SLEEP pin is driven LOW.
any of the LED output pins. Programming is done by
writing to BCR4 to BCR7. 10BASE-T Interface Connection
Figure 37 shows the proper 10BASE-T network inter-
In the Link Fail state, XMT, RCV, and COL are inactive.
face design. Refer to the PCnet Family Board Design
Collision Detection Function and Layout Recommendations Application Note (PID
#19595A) for more design details. Also, refer to Appen-
Activity on both twisted pair signals (RXD± and TXD±)
dix A, Am79C971 Compatible Media Interface Modules
at the same time constitutes a collision, thereby, caus-
for a list of compatible 10BASE-T filter/transformer
ing the internal COL signal to be activated. COL will re-
modules.
main active until one of the two colliding signals
changes from active to idle. However, transmission at- Note: The recommended resistor values and filter and
tempt in Link Fail state results in LCAR and CERR in- transformer modules are the same as those used by
dication. COL stays active for 2 bit times at the end of the IMR+ (Am79C981).
a collision.
74 Am79C971
General Purpose Serial Interface GPSI signal functions are described in the pin descrip-
tion section under the GPSI subheading.
The General Purpose Serial Interface (GPSI) provides
a direct interface to the MAC section of the Am79C971 Note that the XTAL1 input must always be driven with a
controller. All signals are digital and data is non-en- clock source, even if GPSI mode is to be used. It is not
coded. The GPSI allows use of an external Manchester necessary for the XTAL1 clock to meet the normal fre-
encoder/decoder such as the Am7992B Serial Inter- quency and stability requirements in this case. Any fre-
face Adapter (SIA). In addition, it allows the Am79C971 quency between 8 MHz and 20 MHz is acceptable.
controller to be used as a MAC sublayer engine in re- However, voltage drive requirements do not change.
peater designs based on the IMR+ device When GPSI mode is used, XTAL1 must be driven for
(Am79C981). several reasons:
GPSI mode is invoked by selecting the interface The default H_RESET configuration for the Am79C971
through the PORTSEL bits of the Mode register controller is AUI port selected. Until GPSI mode is se-
(CSR15, bits 8-7). lected, the XTAL1 clock is needed for some internal op-
erations (namely, RESET). The XTAL1 clock drives the
The GPSI interface uses some of the same pins as the
EEPROM read operation, regardless of the network
interface to the MII. Simultaneous use of both functions
mode selected.
is not possible.
The XTAL1 clock determines the length of the internal
After an H_RESET, all MII pins are internally config-
S_RESET caused by the read of the Reset register, re-
ured to function as the MII interface. When the GPSI in-
gardless of the network mode.
terface is selected by setting PORTSEL (CSR15, bits
8-7) to 10b, the Am79C971 controller will terminate all Note: If a clock slower than 20 MHz is provided at the
further accesses to the MII. XTAL1 input, the time needed for EEPROM read and
the internal S_RESET will increase.
Filter &
Transformer
61.9 Ω Module RJ45
TXD+ 1.21 KΩ Connector
422 Ω 1:1
TXP+ TD+ 1
61.9 Ω XMT
TXD- Filter TD- 2
Am79C971
422 Ω
TXP-
1:1
RXD+ RD+ 3
RCV
RXD- Filter RD- 6
100 Ω
20550D-40
Figure 37. 10BASE-T Interface Connection
Full-Duplex Operation or when Auto-Negotiation is running on the internal

PHY.
The Am79C971 controller supports full-duplex opera-
tion on all four network interfaces: AUI, GPSI, 10BASE- When operating in full-duplex mode, the following
T, and MII. Full-duplex operation allows simultaneous changes to the device operation are made:
transmit and receive activity on the TXD± and RXD±
Bus Interface/Buffer Management Unit changes:
pairs of the 10BASE-T port, the DO± and DI± pairs of
the AUI port, TXDAT and RXDAT pins of the GPSI port, ■ The first 64 bytes of every transmit frame are not
and the TXD[3:0] and RXD[3:0] pins of the MII port. preserved in the Transmit FIFO during transmission
Full-duplex operation is enabled by the FDEN and of the first 512 bits as described in the Transmit Ex-
AUIFD bits located in BCR9 for all ports. Full-duplex ception Conditions section. Instead, when full-du-
operation is enabled through Auto-Negotiation when p l ex m o d e i s a c t i ve a n d a f r a m e i s b e i n g
DANAS (BCR 32, bit 7) is not enabled on the MII port
Am79C971 75
transmitted, the XMTFW bits (CSR80, bits 9-8) al- LEDOUT bit when the T-MAU is in the Full-Duplex
ways govern when transmit DMA is requested. Link Pass state only.
■ Successful reception of the first 64 bytes of every Media Independent Interface
receive frame is not a requirement for Receive DMA
to begin as described in the Receive Exception The Am79C971 controller fully supports the MII ac-
Conditions section. Instead, receive DMA will be re- cording to the IEEE 802.3 standard. This Reconcilia-
quested as soon as either the RCVFW threshold tion Sublayer interface allows a variety of PHYs
(CSR80, bits 12-13) is reached or a complete valid (100BASE-TX, 100BASE-FX, 100BASE-T4,
receive frame is detected, regardless of length. This 100BASE-T2, 10BASE-T, etc.) to be attached to the
Receive FIFO operation is identical to when the Am79C971 MAC engine without future upgrade prob-
RPA bit (CSR124, bit 3) is set during half-duplex lems. The MII interface is a 4-bit (nibble) wide data path
mode operation. interface that runs at 25 MHz for 100-Mbps networks
and 2.5 MHz for 10-Mbps networks. The interface con-
The MAC engine changes for full-duplex operation are s is ts of t wo i nd ep end ent dat a pa ths, r ec ei ve
as follows: (RXD(3:0)) and transmit (TXD(3:0)), control signals for
■ Changes to the Transmit Deferral mechanism: each data path (RX_ER, RX_DV, TX_ER, TX_EN), net-
work status signals (COL, CRS), clocks (RX_CLK,
— Transmission is not deferred while receive is TX_CLK) for each data path, and a two-wire manage-
active. ment interface (MDC and MDIO). See Figure 38.
— The IPG counter which governs transmit deferral
MII Transmit Interface
during the IPG between back-to-back transmits
is started when transmit activity for the first The MII transmit clock is generated by the external
packet ends, instead of when transmit and car- PHY and is sent to the Am79C971 controller on the
rier activity ends. TX_CLK input pin. The clock can run at 25 MHz or 2.5
MHz, depending on the speed of the network that the
■ When the AUI or MII port is active, Loss of Carrier external PHY is attached to. The data is a nibble-wide
(LCAR) reporting is disabled (LCAR is still reported (4 bits) data path, TXD(3:0), from the Am79C971 con-
when the 10BASE-T port is active if a packet is troller to the external PHY and is synchronous to the
transmitted while in Link Fail state). rising edge of TX_CLK. The transmit process starts
■ The 4.0 µs carrier sense blinding period after a when the Am79C971 controller asserts the TX_EN,
transmission during which the SQE test normally which indicates to the external PHY that the data on
occurs is disabled. TXD(3:0) is valid.
■ When the AUI port is active, the SQE Test error re- Normally, unrecoverable errors are signaled through
porting (CERR) is disabled (CERR is still reported the MII to the external PHY with the TX_ER output pin.
when the 10BASE-T port is active if a packet is The external PHY will respond to this error by generat-
transmitted while in Link Fail state). ing a TX coding error on the current transmitted frame.
■ The collision indication input to the MAC engine is The Am79C971 controller does not use this method of
ignored. signaling errors on the transmit side. The Am79C971
controller will invert the FCS on the last byte generating
The T-MAU changes for full-duplex operation are as fol- an invalid FCS. The TX_ER pin is reserved for future
lows: use and is actively driven to 0.
■ The transmit to receive loopback path in the T-MAU MII Receive Interface
is disabled.
The MII receive clock is also generated by the external
■ The collision detect circuit is disabled. PHY and is sent to the Am79C971 controller on the
■ The SQE test function is disabled. RX_CLK input pin. The clock will be the same fre-
quency as the TX_CLK but will be out of phase and can
The MII changes for full-duplex operation are as fol-
run at 25 MHz or 2.5 MHz, depending on the speed of
lows:
the network the external PHY is attached to. The
■ The collision detect (COL) pin is disabled. RX_CLK is a continuous clock during the reception of
■ The SQE test function is disabled. the frame, but can be stopped for up to two RX_CLK
periods at the beginning and the end of frames, so that
Full-Duplex Link Status LED Support the external PHY can sync up to the network data traffic
The Am79C971 controller provides bits in each of the necessary to recover the receive clock. During this
LED Status registers (BCR4, BCR5, BCR6, BCR7) to time, the external PHY may switch to the TX_CLK to
display the Full-Duplex Link Status. If the FDLSE bit maintain a stable clock on the receive interface. The
(bit 8) is set, a value of 1 will be sent to the associated Am79C971 controller will handle this situation with no
loss of data. The data is a nibble-wide (4 bits) data
76 Am79C971
path, RXD(3:0), from the exter nal PHY to the The Am79C971 controller can support up to 31 exter-
Am79C971 controller and is synchronous to the rising nal PHYs attached to the MII Management Interface
edge of RX_CLK. with software support and only one such device without
software support.
The receive process starts when RX_DV is asserted.
RX_DV will remain asserted until the end of the receive The Network Port Manager copies the PHYAD after the
frame. The Am79C971 controller requires CRS (Car- Am79C971 controller reads the EEPROM and uses it
rier Sense) to toggle in between frames in order to re- to communicate with the external PHY. The PHY ad-
ceive them properly. Errors in the currently received dress must be programmed into the EEPROM prior to
frame are signaled across the MII by the RX_ER pin. starting the Am79C971 controller. This is necessary so
RX_ER can be used to signal special conditions out of that the internal management controller can work au-
band when RX_DV is not asserted. Two defined out-of- tonomously from the software driver and can always
band conditions for this are the 100BASE-TX signaling know where to ac cess the exter nal PHY. The
of bad Start of Frame Delimiter and the 100BASE-T4 Am79C971 controller is unique by offering direct hard-
indication of illegal code group before the receiver has ware support of the external PHY device without soft-
synched to the incoming data. The Am79C971 control- ware support. The internal PHY is addressed at the last
ler will not respond to these conditions. All out of band available MII address of 1Fh. To access the 31 external
conditions are currently treated as NULL events. Cer- PHYs, the software driver must have knowledge of the
tain in band non-IEEE 802.3u-compliant flow control external PHY’s address when multiple PHYs are
sequences may cause erratic behavior for the present before attempting to address it.
Am79C971 controller. Consult the switch/bridge/router/
The MII Management Interface uses the MII Control,
hub manual to disable the in-band flow control se-
Address, and Data registers (BCR32, 33, 34) to control
quences if they are being used.
and communicate to the exter nal and inter nal
MII Network Status Interface 10BASE-T only PHYs. Am79C971 generates MII man-
The MII also provides signals that are consistent and agement frames to the external PHY through the MDIO
necessary for IEEE 802.3 and IEEE 802.3u operation. pin synchronous to the rising edge of the Management
These signals are CRS (Carrier Sense) and COL (Col- Data Clock (MDC) based on a combination of writes
lision Sense). Carrier Sense is used to detect non-idle and reads to these registers. To prevent problems on
activity on the network. Collision Sense is used to indi- the exposed interface, MII management frames will not
cate that simultaneous transmission has occurred in a be generated when the internal PHY is the target. The
half-duplex network. MII only supports internal and external 10BASE-T or
100BASE-T as possible network connections. The in-
MII Management Interface ternal AUI and GPSI are not considered part of the MII
The MII provides a two-wire management interface so and cannot be selected through the MII.
that the Am79C971 controller can control and receive
status from external PHY devices.
4 RXD(3:0)
RX_DV
Receive Signals
RX_ER
RX_CLK
CRS
MII Interface
Network Status Signals

COL
4
Am79C971 TXD(3:0)
TX_EN
TX_ER Transmit Signals
TX_CLK
MDC
Management Port Signals
MDIO
20550D-41
Figure 38. Media Independent Interface
Am79C971 77
The MII Management Interface has a built-in detection The start of the frame is a preamble of 32 ones and
system to allow the Am79C971 controller to determine guarantees that all of the external PHYs are synchro-
if an external PHY is attached. The MDIO I/O pin has a nized on the same interface. (See Figure 39.) Loss of
resistor network between the Am79C971 controller and synchronization is possible due to the hot-plugging ca-
the external PHY that will assert a static 1 when pability of the exposed MII.
connected. If there is no external PHY connected, the
The IEEE 802.3 specification allows you to drop the
resistor network will drive a static zero. This information
preamble, if after reading the MII Status Register from
is signaled by the interrupt MPDTINT (CSR7, MIIPDTI,
the external PHY you can determine that the external
bit 1), and the status is provided by reading the Media
PHY will support Preamble Suppression (BCR34, bit
Independent Interface PHY Detected (MIIPD) (BCR32,
6). After having a valid MII Status Register read, the
bit 14). This resistor network is only required on an
Am79C971 controller will then drop the creation of the
exposed MII connector.
preamble stream until a reset occurs, receives a read
MII Management Frames error, or the external PHY is disconnected.
MII management frames are automatically generated
by the Am79C971 controller and conform to the MII
clause in the IEEE 802.3u standard.
TA
Preamb le ST OP PHY Register Z0 Rd Data
1111....1111 01 10 Rd Address Address Idle
10 Wr
01 Wr Z
32 2 2 5 5 2 16 1
Bits Bits Bits Bits Bits Bits Bits Bit
miiframe
20550D-42
Figure 39. Frame Format at the MII Interface Connection
This is followed by a start field (ST) and an operation will drive the MDC to 0 and tri-state the MDIO anytime
field (OP). The operation field (OP) indicates whether the MII Management Port is not active.
the Am79C971 controller is initiating a read or write op-
To help to speed up the reading and writing of the MII
eration. This is followed by the external PHY address
management frames to the external PHY, the MDC can
(PHYAD) and the register address (REGAD) pro-
be sped up to 10 MHz by setting the FMDC bits in
grammed in BCR33. The internal PHYAD is at location
BCR32. The IEEE 802.3 specification requires use of
1Fh and the internal register address space REGAD is
the 2.5-MHz clock rate, but 5 MHz and 10 MHz are
00h - 08h. The external PHY may have a larger ad-
available for the user. The intended applications are
dress space starting at 10h - 1Fh. This is the address
that the 10-MHz clock rate can be used for a single ex-
range set aside by the IEEE as vendor usable address
ternal PHY on an adapter card or motherboard. The 5-
space and will vary from vendor to vendor. This field is
MHz clock rate can be used for an exposed MII with
followed by a bus turnaround field. During a read oper-
one external PHY attached. The 2.5-MHz clock rate is
ation, the bus turnaround field is used to determine if
intended to be used when multiple external PHYs are
the external PHY is responding correctly to the read re-
connected to the MII Management Port or if compli-
quest or not. The Am79C971 controller will tri-state the
ance to the IEEE 802.3u standard is required.
MDIO for both MDC cycles. During the second cycle, if
the external PHY is synchronized to the Am79C971 Auto-Poll External PHY Status Polling
controller, the external PHY will drive a 0. If the external As defined in the IEEE 802.3 standard, the external
PHY does not drive a 0, the Am79C971 controller will PHY attached to the Am79C971 controller’s MII has no
signal a MREINT (CSR7, bit 9) interrupt, if MREINTE way of communicating important timely status informa-
(CSR7, bit 8) is set to a 1, indicating the Am79C971 tion back to Am79C971 controller. The Am79C971
controller had an MII management frame read error controller has no way of knowing that an external PHY
and that the data in BCR34 is not valid. The data field has undergone a change in status without polling the
to/from the internal or external PHY is read or written MII status register. To prevent problems from occurring
into the BCR34 register. The last field is an IDLE field with i nadequate ho st or softwar e po lling, the
that is necessary to give ample time for drivers to turn Am79C971 controller will Auto-Poll when APEP
off before the next access. The Am79C971 controller (BCR32, bit 11) is set to 1 to insure that the most cur-
rent information is available. See Appendix E, Auto Ne-
78 Am79C971
gotiation Registers, for the bit descriptions of the MII ities of the internal PHY. The internal PHY is capable of
Status Register. The contents of the latest read from half- or full-duplex 10BASE-T. Through the external
the external PHY will be stored in a shadow register in PHY, the following capabilities are possible: 100BASE-
the Auto-Poll block. The first read of the MII Status Reg- T4, 100BASE-TX Full-/Half-Duplex, and 10BASE-T
ister will just be stored, but subsequent reads will be Full-/Half-Duplex. The capabilities are then sent to a
compared to the contents already stored in the shadow link partner that will also send its capabilities. Both
register. If there has been a change in the contents of sides look to see what is possible and then they will
the MII Status Register, a MAPINT (CSR7, bit 7) in- connect at the greatest possible speed and capability
terrupt will be generated on INTA if the MAPINTE according to the following table as defined in the IEEE
(CSR7, bit 6) is set to 1. The Auto-Poll features can be 802.3u standard.
disabled if software driver polling is required.
The Auto-Poll’s frequency of generating MII manage- Table 10. Auto-Negotiation Capabilities
ment frames can be adjusted by setting of the APDW
bits (BCR32, bits 10-8). The delay can be adjusted Network Speed Physical Network Type
from 0 MDC periods to 2048 MDC periods. Auto-Poll by
default will only read the MII Status register in the ex- 200 Mbps 100BASE-X, Full Duplex
ternal PHY.
100 Mbps 100BASE-T4, Half Duplex
Network Port Manager
100 Mbps 100BASE-X, Half Duplex
The Am79C971 controller is unique in that it does not
require software intervention to control and configure 20 Mbps 10BASE-T, Full Duplex
an external PHY attached to the MII. This was done to
ensure backwards compatibility with existing software 10 Mbps 10BASE-T, Half Duplex
drivers. To the current software drivers, the Am79C971
controller will look and act like the PCnet-PCI II and will By default, the link partner must be at least 10BASE-T
interoperate with existing PCnet drivers from revision half-duplex capable. The Am79C971 controller can au-
2.5 upward. The heart of this system is the Network tomatically negotiate either internally or externally with
Port Manager, which acts as an arbiter between all of the network and yield the highest performance possible
the possible automatically controllable physical con- without software support. See the section on Network
nections, including the external PHY and the internal Port Manager for more details.
10BASE-T/AUI ports. See the section on Automatic Auto-Negotiation goes further by providing a message-
Network Port Selection for more details. based communication scheme called, Next Pages, be-
If the external PHY is present and is active, the Net- fore connecting to the Link Partner. This feature is not
work Port Manager will request status from the external supported in Am79C971 unless the DANAS (BCR32,
PHY by generating MII management frames. These bit 10) is selected and the software driver is capable of
frames will be sent roughly every 900 ms. These controlling the internal or external PHY.
frames are necessary so that the Network Port Man- A complete bit description of the MII and Auto-Negoti-
ager can monitor the current active link and can select ation registers can be found in Appendix E.
a different network port if the current link goes down.
Automatic Network Port Selection
Auto-Negotiation
The Am79C971 controller extends the PCnet-PCI II de-
The Am79C971 controller implements the Auto-Nego- vice’s automatic network port selection by adding the
tiation portion of the IEEE 802.3u specification for the MII port to the already existing 10BASE-T, and AUI
10BASE-T MAU. Auto-Negotiation attempts to auto- ports. If ASEL (BCR2, bit 0) is set to 1 and DANAS
matically configure the link between two link partners. (BCR 32, bit 7) is set to 0, then the Network Port Man-
To accomplish this, the 10BASE-T MAU can send a ager will start to configure the external PHY if it detects
new link pulse train called Fast Link Pulses. These Fast the external PHY on the MII Interface. If the external
Link Pulses replace the current 10BASE-T Link Pulse. PHY is not responding, the Network Port Manager will
The Fast Link Pulse are made up of a train of 17 clocks try to resolve problems and to fail non-responding links
alternating with 16 data fields for a total of 33 pulses. in a graceful manner, utilizing a large timer on the
The two link partners will send information in those 16 Am79C971 controller to time-out links.
data positions between themselves. The primary infor- Automatic Network Selection: Exceptions
mation sent is called the Base Code Link Word. See
Appendix E, Auto Negotiation Registers, for details on If ASEL (BCR2, bit 0) is set to 0 or DANAS (BCR 32, bit
the Auto-Negotiation Registers. The Am79C971 con- 7) is set to 1, then the Network Port Manager will dis-
troller will send in its Base Code Link Word the capabil- continue actively trying to establish the connections. It
is assumed that the software driver is attempting to
Am79C971 79
configure the network port and the Am79C971 control- ■ External PHY Not Present
ler will always defer to the software driver. When The ■ External PHY Present but Not Auto-Negotiable
ASEL is set to 0, the software driver should then con-
figure the ports with PORTSEL (CSR15, bits 7-8). The ■ External PHY Present and Auto-Negotiable
GPSI does not participate in the automatic selection Automatic Network Selection: External PHY Not
process and should be manually configured with the Present
PORTSEL bits. If FDEN (BCR9, bit 0) is set to 1 or
The first case occurs when the MIIPD (BCR32, bit 14)
DLNKST (CSR15, bit 12) is set to 1, the Network Port
bit is 0. This indicates that there is no external PHY at-
Manager will continue to select the active network port,
tached to Am79C971 controller’s MII. The Am79C971
but the internal T-MAU will not auto-negotiate the net-
controller’s Network Port Manager will start the internal
work port. Instead, if FDEN (BCR9, bit 0) is set to 1, the
Auto-Negotiation 10BASE-T MAU. If the Auto-Negotia-
internal T-MAU will come up as a full-duplex T-MAU port
tion 10BASE-T MAU fails to respond within a specific
if link beats are found. If DLNKST (CSR15, bit 12) is set
time frame, then the Am79C971 controller will enable
to 1 and the internal T-MAU is active, the T-MAU will be
the AUI. Auto-Negotiation FAST Link Pulses are still
in a link pass state regardless of link beat.
being sent and the Auto-Negotiation 10BASE-T MAU is
Note: It is highly recommended that ASEL and still running. At that point, the active link can switch
PORTSEL be used when trying to manually configure back to the 10BASE-T MAU when Link Pulses or FAST
a specific network port. Link Pulses are detected. The only way to disable the
In order to manually configure the External PHY, the Auto-Negotiation process without using FDEN or
recommended procedure is to force the PHY configu- DLNKST is to enable the DANAS (BCR32, bit 7) bit or
rations when Auto-Negotiation is not enabled. Set the to write to the internal/external PHYs MII control regis-
DANAS bit (BCR32, bit 7) to turn off the Network Port ter and disable Auto-Negotiation when the internal Net-
Manager. Then write again to BCR32 with the DANAS work Port Manager is disabled.
and XPHYANE (BCR32, bit 5) bits cleared, together Automatic Network Selection: External PHY
with the XPHYFD (BCR32, bit 4) and XPHYSP Present but Not Auto-Negotiable
(BCR32, bit 3) bits set to the desired configuration. The
The second case occurs when the MIIPD (BCR32, bit
Network Port Manager will send a few frames to vali-
14) bit is 1. This indicates that there is an external PHY
date the configuration.
attached to Am79C971 controller’s MII. If more than
If FCON (BCR32, bit 0) is set to 1, this bit will force the one external PHY is attached to the MII Management
internal Network Port Manager into Fast Configuration Interface, then the DANAS (BCR32, bit 7) bit must be
Mode. During this mode, the Network Port Manager will set to 1 and then all configuration control should revert
not attempt to start Auto-Negotiation on the internal as to software. The Am79C971 controller will read the reg-
well as the external PHY. Instead, it will rely on link in- ister of the external PHY to determine its status and
tegrity tests for link pass state. This will accelerate the network capabilities. See Appendix E, Auto Negotiation
automatic port selection on the Am79C971 controller. Registers, for the bit descriptions of the MII Status reg-
The Network Port Manager in Fast Configuration Mode ister. If the external PHY is not Auto-Negotiation capa-
will start with the external PHY if one is detected. If the ble and/or the XPHYANE (BCR32, bit 5) bit is set to 0,
link does not come up, the Network Port Manager will then the Network Port Manager will match up the exter-
enable the internal 10BASE-T MAU. If the internal port nal PHY capabilities with the XPHYFD (BCR 32, bit 4)
also does not come up, the Network Port Manager will and the XPHYSP (BCR32, bit 3) bits programmed from
continue to search the MII and the internal T-MAU ports the EEPROM. The Am79C971 controller will then pro-
while enabling the internal AUI por t. The FCON gram the external PHY with those values. A new read
(BCR32, bit 0) should only be used if the network is ex- of the external PHYs MII Status register will be made to
periencing difficulty and is not stable. see if the link is up. If the link does not come up as pro-
grammed after a specific time, the Am79C971 control-
CAUTION: The Network Port Manager utilizes the
ler will fail the external PHY link and start the internal
PHYADD (BCR33, bits 9-5) to communicate with the
PHY process as described above. The Am79C971
external PHY during the automatic port selection pro-
controller will only start the external PHY link if the in-
cess. The PHYADD is copied into a shadow register
ternal link has failed. If both links have failed, the AUI is
after the Am79C971 controller has read the configura-
enabled but the Network Port Manager will still query
tion information from the EEPROM. Extreme care must
the internal and external PHYs for active links.
be exercised by the host software not to access BCR33
during this time. A read of PVALID (BCR19, bit 15) be- Automatic Network Selection: External PHY
fore accessing BCR33 will guarantee that the PHYADD Present and Auto-Negotiable
has been shadowed. The third case occurs when the MIIPD (BCR32, bit 14)
Am79C972’s Automatic Network Port selection mecha- bit is 1. This indicates that there is an external PHY at-
nism falls within the following three general categories: tached to Am79C971 controller’s MII. If more than one
80 Am79C971
external PHY is attached to the MII Management Inter- handshake is to prevent the 6692 from renegotiating
face, then the DANAS (BCR32, bit 7) bit must be set to the link without the Network Port Manager’s knowl-
1 and then all configuration control should revert to edge. Connecting the LED0 pin to the 10BTRCV pin of
software. The Am79C971 controller will read the MII the 6692 will accomplish this. The LED0 reports the link
Status register of the external PHY to determine its sta- status from the internal TMAU. The Network Port Man-
tus and network capabilities. See Appendix E for the bit ager monitors the internal link status, and knowing
descriptions of the MII Status register. If the external when the 6692 will start to renegotiate the link, it will
PHY is Auto-Negotiation capable and/or the XPHYANE stay in synchronization with the 6692.
(BCR32, bit 5) bit is set to 1, then the Am79C971 con-
Automatic Network Selection: Force External Reset
troller will start the external PHY’s Auto-Negotiation
process. The Am79C971 controller will write to the ex- If the XPHYRST bit (BCR32, bit 6) is set to 1, then the
ternal PHY’s Advertisement register with the following external case flow changes slightly. The Am79C971
conditions set: turn off the Next Pages support, set the controller will write to the external PHY’s MII Control
Technology Ability Field (See Appendix E for the Auto- register with the RESET bit set to 1 (See Appendix E,
Negotiation register bit descriptions) from the external Auto Negotiation Registers, for the MII register bit de-
PHY MII Status register read, and set the Type Selector scriptions). This will force a complete reset of the exter-
field to the IEEE 802.3 standard. The Am79C971 con- nal PHY. The Am79C971 controller after a specific time
troller will then write to the external PHY’s MII Control will poll the external PHY’s MII Control register to see if
register instructing the external PHY to negotiate the the RESET bit is 0. After the RESET bit is cleared, then
link. The Am79C971 controller will poll the external the normal flow continues.
PHY’s MII Status register until the Auto-Negotiation
External Address Detection Interface
Complete bit is set to 1and the Link Status bit is set to
1. The Am79C971 controller will then wait a specific (EADI)
time and then again read the external PHY’s MII Status The EADI is provided to allow external address filtering
register. If the Am79C971 controller sees that the exter- and to provide a Receive Frame Tag word for propri-
nal PHY’s link is down, it will try to bring up the external etary routing information. It is selected by setting the
PHY’s link manually as described above. A new read of EADISEL bit in BCR2 to 1. This feature is typically uti-
the external PHY’s MII Status register will be made to lized by terminal servers, bridges and/or router prod-
see if the link is up. If the link does not come up as pro- ucts. The EADI interface can be used in conjunction
grammed after a specific time, the Am79C971 control- with external logic to capture the packet destination ad-
ler will fail the external PHY link and start the process dress from the serial bit stream as it arrives at the
again for the internal PHY. If the link has failed, the AUI Am79C971 controller, to compare the captured ad-
is enabled, but the Network Port Manager will still query dress with a table of stored addresses or identifiers,
the external PHY for an active link. and then to determine whether or not the Am79C971
controller should accept the packet.
Automatic Network Selection: Working with the
Micro Linear 6692 External Address Detection Interface: Internal PHY
The final case that occurs is the hybrid condition that The EADI interface outputs are delivered directly from
does not fit neither the Auto-Negotiable case nor the the NRZ decoded data and clock recovered by the
Non-Auto-Negotiable case. An example of this case is Manchester decoder. This allows the external address
the Micro Linear 6692 PHY. The Micro Linear 6692 detection to be performed in parallel with frame recep-
PHY masquerades as an Auto-Negotiable PHY by pro- tion and address comparison in the MAC Station Ad-
viding Auto-Negotiation capabilities, but does not pro- dress Detection (SAD) block of the Am79C971
vide the 10BASE-T MAU. It relies on the MAC controller.
controller, the Am79C971 controller in this case, to pro-
SRDCLK is provided to allow clocking of the receive bit
vide the 10BASE-T MAU for it. The Network Port Man-
stream into the external address detection logic. Note
ager handles this condition virtually the same way as
that when the 10BASE-T port is selected, transitions on
the Auto-Negotiable case, except for the final hand-
SRDCLK will only occur during receive activity. When
shake that enables the internal 10BASE-T MAU. After
the AUI port is selected, transitions on SRDCLK will
the 6692 negotiates for the 10BASE-T MAU, it monitors
occur during both transmit and receive activity. Once a
the link for Normal LInk Pulses (NLPs). If it sees the
received frame commences and data and clock are
NLPs, then it will report that it completed the Auto-Ne-
available from the decoder, the EADI logic will monitor
gotiation process. The Am79C971 controller will read
the alternating (“1,0”) preamble pattern until the two 1s
the MII and Auto-Negotiation registers to figure out
of the Start Frame Delimiter (SFD, 10101011 bit pat-
which port has been negotiated. At this point, the Net-
tern) are detected, at which point the SFBD output will
work Port Manager will enable the internal 10BASE-T
be driven HIGH.
MAU, if that port has been negotiated, and complete
the first part of the handshake. The final part of the
Am79C971 81
The SFBD signal will initially be LOW. The assertion of after the last bit of the destination address is available.
SFBD is a signal to the external address detection logic EAR must have a pulse width of at least 110 ns.
that the SFD has been detected and that subsequent
The EADI outputs continue to provide data throughout
SRDCLK cycles will deliver packet data to the external
the reception of a frame. This allows the external logic
logic. Therefore, when SFBD is asserted, the external
to capture frame header information to determine pro-
address matching logic should begin de-serialization of
tocol type, internetworking information, and other use-
the SRD data and send the resulting destination ad-
ful data.
dress to a Content Addressable Memory (CAM) or
other address detection device. In order to reduce the The EADI interface will operate as long as the STRT bit
amount of logic external to the Am79C971 controller for in CSR0 is set, even if the receiver and/or transmitter
multiple address decoding systems, the SFBD signal are disabled by software (DTX and DRX bits in CSR15
will toggle at each new byte boundary within the are set). This configuration is useful as a semi-power-
packet, subsequent to the SFD. This eliminates the down mode in that the Am79C971 controller will not
need for externally supplying byte framing logic. perform any power-consuming DMA operations. How-
ever, external circuitry can still respond to control
SRD is the decoded NRZ data from the network. This
frames on the network to facilitate remote node control.
signal can be used for external address detection. Note
Table 11 summarizes the operation of the EADI inter-
that when the 10BASE-T port is selected, transitions on
face.
SRD will only occur during receive activity. When the
AUI or GPSI port is selected, transitions on SRD will
occur during receive activity. Table 11. EADI Operations
The EAR pin should be driven LOW by the external ad- Required Received
dress comparison logic to reject a frame. PROM EAR Timing Messages
No timing
If an address match is detected by comparison with ei- 1 X All received frames
requirements
ther the Physical Address or Logical Address Filter reg-
No timing
isters contained within the Am79C971 controller or the 0 1 All received frames
requirements
frame is of the type ’Broadcast’, then the frame will be
Am79C971
accepted regardless of the condition of EAR. When the Low for 110 ns
controller internal
EADISEL bit of BCR2 is set to 1 and the Am79C971 during the window
physical address
controller is programmed to promiscuous mode 0 0 from 0 bits after
and logical address
(PROM bit of the Mode Register is set to 1), then all in- SFD to 512 bits
filter matches and
coming frames will be accepted, regardless of any ac- after SFD
broadcast frames
tivity on the EAR pin.
External Address Detection Interface: External
Internal address match is disabled when PROM PHY
(CSR15, bit 15) is cleared to 0, DRCVBC (CSR15, bit
14) and DRCVPA (CSR15, bit 13) are set to 1, and the When using the MII, the EADI interface changes to re-
Logical Address Filter registers (CSR8 to CSR11) are flect the changes on that interface. Except for the nota-
programmed to all zeros. tions below the interface conforms to the previous
functionality. The data arrives in nibbles and can be at
When the EADISEL bit of BCR2 is set to 1 and internal a rate of 25 MHz or 2.5 MHz.
address match is disabled, then all incoming frames
will be accepted by the Am79C971 controller, unless The MII provides all necessary data and clock signals
the EAR pin becomes active during the first 64 bytes of needed for the EADI interface. Consequently, SRDCLK
the frame (excluding preamble and SFD). This allows and SRD are not used and are driven to 0. Data for the
external address lookup logic approximately 58 byte EADI is the RXD(3:0) receive data provided to the MII.
times after the last destination address bit is available Instead of deserializing the network data, the user will
to generate the EAR signal, assuming that the receive the data as 4 bit nibbles. RX_CLK is provided
Am79C971 controller is not configured to accept runt to allow clocking of the RXD(3:0) receive nibble stream
packets. The EADI logic only samples EAR from 2 bit into the external address detection logic. The RXD(3:0)
times after SFD until 512 bit times (64 bytes) after SFD. data is synchronous to the rising edge of the RX_CLK.
The frame will be accepted if EAR has not been as- The assertion of SFBD is a signal to the external ad-
serted during this window. If Runt Packet Accept dress detection logic that the SFD has been detected
(CSR124, bit 3) is enabled, then the EAR signal must and that the first valid data nibble is on the RXD(3:0)
be generated prior to the 8 bytes received, if frame re- data bus. The SFBD signal is delayed one RX_CLK
jection is to be guaranteed. Runt packet sizes could be cycle from the above definition and actually signals the
as short as 12 byte times (assuming 6 bytes for source start of valid data. In order to reduce the amount of
address, 2 bytes for length, no data, 4 bytes for FCS) logic external to the Am79C971 controller for multiple
82 Am79C971
address decoding systems, the SFBD signal will go input, data input clock, and the data input for the re-
HIGH at each new byte boundary within the packet, ceive frame tagging enable, respectively.
subsequent to the SFD. This eliminates the need for ex-
The receive frame tag register is a shift register that
ternally supplying byte framing logic.
shifts data in MSB first, so that less than the 15 bits al-
The EAR pin function is the same and should be driven located may be utilized by the user. The upper bits not
LOW by the external address comparison logic to reject utilized will return zeros. The receive frame tag register
a frame. is set to 0 in between reception of frames. After receiv-
ing SFBD indication on the EADI, the user can start
External Address Detection Interface: Receive
shifting data into the receive tag register until one net-
Frame Tagging
work clock period before the Am79C971 controller re-
The Am79C971 controller supports receive frame tag- ceives the end of the current receive frame.
ging in both internal PHY mode or in the MII mode. The
method remains constant, but the chip interface pins In the MII mode, the user must see the RX_CLK to
will change between the MII and the internal PHY drive the synchronous receive frame tag data interface.
modes. The receive frame tagging implementation will After receiving the SFBD indication, sampled by the ris-
be a two- and three-wire chip interface, respectively, ing edge of the RX_CLK, the user will drive the data
added to the existing EADI. input and the data input enable synchronous with the
rising edge of the RX_CLK. The user has until one net-
The Am79C971 controller supports up to 15 bits of re- work clock period before the deassertion of the RX_DV
ceive frame tagging per frame in the receive frame sta- to input the data into the receive frame tag register. At
tus (RFRTAG). The RFRTAG bits are in the receive the deassertion of the RX_DV, the receive frame tag
frame status field in RMD2 (bits 30-16) in 32-bit soft- register will no longer accept data from the two-wire in-
ware mode. The receive frame tagging is not supported terface. If the user is still driving the data input enable
in the 16-bit software mode. The RFRTAG field are all pin, erroneous or corrupted data may reside in the re-
zeros when either the EADISEL (BCR2, bit3) or the ceive frame tag register. See Figure 40.
RXFRTAG (CSR7, bit 14) are set to 0. When EADISEL
(BCR2, bit 3) and RXFRTAG (CSR7, bit 14) are set to In the internal PHY mode, the user must use the recov-
1, then the RFRTAG reflects the tag word shifted in dur- ered receive data clock driven on the SRDCLK pin to
ing that receive frame. drive the synchronous receive frame tag data interface.
After receiving the SFBD indication, sampled by the ris-
In the MII mode, the two-wire interface will use the ing edge of the recovered receive data clock, the user
MIIRXFRTGD and MIIRXFRTGE pins from the EADI will drive the data input and the data input enable syn-
interface. These pins will provide the data input and chronous with the rising edge of the recovered receive
data input enable for the receive frame tagging, respec- data clock. The user has until one network clock period
tively. These pins are normally not used during the MII before the deassertion of the data from the network to
operation. input the data into the receive frame tag register. At the
In the internal PHY mode, the three-wire interface will completion of received network data, the receive frame
use the RXFRTGD, SRDCLK, and the RXFRTGE pins tag register will no longer accept data from the two-wire
from the EADI and MII. These pins will provide the data interface. If the user is still driving the data input enable
pin, erroneous or corrupted data may reside in the re-
ceive frame tag register. See Figure 41.
RX_CLK
RX_DV
SF/BD
MIIRXFRTGE
MIIRXFRTGD 20550D-44
Figure 40. MII Receive Frame Tagging
Am79C971 83
SRDCLK ..
SRD SFD Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bitx Bity Bitz
SFBD ..
MIIRXFRTGE ..
MIIRXFRTGD ..
20550D-44
Figure 41. Internal PHY Receive Frame Tagging
Expansion Bus Interface EBWE is connected to the WE of the SRAM and Flash
devices.
The Am79C971 controller contains an Expansion Bus
Interface that supports two different boot devices, The Expansion Data Bus is configured for 16-bit word
EPROM and Flash, as well as SRAM used as an exten- access during SRAM accesses and 8-bit byte access
sion to the internal FIFOs to buffer packets. The during EPROM/Flash accesses. During SRAM ac-
Am79C971 controller supports Flash and EPROM de- cesses, EBD[7:0] provides the lower data byte while
vices as boot devices as well as providing read/write EBDA[15:8] provides the upper data byte. During
access to Flash or EPROM while the Am79C971 con- EPROM/Flash accesses, EBD[7:0] provides the data
troller is in STOP or in SPND or when the SRAM SIZE byte. See Figure 42.
bits (BCR25, bits 7-0) are set to 0. While in STOP, the
Expansion ROM - Boot Device Access
Am79C971 controller provides read/write diagnostic
access to SRAM (when present). This limitation on the The Am79C971 controller supports EPROM or Flash
SRAM diagnostic is necessary to prevent data corrup- as an Expansion ROM boot device. Both are config-
tion. ured using the same methods and operate the same.
See the previous section on Expansion ROM transfers
The signal AS_EBOE is provided to strobe the upper 8 to get the PCI timing and functional description of the
bits of the address into an external ‘374 (D flip-flop) ad- transfer method. The Am79C971 controller is function-
dress latch. AS_EBOE is asser ted LOW during ally equivalent to the PCnet-PCI II controller with Ex-
EPROM/Flash read operations to control the OE input pansion ROM. See Figure 43 and Figure 44.
of the EPROM/Flash.
The Am79C971 controller will always read four bytes for
The Expansion Bus Address is split into two different every host Expansion ROM read access. The interface
bus es, EBUA _EB A[7:0] and EB DA [15:8]. Th e to the Expansion Bus runs synchronous to the PCI bus
EBUA_EBA[7:0] provides the least and the most signif- interface clock. The Am79C971 controller will start the
icant address byte. When accessing SRAM and read operation to the Expansion ROM by driving the
EPROM/Flash the EBUA_EBA[7:0] is strobed into an upper 8 bits of the Expansion ROM address on
external ‘374 (D flip-flop) address latch. This consti- EBUA_EBA[7:0]. One-half clock later, AS_EBOE goes
tutes the most significant portion of the Expansion Bus high to allow registering of the upper address bits ex-
Addr es s. For S RAM/E PROM/Fla sh ac ces ses, ternally. The upper portion of the Expansion ROM ad-
EBUA_EBA[7:0] constitutes the remaining least signif- dress will be the same for all four byte read cycles.
icant address byte. For byte oriented EPROM/Flash ac- AS_EBOE is driven high for one-half clock,
cesses, EBDA[15:8] constitutes the upper or middle EBUA_EBA[7:0] are driven with the upper 8 bits of the
address byte. EBADDRU (BCR29, bits 3-0) should be Expansion ROM address for one more clock cycle after
set to 0 even when not used, since EBADDRU consti- AS_EBOE goes low. Next, the Am79C971 controller
tutes the EBUA portion of the EBUA EBA address byte starts driving the lower 8 bits of the Expansion ROM
and is strobed into the external’374 address latch. address on EBUA_EBA[7:0].
The signal EROMCS is connected to the CS/CE input
of the EPROM/Flash. The signal ERAMCS is con-
nected to the CE/CS input of the SRAM. The signal
84 Am79C971
EBD[7:0] I/O[7:0]
A[14:8]
A[7:0]
32K x 8 SRAM
EBWE WE
ERAMCS CS
OE
EBUA_EBA[7:0]
'374
D-FF
AS_/EBOE
EBDA[15:8] I/O[7:0]
A[14:8]
Am79C971 A[7:0]
32K x 8 SRAM
WE
CS
OE
A[23:16]
A[15:8]
A[7:0]
FLASH
WE
DQ[7:0]
EROMCS
CS
OE
20550D-45
Figure 42. SRAM and Flash Configuration for the Expansion Bus
The time that the Am79C971 controller waits for data to tACC <= ROMTMG* clock period - tv_A_D - ts_D
be valid is programmable. ROMTMG (BCR18, bits 15-
For an adapter card application, the value used for
12) defines the time from when the Am79C971 control-
clock period should be 30 ns to guarantee correct inter-
ler drives EBUA_EBA[7:0] with the lower 8 bits of the
face timing at the maximum clock frequency of 33 MHz.
Expansion ROM address to when the Am79C971 con-
troller latches in the data on the EBD[7:0] inputs. The The timing diagram in Figure 45 assumes the default
register value specifies the time in number of clock cy- programming of ROMTMG (1001b = 9 CLK). After
cles. When ROMTMG is set to nine (the default value), reading the first byte, the Am79C971 controller reads in
EBD[7:0] is sampled with the next rising edge of CLK three more bytes by incrementing the lower portion of
ten clock cycles after EBUA_EBA[7:0] was driven with the ROM address. After the last byte is strobed in,
a new address value. The clock edge that is used to TRDY will be asserted on clock 50. When the host tries
sample the data is also the clock edge that generates to perform a burst read of the Expansion ROM, the
the next Expansion ROM address. All four bytes of Ex- Am79C971 controller will disconnect the access at the
pansion ROM data are stored in holding registers. One second data phase.
clock cycle after the last data byte is available, the
The host must program the Expansion ROM Base Ad-
Am79C971 controller asserts TRDY.
dress register in the PCI configuration space before the
The access time for the Expansion ROM device (tACC) first access to the Expansion ROM. The Am79C971
can be calculated by subtracting the clock-to-output controller will not react to any access to the Expansion
delay for the EBUA_EBA[7:0] outputs (tv_A_D) and the ROM until both MEMEN (PCI Command register, bit 1)
input-to-clock setup time for the EBD[7:0] inputs (ts_D) and ROMEN (PCI Expansion ROM Base Address reg-
from the time defined by ROMTMG: ister, bit 0) are set to 1.
Am79C971 85
EBD[7:0]
EBWE
ERAMCS A[15:8]
A[7:0]
EBUA_EBA[7:0]
EPROM
DQ[7:0]
EROMCS CS
OE
EBDA[15:8]
Am79C971
AS_EBOE
20550D-46
Figure 43. EPROM Only Configuration for the Expansion Bus (64K EPROM)
After the Expansion ROM is enabled, the Am79C971 Direct Flash Access
controller will claim all memory read accesses with an Am79C971 controller supports Flash as an Expansion
address between ROMBASE and ROMBASE + 1M - 4 ROM device, as well as providing a read/write data
(ROMBASE, PCI Expansion ROM Base Address reg- path to the Flash. The Am79C971 controller will sup-
ister, bits 31-20). The address output to the Expansion port up to 1 Mbyte of Flash on the Expansion Bus. The
ROM is the offset from the address on the PCI bus to Flash is accessed by a read or write to the Expansion
ROMBASE. The Am79C971 controller aliases all ac- Bus Data port (BCR30). The user must load the upper
cesses to the Expansion ROM of the command types address EPADDRU (BCR 29, bits 3-0) and then set the
Memory Read Multiple and Memory Read Line to the FLASH (BCR29, bit 15) bit to a 1. The Flash read/write
basic Memory Read command. utilizes the PCI clock instead of the EBCLK during all
Since setting MEMEN also enables memory mapped accesses. EPADDRU is not needed if the Flash size is
access to the I/O resources, attention must be given to 64K or less, but still must be programmed. The user will
the PCI Memory Mapped I/O Base Address register, then load the lower 16 bits of address, EPADDRL (BCR
before enabling access to the Expansion ROM. The 28, bits 15-0).
host must set the PCI Memory Mapped I/O Base Ad- Flash/EPROM Read
dress register to a value that prevents the Am79C971
controller from claiming any memory cycles not in- A read to the Expansion Bus Data Port (BCR30) will
tended for it. start a read cycle on the Expansion Bus Interface. The
Am79C971 controller will drive EBUA_EBA[7:0] with
During the boot procedure, the system will try to find an the most significant address byte at the same time the
Expansion ROM. A PCI system assumes that an Ex- Am79C971 controller will drive AS_EBOE high to
pansion ROM is present when it reads the ROM signa- strobe the address in the external ‘374 (D flip-flop). On
ture 55h (byte 0) and AAh (byte 1). A design without the next clock, the Am79C971 controller will drive
Expansion ROM can guarantee that the Expansion EBDA[15:8] and EBUA_EBA[7:0] with the middle and
ROM detection fails by connecting two adjacent EBD least significant address bytes.
pins together and tying them high or low.
86 Am79C971
EBD[7:0]
Am79C971
'374
EBWE D-FF A[19:16]
ERAMCS A[15:8]
A[7:0]
EBUA_EBA[7:0] EPROM
DQ[7:0]
EROMCS CS
OE
EBDA[15:8]
AS_EBOE
20550D-47
Figure 44. EPROM Only Configuration for the Expansion Bus (>64K EPROM)
Am79C971 87
EBCLK
EBUA_EBA[7:0] Upper Lower Lower

Address Address Address
tv_A_D
EBDA[15:8], EBD[7:0]
DATA DATA
ERAMCS t_CS_H
t_CS_L
t_WE_CSAD
EBWE
t_WE_L t_WE_H
t_AS_H
AS_EBOE
t_AS_L
20550D-48
Figure 45. Expansion ROM Bus Read Sequence
EBUA[19:16]
CLK 1 2 3 4 5 6 7 8 9 10 11 12 13
EBUA_EBA[7:0] EBA[7:0]
EBDA[15:8] EBDA[15:8]
EBD[7:0]
EROMCS
AS_EBOE
20550D-49
Figure 46. Flash Read from Expansion Bus Data Port
88 Am79C971
The EROMCS is driven low for the value ROMTMG + incremented and a continuous series of reads from the
1. Figure 46 assumes that ROMTMG is set to nine. Expansion Data Port (EBDATA, BCR30) is possible.
EBD[7:0] is sampled with the next rising edge of CLK The address incrementor will roll over without warning
ten clock cycles after EBUA_EBA[7:0] was driven with and without incrementing the upper address EBAD-
a new address value. This PCI slave access to the DRU.
Flash/EPROM will result in a retry for the very first ac-
The Flash write is almost the same procedure as the
cess. Subsequent accesses may give a retry or not, de-
read access, except that the Am79C971 controller will
pending on whether or not the data is present and valid.
not drive AS_EBOE low. The EROMCS and EBWE are
The access time is dependent on the ROMTMG bits
driven low for the value ROMTMG again. The write to
(BCR18, bits 15-12) and the Flash/EPROM. This ac-
the FLASH port is a posted write and will not result in a
cess mechanism differs from the Expansion ROM ac-
retry to the PCI unless the host tries to write a new
cess mechanism since only one byte is read in this
value before the previous write is complete, then the
manner, instead of the 4 bytes in an Expansion ROM
host will experience a retry. The FLASH can only be ac-
access. The PCI bus will not be held during accesses
cessed while in STOP or when the SRAM_SIZE = 0
through the Expansion Bus Data Port. If the LAAINC
(BCR25, bits 7-0). See Figure 47.
(BCR29, bit 15) is set, the EBADDRL address will be
EBUA[19:16]
CLK 1 2 3 4 5 6 7 8 9 10 11 12 13
EBUA_EBA[7:0] EBA[7:0]
EBDA[15:8] EBDA[15:8]
EBD[7:0]
EROMCS
AS_EBOE
20550D-50
EBWE
Figure 47. Flash Write from Expansion Bus Data Port
AMD Flash Programming the AMD Flash Embedded Erase Algorithm command
AMD’s Flash products are programmed on a byte-by- sequence, the Flash device will program and verify the
byte basis. Programming is a four bus cycle operation. entire memory for an all zero data pattern prior to elec-
There are two “unlock” write cycles. These are followed trical erase. The Am79C971 controller is not required
by the program set-up command and data write cycles. to provide any controls or timings during these opera-
Addresses are latched on the falling edge of EBWE tions. The automatic erase begins on the rising edge of
and the data is latched on the rising edge of EBWE. the last EBWE pulse in the command sequence and
The rising edge of EBWE begins programming. terminates when the data on EBD[7] is 1, at which time
the Flash device returns to the read mode. Polling by
Upon executing the AMD Flash Embedded Program the Am79C971 controller is not required during the
Algorithm command sequence, the Am79C971 con- erase sequence. The following FLASH programming-
troller is not required to provide further controls or tim- table excerpt (Table 12) shows the command sequence
ing. The AMD Flash product will compliment EBD[7] for byte programming and sector/chip erasure on an
during a read of the programmed location until the pro- AMD Flash device. In the following table, PA and PD
gramming is complete. The host software should poll stand for programmed address and programmed data,
the programmed address until EBD[7] matches the and SA stands for sector address.
programmed value.
The Am79C971 controller will support only a single
AMD Flash byte programming is allowed in any se- sector erase per command and not concurrent sector
quence and across sector boundaries. Note that a data erasures. The Am79C971 controller will support most
0 cannot be programmed back to a 1. Only erase oper- FLASH devices as long as there is no timing require-
ations can convert zeros to ones. AMD Flash chip ment between the completion of commands. The
erase is a six-bus cycle operation. There are two unlock FLASH access time cannot be guaranteed with the
write cycles, followed by writing the set-up command. Am79C971 controller access mechanism. The
Two more unlock cycles are then followed by the chip Am79C971 controller will also support only Flash de-
erase command. Chip erase does not require the user vices that do not require data hold times after write op-
to program the device prior to erasure. Upon executing erations.
Am79C971 89
Table 12. Am29Fxxx Flash Command
Bus
Write
Command Cycles First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Sequence Req’d Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Byte Program 4 5555h AAh 2AAAh 55H 5555h A0h PA PD
Chip Erase 6 5555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h 5555h 10h
Sector Erase 6 5555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h SA 3h
SRAM Configuration The SRAM_BND upon H_RESET will be reset to
The Am79C971 controller supports SRAM as a FIFO 0000h. The Am79C971 controller will not have any
extension as well as providing a read/write data path to transmit buffer space unless SRAM_BND is pro-
the SRAM. See Figure 48. The Am79C971 controller grammed. The last configuration parameter necessary
will support up to 128K of SRAM on the Expansion is the clock source used to control the Expansion Bus
Bus. See Figure 49. interface. This is programmed through the SRAM Inter-
face Control register. The externally driven Expansion
External SRAM Configuration Bus Clock (EBCLK) can be used by specifying a value
The SRAM_SIZE (BCR25, bits 7-0) programs the size of 010h in EBCS (BCR27, bits 5-3). This allows the
of the external SRAM. SRAM_SIZE can also be pro- user to utilize any clock that may be available.
grammed to a smaller value than what is present on the There are two standard clocks that can be chosen as
Expansion Bus. well, the PCI clock or the crystal clock used to power
The external SRAM should be programmed on a 512- the network MAUs. When the PCI or the crystal clock is
byte boundary. However, there should be no accesses used, the EBCLK does not have to be driven, but it
to the RAM space while the Am79C971 controller is must be tied to VDD through a resistor. The user must
running. The Am79C971 controller assumes that it specify an SRAM clock (BCR27, bits 5-3) that will not
completely owns the SRAM while it is in operation. To stop unless the Am79C971 controller is stopped. Oth-
specify how much of the SRAM is allocated to transmit erwise, the Am79C971 controller will report buffer over-
and how much is allocated to receive, the user should flows, underflows, corr upt data, and will hang
program SRAM_BND (BCR26, bits 7-0) with the page eventually.
boundar y where the receive buffer begins. The The user can decide to use a fast clock and then divide
SRAM_BND also should be programmed on a 512- down the frequency to get a better duty-cycle if re-
byte boundary. The transmit buffer space starts at quired. The choices are a divide by 2 or 4 and is pro-
0000h. It is up to the user or the software driver to split grammed by the CLK_FAC bits (BCR27, bits 2-0). Note
up the memory for transmit or receive; there is no de- that the Am79C971 controller does not support an
faulted value. The minimum SRAM size required is four SRAM frequency above 33 MHz regardless of the clock
512-byte pages for each transmit and receive queue, and clock factor used.
which limits the SRAM size to be at least 4 Kbytes.
90 Am79C971
EBD[7:0] I/O[7:0]
A[14:8]
A[7:0]
32K x 8 SRAM
EBWE WE
ERAMCS CS
OE
EBUA_EBA[7:0]
'374
D-FF
AS_EBOE
EBDA[15:8] I/O[7:0]
A[14:8]
Am79C971
A[7:0]
32K x 8 SRAM
WE
CS
OE
20550D-51
Figure 48. SRAM Only Configuration for the Expansion Bus
Bus MAC
Rcv Rcv
FIFO FIFO
PCI Bus
Interface
Unit 802.3
MAC
Core
MAC
Bus Xmt
Xmt
FIFO
FIFO
Buffer FIFO
Management Control
Unit
20550D-52
Figure 49. Block Diagram With External SRAM
Am79C971 91
No SRAM Configuration wait for the first 64 bytes to pass to check for collisions
If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the in Low Latency Receive mode. The Am79C971 control-
SRAM size register, the Am79C971 controller will as- ler must be in STOP before switching to this mode. See
sume that there is no SRAM present and will reconfig- Figure 51.
ure the four internal FIFOs into two FIFOs, one for CAUTION: To provide data integrity when switching
transmit and one for receive. The FIFOs will operate into and out of the low latency mode, DO NOT SET
the same as in the PCnet-PCI II controller. When the the FASTSPNDE bit when setting the SPND bit. Re-
SRAM SIZE (BCR25, bits 7-0) value is 0, the SRAM ce iv e f ra me s WI LL b e ove rw ri t t en a n d t h e
BND (BCR26, bits 7-0) are ignored by the Am79C971 Am79C971 controller may give erratic behavior
controller. See Figure 50. when it is enabled again.
NOTE: A “No SRAM configuration” is only valid for Direct SRAM Access
10Mb mode. In 100Mb mode, SRAM is mandatory and The SRAM can be accessed through the Expansion
must always be used. Bus Data port (BCR30). To access this data port, the
Low Latency Receive Configuration user must load the upper address EPADDRU (BCR29,
If the LOLATRX (BCR27, bit 4) bit is set to 1, then the bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the
Am79C971 controller will configure itself for a low la- user will load the lower 16 bits of address EPADDRL
tency receive configuration. In this mode, external (BCR28, bits 15-0). To initiate a read, the user reads
SRAM is required at all times. If the SRAM_SIZE the Expansion Bus Data Port (BCR30). This slave ac-
(BCR25, bits 7-0) value is 0, the Am79C971 controller cess from the PCI will result in a retry for the very first
will not configure for low latency receive mode. The access. Subsequent accesses may give a retry or not,
Am79C971 controller will provide a fast path on the re- depending on whether or not the data is present and
ceive side bypassing the external RAM. All transmit valid. The direct SRAM access uses the same FLASH/
traffic will go to the SRAM, so SRAM_BND (BCR26, EPROM access except for accessing the SRAM in
bits 7-0) has no meaning in low latency receive mode. word format instead of byte format. This access is
When the Am79C971 controller has received 16 bytes meant to be a diagnostic access only. The SRAM can
from the network, it will start a DMA request to the PCI only be accessed while the Am79C971 controller is in
Bus Interface Unit. The Am79C971 controller will not STOP or SPND (FASTSPNDE is set to 0) mode.
Bus MAC
Rcv Rcv
FIFO FIFO
PCI Bus 802.3

MAC
Interface Core
Unit
Bus MAC
Xmt Xmt
FIFO FIFO
Buffer FIFO
Management Control
Unit
20550D-53
Figure 50. Block Diagram No SRAM Configuration
92 Am79C971
Bus MAC
Rcv Rcv
FIFO FIFO
PCI Bus
Interface
Unit 802.3
MAC
Core
Bus MAC
Xmt Xmt
FIFO FIFO
Buffer FIFO
Management Control
Unit
20550D-54
Figure 51. Block Diagram Low Latency Receive Configuration
SRAM Accesses AS_EBOE The least significant address byte is then

The SRAM access during normal operations is a single toggled on the EBUA_EBA[7:0] throughout the remain-
cycle address load to fill the upper bits into the ‘374 fol- der of the read/write access. The data word is made up
lowed by 17 subsequent accesses. This results in the of the most significant data byte EBDA[15:8], and the
best utilization for the 4-FIFO arbiter in the Am79C971 least significant data byte EBD[7:0]. ERAMCS is con-
controller. If the FIFO does not have enough data to nected to the CE/CS chip select of the external SRAM.
complete the full 18 cycles, the arbiter will switch after AS_EBOE provides the output enable signal to the
all of the data has been written or read. This under uti- SRAM during read operations. During write operations,
lization occurs only at the end of a packet. the AS_EBOE is driven high during the remainder of
the accesses. EBWE is toggled during SRAM writes.
The most significant address byte EBUA_EBA[7:0] is See Figure 52 and Figure 53.
registered into the external ‘374 by asser tion of
EBCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
EBD[15:0]
EBUA_EBA[7:0] 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0
AS_EBOE
EBWE
ERAMCS
20550D-55
Figure 52. Typical SRAM Read Operation
Am79C971 93
EBCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
EBD[15:0]
EBUA_EBA[7:0] 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0
AS_EBOE
EBWE
ERAMCS
Note:
EBD[15:0] = EBDA[15:8]+EBD[7:0] 20550D-56
Figure 53. Typical SRAM Write Operation
SRAM Interface Bandwidth Requirements EEPROM that is attached to the interface. Because of
When the EBCLK pin is used to drive the Expansion this automatic-read capability of the Am79C971 con-
Bus cycles and external SRAMs are present, the troller, an EEPROM can be used to program many of
CLK_FAC (BCR27, bits 2-0) selects the clock factor for the features of the Am79C971 controller at power-up,
the Expansion Bus Clock (EBCLK). The Expansion allowing system-dependent configuration information
Bus Clock can be divided down by factors of 2 or 4. For to be stored in the hardware, instead of inside the
maximum throughput capability to support maximum device driver.
wire rates in a full-duplex 100-Mbps network, a 33-MHz If an EEPROM exists on the interface, the Am79C971
clock should be supplied to the EBCLK input pin and controller will read the EEPROM contents at the end of
15-ns SRAM devices must be used. For systems with the H_RESET operation. The EEPROM contents will
lower throughput requirements, a lower clock fre- be serially shifted into a temporary register and then
quency, along with slower speed SRAM devices, may sent to various register locations on board the
be used. In a half-duplex 10-Mbps design, an EBCLK Am79C971 controller. Access to the Am79C971 con-
frequency as low as 2.5 MHz may be used, while still figuration space, the Expansion ROM or any I/O
providing sufficient bandwidth on the SRAM interface resource is not possible during the EEPROM read op-
to keep up with maximum wire data rates. eration. The Am79C971 controller will terminate any
Frequency Demands for Network Operation access attempt with the assertion of DEVSEL and
STOP while TRDY is not asserted, signaling to the ini-
The minimum supported clock frequency on the Ex- tiator to disconnect and retry the access at a later time.
pansion Bus for normal network operations is 10 MHz.
The minimum supported clock frequency on the PCI A checksum verification is performed on the data that
Bus for normal network operations is 15 MHz. The PCI is read from the EEPROM. If the checksum verification
clock pin can be stopped or run at any frequency, but passes, PVALID (BCR19, bit 15) will be set to 1. If the
may give underflows and overflows due to reduced checksum verification of the EEPROM data fails,
bandwidth. These minimum requirements apply only to PVALID will be cleared to 0, and the Am79C971 con-
10-Mbps half-duplex operation. Details of the clock fre- troller will force all EEPROM-programmable BCR reg-
quency and SRAM depth requirements for typical net- isters back to their H_RESET default values. However,
work can be found in the PCnet Fast Buffer Memory the content of the Address PROM locations (offsets
Performance White Paper, PID #20898A. 0h - Fh from the I/O or memory mapped I/O base ad-
dress) will not be cleared. The 8-bit checksum for the
EEPROM Interface entire 64 bytes of the EEPROM should be FFh.
The Am79C971 controller contains a built-in capability If no EEPROM is present at the time of the automatic
for reading and writing to an external serial 93C46 read operation, the Am79C971 controller will recognize
EEPROM. This built-in capability consists of an inter- this condition and will abort the automatic read opera-
face for direct connection to a 93C46 compatible tion and clear both the PREAD and PVALID bits in
EEPROM, an automatic EEPROM read feature, and a BCR19. All EEPROM-programmable BCR registers
user-programmable register that allows direct access will be assigned their default values after H_RESET.
to the interface pins. The content of the Address PROM locations (offsets
Automatic EEPROM Read Operation 0h - Fh from the I/O or memory mapped I/O base ad-
dress) will be undefined.
Shortly after the deassertion of the RST pin, the
Am79C971 controller will read the contents of the
94 Am79C971
If the user wishes to modify any of the configuration bits EEPROM-Programmable Registers
that are contained in the EEPROM, then the seven The following registers contain configuration informa-
command, data and status bits of BCR19 can be used tion that will be programmed automatically during the
to write to the EEPROM. After writing to the EEPROM, EEPROM read operation:
the host should set the PREAD bit of BCR19. This
action forces an Am79C971 controller reread of the ■ I/O offsets 0h-Fh Address PROM locations
EEPROM so that the new EEPROM contents will be ■ BCR2 Miscellaneous Configuration
loaded into the EEPROM-programmable registers on
■ BCR4 LED0 Status
board the Am79C971 controller. (The EEPROM-pro-
grammable registers may also be reprogrammed di- ■ BCR5 LED1 Status
rectly, but only information that is stored in the ■ BCR6 LED2 Status
EEPROM will be preserved at system power-down.)
■ BCR7 LED3 Status
When the PREAD bit of BCR19 is set, it will cause the
Am79C971 controller to ignore further accesses to the ■ BCR9 Full-Duplex Control
Am79C971 configuration space, the Expansion ROM, ■ BCR18 Burst and Bus Control
or any I/O resource until the completion of the EE-
■ BCR22 PCI Latency
PROM read operation. The Am79C971 controller will
terminate these access attempts with the assertion of ■ BCR23 PCI Subsystem Vendor ID
DEVSEL and STOP while TRDY is not asserted, sig- ■ BCR24 PCI Subsystem ID
naling to the initiator to disconnect and retry the access
■ BCR25 SRAM Size
at a later time.
■ BCR26 SRAM Boundary
EEPROM Auto-Detection
■ BCR27 SRAM Interface Control
The Am79C971 controller uses the EESK/LED1/SFBD
pin to determine if an EEPROM is present in the sys- ■ BCR32 MII Control and Status
tem. At the rising edge of CLK during the last clock dur- ■ BCR33 MII Address
ing which RST is asserted, the Am79C971 controller ■ BCR35 PCI Vendor ID
will sample the value of the EESK/LED1/SFBD pin. If
the sampled value is a 1, then the Am79C971 controller If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)
assumes that an EEPROM is present, and the EE- are cleared to 0, then the EEPROM read has experi-
PROM read operation begins shortly after the RST pin enced a failure and the contents of the EEPROM pro-
is deasserted. If the sampled value of EESK/LED1/ grammable BCR register will be set to default
SFBD is a 0, the Am79C971 controller assumes that an H_RESET values. The content of the Address PROM
external pulldown device is holding the EESK/LED1/ locations, however, will not be cleared.
SFBD pin low, indicating that there is no EEPROM in Note that accesses to the Address PROM I/O locations
the system. Note that if the designer creates a system do not directly access the Address EEPROM itself. In-
that contains an LED circuit on the EESK/LED1/SFBD stead, these accesses are routed to a set of shadow
pin, but has no EEPROM present, then the EEPROM registers on board the Am79C971 controller that are
auto-detection function will incorrectly conclude that an loaded with a copy of the EEPROM contents during the
EEPROM is present in the system. However, this will automatic read operation that immediately follows the
not pose a problem for the Am79C971 controller, since H_RESET operation.
the checksum verification will fail.
EEPROM MAP
Direct Access to the Interface
The automatic EEPROM read operation will access 32
The user may directly access the port through the words (i.e., 64 bytes) of the EEPROM. The format of
EEPROM register, BCR19. This register contains bits the EEPROM contents is shown in Table 14, beginning
that can be used to control the interface pins. By per- with the byte that resides at the lowest EEPROM ad-
forming an appropriate sequence of accesses to dress.
BCR19, the user can effectively write to and read from
the EEPROM. This feature may be used by a system Note that the first bit out of any word location in the EE-
configuration utility to program hardware configuration PROM is treated as the MSB of the register being pro-
information into the EEPROM. grammed. For example, the first bit out of EEPROM
word location 09h will be written into BCR4, bit 15; the
second bit out of EEPROM word location 09h will be
written into BCR4, bit 14, etc.
Am79C971 95
Table 13. EEPROM Content
Word Byte Byte
Address Addr. Most Significant Byte Addr. Least Significant Byte
First byte of the ISO 8802-3 (IEEE/ANSI 802.3)
2nd byte of the ISO 8802-3 (IEEE/ANSI
station physical address for this node, where “first
00h* 01h 802.3) station physical address for this 00h
byte” refers to the first byte to appear on the 802.3
node
medium
01h 03h 4th byte of the node address 02h 3rd byte of the node address
02h 05h 6th byte of the node address 04h 5th byte of the node address
03h 07h reserved location: must be 00h 06h Reserved location must be 00h
Hardware ID: must be 11h if compatibility
04h 09h 08h Reserved location must be 00h
to AMD drivers is desired
05h 0Bh User programmable space 0Ah User programmable space
MSB of two-byte checksum, which is the
LSB of two-byte checksum, which is the sum of bytes
06h 0Dh sum of bytes 00h-0Bh and bytes 0Eh and 0Ch
00h-0Bh and bytes 0Eh and 0Fh
0Fh
Must be ASCII “W” (57h) if compatibility Must be ASCII “W” (57h) if compatibility to AMD driver
07h 0Fh 0Eh
to AMD driver software is desired software is desired
BCR2[15:8] (Miscellaneous
08h 11h 10h BCR2[7:0] (Miscellaneous Configuration)
Configuration)
09h 13h BCR4[15:8] (Link Status LED) 12h BCR4[7:0] (Link Status LED)
0Ah 15h BCR5[15:8] (LED1 Status) 14h BCR5[7:0] (LED1 Status)
0Bh 17h BCR6[15:8] (LED2 Status) 16h BCR6[7:0] (LED2 Status)
0Ch 19h BCR7[15:8] (LED3 Status) 18h BCR7[7:0] (LED3 Status)
0Dh 1Bh BCR9[15:8] (Full-Duplex Control) 1Ah BCR9[7:0] (Full-Duplex Control)
0Eh 1Dh BCR18[15:8] (Burst and Bus Control) 1Ch BCR18[7:0] (Burst and Bus Control)
0Fh 1Fh BCR22[15:8] (PCI Latency) 1Eh BCR22[7:0] (PCI Latency)
BCR23[15:8] (PCI Subsystem Vendor
10h 21h 20h BCR23[7:0] (PCI Subsystem Vendor ID)
ID)
11h 23h BCR24[15:8] (PCI Subsystem ID) 22h BCR24[7:0] (PCI Subsystem ID)
12h 25h BCR25[15:8] (SRAM Size) 24h BCR25[7:0] (SRAM Size)
13h 27h BCR26[15:8] (SRAM Boundary) 26h BCR26[7:0] (SRAM Boundary)
14h 29h BCR27[15:8] (SRAM Interface Control) 28h BCR27[7:0] (SRAM Interface Control)
15h 2Bh BCR32[15:8] (MII Control and Status) 2Ah BCR32[7:0] (MII Control and Status)
16h 2Dh BCR33[15:8] (MII Address) 2Ch BCR33[7:0] (MII Address)
17h 2Fh BCR35[15:8] (PCI Vendor ID) 2Eh BCR35[7:0] (PCI Vendor ID)
18h 31h Reserved location must be 00h 30h Reserved location must be 00h
19h 33h Reserved location must be 00h 32h Reserved location must be 00h
1Ah 35h Reserved location must be 00h 34h Reserved location must be 00h
1Bh 37h Reserved location must be 00h 36h Reserved location must be 00h
1Ch 39h Reserved location must be 00h 38h Reserved location must be 00h
1Dh 3Bh Reserved location must be 00h 3Ah Reserved location must be 00h
1Eh 3Dh Reserved location must be 00h 3Ch Reserved location must be 00h
Checksum adjust byte for the 64 bytes of
the EEPROM contents, checksum of the
1Fh 3Fh 3Eh Reserved location must be 00h
64 bytes of the EEPROM should total to
FFh
Note:
*Lowest EEPROM address.
96 Am79C971
OR’d together to form a combined status signal. Each
LED pin combined status signal can be programmed to
There are two checksum locations within the EE-
run to a pulse stretcher, which consists of a 3-bit shift
PROM. The first checksum will be used by AMD driver
register clocked at 38 Hz (26 ms). The data input of
software to verify that the ISO 8802-3 (IEEE/ANSI
each shift register is normally at logic 0. The OR gate
802.3) station address has not been corrupted. The
output for each LED register asynchronously sets all
value of bytes 0Ch and 0Dh should match the sum of
three bits of its shift register when the output becomes
bytes 00h through 0Bh and 0Eh and 0Fh. The second
asserted. The inverted output of each shift register is
checksum location (byte 3Fh) is not a checksum total,
used to control an LED pin. Thus, the pulse stretcher
but is, instead, a checksum adjustment. The value of
provides 2 to 3 clocks of stretched LED output, or 52
this byte should be such that the total checksum for the
ms to 78 ms. See Figure 54.
entire 64 bytes of EEPROM data equals the value FFh.
The checksum adjust byte is needed by the Am79C971
controller in order to verify that the EEPROM content
has not been corrupted.
LED Support COL
COLE
The Am79C971 controller can support up to four LEDs. FDLS

FDLSE
LED outputs LED0, LED1, and LED2 allow for direct
JAB
connection of an LED and its supporting pullup device. JABE
LNKST
In applications that want to use the pin to drive an LED LNKSE
and also have an EEPROM, it might be necessary to RCV
TO
buffer the LED3 circuit from the EEPROM connection. RCVE PULSE
STRETCHER
When an LED circuit is directly connected to the RCVM
RCVME
EEDO/LED3/SRD pin, then it is not possible for most
RXPOL
EEPROM devices to sink enough IOL to maintain a valid RXPOLE
low level on the EEDO input to the Am79C971 control- XMT
ler. XMTE
ledctrl.eps
MII_SEL
Each LED can be programmed through a BCR register MIISE
to indicate one or more of the following network status MR_SPEED_SEL

or activities: Collision Status, Full-Duplex Link Status, 100E
Half-Duplex Link Status, Jabber Status, Receive MPS

MPSE
Match, Receive Polarity, Receive Status, Magic Packet,
Disable Transceiver, MII Enable Status, and Transmit LNKST
DXCVRCTL
Status. The LED pins can be configured to operate in
either open-drain mode (active low) or in totem-pole 20550D-57
mode (active high). The output can be stretched to
allow the human eye to recognize even short events Figure 54. LED Control Logic
that last only several microseconds. After H_RESET,
the four LED outputs are configured as shown in Table
14:
Power Savings Modes
SLEEP Mode
Table 14. LED Default Configuration The Am79C971 controller supports two hardware
LED power savings modes. Both are entered by driving the
Output Indication Driver Mode Pulse Stretch SLEEP pin LOW and by leaving the MPMODE (CSR 5,
Open Drain - bit 1) bit at its default value of 0.
LED0 Link Status Enabled
Active Low The power down mode that yields the most power sav-
LED1
Receive Open Drain -
Enabled
ings is called, coma mode. In coma mode, the entire
Status Active Low device is shut down. All inputs are ignored except the
Receive Open Drain - SLEEP pin itself. Coma mode is enabled when AWAKE
LED2 Enabled
Polarity Active Low (BCR2, bit 2) is at its default value of 0 and SLEEP is
Transmit Open Drain - asserted.
LED3 Enabled
Status Active Low
The second power saving mode is called, snooze
For each LED register, each of the status signals is mode. In snooze mode, enabled by setting AWAKE to
AND’d with its enable signal, and these signals are all 1 and driving the SLEEP pin LOW, the T-MAU receive
Am79C971 97
circuitry will remain active even while the SLEEP pin is to 1 (software control). Note that FASTSPNDE (CSR7,
driven LOW. All other sections of the device are shut bit 15) has no meaning in Magic Packet mode.
down except the LED0 pin, the only LED pin that con-
In Magic Packet mode, the Am79C971 controller re-
tinues to function, just as in normal operation. The
mains fully powered up (all VDD and VDDB pins must
LNKSTE bit must be set in BCR4 to enable indication
remain at their supply levels). The device will not gen-
of a good 10BASE-T link if there are link beat pulses or
erate any bus master transfers. No transmit operations
valid frames present. Once the T-MAU has a good link,
will be initiated on the network. The device will continue
LED0 will be active. This LED0 pin can be used to drive
to receive frames from the network, but all frames will
an LED and/or external hardware that directly controls
be automatically flushed from the receive FIFO. Slave
the SLEEP pin of the Am79C971 controller. In the case
accesses to the Am79C971 controller are still possible.
of driving external hardware, it can be used to tell an
The Magic Packet mode can be disabled at any time by
external SLEEP control logic to drive the SLEEP pin
deasserting SLEEP or clearing MPEN.
HIGH to bring the Am79C971 controller out of the
snooze mode. This configuration effectively wakes the A Magic Packet frame is a frame that is addressed to
system when there is any activity on the 10BASE-T the Am79C971 MAC and contains a data sequence in
link. Snooze mode can be used only if the T-MAU is the its data field made up of 16 repetitions of the physical
selected network port. Link beat pulses are not trans- addresses (PADR[47:0]). The Am79C971 controller will
mitted during snooze mode. search incoming frames until it finds a Magic Packet
frame. It starts scanning for the sequence after pro-
SLEEP must not be asserted while the Am79C971
cessing the length field of the frame. The data se-
controller is requesting the bus or while a bus cycle is
quence can begin anywhere in the data field of the
active. It is recommended to set the Am79C971 con-
frame, but must be detected before the Am79C971
troller into suspend mode (SPND (CSR5, bit 0) set to 1)
controller reaches the frame’s FCS field. Any deviation
or to stop the device (STOP (CSR0, bit 2) set to 1) be-
of the incoming frame’s data sequence from the re-
fore asserting the SLEEP pin.
quired physical address sequence, even by a single bit,
Before the sleep mode is invoked, the Am79C971 con- will prevent the detection of that frame as a Magic
troller will perfor m an inter nal S_RESET. This Packet frame.
S_RESET operation will not affect the values of the
The Am79C971 controller supports two different
BCR registers or the PCI configuration space.
modes of address detection for a Magic Packet frame.
S_RESET terminates all network activity abruptly. The
If MPPLBA (CSR5, bit 5) is at its default value of 0, the
host can use the suspend mode (SPND, CSR5, bit 0)
Am79C971 controller will only detect a Magic Packet
to terminate all network activity in an orderly sequence
frame if the destination address of the frame matches
before issuing an S_RESET.
the content of the physical address register (PADR). If
When coming out of the sleep mode, the Am79C971 MPPLBA is set to 1, the destination address of the
controller can be programmed to generate an interrupt Magic Packet frame can be unicast, multicast or broad-
and infor m the dr iver about the wake-up. The cast. Note that the setting of MPPLBA only effects the
Am79C971 controller will set SLPINT (CSR5, bit 9), address detection of the Magic Packet frame. The
when coming out of the sleep mode. INTA will be as- Magic Packet frame’s data sequence must be made up
serted, when the enable bit SLPINTE (CSR5, bit 8) is o f 1 6 r e p e t i t i o n s o f t h e p hy s i c a l a d d r e s s e s
set to 1. Note that the assertion of INTA due to SLPINT (PADR[47:0]), regardless of what kind of destination
is not dependent on the main interrupt enable bit INEA address it has.
(CSR0, bit 6), which will be cleared by the reset going
When the Am79C971 controller detects a Magic
into the sleep mode.
Packet frame, it sets MPINT (CSR5, bit 4) to 1. If INEA
The SLEEP pin should not be asserted during power (CSR0, bit 6) and MPINTE (CSR5, bit 3) are set to 1,
supply ramp-up. If it is desired that SLEEP be asserted INTA will be asserted. The interrupt signal can be used
at power up time, then the system must delay the as- wake up the system. As an alternative, one of the four
sertion of SLEEP until three clock cycles after comple- LED pins can be programmed to indicated that a Magic
tion of a hardware reset operation. Packet frame has been received. MPSE (BCR4-7, bit
9) must be set to 1 and the RCVE (BCR4-7, bit 2) must
Magic Packet Mode
be set to 0 to enable that function. Note that the polarity
Magic Packet mode is enabled by performing three of the LED pin can be programmed to be active high by
steps. First, the Am79C971 controller must be put into setting LEDPOL (BCR4-7, bit 14) to 1.
suspend mode (see description of CSR5, bit 0), allow-
ing any current network activity to finish. Next, MP- O n c e a M a gi c Pa cket fr am e i s d e t ec te d , t h e
MODE (CSR5, bit 1) must be set to 1 if it has not been Am79C971 controller will discard the frame internally,
set already. Finally, either SLEEP must be asserted but will not resume normal transmit and receive opera-
(hardware control) or MPEN (CSR5, bit 2) must be set tions until SLEEP is deasserted, or MPEN is cleared,
98 Am79C971
disabling Magic Packet mode. Once either of these for the TDI, TCK, and TMS pins. The boundary scan
events has occurred indicating that the system has de- circuit remains active during Sleep mode.
tected the assertion of INTA or an LED pin and is now TAP Finite State Machine
awake, the controller will continue polling the receive
and transmit descriptor rings where it left off. Re-initial- The TAP engine is a 16-state finite state machine
ization should not be performed. If the part is re-initial- (FSM), driven by the Test Clock (TCK), and the Test
ized, then the descriptor locations will be reset also, Mode Select (TMS) pins. An independent power-on
and the Am79C971 controller will not start where it left reset circuit is provided to ensure that the FSM is in the
off. TEST_LOGIC_RESET state at power-up. Therefore,
the TRST is not provided. The FSM is also reset when
If Magic Packet mode is disabled by the deassertion of TMS and TDI are high for five TCK periods.
SLEEP, then in order to immediately re-enable Magic
Packet mode, the SLEEP pin must remain deasserted Supported Instructions
for at least 200 ns before it is reasserted. If Magic In addition to the minimum IEEE 1149.1 requirements
Packet mode is disabled by clearing MPEN, then it may (BYPASS, EXTEST, and SAMPLE instructions), three
be immediately re-enabled by setting MPEN back to 1. additional instructions (IDCODE, TRIBYP, and SET-
BYP) are provided to further ease board-level testing.
The PCI bus interface clock (CLK) is not required to be
All unused instruction codes are reserved. See Table
running. Both INTA and the LED pins may be used to
15 for a summary of supported instructions.
indicate the receipt of a Magic Packet frame when the
CLK is stopped. If the system wishes to stop the CLK,
it should do so after enabling the Magic Packet mode. Table 15. IEEE 1149.1 Supported Instruction
The clock should be restarted before Magic Packet Summary
mode is disabled if MPEN is being cleared, or the clock
Instruc- Instruc- Selected
must be restarted right after Magic Packet mode is dis-
tion tion Data
abled if SLEEP is being deasserted. Otherwise, the re-
Name Code Description Mode Register
ceive FIFO may overflow if new frames arrive. The
EXTEST 0000 External Test Test BSR
network clock (XTAL) must continue running at all times
while in Magic Packet mode. ID Code
IDCODE 0001 Normal ID REG
Inspection
CAUTION: To prevent unwanted interrupts from other Sample
active parts of the Am79C971 controller, care must be SAMPLE 0010 Normal BSR
Boundary
taken to mask all likely interruptible events during TRIBYP 0011 Force Float Normal Bypass
Magic Packet mode. An example would be the inter-
Control
rupts from the MII which operate while in Magic Packet SETBYP 0100 Boundary To Test Bypass
mode. 1/0
IEEE 1149.1 (1990) Test Access Port BYPASS 1111 Bypass Scan Normal Bypass
Interface
Instruction Register and Decoding Logic
An IEEE 1149.1-compatible boundary scan Test Ac-
After the TAP FSM is reset, the IDCODE instruction is
cess Port is provided for board-level continuity test and
always invoked. The decoding logic gives signals to
diagnostics. All digital input, output, and input/output
control the data flow in the Data registers according to
pins are tested. Analog pins, including the AUI differen-
the current instruction.
tial driver (DO±) and receivers (DI±, CI±), and the crys-
tal input (XTAL1/XTAL2) pins are tested. The T-MAU Boundary Scan Register
drivers TXD ± , TXP ± , and receiver RXD ± are also Each Boundary Scan Register (BSR) cell has two
tested. The following is a brief summary of the IEEE stages. A flip-flop and a latch are used for the Serial
1149.1-compatible test functions implemented in the Shift Stage and the Parallel Output Stage, respectively.
Am79C971 controller. There are four possible operation modes in the BSR
Boundary Scan Circuit cell shown in Table 16.
The boundary scan test circuit requires four pins (TCK,
TMS, TDI, and TDO), defined as the Test Access Port Table 16. BSR Mode Of Operation
(TAP). It includes a finite state machine (FSM), an
instruction register, a data register array, and a power- 1 Capture
on reset circuit. Internal pull-up resistors are provided 2 Shift
3 Update
4 System Function
Am79C971 99
Other Data Registers Pin 143 (RST) is the first input to the NAND tree. Pin
Other data registers are the following: 145 (CLK) is the second input to the NAND tree, fol-
lowed by pin 147 (GNT). All other PCI bus, Expansion
1. Bypass Register (1 bit) Bus, MII, LED signals follow, counterclockwise, with pin
2. Device ID register (32 bits) (Table 17). 136 (EECS) being the last. Pins labeled NC, analog in-
terfaces, and all power supply pins are not part of the
NAND tree. Table 18 shows the complete list of pins
Table 17. Device ID Register connected to the NAND tree.
Bits 31-28 Version RST must be asserted low to start a NAND tree test
Bits 27-12 Part Number (0010 0110 0010 0011) sequence. Initially, all NAND tree inputs except RST
Manufacturer ID. The 11 bit manufacturer ID should be driven high. This will result in a high output
Bits 11-1 cod for AMD is 00000000001 in accordance at the INTA pin. If the NAND tree inputs are driven from
with JEDEC publication 106-A. high to low in the same order as they are connected to
Bit 0 Always a logic 1 build the NAND tree, INTA will toggle every time an ad-
ditional input is driven low. INTA will change to low,
The contents of the Device ID register is the same as when CLK is driven low and all other NAND tree inputs
the contents of CSR88. stay high. INTA will toggle back to high, when GNT is
additionally driven low. The square wave will continue
until all NAND tree inputs are driven low. INTA will be
NAND Tree Testing high, when all NAND tree inputs are driven low. See
The Am79C971 controller provides a NAND tree test Figure 56.
mode to allow checking connectivity to the device on a Note: Some of the pins connected to the NAND tree
printed circuit board. The NAND tree is built on all PCI are outputs in normal mode of operation. They must not
bus, MII, and LED signals. be driven from an external source until the Am79C971
NAND tree testing is enabled by asserting RST. The re- controller is configured for NAND tree testing.
sult of the NAND tree test can be observed on the INTA
pin. See Figure 55.
VDD
RST (pin143)
CLK (pin 145)
Am79C971
GNT (pin 147) Core
....
INTA
B S INTA (pin 142)
O
A
MUX
EECS (pin 136)
20550D-58
Figure 55. NAND Tree Circuitry
100 Am79C971
RST
CLK
GNT
REQ
AD[31:0] FFFFFFFF 0000FFFF
C/BE[3:0] F 7 3 1
IDSEL
FRAME
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
PAR
... ... ...
INTA
20550D-59
Figure 56. NAND Tree Waveform
Table 18. NAND Tree Pin Sequence

NAND
Tree Input NAND Tree NAND Tree
No. Pin No. Name Input No. Pin No. Name Input No. Pin No. Name
1 143 RST 25 16 IRDY 49 47 AD0
2 145 CLK 26 17 TRDY 50 79 CRS
3 147 GNT 27 18 DEVSEL 51 80 COL
4 148 REQ 28 19 STOP 52 81 TXD3
5 149 AD31 29 21 PERR 53 90 TXD2
6 151 AD30 30 22 SERR 54 91 TXD1
7 152 AD29 31 24 PAR 55 92 TXD0
8 153 AD28 32 25 C/BE1 56 94 TX_EN
9 154 AD27 33 26 AD15 57 95 TX_CLK
10 155 AD26 34 28 AD14 58 96 TX_ER
11 157 AD25 35 29 AD13 59 98 RX_ER
12 159 C/BE3 36 29 AD12 60 99 RX_CLK
13 160 AD24 37 31 AD11 61 100 RX_DV
14 1 IDSEL 38 32 AD10 62 102 RXD0
15 3 AD23 39 34 AD9 63 103 RXD1
16 4 AD22 40 35 AD8 64 104 RXD2
17 6 AD21 41 37 C/BE0 65 105 RXD3
18 7 AD20 42 38 AD7 66 106 SLEEP/EAR
19 9 AD19 43 39 AD6 67 108 MDIO
20 10 AD18 44 41 AD5 68 131 EEDO/LED3/SRD
21 12 AD17 45 42 AD4 69 132 EEDI/LED0
22 13 AD16 46 43 AD3 70 133 LED2/SRDCLK
23 14 C/BE2 47 44 AD2 71 134 EESK/LED1/SFBD
24 15 FRAME 48 46 AD1 72 136 EECS
Am79C971 101
Reset S_RESET terminates all network activity abruptly. The
host can use the suspend mode (SPND, CSR5, bit 0)
There are three different types of RESET operations
to terminate all network activity in an orderly sequence
that may be performed on the Am79C971 device,
before issuing an S_RESET.
H_RESET, S_RESET, and STOP. The following is a de-
scription of each type of RESET operation. STOP
H_RESET A STOP reset is generated by the assertion of the STOP
bit in CSR0. Writing a 1 to the STOP bit of CSR0, when
Hardware Reset (H_RESET) is an Am79C971 reset
the stop bit currently has a value of 0, will initiate a STOP
operation that has been created by the proper asser-
reset. If the STOP bit is already a 1, then writing a 1 to
tion of the RST pin of the Am79C971 device. When the
the STOP bit will not generate a STOP reset.
minimum pulse width timing as specified in the RST pin
description has been satisfied, then an internal reset STOP will reset all or some portions of CSR0, 3, and 4
operation will be performed. to default values. For the identity of individual CSRs and
bit locations that are affected by STOP, see the individ-
H_RESET will program most of the CSR and BCR reg-
ual CSR register descriptions. STOP will not affect any
isters to their default value. Note that there are several
of the BCR and PCI configuration space locations.
CSR and BCR registers that are undefined after
STOP will cause the microcode program to jump to its
H_RESET. See the sections on the individual registers
reset state. Following the end of the STOP operation,
for details.
the Am79C971 controller will not attempt to read the
H_RESET will clear all registers in the PCI configura- EEPROM device. Setting the STOP bit does not affect
tion space. H_RESET will cause the microcode pro- the T-MAU.
gram to jump to its reset state. Following the end of the
Note: STOP will not cause a deassertion of the REQ
H_RESET operation, the Am79C971 controller will at-
signal, if it happens to be active at the time of the write
tempt to read the EEPROM device through the EE-
to CSR0. The Am79C971 controller will wait until it
PROM interface. H_RESET resets the T-MAU into the
gains bus ownership and it will first finish all scheduled
Link Fail state.
bus master accesses before the STOP reset is exe-
H_RESET will clear DWIO (BCR18, bit 7) and the cuted.
Am79C971 controller will be in 16-bit I/O mode after STOP terminates all network activity abruptly. The host
the reset operation. A DWord write operation to the can use the suspend mode (SPND, CSR5, bit 0) to ter-
RDP (I/O offset 10h) must be performed to set the de- minate all network activity in an orderly sequence before
vice into 32-bit I/O mode. setting the STOP bit.
S_RESET
Software Access
Software Reset (S_RESET) is an Am79C971 reset op-
PCI Configuration Registers
eration that has been created by a read access to the
Reset register, which is located at offset 14h in Word The Am79C971 controller implements a 256-byte con-
I/O mode or offset 18h in DWord I/O mode from the figuration space as defined by the PCI specification
Am79C971 I/O or memory mapped I/O base address. revision 2.1. The 64-byte header includes all registers
required to identify the Am79C971 controller and its
S_RESET will reset all of or some portions of CSR0, 3, function. Additional registers are used to setup the con-
4, 15, 80, 100, and 124 to default values. For the iden- figuration of the Am79C971 controller in a system.
tity of individual CSRs and bit locations that are af- None of the device specific registers located at offsets
fected by S_RESET, see the individual CSR register 40h through FCh are implemented. The layout of the
descriptions. S_RESET will not affect any PCI configu- Am79C971 PCI configuration space is shown in Table
ration space location. S_RESET will not affect any of 19.
the BCR register values. S_RESET will cause the mi-
crocode program to jump to its reset state. Following The PCI configuration registers are accessible only by
the end of the S_RESET operation, the Am79C971 configuration cycles. All multi-byte numeric fields follow
controller will not attempt to read the EEPROM device. little endian byte ordering. All write accesses to Re-
S_RESET does not affect the status of the T-MAU. served locations have no effect; reads from these loca-
After S_RESET, the host must perform a full re-initial- tions will return a data value of 0.
ization of the Am79C971 controller before starting net-
work activity. S_RESET will cause REQ to deassert
immediately. STOP (CSR0, bit 2) or SPND (CSR5, bit
0) can be used to terminate any pending bus master-
ship request in an orderly sequence.
102 Am79C971
Table 19. PCI Configuration Space Layout
31 24 23 16 15 8 7 0 Offset
Device ID Vendor ID 00h
Status Command 04h
Base-Class Sub-Class Programming IF Revision ID 08h
Reserved Header Type Latency Timer Reserved 0Ch
I/O Base Address 10h
Memory Mapped I/O Base Address 14h
Reserved 18h
Reserved 1Ch
Reserved 20h
Reserved 24h
Reserved 28h
Subsystem ID Subsystem Vendor ID 2Ch
Expansion ROM Base Address 30h
Reserved 34h
Reserved 38h
MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3Ch
Reserved 40h
.
Reserved
.
Reserved FCh
I/O Resources (BCR) are used to configure the bus interface unit and
The Am79C971 controller requires 32 bytes of address the LEDs. Both sets of registers are accessed using in-
space for access to all the various internal registers as direct addressing.
well as to some setup information stored in an external The CSR and BCR share a common Register Address
serial EEPROM. A software reset port is available, too. Port (RAP). There are, however, separate data ports.
The Am79C971 controller supports mapping the ad- The Register Data Port (RDP) is used to access a
dress space to both I/O and memory space. The value CSR. The BCR Data Port (BDP) is used to access a
in the PCI I/O Base Address register determines the BCR.
start address of the I/O address space. The register is In order to access a particular CSR location, the RAP
typically programmed by the PCI configuration utility should first be written with the appropriate CSR ad-
after system power-up. The PCI configuration utility dress. The RDP will then point to the selected CSR. A
must also set the IOEN bit in the PCI Command regis- read of the RDP will yield the selected CSR data. A
ter to enable I/O accesses to the Am79C971 controller. write to the RDP will write to the selected CSR. In order
For memory mapped I/O access, the PCI Memory to access a particular BCR location, the RAP should
Mapped I/O Base Address register controls the start first be written with the appropriate BCR address. The
address of the memory space. The MEMEN bit in the BDP will then point to the selected BCR. A read of the
PCI Command register must also be set to enable the BDP will yield the selected BCR data. A write to the
mode. Both base address registers can be active at the BDP will write to the selected BCR.
same time.
Once the RAP has been written with a value, the RAP
The Am79C971 controller supports two modes for ac- value remains unchanged until another RAP write oc-
cessing the I/O resources. For backwards compatibility curs, or until an H_RESET or S_RESET occurs. RAP
with AMD’s 16-bit Ethernet controllers, Word I/O is the is cleared to all 0s when an H_RESET or S_RESET oc-
default mode after power up. The device can be config- curs. RAP is unaffected by setting the STOP bit.
ured to DWord I/O mode by software.
Address PROM Space
I/O Registers
The Am79C971 controller allows for connection of a
The Am79C971 controller registers are divided into two serial EEPROM. The first 16 bytes of the EEPROM will
groups. The Control and Status Registers (CSR) are be automatically loaded into the Address PROM
used to configure the Ethernet MAC engine and to ob- (APROM) space after H_RESET. The Address PROM
tain status information. The Bus Control Registers space is a convenient place to store the value of the 48-
Am79C971 103
bit IEEE station address. It can be overwritten by the gramming of the Am79C971 control registers. Table 20
host computer and its content has no effect on the op- shows legal I/O accesses in Word I/O mode.
eration of the controller. The software must copy the
station address from the Address PROM space to the
initialization block or to CSR12-14 in order for the re- Table 20. I/O Map In Word I/O Mode (DWIO = 0)
ceiver to accept unicast frames directed to this station. No. of
Offset Bytes Register
The six bytes of the IEEE station address occupy the
first six locations of the Address PROM space. The 00h - 0Fh 16 APROM
next six bytes are reserved. Bytes 12 and 13 should 10h 2 RDP
match the value of the checksum of bytes 1 through 11 12h 2 RAP (shared by RDP and BDP)
and 14 and 15. Bytes 14 and 15 should each be ASCII
14h 2 Reset Register
“W” (57h). The above requirements must be met in
order to be compatible with AMD driver software. 16h 2 BDP
APROMWE bit (BCR2, bit 8) must be set to 1 to enable 18h - 1Fh 8 Reserved
write access to the Address PROM space.
Double Word I/O Mode
Reset Register
After H_RESET, the Am79C971 controller is pro-
A read of the Reset register creates an internal soft- grammed to operate in Word I/O mode. DWIO (BCR18,
ware reset (S_RESET) pulse in the Am79C971 control- bit 7) will be cleared to 0. It will then be loaded by the
ler. The internal S_RESET pulse that is generated by value in the EEPROM. Table 20 shows how the 32
this access is different from both the assertion of the bytes of address space are used in Word I/O mode.
hardware RST pin (H_RESET) and from the assertion
of the software STOP bit. Specifically, S_RESET is the All I/O resources must be accessed in word quantities
equivalent of the assertion of the RST pin (H_RESET) and on word addresses. The Address PROM locations
except that S_RESET has no effect on the BCR or PCI can also be read in byte quantities. The only allowed
Configuration space locations or on the T-MAU. DWord operation is a write access to the RDP, which
switches the device to DWord I/O mode. A read access
The NE2100 LANCE-based family of Ethernet cards other than listed in the table below will yield undefined
requires that a write access to the Reset register fol- data, a write operation may cause unexpected repro-
lows each read access to the Reset register. The gramming of the Am79C971 control registers. Table 23
Am79C971 controller does not have a similar require- shows legal I/O accesses in Word I/O mode.
ment. The write access is not required and does not
have any effect.
Table 21. I/O Map In Word I/O Mode (DWIO = 0)
Note: The Am79C971 controller cannot service any
slave accesses for a very short time after a read access No. of
of the Reset register, because the internal S_RESET Offset Bytes Register
operation takes about 1 µs to finish. The Am79C971 00h - 0Fh 16 APROM
controller will terminate all slave accesses with the as- 10h 2 RDP
sertion of DEVSEL and STOP while TRDY is not as- 12h 2 RAP (shared by RDP and BDP)
serted, signaling to the initiator to disconnect and retry
14h 2 Reset Register
the access at a later time.
16h 2 BDP
Word I/O Mode
18h - 1Fh 8 Reserved
After H_RESET, the Am79C971 controller is pro-
grammed to operate in Word I/O mode. DWIO (BCR18, Double Word I/O Mode
bit 7) will be cleared to 0. It will then be loaded by the
The Am79C971 controller can be configured to operate
value in the EEPROM. Table 20 shows how the 32
in DWord (32-bit) I/O mode. The software can invoke
bytes of address space are used in Word I/O mode.
the DWIO mode by performing a DWord write access
All I/O resources must be accessed in word quantities to the I/O location at offset 10h (RDP). The data of the
and on word addresses. The Address PROM locations write access must be such that it does not affect the in-
can also be read in byte quantities. The only allowed tended operation of the Am79C971 controller. Setting
DWord operation is a write access to the RDP, which the device into 32-bit I/O mode is usually the first oper-
switches the device to DWord I/O mode. A read access ation after H_RESET or S_RESET. The RAP register
other than listed in the table below will yield undefined will point to CSR0 at that time. Writing a value of 0 to
data, a write operation may cause unexpected repro- CSR0 is a safe operation. DWIO (BCR18, bit 7) will be
set to 1 as an indication that the Am79C971 controller
operates in 32-bit I/O mode.
104 Am79C971
The DWIO mode can be configured from the EEPROM .
or programmed by the software. Table 22. I/O Map In Word I/O Mode (DWIO = 0)
Note: Even though the I/O resource mapping changes No. of
when the I/O mode setting changes, the RDP location Offset Bytes Register
offset is the same for both modes. Once the DWIO bit 00h - 0Fh 16 APROM
has been set to 1, only H_RESET or a read of
10h 2 RDP
EEPROM can clear it to 0. The DWIO mode setting is
unaffected by setting the STOP bit. Table 24 shows 12h 2 RAP (shared by RDP and BDP)
how the 32 bytes of address space are used in DWord 14h 2 Reset Register
I/O mode. 16h 2 BDP
All I/O resources must be accessed in DWord quanti- 18h - 1Fh 8 Reserved
ties and on DWord addresses. A read access other
than listed in Table 25 will yield undefined data, a write Double Word I/O Mode
operation may cause unexpected reprogramming of The Am79C971 controller can be configured to operate
the Am79C971 control registers in DWord (32-bit) I/O mode. The software can invoke
After H_RESET, the Am79C971 controller is pro- the DWIO mode by performing a DWord write access
grammed to operate in Word I/O mode. DWIO (BCR18, to the I/O location at offset 10h (RDP). The data of the
bit 7) will be cleared to 0. It will then be loaded by the write access must be such that it does not affect the in-
value in the EEPROM. Table 20 shows how the 32 tended operation of the Am79C971 controller. Setting
bytes of address space are used in Word I/O mode. the device into 32-bit I/O mode is usually the first oper-
ation after H_RESET or S_RESET. The RAP register
All I/O resources must be accessed in word quantities will point to CSR0 at that time. Writing a value of 0 to
and on word addresses. The Address PROM locations CSR0 is a safe operation. DWIO (BCR18, bit 7) will be
can also be read in byte quantities. The only allowed set to 1 as an indication that the Am79C971 controller
DWord operation is a write access to the RDP, which operates in 32-bit I/O mode.
switches the device to DWord I/O mode. A read access
other than listed in the table below will yield undefined The DWIO mode can be configured from the EEPROM
data, a write operation may cause unexpected repro- or programmed by the software.
gramming of the Am79C971 control registers. Table 23 Note: Even though the I/O resource mapping changes
shows legal I/O accesses in Word I/O mode when the I/O mode setting changes, the RDP location
offset is the same for both modes. Once the DWIO bit
has been set to 1, only H_RESET or a read of
EEPROM can clear it to 0. The DWIO mode setting is
unaffected by setting the STOP bit. Table 24 shows
how the 32 bytes of address space are used in DWord
I/O mode.
All I/O resources must be accessed in DWord quanti-
ties and on DWord addresses. A read access other
than listed in Table 25 will yield undefined data, a write
operation may cause unexpected reprogramming of
the Am79C971 control registers
Am79C971 105
Table 23. Legal I/O Accesses in Word I/O Mode (DWIO = 0)
AD[4:0] BE[3:0] Type Comment
0XX00 1110 RD Byte read of APROM location 0h, 4h, 8h or Ch
0XX01 1101 RD Byte read of APROM location 1h, 5h, 9h or Dh
0XX10 1011 RD Byte read of APROM location 2h, 6h, Ah or Eh
0XX11 0111 RD Byte read of APROM location 3h, 7h, Bh or Fh
Word read of APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or
0XX00 1100 RD
Ch and Dh
Word read of APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or
0XX10 0011 RD
Fh and Eh
10000 1100 RD Word read of RDP
10010 0011 RD Word read of RAP
10100 1100 RD Word read of Reset Register
10110 0011 RD Word read of BDP
Word write to APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or
0XX00 1100 WR
Ch and Dh
Word write to APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or
0XX10 0011 WR
Fh and Eh
10000 1100 WR Word write to RDP
10010 0011 WR Word write to RAP
10100 1100 WR Word write to Reset Register
10110 0011 WR Word write to BDP
DWord write to RDP,
10000 0000 WR
switches device to DWord I/O mode
Table 24. I/O Map In DWord I/O Mode (DWIO = 1) USER ACCESSIBLE REGISTERS
Offset No. of Bytes Register The Am79C971 controller has three types of user reg-
00h - 0Fh 16 APROM isters: the PCI configuration registers, the Control and
10h 4 RDP Status registers (CSR), and the Bus Control registers
(BCR).
RAP (shared by RDP and
14h 4
BDP) The Am79C971 controller implements all PCnet-ISA
18h 4 Reset Register (Am79C960) registers, all C-LANCE (Am79C90) regis-
1Ch 4 BDP ters, plus a number of additional registers. The
Am79C971 controller CSRs are compatible upon
Table 25. Legal I/O Accesses in Double Word I/O power up with both the PCnet-ISA CSRs and all of the
Mode (DWIO =1) C-LANCE CSRs.
AD[4:0] BE[3:0] Type Comment The PCI configuration registers can be accessed in any
DWord read of APROM data width. All other registers must be accessed ac-
0XX00 0000 RD locations 3h (MSB) to 0h (LSB), cording to the I/O mode that is currently selected.
7h to 4h, Bh to 8h or Fh to Ch When WIO mode is selected, all other register loca-
10000 0000 RD DWord read of RDP tions are defined to be 16 bits in width. When DWIO
10100 0000 RD DWord read of RAP mode is selected, all these register locations are de-
11000 0000 RD DWord read of Reset Register fined to be 32 bits in width, with the upper 16 bits of
11100 0000 RD DWord read of BDP most register locations marked as reserved locations
DWord write to APROM with undefined values. When performing register write
0XX00 0000 WR locations 3h (MSB) to 0h (LSB), operations in DWIO mode, the upper 16 bits should al-
7h to 4h, Bh to 8h or Fh to Ch ways be written as zeros. When performing register
10000 0000 WR DWord write to RDP read operations in DWIO mode, the upper 16 bits of I/
10100 0000 WR DWord write to RAP O resources should always be regarded as having un-
11000 0000 WR DWord write to Reset Register defined values, except for CSR88.
11100 0000 WR DWord write of BDP The Am79C971 registers can be divided into four
groups: PCI Configuration, Setup, Running, and Test.
Registers not included in any of these categories can
be assumed to be intended for diagnostic purposes.
106 Am79C971
■ PCI Configuration Registers CSR13*^ Physical Address[31:16]
These registers are intended to be initialized by the CSR14*^ Physical Address[47:32]
system initialization procedure (e.g., BIOS device ini-
tialization routine) to program the operation of the CSR15* Mode
Am79C971 controller PCI bus interface. CSR24* Base Address of Receive Ring Lower
The following is a list of the registers that would typi- CSR25* Base Address of Receive Ring Upper
cally need to be programmed once during the initializa-
tion of the Am79C971 controller within a system: CSR30* Base Address of Transmit Ring Lower
— PCI I/O Base Address or Memory Mapped I/O CSR31* Base Address of Transmit Ring Upper
Base Address register CSR47* Transmit Polling Interval
— PCI Expansion ROM Base Address register CSR49* Receive Polling Interval
— PCI Interrupt Line register
CSR76* Receive Ring Length
— PCI Latency Timer register
CSR78* Transmit Ring Length
— PCI Status register
CSR80 DMA Transfer Counter and FIFO
— PCI Command register
Threshold Control
■ Setup Registers
CSR82 Bus Activity Timer
These registers are intended to be initialized by the de-
vice driver to program the operation of various CSR100 Memory Error Timeout
Am79C971 controller features. CSR122 Receiver Packet Alignment Control
The following is a list of the registers that would typi- CSR125^ MAC Enhanced Configuration Control
cally need to be programmed once during the setup of
the Am79C971 controller within a system. The control BCR2^ Miscellaneous Configuration
bits in each of these registers typically do not need to BCR4^ LED0 Status
be modified once they have been written. However,
there are no restrictions as to how many times these BCR5^ LED1 Status
registers may actually be accessed. Note that if the de- BCR6^ LED2 Status
fault power up values of any of these registers is ac-
ceptable to the application, then such registers need BCR7^ LED3 Status
never be accessed at all. BCR9^ Full-Duplex Control
Note: Registers marked with “^” may be programma- BCR18^ Bus and Burst Control
ble through the EEPROM read operation and, there-
fore, do not necessarily need to be written to by the BCR19 EEPROM Control and Status
system initialization procedure or by the driver soft- BCR20 Software Style
ware. Registers marked with “*” will be initialized by the
initialization block read operation. BCR22^ PCI Latency
CSR1 Initialization Block Address[15:0] BCR23^ PCI Subsystem Vendor ID
CSR2* Initialization Block Address[31:16] BCR24^ PCI Subsystem ID
CSR3 Interrupt Masks and Deferral Control BCR25^ SRAM Size
CSR4 Test and Features Control BCR26^ SRAM Boundary
CSR5 Extended Control and Interrupt BCR27^ SRAM Interface Control
CSR7 Extended Control and Interrupt2 BCR32^ MII Control and Status
CSR8* Logical Address Filter[15:0] BCR33^ MII Address
CSR9* Logical Address Filter[31:16] BCR35^ PCI Vendor ID
CSR10* Logical Address Filter[47:32] ■ Running Registers
CSR11* Logical Address Filter[63:48] These registers are intended to be used by the device
driver software after the Am79C971 controller is running
CSR12*^ Physical Address[15:0] to access status information and to pass control infor-
mation.
Am79C971 107
The following is a list of the registers that would typically PCI Command Register
need to be periodically read and perhaps written during Offset 04h
the normal running operation of the Am79C971 control-
ler within a system. Each of these registers contains The PCI Command register is a 16-bit register used to
control bits, or status bits, or both. control the gross functionality of the Am79C971 con-
troller. It controls the Am79C971 controller's ability to
RAP Register Address Port generate and respond to PCI bus cycles. To logically
CSR0 Am79C971 Controller Status disconnect the Am79C971 device from all PCI bus cy-
cles except configuration cycles, a value of 0 should be
CSR3 Interrupt Masks and Deferral Control written to this register.
CSR4 Test and Features Control The PCI Command register is located at offset 04h in
CSR5 Extended Control and Interrupt the PCI Configuration Space. It is read and written by
the host.
CSR7 Extended Control and Interrupt2
Bit Name Description
CSR112 Missed Frame Count
CSR114 PCI Status register 15-10 RES Reserved locations. Read as ze-
ros; write operations have no ef-
The following registers are only necessary if an exter- fect.
nal PHY device is being used and accessed.
9 FBTBEN Fast Back-to-Back Enable. Read
BCR32 MII Control and Status
as zero; write operations have no
BCR33 MII Address effect. The Am79C971 controller
will not generate Fast Back-to-
BCR34 MII Management Data
Back cycles.
■ Test Registers
8 SERREN SERR Enable. Controls the as-
These registers are intended to be used only for testing
sertion of the SERR pin. SERR is
and diagnostic purposes. Those registers not included
disabled when SERREN is
in any of the above lists can be assumed to be intended
cleared. SERR will be asserted
for diagnostic purposes.
on detection of an address parity
PCI Configuration Registers error and if both SERREN and
PERREN (bit 6 of this register)
PCI Vendor ID Register
are set.
Offset 00h
The PCI Vendor ID register is a 16-bit register that iden- SERREN is cleared by
tifies the manufacturer of the Am79C971 controller. H_RESET and is not effected by
AMD’s Vendor ID is 1022h. Note that this vendor ID is S_RESET or by setting the STOP
not the same as the Manufacturer ID in CSR88 and bit.
CSR89. The vendor ID is assigned by the PCI Special
7 RES Reserved location. Read as ze-
Interest Group.
ros; write operations have no ef-
The PCI Vendor ID register is located at offset 00h in fect.
the PCI Configuration Space. It is read only.
6 PERREN Parity Error Response Enable.
PCI Device ID Register Enables the parity error response
Offset 02h functions. When PERREN is 0
The PCI Device ID register is a 16-bit register that and the Am79C971 controller de-
uniquely identifies the Am79C971 controller within tects a parity error, it only sets the
AMD's product line. The Am79C971 Device ID is Detected Parity Error bit in the
2000h. Note that this Device ID is not the same as the PCI Status register. When PER-
Part number in CSR88 and CSR89. The Device ID is REN is 1, the Am79C971 control-
assigned by AMD. The Device ID is the same as the ler asserts PERR on the
PCnet-PCI II (Am79C970A) device. detection of a data parity error. It
also sets the DATAPERR bit (PCI
The PCI Device ID register is located at offset 02h in Status register, bit 8), when the
the PCI Configuration Space. It is read only. data parity error occurred during
This register is the same as BCR35 and can be written a master cycle. PERREN also
by the EEPROM. enables reporting address parity
108 Am79C971
errors through the SERR pin and when both ROMEN (PCI Expan-
the SERR bit in the PCI Status sion ROM Base Address register,
register. bit 0) and MEMEN are set to 1.
Since MEMEN also enables the
PERREN is cleared by memory mapped access to the
H_RESET and is not effected by Am79C971 I/O resources, the
S_RESET or by setting the STOP PCI Memory Mapped I/O Base
bit. Address register must be pro-
grammed with an address so that
5 VGASNOOPVGA Palette Snoop. Read as ze- the device does not claim cycles
ro; write operations have no ef- not intended for it.
fect.
MEMEN is cleared by H_RESET
4 MWIEN Memory Write and Invalidate Cy- and is not effected by S_RESET
cle Enable. Read as zero; write or by setting the STOP bit.
operations have no effect. The
Am79C971 controller only gener- 0 IOEN I/O Space Access Enable. The
ates Memory Write cycles. Am79C971 controller will ignore
all I/O accesses when IOEN is
3 SCYCEN Special Cycle Enable. Read as cleared. The host must set IOEN
zero; write operations have no ef- before the first I/O access to the
fect. The Am79C971 controller device. The PCI I/O Base Ad-
ignores all Special Cycle opera- dress register must be pro-
tions. grammed with a valid I/O address
before setting IOEN.
2 BMEN Bus Master Enable. Setting
BMEN enables the Am79C971 IOEN is cleared by H_RESET
controller to become a bus mas- and is not effected by S_RESET
ter on the PCI bus. The host must or by setting the STOP bit.
set BMEN before setting the INIT
or STRT bit in CSR0 of the PCI Status Register
Am79C971 controller.
Offset 06h
BMEN is cleared by H_RESET The PCI Status register is a 16-bit register that contains
and is not effected by S_RESET status information for the PCI bus related events. It is
or by setting the STOP bit. located at offset 06h in the PCI Configuration Space.
1 MEMEN Memory Space Access Enable. Bit Name Description

The Am79C971 controller will ig-
nore all memory accesses when 15 PERR Parity Error. PERR is set when
MEMEN is cleared. The host the Am79C971 controller detects
must set MEMEN before the first a parity error.
memory access to the device.
The Am79C971 controller sam-
For memory mapped I/O, the ples the AD[31:0], C/BE[3:0], and
host must program the PCI Mem- the PAR lines for a parity error at
ory Mapped I/O Base Address the following times:
register with a valid memory ad-
• In slave mode, during the ad-
dress before setting MEMEN.
dress phase of any PCI bus com-
For accesses to the Expansion mand.
ROM, the host must program the
• In slave mode, for all I/O, mem-
PCI Expansion ROM Base Ad-
ory and configuration write com-
dress register at offset 30h with a
mands that select the Am79C971
valid memory address before set-
controller when data is trans-
ting MEMEN. The Am79C971
ferred (TRDY and IRDY are as-
controller will only respond to ac-
serted).
cesses to the Expansion ROM
Am79C971 109
• In master mode, during the data cleared by writing a 1. Writing a 0
phase of all memory read com- has no effect. RTABORT is
mands. cleared by H_RESET and is not
affected by S_RESET or by set-
In master mode, during the data ting the STOP bit.
phase of the memory write com-
mand, the Am79C971 controller 11 STABORT Send Target Abort. Read as ze-
sets the PERR bit if the target re- ro; write operations have no ef-
ports a data parity error by as- fect. The Am79C971 controller
serting the PERR signal. will never terminate a slave ac-
cess with a target abort se-
PERR is not effected by the state quence.
of the Parity Error Response en-
able bit (PCI Command register, STABORT is read only.
bit 6).
10-9 DEVSEL Device Select Timing. DEVSEL
PERR is set by the Am79C971 is set to 01b (medium), which
controller and cleared by writing a means that the Am79C971 con-
1. Writing a 0 has no effect. troller will assert DEVSEL two
PERR is cleared by H_RESET clock periods after FRAME is as-
and is not affected by S_RESET serted.
or by setting the STOP bit.
DEVSEL is read only.
14 SERR Signaled SERR. SERR is set
when the Am79C971 controller 8 DATAPERR Data Parity Error Detected.
detects an address parity error DATAPERR is set when the
and both SERREN and PERREN Am79C971 controller is the cur-
(PCI Command register, bits 8 rent bus master and it detects a
and 6) are set. data parity error and the Parity
Error Response enable bit (PCI
SERR is set by the Am79C971 Command register, bit 6) is set.
controller and cleared by writing a
1. Writing a 0 has no effect. During the data phase of all
SERR is cleared by H_RESET memory read commands, the
and is not affected by S_RESET Am79C971 controller checks for
or by setting the STOP bit. parity error by sampling the
AD[31:0] and C/BE[3:0] and the
13 RMABORT Received Master Abort. RM- PAR lines. During the data phase
ABORT is set when the of all memory write commands,
Am79C971 controller terminates the Am79C971 controller checks
a master cycle with a master the PERR input to detect whether
abort sequence. the target has reported a parity
error.
RMABORT is set by the
Am79C971 controller and DATAPERR is set by the
cleared by writing a 1. Writing a 0 Am79C971 controller and
has no effect. RMABORT is cleared by writing a 1. Writing a 0
cleared by H_RESET and is not has no effect. DATAPERR is
affected by S_RESET or by set- cleared by H_RESET and is not
ting the STOP bit. affected by S_RESET or by set-
ting the STOP bit.
12 RTABORT Received Target Abort. RT-
ABORT is set when a target ter- 7 FBTBC Fast Back-To-Back Capable.
minates an Am79C971 master Read as one; write operations
cycle with a target abort se- have no effect. The Am79C971
quence. controller is capable of accepting
fast back-to-back transactions
RTABORT is set by the with the first transaction address-
Am79C971 controller and ing a different target.
110 Am79C971
6-0 RES Reserved locations. Read as ze- will continue with its data transfers. It will only release
ro; write operations have no ef- the bus when the counter has reached 0.
fect.
The PCI Latency Timer is only significant in burst trans-
PCI Revision ID Register actions, where FRAME stays asserted until the last
data phase. In a non-burst transaction, FRAME is only
Offset 08h asserted during the address phase. The internal la-
The PCI Revision ID register is an 8-bit register that tency counter will be cleared and suspended while
specifies the Am79C971 controller revision number. FRAME is deasserted.
The value of this register is 2Xh, with the lower four bits
All eight bits of the PCI Latency Timer register are pro-
being silicon-revision dependent. The initial revision
grammable. The host should read the Am79C971 PCI
value will be 21h.
MIN_GNT and PCI MAX_LAT registers to determine
The PCI Revision ID register is located at offset 08h in the latency requirements for the device and then initial-
the PCI Configuration Space. It is read only. ize the Latency Timer register with an appropriate
value.
PCI Programming Interface Register
Offset 09h The PCI Latency Timer register is located at offset 0Dh
in the PCI Configuration Space. It is read and written by
The PCI Programming Interface register is an 8-bit reg- the host. The PCI Latency Timer register is cleared by
ister that identifies the programming interface of H_RESET and is not effected by S_RESET or by set-
Am79C971 controller. PCI does not define any specific ting the STOP bit.
register-level programming interfaces for network de-
vices. The value of this register is 00h. PCI Header Type Register
The PCI Programming Interface register is located at Offset 0Eh

offset 09h in the PCI Configuration Space. It is read The PCI Header Type register is an 8-bit register that
only. describes the format of the PCI Configuration Space lo-
cations 10h to 3Ch and that identifies a device to be
PCI Sub-Class Register
single or multi-function. The PCI Header Type register
Offset 0Ah is located at address 0Eh in the PCI Configuration
The PCI Sub-Class register is an 8-bit register that Space. It is read only.
identifies specifically the function of the Am79C971 Bit Name Description
controller. The value of this register is 00h which iden- 7 FUNCT Single-function/multi-function de-
tifies the Am79C971 device as an Ethernet controller. vice. Read as zero; write opera-
The PCI Sub-Class register is located at offset 0Ah in tions have no effect. The
the PCI Configuration Space. It is read only. Am79C971 controller is a single
function device.
PCI Base-Class Register
Offset 0Bh 6-0 LAYOUT PCI configuration space layout.
Read as zeros; write operations
The PCI Base-Class register is an 8-bit register that
have no effect. The layout of the
broadly classifies the function of the Am79C971 con-
PCI configuration space loca-
troller. The value of this register is 02h which classifies
tions 10h to 3Ch is as shown in
the Am79C971 device as a network controller.
the table at the beginning of this
The PCI Base-Class register is located at offset 0Bh in section.
the PCI Configuration Space. It is read only.
PCI I/O Base Address Register
PCI Latency Timer Register
Offset 10h
Offset 0Dh
The PCI I/O Base Address register is a 32-bit register
The PCI Latency Timer register is an 8-bit register that that determines the location of the Am79C971 I/O re-
specifies the minimum guaranteed time the Am79C971 sources in all of I/O space. It is located at offset 10h in
controller will control the bus once it starts its bus mas- the PCI Configuration Space.
tership period. The time is measured in clock cycles.
Every time the Am79C971 controller asserts FRAME Bit Name Description
at the beginning of a bus mastership period, it will copy
the value of the PCI Latency Timer register into a 31-5 IOBASE I/O base address most significant
counter and start counting down. The counter will 27 bits. These bits are written by
freeze at 0. When the system arbiter removes GNT the host to specify the location of
while the counter is non-zero, the Am79C971 controller the Am79C971 I/O resources in
Am79C971 111
all of I/O space. IOBASE must be Am79C971 I/O resources in all of
written with a valid address be- memory space. MEMBASE must
fore the Am79C971 controller be written with a valid address
slave I/O mode is turned on by before the Am79C971 controller
setting the IOEN bit (PCI Com- slave memory mapped I/O mode
mand register, bit 0). is turned on by setting the ME-
MEN bit (PCI Command register,
When the Am79C971 controller bit 1).
is enabled for I/O mode (IOEN is
set), it monitors the PCI bus for a When the Am79C971 controller
valid I/O command. If the value is enabled for memory mapped
on AD[31:5] during the address I/O mode (MEMEN is set), it mon-
phase of the cycles matches the itors the PCI bus for a valid mem-
value of IOBASE, the Am79C971 ory command. If the value on
controller will drive DEVSEL indi- AD[31:5] during the address
cating it will respond to the ac- phase of the cycles matches the
cess. value of MEMBASE, the
Am79C971 controller will drive
IOBASE is read and written by DEVSEL indicating it will respond
the host. IOBASE is cleared by to the access.
H_RESET and is not affected by
S_RESET or by setting the STOP MEMBASE is read and written by
bit. the host. MEMBASE is cleared
by H_RESET and is not affected
4-2 IOSIZE I/O size requirements. Read as by S_RESET or by setting the
zeros; write operations have no STOP bit.
effect.
4 MEMSIZE Memory mapped I/O size re-
IOSIZE indicates the size of the quirements. Read as zeros; write
I/O space the Am79C971 control- operations have no effect.
ler requires. When the host writes
a value of FFFF FFFFh to the I/O MEMSIZE indicates the size of
Base Address register, it will read the memory space the
back a value of 0 in bits 4-2. That Am79C971 controller requires.
indicates an Am79C971 I/O When the host writes a value of
space requirement of 32 bytes. FFFF FFFFh to the Memory
Mapped I/O Base Address regis-
1 RES Reserved location. Read as zero; ter, it will read back a value of 0 in
write operations have no effect. bit 4. That indicates a Am79C971
memory space requirement of 32
0 IOSPACE I/O space indicator. Read as one; bytes.
write operations have no effect.
Indicating that this base address 3 PREFETCH Prefetchable. Read as zero; write
register describes an I/O base operations have no effect. Indi-
address. cates that memory space con-
trolled by this base address
PCI Memory Mapped I/O Base Address Register register is not prefetchable. Data
Offset 14h in the memory mapped I/O space
The PCI Memory Mapped I/O Base Address register is cannot be prefetched. Because
a 32-bit register that determines the location of the one of the I/O resources in this
Am79C971 I/O resources in all of memory space. It is address space is a Reset regis-
located at offset 14h in the PCI Configuration Space. ter, the order of the read access-
es is important.
2-1 TYPE Memory type indicator. Read as
31-5 MEMBASE Memory mapped I/O base ad- zeros; write operations have no
dress most significant 27 bits. effect. Indicates that this base ad-
These bits are written by the host dress register is 32 bits wide and
to specify the location of the
112 Am79C971
mapping can be done anywhere MEMEN (PCI Command register,
in the 32-bit memory space. bit 1).
0 MEMSPACE Memory space indicator. Read Since the 12 most significant bits
as zero; write operations have no of the base address are program-
effect. Indicates that this base ad- mable, the host can map the Ex-
dress register describes a memo- pansion ROM on any 1M
ry base address. boundary.
PCI Subsystem Vendor ID Register When the Am79C971 controller

Offset 2Ch is enabled for Expansion ROM
access (ROMEN and MEMEN
The PCI Subsystem Vendor ID register is a 16-bit reg- are set to 1), it monitors the PCI
ister that together with the PCI Subsystem ID uniquely bus for a valid memory com-
identifies the add-in card or subsystem the Am79C971 mand. If the value on AD[31:2]
controller is used in. Subsystem Vendor IDs can be ob- during the address phase of the
tained from the PCI SIG. A value of 0 (the default) indi- cycle falls between ROMBASE
cates that the Am79C971 controller does not support and ROMBASE + 1M - 4, the
subsystem identification. The PCI Subsystem Vendor Am79C971 controller will drive
ID is an alias of BCR23, bits 15-0. It is programmable DEVSEL indicating it will respond
through the EEPROM. to the access.
The PCI Subsystem Vendor ID register is located at off-
set 2Ch in the PCI Configuration Space. It is read only. ROMBASE is read and written by
the host. ROMBASE is cleared
PCI Subsystem ID Register by H_RESET and is not affected
Offset 2Eh by S_RESET or by setting the
STOP bit.
The PCI Subsystem ID register is a 16-bit register that
together with the PCI Subsystem Vendor ID uniquely 19-1 ROMSIZE ROM size. Read as zeros; write
identifies the add-in card or subsystem the Am79C971 operation have no effect. ROM-
controller is used in. The value of the Subsystem ID is SIZE indicates the maximum size
up to the system vendor. A value of 0 (the default) indi- of the Expansion ROM the
cates that the Am79C971 controller does not support Am79C971 controller can sup-
subsystem identification. The PCI Subsystem ID is an port. The host can determine the
alias of BCR24, bits 15-0. It is programmable through Expansion ROM size by writing
the EEPROM. FFFF FFFFh to the Expansion
The PCI Subsystem ID register is located at offset 2Eh ROM Base Address register. It
in the PCI Configuration Space. It is read only. will read back a value of 0 in bit
19-1, indicating an Expansion
PCI Expansion ROM Base Address Register ROM size of 1M.
Offset 30h
Note that ROMSIZE only speci-
The PCI Expansion ROM Base Address register is a
fies the maximum size of Expan-
32-bit register that defines the base address, size and
sion ROM the Am79C971
address alignment of an Expansion ROM. It is located
controller supports. A smaller
at offset 30h in the PCI Configuration Space.
ROM can be used, too. The actu-
Bit Name Description al size of the code in the Expan-
sion ROM is always determined
31-20 ROMBASE Expansion ROM base address by reading the Expansion ROM
most significant 12 bits. These header.
bits are written by the host to
specify the location of the Expan- 0 ROMEN Expansion ROM Enable. Written
sion ROM in all of memory space. by the host to enable access to
ROMBASE must be written with a the Expansion ROM. The
valid address before the Am79C971 controller will only re-
Am79C971 Expansion ROM ac- spond to accesses to the Expan-
cess is enabled by setting sion ROM when both ROMEN
ROMEN (PCI Expansion ROM and MEMEN (PCI Command reg-
Base Address register, bit 0) and ister, bit 1) are set to 1.
Am79C971 113
ROMEN is read and written by PCI MAX_LAT Register
the host. ROMEN is cleared by Offset 3Fh
H_RESET and is not effected by
S_RESET or by setting the STOP The PCI MAX_LAT register is an 8-bit register that
bit. specifies the maximum arbitration latency the
Am79C971 controller can sustain without causing
PCI Interrupt Line Register problems to the network activity. The register value
specifies the time in units of 1/4 µs. The MAX_LAT reg-
Offset 3Ch
ister is an alias of BCR22, bits 15-8. It is recommended
The PCI Interrupt Line register is an 8-bit register that that BCR22 be programmed to the value of 1818H.
is used to communicate the routing of the interrupt.
This register is written by the POST software as it ini- The host should use the value in this register to deter-
tializes the Am79C971 controller in the system. The mine the setting of the PCI Latency Timer register.
register is read by the network driver to determine the The PCI MAX_LAT register is located at offset 3Fh in
interrupt channel which the POST software has as- the PCI Configuration Space. It is read only.
signed to the Am79C971 controller. The PCI Interrupt
Line register is not modified by the Am79C971 control- RAP Register
ler. It has no effect on the operation of the device. The RAP (Register Address Pointer) register is used to
The PCI Interrupt Line register is located at offset 3Ch gain access to CSR and BCR registers on board the
in the PCI Configuration Space. It is read and written by Am79C971 controller. The RAP contains the address
the host. It is cleared by H_RESET and is not affected of a CSR or BCR.
S_RESET or by setting the STOP bit. As an example of RAP use, consider a read access to
PCI Interrupt Pin Register CSR4. In order to access this register, it is necessary
to first load the value 0004h into the RAP by performing
Offset 3Dh a write access to the RAP offset of 12h (12h when WIO
This PCI Interrupt Pin register is an 8-bit register that mode has been selected, 14h when DWIO mode has
indicates the interrupt pin that the Am79C971 controller been selected). Then a second access is performed,
is using. The value for the Am79C971 Interrupt Pin reg- this time to the RDP offset of 10h (for either WIO or
ister is 01h, which corresponds to INTA. DWIO mode). The RDP access is a read access, and
since RAP has just been loaded with the value of
The PCI Interrupt Pin register is located at offset 3Dh
0004h, the RDP read will yield the contents of CSR4. A
in the PCI Configuration Space. It is read only.
read of the BDP at this time (offset of 16h when WIO
PCI MIN_GNT Register mode has been selected, 1Ch when DWIO mode has
Offset 3Eh been selected) will yield the contents of BCR4, since
the RAP is used as the pointer into both BDP and RDP
The PCI MIN_GNT register is an 8-bit register that space.
specifies the minimum length of a burst period that the
Am79C971 needs to keep up with the network activity. RAP: Register Address Port
The length of the burst period is calculated assuming a Bit Name Description
clock rate of 33 MHz. The register value specifies the
time in units of 1/4 µs. The PCI MIN_GNT register is an 31-16 RES Reserved locations. Written as
alias of BCR22, bits 7-0. The default value for zeros and read as undefined.
MIN_GNT is 06h, which corresponds to a minimum
grant of 1.5 µ s and which is the time it takes the 15-8 RES Reserved locations. Read and
Am79C971 controller to read/write half of the FIFO. (16 written as zeros.
DWord transfers in burst mode with one extra wait state
per data phase inserted by the target.) Note that the 7-0 RAP Register Address Port. The value
default is only a typical value. This calculation also of these 8 bits determines which
does not take into account any descriptor accesses. CSR or BCR will be accessed
when an I/O access to the RDP
The host should use the value in this register to deter- or BDP port, respectively, is per-
mine the setting of the PCI Latency Timer register. formed.
The PCI MIN_GNT register is located at offset 3Eh in
the PCI Configuration Space. It is read only. A write access to undefined CSR
or BCR locations may cause un-
expected reprogramming of the
Am79C971 control registers. A
114 Am79C971
read access will yield undefined H_RESET, S_RESET, or by set-
values. ting the STOP bit.
Read/Write accessible always. 13 CERR Collision Error is set by the

RAP is cleared by H_RESET or Am79C971 controller when the
S_RESET and is unaffected by device operates in half-duplex
setting the STOP bit. mode and the collision inputs to
the AUI or to the GPSI port failed
Control and Status Registers to activate within 20 network bit
The CSR space is accessible by performing accesses times after the chip terminated
to the RDP (Register Data Port). The particular CSR transmission (SQE Test). This
that is read or written during an RDP access will de- feature is a transceiver test fea-
pend upon the current setting of the RAP. RAP serves ture. CERR reporting is disabled
as a pointer into the CSR space. when the AUI or the GPSI port is
active and the Am79C971 con-
CSR0: Am79C971 Controller Status and Control troller operates in full-duplex
Register mode.
Certain bits in CSR0 indicate the cause of an interrupt.
The register is designed so that these indicator bits are When the 10BASE-T port is se-
cleared by writing ones to those bit locations. This lected, for both half-duplex and
means that the software can read CSR0 and write back full-duplex operation, CERR will
the value just read to clear the interrupt condition. be set after a transmission if the
T-MAU is in Link Fail state.
When the MII port is selected,

CERR is only reported when the
external PHY is operating as a
31-16 RES Reserved locations. Written as
10BASE-T PHY and if the exter-
zeros and read as undefined.
nal T-MAU is in Link Fail state.
15 ERR Error is set by the OR of BABL,
CERR assertion will not result in
CERR, MISS, and MERR. ERR
an interrupt being generated.
remains set as long as any of the
CERR assertion will set the ERR
error flags are true.
bit.
Read accessible always. ERR is
Read/Write accessible always.
read only. Write operations are
CERR is cleared by the host by
ignored.
writing a 1. Writing a 0 has no ef-
14 BABL Babble is a transmitter time-out fect. CERR is cleared by
error. BABL is set by the H_RESET, S_RESET, or by set-
Am79C971 controller when the ting the STOP bit.
transmitter has been on the chan-
12 MISS Missed Frame is set by the
nel longer than the time required
Am79C971 controller when it has
to send the maximum length
lost an incoming receive frame
frame. BABL will be set if 1519
resulting from a Receive Descrip-
bytes or greater are transmitted.
tor not being available. This bit is
When BABL is set, INTA is as- the only immediate indication that
serted if IENA is 1 and the mask receive data has been lost since
bit BABLM (CSR3, bit 14) is 0. there is no current receive de-
BABL assertion will set the ERR scriptor. The Missed Frame
bit, regardless of the settings of Counter (CSR112) also incre-
IENA and BABLM. ments each time a receive frame
is missed.
BABL is cleared by the host by When MISS is set, INTA is as-
writing a 1. Writing a 0 has no ef- serted if IENA is 1 and the mask
fect. BABL is cleared by bit MISSM (CSR3, bit 12) is 0.
MISS assertion will set the ERR
Am79C971 115
bit, regardless of the settings of 9 TINT Transmit Interrupt is set by the
IENA and MISSM. Am79C971 controller after the
OWN bit in the last descriptor of a
Read/Write accessible always. transmit frame has been cleared
MISS is cleared by the host by to indicate the frame has been
writing a 1. Writing a 0 has no ef- sent or an error occurred in the
fect. MISS is cleared by transmission.
H_RESET, S_RESET, or by set-
ting the STOP bit. When TINT is set, INTA is assert-
ed if IENA is 1 and the mask bit
11 MERR Memory Error is set by the TINTM (CSR3, bit 9) is 0.
Am79C971 controller when it re-
quests the use of the system in- TINT will not be set if TINTOKD
terface bus by asserting REQ (CSR5, bit 15) is set to 1 and the
and has not received GNT asser- transmission was successful.
tion after a programmable length
of time. The length of time in mi- Read/Write accessible always.
croseconds before MERR is as- TINT is cleared by the host by
serted will depend upon the writing a 1. Writing a 0 has no ef-
setting of the Bus Timeout Regis- fect. TINT is cleared by
ter (CSR100). The default setting H_RESET, S_RESET, or by set-
of CSR100 will give a MERR after ting the STOP bit.
153.6 µs of bus latency.
8 IDON Initialization Done is set by the
When MERR is set, INTA is as- Am79C971 controller after the
serted if IENA is 1 and the mask initialization sequence has com-
bit MERRM (CSR3, bit 11) is 0. pleted. When IDON is set, the
MERR assertion will set the ERR Am79C971 controller has read
bit, regardless of the settings of the initialization block from mem-
IENA and MERRM. ory.
Read/Write accessible always. When IDON is set, INTA is as-

MERR is cleared by the host by serted if IENA is 1 and the mask
writing a 1. Writing a 0 has no ef- bit IDONM (CSR3, bit 8) is 0.
fect. MERR is cleared by
H_RESET, S_RESET, or by set- Read/Write accessible always.
ting the STOP bit. IDON is cleared by the host by
10 RINT Receive Interrupt is set by the fect. IDON is cleared by
Am79C971 controller after the H_RESET, S_RESET, or by set-
last descriptor of a receive frame ting the STOP bit.
has been updated by writing a 0
to the OWNership bit. RINT may 7 INTR Interrupt Flag indicates that one
also be set when the first descrip- or more following interrupt caus-
tor of a receive frame has been ing conditions has occurred:
updated by writing a 0 to the BABL, EXDINT, IDON, JAB,
OWNership bit if the LAPPEN bit MERR, MISS, MFCO, RCVCCO,
of CSR3 has been set to a 1. RINT, SINT, SLPINT, TINT, TX-
STRT, UINT, STINT, MREINT,
When RINT is set, INTA is assert- MCCINT, MCCIINT, MIIPDTINT,
ed if IENA is 1 and the mask bit MAPINT and the associated
RINTM (CSR3, bit 10) is 0. mask or enable bit is pro-
grammed to allow the event to
Read/Write accessible always. cause an interrupt. If IENA is set
RINT is cleared by the host by to 1 and INTR is set, INTA will be
writing a 1. Writing a 0 has no ef- active. When INTR is set by SINT
fect. RINT is cleared by or SLPINT, INTA will be active in-
H_RESET, S_RESET, or by set- dependent of the state of IENA.
ting the STOP bit.
116 Am79C971
Read accessible always. INTR is merely hastens the Am79C971
read only. INTR is cleared by controller’s response to a Trans-
clearing all of the active individual mit Descriptor Ring Entry.
interrupt bits that have not been
masked out. Read/Write accessible always.
TDMD is set by writing a 1. Writ-
6 IENA Interrupt Enable allows INTA to ing a 0 has no effect. TDMD will
be active if the Interrupt Flag is be cleared by the Buffer Manage-
set. If IENA = 0, then INTA will be ment Unit when it fetches a
disabled regardless of the state Transmit Descriptor. TDMD is
of INTR. cleared by H_RESET or
S_RESET and setting the STOP
Read/Write accessible always. bit.
IENA is set by writing a 1 and
cleared by writing a 0. IENA is 2 STOP STOP assertion disables the chip
cleared by H_RESET or from all DMA activity. The chip re-
S_RESET and setting the STOP mains inactive until either STRT
bit. or INIT are set. If STOP, STRT
and INIT are all set together,
5 RXON Receive On indicates that the re- STOP will override STRT and
ceive function is enabled. RXON INIT.
is set if DRX (CSR15, bit 0) is set
to 0 after the START bit is set. If Read/Write accessible always.
INIT and START are set together, STOP is set by writing a 1, by
RXON will not be set until after H_RESET or S_RESET. Writing
the initialization block has been a 0 has no effect. STOP is
read in. cleared by setting either STRT or
INIT.
Read accessible always. RXON
is read only. RXON is cleared by 1 STRT STRT assertion enables
H_RESET or S_RESET and set- Am79C971 controller to send and
ting the STOP bit. receive frames, and perform buff-
er management operations. Set-
4 TXON Transmit On indicates that the ting STRT clears the STOP bit. If
transmit function is enabled. STRT and INIT are set together,
TXON is set if DTX (CSR15, bit 1) the Am79C971 controller initial-
is set to 0 after the START bit is ization will be performed first.
set. If INIT and START are set to-
gether, TXON will not be set until Read/Write accessible always.
after the initialization block has STRT is set by writing a 1. Writing
been read in. a 0 has no effect. STRT is cleared
by H_RESET, S_RESET, or by
Read accessible always. TXON setting the STOP bit.
is read only. TXON is cleared by
H_RESET or S_RESET and set- 0 INIT INIT assertion enables the
ting the STOP bit. Am79C971 controller to begin the
initialization procedure which
3 TDMD Transmit Demand, when set, reads in the initialization block
causes the Buffer Management from memory. Setting INIT clears
Unit to access the Transmit De- the STOP bit. If STRT and INIT
scriptor Ring without waiting for are set together, the Am79C971
the poll-time counter to elapse. If controller initialization will be per-
TXON is not enabled, TDMD bit formed first. INIT is not cleared
will be reset and no Transmit De- when the initialization sequence
scriptor Ring access will occur. has completed.
TDMD is required to be set if the Read/Write accessible always.
TXDPOLL bit in CSR4 is set. Set- INIT is set by writing a 1. Writing
ting TDMD while TXDPOLL = 0 a 0 has no effect. INIT is cleared
Am79C971 117
by H_RESET, S_RESET, or by dress registers and the buffer ad-
setting the STOP bit. dress registers which are stored
on board the Am79C971 control-
CSR1: Initialization Block Address 0 ler will be overwritten with the
Bit Name Description IADR[31:24] value, so that CSR
accesses to these registers will
31-16 RES Reserved locations. Written as show the 32-bit address that in-
zeros and read as undefined. cludes the appended field.
15-0 IADR[15:0] Lower 16 bits of the address of If SSIZE32 = 1, then software will
the Initialization Block. Bit loca- provide 32-bit pointer values for
tions 1 and 0 must both be 0 to all of the shared software struc-
align the initialization block to a tures - i.e., descriptor bases and
DWord boundary. buffer addresses, and therefore,
IADR[31:24] will not be written to
This register is aliased with the upper 8 bits of any of these
CSR16. resources, but it will be used as
the upper 8 bits of the initializa-
Read/Write accessible only when tion address.
either the STOP or the SPND bit
is set. Unaffected by H_RESET This register is aliased with
or S_RESET, or by setting the CSR17.
STOP bit.
Read/Write accessible only when
CSR2: Initialization Block Address 1 either the STOP or the SPND bit
Bit Name Description is set. Unaffected by H_RESET,
S_RESET, or by setting the
31-16 RES Reserved locations. Written as STOP bit.
7-0 IADR[23:16] Bits 23 through 16 of the address
15-8 IADR[31:24] If SSIZE32 is set (BCR20, bit 8), of the Initialization Block. When-
then the IADR[31:24] bits will be ever this register is written,
used strictly as the upper 8 bits of CSR17 is updated with CSR2’s
the initialization block address. contents.
However, if SSIZE32 is reset Read/Write accessible only when

(BCR20, bit 8), then the either the STOP or the SPND bit
IADR[31:24] bits will be used to is set. Unaffected by H_RESET,
generate the upper 8 bits of all S_RESET, or by setting the
bus mastering addresses, as re- STOP bit.
quired for a 32-bit address bus.
CSR3: Interrupt Masks and Deferral Control
Note that the 16-bit software
structures specified by the
SSIZE32 = 0 setting will yield Bit Name Description
only 24 bits of address for the 31-16 RES Reserved locations. Written as
Am79C971 bus master access- zeros and read as undefined.
es, while the 32-bit hardware for
which the Am79C971 controller is 15 RES Reserved location. Read and
intended will require 32 bits of ad- written as zero.
dress. Therefore, whenever
14 BABLM Babble Mask. If BABLM is set,
SSIZE32 = 0, the IADR[31:24]
the BABL bit will be masked and
bits will be appended to the 24-bit
unable to set the INTR bit.
initialization address, to each 24-
bit descriptor base address and Read/Write accessible always.
to each beginning 24-bit buffer BABLM is cleared by H_RESET
address in order to form complete or S_RESET and is not affected
32-bit addresses. The upper 8 by STOP.
bits that exist in the descriptor ad-
118 Am79C971
13 RES Reserved location. Read and off when an UFLO error occurs
written as zero. (CSR0, TXON = 0).
12 MISSM Missed Frame Mask. If MISSM is When DXSUFLO is set to 1, the

set, the MISS bit will be masked Am79C971 controller gracefully
and unable to set the INTR bit. recovers from an UFLO error. It
scans the transmit descriptor ring
Read/Write accessible always. until it finds the start of a new
MISSM is cleared by H_RESET frame and starts a new transmis-
or S_RESET and is not affected sion.
by STOP.
11 MERRM Memory Error Mask. If MERRM DXSUFLO is cleared by
is set, the MERR bit will be H_RESET or S_RESET and is
masked and unable to set the not affected by STOP.
INTR bit.
5 LAPPEN Look Ahead Packet Processing
Read/Write accessible always. Enable. When set to a 1, the
MERRM is cleared by H_RESET LAPPEN bit will cause the
or S_RESET and is not affected Am79C971 controller to generate
by STOP. an interrupt following the descrip-
tor write operation to the first buff-
10 RINTM Receive Interrupt Mask. If RINTM er of a receive frame. This
is set, the RINT bit will be masked interrupt will be generated in ad-
and unable to set the INTR bit. dition to the interrupt that is gen-
erated following the descriptor
write operation to the last buffer
RINTM is cleared by H_RESET
of a receive packet. The interrupt
or S_RESET and is not affected
will be signaled through the RINT
by STOP.
bit of CSR0.
9 TINTM Transmit Interrupt Mask. If
Setting LAPPEN to a 1 also en-
TINTM is set, the TINT bit will be
ables the Am79C971 controller to
masked and unable to set the
read the STP bit of receive de-
INTR bit.
scriptors. The Am79C971 con-
Read/Write accessible always. troller will use the STP
TINTM is cleared by H_RESET information to determine where it
or S_RESET and is not affected should begin writing a receive
by STOP. packet’s data. Note that while in
this mode, the Am79C971 con-
8 IDONM Initialization Done Mask. If troller can write intermediate
IDONM is set, the IDON bit will be packet data to buffers whose de-
masked and unable to set the scriptors do not contain STP bits
INTR bit. set to 1. Following the write to the
last descriptor used by a packet,
Read/Write accessible always. the Am79C971 controller will
IDONM is cleared by H_RESET scan through the next descriptor
or S_RESET and is not affected entries to locate the next STP bit
by STOP. that is set to a 1. The Am79C971
controller will begin writing the
7 RES Reserved location. Read and next packets data to the buffer
written as zeros. pointed to by that descriptor.
6 DXSUFLO Disable Transmit Stop on Under- Note that because several de-
flow error. scriptors may be allocated by the
host for each packet, and not all
When DXSUFLO (CSR3, bit 6) is messages may need all of the de-
set to 0, the transmitter is turned scriptors that are allocated be-
tween descriptors that contain
Am79C971 119
STP = 1, then some descriptors/ See Appendix D for more infor-
buffers may be skipped in the mation on the Look Ahead Pack-
ring. While performing the search et Processing concept.
for the next STP bit that is set to
1, the Am79C971 controller will 4 DXMT2PD Disable Transmit Two Part Defer-
advance through the receive de- ral (see Medium Allocation sec-
scriptor ring regardless of the tion in the Media Access
state of ownership bits. If any of Management section for more
the entries that are examined details). If DXMT2PD is set,
during this search indicate Transmit Two Part Deferral will
Am79C971 controller ownership be disabled.
of the descriptor but also indicate
STP = 0, then the Am79C971 Read/Write accessible always.
controller will reset the OWN bit DXMT2PD is cleared by
to 0 in these entries. If a scanned H_RESET or S_RESET and is
entry indicates host ownership not affected by STOP.
with STP = 0, then the
3 EMBA Enable Modified Back-off Algo-
Am79C971 controller will not al-
rithm (see Contention Resolution
ter the entry, but will advance to
section in Media Access Man-
the next entry.
agement section for more de-
When the STP bit is found to be tails). If EMBA is set, a modified
true, but the descriptor that con- back-off algorithm is implement-
tains this setting is not owned by ed.
the Am79C971 controller, then
the Am79C971 controller will stop
EMBA is cleared by H_RESET or
advancing through the ring en-
S_RESET and is not affected by
tries and begin periodic polling of
STOP.
this entry. When the STP bit is
found to be true, and the descrip- 2 BSWP Byte Swap. This bit is used to
tor that contains this setting is choose between big and little En-
owned by the Am79C971 control- dian modes of operation. When
ler, then the Am79C971 control- BSWP is set to a 1, big Endian
ler will stop advancing through mode is selected. When BSWP is
the ring entries, store the descrip- set to 0, little Endian mode is se-
tor information that it has just lected.
read, and wait for the next re-
ceive to arrive. When big Endian mode is select-
ed, the Am79C971 controller will
This behavior allows the host swap the order of bytes on the AD
software to pre-assign buffer bus during a data phase on ac-
space in such a manner that the cesses to the FIFOs only. Specif-
header portion of a receive pack- ically, AD[31:24] becomes Byte
et will always be written to a par- 0, AD[23:16] becomes Byte 1,
ticular memory area, and the data AD[15:8] becomes Byte 2, and
portion of a receive packet will al- AD[7:0] becomes Byte 3 when
ways be written to a separate big Endian mode is selected.
memory area. The interrupt is When little Endian mode is se-
generated when the header bytes lected, the order of bytes on the
have been written to the header AD bus during a data phase is:
memory area. AD[31:24] is Byte 3, AD[23:16] is
Byte 2, AD[15:8] is Byte 1, and
AD[7:0] is Byte 0.
The LAPPEN bit will be reset to 0
by H_RESET or S_RESET and Byte swap only affects data
will be unaffected by STOP. transfers that involve the FIFOs.
Initialization block transfers are
not affected by the setting of the
120 Am79C971
BSWP bit. Descriptor transfers write to bits in CSR124, which en-
are not affected by the setting of ables the GPSI interface
the BSWP bit. RDP, RAP, BDP (GPSIEN, bit 4) and Runt Packet
and PCI configuration space ac- Accept mode (RPA, bit 3). Once
cesses are not affected by the these bits are accessed, EN124
setting of the BSWP bit. Address must be cleared back to 0.
PROM transfers are not affected
by the setting of the BSWP bit. Read/Write accessible always.
Expansion ROM accesses are ENTST is cleared by H_RESET
not affected by the setting of the or S_RESET and is unaffected by
BSWP bit. the STOP bit.
Note that the byte ordering of the 14 DMAPLUS Writing and reading from this bit
PCI bus is defined to be little En- has no effect. DMAPLUS is al-
dian. BSWP should not be set to ways set to 1.
1 when the Am79C971 controller
is used in a PCI bus application. 13 RES Reserved Location. Written as
zero and read as undefined.
BSWP is cleared by H_RESET or 12 TXDPOLL Transmit Disable Transmit Poll-
S_RESET and is not affected by ing. If TXDPOLL is set, the Buffer
STOP. Management Unit will disable
transmit polling. Likewise, if TXD-
1 RES Reserved location. The default POLL is cleared, automatic trans-
value of this bit is a 0. Writing a 1 mit polling is enabled. If
to this bit has no effect on device TXDPOLL is set, TDMD bit in
function. If a 1 is written to this bit, CSR0 must be set in order to ini-
then a 1 will be read back. Exist- tiate a manual poll of a transmit
ing drivers may write a 1 to this bit descriptor. Transmit descriptor
for compatibility, but new drivers polling will not take place if TXON
should write a 0 to this bit and is reset. Transmit polling will take
should treat the read value as un- place following Receive activi-
defined. ties.
0 RES Reserved location. The default Read/Write accessible always.

value of this bit is a 0. Writing a 1 TXDPOLL is cleared by
to this bit has no effect on device H_RESET or S_RESET and is
function. If a 1 is written to this bit, unaffected by the STOP bit.
then a 1 will be read back. Exist-
ing drivers may write a 1 to this bit 11 APAD_XMT Auto Pad Transmit. When set,
for compatibility, but new drivers APAD_XMT enables the auto-
should write a 0 to this bit and matic padding feature. Transmit
should treat the read value as un- frames will be padded to extend
defined. them to 64 bytes including FCS.
The FCS is calculated for the en-
CSR4: Test and Features Control tire frame, including pad, and ap-
pended after the pad field.
Certain bits in CSR4 indicate the cause of an interrupt.
APAD_XMT will override the pro-
The register is designed so that these indicator bits are
gramming of the DXMTFCS bit
cleared by writing ones to those bit locations. This
(CSR15, bit 3) and of the
means that the software can read CSR4 and write back
ADD_FCS/NO_FCS bit (TMD1,
the value just read to clear the interrupt condition.
bit 29) for frames shorter than 64
Bit Name Description bytes.
31-16 RES Reserved locations. Written as Read/Write accessible always.

zeros and read as undefined. APAD_XMT is cleared by
H_RESET or S_RESET and is
15 EN124 Enable CSR124 access. Setting unaffected by the STOP bit.
EN124 to 1 allows the user to
Am79C971 121
10 ASTRP_RCV Auto Strip Receive. When set, Read/Write accessible always.
ASTRP_RCV enables the auto- UINT is cleared by the host by
matic pad stripping feature. The writing a 1. Writing a 0 has no ef-
pad and FCS fields will be fect. UINT is cleared by
stripped from receive frames and H_RESET or S_RESET or by
not placed in the FIFO. setting the STOP bit.
Read/Write accessible always. 5 RCVCCO Receive Collision Counter Over-

ASTRP_RCV is cleared by flow is set by the Am79C971 con-
H_RESET or S_RESET and is troller when the Receive Collision
unaffected by the STOP bit. Counter (CSR114 and CSR115)
has wrapped around.
9 MFCO Missed Frame Counter Overflow
is set by the Am79C971 control- When RCVCCO is set, INTA is
ler when the Missed Frame asserted if IENA is 1 and the
Counter (CSR112 and CSR114) mask bit RCVCCOM is 0.
has wrapped around.
When MFCO is set, INTA is as- RCVCCO is cleared by the host
serted if IENA is 1 and the mask by writing a 1. Writing a 0 has no
bit MFCOM is 0. effect. RCVCCO is cleared by
Read/Write accessible always. ting the STOP bit.
MFCO is cleared by the host by
writing a 1. Writing a 0 has no ef- 4 RCVCCOM Receive Collision Counter Over-
fect. MFCO is cleared by flow Mask. If RCVCCOM is set,
H_RESET, S_RESET, or by set- the RCVCCO bit will be masked
ting the STOP bit. and unable to set the INTR bit.
8 MFCOM Missed Frame Counter Overflow Read/Write accessible always.

Mask. If MFCOM is set, the RCVCCOM is set to 1 by
MFCO bit will be masked and un- H_RESET or S_RESET and is
able to set the INTR bit. not affected by the STOP bit.
Read/Write accessible always. 3 TXSTRT Transmit Start status is set by the

MFCOM is set to 1 by H_RESET Am79C971 controller whenever it
or S_RESET and is not affected begins transmission of a frame.
by the STOP bit.
When TXSTRT is set, INTA is as-
7 UINTCMD User Interrupt Command. serted if IENA is 1 and the mask
UINTCMD can be used by the bit TXSTRTM is 0.
host to generate an interrupt un-
related to any network activity. Read/Write accessible always.
When UINTCMD is set, INTA is TXSTRT is cleared by the host by
asserted if IENA is set to 1. writing a 1. Writing a 0 has no ef-
UINTCMD will be cleared inter- fect. TXSTRT is cleared by
nally after the Am79C971 control- H_RESET, S_RESET, or by set-
ler has set UINT to 1. ting the STOP bit.
Read/Write accessible always. 2 TXSTRTM Transmit Start Mask. If TX-

UINTCMD is cleared by STRTM is set, the TXSTRT bit
H_RESET or S_RESET or by will be masked and unable to set
setting the STOP bit. the INTR bit.
6 UINT User Interrupt. UINT is set by the Read/Write accessible always.

Am79C971 controller after the TXSTRTM is set to 1 by
host has issued a user interrupt H_RESET or S_RESET and is
command by setting UINTCMD not affected by the STOP bit.
(CSR4, bit 7) to 1.
122 Am79C971
1 JAB Jabber Error is set by the 14 LTINTEN Last Transmit Interrupt Enable.
Am79C971 controller when the When set to 1, the LTINTEN bit
T-MAU exceeds the allowed will cause the Am79C971 control-
transmission limit. Jabber can ler to read bit 28 of TMD1 as
only be asserted in 10BASE-T LTINT. The setting LTINT will de-
mode. termine if TINT will be set at the
end of the transmission.
When JAB is set, INTA is assert-
ed if IENA is 1 and the mask bit Read/Write accessible always.
JABM is 0. LTINTEN is cleared by
Read/Write accessible always. unaffected by STOP.
JAB is cleared by the host by writ-
ing a 1. Writing a 0 has no effect. 13-12 RES Reserved locations. Written as
JAB is cleared by H_RESET, zeros and read as undefined.
S_RESET or by setting the STOP
bit. 11 SINT System Interrupt is set by the
Am79C971 controller when it de-
0 JABM Jabber Error Mask. If JABM is tects a system error during a bus
set, the JAB bit will be masked master transfer on the PCI bus.
and unable to set the INTR bit. System errors are data parity er-
ror, master abort, or a target
Read/Write accessible always. abort. The setting of SINT due to
JABM is set to 1 by H_RESET or data parity error is not dependent
S_RESET and is not affected by on the setting of PERREN (PCI
the STOP bit. Command register, bit 6).
CSR5: Extended Control and Interrupt 1 When SINT is set, INTA is assert-
Certain bits in CSR5 indicate the cause of an interrupt. ed if the enable bit SINTE is 1.
The register is designed so that these indicator bits are Note that the assertion of an in-
cleared by writing ones to those bit locations. This terrupt due to SINT is not depen-
means that the software can read CSR5 and write back dent on the state of the INEA bit,
the value just read to clear the interrupt condition. since INEA is cleared by the
STOP reset generated by the
Bit Name Description system error.
31-16 RES Reserved locations. Written as Read/Write accessible always.

zeros and read as undefined. SINT is cleared by the host by
15 TOKINTD Transmit OK Interrupt Disable. If fect. The state of SINT is not af-
TOKINTD is set to 1, the TINT bit fected by clearing any of the PCI
in CSR0 will not be set when a Status register bits that get set
transmission was successful. when a data parity error
Only a transmit error will set the (DATAPERR, bit 8), master abort
TINT bit. (RMABORT, bit 13), or target
abort (RTABORT, bit 12) occurs.
TOKINTD has no effect when
SINT is cleared by H_RESET or
LTINTEN (CSR5, bit 14) is set to
S_RESET and is not affected by
1. A transmit descriptor with
setting the STOP bit.
LTINT set to 1 will always cause
TINT to be set to 1, independent 10 SINTE System Interrupt Enable. If SIN-
of the success of the transmis- TE is set, the SINT bit will be able
sion. to set the INTR bit.
Read/Write accessible always. Read/Write accessible always.
TOKINTD is cleared by SINTE is set to 0 by H_RESET or
H_RESET or S_RESET and is S_RESET and is not affected by
unaffected by STOP. setting the STOP bit.
Am79C971 123
9 SLPINT Sleep Interrupt is set by the S_RESET or setting the STOP
Am79C971 controller when it bit.
comes out of sleep mode.
5 MPPLBA Magic Packet Physical Logical
When SLPINT is set, INTA is as- Broadcast Accept. If MPPLBA is
serted if the enable bit SLPINTE at its default value of 0, the
is 1. Note that the assertion of an Am79C971 controller will only de-
interrupt due to SLPINT is not detect a Magic Packet frame if the
pendent on the state of the INEA destination address of the packet
bit, since INEA is cleared by the matches the content of the physi-
S_RESET reset generated when cal address register (PADR). If
entering the sleep mode. MPPLBA is set to 1, the destina-
tion address of the Magic Packet
Read/Write accessible always. frame can be unicast, multicast,
SLPINT is cleared by the host by or broadcast. Note that the set-
writing a 1. Writing a 0 has no ef- ting of MPPLBA only affects the
fect. SLPINT is cleared by address detection of the Magic
H_RESET and is not affected by Packet frame. The Magic Packet
S_RESET or setting the STOP frame’s data sequence must be
bit. made up of 16 consecutive phys-
ical addresses (PADR[47:0]) re-
8 SLPINTE Sleep Interrupt Enable. If gardless of what kind of
SLPINTE is set, the SLPINT bit destination address it has.
will be able to set the INTR bit.
Read/Write accessible always. MPPLBA is set to 0 by H_RESET
SLPINTE is set to 0 by H_RESET or S_RESET and is not affected
and is not affected by S_RESET by setting the STOP bit.
or setting the STOP bit.
4 MPINT Magic Packet Interrupt. Magic
7 EXDINT Excessive Deferral Interrupt is Packet Interrupt is set by the
set by the Am79C971 controller Am79C971 controller when the
when the transmitter has experi- device is in the Magic Packet
enced Excessive Deferral on a mode and the Am79C971 con-
transmit frame, where Excessive troller receives a Magic Packet
Deferral is defined in the ISO frame. When MPINT is set to 1,
8802-3 (IEEE/ANSI 802.3) stan- INTA is asserted if IENA (CSR0,
dard. bit 6) and the enable bit MPINTE
are set to 1.
When EXDINT is set, INTA is as-
serted if the enable bit EXDINTE Read/Write accessible always.
is 1. MPINT is cleared by the host by
writing a 1. Writing a 0 has no af-
fect. MPINT is cleared by
EXDINT is cleared by the host by
ting the STOP bit.
fect. EXDINT is cleared by
H_RESET and is not affected by 3 MPINTE Magic Packet Interrupt Enable. If
S_RESET or setting the STOP MPINTE is set to 1, the MPINT bit
bit. will be able to set the INTR bit.
6 EXDINTE Excessive Deferral Interrupt En- Read/Write accessible always.
able. If EXDINTE is set, the MPINT is cleared to 0 by
EXDINT bit will be able to set the H_RESET or S_RESET and is
INTR bit. not affected by setting the STOP
bit.
EXDINTE is set to 0 by
124 Am79C971
2 MPEN Magic Packet Enable. MPEN al- suspend mode (by H_RESET,
lows activation of the Magic S_RESET or by setting the STOP
Packet mode by the host. The bit), no re-initialization of the de-
Am79C971 controller will enter vice is required after the device
the Magic Packet mode when comes out of suspend mode. The
both MPEN and MPMODE are Am79C971 controller will contin-
set to 1. ue at the transmit and receive de-
scriptor ring locations, from
Read/Write accessible always. where it had left, when it entered
MPEN is cleared to 0 by the suspend mode.
not affected by setting the STOP Read/Write accessible always.
bit. SPND is cleared by H_RESET,
S_RESET, or by setting the
1 MPMODE Magic Packet Mode. Setting MP- STOP bit.
MODE to 1 will redefine the
SLEEP pin to be a Magic Packet CSR6: RX/TX Descriptor Table Length
enable pin. The Am79C971 con- Bit Name Description
troller will enter the Magic Packet
mode when MPMODE is set to 1 31-16 RES Reserved locations. Written as
and either SLEEP is asserted or zeros and read as undefined.
MPEN is set to 1.
15-12 TLEN Contains a copy of the transmit
Read/Write accessible always. encoded ring length (TLEN) field
MPMODE is cleared to 0 by read from the initialization block
H_RESET or S_RESET and is during the Am79C971 controller
not affected by setting the STOP initialization. This field is written
bit during the Am79C971 controller
initialization routine.
0 SPND Suspend. Setting SPND to 1 will
cause the Am79C971 controller Read accessible only when either
to start requesting entrance into the STOP or the SPND bit is set.
suspend mode. The host must Write operations have no effect
poll SPND until it reads back 1 to and should not be performed.
determine that the Am79C971 TLEN is only defined after initial-
controller has entered the sus- ization. These bits are unaffected
pend mode. Setting SPND to 0 by H_RESET, S_RESET, or
will get the Am79C971 controller STOP.
out of suspend mode. SPND can
only be set to 1 if STOP (CSR0, 11-8 RLEN Contains a copy of the receive
bit 2) is set to 0. H_RESET, encoded ring length (RLEN) read
S_RESET or setting the STOP bit from the initialization block during
will get the Am79C971 controller Am79C971 controller initializa-
out of suspend mode. tion. This field is written during
the Am79C971 controller initial-
Requesting entrance into the ization routine.
suspend mode by the host de-
pends on the setting of the Read accessible only when either
FASTSPNDE bit (CSR7, bit 15). the STOP or the SPND bit is set.
Refer to the bit description of the Write operations have no effect
FASTSPNDE bit and the Sus- and should not be performed.
pend section in Detailed Func- RLEN is only defined after initial-
tions, Buffer Management Unit ization. These bits are unaffected
for details. by H_RESET, S_RESET, or
STOP.
In suspend mode, all of the CSR
and BCR registers are accessi- 7-0 RES Reserved locations. Read as 0s.
ble. As long as the Am79C971 Write operations are ignored.
controller is not reset while in
Am79C971 125
CSR7: Extended Control and Interrupt 2 FIFOs, and the receive buffer
Certain bits in CSR7 indicate the cause of an interrupt. area in the external SRAM (if one
The register is designed so that these indicator bits are is present) will be transferred into
cleared by writing ones to those bit locations. This system memory. Since the FIFO
means that the software can read CSR7 and write back and external SRAM contents are
the value just read to clear the interrupt condition. flushed, it may take much longer
before the Am79C971 controller
Bit Name Description enters the suspend mode. The
amount of time that it takes de-
31-16 RES Reserved locations. Written as pends on many factors including
zeros and read as undefined. the size of the external SRAM,
bus latency, and network traffic
15 FASTSPNDE Fast Suspend Enable. When level.
FASTSPNDE is set to 1, the
Am79C971 controller performs a When a write to CSR5 is per-
fast suspend whenever the formed with bit 0 (SPND) set to 1,
SPND bit is set. the value that is simultaneously
written to FASTSPNDE is used to
When a fast suspend is request- determine which approach is
ed, the Am79C971 controller per- used to enter suspend mode.
forms a quick entry into the
suspend mode. At the time the Read/Write accessible always.
SPND bit is set, the Am79C971 FASTSPNDE is cleared by
controller will complete the DMA H_RESET, S_RESET or by set-
process of any transmit and/or re- ting the STOP bit.
ceive packet that had already be-
gun DMA activity. In addition, any 14 RXFRTG Receive Frame Tag. When Re-
transmit packet that had started ceive Frame Tag is set to 1, a tag
transmission will be fully transmit- word is put into the receive de-
ted and any receive packet that scriptor supplied by the EADI.
had begun reception will be fully See the section Receive Frame
received. However, no additional Tagging for details. This bit is
packets will be transmitted or re- valid only when the EADISEL
ceived and no additional transmit (BCR2, bit 3) is set to 1.
or receive DMA activity will begin.
Hence, the Am79C971 controller Read/Write accessible always.
may enter the suspend mode RXFRTG is cleared by
with transmit and/or receive H_RESET. RXFRTG is unaffect-
packets still in the FIFOs or exter- ed by S_RESET or by setting the
nal SRAM. STOP bit.
When FASTSPNDE is 0 and the 13 RDMD Receive Demand, when set,

SPND bit is set, the Am79C971 causes the Buffer Management
controller may take longer before Unit to access the Receive De-
entering the suspend mode. At scriptor Ring without waiting for
the time the SPND bit is set, the the receive poll-time counter to
Am79C971 controller will com- elapse. If RXON is not enabled,
plete the DMA process of a trans- RDMD has no meaning and no
mit packet if it had already begun receive Descriptor Ring access
and the Am79C971 controller will will occur.
completely receive a receive
packet if it had already begun. RDMD is required to be set if the
Additionally, all transmit packets RXDPOLL bit in CSR7 is set. Set-
stored in the transmit FIFOs and ting RDMD while RXDPOLL = 0
the transmit buffer area in the ex- merely hastens the Am79C971
ternal SRAM (if one is present) controller’s response to a receive
will be transmitted and all receive Descriptor Ring Entry.
packets stored in the receive
126 Am79C971
Read/Write accessible always. 9 MREINT MII Management Read Error In-
RDMD is set by writing a 1. Writ- terrupt. The MII Read Error inter-
ing a 0 has no effect. RDMD will rupt is set by the Am79C971
be cleared by the Buffer Manage- controller to indicate that the cur-
ment Unit when it fetches a re- rently read register from the ex-
ceive Descriptor. RDMD is ternal PHY is invalid. The
cleared by H_RESET. RDMD is contents of BCR34 are incorrect
unaffected by S_RESET or by and that the operation should be
setting the STOP bit. performed again. The indication
of an incorrect read comes from
12 RXDPOLL Receive Disable Polling. If RXD- the PHY. During the read turn-
POLL is set, the Buffer Manage- around time of the MII manage-
ment Unit will disable receive ment frame the external PHY
polling. Likewise, if RXDPOLL is should drive the MDIO pin to a
cleared, automatic receive poll- LOW state. If this does not hap-
ing is enabled. If RXDPOLL is pen, it indicates that the PHY and
set, RDMD bit in CSR7 must be the Am79C971 controller have
set in order to initiate a manual lost synchronization.
poll of a receive descriptor. Re-
ceive Descriptor Polling will not When MREINT is set to 1, INTA is
take place if RXON is reset. asserted if the enable bit MREIN-
TE is set to 1.
RXDPOLL is cleared by Read/Write accessible always.
H_RESET. RXDPOLL is unaf- MREINT is cleared by the host by
fected by S_RESET or by setting writing a 1. Writing a 0 has no ef-
the STOP bit. fect. MREINT is cleared by
11 STINT Software Timer Interrupt. The S_RESET or setting the STOP
Software Timer interrupt is set by bit.
the Am79C971 controller when
the Software Timer counts down 8 MREINTE MII Management Read Error In-
to 0. The Software Timer will im- terrupt Enable. If MREINTE is
mediately load the STVAL (BCR set, the MREINT bit will be able to
31, bits 5-0) into the Software set the INTR bit.
Timer and begin counting down.
When STINT is set to 1, INTA is MREINTE is set to 0 by
asserted if the enable bit STINTE H_RESET and is not affected by
is set to 1. S_RESET or setting the STOP bit
Read/Write accessible always. 7 MAPINT MII Management Auto-Poll Inter-

STINT is cleared by the host by rupt. The MII Auto-Poll interrupt is
writing a 1. Writing a 0 has no ef- set by the Am79C971 controller
fect. STINT is cleared by to indicate that the currently read
H_RESET and is not affected by status does not match the stored
S_RESET or setting the STOP previous status indicating a
bit. change in state for the external
PHY. A change in the Auto-Poll
10 STINTE Software Timer Interrupt Enable. Access Method (BCR32, Bit 10)
If STINTE is set, the STINT bit will reset the shadow register and
will be able to set the INTR bit. will not cause an interrupt on the
first access from the Auto-Poll
Read/Write accessible always. section. Subsequent accesses
STINTE is set to 0 by H_RESET will generate an interrupt if the
and is not affected by S_RESET shadow register and the read
or setting the STOP bit register produce differences.
Am79C971 127
When MAPINT is set to 1, INTA is Read/Write accessible always.
asserted if the enable bit MAP- MCCINTE is set to 0 by
INTE is set to 1. H_RESET and is not affected by
S_RESET or setting the STOP
Read/Write accessible always. bit.
MAPINT is cleared by the host by
writing a 1. Writing a 0 has no ef- 3 MCCIINT MII Management Command
fect. MAPINT is cleared by Complete Internal Interrupt. The
H_RESET and is not affected by MII Management Command
S_RESET or setting the STOP Complete Interrupt is set by the
bit. Am79C971 controller when a
read or write operation on the MII
6 MAPINTE MII Auto-Poll Interrupt Enable. If management port is complete
MAPINTE is set, the MAPINT bit from an internal operation. Exam-
will be able to set the INTR bit. ples of internal operations are
Auto-Poll or MII Management
Read/Write accessible always. Port generated MII management
MAPINTE is set to 0 by frames. These are normally hid-
H_RESET and is not affected by den to the host.
S_RESET or setting the STOP bit
When MCCIINT is set to 1, INTA
5 MCCINT MII Management Command is asserted if the enable bit MC-
Complete Interrupt. The MII Man- CINTE is set to 1.
agement Command Complete In-
terrupt is set by the Am79C971 Read/Write accessible always.
controller when a read or write MCCIINT is cleared by the host
operation to the MII Data Port by writing a 1. Writing a 0 has no
(BCR34) is complete. effect. MCCIINT is cleared by
When MCCINT is set to 1, INTA S_RESET or setting the STOP
is asserted if the enable bit MC- bit.
CINTE is set to 1.
2 MCCIINTE MII Management Command
Read/Write accessible always. Complete Internal Interrupt En-
MCCINT is cleared by the host by able. If MCCIINTE is set to 1, the
writing a 1. Writing a 0 has no ef- MCCIINT bit will be able to set
fect. MCCINT is cleared by the INTR bit when the internal
H_RESET and is not affected by state machines generate MII
S_RESET or setting the STOP management frames. For in-
bit. stance, when MCCIINTE is set to
1 and the Auto-Poll state ma-
4 MCCINTE MII Management Command
chine generates a MII manage-
Complete Interrupt Enable. If
ment frame, the MCCIINT will set
MCCINTE is set to 1, the MC-
the INTR bit upon completion of
CINT bit will be able to set the
the MII management frame re-
INTR bit when the host reads or
gardless of the comparison out-
writes to the MII Data Port
come.
(BCR34) only. Internal MII Man-
agement Commands will not gen- Read/Write accessible always.
erate an interrupt. For instance MCCIINTE is set to 0 by
Auto-Poll state machine generat- H_RESET and is not affected by
ed MII management frames will S_RESET or setting the STOP
not generate an interrupt upon bit.
completion unless there is a com-
pare error which get reported
through the MAPINT (CSR7, bit
6) interrupt or the MCCIINTE is
set to 1.
128 Am79C971
1 MIIPDTINT MII PHY Detect Transition Inter- a direct register write has been
rupt. The MII PHY Detect Transi- performed on this register.
tion Interrupt is set by the
Am79C971 controller whenever Read/Write accessible only when
the MIIPD bit (BCR32, bit 14) either the STOP or the SPND bit
transitions from 0 to 1 or vice ver- is set. These bits are unaffected
sa. by H_RESET, S_RESET, or
STOP.
MIIPDTINT is cleared by the host CSR10: Logical Address Filter 2
by writing a 1. Writing a 0 has no Bit Name Description
effect. MIIPDTINT is cleared by
H_RESET and is not affected by 31-16 RES Reserved locations. Written as
S_RESET or setting the STOP zeros and read as undefined.
bit.
15-0 LADRF[47:32] Logical Address Filter,
0 MIIPDTINTE MII PHY Detect Transition Inter- LADRF[47:32]. The content of
rupt Enable. If MIIPDTINTE is set this register is undefined until
to 1, the MIIPDTINT bit will be loaded from the initialization
able to set the INTR bit. block after the INIT bit in CSR0
has been set or a direct register
Read/Write accessible always. write has been performed on this
MIIPDTINTE is set to 0 by register.
S_RESET or setting the STOP Read/Write accessible only when
bit. either the STOP or the SPND bit
is set. These bits are unaffected
CSR8: Logical Address Filter 0 by H_RESET, S_RESET, or
Bit Name Description STOP.
31-16 RES Reserved locations. Written as CSR11: Logical Address Filter 3

zeros and read as undefined. Bit Name Description
15-0 LADRF[15:0] Logical Address Filter, LADRF- 31-16 RES Reserved locations. Written as
[15:0]. The content of this register zeros and read as undefined.
is undefined until loaded from the
initialization block after the INIT 15-0 LADRF[63:48] Logical Address Filter,
bit in CSR0 has been set or a di- LADRF[63:48]. The content of
rect register write has been per- this register is undefined until
formed on this register. loaded from the initialization
block after the INIT bit in CSR0
Read/Write accessible only when has been set or a direct register
either the STOP or the SPND bit write has been performed on this
is set. These bits are unaffected register.
by H_RESET, S_RESET, or
STOP. Read/Write accessible only when
CSR9: Logical Address Filter 1 is set. These bits are unaffected
Bit Name Description by H_RESET, S_RESET, or
STOP.
zeros and read as undefined. CSR12: Physical Address Register 0
15-0 LADRF[31:16] Logical Address Filter, LADRF- Bit Name Description

[31:16]. The content of this regis- 31-16 RES Reserved locations. Written as
ter is undefined until loaded from zeros and read as undefined.
the initialization block after the
INIT bit in CSR0 has been set or
Am79C971 129
15-0 PADR[15:0] Physical Address Register, Initialization Block values, or when a direct register
PADR[15:0]. The content of this write has been performed on this register.
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
15 PROM Promiscuous Mode. When
PROM = 1, all incoming receive
frames are accepted.
by H_RESET, S_RESET, or Read/Write accessible only when
STOP. either the STOP or the SPND bit
is set.
CSR13: Physical Address Register 1
Bit Name Description 14 DRCVBC Disable Receive Broadcast.
When set, disables the
31-16 RES Reserved locations. Written as Am79C971 controller from re-
zeros and read as undefined. ceiving broadcast messages.
Used for protocols that do not
15-0 PADR[31:16] Physical Address Register, support broadcast addressing,
PADR[31:16]. The content of this except as a function of multicast.
register is undefined until loaded DRCVBC is cleared by activation
from the initialization block after of H_RESET or S_RESET
the INIT bit in CSR0 has been set (broadcast messages will be re-
or a direct register write has been ceived) and is unaffected by
performed on this register. STOP.
Read/Write accessible only when Read/Write accessible only when

either the STOP or the SPND bit either the STOP or the SPND bit
is set. These bits are unaffected is set.
STOP. 13 DRCVPA Disable Receive Physical Ad-
dress. When set, the physical ad-
CSR14: Physical Address Register 2 dress detection (Station or node
Bit Name Description ID) of the Am79C971 controller
will be disabled. Frames ad-
31-16 RES Reserved locations. Written as dressed to the nodes individual
zeros and read as undefined. physical address will not be rec-
ognized.
15-0 PADR[47:32] Physical Address Register,
PADR[47:32]. The content of this Read/Write accessible only when
register is undefined until loaded either the STOP or the SPND bit
from the initialization block after is set.
the INIT bit in CSR0 has been set
or a direct register write has been 12 DLNKTST Disable Link Status. When
performed on this register. DLNKTST = 1, monitoring of Link
Pulses is disabled. When
Read/Write accessible only when DLNKTST = 0, monitoring of Link
either the STOP or the SPND bit Pulses is enabled. This bit only
is set. These bits are unaffected has meaning when the 10BASE-
by H_RESET, S_RESET, or T network interface is selected.
STOP.
CSR15: Mode either the STOP or the SPND bit
is set.
This register’s fields are loaded during the Am79C971
controller initialization routine with the corresponding 11 DAPC Disable Automatic Polarity Cor-
rection. When DAPC = 1, the
130 Am79C971
10BASE-T receive polarity rever- TSEL (AUI mode) Transmit Mode Se-
sal algorithm is disabled. Like- lect. TSEL controls the levels at
wise, when DAPC = 0, the which the AUI drivers rest when
polarity reversal algorithm is en- the AUI transmit port is idle.
abled. When TSEL = 0, DO+ and DO-
yield “zero” differential to operate
This bit only has meaning when transformer coupled loads
the 10BASE-T network interface (Ethernet 2 and IEEE 802.3).
is selected. When TSEL = 1, the DO+ idles at
a higher value with respect to
Read/Write accessible only when DO-, yielding a logical HIGH state
either the STOP or the SPND bit (Ethernet 1).
is set.
This bit only has meaning when
10 MENDECL MENDEC Loopback Mode. See the AUI network interface is se-
the description of the LOOP bit in lected.
CSR15, bit 2.
Read/Write accessible only when either the STOP or the SPND bit
either the STOP or the SPND bit is set. Cleared by H_RESET or
is set. S_RESET.
9 LRT (TMAU mode) Low Receive 8-7 PORTSEL[1:0]Port Select bits allow for software
Threshold. When LRT = 1, the in- controlled selection of the net-
ternal twisted pair receive thresh- work medium. See Table 26.
olds are reduced by 4.5 dB below
the standard 10BASE-T value PORTSEL settings of AUI,
(approximately 3/5) and the un- 10BASE-T and MII are ignored
squelch threshold for the RXD when the ASEL bit of BCR2 (bit 1)
circuit will be 180 mV to 312 mV has been set to 1.
peak.
When LRT = 0, the unsquelch either the STOP or the SPND bit
threshold for the RXD circuit will is set. Cleared by H_RESET or
be the standard 10BASE-T value, S_RESET and is unaffected by
300 mV to 520 mV peak. STOP.
In either case, the RXD circuit 6 INTL Internal Loopback. See the de-
post squelch threshold will be scription of LOOP (CSR15, bit 2).
one-half of the unsquelch thresh-
old. Read/Write accessible only when
This bit only has meaning when is set.
the 10BASE-T network interface
is selected.

is set. Cleared by H_RESET or
S_RESET and is unaffected by
STOP.
Am79C971 131
Table 26. Network Port Configuration.
ASEL Link Status MII Status Network
PORTSEL [1:0] (BCR2[1]) (10BASE-T) (BCR32[14]) Port
XX 1 Fail 0 AUI
XX 1 Pass 0 10BASE-T
XX 1 Don’t Care 1 MII
00 0 Don’t Care Don’t Care AUI
01 0 Don’t Care Don’t Care 10BASE-T
10 0 Don’t Care Don’t Care GPSI
11 0 Don’t Care Don’t Care MII
5 DRTY Disable Retry. When DRTY is set DXMTFCS has no effect on

to 1, the Am79C971 controller will frames shorter than 64 bytes.
attempt only one transmission. In
this mode, the device will not pro- If DXMTFCS is set and
tect the first 64 bytes of frame ADD_FCS is clear for a particular
data in the Transmit FIFO from frame, no FCS will be generated.
being overwritten, because auto- The value of ADD_FCS is valid
matic retransmission will not be only when STP is set in TMD1. If
necessary. When DRTY is set to ADD_FCS is set for a particular
0, the Am79C971 controller will frame, the state of DXMTFCS is
attempt 16 transmissions before ignored and a FCS will be ap-
signaling a retry error. pended on that frame by the
transmit circuitry. See also the
Read/Write accessible only when ADD_FCS bit in TMD1.
is set. This bit was called DTCR in the
LANCE (Am7990) device.
4 FCOLL Force Collision. This bit allows
the collision logic to be tested. Read/Write accessible only when
The Am79C971 controller must either the STOP or the SPND bit
be in internal loopback for FCOLL is set.
to be valid. If FCOLL = 1, a colli-
sion will be forced during loop- 2 LOOP Loopback Enable allows the
back transmission attempts, Am79C971 controller to operate
which will result in a Retry Error. in full-duplex mode for test pur-
If FCOLL = 0, the Force Collision poses. The setting of the full-
logic will be disabled. FCOLL is duplex control bits in BCR9 have
defined after the initialization no effect when the device oper-
block is read. ates in loopback mode. When
LOOP = 1, loopback is enabled.
Read/Write accessible only when In combination with INTL and
either the STOP or the SPND bit MENDECL, various loopback
is set. modes are defined as follows in
Table 27. Refer to Loop Back Op-
3 DXMTFCS Disable Transmit CRC (FCS). eration section for more details.
When DXMTFCS is set to 0, the
transmitter will generate and ap-
pend an FCS to the transmitted Table 27. Loopback Configuration for AUI
frame. When DXMTFCS is set to
LOOP INTL MENDECL Loopback Mode
1, no FCS is generated or sent
with the transmitted frame. 0 X X Non-loopback
DXMTFCS is overridden when 1 0 X External Loopback
ADD_FCS is set in TMD1. Internal Loopback Include
1 1 0
MENDEC
When APAD_XMT (CSR4, bit Internal Loopback
11) is set to 1, the setting of 1 1 1
Exclude MENDEC
132 Am79C971
Read/Write accessible only when CSR18: Current Receive Buffer Address Lower
either the STOP or the SPND bit Bit Name Description
is set. LOOP is cleared by
H_RESET or S_RESET and is 31-16 RES Reserved locations. Written as
unaffected by STOP. zeros and read as undefined.
1 DTX Disable Transmit results in 15-0 CRBAL Contains the lower 16 bits of the
Am79C971 controller not access- current receive buffer address at
ing the Transmit Descriptor Ring which the Am79C971 controller
and, therefore, no transmissions will store incoming frame data.
are attempted. DTX = 0, will set
TXON bit (CSR0 bit 4) if STRT Read/Write accessible only when
(CSR0 bit 1) is asserted. either the STOP or the SPND bit
Read/Write accessible only when by H_RESET, S_RESET, or
either the STOP or the SPND bit STOP.
is set.
CSR19: Current Receive Buffer Address Upper
0 DRX Disable Receiver results in the
Am79C971 controller not access- Bit Name Description
ing the Receive Descriptor Ring
and, therefore, all receive frame 31-16 RES Reserved locations. Written as
data are ignored. DRX = 0, will zeros and read as undefined.
set RXON bit (CSR0 bit 5) if
15-0 CRBAU Contains the upper 16 bits of the
STRT (CSR0 bit 1) is asserted.
current receive buffer address at
Read/Write accessible only when which the Am79C971 controller
either the STOP or the SPND bit will store incoming frame data.
is set.
CSR16: Initialization Block Address Lower either the STOP or the SPND bit
Bit Name Description by H_RESET, S_RESET, or
STOP.
zeros and read as undefined. CSR20: Current Transmit Buffer Address Lower
15-0 IADRL This register is an alias of CSR1. Bit Name Description
Read/Write accessible only when 31-16 RES Reserved locations. Written as

either the STOP or the SPND bit zeros and read as undefined.
is set.
15-0 CXBAL Contains the lower 16 bits of the
CSR17: Initialization Block Address Upper current transmit buffer address
from which the Am79C971 con-
troller is transmitting.
31-16 RES Reserved locations. Written as Read/Write accessible only when
zeros and read as undefined. either the STOP or the SPND bit
15-0 IADRH This register is an alias of CSR2.
Read/Write accessible only when STOP.
CSR21: Current Transmit Buffer Address Upper
is set.

Am79C971 133
15-0 CXBAU Contains the upper 16 bits of the by H_RESET, S_RESET, or
current transmit buffer address STOP.
from which the Am79C971 con-
troller is transmitting. CSR25: Base Address of Receive Ring Upper
either the STOP or the SPND bit 31-16 RES Reserved locations. Written as
is set. These bits are unaffected zeros and read as undefined.
STOP. 15-0 BADRU Contains the upper 16 bits of the
base address of the Receive
CSR22: Next Receive Buffer Address Lower Ring.
31-16 RES Reserved locations. Written as either the STOP or the SPND bit
zeros and read as undefined. is set. These bits are unaffected
15-0 NRBAL Contains the lower 16 bits of the STOP.
next receive buffer address to
which the Am79C971 controller CSR26: Next Receive Descriptor Address Lower
will store incoming frame data. Bit Name Description
Read/Write accessible only when 31-16 RES Reserved locations. Written as

either the STOP or the SPND bit zeros and read as undefined.
by H_RESET, S_RESET, or 15-0 NRDAL Contains the lower 16 bits of the
STOP. next receive descriptor address
pointer.
CSR23: Next Receive Buffer Address Upper
Bit Name Description Read/Write accessible only when
31-16 RES Reserved locations. Written as is set. These bits are unaffected
zeros and read as undefined. by H_RESET, S_RESET, or
STOP.
15-0 NRBAU Contains the upper 16 bits of the
next receive buffer address to CSR27: Next Receive Descriptor Address Upper
which the Am79C971 controller Bit Name Description
will store incoming frame data.
Read/Write accessible only when zeros and read as undefined.
is set. These bits are unaffected 15-0 NRDAU Contains the upper 16 bits of the
by H_RESET, S_RESET, or next receive descriptor address
STOP. pointer.
CSR24: Base Address of Receive Ring Lower Read/Write accessible only when
Bit Name Description either the STOP or the SPND bit
31-16 RES Reserved locations. Written as by H_RESET, S_RESET, or
zeros and read as undefined. STOP.
15-0 BADRL Contains the lower 16 bits of the CSR28: Current Receive Descriptor Address Lower
base address of the Receive Bit Name Description
Ring.
134 Am79C971
15-0 CRDAL Contains the lower 16 bits of the CSR32: Next Transmit Descriptor Address Lower
current receive descriptor ad- Bit Name Description
dress pointer.
is set. These bits are unaffected 15-0 NXDAL Contains the lower 16 bits of the
by H_RESET, S_RESET, or next transmit descriptor address
STOP. pointer.
CSR29: Current Receive Descriptor Address Upper Read/Write accessible only when
15-0 CRDAU Contains the upper 16 bits of the CSR33: Next Transmit Descriptor Address Upper
current receive descriptor ad- Bit Name Description
dress pointer.
is set. These bits are unaffected 15-0 NXDAU Contains the upper 16 bits of the
by H_RESET, S_RESET, or next transmit descriptor address
STOP. pointer.
CSR30: Base Address of Transmit Ring Lower Read/Write accessible only when
15-0 BADXL Contains the lower 16 bits of the CSR34: Current Transmit Descriptor Address
base address of the Transmit Lower
Ring. Bit Name Description
by H_RESET, S_RESET, or 15-0 CXDAL Contains the lower 16 bits of the
STOP. current transmit descriptor ad-
dress pointer.
CSR31: Base Address of Transmit Ring Upper
Bit Name Description Read/Write accessible only when
31-16 RES Reserved locations. Written as is set. These bits are unaffected
zeros and read as undefined. by H_RESET, S_RESET, or
STOP.
15-0 BADXU Contains the upper 16 bits of the
base address of the Transmit CSR35: Current Transmit Descriptor Address
Ring. Upper
STOP.
Am79C971 135
15-0 CXDAU Contains the upper 16 bits of the is set. These bits are unaffected
current transmit descriptor ad- by H_RESET, S_RESET, or
dress pointer. STOP.
Read/Write accessible only when CSR39: Next Next Transmit Descriptor Address
either the STOP or the SPND bit Upper
is set. These bits are unaffected Bit Name Description
STOP. 31-16 RES Reserved locations. Written as
CSR36: Next Next Receive Descriptor Address
Lower 15-0 NNXDAU Contains the upper 16 bits of the
Bit Name Description next next transmit descriptor ad-
dress pointer.
zeros and read as undefined. Read/Write accessible only when
15-0 NNRDAL Contains the lower 16 bits of the is set. These bits are unaffected
next next receive descriptor ad- by H_RESET, S_RESET, or
dress pointer. STOP.
Read/Write accessible only when CSR40: Current Receive Byte Count

by H_RESET, S_RESET, or 31-16 RES Reserved locations. Written as
STOP. zeros and read as undefined.
CSR37: Next Next Receive Descriptor Address 15-12 RES Reserved locations. Read and
Upper written as zeros.
11-0 CRBC Current Receive Byte Count.
31-16 RES Reserved locations. Written as This field is a copy of the BCNT
zeros and read as undefined. field of RMD1 of the current re-
ceive descriptor.
15-0 NNRDAU Contains the upper 16 bits of the
next next receive descriptor ad- Read/Write accessible only when
dress pointer. either the STOP or the SPND bit
by H_RESET, S_RESET, or CSR41: Current Receive Status
STOP. Bit Name Description
CSR38: Next Next Transmit Descriptor Address 31-16 RES Reserved locations. Written as
Lower zeros and read as undefined.
15-0 CRST Current Receive Status. This
31-16 RES Reserved locations. Written as field is a copy of bits 31-16 of
zeros and read as undefined. RMD1 of the current receive de-
scriptor.
15-0 NNXDAL Contains the lower 16 bits of the
next next transmit descriptor ad- Read/Write accessible only when
dress pointer. either the STOP or the SPND bit
136 Am79C971
CSR42: Current Transmit Byte Count CSR45: Next Receive Status
Bit Name Description Bit Name Description
31-16 RES Reserved locations. Written as 31-16 RES Reserved locations. Written as
zeros and read as undefined. zeros and read as undefined.
15-12 RES Reserved locations. Read and 15-0 NRST Next Receive Status. This field is
written as zeros. a copy of bits 31-16 of RMD1 of
the next receive descriptor.
11-0 CXBC Current Transmit Byte Count.
This field is a copy of the BCNT Read/Write accessible only when
field of TMD1 of the current trans- either the STOP or the SPND bit
mit descriptor. is set. These bits are unaffected
is set. These bits are unaffected CSR46: Transmit Poll Time Counter
by H_RESET, S_RESET, or Bit Name Description
STOP.
CSR43: Current Transmit Status
15-0 TXPOLL Transmit Poll Time Counter. This
31-16 RES Reserved locations. Written as counter is incremented by the
zeros and read as undefined. Am79C971 controller microcode
and is used to trigger the transmit
15-0 CXST Current Transmit Status. This descriptor ring polling operation
field is a copy of bits 31-16 of of the Am79C971 controller.
TMD1 of the current transmit de-
scriptor. Read/Write accessible only when
Read/Write accessible only when is set. These bits are unaffected
either the STOP or the SPND bit by H_RESET, S_RESET, or
is set. These bits are unaffected STOP.
STOP. CSR47: Transmit Polling Interval
CSR44: Next Receive Byte Count
Bit Name Description 31-16 RES Reserved locations. Written as
zeros and read as undefined. 15-0 TXPOLLINT Transmit Polling Interval. This
register contains the time that the
15-12 RES Reserved locations. Read and Am79C971 controller will wait be-
written as zeros. tween successive polling opera-
tions. The TXPOLLINT value is
11-0 NRBC Next Receive Byte Count. This expressed as the two’s comple-
field is a copy of the BCNT field of ment of the desired interval,
RMD1 of the next receive de- where each bit of TXPOLLINT
scriptor. represents 1 clock period of time.
TXPOLLINT[3:0] are ignored.
(TXPOLLINT[16] is implied to be
a one, so TXPOLLINT[15] is sig-
nificant and does not represent
the sign of the two’s complement
STOP.
TXPOLLINT value.)
Am79C971 137
The default value of this register Read/Write accessible only when
is 0000b. This corresponds to a either the STOP or the SPND bit
polling interval of 65,536 clock is set. These bits are unaffected
periods (1.966 ms when by H_RESET, S_RESET, or
CLK = 33 MHz). The TXPOL- STOP.
LINT value of 0000b is created
during the microcode initialization CSR49: Receive Polling Interval
routine and, therefore, might not Bit Name Description
be seen when reading CSR47 af-
ter H_RESET or S_RESET. 31-16 RES Reserved locations. Written as
If the user desires to program a
value for POLLINT other than the 15-0 RXPOLLINT Receive Polling Interval. This reg-
default, then the correct proce- ister contains the time that the
dure is to first set INIT only in Am79C971 controller will wait be-
CSR0. Then, when the initializa- tween successive polling opera-
tion sequence is complete, the tions. The RXPOLLINT value is
user must set STOP (CSR0, bit expressed as the two’s comple-
2). Then the user may write to ment of the desired interval,
CSR47 and then set STRT in where each bit of RXPOLLINT
CSR0. In this way, the default approximately represents one
value of 0000h in CSR47 will be clock time period. RXPOL-
overwritten with the desired user LINT[3:0] are ignored. (RXPOL-
value. LINT[16] is implied to be a 1, so
RXPOLLINT[15] is significant
If the user does not use the stan- and does not represent the sign
dard initialization procedure of the two’s complement RXPOL-
(standard implies use of an initial- LINT value.)
ization block in memory and set-
ting the INIT bit of CSR0), but The default value of this register
instead, chooses to write directly is 0000h. This corresponds to a
to each of the registers that are polling interval of 65,536 clock
involved in the INIT operation, periods (1.966 ms when
then it is imperative that the user CLK = 33 MHz). The RXPOL-
also writes all zeros to CSR47 as LINT value of 0000h is created
part of the alternative initialization during the microcode initialization
sequence. routine and, therefore, might not
be seen when reading CSR49 af-
Read/Write accessible only when ter H_RESET or S_RESET.
is set. These bits are unaffected If the user desires to program a
by H_RESET, S_RESET, or value for RXPOLLINT other than
STOP. the default, then the correct pro-
cedure is to first set INIT only in
CSR48: Receive Poll Time Counter CSR0. Then, when the initializa-
Bit Name Description tion sequence is complete, the
user must set STOP (CSR0, bit
31-16 RES Reserved locations. Written as 2). Then the user may write to
zeros and read as undefined. CSR49 and then set STRT in
CSR0. In this way, the default
15-0 RXPOLL Receive Poll Time Counter. This value of 0000h in CSR47 will be
counter is incremented by the overwritten with the desired user
Am79C971 controller microcode value.
and is used to trigger the receive
descriptor ring polling operation
of the Am79C971 controller.
138 Am79C971
P R E L I M I N A R Y
If the user does not use the stan- 9 RES Reserved locations. Written as
dard initialization procedure zeros and read as undefined.
(standard implies use of an initial-
ization block in memory and set- 8 SSIZE32 Software Size 32 bits. When set,
ting the INIT bit of CSR0), but this bit indicates that the
instead, chooses to write directly Am79C971 controller utilizes 32-
to each of the registers that are bit software structures for the ini-
involved in the INIT operation, tialization block and the transmit
then it is imperative that the user and receive descriptor entries.
also writes all zeros to CSR49 as When cleared, this bit indicates
part of the alternative initialization that the Am79C971 controller uti-
sequence. lizes 16-bit software structures for
the initialization block and the
Read/Write accessible only when transmit and receive descriptor
either the STOP or the SPND bit entries. In this mode, the
is set. These bits are unaffected Am79C971 controller is back-
by H_RESET, S_RESET, or wards compatible with the
STOP. Am7990 LANCE and Am79C960
PCnet-ISA controllers.
CSR58: Software Style
This register is an alias of the location BCR20. Accesses The value of SSIZE32 is deter-
to and from this register are equivalent to accesses to mined by the Am79C971 control-
BCR20. ler according to the setting of the
Software Style (SWSTYLE, bits
Bit Name Description 7-0 of this register).
31-16 RES Reserved locations. Written as Read accessible always.

zeros and read as undefined. SSIZE32 is read only; write oper-
ations will be ignored. SSIZE32
15-11 RES Reserved locations. Written as will be cleared after H_RESET
zeros and read as undefined. (since SWSTYLE defaults to 0)
and is not affected by S_RESET
10 APERREN Advanced Parity Error Handling or STOP.
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and If SSIZE32 is reset, then bits
TMD1, bit 23) start having a IADR[31:24] of CSR2 will be
meaning. BPE will be set in the used to generate values for the
descriptor associated with the upper 8 bits of the 32-bit address
buffer that was accessed when a bus during master accesses initi-
data parity error occurred. Note ated by the Am79C971 controller.
that since the advanced parity er- This action is required, since the
ror handling uses an additional bit 16-bit software structures speci-
in the descriptor, SWSTYLE (bits fied by the SSIZE32 = 0 setting
7-0 of this register) must be set to will yield only 24 bits of address
2 or 3 to program the Am79C971 for the Am79C971 controller bus
controller to use 32-bit software master accesses.
structures.
If SSIZE32 is set, then the soft-
APERREN does not affect the re- ware structures that are common
porting of address parity errors or to the Am79C971 controller and
data parity errors that occur when the host system will supply a full
the Am79C971 controller is the 32 bits for each address pointer
target of the transfer. that is needed by the Am79C971
controller for performing master
Read anytime, write accessible accesses.
only when either the STOP or the
SPND bit is set. APERREN is The value of the SSIZE32 bit has
cleared by H_RESET and is not no effect on the drive of the upper
affected by S_RESET or STOP. 8 address bits. The upper 8 ad-
Am79C971 139
dress pins are always driven, re- ways fully functional as specified
gardless of the state of the in the CSR and BCR sections.
SSIZE32 bit.
Note that the setting of the either the STOP or the SPND bit
SSIZE32 bit has no effect on the is set. The SWSTYLE register will
defined width for I/O resources. contain the value 00h following
I/O resource width is determined H_RESET and will be unaffected
by the state of the DWIO bit by S_RESET or STOP.
(BCR18, bit 7).
CSR60: Previous Transmit Descriptor Address
7-0 SWSTYLE Software Style register. The val- Lower
ue in this register determines the Bit Name Description
style of register and memory re-
sources that shall be used by the 31-16 RES Reserved locations. Written as
Am79C971 controller. The Soft- zeros and read as undefined.
ware Style selection will affect the
interpretation of a few bits within 15-0 PXDAL Contains the lower 16 bits of the
the CSR space, the order of the previous transmit descriptor ad-
descriptor entries and the width of dress pointer. Am79C971 con-
the descriptors and initialization troller has the capability to stack
block entries. multiple transmit frames.
All Am79C971 controller CSR Read/Write accessible only when
bits and BCR bits and all descrip- either the STOP or the SPND bit
tor, buffer, and initialization block is set. These bits are unaffected
entries not cited in Table 26 are by H_RESET, S_RESET, or
unaffected by the Software Style STOP.
selection and are, therefore, al-
Table 26. Software Styles

SWSTYLE Style Initialization Block
[7:0] Name SSIZE32 Entries Descriptor Ring Entries
LANCE/
16-bit software structures, 16-bit software structures,
00h PCnet-ISA 0
non-burst or burst access non-burst access only
controller
01h RES 1 RES RES
PCnet-PCI 32-bit software structures, 32-bit software structures,

02h 1
controller non-burst or burst access non-burst access only
PCnet-PCI 32-bit software structures, 32-bit software structures,

03h 1
controller non-burst or burst access non-burst access only
All Other Reserved Undefined Undefined Undefined
CSR61: Previous Transmit Descriptor Address address pointer. The Am79C971

Upper controller has the capability to
Bit Name Description stack multiple transmit frames.

15-0 PXDAU Contains the upper 16 bits of the by H_RESET, S_RESET, or
previous transmit descriptor STOP.
140 Am79C971
CSR62: Previous Transmit Byte Count 31-16 RES Reserved locations. Written as
Bit Name Description zeros and read as undefined.
15-0 NXBAU Contains the upper 16 bits of the

next transmit buffer address from
which the Am79C971 controller
15-12 RES Reserved locations. will transmit an outgoing frame.
11-0 PXBC Previous Transmit Byte Count. Read/Write accessible only when
This field is a copy of the BCNT either the STOP or the SPND bit
field of TMD1 of the previous is set. These bits are unaffected
transmit descriptor. by H _ R E S E T, S _ R E S E T, o r
STOP.
Read/Write accessible only when CSR66: Next Transmit Byte Count
STOP. 31-16 RES Reserved locations. Written as
CSR63: Previous Transmit Status
15-12 RES Reserved locations. Read and
written as zeros.
31-16 RES Reserved locations. Written as 11-0 NXBC Next Transmit Byte Count. This
zeros and read as undefined. field is a copy of the BCNT field of
TMD1 of the next transmit de-
15-0 PXST Previous Transmit Status. This scriptor.
field is a copy of bits 31-16 of
TMD1 of the previous transmit Read/Write accessible only when
descriptor. either the STOP or the SPND bit
by H_RESET, S_RESET, or CSR67: Next Transmit Status
STOP.
CSR64: Next Transmit Buffer Address Lower
31-16 RES Reserved locations. Written as 15-0 NXST Next Transmit Status. This field is
zeros and read as undefined. a copy of bits 31-16 of TMD1 of
the next transmit descriptor.
15-0 NXBAL Contains the lower 16 bits of the
next transmit buffer address from Read/Write accessible only when
which the Am79C971 controller either the STOP or the SPND bit
will transmit an outgoing frame. is set. These bits are unaffected
is set. These bits are unaffected 7-0 RES Reserved locations. Read and
by H_RESET, S_RESET, or written as zeros. Accessible only
STOP. when either the STOP or the
SPND bit is set.
CSR65: Next Transmit Buffer Address Upper

Am79C971 141
CSR72: Receive Ring Counter be manually altered. The actual

Bit Name Description receive ring length is defined by
the current value in this register.
31-16 RES Reserved locations. Written as The ring length can be defined as
zeros and read as undefined. any value from 1 to 65535.
15-0 RCVRC Receive Ring Counter location. Read/Write accessible only when
Contains a two’s complement bi- either the STOP or the SPND bit
nary number used to number the is set. These bits are unaffected
current receive descriptor. This by H_RESET, S_RESET, or
counter interprets the value in STOP.
CSR76 as pointing to the first de-
CSR78: Transmit Ring Length
scriptor. A counter value of zero
corresponds to the last descriptor Bit Name Description
in the ring.
is set. These bits are unaffected 15-0 XMTRL Transmit Ring Length. Contains
by H_RESET, S_RESET, or the two’s complement of the
STOP. transmit descriptor ring length.
This register is initialized during
CSR74: Transmit Ring Counter the Am79C971 controller initial-
Bit Name Description ization routine based on the value
in the TLEN field of the initializa-
31-16 RES Reserved locations. Written as tion block. However, this register
zeros and read as undefined. can be manually altered. The ac-
tual transmit ring length is defined
15-0 XMTRC Transmit Ring Counter location. by the current value in this regis-
Contains a two’s complement bi- ter. The ring length can be de-
nary number used to number the fined as any value from 1 to
current transmit descriptor. This 65535.
counter interprets the value in
CSR78 as pointing to the first de- Read/Write accessible only when
scriptor. A counter value of zero either the STOP or the SPND bit
corresponds to the last descriptor is set. These bits are unaffected
in the ring. by H_RESET, S_RESET, or
STOP.
either the STOP or the SPND bit CSR80: DMA Transfer Counter and FIFO Threshold
is set. These bits are unaffected Control
by H_RESET, S_RESET, or Bit Name Description
STOP.
CSR76: Receive Ring Length zeros and read as undefined.
31-16 RES Reserved locations. Written as zeros and read as undefined.
13-12 RCVFW[1:0] Receive FIFO Watermark.
15-0 RCVRL Receive Ring Length. Contains RCVFW controls the point at
the two’s complement of the re- which receive DMA is requested
ceive descriptor ring length. This in relation to the number of re-
register is initialized during the ceived bytes in the Receive FIFO.
Am79C971 controller initializa- RCVFW specifies the number of
tion routine based on the value in bytes which must be present
the RLEN field of the initialization (once the frame has been verified
block. However, this register can as a non-runt) before receive
142 Am79C971
DMA is requested. Note however Table 27. Receive Watermark Programming

that, if the network interface is op-
RCVFW[1:0] Bytes Received
erating in half-duplex mode, in or-
der for receive DMA to be 00 16
performed for a new frame, at 01 64
least 64 bytes must have been re- 10 112
ceived. This effectively avoids 11 Reserved
having to react to receive frames
which are runts or suffer a colli- Read/Write accessible only when
sion during the slot time (512 bit either the STOP or the SPND bit
times). If the Runt Packet Accept is set. RCVFW[1:0] is set to a val-
feature is enabled or if the net- ue of 01b (64 bytes) after
work interface is operating in full- H_RESET or S_RESET and is
duplex mode, receive DMA will unaffected by STOP.
be requested as soon as either
the RCVFW threshold is reached, 11-10 XMTSP[1:0] Transmit Start Point. XMTSP
or a complete valid receive frame controls the point at which pream-
is detected (regardless of length). ble transmission attempts to com-
When the FDRPAD (BCR9, bit 2) mence in relation to the number
is set and the Am79C971 control- of bytes written to the MAC
ler is in full-duplex mode, in order Transmit FIFO for the current
to receive DMA to be performed transmit frame. When the entire
for a new frame, at least 64 bytes frame is in the MAC Transmit
must have been received. This FIFO, transmission will start re-
effectively disables the runt pack- gardless of the value in XMTSP.
et accept feature in full duplex. If the network interface is operat-
ing in half-duplex mode, regard-
When operating in the NO-SRAM less of XMTSP, the FIFO will not
mode (no SRAM present), the internally overwrite its data until
Bus Receive FIFO and the MAC at least 64 bytes (or the entire
Receive operate like a single frame if shorter than 64 bytes)
FIFO and the watermark value have been transmitted onto the
selected by RCVFW[1:0] sets the network. This ensures that for
number of bytes that must be collisions within the slot time win-
present in the FIFO before re- dow, transmit data need not be
ceive DMA is requested. rewritten to the Transmit FIFO,
and retries will be handled auton-
NOTE: A “No SRAM configura- omously by the MAC. If the Dis-
tion” is only valid for 10Mb mode. able Retry feature is enabled, or if
In 100Mb mode, SRAM is man- the network is operating in full-du-
datory and must always be used. plex mode, the Am79C971 con-
troller can overwrite the
When operating with an external beginning of the frame as soon as
SRAM, the Bus Receive FIFO, the data is transmitted, because
and the MAC Receive FIFO oper- no collision handling is required in
ate independently on the bus side these modes.
and MAC side of the external
SRAM, respectively. In this case, Note that when an external
the watermark value set by SRAM is being used, if the NOU-
RCVFW[1:0] sets the number of FLO bit (BCR18, bit 11) is set to
bytes that must be present in the 1, there is the additional restric-
Bus Receive FIFO only. See Ta- tion that the complete transmit
ble 27. frame must be DMA’d into the
Am79C971 controller and reside
within a combination of the Bus
Transmit FIFO, the external
SRAM, and the MAC Transmit
FIFO.
Am79C971 143
When an external SRAM is used, When operating in the NO-SRAM

SRAM_SIZE > 0, there is a re- mode (no SRAM present),
striction that the number of bytes SRAM_SIZE set to 0, the Bus
written is a combination of bytes Transmit FIFO and the MAC
written into the Bus Transmit Transmit FIFO operate like a sin-
FIFO and the MAC Transmit gle FIFO and the watermark val-
FIFO. The Am79C971 controller ue selected by XMTFW[1:0] sets
supports a mode that will wait un- the number of FIFO byte loca-
til a full packet is available before tions that must be available in the
commencing with the transmis- FIFO before receive DMA is re-
sion of preamble. This mode is quested.
useful in a system where high la-
tencies cannot be avoided. See NOTE: A “No SRAM configura-
Table 28. tion” is only valid for 10Mb mode.
In 100Mb mode, SRAM is man-
datory and must always be used.
Table 28. Transmit Start Point Programming When operating with an external
XMTSP[1:0] SRAM_SIZE Bytes Written SRAM, the Bus Transmit FIFO
00 0 20 and the MAC Transmit FIFO op-
erate independently on the bus
01 0 64
side and MAC side of the external
10 0 128 SRAM, respectively. In this case,
11 0 248 the watermark value set by XMT-
00 >0 44 FW[1:0] sets the number of FIFO
01 >0 64 byte locations that must be avail-
10 >0 128 able in the Bus Transmit FIFO.
See Table 29.
11 >0 Full Packet
NOTE: A “No SRAM configuration” is

only valid for 10Mb mode. In 100Mb Table 29. Transmit Watermark Programming
mode, SRAM is mandatory and must
XMTFW[1:0] Bytes Available
always be used.
00 16
Read/Write accessible only when 01 64
10 108
is set. XMTSP is set to a value of
01b (64 bytes) after H_RESET or 11 Reserved
STOP. Read/Write accessible only when
9-8 XMTFW[1:0] Transmit FIFO Watermark. XMT- is set. XMTFW is set to a value of
FW specifies the point at which 00b (16 bytes) after H_RESET or
transmit DMA is requested, S_RESET and is unaffected by
based upon the number of bytes STOP.
that could be written to the Trans-
7-0 DMATC[7:0] DMA Transfer Counter. Writing
mit FIFO without FIFO overflow.
and reading to this field has no ef-
Transmit DMA is requested at
fect. Use MAX_LAT and
any time when the number of
MIN_GNT in the PCI configura-
bytes specified by XMTFW could
tion space.
be written to the FIFO without
causing Transmit FIFO overflow,
CSR82: Transmit Descriptor Address Pointer Lower
and the internal microcode en-
gine has reached a point where Bit Name Description
the Transmit FIFO is checked to
determine if DMA servicing is re- 31-16 RES Reserved locations. Written as
quired. zeros and read as undefined.
144 Am79C971
15-0 TXDAPL Contains the lower 16 bits of the issuing increment commands to
transmit descriptor address cor- increment the memory address
responding to the last buffer of for sequential operations. The
the previous transmit frame. If the DMABAU register is undefined
previous transmit frame did not until the first Am79C971 control-
use buffer chaining, then TXDA- ler DMA operation.
PL contains the lower 16 bits of
the previous frame’s transmit de- Read/Write accessible only when
scriptor address. either the STOP or the SPND bit
When both the STOP or SPND by H_RESET, S_RESET, or
bits are cleared, this register is STOP.
updated by Am79C971 controller
immediately before a transmit de-
scriptor write.
Read accessible always. Write

accessible through the PXDAL CSR86: Buffer Byte Counter
bits (CSR60) when the STOP or Bit Name Description
SPND bit is set. TXDAPL is set to
0 by H_RESET and are unaffect- 31-16 RES Reserved locations. Written as
ed by S_RESET or STOP. zeros and read as undefined.
CSR84: DMA Address Register Lower 15-12 RES Reserved. Read and written with
Bit Name Description ones.
11-0 DMABC DMA Byte Count Register. Con-

tains the two's complement of the
current size of the remaining
15-0 DMABAL This register contains the lower transmit or receive buffer in
16 bits of the address of system bytes. This register is increment-
memory for the current DMA cy- ed by the Bus Interface Unit. The
cle. The Bus Interface Unit con- DMABC register is undefined un-
trols the Address Register by til written.
issuing increment commands to
increment the memory address
for sequential operations. The
DMABAL register is undefined
until the first Am79C971 control-
STOP.
ler DMA operation.
CSR88: Chip ID Register Lower
either the STOP or the SPND bit Bit Name Description
by H_RESET, S_RESET, or 31-28 VER Version. This 4-bit pattern is
STOP. silicon-revision dependent.
CSR85: DMA Address Register Upper Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. Write opera-
tions are ignored.
zeros and read as undefined. 27-12 PARTID Part number. The 16-bit code for
the Am79C971 controller is 0010
15-0 DMABAU This register contains the upper
0110 0010 0011b (2623h).
16 bits of the address of system
memory for the current DMA cy- This register is exactly the same
cle. The Bus Interface Unit con- as the Device ID register in the
trols the Address Register by JTAG description. It is, however,
Am79C971 145
a different ID as that stored in the CSR92: Ring Length Conversion

Device ID register in the PCI con- Bit Name Description
figuration space.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. PARTID is read 15-0 RCON Ring Length Conversion Regis-
only. Write operations are ig- ter. This register performs a ring
nored. length conversion from an encod-
ed value as found in the initializa-
11-1 MANFID Manufacturer ID. The 11-bit man-
tion block to a two’s complement
ufacturer code for AMD is
value used for internal counting.
00000000001b. This code is per
By writing bits 15-12 with an en-
the JEDEC Publication 106-A.
coded ring length, a two’s com-
Note that this code is not the plemented value is read. The
same as the Vendor ID in the PCI RCON register is undefined until
configuration space. written.
Read accessible only when either Read/Write accessible only when

the STOP or the SPND bit is set. either the STOP or the SPND bit
VER is read only. MANFID is is set. These bits are unaffected
read only. Write operations are by H_RESET, S_RESET, or
ignored. STOP.
0 ONE Always a logic 1. CSR100: Bus Timeout

Read accessible only when either
the STOP or the SPND bit is set. 31-16 RES Reserved locations. Written as
VER is read only. ONE is read zeros and read as undefined.
only. Write operations are ig-
nored. 15-0 MERRTO This register contains the value of
the longest allowable bus latency
CSR89: Chip ID Register Upper (interval between assertion of
Bit Name Description REQ and assertion of GNT) that a
system may insert into an
31-16 RES Reserved locations. Read as un- Am79C971 controller master
defined. transfer. If this value of bus laten-
cy is exceeded, then a MERR will
15-12 VER Version. This 4-bit pattern is be indicated in CSR0, bit 11, and
silicon-revision dependent. an interrupt may be generated,
depending upon the setting of the
Read accessible only when either MERRM bit (CSR3, bit 11) and
the STOP or the SPND bit is set. the IENA bit (CSR0, bit 6).
VER is read only. VER is read
only. Write operations are ig- The value in this register is inter-
nored. preted as the unsigned number of
XTAL1 clock periods divided by
11-0 PARTIDU Upper 12 bits of the Am79C971 two, (i.e., the value in this register
controller part number, i.e., 0010 is given in 0.1 µs increments.) For
0110 0010b (262h). example, the value 0600h (1536
decimal) will cause a MERR to be
Read accessible only when either indicated after 153.6 µs of bus la-
the STOP or the SPND bit is set. tency. A value of 0 will allow an
VER is read only. PARTIDU is infinitely long bus latency, i.e.,
read only. Write operations are bus timeout error will never oc-
ignored. cur.
146 Am79C971
Read/Write accessible only when 0 RCVALGN Receive Packet Align. When set,
either the STOP or the SPND bit this bit forces the data field of ISO
is set. This register is set to 8802-3 (IEEE/ANSI 802.3) pack-
0600h by H_RESET or ets to align to 0. MOD 4 address
S_RESET and is unaffected by boundaries (i.e., DWord aligned
STOP. addresses). It is important to note
that this feature will only function
CSR112: Missed Frame Count correctly if all receive buffer
Bit Name Description boundaries are DWord aligned
and all receive buffers have 0
31-16 RES Reserved locations. Written as MOD 4 lengths. In order to ac-
zeros and read as undefined. complish the data alignment, the
Am79C971 controller simply in-
15-0 MFC Missed Frame Count. Indicates serts two bytes of random data at
the number of missed frames. the beginning of the receive pack-
et (i.e., before the ISO 8802-3
MFC will roll over to a count of 0 (IEEE/ANSI 802.3) destination
from the value 65535. The MFCO address field). The MCNT field
bit of CSR4 (bit 8) will be set each reported to the receive descriptor
time that this occurs. will not include the extra two
bytes.
Read accessible always. MFC is
read only, write operations are ig- Read/Write accessible always.
nored. MFC is cleared by RCVALGN is cleared by
H_RESET or S_RESET or by H_RESET or S_RESET and is
setting the STOP bit. not affected by STOP.
CSR114: Receive Collision Count CSR124: Test Register 1

Bit Name Description This register is used to place the Am79C971 controller
into various test modes. The Runt Packet Accept is the
31-16 RES Reserved locations. Written as only user accessible test mode. All other test modes are
zeros and read as undefined. for AMD internal use only.
15-0 RCC Receive Collision Count. Indi- Bit Name Description

cates the total number of colli-
sions encountered by the 31-16 RES Reserved locations. Written as
receiver since the last reset of the zeros and read as undefined.
counter.
RCC will roll over to a count of 0 zeros and read as undefined.
from the value 65535. The
RCVCCO bit of CSR4 (bit 5) will 3 RPA Runt Packet Accept. This bit
be set each time that this occurs. forces the Am79C971 controller
to accept runt packets (packets
Read accessible always. RCC is shorter than 64 bytes).
read only, write operations are ig-
nored. RCC is cleared by Read accessible always; write
H_RESET or S_RESET, or by accessible only when STOP is
setting the STOP bit. set to 1. RPA is cleared by
CSR122: Advanced Feature Control not affected by STOP.
Bit Name Description 2-0 RES Reserved locations. Written as
zeros and read as undefined. CSR125: MAC Enhanced Configuration Control
15-1 RES Reserved locations. Written as Bit Name Description

Am79C971 147
31-16 RES Reserved locations. Written as 7-0 IFS1 InterFrameSpacingPart1. Chang-

zeros and read as undefined. ing IFS1 allows the user to pro-
gram the value of the InterFrame-
15-8 IPG Inter Packet Gap. Changing IPG SpacePart1 timing. The
allows the user to program the Am79C971 controller sets the de-
Am79C971 controller for aggres- fault value at 60 bit times (3ch).
siveness on a network. By chang- See the subsection on Medium
ing the default value of 96 bit Allocation in the section Media
times (6oh) the user can adjust Access Management for more
the fairness or aggressiveness of details. The equation for setting
the Am79C971 MAC on the net- IFS1 when IPG ≥ 96 bit times is:
work. By programming a lower
number of bit times other then the IFS1 = IPG - 36 bit times
ISO/IEC 8802-3 standard re-
quires, the Am79C971 MAC will Note: Programming of the IPG
become more aggressive on the should be done in nibble intervals
network. This aggressive nature instead of absolute bit times due
will give rise to the Am79C971 to the MII. The decimal and hex
controller possibly “capturing the values do not match due to de-
network” at times by forcing other lays in the part used to make up
less aggressive nodes to defer. the final IPG.
By programming a larger number
of bit times, the Am79C971 MAC Changes should be added or
will become less aggressive on subtracted from the provided hex
the network and may defer more value on a one-for-one basis.
often than normal. The perfor- Due to changes in synchroniza-
mance of the Am79C971 control- tion delays internally through dif-
ler may decrease as the IPG ferent network ports, the IFS1
value is increased from the de- can be off by as much as +12 bit
fault value. times.
Note: Programming of the IPG Read accessible always. Write

should be done in nibble intervals accessible only when the SPND
instead of absolute bit times. The bit or the STOP bit is set to 1.
decimal and hex values do not IFS1 is set to 3ch (60 bit times) by
match due to delays in the part H_RESET or S_RESET and is
used to make up the final IPG. not affected by STOP.
Changes should be added or sub-
tracted from the provided hex val- Bus Configuration Registers
ue on a one-for-one basis. The Bus Configuration Registers (BCR) are used to
program the configuration of the bus interface and
CAUTION: Use this parameter
other special features of the Am79C971 controller that
with care. By lowering the IPG
are not related to the IEEE 8802-3 MAC functions. The
below the ISO/IEC 8802-3 stan-
BCRs are accessed by first setting the appropriate
dard 96 bit times, the
RAP value and then by performing a slave access to
Am79C971 controller can inter-
the BDP. See Table 30.
rupt normal network behavior.
All BCR registers are 16 bits in width in Word I/O mode
Read accessible always. Write (DWIO = 0, BCR18, bit 7) and 32 bits in width in DWord
accessible when the STOP bit is I/O mode (DWIO = 1). The upper 16 bits of all BCR reg-
set to 1. IPG is set to 60h (96 Bit isters is undefined when in DWord I/O mode. These
times) by H_RESET or bits should be written as zeros and should be treated
S_RESET and is not affected by as undefined when read. The default value given for
STOP. any BCR is the value in the register after H_RESET.
Some of these values may be changed shortly after
H_RESET when the contents of the external EEPROM
is automatically read in. None of the BCR register val-
ues are affected by the assertion of the STOP bit.
148 Am79C971
Note that several registers have no default value. Writing to these registers have no effect on the opera-
BCR0, BCR1, BCR3, BCR8, BCR10-17, and BCR21 tion of the Am79C971 controller.
are reserved and have undefined values. BCR2 and
Writes to those registers marked as “Reserved” will
BCR34 are not observable without first being pro-
have no effect. Reads from these locations will produce
grammed through the EEPROM read operation or a
undefined values.
user register write operation.
BCR0, BCR1, BCR16, BCR17, and BCR21 are regis-
ters that are used by other devices in the PCnet family.
Table 30. BCR Registers
Programmability
RAP Mnemonic Default Name User EEPROM
0 MSRDA 0005h Reserved No No
1 MSWRA 0005h Reserved No No
2 MC 0002h Miscellaneous Configuration Yes Yes
3 Reserved N/A Reserved No No
4 LED0 00C0h LED0 Status Yes Yes
5 LED1 0084h LED1 Status Yes Yes
9 FDC 0000h Full-Duplex Control Yes Yes
10-15 Reserved N/A Reserved No No
16 IOBASEL N/A Reserved No No
17 IOBASEU N/A Reserved No No
18 BSBC 9001h Burst and Bus Control Yes Yes
19 EECAS 0002h EEPROM Control and Status Yes No
20 SWS 0000h Software Style Yes No
21 INTCON N/A Reserved No No
22 PCILAT FF06h PCI Latency Yes Yes
23 PCISID 0000h PCI Subsystem ID No Yes
24 PCISVID 0000h PCI Subsystem Vendor ID No Yes
25 SRAMSIZ 0000h SRAM Size Yes Yes
26 SRAMB 0000h SRAM Boundary Yes Yes
27 SRAMIC 0000h SRAM Interface Control Yes Yes
28 EBADDRL N/A Expansion Bus Address Lower Yes No
29 EBADDRU N/A Expansion Bus Address Upper Yes No
30 EBD N/A Expansion Bus Data Port Yes No
31 STVAL FFFFh Software Timer Value Yes No
32 MIICAS 0000h MII Control and Status Yes Yes
33 MIIADDR 0000h MII Address Yes Yes
34 MIIMDR N/A MII Management Data Yes No
35 PCIVID 1022h PCI Vendor ID No Yes
BCR0: Master Mode Read Active 15-0 MSRDA Reserved locations. After
Bit Name Description H_RESET, the value in this regis-
ter will be 0005h. The setting of
31-16 RES Reserved locations. Written as this register has no effect on any
zeros and read as undefined. Am79C971 controller function. It
is only included for software com-
patibility with other PCnet family
devices.
Read always. MSRDA is read

only. Write operations have no ef-
fect.
Am79C971 149
BCR1: Master Mode Write Active Read/Write accessible always.

Bit Name Description LEDPE is cleared to 0 by
H_RESET and is unaffected by
31-16 RES Reserved locations. Written as S_RESET or by setting the STOP
zeros and read as undefined. bit.
15-0 MSWRA Reserved locations. After 11-9 RES Reserved locations. Written and
H_RESET, the value in this regis- read as zeros.
ter will be 0005h. The setting of
8 APROMWE Address PROM Write Enable.
this register has no effect on any
The Am79C971 controller con-
Am79C971 controller function. It
tains a shadow RAM on board for
is only included for software com-
storage of the first 16 bytes load-
patibility with other PCnet family
ed from the serial EEPROM.
devices.
Accesses to Address PROM I/O
Read always. MSWRA is read Resources will be directed toward
only. Write operations have no ef- this RAM. When APROMWE is
fect. set to 1, then write access to the
shadow RAM will be enabled.
BCR2: Miscellaneous Configuration
Note: Bits 15-0 in this register are programmable APROMWE is cleared to 0 by
through the EEPROM. H_RESET and is unaffected by
Bit Name Description S_RESET or by setting the STOP
bit.
zeros and read as undefined. 7 INTLEVEL Interrupt Level. This bit allows the
interrupt output signals to be pro-
15 RES Reserved location. Written and grammed for level or edge-
read as zeros. sensitive applications.
14 TMAULOOP When set, this bit allows external When INTLEVEL is cleared to 0,
loopback packets to pass onto the INTA pin is configured for
the network through the T-MAU level-sensitive applications. In
interface, if the T-MAU interface this mode, an interrupt request is
has been selected. If the T-MAU signaled by a low level driven on
interface has not been selected, the INTA pin by the Am79C971
then this bit has no effect. controller. When the interrupt is
cleared, the INTA pin is tri-stated
Read/Write accessible always. by the Am79C971 controller and
TMAULOOP is reset to 0 by allowed to be pulled to a high lev-
H_RESET and is unaffected by el by an external pullup device.
S_RESET or STOP. This mode is intended for sys-
tems which allow the interrupt
13 RES Reserved location. Written and signal to be shared by multiple
read as zero. devices.
12 LEDPE LED Program Enable. When When INTLEVEL is set to 1, the
LEDPE is set to 1, programming INTA pin is configured for edge-
of the LED0 (BCR4), LED1 sensitive applications. In this
(BCR5), LED2 (BCR6), and mode, an interrupt request is sig-
LED3 (BCR7) registers is en- naled by a high level driven on
abled. When LEDPE is cleared to the INTA pin by the Am79C971
0, programming of LED0 (BCR4), controller. When the interrupt is
LED1 (BCR5), LED2 (BCR6), cleared, the INTA pin is driven to
and LED3 (BCR7) registers is a low level by the Am79C971
disabled. Writes to those regis- controller. This mode is intended
ters will be ignored. for systems that do not allow
150 Am79C971
interrupt channels to be shared dia interface port. If ASEL has

by multiple devices. been set to a 1, then when the MI-
IPD bit (BCR32, bit 14) is 1, the
INTLEVEL should not be set to 1 MII port is selected. If the MIIPD
when the Am79C971 controller is bit is 0, and then, if the 10BASE-
used in a PCI bus application. T transceiver is in the link pass
state (due to receiving valid frame
Read/Write accessible always. data and/or Link Test pulses or
INTLEVEL is cleared to 0 by the DLNKTST bit is set), the
H_RESET and is unaffected by 10BASE-T port will be used. If the
S_RESET or by setting the STOP MIIPD bit is 0 and the 10BASE-T
bit. port is in the Link Fail state, the
AUI port will be used. Switching
between the ports will not occur
during transmission to avoid any
3 EADISEL EADI Select. When set to 1, this type of fragment generation.
bit enables the three EADI inter-
The network port configurations
face pins that are multiplexed
are found in Table 31.
with other functions. EESK/LED1
becomes SFBD, EEDO/LED3 When ASEL is set to 1 and the
becomes SRD, LED2 becomes MIIPD bit is 0, Link Beat Pulses
SRDCLK, and SLEEP becomes will be transmitted on the
EAR. See the section on External 10BASE-T port, regardless of the
Address Detection for more de- state of Link Status. When ASEL
tails. is reset to 0, Link Beat Pulses will
only be transmitted on the
10BASE-T port when the PORT-
EADISEL is cleared by
SEL bits of the Mode Register
(CSR15) have selected 10BASE-
T as the active port.
bit.
When ASEL is set to a 0, then the
2 AWAKE This bit selects one of two differ-
selected network port will be de-
ent sleep modes.
termined by the settings of the
If AWAKE is set to 1 and the PORTSEL bits of CSR15. When
SLEEP pin is asserted, the ASEL is set to 1, the selected net-
Am79C971 controller goes into work port may be determined
snooze mode. If AWAKE is through software by reading the
cleared to 0 and the SLEEP pin is MIIPD bit and, if MIIPD is 0, read-
asserted, the Am79C971 control- ing the link status through BCR4
ler goes into coma mode. See the or another LED Control register if
section Power Saving Modes for it is programmed for link status.
more details. The PORTSEL[1:0] bits do not
reflect the selected network port
This bit only has meaning when when ASEL is 1. Read/Write ac-
the 10BASE-T network interface cessible always. ASEL is set to 1
is selected. by H_RESET and is unaffected
by S_RESET or STOP.
AWAKE is cleared to 0 by 0 XMAUSEL Reserved location. Read/Write
H_RESET and is unaffected by accessible always. This reserved
S_RESET or by setting the STOP location is cleared by H_RESET
bit. and is unaffected by S_RESET or
STOP. Writing a 1 to this bit has
1 ASEL Auto Select. When set, the no effect on the operation of the
Am79C971 controller will auto- Am79C971 controller.
matically select the operating me-
Am79C971 151
Table 31. Network Port Configuration

ASEL Link Status MII Status Network
PORTSEL[1:0] (BCR2[1]) (of 10BASE-T) (BCR32[14]) Port
XX 1 Fail 0 AUI
XX 1 Pass 0 10BASE-T
XX 1 Don’t Care 1 MII
00 0 Don’t Care Don’t Care AUI
01 0 Don’t Care Don’t Care 10BASE-T
10 0 Don’t Care Don’t Care GPSI
11 0 Don’t Care Don’t Care MII
BCR4: LED0 Status disabled and allowed to float high
BCR4 controls the function(s) that the LED0 pin dis- whenever the OR of the enabled
plays. Multiple functions can be simultaneously en- signals is false (i.e., the LED out-
abled on this LED pin. The LED display will indicate the put will be an Open Drain output
logical OR of the enabled functions. BCR4 defaults to and the output value will be the
Link Status (LNKST) with pulse stretcher enabled inverse of the LEDOUT status
(PSE = 1) and is fully programmable. bit).
Note: When LEDPE (BCR2, bit 12) is set to 1, pro- When this bit has the value 1,
gramming of the LED0 Status register is enabled. then the LED pin will be driven to
When LEDPE is cleared to 0, programming of the a HIGH level whenever the OR of
LED0 register is disabled. Writes to those registers will the enabled signals is true, and
be ignored. the LED pin will be driven to a
Note: Bits 15-0 in this register are programmable LOW level whenever the OR of
through the EEPROM. the enabled signals is false (i.e.,
the LED output will be a Totem
Bit Name Description Pole output and the output value
will be the same polarity as the
31-16 RES Reserved locations. Written as LEDOUT status bit.).
The setting of this bit will not ef-
15 LEDOUT This bit indicates the current fect the polarity of the LEDOUT
(non-stretched) value of the LED bit for this register.
output pin. A value of 1 in this bit
indicates that the OR of the en- Read/Write accessible always.
abled signals is true. LEDPOL is cleared by H_RESET
The logical value of the LEDOUT or setting the STOP bit.
status signal is determined by the
settings of the individual Status 13 LEDDIS LED Disable. This bit is used to
Enable bits of the LED register disable the LED output. When
(bits 8 and 6-0). LEDDIS has the value 1, then the
LED output will always be dis-
Read accessible always. This bit abled. When LEDDIS has the val-
is read only; writes have no ef- ue 0, then the LED output value
fect. LEDOUT is unaffected by will be governed by the LEDOUT
H_RESET, S_RESET, or STOP. and LEDPOL values.
14 LEDPOL LED Polarity. When this bit has Read/Write accessible always.
the value 0, then the LED pin will LEDDIS is cleared by H_RESET
be driven to a LOW level whenev- and is not affected by S_RESET
er the OR of the enabled signals or setting the STOP bit.
is true, and the LED pin will be
152 Am79C971
12 100E 100 Mbps Enable. When this bit network port, the DXCVR output
is set to 1, a value of 1 is passed is always deasserted.
to the LEDOUT bit in this register
when the Am79C971 controller is Read/Write accessible always.
operating at 100 Mbps mode. The DXCVRCTL is cleared by
indication is valid with both the in- H_RESET and is unaffected by
ternal and external PHYs. S_RESET or by setting the STOP
bit.
9 MPSE Magic Packet Status Enable.

Read/Write accessible always. When this bit is set to 1, a value of
100E is cleared by H_RESET 1 is passed to the LEDOUT bit in
and is not affected by S_RESET this register when Magic Packet
or setting the STOP bit. frame mode is enabled and a
Magic Packet frame is detected
11 MIISE Media Independent Interface Se- on the network.
lected Enable. Indicates when the
MII interface is selected. This will Read/Write accessible always.
be set when either the Manage- MPSE is cleared by H_RESET
ment Port State Machine is se- and is not affected by S_RESET
lecting the MII or when ASEL or setting the STOP bit.
(BCR2, bit1) is disabled and
PORTSEL (CSR15, bits 8-7) se- 8 FDLSE Full-Duplex Link Status Enable.
lects the MII. This could control Indicates the Full-Duplex Link
relays to switch in and out appro- Test Status. When this bit is set,
priate filters or could control an a value of 1 is passed to the LED-
external PHY when sharing an OUT signal when the Am79C971
RJ45 connector. controller is functioning in a Link
Pass state and full-duplex opera-
Read/Write accessible always. tion is enabled. When the
MIISE is cleared by H_RESET Am79C971 controller is not func-
and is not affected by S_RESET tioning in a Link Pass state with
or setting the STOP bit. full-duplex operation being en-
abled, a value of 0 is passed to
10 DXCVRCTL DXCVR Control. When the AUI the LEDOUT signal.
interface is the active network
port, DXCVRCTL controls the as- When the 10BASE-T port is ac-
sertion of the LED0 output. The tive, a value of 1 is passed to the
polarity of the asserted state is LEDOUT signal whenever the
controlled by the LEDPOL bit Link Test Function (described in
(BCR4, bit 14). The LED0 pin can the T-MAU section) detects a
be used to control a DC-to-DC Link Pass state and the FDEN
converter in applications that (BCR9, bit 0) bit is set. When the
want to connect a 10BASE2 AUI port is active, a value of 1 is
MAU, as well as a standard DB15 passed to the LEDOUT signal
AUI connector to the Am79C971 whenever full-duplex operation
AUI port. When DXCVRCTL is on the AUI port is enabled (both
set to 1, the LED0 output will be FDEN and AUIFD bits in BCR9
asserted. This could be used to are set to 1). When the MII port is
enable a DC-to-DC converter for active, a value of 1 is passed to
10BASE2 MAUs (assuming the the LEDOUT signal whenever
enable input of the DC-to-DC full-duplex operation on the MII
converter is active high and LED- port is enabled (FDEN bit in
POL is cleared to 0). When DX- BCR9 is set to 1).
CVRCTL is cleared to 0, the
LED0 output will be deasserted. Read/Write accessible always.
This would power down the DC- FDLSE is cleared by H_RESET
to-DC converter. When the and is not affected by S_RESET
10BASE-T interface is the active or setting the STOP bit.
Am79C971 153
7 PSE Pulse Stretcher Enable. When Read/Write accessible always.

this bit is set, the LED illumination XMTE is cleared by H_RESET
time is extended for each new oc- and is not affected by S_RESET
currence of the enabled function or setting the STOP bit.
for this LED output. A value of 0
disables the pulse stretcher. 3 RXPOLE Receive Polarity Status Enable.
When this bit is set, a value of 1 is
Read/Write accessible always. passed to the LEDOUT bit in this
PSE is set to 1 by H_RESET and register when the polarity of the
is not affected by S_RESET or RXD± pair has not been re-
setting the STOP bit. versed.
6 LNKSE Link Status Enable. When this bit Receive polarity indication is val-
is set, a value of 1 will be passed id only if the T-MAU is in link pass
to the LEDOUT bit in this register state.
when the T-MAU mode is in Link
Pass state. When the T-MAU is in Read/Write accessible always.
Link Fail state, a value of 0 is RXPOLE is cleared by H_RESET
passed to the LEDOUT bit. This and is not affected by S_RESET
bit does not reflect the link status or setting the STOP bit.
of the external PHY.
2 RCVE Receive Status Enable. When
The function of this bit is masked this bit is set, a value of 1 is
if the 10BASE-T port is operating passed to the LEDOUT bit in this
in full-duplex mode. This allows a register when there is receive ac-
Half-Duplex Link Status LED and tivity on the network.
a Full-Duplex Link Status LED at
the same time. Read/Write accessible always.
RCVE is cleared by H_RESET
Read/Write accessible always. and is not affected by S_RESET
LNKSE is set to 1 by H_RESET or setting the STOP bit.
or setting the STOP bit. 1 JABE Jabber Status Enable. When this
bit is set, a value of 1 is passed to
5 RCVME Receive Match Status Enable. the LEDOUT bit in this register
When this bit is set, a value of 1 is when the Am79C971 controller is
passed to the LEDOUT bit in this jabbering on the network.
register when there is receive ac-
tivity on the network that has Read/Write accessible always.
passed the address match func- JABE is cleared by H_RESET
tion for this node. All address and is not affected by S_RESET
matching modes are included: or setting the STOP bit.
physical, logical filtering, broad-
0 COLE Collision Status Enable. When
cast and promiscuous.
this bit is set, a value of 1 is
Read/Write accessible always. passed to the LEDOUT bit in this
RCVME is cleared by H_RESET register when there is collision
and is not affected by S_RESET activity on the network. The activ-
or setting the STOP bit. ity on the collision inputs to the
AUI ports within the first 4 µs after
4 XMTE Transmit Status Enable. When every transmission for the pur-
this bit is set, a value of 1 is pose of SQE testing will not
passed to the LEDOUT bit in this cause the LEDOUT bit to be set.
register when there is transmit
activity on the network. Read/Write accessible always.
COLE is cleared by H_RESET
154 Am79C971
BCR5: LED1 Status Pole output and the output value

BCR5 controls the function(s) that the LED1 pin dis- will be the same polarity as the
plays. Multiple functions can be simultaneously en- LEDOUT status bit).
abled on this LED pin. The LED display will indicate the
The setting of this bit will not ef-
logical OR of the enabled functions. BCR5 defaults to
fect the polarity of the LEDOUT
Receive Status (RCV) with pulse stretcher enabled
bit for this register.
(PSE = 1) and is fully programmable.
Note: When LEDPE (BCR2, bit 12) is set to 1, pro- Read/Write accessible always.
gramming of the LED1 Status register is enabled. LEDPOL is cleared by H_RESET
When LEDPE is cleared to 0, programming of the and is not affected by S_RESET
LED1 register is disabled. Writes to those registers will or setting the STOP bit.
be ignored.
13 LEDDIS LED Disable. This bit is used to
Note: Bits 15-0 in this register are programmable disable the LED output. When
through the EEPROM. LEDDIS has the value 1, then the
Bit Name Description LED output will always be dis-
abled. When LEDDIS has the val-
31-16 RES Reserved locations. Written as ue 0, then the LED output value
zeros and read as undefined. will be governed by the LEDOUT
and LEDPOL values.
15 LEDOUT This bit indicates the current
(non-stretched) value of the LED Read/Write accessible always.
output pin. A value of 1 in this bit LEDDIS is cleared by H_RESET
indicates that the OR of the en- and is not affected by S_RESET
abled signals is true. or setting the STOP bit.
The logical value of the LEDOUT 12 100E 100 Mbps Enable. When this bit
status signal is determined by the is set to 1, a value of 1 is passed
settings of the individual Status to the LEDOUT bit in this register
Enable bits of the LED register when the Am79C971 controller is
(bits 8 and 6-0). operating at 100 Mbps mode. The
indication is valid with both the in-
Read accessible always. This bit ternal and external PHYs.
is read only, writes have no ef-
fect. LEDOUT is unaffected by Read/Write accessible always.
H_RESET, S_RESET, or STOP. 100E is cleared by H_RESET
14 LEDPOL LED Polarity. When this bit has or setting the STOP bit.
the value 0, then the LED pin will
be driven to a LOW level whenev- 11 MIISE Media Independent Interface Se-
er the OR of the enabled signals lected Enable. Indicates when the
is true, and the LED pin will be MII interface is selected. This will
disabled and allowed to float high be set when either the Manage-
whenever the OR of the enabled ment Port State Machine is se-
signals is false (i.e., the LED out- lecting the MII or when ASEL
put will be an Open Drain output (BCR2, bit1) is disabled and
and the output value will be the PORTSEL (CSR15, bits 8-7) se-
inverse of the LEDOUT status lects the MII. This could control
bit). relays to switch in and out appro-
priate filters or could control an
When this bit has the value 1, external PHY when sharing an
then the LED pin will be driven to RJ45 connector.
a HIGH level whenever the OR of
the enabled signals is true, and Read/Write accessible always.
the LED pin will be driven to a MIISE is cleared by H_RESET
LOW level whenever the OR of and is not affected by S_RESET
the enabled signals is false (i.e., or setting the STOP bit.
the LED output will be a Totem
Am79C971 155
10 DXCVRCTL DXCVR Control. When the AUI full-duplex operation being en-
interface is the active network abled, a value of 0 is passed to
port, DXCVRCTL controls the as- the LEDOUT signal.
sertion of the LED1 output. The
polarity of the asserted state is When the 10BASE-T port is ac-
controlled by the LEDPOL bit tive, a value of 1 is passed to the
(BCR4, bit 14). The LED1 pin can LEDOUT signal whenever the
be used to control a DC-to-DC Link Test Function (described in
converter in applications that the T-MAU section) detects a
want to connect a 10BASE2 Link Pass state and the FDEN
MAU, as well as a standard DB15 (BCR9, bit 0) bit is set. When the
AUI connector to the Am79C971 AUI port is active, a value of 1 is
AUI port. When DXCVRCTL is passed to the LEDOUT signal
set to 1, the LED1 output will be whenever full-duplex operation
asserted. This could be used to on the AUI port is enabled (both
enable a DC-to-DC converter for FDEN and AUIFD bits in BCR9
10BASE2 MAUs (assuming the are set to 1).
enable input of the DC-to-DC
converter is active high and LED- Read/Write accessible always.
POL is cleared to 0). When DX- FDLSE is cleared by H_RESET
CVRCTL is cleared to 0, the and is not affected by S_RESET
LED1 output will be deasserted. or setting the STOP bit.
This would power down the DC-
7 PSE Pulse Stretcher Enable. When
to-DC converter. When the
this bit is set, the LED illumination
10BASE-T interface is the active
time is extended for each new oc-
network port, the DXCVR output
currence of the enabled function
is always deasserted.
for this LED output. A value of 0
Read/Write accessible always. disables the pulse stretcher.
DXCVRCTL is cleared by
PSE is set to 1 by H_RESET and
is not affected by S_RESET or
bit.
setting the STOP bit.
6 LNKSE Link Status Enable. When this bit
When this bit is set to 1, a value of
is set, a value of 1 will be passed
1 is passed to the LEDOUT bit in
this register when Magic Packet
when the T-MAU is in Link Pass
mode is enabled and a Magic
state. When the T-MAU is in Link
Packet frame is detected on the
Fail state, a value of 0 is passed
network.
to the LEDOUT bit. This bit does
Read/Write accessible always. not reflect the link status of the
MPSE is cleared by H_RESET external PHY.
The function of this bit is masked
if the 10BASE-T port is operating
8 FDLSE Full-Duplex Link Status Enable. in full-duplex mode. This allows a
Indicates the Full-Duplex Link Half-Duplex Link Status LED and
Test Status. When this bit is set, a Full-Duplex Link Status LED at
a value of 1 is passed to the LED- the same time.
OUT signal when the Am79C971
controller is functioning in a Link
LNKSE is cleared by H_RESET
Pass state and full-duplex opera-
tion is enabled. When the
Am79C971 controller is not func-
tioning in a Link Pass state with
156 Am79C971
5 RCVME Receive Match Status Enable. Read/Write accessible always.

When this bit is set, a value of 1 is JABE is cleared by H_RESET
passed to the LEDOUT bit in this and is not affected by S_RESET
register when there is receive ac- or setting the STOP bit.
tivity on the network that has
passed the address match func- 0 COLE Collision Status Enable. When
tion for this node. All address this bit is set, a value of 1 is
matching modes are included: passed to the LEDOUT bit in this
physical, logical filtering, broad- register when there is collision
cast, and promiscuous. activity on the network. The activ-
ity on the collision inputs to the
Read/Write accessible always. AUI port within the first 4 µs after
RCVME is cleared by H_RESET every transmission for the pur-
and is not affected by S_RESET pose of SQE testing will not
or setting the STOP bit. cause the LEDOUT bit to be set.
4 XMTE Transmit Status Enable. When Read/Write accessible always.

this bit is set, a value of 1 is COLE is cleared by H_RESET
passed to the LEDOUT bit in this and is not affected by S_RESET
register when there is transmit or setting the STOP bit.
activity on the network.
BCR6: LED2 Status
Read/Write accessible always. BCR6 controls the function(s) that the LED2 pin dis-
XMTE is cleared by H_RESET plays. Multiple functions can be simultaneously en-
and is not affected by S_RESET abled on this LED pin. The LED display will indicate the
or setting the STOP bit. logical OR of the enabled functions. BCR6 defaults to
Receive Polarity Status (RXPOL) with pulse stretcher
3 RXPOLE Receive Polarity Status Enable.
enabled (PSE = 1) and is fully programmable.
passed to the LEDOUT bit in this Note: When LEDPE (BCR2, bit 12) is set to 1, pro-
register when normal polarity of gramming of the LED2 Status register is enabled.
the RXD± pair has not been re- When LEDPE is cleared to 0, programming of the
versed. LED2 register is disabled. Writes to those registers will
be ignored.
Receive polarity indication is val-
Note: Bits 15-0 in this register are programmable
id only if the T-MAU is in link pass
through the EEPROM PREAD operation.
state.
RXPOLE is cleared by H_RESET 31-16 RES Reserved locations. Written as
and is not affected by S_RESET zeros and read as undefined.
15 LEDOUT This bit indicates the current
2 RCVE Receive Status Enable. When (non-stretched) value of the LED
this bit is set, a value of 1 is output pin. A value of 1 in this bit
passed to the LEDOUT bit in this indicates that the OR of the en-
register when there is receive ac- abled signals is true.
tivity on the network.
The logical value of the LEDOUT
Read/Write accessible always. status signal is determined by the
RCVE is set to 1 by H_RESET settings of the individual Status
and is not affected by S_RESET Enable bits of the LED register
or setting the STOP bit. (bits 8 and 6-0).
1 JABE Jabber Status Enable. When this Read accessible always. This bit
bit is set, a value of 1 is passed to is read only; writes have no ef-
the LEDOUT bit in this register fect. LEDOUT is unaffected by
when the Am79C971 controller is H_RESET, S_RESET, or STOP.
jabbering on the network.
Am79C971 157
14 LEDPOL LED Polarity. When this bit has Read/Write accessible always.
the value 0, then the LED pin will 100E is cleared by H_RESET
be driven to a LOW level whenev- and is not affected by S_RESET
er the OR of the enabled signals or setting the STOP bit.
disabled and allowed to float high 11 MIISE Media Independent Interface Se-
whenever the OR of the enabled lected Enable. Indicates when the
signals is false (i.e., the LED out- MII interface is selected. This will
put will be an Open Drain output be set when either the Manage-
and the output value will be the ment Port State Machine is se-
inverse of the LEDOUT status lecting the MII or when ASEL
bit). (BCR2, bit1) is disabled and
PORTSEL (CSR15, bits 8-7) se-
When this bit has the value 1, lects the MII. This could control
then the LED pin will be driven to relays to switch in and out appro-
a HIGH level whenever the OR of priate filters or could control an
the enabled signals is true, and external PHY when sharing an
the LED pin will be driven to a RJ45 connector.
LOW level whenever the OR of
the enabled signals is false (i.e., Read/Write accessible always.
the LED output will be a Totem MIISE is cleared by H_RESET
Pole output and the output value and is not affected by S_RESET
will be the same polarity as the or setting the STOP bit.
LEDOUT status bit).
10 DXCVRCTL DXCVR Control. When the AUI
The setting of this bit will not ef- interface is the active network
fect the polarity of the LEDOUT port, DXCVRCTL controls the as-
bit for this register. sertion of the LED2 output. The
polarity of the asserted state is
Read/Write accessible always. controlled by the LEDPOL bit
LEDPOL is cleared by H_RESET (BCR4, bit 14). The LED2 pin can
and is not affected by S_RESET be used to control a DC-to-DC
or setting the STOP bit. converter in applications that
want to connect a 10BASE2
13 LEDDIS LED Disable. This bit is used to MAU, as well as a standard DB15
disable the LED output. When AUI connector to the Am79C971
LEDDIS has the value 1, then the AUI port. When DXCVRCTL is
LED output will always be dis- set to 1, the LED2 output will be
abled. When LEDDIS has the val- asserted. This could be used to
ue 0, then the LED output value enable a DC-to-DC converter for
will be governed by the LEDOUT 10BASE2 MAUs (assuming the
and LEDPOL values. enable input of the DC-to-DC
converter is active high and LED-
Read/Write accessible always. POL is cleared to 0). When DX-
LEDDIS is cleared by H_RESET CVRCTL is cleared to 0, the
and is not affected by S_RESET LED2 output will be deasserted.
or setting the STOP bit. This would power down the DC-
to-DC converter. When the
12 100E 100 Mbps Enable. When this bit
10BASE-T interface is the active
is set to 1, a value of 1 is passed
network port, the DXCVR output
when the Am79C971 controller is
operating at 100 Mbps mode. The Read/Write accessible always.
indication is valid with both the in- DXCVRCTL is cleared by
ternal and external PHYs. H_RESET and is unaffected by
bit.
158 Am79C971
9 MPSE Magic Packet Status Enable. 6 LNKSE Link Status Enable. When this bit
When this bit is set to 1, a value of is set, a value of 1 will be passed
1 is passed to the LEDOUT bit in to the LEDOUT bit in this register
this register when Magic Packet when the T-MAU is in Link Pass
frame mode is enabled and a state. When the T-MAU is in Link
Magic Packet frame is detected Fail state, a value of 0 is passed
on the network. to the LEDOUT bit. This bit does
not reflect the link status of the
Read/Write accessible always. external PHY.
MPSE is cleared by H_RESET
and is not affected by S_RESET The function of this bit is masked
or setting the STOP bit. if the 10BASE-T port is operating
in full-duplex mode. This allows a
8 FDLSE Full-Duplex Link Status Enable. Half-Duplex Link Status LED and
Indicates the Full-Duplex Link a Full-Duplex Link Status LED at
Test Status. When this bit is set, the same time.
a value of 1 is passed to the LED-
OUT signal when the Am79C971 Read/Write accessible always.
controller is functioning in a Link LNKSE is cleared by H_RESET
Pass state and full-duplex opera- and is not affected by S_RESET
tion is enabled. When the or setting the STOP bit.
Am79C971 controller is not func-
tioning in a Link Pass state with 5 RCVME Receive Match Status Enable.
full-duplex operation being en- When this bit is set, a value of 1 is
abled, a value of 0 is passed to passed to the LEDOUT bit in this
the LEDOUT signal. register when there is receive ac-
tivity on the network that has
When the 10BASE-T port is ac- passed the address match func-
tive, a value of 1 is passed to the tion for this node. All address
LEDOUT signal whenever the matching modes are included:
Link Test Function (described in physical, logical filtering, broad-
the T-MAU section) detects a cast, and promiscuous.
Link Pass state and the FDEN
(BCR9, bit 0) bit is set. When the Read/Write accessible always.
AUI port is active, a value of 1 is RCVME is cleared by H_RESET
passed to the LEDOUT signal and is not affected by S_RESET
whenever full-duplex operation or setting the STOP bit.
on the AUI port is enabled (both
FDEN and AUIFD bits in BCR9 4 XMTE Transmit Status Enable. When
are set to 1). this bit is set, a value of 1 is
passed to the LEDOUT bit in this
Read/Write accessible always. register when there is transmit
FDLSE is cleared by H_RESET activity on the network.
or setting the STOP bit. Read/Write accessible always.
XMTE is cleared by H_RESET
7 PSE Pulse Stretcher Enable. When and is not affected by S_RESET
this bit is set, the LED illumination or setting the STOP bit.
currence of the enabled function 3 RXPOLE Receive Polarity Status Enable.
for this LED output. A value of 0 When this bit is set, a value of 1 is
disables the pulse stretcher. passed to the LEDOUT bit in this
register when normal polarity of
Read/Write accessible always. the RXD± pair has not been re-
PSE is set to 1 by H_RESET and versed.
setting the STOP bit. Receive polarity indication is
valid only if the T-MAU is in link
pass state.
Am79C971 159
Read/Write accessible always. Note: Bits 15-0 in this register are programmable
RXPOLE is set to 1 by H_RESET through the EEPROM.
and is not affected by S_RESET Bit Name Description
2 RCVE Receive Status Enable. When
passed to the LEDOUT bit in this 15 LEDOUT This bit indicates the current
register when there is receive ac- (non-stretched) value of the LED
tivity on the network. output pin. A value of 1 in this bit
indicates that the OR of the en-
abled signals is true.
RCVE is set to 1 by H_RESET
and is not affected by S_RESET The logical value of the LEDOUT
or setting the STOP bit. status signal is determined by the
settings of the individual Status
1 JABE Jabber Status Enable. When this
Enable bits of the LED register
bit is set, a value of 1 is passed to
(bits 8 and 6-0).
the LEDOUT bit in this register
when the Am79C971 controller is Read accessible always. This bit
jabbering on the network. is read only; writes have no ef-
fect. LEDOUT is unaffected by
H_RESET, S_RESET, or STOP.
JABE is cleared by H_RESET
and is not affected by S_RESET 14 LEDPOL LED Polarity. When this bit has
or setting the STOP bit. the value 0, then the LED pin will
be driven to a LOW level whenev-
0 COLE Collision Status Enable. When
er the OR of the enabled signals
disabled and allowed to float high
register when there is collision
whenever the OR of the enabled
activity on the network. The activ-
signals is false (i.e., the LED out-
ity on the collision inputs to the
put will be an Open Drain output
AUI port within the first 4 µs after
and the output value will be the
every transmission for the pur-
inverse of the LEDOUT status
pose of SQE testing will not
bit.).
cause the LEDOUT bit to be set.
When this bit has the value 1,
then the LED pin will be driven to
COLE is cleared by H_RESET
a HIGH level whenever the OR of
the enabled signals is true, and
the LED pin will be driven to a
BCR7: LED3 Status LOW level whenever the OR of
the enabled signals is false (i.e.,
BCR7 controls the function(s) that the LED3 pin dis- the LED output will be a Totem
plays. Multiple functions can be simultaneously en- Pole output and the output value
abled on this LED pin. The LED display will indicate the will be the same polarity as the
logical OR of the enabled functions. BCR7 defaults to LEDOUT status bit).
Transmit Status (XMT) with pulse stretcher enabled
(PSE = 1) and is fully programmable. The setting of this bit will not ef-
Note: When LEDPE (BCR2, bit 12) is set to 1, pro- fect the polarity of the LEDOUT
gramming of the LED3 Status register is enabled. bit for this register.
When LEDPE is cleared to 0, programming of the
LED3 register is disabled. Writes to those registers will
LEDPOL is cleared by H_RESET
be ignored.
160 Am79C971
13 LEDDIS LED Disable. This bit is used to set to 1, the LED3 output will be
disable the LED output. When asserted. This could be used to
LEDDIS has the value 1, then the enable a DC-to-DC converter for
LED output will always be dis- 10BASE2 MAUs (assuming the
abled. When LEDDIS has the val- enable input of the DC-to-DC
ue 0, then the LED output value converter is active high and LED-
will be governed by the LEDOUT POL is cleared to 0). When DX-
and LEDPOL values. CVRCTL is cleared to 0, the
LED3 output will be deasserted.
Read/Write accessible always. This would power down the DC-
LEDDIS is cleared by H_RESET to-DC converter. When the
and is not affected by S_RESET 10BASE-T interface is the active
or setting the STOP bit. network port, the DXCVR output
12 100E 100 Mbps Enable. When this bit
is set to 1, a value of 1 is passed Read/Write accessible always.
to the LEDOUT bit in this register DXCVRCTL is cleared by
when the Am79C971 controller is H_RESET and is unaffected by
operating at 100 Mbps mode. The S_RESET or by setting the STOP
indication is valid with both the in- bit.
ternal and external PHYs.
Read/Write accessible always. When this bit is set to 1, a value of
100E is cleared by H_RESET 1 is passed to the LEDOUT bit in
and is not affected by S_RESET this register when magic frame
or setting the STOP bit. mode is enabled and a magic
frame is detected on the network.
11 MIISE Media Independent Interface Se-
lected Enable. Indicates when the Read/Write accessible always.
MII interface is selected. This will MPSE is cleared by H_RESET
be set when either the Manage- and is not affected by S_RESET
ment Port State Machine is se- or setting the STOP bit.
lecting the MII or when ASEL
(BCR2, bit1) is disabled and 8 FDLSE Full-Duplex Link Status Enable.
PORTSEL (CSR15, bits 8-7) se- Indicates the Full-Duplex Link
lects the MII. This could control Test Status. When this bit is set,
relays to switch in and out appro- a value of 1 is passed to the LED-
priate filters or could control an OUT signal when the Am79C971
external PHY when sharing an controller is functioning in a Link
RJ45 connector. Pass state and full-duplex opera-
tion is enabled. When the
Read/Write accessible always. Am79C971 controller is not func-
MIISE is cleared by H_RESET tioning in a Link Pass state with
and is not affected by S_RESET full-duplex operation being en-
or setting the STOP bit. abled, a value of 0 is passed to
the LEDOUT signal.
10 DXCVRCTL DXCVR Control. When the AUI
interface is the active network When the 10BASE-T port is ac-
port, DXCVRCTL controls the as- tive, a value of 1 is passed to the
sertion of the LED3 output. The LEDOUT signal whenever the
polarity of the asserted state is Link Test Function (described in
controlled by the LEDPOL bit the T-MAU section) detects a
(BCR4, bit 14). The LED3 pin can Link Pass state and the FDEN
be used to control a DC-to-DC (BCR9, bit 0) bit is set. When the
converter in applications that AUI port is active, a value of 1 is
want to connect a 10BASE2 passed to the LEDOUT signal
MAU, as well as a standard DB15 whenever full-duplex operation
AUI connector to the Am79C971 on the AUI port is enabled (both
AUI port. When DXCVRCTL is
Am79C971 161
FDEN and AUIFD bits in BCR9 4 XMTE Transmit Status Enable. When
are set to 1). this bit is set, a value of 1 is
Read/Write accessible always. register when there is transmit
FDLSE is cleared by H_RESET activity on the network.
or setting the STOP bit. Read/Write accessible always.
XMTE is set to 1 by H_RESET
7 PSE Pulse Stretcher Enable. When and is not affected by S_RESET
this bit is set, the LED illumination or setting the STOP bit.
currence of the enabled function 3 RXPOLE Receive Polarity Status Enable.
for this LED output. A value of 0 When this bit is set, a value of 1 is
disables the pulse stretcher. passed to the LEDOUT bit in this
register when normal polarity of
Read/Write accessible always. the RXD± pair has not been re-
PSE is set to 1 by H_RESET and versed.
setting the STOP bit. Receive polarity indication is val-
id only if the T-MAU is in link pass
6 LNKSE Link Status Enable. When this bit state.
is set, a value of 1 will be passed
to the LEDOUT bit in this register Read/Write accessible always.
when the T-MAU is in Link Pass RXPOLE is cleared by H_RESET
state. When the T-MAU is in Link and is not affected by S_RESET
Fail state, a value of 0 is passed or setting the STOP bit.
to the LEDOUT bit. This bit does
not reflect the link status of the 2 RCVE Receive Status Enable. When
external PHY. this bit is set, a value of 1 is
The function of this bit is masked register when there is receive ac-
if the 10BASE-T port is operating tivity on the network.
in full-duplex mode. This allows a
Half-Duplex Link Status LED and Read/Write accessible always.
a Full-Duplex Link Status LED at RCVE is cleared by H_RESET
the same time. and is not affected by S_RESET
LNKSE is cleared by H_RESET 1 JABE Jabber Status Enable. When this
and is not affected by S_RESET bit is set, a value of 1 is passed to
or setting the STOP bit. the LEDOUT bit in this register
when the Am79C971 controller is
5 RCVME Receive Match Status Enable. jabbering on the network.
passed to the LEDOUT bit in this Read/Write accessible always.
register when there is receive ac- JABE is cleared by H_RESET
tivity on the network that has and is not affected by S_RESET
passed the address match func- or setting the STOP bit.
tion for this node. All address
matching modes are included: 0 COLE Collision Status Enable. When
physical, logical filtering, broad- this bit is set, a value of 1 is
cast, and promiscuous. passed to the LEDOUT bit in this
register when there is collision
Read/Write accessible always. activity on the network. The activ-
RCVME is cleared by H_RESET ity on the collision inputs to the
and is not affected by S_RESET AUI port within the first 4 µs after
or setting the STOP bit. every transmission for the pur-
pose of SQE testing will not
cause the LEDOUT bit to be set.
162 Am79C971

COLE is cleared by H_RESET AUIFD is reset to 0 by H_RESET,
and is not affected by S_RESET and is unaffected by S_RESET
or setting the STOP bit. and the STOP bit.
BCR9: Full-Duplex Control 0 FDEN Full-Duplex Enable. FDEN con-

Note: Bits 15-0 in this register are programmable trols whether full-duplex opera-
through the EEPROM. tion is enabled. When FDEN is
cleared, full-duplex operation is
Bit Name Description not enabled and the Am79C971
controller will always operate in
31-16 RES Reserved locations. Written as the half-duplex mode. When
zeros and read as undefined. FDEN is set, the Am79C971 con-
troller will operate in full-duplex
mode when the 10BASE-T or MII
port is enabled or when the AUI
2 FDRPAD Full-Duplex Runt Packet Accept port is enabled and the AUIFD
Disable. When FDRPAD is set to (BCR9, bit 1) bit is set. When
1 and full-duplex mode is en- DLNKTST (CSR15, bit 12) is set
abled, the Am79C971 controller to 1, full-duplex operation will not
will only receive frames that meet be enabled on the 10BASE-T
the minimum Ethernet frame port. FDEN will override the Auto-
length of 64 bytes. Receive DMA Negotiation portion of the internal
will not start until at least 64 bytes 10BASE-T MAU. The internal
or a complete frame have been TMAU will no longer try to auto-
received. By default, FDRPAD is matically negotiate for the link. It
cleared to 0. The Am79C971 con- assumes that the software is pro-
troller will accept any length gramming the FDEN bit for a rea-
frame and receive DMA will start son and defers control. See Table
according to the programming of 32. Do not set this bit when Auto-
the receive FIFO watermark. Negotiation is enabled.
Note that there should not be any
runt packets in a full-duplex net-
FDEN is reset to 0 by H_RESET,
work, since the main cause for
and is unaffected by S_RESET
runt packets is a network collision
and the STOP bit.
and there are no collisions in a
full-duplex network. BCR16: I/O Base Address Lower
Read/Write accessible always. Bit Name Description
FDRPAD is cleared by H_RESET
and is not affected by S_RESET 31-16 RES Reserved locations. Written as
or by setting the STOP bit. zeros and read as undefined.
1 AUIFD AUI Full-Duplex. AUIFD controls 15-5 IOBASEL Reserved locations. After
whether or not full-duplex opera- H_RESET, the value of these bits
tion on the AUI port is enabled. will be undefined. The settings of
AUIFD is only meaningful if these bits will have no effect on
FDEN (BCR9, bit 0) is set to 1. If any Am79C971 controller func-
the FDEN bit is 0, the AUI port will tion. It is only included for soft-
always operate in half-duplex ware compatibility with other
mode. In addition, if FDEN is set PCnet family devices.
to 1 but the AUIFD bit is reset to
0, the AUI port will always oper- Read/Write accessible always.
ate in half-duplex mode. If FDEN IOBASEL is not affected by
is set to 1 and AUIFD is set to 1, S_RESET or STOP.
full-duplex operation on the AUI
port is enabled.
Am79C971 163

zeros, read as undefined.
Table 32. Network Port Configuration

AUIFD (bit FDEN (bit Effect on the AUI Effect on the Effect on the GPSI Effect On the MII Port (ASEL =
1) 0) Port 10BASE-T Port Port 0, PORTSEL = MII)
X 0 Half-Duplex Half-Duplex Half-Duplex Half-Duplex
0 1 Half-Duplex Full-Duplex Full-Duplex Full-Duplex
1 1 Full-Duplex Full-Duplex Full-Duplex Full-Duplex
BCR17: I/O Base Address Upper EBWE and EROMCS deassert.
Bit Name Description The differences in the sizes of the
Expansion Bus Address and
31-16 RES Reserved locations. Written as Data busses is due to the differ-
zeros and read as undefined. ence in the access for SRAM ver-
sus Flash/EPROM.
15-0 IOBASEU Reserved locations. After
H_RESET, the value in this regis- The register value specifies the
ter will be undefined. The settings time in number of clock cycles +1
of this register will have no effect according to Table 33.
on any Am79C971 controller
function. It is only included for
software compatibility with other Table 33. ROMTNG Programming Values
PCnet family devices. ROMTMG (bits 15-12) No. of Expansion Bus Cycles
1h<=n <=Fh n+1
IOBASEU is not affected by
Note: Programming ROMTNG
S_RESET or STOP.
with a value of 0 is not permitted.
BCR18: Burst and Bus Control Register
The access time for the Expan-
Note: Note that bits 15-0 in this register are program- sion ROM or the EDBATA
mable through the EEPROM. (BCR30) device (tACC) during
Bit Name Description read operations can be calculat-
ed by subtracting the clock to out-
31-16 RES Reserved locations. Written as put delay for the EBUA_EBA[7:0]
zeros and read as undefined. outputs (tv_A_D) and by subtract-
ing the input to clock setup time
15-12 ROMTMG Expansion ROM Timing. The val- for the EBD[7:0] inputs (ts_D)
ue of ROMTMG is used to tune from the time defined by ROMT-
the timing for all EBDATA MG:
(BCR30) accesses to SRAM/
Flash/EPROM as well as all Ex- tACC = ROMTMG * CLK period
pansion ROM accesses to Flash/ *CLK_FAC - (tv_A_D) - (ts_D)
EPROM.
The access time for the Expan-
ROMTMG, during read opera- sion ROM or for the EDBATA
tions, defines the time from when (BCR30) device (tACC) during
the Am79C971 controller drives write operations can be calculat-
the lower 8 or 16 bits of the Ex- ed by subtracting the clock to out-
pansion Bus Address bus to put delay for the EBUA EBA[7:0]
when the Am79C971 controller outputs (tv_A_D) and by adding
latches in the data on the 8 or 16 the input to clock setup time for
bits of the Expansion Bus Data SRAM/Flash/EPRO inputs (ts_D)
inputs. ROMTMG, during write from the time defined by ROMT-
operations, defines the time from MG:
when the Am79C971 controller
tACC = ROMTMG * CLK period *
drives the lower 8 or 16 bits of the
CLK_FAC - (tv_A_D) - (ts_D)
Expansion Bus Data to when the
164 Am79C971
For an adapter card application, The NOUFLO bit should not be

the value used for clock period set when the Am79C971 control-
should be 30 ns to guarantee cor- ler is operating in the NO-SRAM
rect interface timing at the maxi- mode with no external SRAM.
mum clock frequency of 33 MHz.
Read accessible always; write either the STOP or the SPND bit
accessible only when the STOP is set. NOUFLO is cleared to 0 af-
bit is set. ROMTMG is set to the ter H_RESET or S_RESET and
value of 1001b by H_RESET and is unaffected by STOP.
STOP. The default value allows 10 RES Reserved location. Written as ze-
using an Expansion ROM with an ros and read as undefined.
access time of 250 ns in a system
with a maximum clock frequency 9 MEMCMD Memory Command used for burst
of 33 MHz. read accesses to the transmit
buffer. When MEMCMD is set to
11 NOUFLO No Underflow on Transmit. When 0, all burst read accesses to the
the NOUFLO bit is set to 1, the transmit buffer are of the PCI
Am79C971 controller will not start command type Memory Read
transmitting the preamble for a Line (type 14). When MEMCMD
packet until the Transmit Start is set to 1, all burst read accesses
Point (CSR80, bits 10-11) re- to the transmit buffer are of the
quirement (except when XMTSP PCI command type Memory
= 3h, Full Packet has no meaning Read Multiple (type 12).
when NOUFLO is set to 1) has
been met and the complete pack- Read accessible always; write
et has been DMA’d into the accessible only when either the
Am79C971 controller. The com- STOP or the SPND bit is set.
plete packet may reside in any MEMCMD is cleared by
combination of the Bus Transmit H_RESET and is not affected by
FIFO, the external SRAM, and S_RESET or STOP.
the MAC Transmit FIFO, as long
8 EXTREQ Extended Request. This bit con-
as enough of the packet is in the
trols the deassertion of REQ for a
MAC Transmit FIFO to meet the
burst transaction. If EXTREQ is
Transmit Start Point requirement.
set to 0, REQ is deasserted at the
When the NOUFLO bit is cleared
beginning of a burst transaction.
to 0, the Transmit Start Point is
(The Am79C971 controller never
the only restriction on when pre-
performs more than one burst
amble transmission begins for
transaction within a single bus
transmit packets.
mastership period.) In this mode,
Setting the NOUFLO bit guaran- the Am79C971 controller relies
tees that the Am79C971 control- on the PCI latency timer to get
ler will never suffer transmit enough bus bandwidth, in case
underflows, because the arbiter the system arbiter also removes
that controls transfers to and from GNT at the beginning of the burst
the external SRAM guarantees a transaction. If EXTREQ is set to
worst case latency on transfers to 1, REQ stays asserted until the
and from the MAC and Bus last but one data phase of the
Transmit FIFOs such that it will burst transaction is done. This
never underflow if the complete mode is useful for systems that
packet has been DMA’d into the implement an arbitration scheme
Am79C971 controller before without preemption and require
packet transmission begins. that REQ stays asserted through-
out the transaction.
Am79C971 165
EXTREQ should not be set to 1 vice from performing bursting

when the Am79C971 controller is during read accesses. The
used in a PCI bus application. Am79C971 controller can per-
form burst transfers when reading
Read accessible always, write the initialization block, the de-
accessible only when either the scriptor ring entries (when
STOP or the SPND bit is set. EX- SWSTYLE = 3) and the buffer
TREQ is cleared by H_RESET memory.
or STOP. BREADE should be set to 1 when
the Am79C971 controller is used
7 DWIO Double Word I/O. When set, this in a PCI bus application to guar-
bit indicates that the Am79C971 antee maximum performance.
controller is programmed for
DWord I/O (DWIO) mode. When Read accessible always; write
cleared, this bit indicates that the accessible only when either the
Am79C971 controller is pro- STOP or the SPND bit is set.
grammed for Word I/O (WIO) BREADE is cleared by H_RESET
mode. This bit affects the I/O Re- and is not affected by S_RESET
source Offset map and it affects or STOP.
the defined width of the
Am79C971 controllers I/O re- 5 BWRITE Burst Write Enable. When set,
sources. See the DWIO and WIO this bit enables burst mode during
sections for more details. memory write accesses. When
cleared, this bit prevents the de-
The initial value of the DWIO bit is vice from performing bursting
determined by the programming during write accesses. The
of the EEPROM. Am79C971 controller can per-
form burst transfers when writing
The value of DWIO can be al- the descriptor ring entries (when
tered automatically by the SWSTYLE = 3) and the buffer
Am79C971 controller. Specifical- memory.
ly, the Am79C971 controller will
set DWIO if it detects a DWord BWRITE should be set to 1 when
write access to offset 10h from the Am79C971 controller is used
the Am79C971 controller I/O in a PCI bus application to guar-
base address (corresponding to antee maximum performance.
the RDP resource).
Read accessible always, write
Once the DWIO bit has been set accessible only when either the
to a 1, only a H_RESET or an EE- STOP or the SPND bit is set.
PROM read can reset it to a 0. BWRITE is cleared by H_RESET
(Note that the EEPROM read op- and is not affected by S_RESET
eration will only set DWIO to a 0 if or STOP.
the appropriate bit inside of the
EEPROM is set to 0.) 4-3 TSTSHDW Reserved locations. Written an
read as zeros.
Read accessible always. DWIO
is read only, write operations 2-0 LINBC Reserved locations. Read acces-
have no effect. DWIO is cleared sible always; write accessible
by H_RESET and is not affected only when either the STOP or the
S_RESET or by setting the STOP SPND bit is set. After H_RESET,
bit. the value in these bits will be
001b. The setting of these bits
6 BREADE Burst Read Enable. When set, have no effect on any Am79C971
this bit enables burst mode during controller function. LINBC is not
memory read accesses. When affected by S_RESET or STOP.
cleared, this bit prevents the de-
166 Am79C971
BCR19: EEPROM Control and Status EEPROM after H_RESET, as

Bit Name Description well as to host-initiated PREAD
commands.
14 PREAD EEPROM Read command bit.
When this bit is set to a 1 by the
15 PVALID EEPROM Valid status bit. Read host, the PVALID bit (BCR19, bit
accessible only. PVALID is read 15) will immediately be reset to a
only; write operations have no ef- 0, and then the Am79C971 con-
fect. A value of 1 in this bit indi- troller will perform a read opera-
cates that a PREAD operation tion of 64 bytes from the
has occurred, and that (1) there is EEPROM through the interface.
an EEPROM connected to the The EEPROM data that is
Am79C971 controller interface fetched during the read will be
pins and (2) the contents read stored in the appropriate internal
from the EEPROM have passed registers on board the
the checksum verification opera- Am79C971 controller. Upon com-
tion. pletion of the EEPROM read op-
eration, the Am79C971 controller
A value of 0 in this bit indicates a will assert the PVALID bit. EE-
failure in reading the EEPROM. PROM contents will be indirectly
The checksum for the entire 64 accessible to the host through
bytes of EEPROM is incorrect or read accesses to the Address
no EEPROM is connected to the PROM (offsets 0h through Oh)
interface pins. and through read accesses to
other EEPROM programmable
PVALID is set to 0 during registers. Note that read access-
H_RESET and is unaffected by es from these locations will not
S_RESET or the STOP bit. How- actually access the EEPROM it-
ever, following the H_RESET op- self, but instead will access the
eration, an automatic read of the Am79C971 controllers internal
EEPROM will be performed. Just copy of the EEPROM contents.
as is true for the normal PREAD Write accesses to these locations
command, at the end of this auto- may change the Am79C971 con-
matic read operation, the PVALID troller register contents, but the
bit may be set to 1. Therefore, EEPROM locations will not be af-
H_RESET will set the PVALID bit fected. EEPROM locations may
to 0 at first, but the automatic EE- be accessed directly through
PROM read operation may later BCR19.
set PVALID to a 1.
At the end of the read operation,
If PVALID becomes 0 following the PREAD bit will automatically
an EEPROM read operation (ei- be reset to a 0 by the Am79C971
ther automatically generated af- controller and PVALID will bet
ter H_RESET, or requested set, provided that an EEPROM
through PREAD), then all EE- existed on the interface pins and
PROM-programmable BCR loca- that the checksum for the entire
tions will be reset to their 64 bytes of EEPROM was cor-
H_RESET values. The content of rect.
the Address PROM locations,
however, will not be cleared. Note that when PREAD is set to a
1, then the Am79C971 controller
If no EEPROM is present at the will no longer respond to any ac-
EESK, EEDI, and EEDO pins, cesses directed toward it, until
then all attempted PREAD com- the PREAD operation has com-
mands will terminate early and pleted successfully. The
PVALID will not be set. This ap- Am79C971 controller will termi-
plies to the automatic read of the nate these accesses with the as-
Am79C971 167
sertion of DEVSEL and STOP 13 EEDET EEPROM Detect. This bit indi-
while TRDY is not asserted, sig- cates the sampled value of the
naling to the initiator to discon- EESK/LED1/SFBD pin at the end
nect and retry the access at a of H_RESET. This value indi-
later time. cates whether or not an EE-
PROM is present at the EEPROM
If a PREAD command is given to interface. If this bit is a 1, it indi-
the Am79C971 controller but no cates that an EEPROM is
EEPROM is attached to the inter- present. If this bit is a 0, it indi-
face pins, the PREAD bit will be cates that an EEPROM is not
cleared to a 0, and the PVALID bit present.
will remain reset with a value of 0.
This applies to the automatic Read accessible only. EEDET is
read of the EEPROM after read only; write operations have
H_RESET as well as to host initi- no effect. The value of this bit is
ated PREAD commands. EE- determined at the end of the
PROM programmable locations H_RESET operation. It is unaf-
on board the Am79C971 control- fected by S_RESET or the STOP
ler will be set to their default val- bit.
ues by such an aborted PREAD
operation. For example, if the Table 34 indicates the possible
aborted PREAD operation imme- combinations of EEDET and the
diately followed the H_RESET existence of an EEPROM and the
operation, then the final state of resulting operations that are pos-
the EEPROM programmable lo- sible on the EEPROM interface.
cations will be equal to the
H_RESET programming for 12-5 RES Reserved locations. Written as
those locations. zeros; read as undefined.
If a PREAD command is given to 4 EEN EEPROM Port Enable. When this

the Am79C971 controller and the bit is set to a 1, it causes the val-
auto-detection pin (EESK/LED1/ ues of ECS, ESK, and EDI to be
SFBD) indicates that no EE- driven onto the EECS, EESK,
PROM is present, then the EE- and EEDI pins, respectively. If
PROM read operation will still be EEN = 0 and no EEPROM read
attempted. function is currently active, then
EECS will be driven LOW. When
Note that at the end of the EEN = 0 and no EEPROM read
H_RESET operation, a read of function is currently active, EESK
the EEPROM will be performed and EEDI pins will be driven by
automatically. This H_RESET- the LED registers BCR5 and
generated EEPROM read func- BCR4, respectively. See Table
tion will not proceed if the auto- 35.
detection pin (EESK/LED1/SF-
BD) indicates that no EEPROM is Read accessible always, write
present. accessible only when either the
STOP or the SPND bit is set.
Read accessible always; write EEN is set to 0 by H_RESET and
accessible only when either the is unaffected by the S_RESET or
STOP or the SPND bit is set. STOP bit.
PREAD is set to 0 during
H_RESET and is unaffected by 3 RES Reserved location. Written as
S_RESET or the STOP bit. zero and read as undefined.
2 ECS EEPROM Chip Select. This bit is

used to control the value of the
EECS pin of the interface when
the EEN bit is set to 1 and the
PREAD bit is set to 0. If EEN = 1
168 Am79C971
and PREAD = 0 and ECS is set to hold times of the EEDI pin value
a 1, then the EECS pin will be with respect to the EESK signal
forced to a HIGH level at the ris- edge are not guaranteed.
ing edge of the next clock follow-
ing bit programming. ESK has no effect on the EESK
pin unless the PREAD bit is set to
If EEN = 1 and PREAD = 0 and 0 and the EEN bit is set to 1.
ECS is set to a 0, then the EECS
pin will be forced to a LOW level Read accessible always, write
at the rising edge of the next accessible only when either the
clock following bit programming. STOP or the SPND bit is set. ESK
ECS has no effect on the output is reset to 1 by H_RESET and is
value of the EECS pin unless the not affected by S_RESET or
PREAD bit is set to 0 and the STOP.
EEN bit is set to 1.
0 EDI/EDO EEPROM Data In/ EEPROM
Read accessible always, write Data Out. Data that is written to
accessible only when either the this bit will appear on the EEDI
STOP or the SPND bit is set. output of the interface, except
ECS is set to 0 by H_RESET and when the PREAD bit is set to 1 or
is not affected by S_RESET or the EEN bit is set to 0. Data that
STOP. is read from this bit reflects the
value of the EEDO input of the in-
1 ESK EEPROM Serial Clock. This bit terface.
and the EDI/EDO bit are used to
control host access to the EE- EDI/EDO has no effect on the
PROM. Values programmed to EEDI pin unless the PREAD bit is
this bit are placed onto the EESK set to 0 and the EEN bit is set to
pin at the rising edge of the next 1.
clock following bit programming,
except when the PREAD bit is set Read accessible always; write
to 1 or the EEN bit is set to 0. If accessible only when either the
both the ESK bit and the EDI/ STOP or the SPND bit is set. EDI/
EDO bit values are changed dur- EDO is reset to 0 by H_RESET
ing one BCR19 write operation, and is not affected by S_RESET
while EEN = 1, then setup and or STOP.
Table 34. EEDET Setting

EEDET Value EEPROM Result of Automatic EEPROM Read
(BCR19[13]) Connected? Result if PREAD is Set to 1 Operation Following H_RESET
EEPROM read operation is attempted. First two EESK clock cycles are generated,
0 No Entire read sequence will occur, checksum then EEPROM read operation is aborted
failure will result, PVALID is reset to 0. and PVALID is reset to 0.
EEPROM read operation is attempted. First two EESK clock cycles are generated,
0 Yes Entire read sequence will occur, checksum then EEPROM read operation is aborted
operation will pass, PVALID is set to 1. and PVALID is reset to 0.
EEPROM read operation is attempted. EEPROM read operation is attempted.
1 No Entire read sequence will occur, checksum Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0. failure will result, PVALID is reset to 0.
EEPROM read operation is attempted. EEPROM read operation is attempted.
1 Yes Entire read sequence will occur, checksum Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1. operation will pass, PVALID is set to 1.
Am79C971 169
Table 35. Interface Pin Assignment

PREAD or Auto
RST Pin Read in Progress EEN EECS EESK EEDI
Low X X 0 Tri-State Tri-State
High 1 X Active Active Active
From ECS From ESK Bit of From EEDI Bit of
High 0 1
Bit of BCR19 BCR19 BCR19
High 0 0 0 LED1 LED0
BCR20: Software Style and receive descriptor entries.
This register is an alias of the location CSR58. Accesses When cleared, this bit indicates
to and from this register are equivalent to accesses to that the Am79C971 controller uti-
CSR58. lizes 16-bit software structures for
the initialization block and the
Bit Name Description transmit and receive descriptor
entries. In this mode, the
31-16 RES Reserved locations. Written as Am79C971 controller is back-
zeros and read as undefined. wards compatible with the
Am7990 LANCE and Am79C960
15-11 RES Reserved locations. Written as PCnet-ISA controllers.
The value of SSIZE32 is deter-
10 APERREN Advanced Parity Error Handling mined by the Am79C971 control-
Enable. When APERREN is set ler according to the setting of the
to 1, the BPE bits (RMD1 and Software Style (SWSTYLE, bits
TMD1, bit 23) start having a 7-0 of this register).
meaning. BPE will be set in the
descriptor associated with the Read accessible always.
buffer that was accessed when a SSIZE32 is read only; write oper-
data parity error occurred. Note ations will be ignored. SSIZE32
that since the advanced parity er- will be cleared after H_RESET
ror handling uses an additional bit (since SWSTYLE defaults to 0)
in the descriptor, SWSTYLE (bits and is not affected by S_RESET
7-0 of this register) must be set to or STOP.
2 or 3 to program the Am79C971
controller to use 32-bit software If SSIZE32 is reset, then bits
structures. IADR[31:24] of CSR2 will be
used to generate values for the
APERREN does not affect the re- upper 8 bits of the 32-bit address
porting of address parity errors or bus during master accesses initi-
data parity errors that occur when ated by the Am79C971 controller.
the Am79C971 controller is the This action is required, since the
target of the transfer. 16-bit software structures speci-
fied by the SSIZE32 = 0 setting
Read anytime; write accessible will yield only 24 bits of address
only when either the STOP or the for Am79C971 controller bus
SPND bit is set. APERREN is master accesses.
cleared by H_RESET and is not
affected by S_RESET or STOP. If SSIZE32 is set, then the soft-
ware structures that are common
9 RES Reserved locations. Written as to the Am79C971 controller and
zeros; read as undefined. the host system will supply a full
32 bits for each address pointer
8 SSIZE32 Software Size 32 bits. When set,
that is needed by the Am79C971
this bit indicates that the
controller for performing master
Am79C971 controller utilizes 32-
accesses.
bit software structures for the ini-
tialization block and the transmit
170 Am79C971
The value of the SSIZE32 bit has All Am79C971 controller CSR
no effect on the drive of the upper bits and all descriptor, buffer, and
8 address bits. The upper 8 ad- initialization block entries not cit-
dress pins are always driven, re- ed in the Table 36 are unaffected
gardless of the state of the by the Software Style selection
SSIZE32 bit. and are, therefore, always fully
functional as specified in the CSR
Note that the setting of the and BCR sections.
SSIZE32 bit has no effect on the
defined width for I/O resources. Read/Write accessible only when
I/O resource width is determined either the STOP or the SPND bit
by the state of the DWIO bit is set. The SWSTYLE register will
(BCR18, bit 7). contain the value 00h following
H_RESET and will be unaffected
7-0 SWSTYLE Software Style register. The val- by S_RESET or STOP.
ue in this register determines the
style of register and memory re- BCR21: Interrupt Control
sources that shall be used by the Bit Name Description
Am79C971 controller. The Soft-
ware Style selection will affect the 31-16 RES Reserved locations. Written as
interpretation of a few bits within zeros and read as undefined.
the CSR space, the order of the
descriptor entries and the width of 15-0 INTCON Reserved locations. Writes to this
the descriptors and initialization register will have no effect on the
block entries. operation of the Am79C971 con-
troller.
Table 36. Software Styles

SWSTYLE Style Initialization Block
[7:0] Name SSIZE32 Entries Descriptor Ring Entries
LANCE/ 16-bit software
16-bit software structures,
00h PCnet-ISA 0 structures, non-burst or
non-burst access only
controller burst access
01h RES 1 RES RES
32-bit software
PCnet-PCI 32-bit software structures,
02h 1 structures, non-burst or
controller non-burst access only
burst access
PCnet-PCI 32-bit software
32-bit software structures,
03h 1 structures, non-burst or
controller non-burst access only
burst access
All Other Reserved Undefined Undefined Undefined
BCR22: PCI Latency Register 4 microseconds. MAX_LAT is
Note: Bits 15-0 in this register are programmable aliased to the PCI configuration
through the EEPROM. space register MAX_LAT (offset
3Fh). The host will use the value
Bit Name Description in the register to determine the
setting of the Am79C971 Latency
31-16 RES Reserved locations. Written as Timer register.
Read accessible always; write
15-8 MAX_LAT Maximum Latency. Specifies the accessible only when either the
maximum arbitration latency the STOP or the SPND bit is set.
Am79C971 controller can sustain MAX_LAT is set to the value of
without causing problems to the FFh by H_RESET which results
network activity. The register val- in a default maximum latency of
ue specifies the time in units of 1/ 63.75 microseconds. It is recom-
Am79C971 171
mended to program the value of 15-0 SVID Subsystem Vendor ID. SVID is
18H via EEPROM. MAX_LAT is used together with SID (BCR24,
not affected by S_RESET or bits 15-0) to uniquely identify the
STOP. add-in board or subsystem the
Am79C971 controller is used in.
7-0 MIN_GNT Minimum Grant. Specifies the Subsystem Vendor IDs can be
minimum length of a burst period obtained from the PCI SIG. A val-
the Am79C971 controller needs ue of 0 (the default) indicates that
to keep up with the network activ- the Am79C971 controller does
ity. The length of the burst period not support subsystem identifica-
is calculated assuming a clock tion. SVID is aliased to the PCI
rate of 33 MHz. The register val- configuration space register Sub-
ue specifies the time in units of 1/ system Vendor ID (offset 2Ch).
4 µs. MIN_GNT is aliased to the
PCI configuration space register Read accessible always. SVID is
MIN_GNT (offset 3Eh). The host read only. Write operations are
will use the value in the register to ignored. SVID is cleared to 0 by
determine the setting of the H_RESET and is not affected by
Am79C971 Latency Timer regis- S_RESET or by setting the STOP
ter. bit.
Read accessible always; write BCR24: PCI Subsystem ID Register

accessible only when either the Note: Bits 15-0 in this register are programmable
STOP or the SPND bit is set. through the EEPROM.
MIN_GNT is set to the value of
06h by H_RESET which results Bit Name Description
in a default minimum grant of
1.5 µs, which is the time it takes 31-16 RES Reserved locations. Written as
the Am79C971 controller to read/ zeros and read as undefined.
write half of the FIFO. (16 DWord
15-0 SID Subsystem ID. SID is used to-
transfers in burst mode with one
gether with SVID (BCR23, bits
extra wait state per data phase
15-0) to uniquely identify the add-
inserted by the target.) Note that
in board or subsystem the
the default is only a typical value.
Am79C971 controller is used in.
It also does not take into account
The value of SID is up to the sys-
any descriptor accesses. It is rec-
tem vendor. A value of 0 (the de-
ommended to program the value
fault) indicates that the
of 18H via EEPROM. MIN_GNT
Am79C971 controller does not
support subsystem identification.
STOP.
SID is aliased to the PCI configu-
BCR23: PCI Subsystem Vendor ID Register ration space register Subsystem
ID (offset 2Eh).
through the EEPROM. Read accessible always. SID is
Bit Name Description read only. Write operations are
ignored. SID is cleared to 0 by
31-16 RES Reserved locations. Written as H_RESET and is not affected by
zeros and read as undefined. S_RESET or by setting the STOP
bit.
BCR25: SRAM Size Register


through the EEPROM.
172 Am79C971
7-0 SRAM_SIZE SRAM Size. Specifies the upper boundary where the receive buffer
8 bits of the 16-bit total size of the begins in the SRAM. The transmit
SRAM buffer. Each bit in buffer in the SRAM begins at ad-
SRAM_SIZE accounts for a 512- dress 0 and ends at the address
byte page. The starting address located just before the address
for the lower 8 bits is assumed to specified by SRAM_BND. There-
be 00h and the ending address fore, the receive buffer always be-
for the lower is assumed to be gins on a 512 byte boundary. The
FFh. Therefore, the maximum ad- lower bits are assumed to be ze-
dress range is the starting ad- ros. SRAM_BND has no effect in
dress of 0000h to ending address the Low Latency Receive mode.
of ((SRAM_SIZE +1) * 256
words) or FFFFh. An Note: The minimum allowed
SRAM_SIZE value of all zeros number of pages is four. The
specifies that no SRAM is present Am79C971 controller will not op-
and the internal FIFOs will be erate correctly with less than four
joined into a contiguous FIFO pages of memory per queue. See
similar to the PCnet-PCI II con- Table 37 for SRAM_BND pro-
troller. gramming details.
Note: The minimum allowed

number of pages is eight for nor- Table 37. SRAM_BND Programming
mal network operation. The
Am79C971 controller will not op-
erate correctly with less than the SRAM_BND Lower Address
eight pages of memory. When SRAM Addresses [7:0] [7:0]
the minimum number of pages is Minimum
used, these pages must be allo- SRAM_BND 04h 00-FFh
cated four each for transmit and address
receive. Also note that a “No Maximum
SRAM configuration” is only valid SRAM_BND FCh 00-FFh
for 10Mb mode. In 100Mb mode, address
SRAM is mandatory and must al-
ways be used. CAUTION: Programming
SRAM_BND and SRAM_SIZE
CAUTION: Programming to the same value will cause
SRAM_BND and SRAM_SIZE data corruption except in the
to the same value will cause case where SRAM SIZE is 0.
data corruption except in the
case where SRAM_SIZE is 0. Read accessible always; write
accessible only when the STOP
Read accessible always; write bit is set. SRAM_BND is set to
accessible only when the STOP 00000000b during H_RESET
bit is set. SRAM_SIZE is set to and is unaffected by S_RESET or
000000b during H_RESET and is STOP.
unaffected by S_RESET or
STOP. BCR27: SRAM Interface Control Register
BCR26: SRAM Boundary Register through the EEPROM.
Note: Bits 7-0 in this register are programmable 31-16 RES Reserved locations. Written as
through the EEPROM. zeros and read as undefined.
zeros and read as undefined. 15 PTR TST Reserved. Reserved for manu-
facturing tests. Written as zero
7-0 SRAM_BND SRAM Boundary. Specifies the and read as undefined.
upper 8 bits of the 16-bit address
Am79C971 173
Note: Use of this bit will cause Read/Write accessible only when
data corruption and erroneous the STOP bit is set. LOLATRX is
operation. cleared to 0 after H_RESET or
Read/Write accessible always. STOP.
PTR_TST is set to 0 by
H_RESET and is unaffected by 13-6 RES Reserved locations. Written as
S_RESET and the STOP bit. zeros and read as undefined.
14 LOLATRX Low Latency Receive. When the 5-3 EBCS Expansion Bus Clock Source.
LOLATRX bit is set to 1, the These bits are used to select the
Am79C971 controller will switch source of the fundamental clock
to an architecture applicable to to drive the SRAM and Expansion
cut-through switches. The ROM access cycles. Table 38
Am79C971 controller will assert a shows the selected clock source
receive frame DMA after only 16 for the various values of EBCS.
bytes of the current receive frame Note that the actual frequency
has been received regardless of that the Expansion Bus access
where the RCVFW (CSR80, bits cycles run at is a function of both
13-12) are set. The watermark is the EBCS and CLK_FAC
a fixed value and cannot be (BCR27, bits 2-0) bit field set-
changed. The receive FIFOs will tings. When EBCS is set to either
be in NO_SRAM mode while all the PCI clock or the XTAL clock,
transmit traffic is buffered through no external clock source is re-
the external SRAM. This bit is quired as the clocks are routed in-
only valid and the low latency re- ternally and the EBCLK pin
ceive only enabled when the should be pulled to VDD through
SRAM_SIZE (BCR25, bits 7-0) a resistor.
bits are non-zero. SRAM_BND
(BCR26, bits 7-0) has no mean-
ing when the Am79C971 control- Table 38. EBCS Values
ler is in the Low Latency mode.
EBCS Expansion Bus Clock Source
See the section on SRAM Config-
000 CLK pin (PCI Clock)
uration for more details.
001 XTAL1 and XTAL2 pins (20-MHz clock)
When the LOLATRX bit is set to 010 EBCLK pin
0, the Am79C971 controller will 011 Reserved
return to a normal receive config- 1XX Reserved
uration. The runt packet accept
bit (RPA, CSR124, bit 3) must be Read accessible always; write
set when LOLATRX is set. accessible only when the STOP
bit is set. EBCS is set to 000b
CAUTION: To provide data in- (PCI clock selected) during
tegrity when switching into H_RESET and is unaffected by
and out of the low latency S_RESET or the STOP bit.
mode, DO NOT SET the
FASTSPNDE (CSR7, bit 15) bit Note: The clock frequency driv-
when setting the SPND bit. Re- ing the Expansion Bus access cy-
ceive frames WILL be overwrit- cles that results from the settings
ten and the Am79C971 of the EBCS and CLK FAC bits
controller may give erratic be- must not exceed 33 MHz at any
havior when it is enable again. time. When EBCS is set to either
The minimum allowed number the PCI clock or the XTAL clock,
of pages is four. The no external clock source is re-
Am79C971 controller will not quired because the clocks are
operate correctly in the LOLA- routed internally and the EBCLK
TRX mode with less than four pin should be pulled to VDD
pages of memory. through a resistor.
174 Am79C971
CAUTION: Care should be ex- SRAM accesses are word orient-

ercised when choosing the PCI ed only, EPADDRL[0] is the least
clock pin because of the nature significant word address bit. On
of the PCI clock signal. The PCI any byte write accesses to the
specification states that the SRAM, the user will have to fol-
PCI clock can be stopped. If low the read-modify-write
that can occur while it is being scheme. On any byte read ac-
used for the Expansion Bus cesses to the SRAM, the user will
clock data, corruption will re- have to chose which byte is
sult. needed from the complete word
returned in BCR30.
CAUtiON: The external clock
source used to drive the EB- Flash accesses are started when
CLK pin must be a continuous a read or write is performed on
clock source at all times. BCR30 and the FLASH (BCR 29,
bit 15) is set to 1. During Flash
2-0 CLK_FAC Clock Factor. These bits are used accesses all bits in EPADDR are
to select whether the clock select- valid.
ed by EBCS is used directly or if it
is divided down to give a slower Read accessible always; write
clock for running the Expansion accessible only when the STOP
Bus access cycles. The possible is set or when SRAM SIZE
factors are given in Table 39. (BCR25, bits 7-0) is 0. EPADDRL
is undefined after H_RESET and
is unaffected by S_RESET or
Table 39. CLK_FAC Values STOP.
CLK_FAC Clock Factor
BCR29: Expansion Port Address Upper (Used for
000 1 Flash/EPROM Accesses)
001 1/2 (divide by 2)
010 Reserved
011 1/4 (divide by 4)
1XX Reserved
Read accessible always; write 15 FLASH Flash Access. When the FLASH
accessible only when the STOP bit is set to 1 the Expansion Bus
bit is set. CLK_FAC is set to 000b access will be a Flash cycle.
during H_RESET and is unaffect- When FLASH is set to 0 the Ex-
ed by S_RESET or STOP. pansion Bus access will be a
SRAM cycle. For a complete de-
BCR28: Expansion Bus Port Address Lower (Used
scription see the section on Ex-
for Flash/EPROM and SRAM Accesses)
pansion Bus Interface. This bit is
Bit Name Description only applicable to reads or writes
to EBDATA (BCR30). It does not
31-8 RES Reserved locations. Written as affect Expansion ROM accesses
zeros and read as undefined. from the PCI system bus.
15-0 EPADDRL Expansion Port Address Lower. Read accessible always; write
This address is used to provide accessible only when the STOP
addresses for the Flash and bit is set. FLASH is 0 after
SRAM port accesses. H_RESET and is unaffected by
S_RESET or the STOP bit.
SRAM accesses are started
when a read or write is performed 14 LAAINC Lower Address Auto Increment.
on BCR30 and the FLASH (BCR When the LAAINC bit is set to 1,
29, bit 15) is set to 0. During the Expansion Port Lower Ad-
SRAM accesses only bits in the dress will automatically increment
EPADDRL are valid. Since all by one after a read or write ac-
Am79C971 175
cess to EBDATA (BCR30). When port. The Flash and SRAM ac-
EBADDRL reaches FFFFh and cesses use different address
LAAINC is set to 1, the Expansion phases. Incorrect configuration
Port Lower Address (EPADDRL) will result in a possible corruption
will roll over to 0000h. When the of data.
LAAINC bit is set to 0, the Expan-
sion Port Lower Address will not Flash read cycles are performed
be affected in any way after an when BCR30 is read and the
access to EBDATA (BCR30) and FLASH bit (BCR29, bit 15) is set
must be programmed. to 1. Upon completion of the read
cycle, the 8-bit result for Flash ac-
Read accessible always; write cess is stored in EBDATA[7:0],
accessible only when the STOP EBDATA[15:8] is undefined.
bit is set. LAINC is 0 after Flash write cycles are performed
H_RESET and is unaffected by when BCR30 is written and the
S_RESET or the STOP bit. FLASH bit (BCR29, bit 15) is set
to 1. EBDATA[7:0] only is valid
13-4 RES Reserved locations. Written as for write cycles.
SRAM read cycles are performed
3-0 EPADDRU Expansion Port Address Upper. when BCR30 is read and the
This upper portion of the Expan- FLASH bit (BCR29, bit 15) is set
sion Bus address is used to pro- to 0. Upon completion of the read
vide addresses for Flash/EPROM cycle, the 16-bit result for SRAM
port accesses. access is stored in EBDATA.
Write cycles to the SRAM are in-
Read accessible always; write voked when BCR30 is written
accessible only when the STOP and the FLASH bit (BCR29, bit
bit is set or when SRAM SIZE 15) is set to 0. Byte writes to the
(BCR25, bits 7-0) is 0. EPADD- SRAM must use a read-modify-
RU is undefined after H_RESET write scheme since the word is al-
and is unaffected by S_RESET or ways valid for SRAM write or
the STOP bit. read accesses.
BCR30: Expansion Bus Data Port Register Read and write accessible only
Bit Name Description when the STOP is set or when
SRAM SIZE (BCR25, bits 7-0) is
31-16 RES Reserved locations. Written as 0. EBDATA is undefined after
zeros and read as undefined. H_RESET, and is unaffected by
S_RESET and the STOP bit.
15-0 EBDATA Expansion Bus Data Port. EBDA-
TA is the data port for operations BCR31: Software Timer Register
on the Expansion Port accesses Bit Name Description
involving SRAM and Flash ac-
cesses. The type of access is set 31-16 RES Reserved locations. Written as
by the FLASH bit (BCR 29, bit zeros and read as undefined.
15). When the FLASH bit is set to
1, the Expansion Bus access will 15-0 STVAL Software Timer Value. STVAL
follow the Flash access timing. controls the maximum time for
When the FLASH bit is set to 0, the Software Timer to count be-
the Expansion Bus access will fore generating the STINT
follow the SRAM access timing. (CSR7, bit 11) interrupt. The Soft-
ware Timer is a free-running timer
Note: It is important to set the that is started upon the first write
FLASH bit and load Expansion to STVAL. After the first write, the
Port Address EPADDR (BCR28, Software Timer will continually
BCR29) with the required ad- count and set the STINT interrupt
dress before attempting read or at the STVAL period.
write to the Expansion Bus data
176 Am79C971
The STVAL value is interpreted IPD bit will set the MIIPDINT bit in
as an unsigned number with a CSR7, bit 1.
resolution of 12.8 µs. For in-
stance, a value of 122 ms would Read accessible always. MIIPD
be programmed with a value of is read only. Write operations are
9531 (253Bh). A value of 0 is un- ignored.
defined and will result in erratic
behavior. 13-12 FMDC Fast Management Data Clock.
When FMDC is set to 2h the MII
Read and write accessible al- Management Data Clock will run
ways. STVAL is set to FFFFh af- at 10 MHz. The Management
ter H_RESET and is unaffected Data Clock will no longer be IEEE
by S_RESET and the STOP bit. 802.3u-compliant and setting this
bit should be used with care. The
BCR32: MII Control and Status Register accompanying external PHY
Note: Bits 15-0 in this register are programmable must also be able to accept man-
through the EEPROM. agement frames at the new clock
rate. When FMDC is set to 1h, the
Bit Name Description MII Management Data Clock will
run at 5 MHz. The Management
31-16 RES Reserved locations. Written as Data Clock will no longer be IEEE
zeros and read as undefined. 802.3u-compliant and setting this
bit should be used with care. The
15 ANTST Reserved. Reserved for manu-
accompanying external PHY
facturing tests. Written as 0 and
must also be able to accept man-
read as undefined.
agement frames at the new clock
Note: Use of this bit will cause rate. When FMDC is set to 0h, the
data corruption and erroneous MII Management Data Clock will
operation. run at 2.5 MHz and will be fully
compliant to IEEE 802.3u stan-
Read/Write accessible always. dards.
ANTST is set to 0 by H_RESET
and the STOP bit. Table 40. FMDC Values
FMDC Fast Management Data Clock
14 MIIPD MII PHY Detect. MIIPD reflects
00 2.5 MHz
the quiescent state of the MDIO
01 5 MHz
pin. MIIPD is continuously updat-
10 10 MHz
ed whenever there is no manage-
ment operation in progress on the 11 Reserved
MII interface. When a manage-
ment operation begins on the in- Read/Write accessible always.
terface, the state of MIIPD is FMDC is set to 0 during
preserved until the operation H_RESET, and is unaffected by
ends, when the quiescent state is S_RESET and the STOP bit
again monitored and continuous-
11 APEP MII Auto-Poll External PHY.
ly updates the MIIPD bit. When
APEP when set to 1 the
the MDIO pin is at a quiescent
Am79C971 controller will poll the
LOW state, MIIPD is cleared to 0.
MII status register in the external
When the MDIO pin is at a quies-
PHY. This feature allows the soft-
cent HIGH state, MIIPD is set to
ware driver or upper layers to see
1. MIIPD is used by the automatic
any changes in the status of the
port selection logic to select the
external PHY. An interrupt when
MII port. When the Auto Select bit
enabled is generated when the
(ASEL, BCR2, bit 1) is a 1 and the
contents of the new status is dif-
MIIPD bit is a 1, the MII port is se-
ferent from the previous status.
lected. Any transition on the MI-
Auto-Poll will not function when
the internal PHY is selected.
Am79C971 177
Read/Write accessible always. agement frames that will reset the

APEP is set to 0 during external PHY. This bit is needed
H_RESET and is unaffected by when there is no way to guaran-
S_RESET and the STOP bit. tee the state of the external PHY.
This bit must be reprogrammed
10-8 APDW MII Auto-Poll Dwell Time. APDW after every H_RESET.
determines the dwell time be-
tween MII Management Frames Read/Write accessible always.
accesses when Auto-Poll is XPHYRST is set to 0 by
turned on. See Table 41. H_RESET and is unaffected by
XPHYRST is only valid when the
Table 41. APDW Values internal Network Port Manager is
scanning for a network port.
APDW Auto-Poll Dwell Time
000 Continuous (26µs @ 2.5 MHz) 5 XPHYANE External PHY Auto-Negotiation
001 Every 128 MDC cycles (103µs @ 2.5 MHz) Enable. This bit will force the ex-
010 Every 256 MDC cycles (206µs @ 2.5 MHz) ternal PHY into enabling Auto-
011 Every 512 MDC cycles (410 µs @ 2.5 MHz) Negotiation. When set to 0 the
100 Every 1024 MDC cycles (819 µs @ 2.5 MHz) Am79C971 controller will send a
101 Every 2048 MDC cycles (1640 µs @ 2.5 MHz) MII management frame disabling
110-111 Reserved Auto-Negotiation.

APDW is set to 100h after XPHYANE is set to 0 by
H_RESET and is unaffected by H_RESET and is unaffected by
S_RESET and the STOP bit. S_RESET and the STOP bit.
XPHYANE is only valid when the
7 DANAS Disable Auto-Negotiation Auto internal Network Port Manager is
Setup. When DANAS is set, the scanning for a network port.
Am79C971 controller after a
H_RESET or S_RESET will re- 4 XPHYFD External PHY Full Duplex. When
main dormant and not automati- set, this bit will force the external
cally startup the Auto-Negotiation PHY into full duplex when Auto-
section or the enhanced automat- Negotiation is not enabled.
ic port selection section. Instead,
the Am79C971 controller will wait
XPHYFD is set to 0 by
for the software driver to setup
H_RESET, and is unaffected by
the Auto-Negotiation portions of
the device. The automatic port
XPHYFD is only valid when the
selection for Am79C971 control-
internal Network Port Manager is
ler will resemble the Pcnet-PCI II
controller. The MII programming
in BCR33 and BCR34 is still valid.
3 XPHYSP External PHY Speed. When set,
The Am79C971 controller will not
this bit will force the external PHY
generate any management
into 100 Mbps mode when Auto-
frames unless Auto-Poll is en-
Negotiation is not enabled.
abled.
Read/write accessible always.
XPHYSP is set to 0 by
DANAS is set to 0 by H_RESET
H_RESET, and is unaffected by
and the STOP bit.
XPHYSP is only valid when the
internal Network Port Manager is
6 XPHYRST External PHY Reset. When XPH-
YRST is set, the Am79C971 con-
troller after an H_RESET or 2 MIIµL Media Independent Interface for
S_RESET will issue an MII man- Micro Linear 6692. When set, this
178 Am79C971
bit will allow the Am79C971 con- valid when the internal Network
troller to work seamlessly with the Port Manager is scanning for a
Micro Linear 6692 PHY. See the network port. See Table 40.
section on Working with Micro
Linear 6692 for details. BCR33: MII Address Register
MIIµL is set to 0 by H_RESET 31-16 RES Reserved locations. Written as
and is unaffected by S_RESET zeros and read as undefined.
and the STOP bit. MIIµL is only
valid when the internal Network 15-10 RES Reserved locations. Written as
Port Manager is scanning for a zeros and read as undefined.
network port.
9-5 PHYAD MII Management Frame PHY Ad-
1 MIIILP Media Independent Interface In- dress. PHYAD contains the 5-bit
ternal Loopback. When set, this PHY Address field that is used in
bit will cause the internal portion the management frame that gets
of the MII data port to loopback clocked out via the MII manage-
on itself. The interface is mapped ment port pins (MDC and MDIO)
in the following way. The whenever a read or write transac-
TXD[3:0] nibble data path is tion occurs to BCR34. The inter-
looped back onto the RXD[3:0] nal PHY device is always
nibble data path. TX_CLK is addressed as 11111b. The MII
looped back as RX_CLK. TX_EN management frame will not ap-
is looped back as RX_DV. CRS is pear on the MII when reading or
correctly OR’d with TX_EN and writing to the internal PHY. This is
RX_DV and always encompass- done for MII compatibility sake.
es the transmit frame. TX_ER is
looped back as RX_ER. Howev- The Network Port Manager cop-
er, TX_ER will not get asserted ies the PHYAD after the
by the Am79C971 controller to Am79C971 controller reads the
signal an error. The TX_ER func- EEPROM and uses it to commu-
tion is reserved for future use. nicate with the external PHY. The
PHY address must be pro-
Read/Write accessible always. grammed into the EEPROM prior
MIIILP is set to 0 by H_RESET to starting the Am79C971 con-
and is unaffected by S_RESET troller.
and the STOP bit.
0 FCON Fast Configuration Mode. When PHYAD is undefined after
set this bit will force the internal H_RESET and is unaffected by
Management Port State Machine S_RESET and the STOP bit.
into a Fast Configuration Mode.
During this mode, the Manage- 4-0 REGAD MII Management Frame Register
ment Port State Machine will not Address. REGAD contains the 5-
attempt to start Auto-Negotiation bit Register Address field that is
on the internal as well as the ex- used in the management frame
ternal PHY. Instead, it will rely on that gets clocked out via the MII
link beats for link pass state. This management port pins (MDC and
will accelerate the automatic port MDIO) whenever a read or write
selection on the Am79C971 con- transaction occurs to BCR34.
troller.
Read/Write accessible always. REGAD is undefined after
FCON is set to 0 by H_RESET H_RESET and is unaffected by
and is unaffected by S_RESET S_RESET and the STOP bit.
and the STOP bit. FCON is only
Am79C971 179
BCR34: MII Management Data Register Vendor ID is not the same as the
Bit Name Description Manufacturer ID in CSR88 and
CSR89. The Vendor ID is as-
31-16 RES Reserved locations. Written as signed by the PCI Special Inter-
zeros and read as undefined. est Group.
15-0 MIIMD MII Management Data. MIIMD is The Vendor ID is not normally
the data port for operations on the programmable, but the
MII management interface (MDIO Am79C971 controller allows this
and MDC). The Am79C971 de- due to legacy operating systems
vice builds management frames that do not look at the PCI Sub-
using the PHYAD and REGAD system Vendor ID and the Ven-
values from BCR33. The opera- dor ID to uniquely identify the
tion code used in each frame is add-in board or subsystem that
based upon whether a read or the Am79C971 controller is used
write operation has been per- in.
formed to BCR34. Read cycles
Note: If the operating system
on the MII management interface
or the network operating sys-
are invoked when BCR34 is read.
tem supports PCI Subsystem
Upon completion of the read cy-
Vendor ID and Subsystem ID,
cle, the 16-bit result of the read
use those to identify the add-in
operation is stored in MIIMD.
board or subsystem and pro-
Write cycles on the MII manage-
gram the VID with the default
ment interface are invoked when
value of 1022h.
BCR34 is written. The value writ-
ten to MIIMD is the value used in VID is aliased to the PCI configu-
the data field of the management ration space register Vendor ID
write frame. (offset 00h).
When the PHYAD (BCR33, bits Read accessible always. VID is
9-5) is 11111b the data written read only. Write operations are
and read from the MIIMD will be
from the internal PHY only. No ignored. VID is set to 1022h by
MII management frame will be H_RESET and is not affected by
sent across the MII when the S_RESET or by setting the STOP
PHYAD is 11111b. bit.
Read/Write accessible always. Initialization Block

MIIMD is undefined after
H_RESET and is unaffected by When SSIZE32 (BCR20, bit 8) is set to 0, the software
S_RESET and the STOP bit. structures are defined to be 16 bits wide. The base ad-
dress of the initialization block must be aligned to a
BCR35: PCI Vendor ID Register DWord boundary, i.e., CSR1, bit 1 and 0 must be
cleared to 0. When SSIZE32 is set to 0, the initialization
block looks like Table 42.
through the EEPROM.
Bit Name Description Note: The Am79C971 controller performs DWord ac-
cesses to read the initialization block. This statement is
31-16 RES Reserved locations. Written as always true, regardless of the setting of the SSIZE32
zeros and read as undefined. bit.
When SSIZE32 (BCR20, bit 8) is set to 1, the software
15-0 VID Vendor ID. The PCI Vendor ID structures are defined to be 32 bits wide. The base ad-
register is a 16-bit register that dress of the initialization block must be aligned to a
identifies the manufacturer of the DWord boundary, i.e., CSR1, bits 1 and 0 must be
Am79C971 controller. AMD’s cleared to 0. When SSIZE32 is set to 1, the initialization
Vendor ID is 1022h. Note that this block looks like Table 43
180 Am79C971
.
Table 42. Initialization Block (SSIZE32 = 0)
Address Bits 15-13 Bit 12 Bits 11-8 Bits 7-4 Bits 3-0
IADR+00h MODE 15-00
IADR+02h PADR 15-00
IADR+04h PADR 31-16
IADR+06h PADR 47-32
IADR+08h LADRF 15-00
IADR+0Ah LADRF 31-16
IADR+0Ch LADRF 47-32
IADR+0Eh LADRF 63-48
IADR+10h RDRA 15-00
IADR+12h RLEN 0 RES RDRA 23-16
IADR+14h TDRA 15-00
IADR+16h TLEN 0 RES TDRA 23-16
Table 43. Initialization Block (SSIZE32 = 1)

Bits Bits Bits Bits Bits Bits Bits Bits
Address 31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0
IADR+00h TLEN RES RLEN RES MODE
IADR+04h PADR 31-00
IADR+08h RES PADR 47-32
IADR+0Ch LADRF 31-00
IADR+10h LADRF 63-32
IADR+14h RDRA 31-00
IADR+18h TDRA 31-00
RLEN and TLEN RDRA and TDRA

When SSIZE32 (BCR20, bit 8) is set to 0, the software RDRA and TDRA indicate where the transmit and re-
structures are defined to be 16 bits wide, and the RLEN ceive descriptor rings begin. Each DRE must be lo-
and TLEN fields in the initialization block are each three cated at a 16-byte address boundary when SSIZE32 is
bits wide. The values in these fields determine the set to 1 (BCR20, bit 8). Each DRE must be located at
number of transmit and receive Descriptor Ring Entries an 8-byte address boundary when SSIZE32 is set to 0
(DRE) which are used in the descriptor rings. Their (BCR20, bit 8).
meaning is shown in Table 44. If a value other than
those listed in Table 44 is desired, CSR76 and CSR78
can be written after initialization is complete.
When SSIZE32 (BCR20, bit 8) is set to 1, the software Table 44. R/TLEN Decoding (SSIZE32 = 0)
structures are defined to be 32 bits wide, and the RLEN R/TLEN Number of DREs
and TLEN fields in the initialization block are each 4 000 1
bits wide. The values in these fields determine the 001 2
number of transmit and receive Descriptor Ring Entries
010 4
(DRE) which are used in the descriptor rings. Their
011 8
meaning is shown in Table 45.
100 16
If a value other than those listed in Table 45 is desired, 101 32
CSR76 and CSR78 can be written after initialization is 110 64
complete. 111 128
Am79C971 181
bit is a 0, it is a physical address and is compared

against the physical address that was loaded through
Table 45. R/TLEN Decoding (SSIZE32 = 1)
the initialization block.
R/TLEN Number of DREs
0000 1 A logical address is passed through the CRC genera-
tor, producing a 32-bit result. The high order 6 bits of
0001 2
the CRC is used to select one of the 64 bit positions in
0010 4
the Logical Address Filter. If the selected filter bit is set,
0011 8
the address is accepted and the frame is placed into
0100 16 memory.
0101 32
0110 64 The Logical Address Filter is used in multicast address-
0111 128 ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message
1000 256
may be intended for the node. It is the node’s responsi-
1001 512
bility to determine if the message is actually intended
11XX 512
for the node by comparing the destination address of
1X1X 512 the stored message with a list of acceptable logical ad-
LADRF dresses.
The Logical Address Filter (LADRF) is a 64-bit mask If the Logical Address Filter is loaded with all zeros and
that is used to accept incoming Logical Addresses. If promiscuous mode is disabled, all incoming logical ad-
the first bit in the incoming address (as transmitted on dresses except broadcast will be rejected. See Figure
the wire) is a 1, it indicates a logical address. If the first 57.
32-Bit Resultant CRC

Received Message 31 26 0
Destination Address
47 1 0
CRC
1 GEN Logical
Address Filter
63 (LADRF) 0
SEL
64
MUX Match
Match = 1 Packet Accepted

Match = 0 Packet Rejected 6
20550D-60
Figure 57. Address Match Logic
PADR (IEEE/ANSI 802.3) maps to the Am79C971 PADR reg-

This 48-bit value represents the unique node address ister as follows: the first byte is compared with
assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and PADR[7:0], with PADR[0] being the least significant bit
used for internal address comparison. PADR[0] is com- of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3)
pared with the first bit in the destination address of the byte is compared with PADR[15:8], again from the least
incoming frame. It must be 0 since only the destination significant bit to the most significant bit, and so on. The
address of a unicast frames is compared to PADR. The sixth byte is compared with PADR[47:40], the least sig-
six hex-digit nomenclature used by the ISO 8802-3 nificant bit being PADR[40].
182 Am79C971
Mode RMD0
The mode register field of the initialization block is cop- Bit Name Description
ied into CSR15 and interpreted according to the de-
scription of CSR15. 31-0 RBADR Receive Buffer address. This field
contains the address of the re-
Receive Descriptors ceive buffer that is associated
When SWSTYLE (BCR20, bits 7-0) is set to 0, then the with this descriptor.
software structures are defined to be 16 bits wide, and
receive descriptors look like Table 46 (CRDA = Current RMD1
Receive Descriptor Address). Bit Name Description
When SWSTYLE (BCR 20, bits 7-0) is set to 2, then the
software structures are defined to be 32 bits wide, and 31 OWN This bit indicates whether the de-
receive descriptors look like Table 47 (CRDA = Current scriptor entry is owned by the
Receive Descriptor Address). host (OWN = 0) or by the
Am79C971 controller (OWN = 1).
When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the The Am79C971 controller clears
software structures are defined to be 32 bits wide, and the OWN bit after filling the buffer
receive descriptors look like Table 48 (CRDA = Current that the descriptor points to. The
Receive Descriptor Address). host sets the OWN bit after emp-
tying the buffer
Table 46. Receive Descriptor (SWSTYLE = 0)

Address 15 14 13 12 11 10 9 8 7-0
CRDA+00h RBADR[15:0]
CRDA+02h OWN ERR FRAM OFLO CRC BUFF STP ENP RBADR[23:16]
CRDA+04h 1 1 1 1 BCNT
CRDA+06h 0 0 0 0 MCNT
Table 47. Receive Descriptor (SWSTYLE = 2

Address 31 30 29 28 27 26 25 24 23 22 21 20 19-16 15-12 11-0
FRA OFL BUF
CRDA+04h OWN ERR CRC STP ENP BPE PAM LAFM BAM RES 1111 BCNT
M O F
CRDA+08h RES RFRTAG[14:0] 0000 MCNT
CRDA+0Ch USER SPACE
Table 48. Receive Descriptor (SWSTYLE = 3)

Address 31 30 29 28 27 26 25 24 23 22 21 20 19-16 15-12 11-0
CRDA+00h RES RFRTAG[14:0] 0000 MCNT
FRA OFL BUF
CRDA+04h OWN ERR CRC STP ENP BPE PAM LAFM BAM RES 1111 BCNT
M O F
CRDA+0Ch USER SPACE
Am79C971 183
Once the Am79C971 controller or If a Buffer Error occurs, an Over-

host has relinquished ownership flow Error may also occur inter-
of a buffer, it must not change any nally in the FIFO, but will not be
field in the descriptor entry. reported in the descriptor status
entry unless both BUFF and
30 ERR ERR is the OR of FRAM, OFLO, OFLO errors occur at the same
CRC, BUFF, or BPE. ERR is set time. BUFF is set by the
by the Am79C971 controller and Am79C971 controller and
cleared by the host. cleared by the host.
29 FRAM Framing error indicates that the 25 STP Start of Packet indicates that this
incoming frame contains a non- is the first buffer used by the
integer multiple of eight bits and Am79C971 controller for this
there was an FCS error. If there frame. If STP and ENP are both
was no FCS error on the incom- set to 1, the frame fits into a single
ing frame, then FRAM will not be buffer. Otherwise, the frame is
set even if there was a non- spread over more than one buff-
integer multiple of eight bits in the er. When LAPPEN (CSR3, bit 5)
frame. FRAM is not valid in inter- is cleared to 0, STP is set by the
nal loopback mode. FRAM is val- Am79C971 controller and
id only when ENP is set and cleared by the host. When LAP-
OFLO is not. FRAM is set by the PEN is set to 1, STP must be set
Am79C971 controller and by the host.
cleared by the host.
24 ENP End of Packet indicates that this
28 OFLO Overflow error indicates that the is the last buffer used by the
receiver has lost all or part of the Am79C971 controller for this
incoming frame, due to an inabili- frame. It is used for data chaining
ty to move data from the receive buffers. If both STP and ENP are
FIFO into a memory buffer before set, the frame fits into one buffer
the internal FIFO overflowed. and there is no data chaining.
OFLO is set by the Am79C971 ENP is set by the Am79C971
controller and cleared by the controller and cleared by the
host. host.
27 CRC CRC indicates that the receiver 23 BPE Bus Parity Error is set by the
has detected a CRC (FCS) error Am79C971 controller when a par-
on the incoming frame. CRC is ity error occurred on the bus inter-
valid only when ENP is set and face during data transfers to a
OFLO is not. CRC is set by the receive buffer. BPE is valid only
Am79C971 controller and when ENP, OFLO, or BUFF are
cleared by the host. CRC will also set. The Am79C971 controller will
be set when Am79C971 receives only set BPE when the advanced
an RX_ER indication from the ex- parity error handling is enabled
ternal PHY through the MII. by setting APERREN (BCR20, bit
10) to 1. BPE is set by the
26 BUFF Buffer error is set any time the Am79C971 controller and
Am79C971 controller does not cleared by the host.
own the next buffer while data
chaining a received frame. This This bit does not exist when the
can occur in either of two ways: Am79C971 controller is pro-
grammed to use 16-bit software
1. The OWN bit of the next buffer structures for the descriptor ring
is 0. entries (BCR20, bits 7-0, SW-
STYLE is cleared to 0).
2. FIFO overflow occurred before
the Am79C971 controller was 22 PAM Physical Address Match is set by
able to read the OWN bit of the Am79C971 controller when it
the next descriptor. accepts the received frame due
184 Am79C971
to a match of the frame’s destina- This bit does not exist when the
tion address with the content of Am79C971 controller is pro-
the physical address register. grammed to use 16-bit software
PAM is valid only when ENP is structures for the descriptor ring
set. PAM is set by the Am79C971 entries (BCR20, bits 7-0, SW-
controller and cleared by the STYLE is cleared to 0).
host.
19-16 RES Reserved locations. These loca-
This bit does not exist when the tions should be read and written
Am79C971 controller is pro- as zeros.
grammed to use 16-bit software
structures for the descriptor ring 15-12 ONES These four bits must be written as
entries (BCR20, bits 7-0, SW- ones. They are written by the host
STYLE is cleared to 0). and unchanged by the
Am79C971 controller.
21 LAFM Logical Address Filter Match is
set by the Am79C971 controller 11-00 BCNT Buffer Byte Count is the length of
when it accepts the received the buffer pointed to by this de-
frame based on the value in the scriptor, expressed as the two’s
logical address filter register. complement of the length of the
LAFM is valid only when ENP is buffer. This field is written by the
set. LAFM is set by the host and unchanged by the
Am79C971 controller and Am79C971 controller.
RMD2
Note that if DRCVBC (CSR15, bit Bit Name Description
14) is cleared to 0, only BAM, but
not LAFM will be set when a ZERO This field is reserved. The
Broadcast frame is received, Am79C971 controller will write a
even if the Logical Address Filter zero to this location.
is programmed in such a way that
a Broadcast frame would pass 30-16 RFRTAG Receive Frame Tag. Indicates
the hash filter. If DRCVBC is set the Receive Frame Tag applied
to 1 and the Logical Address Fil- from the EADI interface. This field
ter is programmed in such a way is user defined and has a default
that a Broadcast frame would value of all zeros. When RX-
pass the hash filter, LAFM will be FRTG (CSR7, bit 14) is set to 0,
set on the reception of a Broad- RFRTAG will be read as all zeros.
cast frame. See the section on Receive
Frame Tagging for details.
This bit does not exist when the
Am79C971 controller is pro- 15-12 ZEROS This field is reserved. Am79C971
grammed to use 16-bit software controller will write zeros to these
structures for the descriptor ring locations.
entries (BCR20, bits 7-0, SW-
STYLE is cleared to 0). 11-0 MCNT Message Byte Count is the length
in bytes of the received message,
20 BAM Broadcast Address Match is set expressed as an unsigned binary
by the Am79C971 controller integer. MCNT is valid only when
when it accepts the received ERR is clear and ENP is set.
frame, because the frame’s desti- MCNT is written by the
nation address is of the type Am79C971 controller and
’Broadcast.’ BAM is valid only cleared by the host.
when ENP is set. BAM is set by
the Am79C971 controller and Note: This is a 13-bit internal
cleared by the host. counter.
Am79C971 185
RMD3 When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the
Bit Name Description software structures are defined to be 32 bits wide, and
transmit descriptors look like Table 51 (CXDA = Current
31-0 US User Space. Reserved for user Transmit Descriptor Address).
defined space. TMD0
Transmit Descriptors
When SWSTYLE (BCR20, bits 7-0) is set to 0, the soft- 31-0 TBADR Transmit Buffer address. This
ware structures are defined to be 16 bits wide, and field contains the address of the
transmit descriptors look like Table 49 (CXDA = Current transmit buffer that is associated
Transmit Descriptor Address). with this descriptor.
When SWSTYLE (BCR 20, bits 7-0) is set to 2, the soft-
ware structures are defined to be 32 bits wide, and
transmit descriptors look like Table 50 (CXDA = Current
Transmit Descriptor Address).
Table 49. Transmit Descriptor (SWSTYLE = 0)

Address 15 14 13 12 11 10 9 8 7-0
CXDA+00h TBADR[15:0]
ADD_ MORE/
CXDA+02h OWN ERR ONE DEF STP ENP TBADR[23:16]
FCS LTINT
CXDA+04h 1 1 1 1 BCNT
EX
CXDA+06h BUFF UFLO LCOL LCAR RTRY TDR
DEF

Address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0
ADD_ MORE/
CXDA+04h OWN ERR ONE DEF STP ENP BPE RES 1111 BCNT
FCS LTINT
EX
CXDA+08h BUFF UFLO LCOL LCAR RTRY RES RES RES RES RES RES TRC
DEF
CXDA+0Ch USER SPACE

Address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0
EX
CXDA+00h BUFF UFLO LCOL LCAR RTRY RES RES TRC
DEF
ADD_ MORE/
CXDA+04h OWN ERR ONE DEF STP ENP BPE RES 1111 BCNT
FCS LTINT
CXDA+0Ch USER SPACE
186 Am79C971
TMD1 MORE MORE indicates that more than
Bit Name Description one retry was needed to transmit
a frame. The value of MORE is
31 OWN This bit indicates whether the de- written by the Am79C971 control-
scriptor entry is owned by the ler. This bit has meaning only if
host (OWN = 0) or by the the ENP bit is set.
Am79C971 controller (OWN = 1).
LTINT LTINT is used to suppress inter-
The host sets the OWN bit after
rupts after successful transmis-
filling the buffer pointed to by the
sion on selected frames. When
descriptor entry. The Am79C971
LTINT is cleared to 0 and ENP is
controller clears the OWN bit af-
set to 1, the Am79C971 controller
ter transmitting the contents of
will not set TINT (CSR0, bit 9) af-
the buffer. Both the Am79C971
ter a successful transmission.
controller and the host must not
TINT will only be set when the
alter a descriptor entry after it has
last descriptor of a frame has
relinquished ownership.
both LTINT and ENP set to 1.
30 ERR ERR is the OR of UFLO, LCOL, When LTINT is cleared to 0, it will
LCAR, RTRY or BPE. ERR is set only cause the suppression of in-
by the Am79C971 controller and terrupts for successful transmis-
cleared by the host. This bit is set sion. TINT will always be set if the
in the current descriptor when the transmission has an error. The
error occurs and, therefore, may LTINTEN overrides the function
be set in any descriptor of a of TOKINTD (CSR5, bit 15).
chained buffer transmission.
27 ONE ONE indicates that exactly one
29 ADD_FCS ADD_FCS dynamically controls retry was needed to transmit a
the generation of FCS on a frame frame. ONE flag is not valid when
by frame basis. It is valid only if LCOL is set. The value of the
the STP bit is set. When ONE bit is written by the
ADD_FCS is set, the state of Am79C971 controller. This bit
DXMTFCS is ignored and trans- has meaning only if the ENP bit is
mitter FCS generation is activat- set.
ed. When ADD_FCS is cleared to
26 DEF Deferred indicates that the
0, FCS generation is controlled
Am79C971 controller had to de-
by DXMTFCS. When
fer while trying to transmit a
APAD_XMT (CSR4, bit 11) is set
frame. This condition occurs if the
to 1, the setting of ADD_FCS has
channel is busy when the
no effect on frames shorter than
Am79C971 controller is ready to
64 bytes. ADD_FCS is set by the
transmit. DEF is set by the
host, and is not changed by the
Am79C971 controller and
Am79C971 controller. This is a
reserved bit in the C-LANCE
(Am79C90) controller. 25 STP Start of Packet indicates that this
is the first buffer to be used by the
28 MORE/LTINT Bit 28 always functions as
Am79C971 controller for this
MORE. The value of MORE is
frame. It is used for data chaining
written by the Am79C971 control-
buffers. The STP bit must be set
ler and is read by the host. When
in the first buffer of the frame, or
LTINTEN is cleared to 0 (CSR5,
the Am79C971 controller will skip
bit 14), the Am79C971 controller
over the descriptor and poll the
will never look at the contents of
next descriptor(s) until the OWN
bit 28, write operations by the
and STP bits are set. STP is set
host have no effect. When LTINT-
by the host and is not changed by
EN is set to 1 bit 28 changes its
the Am79C971 controller.
function to LTINT on host write
operations and on Am79C971
controller read operations.
Am79C971 187
24 ENP End of Packet indicates that this TMD2
is the last buffer to be used by the Bit Name Description
Am79C971 controller for this
frame. It is used for data chaining 31 BUFF Buffer error is set by the
buffers. If both STP and ENP are Am79C971 controller during
set, the frame fits into one buffer transmission when the
and there is no data chaining. Am79C971 controller does not
ENP is set by the host and is not find the ENP flag in the current
changed by the Am79C971 con- descriptor and does not own the
troller. next descriptor. This can occur in
either of two ways:
23 BPE Bus Parity Error is set by the
Am79C971 controller when a par- 1. The OWN bit of the next buffer
ity error occurred on the bus inter- is 0.
face during a data transfers from
the transmit buffer associated 2. FIFO underflow occurred be-
with this descriptor. The fore the Am79C971 controller ob-
Am79C971 controller will only set tained the STATUS byte
BPE when the advanced parity (TMD1[31:24]) of the next de-
error handling is enabled by set- scriptor. BUFF is set by the
ting APERREN (BCR20, bit 10) to Am79C971 controller and
1. BPE is set by the Am79C971 cleared by the host.
controller and cleared by the
host. If a Buffer Error occurs, an Un-
derflow Error will also occur.
This bit does not exist, when the BUFF is not valid when LCOL or
Am79C971 controller is pro- RTRY error is set during transmit
grammed to use 16-bit software data chaining. BUFF is set by the
structures for the descriptor ring Am79C971 controller and
entries (BCR20, bits 7-0, SW- cleared by the host.
STYLE is cleared to 0).
30 UFLO Underflow error indicates that the
22-16 RES Reserved locations. transmitter has truncated a mes-
sage because it could not read
15-12 ONES These four bits must be written as data from memory fast enough.
ones. This field is written by the UFLO indicates that the FIFO has
host and unchanged by the emptied before the end of the
Am79C971 controller. frame was reached.
11-00 BCNT Buffer Byte Count is the usable When DXSUFLO (CSR3, bit 6) is
length of the buffer pointed to by cleared to 0, the transmitter is
this descriptor, expressed as the turned off when an UFLO error
two’s complement of the length of occurs (CSR0, TXON = 0).
the buffer. This is the number of
bytes from this buffer that will be When DXSUFLO is set to 1, the
transmitted by the Am79C971 Am79C971 controller gracefully
controller. This field is written by recovers from an UFLO error. It
the host and is not changed by scans the transmit descriptor ring
the Am79C971 controller. There until it finds the start of a new
are no minimum buffer size re- frame and starts a new transmis-
strictions. sion.
UFLO is set by the Am79C971

host.
29 EXDEF Excessive Deferral. Indicates that

the transmitter has experienced
Excessive Deferral on this trans-
188 Am79C971
mit frame, where Excessive De- 26 RTRY Retry error indicates that the
ferral is defined in the ISO 8802-3 transmitter has failed after 16 at-
(IEEE/ANSI 802.3) standard. Ex- tempts to successfully transmit a
cessive Deferral will also set the message, due to repeated colli-
interrupt bit EXDINT (CSR5, bit sions on the medium. If DRTY is
7). set to 1 in the MODE register,
RTRY will set after one failed
28 LCOL Late Collision indicates that a col- transmission attempt. RTRY is
lision has occurred after the first set by the Am79C971 controller
channel slot time has elapsed. and cleared by the host.
The Am79C971 controller does
not retry on late collisions. LCOL 25-16 RES Reserved locations.
is set by the Am79C971 controller
and cleared by the host. 15-4 RES Reserved locations.
27 LCAR Loss of Carrier is set when the 3-0 TRC Transmit Retry Count. Indicates
carrier is lost during an the number of transmit retries of
Am79C971 controller initiated the associated packet. The maxi-
transmission when in AUI mode mum count is 15. However, if a
and the device is operating in RETRY error occurs, the count
half-duplex mode. The will roll over to 0.
Am79C971 controller does not
retry upon loss of carrier. It will In this case only, the Transmit
continue to transmit the whole Retry Count value of 0 should be
frame until done. LCAR will not interpreted as meaning 16. TRC
be set when the device is operat- is written by the Am79C971 con-
ing in full-duplex mode and the troller into the last transmit de-
AUI port is active. LCAR is not scriptor of a frame, or when an
valid in Internal Loopback Mode. error terminates a frame. Valid
LCAR is set by the Am79C971 only when OWN is cleared to 0.
TMD3
host.
LCAR does not reflect a link sta-
tus problem on the external PHY. 31-0 US User Space. Reserved for user
defined space.
In 10BASE-T mode, LCAR will be
set when the T-MAU was in Link
Fail state during the transmis-
sion.
Am79C971 189
REGISTER SUMMARY
PCI Configuration Registers
Width Access Default

Offset Name in Bit Mode Value
00h PCI Vendor ID 16 RO 1022h
02h PCI Device ID 16 RO 2000h
04h PCI Command 16 RW 0000h
06h PCI Status 16 RW 0280h
08h PCI Revision ID 8 RO 10h
09h PCI Programming IF 8 RO 00h
0Ah PCI Sub-Class 8 RO 00h
0Bh PCI Base-Class 8 RO 02h
0Ch Reserved 8 RO 00h
0Dh PCI Latency Timer 8 RW 00h
0Eh PCI Header Type 8 RO 00h
0Fh Reserved 8 RO 00h
10h PCI I/O Base Address 32 RW 0000 0001h
14h PCI Memory Mapped I/O Base Address 32 RW 0000 0000h
18h - 2Bh Reserved 8 RO 00h
2Ch PCI Subsystem Vendor ID 16 RO 00h
2Eh PCI Subsystem ID 16 RO 00h
30h PCI Expansion ROM Base Address 32 RW 0000 0000h
34h - 3Bh Reserved 8 RO 00h
3Ch PCI Interrupt Line 8 RW 00h
3Dh PCI Interrupt Pin 8 RO 01h
3Eh PCI MIN_GNT 8 RO 06h
3Fh PCI MAX_LAT 8 RO FFh
40h - FFh Reserved 8 RO 00h
Note:
RO = read only, RW = read/write
190 Am79C971
Control and Status Registers
RAP
Addr Symbol Default Value Comments Use
00 CSR0 uuuu 0004 Am79C971 Controller Status Register R
01 CSR1 uuuu uuuu Lower IADR: maps to location 16 S
02 CSR2 uuuu uuuu Upper IADR: maps to location 17 S
03 CSR3 uuuu 0000 Interrupt Masks and Deferral Control S
04 CSR4 uuuu 0115 Test and Features Control R
05 CSR5 uuuu 0000 Extended Control and Interrupt 1 R
06 CSR6 uuuu uuuu RXTX: RX/TX Encoded Ring Lengths S
07 CSR7 0uuu 0000 Extended Control and Interrupt 1 R
08 CSR8 uuuu uuuu LADRF0: Logical Address Filter — LADRF[15:0] S
12 CSR12 uuuu uuuu PADR0: Physical Address Register — PADR[15:0][ S
13 CSR13 uuuu uuuu PADR1: Physical Address Register — PADR[31:16] S
14 CSR14 uuuu uuuu PADR2: Physical Address Register — PADR[47:32] S
see register
15 CSR15 MODE: Mode Register S
description
16 CSR16 uuuu uuuu IADRL: Base Address of INIT Block Lower (Copy) T
17 CSR17 uuuu uuuu IADRH: Base Address of INIT Block Upper (Copy) T
18 CSR18 uuuu uuuu CRBAL: Current RCV Buffer Address Lower T
19 CSR22 uuuu uuuu CRBAU: Current RCV Buffer Address Upper T
20 CSR20 uuuu uuuu CXBAL: Current XMT Buffer Address Lower T
21 CSR21 uuuu uuuu CXBAU: Current XMT Buffer Address Upper T
22 CSR22 uuuu uuuu NRBAL: Next RCV Buffer Address Lower T
23 CSR23 uuuu uuuu NRBAU: Next RCV Buffer Address Upper T
24 CSR24 uuuu uuuu BADRL: Base Address of RCV Ring Lower S
25 CSR25 uuuu uuuu BADRU: Base Address of RCV Ring Upper S
26 CSR26 uuuu uuuu NRDAL: Next RCV Descriptor Address Lower T
27 CSR27 uuuu uuuu NRDAU: Next RCV Descriptor Address Upper T
28 CSR28 uuuu uuuu CRDAL: Current RCV Descriptor Address Lower T
29 CSR29 uuuu uuuu CRDAU: Current RCV Descriptor Address Upper T
30 CSR30 uuuu uuuu BADXL: Base Address of XMT Ring Lower S
31 CSR31 uuuu uuuu BADXU: Base Address of XMT Ring Upper S
32 CSR32 uuuu uuuu NXDAL: Next XMT Descriptor Address Lower T
33 CSR33 uuuu uuuu NXDAU: Next XMT Descriptor Address Upper T
Note:
u = undefined value, R = Running register, S = Setup register, T = Test register; all default values are in hexadecimal format.
Am79C971 191
CONTROL AND STATUS REGISTERS (CONTINUED)
RAP Default Value

Addr Symbol After H_RESET Comments Use
34 CSR34 uuuu uuuu CXDAL: Current XMT Descriptor Address Lower T
35 CSR35 uuuu uuuu CXDAU: Current XMT Descriptor Address Upper T
36 CSR36 uuuu uuuu NNRDAL: Next Next Receive Descriptor Address Lower T
37 CSR37 uuuu uuuu NNRDAU: Next Next Receive Descriptor Address Upper T
38 CSR38 uuuu uuuu NNXDAL: Next Next Transmit Descriptor Address Lower T
39 CSR39 uuuu uuuu NNXDAU: Next Next Transmit Descriptor Address Upper T
40 CSR40 uuuu uuuu CRBC: Current Receive Byte Count T
41 CSR41 uuuu uuuu CRST: Current Receive Status T
42 CSR42 uuuu uuuu CXBC: Current Transmit Byte T
43 CSR43 uuuu uuuu CXST: Current Transmit Status T
44 CSR44 uuuu uuuu NRBC: Next RCV Byte Count T
45 CSR45 uuuu uuuu NRST: Next RCV Status T
46 CSR46 uuuu uuuu TXDPOLL: Transmit Poll Time Counter T
47 CSR47 uuuu uuuu TXPI: Transmit Polling Interval S
48 CSR48 uuuu uuuu RXPOLL: Receive Poll Time Counter
49 CSR49 uuuu uuuu RXPI: Receive Polling Interval
50 CSR50 uuuu uuuu Reserved
see register
58 CSR58 SWS: Software Style S
description
59 CSR59 uuuu uuuu Reserved T
60 CSR60 uuuu uuuu PXDAL: Previous XMT Descriptor Address Lower T
61 CSR61 uuuu uuuu PXDAU: Previous XMT Descriptor Address Upper T
62 CSR62 uuuu uuuu PXBC: Previous Transmit Byte Count T
63 CSR63 uuuu uuuu PXST: Previous Transmit Status T
64 CSR64 uuuu uuuu NXBAL: Next XMT Buffer Address Lower T
65 CSR65 uuuu uuuu NXBAU: Next XMT Buffer Address Upper T
66 CSR66 uuuu uuuu NXBC: Next Transmit Byte Count T
67 CSR67 uuuu uuuu NXST: Next Transmit Status T
192 Am79C971
Control and Status Registers (Continued)
RAP Default Value

72 CSR72 uuuu uuuu RCVRC: RCV Ring Counter T
74 CSR74 uuuu uuuu XMTRC: XMT Ring Counter T
76 CSR76 uuuu uuuu RCVRL: RCV Ring Length S
78 CSR78 uuuu uuuu XMTRL: XMT Ring Length S
80 CSR80 uuuu 1410 DMATCFW: DMA Transfer Counter and FIFO Threshold S
82 CSR82 uuuu uuuu Transmit Descriptor Pointer Address Lower S
84 CSR84 uuuu uuuu DMABA: Address Register Lower T
85 CSR85 uuuu uuuu DMABA: Address Register Upper T
86 CSR86 uuuu uuuu DMABC: Buffer Byte Counter T
88 CSR88 x262 3003 Chip ID Register Lower T
89 CSR89 uuuu x262 Chip ID Register Upper T
91 CSR91 uuuu uuuu Reserved T
92 CSR92 uuuu uuuu RCON: Ring Length Conversion T
100 CSR100 uuuu 0200 Bus Timeout S
103 CSR103 uuuu 0105 Reserved
Am79C971 193
CONTROL AND STATUS REGISTERS (CONCLUDED)
RAP Default Value

112 CSR112 uuuu uuuu Missed Frame Count R
114 CSR114 uuuu uuuu Received Collision Count R
122 CSR226 uuuu 0000 Receive Frame Alignment Control S
124 CSR248 uuuu 0000 Test Register 1 T
125 CSR125 003c 0060 MAC Enhanced Configuration Control T
194 Am79C971
Bus Configuration Registers
Writes to those registers marked as “Reserved” will have no effect. Reads from these locations will produce unde-
fined values.
Programmability
RAP Mnemonic Default Name User EEPROM
0 MSRDA 0005h Reserved No No
1 MSWRA 0005h Reserved No No
2 MC 0002h Miscellaneous Configuration Yes Yes
4 LED0 00C0h LED0 Status Yes Yes
9 FDC 0000h Full-Duplex Control Yes Yes
10-15 Reserved N/A Reserved No No
16 IOBASEL N/A Reserved No No
17 IOBASEU N/A Reserved No No
18 BSBC 9001h Burst and Bus Control Yes Yes
19 EECAS 0002h EEPROM Control and Status Yes No
20 SWS 0200h Software Style Yes No
21 INTCON N/A Reserved No No
22 PCILAT FF06h PCI Latency Yes Yes
23 PCISID 0000h PCI Subsystem ID No Yes
24 PCISVID 0000h PCI Subsystem Vendor ID No Yes
25 SRAMSIZ 0000h SRAM Size Yes Yes
26 SRAMB 0000h SRAM Boundary Yes Yes
27 SRAMIC 0000h SRAM Interface Control Yes Yes
28 EBADDRL N/A Expansion Bus Address Lower Yes No
29 EBADDRU N/A Expansion Bus Address Upper Yes No
30 EBDR N/A Expansion Bus Data Port Yes No
31 STVAL FFFFh Software Timer Value Yes No
32 MIICAS 0000h MII Control and Status Yes Yes
33 MIIADDR N/A MII Address Yes Yes
34 MIIMDR N/A MII Management Data Yes No
35 PCIVID 1022h PCI Vendor ID No Yes
Am79C971 195
REGISTER PROGRAMMING SUMMARY
Am79C971 Programmable Registers
Am79C971 Control and Status Registers
Register Contents
CSR0 Status and control bits: (DEFAULT = 0004)
8000 ERR 0800 MERR 0080 INTR 0008 TDMD
4000 BABL 0400 RINT 0040 IENA 0004 STOP
2000 CERR 0200 TINT 0020 RXON 0002 STRT
1000 MISS 0100I IDON 0010 TXON 0001 INIT
CSR1 Lower IADR (Maps to CSR 16)
CSR2 Upper IADR (Maps to CSR 17)
CSR3 Interrupt masks and Deferral Control: (DEFAULT = 0)
8000-- 0800 MERRM 0080- - 0008 EMBA
4000 BABLM 0400 RINTM 0040 DXSUFLO 0004 BSWP
2000 - 0200 TINTM 0020 LAPPEN 0002 --
1000 MISSM 0100I DONM 0010 DXMT2PD 0001 --
CSR4 Interrupt masks, configuration and status bits: (DEFAULT = 0115)
8000 EN124 0800 APAD_XMT 0080 UNITCMD 0008 TXSTRT
4000 DMAPLUS 0400 ASTRP_RCV 0040 UNIT 0004 TXSTRTM
2000 TIMER 0200 MFCO 0020 RCVCCO 0002 JAB
1000 TXDPOLL 0100 MFCOM 0010 RCVCCOM 0001 JABM
CSR5 Extended Interrupt masks, configuration and status bits: (DEFAULT = 0XXX)
8000TOKINTD 0800 SINT 0080 EXDINT 0008 MPINTE
4000LTINTEN 0400 SINTE 0040 EXDINTE 0004 MPEN
2000-- 0200 SLPINT 0020 MPPLBA 0002 MPMODE
1000-- 0100 SLPINTE 0010 MPINT 0001 SPND
CSR7 Extended Interrupt masks, configuration and status bits: (DEFAULT = 0000)
8000 FASTSPND 0800 STINT 0080 MAPINT 0008 MCCIINT
4000 RXFRMTG 0400 STINTE 0040 MAPINTE 0004 MCCIINTE
2000 RDMD 0200 MREINT 0020 MCCINT 0002 MIIPDTINT
1000 RXDPOLL 0100 MREINTE 0010 MCCINTE 0001 MIIPDTNTE
CSR8 - CSR11 Logical Address Filter
CSR12 - CSR14 Physical Address Register
MODE: (DEFAULT = 0)
bits [8:7] = PORTSEL, Port Selection
CSR15 0000AUI port
008010BASE-T
0101Media Independent Interface
8000PROM 0800 DAPC 0080 POTSEL0 0008 DXMTFCS
4000DRCVBC 0400 MENDECL 0040 INTL 0004 LOOP
2000DRCVPA 0200 LRT/TSEL 0020 DRTY 0002 DTX
1000DLNKTST 0100 PORTSEL1 0010 FCOLL 0001 DRX
CSR47 TXPOLLINT: Transmit Polling Interval
CSR49 RXPOLLINT: Receive Polling Interval
196 Am79C971
AM79C971 CONTROL AND STATUS REGISTERS (CONTINUED)
Register Contents
CSR58 Software Style (mapped to BCR20)
bits [7:0] = SWSTYLE, Software Style Register.
0000 LANCE/PCnet-ISA
0002 PCnet-32
8000 -- 0800 -- 0080 SWSTYLE7 0008 SWSTYLE3
4000 -- 0400 APERREN 0040 SWSTYLE6 0004 SWSTYLE2
2000 -- 0200 CSRPCNET 0020 SWSTYLE5 0002 SWSTYLE1
1000 -- 0100 SSIZE32 0010 SWSTYLE4 0001 SWSTYLE0
CSR76 RCVRL: RCV Descriptor Ring length
CSR78 XMTRL: XMT Descriptor Ring length
CSR80 FIFO threshold and DMA burst control. (DEFAULT = 2810)
8000 Reserved
4000 Reserved
bits [13:12] = RCVFW, Receive FIFO Watermark
0000 Request DMA when 16 bytes are present
3000 Reserved
bits [11:10] = XMTSP, Transmit Start Point
0000 Start transmission after 20/44 (No SRAM/SRM) bytes have been written
0400 Start transmission after 64 bytes have been written
0800 Start transmission after 128 bytes have been written
0C00 Start transmission after 248 bytes (full packet) have been written
bits [9:8] = XMTFW, Transmit FIFO Watermark
0000 Start DMA when 16 write cycles can be made
0300 Reserved
bits [7:0] = DMA Transfer Counter
CSR88~89 Chip ID (Contents = v2623003; v = Version Number)
CSR112 Missed Frame Count
CSR114 Receive Collision Count
CSR122 Receive Frame Alignment Control
8000 -- 0800 -- 0080 -- 0008 --
4000 -- 0400 -- 0040 -- 0004 --
2000 -- 0200 -- 0020 -- 0002 --
1000 -- 0100 -- 0010 -- 0001 RCVALGN
CSR124 BMU Test Register (DEFAULT = 0000)
8000 -- 0800 -- 0080 -- 0008 GPSIEN
4000 -- 0400 -- 0040 -- 0004 RPA
2000 -- 0200 -- 0020 -- 0002 --
1000 -- 0100 -- 0010 -- 0001 --
CSR125 MAC Enhanced Configuration Control (DEFAULT = 603c
bits [15:8] = IPG, InterPacket Gap (Default=60xx, 96 bit times)
bits [8:0] = IFS1, InterFrame Space Part 1 (Default=xx3c, 60 bit times)
Am79C971 197
Am79C971 Bus Configuration Registers
RAP
Addr Register Contents
0 MSRDA Programs width of DMA read signal (DEFAULT = 5)
1 MSWRA Programs width of DMA write signal (DEFAULT = 5)
2 MC Miscellaneous Configuration bits: (DEFAULT = 2)
8000 -- 0800 -- 0080 INITLEVEL 0008 EADISEL
4000 TMAULOOP 0400 -- 0040 -- 0004 AWAKE
2000 -- 0200 -- 0020 -- 0002 ASEL
1000 -- 0100 APROMWE 0010 DRACC 0001 XMAUSEL
4 LED0 Programs the function and width of the LED0 signal. (DEFAULT = 00C0)
8000 LEDOUT 0800 MIISE 0080 PSE 0008 RXPOLE
4000 LEDPOL 0400 DXCVRCTL 0040 LINKSE 0004 RCVE
2000 LEDDIS 0200 MPSE 0020 RCVME 0002 JABE
1000 100E 0100 FDLSE 0010 XMTE 0001 COLE
5 LED1 Programs the function and width of the LED1 signal. (DEFAULT = 0084)
1000 100E 0100 FDLSE 0010 XMTE 0001 COLE
1000 100E 0100 FDLSE 0010 XMTE 0001 COLE
1000 100E 0100 FDLSE 0010 XMTE 0001 COLE
9 FDC Full-Duplex Control. (DEFAULT= 0000)
8000 -- 0800 -- 0080 -- 0008 --
4000 -- 0400 -- 0040 -- 0004 FDRPAD
2000 -- 0200 -- 0020 -- 0002 AUIFD
1000 -- 0100 -- 0010 -- 0001 FDEN
16 IOBASEL I/O Base Address Lower
17 IOBASEU I/O Base Address Upper
18 BSBC Burst Size and Bus Control (DEFAULT = 2101)
8000 ROMTMG3 0800 NOUFLO 0080 DWIO 0008 TSTSHDW0
4000 ROMTMG2 0400 -- 0040 BREADE 0004 LINBC2
2000 ROMTMG1 0200 MEMCMD 0020 BWRITE 0002 LINBC1
1000 ROMTMG0 0100 EXTREQ 0010 TSTSHDW1 0001 LINBC0
19 EECAS EEPROM Control and Status (DEFAULT = 0002)
8000 PVALID 0800 -- 0080 -- 0008 --
4000 PREAD 0400 -- 0040 -- 0004 ECS
2000 EEDET 0200 -- 0020 -- 0002 ESK
1000 -- 0100 -- 0010 EEN 0001 EDI/
EDO
198 Am79C971
AM79C971 BUS CONFIGURATION REGISTERS (CONTINUED)
20 SWSTYLE Software Style (DEFAULT = 0000, maps to CSR 58)

21 INTCON Interrupt Control
8000 -- 0800-- 0080-- 0008--
0400-- 0040-- 0004--
4000 --
0200-- 0020-- 0002--
2000 -- 0100-- 0010-- 0001--
1000 --
22 PCILAT PCI Latency (DEFAULT = FF06)
bits [15:8] = MAX_LAT
bits [7:0] = MIN_GNT
25 SRAMSIZE SRAM Size (DEFAULT = 000)
bits [7:0] = SRAM_SIZE
26 SRAMBND SRAM Boundary (DEFAULT = 0000)
bits [7:0] = SRAM_BND
27 SRAMIC SRAM Interface Control
8000 PTR TST
4000 LOLATRX
bits [5:3] = EBCS, Expansion Bus Clock Source
0000 CLK pin, PCI clock (external clock not required)
0008 XTAL1 and XTAL2 pins, 20 MHz clock (external clock not required)
0010 EBCLK pin, Expansion Bus Clock (external clock not required)
bits [2:0] = CLK_FAC, Expansion Bus Clock Factor
0000 1/1 clock factor
0001 1/2 clock factor
0002 --
0003 --
EPADDRL Expansion Port Address Lower
29 EPADDRU Expansion Port Address Upper
8000 FLASH 0800 -- 0080 -- 0008 EPADDRU3
4000 AINC 0400 -- 0040 -- 0004 EPADDRU2
2000 -- 0200 -- 0020 -- 0002 EPADDRU1
1000 -- 0100 -- 0010 -- 0001 EPADDRU0
30 EBDATA Expansion Bus Data Port
31 STVAL Software Timer Interrupt Value (DEFAULT = FFFF)
32 MIICAS MII Status and Control (DEFAULT = 0400)
8000 ANTST 0800 APEP 0080 DANAS 0008 XPHYSP
4000 MIIPD 0400 APDW2 0040 XPHYRST 0004 MIIµL
2000 FMDC1 0200 APDW1 0020 XPHYANE 0002 MIILP
1000 FMD0 0100 APDW0 0010 XPHYFD 0001 FCON
33 MIIADDR MII Address

bits [9:5] = PHYAD, Physical Layer Device Address
bits [4:0] = REGAD, MII/Auto-Negotiation Register Address
34 MIIMDR MII Data Port
Am79C971 199
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES
Storage Temperature ........................ –65°C to +150°C Commercial (C) Devices
Ambient Temperature .......................... -65°C to +70°C Temperature (TA) ................................... 0°C to +70°C
Supply voltage with Supply Voltages (AVDD, VDD_PLL, VDD) ..........+5 V ±5%
respect to AVSS, VSSB, VSSM, VSS_PLL, VSS (AVDD, VDDB,
(VDDB for 5-V Signaling) ...........................+5 V ±5%
VDDM, VDD_PLL, VDD ............................. –0.3 V to +6.0 V
(VDD_PCI for 3.3-V Signaling) ..............+ 3.3 V ±10%
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Function- All inputs within the range:
ality at or above these limits is not implied. Exposure to AVSS - 0.5 V _ VIN _ AVDD + 0.5 V,
Absolute Maximum Ratings for extended periods may
affect device reliability. or VSSB - 0.5 V _ VIN _ VDD_PCI + 0.5 V,
or VSS_PLL - 0.5 V _ VIN _ VDD_PLL + 0.5V,
or VSS - 0.5 V _ VIN _ VDD + 0.5 V,
or VSSB - 0.5 < VIN < VDDB + 0.5V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES unless otherwise

specified
Parameter
Symbol Parameter Description Test Conditions Min Max Units
Digital Input Voltage for 5-V Signaling
VIL Input LOW Voltage 0.8 V
VIH Input HIGH Voltage 2.0 V
Digital Output Voltage for 5-V Signaling
IOL1 = 3 mA
IOL2 = 6 mA
VOL Output LOW Voltage 0.45 V
IOL3 = 12 mA
(Note 1)
IOH 1= -2 mA
VOH Output HIGH Voltage (Note 2) IOH 2= -4 mA 2.4 V
(Note 3)
Digital Input Leakage Current for 5-V Signaling
Input Low Leakage Current VIN = 0 V, VDD = VDDB = VDD_PCI =
IIX -10 10 µA
(Note 4) 5V
Digital Output Leakage Current for 5-V Signaling
Output Low Leakage Current
IOZL VOUT = 0.4V -10 µA
(Note 5)
Digital Input Voltage for 3.3-V Signaling
0.325
VIL Input LOW Voltage -0.5
VDDB
VDDB +
VIH Input HIGH Voltage 0.475 VDDB
0.5
Digital Output Voltage for 3.3-V Signaling
0.1
VOL Output LOW Voltage IOL = 1.5 mA
VDDB
VOH Output HIGH Voltage (Note 2) IOH = -0.5 mA 0.9 VDDB
200 Am79C971
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS
OTHERWISE SPECIFIED (CONTINUED)
Parameter
Digital Input Leakage Current for 3.3-V Signaling
Input Low Leakage Current
IIX VIN = 0 V, VDD = VDD_PCI = 3.3 V -10 10 µA
(Note 4)
Digital Output Leakage Current for 3.3-V Signaling
Output Low Leakage Current
IOZL VOUT = 0.4V -10 µA
(Note 5)
Output High Leakage Current
IOZH VOUT = VDD, VDD_PCI 10 µA
(Note 5)
Crystal Input Current
XTAL1 Input LOW Voltage
VILX VIN = External Clock -0.5 0.8 V
Threshold
XTAL1 Input HIGH Voltage
VIHX VIN = External Clock VDD - 0.8 VDD + 0.5 V
Threshold
IILX XTAL1 Input LOW Current VIN = External Clock Active -120 0 µA
VIN = VSS Sleep -10 +10 µA
IIHX XTAL1 Input HIGH Current VIN = External Clock Active 0 120 µA
VIN = VDD Sleep 400 µA
Power Supply Current
XTAL1 = 20 MHz, CLK = 33 MHz,
IDD Active Power Supply Current MDC = 2.5 MHz, 190 mA
TX_CLK=RX_CLK=25 MHz
IDDCOMA Sleep Mode Power Supply Current SLEEP active 700 µA
Auto Wake Mode Power Supply
IDDSNOOZE Awake bit set active 20 mA
Current
Magic Packet Mode Power
IDDmagic0 CLK = 0 MHz (Note 11) 55 mA
Supply Current
Magic Packet Mode Power
IDDmagic33 CLK = 33 MHz (Note 11) 125 mA
Supply Current
Pin Capacitance
CIN Input Pin Capacitance FC = 1 MHz (Note 6, 10) 10 pF
CO I/O or Output Pin Capacitance FC = 1 MHz (Note 6) 10 pF
CCLK CLK Pin Capacitance FC = 1 MHz (Note 6) 5 12 pF
Twisted Pair Interface (10BASE-T)
IIRXD Input Current at RXD± AVDD< VIN < AVDD -500 500 µA
RRXD RXD± differential input resistance 10 kΩ
RXD±, RXD- open circuit input AVDD -
VTIVB IIN = 0 mA AVDD - 1.5 V
voltage (Bias) 3.0
Differential Mode input voltage range
VTIDV AVDD = 5.0 V -3.1 3.1 V
(RXD±)
Sinusoid 5 MHz ≤ f ≤ 10
RXD positive squelch threshold MHz
VTSQ+ 300 520 mV
(peak)
LRT = 0 (CSR15, bit 9)
RXD negative squelch threshold MHz
VTSQ- -520 -300 mV
(peak)
RXD post-squelch positive threshold MHz
VTHS+ 150 293 mV
(peak)
Am79C971 201
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS
OTHERWISE SPECIFIED (CONTINUED)
Parameter
Twisted Pair Interface (10BASE-T) (Cont’d)
RXD post-squelch negative Sinusoid 5 MHz ≤ f ≤ 10 MHz
VTHS- -293 -150 mV
threshold (peak) LRT = 0 (CSR15, bit 9)
RXD positive squelch threshold Sinusoid 5 MHz ≤ f ≤ 10 MHz
VLTSQ+ 180 312 mV
(peak) LRT = 1 (CSR15, bit 9)
RXD negative squelch threshold Sinusoid 5 MHz ≤ f ≤ 10 MHz
VLTSQ- -312 -180 mV
RXD post-squelch positive threshold Sinusoid 5 MHz ≤ f ≤ 10 MHz
VLTHS+ 90 176 mV
RXD post-squelch negative Sinusoid 5 MHz ≤ f ≤10 MHz
VLTHS- -176 -90 mV
threshold (peak) LRT = 1 (CSR15, bit 9)
VRXDTH RXD switching threshold (Note 4) -35 35 mV
TXD± and TXP± output HIGH
VTXH VSS= 0 V VDD - 0.6 VDD V
voltage
TXD± and TXP± output LOW
VTXL VDD= 5 V VSS VSS + 0.6 V
voltage
TXD± and TXP± differential output
VTXI -40 40 mV
voltage imbalance
VTXOFF TXD± and TXP± idle output voltage 40 mV
TXD±, TXP± differential driver
RTX (Note 4) 80 _
output impedance
Attachment Unit Interface (AUI)
Input Current at
IIAXD -1V < VIN < AVDD + 0.5 V -500 +500 µA
DI+ and DI-
Input current at
IIAXC -1V < VIN < AVDD + 0.5 V -500 +500 µA
CI+ and CI-
Differential Output Voltage |(DO+)-
VAOD RL = 78 Ω 630 1200 mV
(DO-)|
Transmit Differential Output Idle RL = 78 Ω
VAODOFF -40 40 mV
Voltage (Note 9)
Transmit Differential Output Idle
IAODOFF RL = 78 Ω (Note 8) -1 1 mA
Current
Transmit Output Common Mode
VCMT RL = 78 Ω 2.5 AVDD V
Voltage
DO± Transmit Differential Output RL = 78 Ω
VODI 25 mV
Voltage Imbalance (Note 7)
Receive Data Differential Input
VATH -35 35 mV
Threshold
DI± and CI± Differential Input
VASQ -275 -160 mV
Threshold (Squelch)
Notes:
2. OL1 applies to AD[31:00], C/BE[3:0], PAR and REQ
OL2 applies to DEVSEL, FRAME, INTA, IRDY, PERR, SERR, STOP, TRDY, EECS, EEDI, EBUA_EBA[7:0], EBDA[15:8],
EBD[7:0], EROMCS, ERAMCS, AS_EBOE, EBWE, TXD[3:0], TX_EN, TX_ER, MDC, MDIO and TDO.
IOL3 applies to EESK/LED1/SFBD, LED2/SRDCLK,
EEDO/LED3/SRD, and EEDI/LED0.
202 Am79C971
3. VOH does not apply to open-drain output pins.
4. OH1 applies to all other outputs.
IOH2 applies to TXD[3:0], TX_EN,TX_ER,MDC, and MDIO
Outputs are CMOS and will be driven to rail if the load is not resistive.
5. IL and IIH apply to all input pins except XTAL1.
6. OZL and IOZH apply to all three-state output pins and bidirectional pins.
7. Parameter not tested. Value determined by characterization.
8. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.
9. Correlated to other tested parameters - not tested directly.
10. Test not implemented to data sheet specification.
11. CIN = 8 pF for the IDSEL input and all input pins on the MII interface (TX_CLK, COL, CRS, RX_CLK, RXD[3:0], RX_DV,
RX_ER).
12. The power supply current in Magic Packet mode is linear with respect to the PCI Clock frequency operation, assuming the
network port remains constant. For example, at CLK = 20 MHz, the maximum Magic Packet power supply current would be
87 mA.
SWITCHING CHARACTERISTICS: BUS INTERFACE
Parameter
Symbol Parameter Name Test Condition Min Max Unit
Clock Timing - PCI Bus Interface
FCLK CLK Frequency 0 33 MHz
@ 1.5 V for VDDB = 5 V
tCYC CLK Period 30 _ ns
@ 0.4 VDD_PCI V for VDD_PCI = 3.3 V
tHIGH CLK High Time @ 0.475 VDD_PCI V for VDD_PCI = 3.3 12 ns
V
tLOW CLK Low Time @ 0.325 VDD_PCI V for VDD_PCI = 3.3 12 ns
V
over 2 V p-p for VDDB = 5 V
over 0.4 VDD_PCI p-p for VDD_PCI =
tFALL CLK Fall Time 1 4 V/ns
3.3 V
(Note 1)
over 2 V p-p for VDDB = 5 V
over 0.4 VDD_PCI p-p for VDD_PCI =
tRISE CLK Rise Time 1 4 V/ns
3.3 V
(Note 1)
Output and Float Delay Timing - PCI Bus Interface
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, DEVSEL,
tVAL 2 11 ns
PERR, SERR
Valid Delay
tVAL (REQ) REQ Valid Delay 2 12 ns
AD[31:00], C/BE[3:0], PAR, FRAME,
tON IRDY, TRDY, STOP, DEVSEL Active 2 ns
Delay
AD[31:00], C/BE[3:0], PAR, FRAME,
tOFF IRDY, TRDY, STOP, DEVSEL Float 28 ns
Delay
Am79C971 203
SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED)
Parameter
Setup and Hold Timing
AD[31:00], C/BE[3:0], PAR, FRAME,
tSU IRDY, TRDY, STOP, DEVSEL, 7 ns
IDSEL Setup Time
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, DEVSEL,
tH 0 ns
IDSEL
Hold Time
tSU (GNT) GNT Setup Time 10 ns
tH (GNT) GNT Hold Time 0 ns
EEPROM Timing
fEESK EESK Frequency (Note 2) 650 kHz
tHIGH (EESK) EESK High Time 780 ns
tLOW (EESK) EESK Low Time 780 ns
tVAL (EEDI) EEDI Valid Output Delay from EESK (Note 2) -15 15 ns
EECS Valid Output Delay from
tVAL (EECS) (Note 2) -15 15 ns
EESK
tLOW (EECS) EECS Low Time 1550 ns
tSU (EEDO) EEDO Setup Time to EESK (Note 2) 50 ns
tH (EEDO) EEDO Hold Time from EESK (Note 2) 0 ns
JTAG (IEEE 1149.1) Test Signal Timing
tJ1 TCK Frequency 10 MHz
tJ2 TCK Period 100 ns
tJ3 TCK High Time @ 2.0 V 45 ns
tJ4 TCK Low Time @ 0.8 V 45 ns
tJ5 TCK Rise Time 4 ns
tJ6 TCK Fall Time 4 ns
tJ7 TDI, TMS Setup Time 8 ns
tJ8 TDI, TMS Hold Time 10 ns
tJ9 TDO Valid Delay 3 30 ns
tJ10 TDO Float Delay 50 ns
tJ11 All Outputs (Non-Test) Valid Delay 3 25 ns
tJ12 All Outputs (Non-Test) Float Delay 36 ns
tJ13 All Inputs (Non-Test)) Setup Time 8 ns
tJ14 All Inputs (Non-Test) Hold Time 7 ns
Notes:
1. Not tested; parameter guaranteed by design characterization.
2. Parameter value is given for automatic EEPROM read operation. When EEPROM port (BCR19) is used to access the
EEPROM, software is responsible for meeting EEPROM timing requirements.
204 Am79C971
SWITCHING CHARACTERISTICS: BUS INTERFACE (CONCLUDED)
Parameter Parameter Name Test Condition Min Max Unit

Symbol
Expansion Bus Interface Timing
FCLK EBCLK Frequency 2.5 33 MHz
tCYC EBCLK Period @ 1.5 V 30 400 ns
tHIGH EBCLK High Time @ 2.0 V 12 ns
tLOW EBCLK Low Time @ 0.8 V 12 ns
tFALL EBCLK Fall Time over 2 V p-p 1 4 V/ns
tRISE EBCLK Rise Time over 2 V p-p 1 4 V/ns
Address and Data valid time from the
tv_A_D 13 ns
rising edge of EBCLK
ERAMCS assert time from the rising
tCS_L 13 ns
edge of EBCLK
ERAMCS deassert time from rising
tCS_H 7 10 ns
edge of EBCLK
Data setup time to the rising edge of
ts_D 0 ns
EBCLK
Data hold time from the rising edge of
th_D 6 ns
EBCLK
AS_EBOE (Address Strobe) rising
t_AS_H 10 13 ns
edge from the falling edge of EBCLK
AS_EBOE falling edge from the
t_AS_L 10 13 ns
rising edge of EBCLK
AS_EBOE (Output enable deassert)
t_OE_H rising edge from the rising edge of 7 ns
EBCLK
Data Bus driving from the rising edge
t_LZ 5 ns
of EBCLK
Data Bus tristated from the rising
t_HZ 13 ns
edge of EBCLK
EBWE assert time from the falling
t_WE_L 6 ns
edge of EBCLK
EBWE deassert time from the rising
t_WE_H 10 ns
edge of EBCLK
EBWE setup time to Address,
t_WE_CSAD 1 ns
ERAMCS, and Data
Note:
Address is the EBUA_EBA[7:0] bus. Data is the EBDA[15:8] and the EBD[7:0] buses.
Am79C971 205
SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE
Parameter
Transmit Timing
tTETD Transmit Start of Idle 250 350 ns
tTR Transmitter Rise Time (10% to 90%) 5.5 ns
tTF Transmitter Fall Time (90% to 10%) 5.5 ns
Transmitter rise and fall time
tTM tTM = | tTR - tTF | 1 ns
mismatch
tXMTON XMT asserted delay 100 ns
tXMTOFF XMT deasserted delay 20 62 ms
tPERLP Idle Signal Period 8 24 ms
tPWLP Idle Link Pulse Width (See note below) 75 120 ns
tPWPLP Predistortion Idle Link Pulse Width (See note below) 45 55 ns
tJA Transmit jabber activation time 20 150 ms
tJR Transmit jabber reset time 250 750 ms
Transmit jabber recovery time
(minimum time gap between
tJREC 1.0 µs
transmitted frames to prevent jabber
activation)
Receiving Timing
RXD pulse width not to turn off
tPWNRD VIN > VTHS(min) 136 ns
internal carrier sense
tPWROFF RXD pulse width to turn off VIN > VTHS(min) 200 ns
tRETD Receive Start of Idle 200 ns
TRON +
tRCVON RCV asserted delay TRON - 50 ns
100
tRCVOFF RCV deasserted delay 20 62 ms
Collision Detection and SQE Test
tCOLON COL asserted delay 750 900 ns
tCOLOFF COL deasserted delay 20 62 ms
Note:
Not tested, parameter guaranteed by characterization.
206 Am79C971
SWITCHING CHARACTERISTICS: ATTACHMENT UNIT INTERFACE
Parameter
AUI Port
tDOTR DO+, DO- Rise Time (10% to 90%)

2.5 5.0 ns
tDOTF DO+, DO- Fall Time (10% to 90%)

2.5 5.0 ns
DO+, DO- Rise and Fall Time
tDORM
Mismatch 1.0 ns
tDOETD DO± End of Transmission 200 375 ns
DI Pulse Width Accept/Reject |VIN| > |VASQ|
tPWODI
Threshold (Note 1) 15 45 ns
DI Pulse Width Maintain/Turn-Off |VIN| > |VASQ|
tPWKDI
CI Pulse Width Accept/Reject |VIN| > |VASQ|
tPWOCI
CI Pulse Width Maintain/Turn-Off |VIN| > |VASQ|
tPWKCI
Internal MENDEC Clock Timing
tX1 XTAL1 Period VIN = External Clock 49.995 50.001 ns
tX1H XTAL1 HIGH Pulse Width VIN = External Clock 20 ns
tX1L XTAL1 LOW Pulse Width VIN = External Clock 20 ns
tX1R XTAL1 Rise Time VIN = External Clock 5 ns
tX1F XTAL1 Fall Time VIN = External Clock 5 ns
Notes:
1. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.
2. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier sense on; pulses wider than tPWKDI (max) will turn
internal DI carrier sense off.
3. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.
4. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier sense on; pulses wider than tPWKCI (max) will turn inter-
nal CI carrier sense off.
Am79C971 207
SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE
Parameter
Transmit Timing
measured from Vilmax = 0.8 V or
TX_EN, TX_ER, TXD valid from
tTVAL measured from Vihmin = 2.0V 0 25 ns
↑ TX_CLK
(Note 1)
Receive Timing
RX_DV, RX_ER, RXD setup to
tRSU measured from Vihmin = 2.0V 10 ns
↑ RX_CLK
(Note 1)
RX_DV, RX_ER, RXD hold to
tRH measured from Vihmin = 2.0V 10 ns
↑ RX_CLK
(Note 1)
Management Cycle Timing
tMHIGH MDC Pulse Width HIGH Time CLOAD = 390 pf 160 ns
tMLOW MDC Pulse Width LOW Time CLOAD = 390 pf 160 ns
tMCYC MDC Cycle Period CLOAD = 390 pf 400 ns
CLOAD = 470 pf,
tMSU MDIO setup to ↑ MDC 10 ns
measured from Vihmin = 2.0V
(Note 1)
CLOAD = 470 pf,
tMH MDIO hold to ↑ MDC 10 ns
measured from Vihmin = 2.0V
(Note 1)
CLOAD = 470 pf,
tMCYC -
tMVAL MDIO valid from ↑ MDC tMSU ns
measured from Vihmin = 2.0V,
(Note 1)
Notes:
1. MDIO valid measured at the exposed mechanical Media Independent Interface.
2. TXCLK and RXCLK frequency and timing parameters are defined for the external physical layer transceiver as defined in the
IEEE 802.3u standard. They are not replicated here.
208 Am79C971
SWITCHING CHARACTERISTICS: GENERAL-PURPOSE SERIAL INTERFACE
Parameter
Transmit Timing
tGPT1 TXCLK Period (802.3 compliant) @ 1.5 V 99.99 100.01 ns
tGPT2 TXCLK HIGH Time @ 2.0 V 40 60 ns
TXDAT and TXEN Delay from ↑
tGPT3 @ 1.5 V 0 70 ns
TXCLK
RXEN Setup before ↑ TXCLK (Last
tGPT4 @ 1.5 V 210 ns
Bit)
tGPT5 RXEN Hold after ↓ TXEN @ 1.5 V 0 ns
CLSN Active Time to Trigger
tGPT6 @ 1.5 V (Note 1) 410 ns
Collision
CLSN Active to ↓ RXEN to Prevent
tGPT7 @ 1.5 V 0 ns
LCAR Assertion
CLSN Active to ↓ RXEN for SQE
tGPT8 @ 1.5 V 0 4.0 µs
Heartbeat window
CLSN Active to ↑ RXEN for Normal
tGPT9 @ 1.5 V 0 51.2 µs
Collision
Receive Timing
tGPR1 RXCLK Period @ 1.5 V (Note 2) 80 120 ns
tGPR2 RXCLK HIGH Time @ 2.0 V (Note 2) 30 80 ns
tGPR3 RXCLK LOW Time @ 0.8 V (Note 2) 30 80 ns
RXDAT and RXEN Setup to ↑
tGPR4 @ 1.5 V 15 ns
RXCLK
tGPR5 RXDAT Hold after ↑ RXCLK @ 1.5 V 15 ns
tGPR6 RXEN Hold after ↓ RXCLK @ 1.5 V 0 ns
CLSN Active to First ↑ RXCLK
tGPR7 @ 1.5 V 0 ns
(Collision Recognition)
CLSN Active to ↑ RXCLK for
tGPR8 @ 1.5 V (Note 3) 51.2 µs
Address Type Designation Bit
CLSN Setup to Last ↑ RXCLK for
tGPR9 @ 1.5 V 210 ns
Collision Recognition
tGPR10 CLSN Active @ 1.5 V 410 ns
CLSN Inactive Setup to First ↑
tGPR11 @ 1.5 V 300 ns
RXCLK
tGPR12 CLSN Inactive Hold to Last ↑ RXCLK @ 1.5 V 300 ns
Notes:
1. CLSN must be asserted for a continuous period of 110 ns or more. Assertion for less than 110 ns period may or may not result
in CLSN recognition.
2. RXCLK should meet jitter requirements of IEEE 802.3 specification.
3. CLSN assertion before 51.2 µs will be indicated as a normal collision. CLSN assertion after 51.2 µs will be considered as a
Late Receive Collision.
Am79C971 209
SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE
Parameter
External Address Detection Interface: Internal PHY
tEAD1 SRD setup to ↑ SRDCLK 40 ns
tEAD2 SRD hold to ↑ SRDCLK 40 ns
tEAD3 SFBD# change to ↓ SRDCLK -15 +15 ns
EAR deassertion to ↑ SRDCLK (first
tEAD4 50 ns
rising edge)
EAR assertion after SFD event
tEAD5 0 51,090 ns
(frame rejection)
tEAD6 EAR assertion width 110 ns
External Address Detection Interface: External PHY - MII @ 25 MHz
tEAD7 SFBD change from ↓ RX_CLK 0 20 (Note 1) ns
EAR deassertion to ↑ RX_CLK (first
tEAD8 40 ns
rising edge)
tEAD9 0 5,080 ns
(frame rejection)
External Address Detection Interface: External PHY - MII @ 2.5 MHz
EAR deassertion to ↑ RX_CLK (first
tEAD11 400 ns
rising edge)
tEAD12 0 50,800 ns
(frame rejection)
Receive Frame Tag Timing with Media Independent Interface
RXFRTGE assertion from ↑SFBD
tEAD14 0 ns
(first rising edge)
RXFRTGE, RXFRTGD setup to ↑
tEAD15 10 ns
RX_CLK
RXFRTGE, RXFRTGD hold to ↑
tEAD16 10 ns
RX_CLK
RX_CLK @25 MHz 40 ns
tEAD17 RXFRTGE deassertion to ↓ RX_DV
RX_CLK @2.5 MHz 400 ns
Note:
1. May need to delay RX_CLK to capture Start Frame Byte Delimiter (SFBD) at 100 Mbps operation.
210 Am79C971
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
Must be Will be
Steady Steady
May Will be
Change Changing
from H to L from H to L
May Will be
Change Changing
from L to H from L to H
DonÕt Care, Changing,

Any Change State
Permitted Unknown
Does Not Center

Apply Line is High-
Impedance
ÒOffÓState
SWITCHING TEST CIRCUITS
IOL
Sense Point VTHRESHOLD
CL
IOH
20550D-61
Figure 58. Normal and Tri-State Outputs
Am79C971 211
SWITCHING TEST CIRCUITS (CONTINUED)
AVDD
52.3 Ω
DO+
Test Point
DO–
100 pF 154 Ω
AVSS
20550D-62
Figure 59. AUI DO Switching Test Circuit
DVDD
294 Ω
TXD+
Test Point
TXD–
100 pF 294 Ω
Includes Test
Jig Capacitance
DVSS
20550D-63
Figure 60. TXD Switching Test Circuit
DVDD
715 Ω
TXP+
Test Point
TXP–
100 pF 715 Ω
Includes Test
Jig Capacitance
DVSS
20550D-64
Figure 61. TXP Outputs Test Circuit
212 Am79C971
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE
tHIGH
2.4 V
2.0 V 2.0 V
tLOW
CLK 1.5 V 1.5 V
0.8 V 0.8 V
0.4V
tRISE tFALL
tCYC
20550D-65
Figure 62. CLK Waveform for 5 V Signaling
tHIGH
0.6 VDD_PCI
0.5 VDD_PCI 0.5 VDD_PCI

tLOW
CLK 0.4 VDD_PCI 0.4 VDD_PCI
0.3 VDD_PCI 0.3 VDD_PCI
0.2 VDD_PCI
tRISE tFALL
tCYC
20550D-66
Figure 63. CLK Waveform for 3.3 V Signaling
Tx Tx
CLK
tSU tH
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP,
DEVSEL, IDSEL
tSU(GNT) tH(GNT)
GNT
20550D-67
Figure 64. Input Setup and Hold Timing
Am79C971 213
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (CONTINUED)
Tx Tx Tx
CLK
tVAL
MIN MAX
AD[31:00] C/BE[3:0],
PAR, FRAME, IRDY, Valid n Valid n+1
TRDY, STOP, DEVSEL,
PERR, SERR tVAL(REQ)
MIN MAX
REQ
Valid n Valid n+1
20550D-68
Figure 65. Output Valid Delay Timing
Tx Tx Tx
CLK
tON
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY, Valid n
TRDY, STOP,
DEVSEL, PERR
tOFF
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY, Valid n
TRDY, STOP,
DEVSEL, PERR
20550D-69
Figure 66. Output Tri-state Delay Timing
EESK
EECS
EEDI 0 1 1 0 A5 A4 A3 A2 A1 A0
EEDO D15 D14 D13 D2 D1 D0
20550D-70
Figure 67. EEPROM Read Functional Timing
214 Am79C971
tHIGH (EESK) tLOW (EESK)

tSU (EEDO)
EESK
tH (EEDO)
tVAL (EEDI,EECS)
EEDO Stable
tLOW (EECS)
EECS
EEDI
20550D-71
Figure 68. Automatic PREAD EEPROM Timing
tJ3
0.8 V
2.0 V 2.0 V
tJ4
TCK 1.5 V 1.5 V
0.8 V
tJ5 tJ6
tJ2
20550D-72
Figure 69. JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling
Am79C971 215
tJ2
TCK
tJ7 tJ8
TDI, TMS
tJ9
TDO
tJ11 tJ12
Output
Signals
tJ13 tJ14
Input
Signals
20550D-73
Figure 70. JTAG (IEEE 1149.1) Test Signal Timing
216 Am79C971
SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE
tHIGH
2.4 V
2.0 V 2.0 V
tLOW
EBCLK 1.5 V 1.5 V
0.8 V 0.8 V
0.4V
tRISE tFALL
tCYC
20550D-74
Figure 71. EBCLK Waveform
EBCLK

tv_A_D ts_D t_LZ
t_HZ
EBDA[15:8], EBD[7:0] Data Data
th_D
ERAMCS t_CS_H
t_CS_L
EBWE t_AS_H
AS_EBOE
t_AS_L
20550D-75
Figure 72. Expansion Bus SRAM Read Timing--Normal SRAM Operation
Am79C971 217
SWITICHING WAVEFORMS: EXPANSION BUS INTERFACE (CONTINUED)
EBCLK

tv_A_D
EBDA[15:8], EBD[7:0]
DATA DATA
ERAMCS t_CS_H
t_CS_L
t_WE_CSAD
EBWE
t_WE_L t_WE_H
t_AS_H
AS_EBOE
t_AS_L
20550D-76
Figure 73. Expansion Bus SRAM Write Timing--Normal SRAM Operation
218 Am79C971
SWITCHING WAVEFORMS: 10BASE-T INTERFACE
TTR TTF
TXD+ TTET
TXP+
TXD-
TXP
TXMTON TXMTOF
XMT
20550D-77
Figure 74. Transmit Timing
TPWPLP
TXD+
TXP+
TXD-
TXP-
TPWLP
TPERL
20550D-78
Figure 75. Idle Link Test Pulse
Am79C971 219
SWITCHING WAVEFORMS: 10BASE-T INTERFACE (CONTINUED)
VTSQ+
VTHS+
RXD±
VTHS-
VTSQ-
20550D-79
Figure 76. Receive Thresholds (LRT = 0)
VLTSQ+
VLTHS+
RXD±
VLTHS-
VLTSQ-
20550D-80
Figure 77. Receive Thresholds (LRT = 1)
220 Am79C971
SWITCHING WAVEFORMS: ATTACHMENT UNIT INTERFACE
tx1H tx1HL
XTAL1
tx1HF tx1HR
ISTDCLK tx1
(Note 1)
ITXEN
(Note 1)
1 1 1 1
ITXDAT+ 0 0
(Note 1)
tDOTR tDOTF
DO+
DO–
DO± 1
Note 1:
Internal signal and is shown for clarification only.
20550D-81
Figure 78. Transmit Timing - Start of Frame
XTAL1
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1 1
ITXDAT+ 0 0
(Note 1)
DO+
DO–
DO± tDOETD
1 0 0 Typical > 200 ns
Bit (n–2) Bit (n–1) Bit (n)
Note 1:
20550D-82
Figure 79. Transmit Timing - End of Frame (Last Bit = 0)
Am79C971 221
SWITCHING WAVEFORMS: ATTACHMENT UNIT INTERFACE (CONTINUED)
XTAL1
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1 1 1
ITXDAT+ 0
(Note 1)
DO+
DO–
DO± tDOETD
Typical > 250 ns
1 0
Bit (n–2) Bit (n–1) Bit (n)
Note 1:
20550D-83
Figure 80. Transmit Timing - End of Frame (Last Bit = 1)
222 Am79C971
SWITCHING WAVEFORMS: ATTACHMENT UNIT INTERFACE (CONTINUED)
tPWKDI
Dl+/–
VASQ
tPWKDI
tPWODI
20550D-84
Figure 81. Receive Timing
tPWKCI
Cl+/–
VASQ
tPWOCI
tPWKCI
20550D-85
Figure 82. Collision Timing
tDOETD
DO+/– 40 mV 0V
100 mV max.
80 Bit Times
20550D-86
Figure 83. Port DO ETD Waveform
Am79C971 223
SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE
Vihmin
TX_CLK Vilmax
tTVAL
TXD[3:0],
TX_EN, Vihmin
TX_ER Vilmax
20550D-87
Vihmin
RX_CLK Vilmax
tRSU tRH
RXD[3:0],
RX_ER, Vihmin
RX_DV Vilmax
20550D-88
tMHIGH
2.4 V
2.0 V 2.0 V
MDC 1.5 V tMLOW 1.5 V
0.8 V 0.8 V
0.4 V
tMCYC
20550D-89
Figure 86. MDC Waveform
224 Am79C971
SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE (CONTINUED)
Vihmin
MDC Vilmax
tMSU tMH
MDIO Vihmin
Vilmax
20550D-90
Figure 87. Management Data Setup and Hold Timing
Vihmin
MDC Vilmax
tMVAL
Vihmin
MDIO
Vilmax
20550D-91
Figure 88. Management Data Output Valid Delay Timing
Am79C971 225
SWITCHING WAVEFORMS: GENERAL-PURPOSE SERIAL INTERFACE
(First Bit Preamble) (Last Bit)

tGPT1
tGPT2
Transmit
Clock
(TXCLK) tGPT3
Transmit
Data
(TXDAT) tGPT3 tGPT3
Transmit
Enable
(TXEN)
tGPT4
Carrier
Present tGPT5
(RXEN)
(Note 1) tGPT5 tGPT6
Collision
(CLSN) tGPT7 tGPT8
(Note 2)
Notes:
1. If RXCRS is not present during transmission, LCAR bit in TMD2 will be set.
2. If CLSN is not present during or shortly after transmission, CERR in CSR0 will be set.
20550D-92
(First Bit Preamble) (Address Type Designation Bit) (Last Bit)

tGPR1
tGPR2 tGPR3
Receive
Clock
(RXCLK)
tGPR4 tGPR5 tGPR5
Receive
Data
(RXDAT)
tGPR4
Carrier tGPR5
Present tGPR8 tGPR9
(RXEN)
tGPR7 tGPR10
Collision
(CLSN),
Active
tGPR11 tGPR12
Collision
(CLSN), (No Collision)
Inactive
20550D-93
226 Am79C971
SWITCHING WAVEFORMS: EXTERNAL ADDRESS DETECTION INTERFACE
Preamble Data Field
SRDCLK
One Zero One SFD Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 8 Bit 0 Bit 7 Bit 8
SRD
tEAD1
tEAD2
SF/BD
tEAD3 tEAD3
tEAD4 Accept
Reject
EAR tEAD5
tEAD6
20550D-94
Figure 91. Reject Timing
RX_CLK
RXD[3:0] Preamble SFD DA DA DA
tEAD8
RX_DV tEAD9 tEAD10
EAR tEAD7
SF/BD
20550D-95
Figure 92. Reject Timing - External PHY MII @ 25 MHz
RX_CLK
Preamble SFD DA DA DA
RXD[3:0]
tEAD11
RX_DV tEAD12 tEAD13
EAR
SF/BD
20550D-96
Figure 93. Reject Timing - External PHY MII @ 2.5 MHz
Am79C971 227
SWITCHING WAVEFORMS: RECEIVE FRAME TAG
RX_CLK
Preamble SFD DA DA DA
RXD[3:0]
RX_DV
EAR
SF/BD
tEAD14 tEAD17
RXFRTGE
tEAD15
RXFRTGD
tEAD16
20550D-97
Figure 94. Receive Frame Tag Timing with Media Independent Interface
228 Am79C971
PHYSICAL DIMENSIONS*
PQR160
Plastic Quad Flat Pack (measured in millimeters)
31.00
31.40
27.90
28.10
Pin 160 25.35
REF Pin 120
Pin 1 I.D.
25.35
REF
27.90
28.10
31.00
31.40
Pin 40
Pin 80
3.95
3.20
0.65 BASIC MAX
3.60
0.25
Min SEATING PLANE
16-038-PQR-1
PQR160
12-22-95 lv
*For reference only. BSC is an ANSI standard for Basic Space Centering.
Am79C971 229
PQL176
Thin Quad Flat Pack (measured in millimeters)
176
25.80
23.80 26.20
24.20
44
23.80
24.20
25.80
26.20
11ϒ – 13ϒ
1.35
1.60 MAX
1.45
0.50 BSC 11ϒ – 13ϒ

1.00 REF.
16-038-PQT-1_AL
PQL176
5.12.97. lv
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or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifi-
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merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a
situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make
changes to its products at any time without notice.
Trademarks
Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
NetPHY is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
230 Am79C971
APPENDIX A
Am79C971 Compatible Media Interface

Modules
AM79C971 COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS

The table below provides a sample list of Am79C971 manufacturer for a complete updated component list-
compatible 10BASE-T filter and transformer modules ing.
available form various vendors. Contact the respective
Filters
Filters Filters Transformers
Filters and Transformers Transformers Resistors Dual
Manufacturer Part No. Package Transformers and Choke Dual Chokes Chokes
Bel Fuse A556-2006-DE 16-pin 0.3 DIL X
Bel Fuse 0556-2006-00 14-pin SIP X
Bel Fuse 0556-2006-01 14-pin SIP X
Bel Fuse 0556-6392-00 16-pin 0.5 DIL X
Halo Electronics FD02-101G 16-pin 0.3 DIL X
PCA Electronics EPA 1990A 16-pin 0.3 DIL X
PCA Electronics EPA 2013D 16-pin 0.3 DIL X
PCA Electronics EPA 2162 16-pin 0.3 SIP X
Pulse
PE-65421 16-pin 0.3 DIL X
Engineering
Pulse
PE-65434 16-pin 0.3 SIL X
Engineering
Pulse
PE-65445 16-pin 0.3 DIL X
Engineering
Pulse
PE-65467 12-pin 0.5 SMT X
Engineering
Valor Electronics PT3877 16-pin 0.3 DIL X
Valor Electronics PT3877 16-pin 0.3 DIL X
Note: 100BASE-TX and 100BASE-T4 interfaces are unique to the external PHY. Contact the PHY vendor for the appropriate
information.
Am79C971 A-1
Am79C971 Compatible AUI Isolation Transformers
The table below provides a sample list of Am79C971 compatible AUI isolation transformers available from various
vendors. Contact the respective manufacturer for a complete updated component listing.
Manufacturer Part No. Package Description
Bel Fuse A553-0506-AB 16-pin 0.3 DIL 50 mH
Bel Fuse S553-0756-AE 16-pin 0.3 SMD 75 µH
Halo Electronics TD01-0765K 16-pin 0.3 DIL 75 µH
Halo Electronics TG01-0756W 16-pin 0.3 SMD 75 µH
PCA Electronics EP9531-4 16-pin 0.3 DIL 50 µH
Pulse Engineering PE-64106 16-pin 0.3 DIL 50 µH
Pulse Engineering PE-65723 16-pin 0.3 SMT 75 µH
Valor Electronics LT6032 16-pin 0.3 DIL 75 µH
Valor Electronics ST7032 16-pin 0.3 SMD 75 µH
Am79C971 Compatible DC/DC Converters

The table below provides a sample list of Am79C971 compatible DC/DC converters available from various vendors.
Contact the respective manufacturer for a complete updated component listing.
Manufacturer Part No. Package Voltage Remote On/Off
Halo Electronics DCUO-0509D 24-pin DIP 5/-9 No
Halo Electronics DCUO=0509E 24-pin DIP 5/-9 Yes
PCA Electronics EPC1007P 24-pin DIP 5/-9 No
PCA Electronics EPC1054P 24-pin DIP 5/-9 Yes
PCA Electronics EPC1078 24-pin DIP 5/-9 Yes
Valor Electronics PM7202 24-pin DIP 5/-9 No
Valor Electronics PM7222 24-pin DIP 5/-9 Yes
Manufacturer Contact Information

Contact the following companies for further information on their products.
Company U. S. and Domestic Asia Europe
Phone: (201) 432-0463 852-328-5515 33-1-69410402
Bel Fuse
Fax: (201) 432-9542 852-352-3706 33-1-69413320
Phone: (415)969-7313 65-285-1566
Halo Electronics
Fax: (415) 367-7158 65-284-9466
33-1-44894800
PCA Electronics Phone: (818) 892-0761 852-553-0165
33-1-42051579
(HPC in Hong Kong) Fax: (818) 894-5791 852-352-3706
Phone: (619) 674-8100 852-425-1651 353-093-24107

Pulse Engineering
Fax: (619) 675-8262 852-480-5974 353-093-24459
Phone: (619) 537-2500 852-513-8210 49-89-69233122
Valor Electronics
Fax: (619) 537-2525 852-513-8214 49-89-6926542
A-2 Am79C971 device, compatible with:10Base-T Filters and Transformers

APPENDIX B
Recommendation for Power and Ground

Decoupling
The mixed analog/digital circuitry in the Am79C971 de- The bulk capacitor(s) should be connected directly to
vice makes it imperative to provide noise-free power the power and ground planes. In addition, at least
and ground connections to the device. Without clean eight high frequency decoupling capacitors (e.g.,
power and ground connections, a design may suffer 0.1 µF multilayer ceramic capacitors of dielectric type
from high bit error rates or may not function at all. XDR) should be used around the periphery of the
Hence, it is highly recommended that the guidelines PCnet-PCI II device to prevent power and ground
presented here are followed to ensure a reliable de- bounce from affecting device operation. To reduce the
sign. inductance between the power and ground pins and
the capacitor, the pins should be connected directly to
Decoupling/Bypass Capacitors the capacitors, rather than through the planes to the ca-
Adequate decoupling of the power and ground pins and pacitors. The suggested connection scheme for the ca-
planes is required by all Am79C971 designs. This in- pacitors is shown in the figure below. Note also that the
cludes both low-frequency bulk capacitors and high fre- traces connecting these pins to the capacitors should
quency capacitors. It is recommended that at least be as wide as possible to reduce inductance (15 mils is
one low-frequency bulk (e.g., 22 µF) decoupling ca- desirable).
pacitor be used in the area of the Am79C971 device.
C C
A Am79C971 A Am79C971
P P
Best OK
C
A Am79C971
P
Not Recommended
19364D-1
Figure 1. Connection Scheme for Capacitors
Am79C971 B-1
The most critical pins in the layout of a Am79C971 de- A dedicated 0.1 µF capacitor between these pins is
sign are the four analog power and two analog ground recommended.
pins, VDD_PLL, AVDD, VSS_PLL and AVSS respec-
VSS_PLL and VDD_PLL
tively. All of these pins are located in one corner of the
device, the “analog corner.” Specific functions and lay- These pins are the most critical pins on the
out requirements of the analog power and ground pins Am79C971 device because they provide the power
are given below. and ground for the phase-lock loop (PLL) portion of the
chip. The voltage-controlled oscillator (VCO) portion of
AVSS and AVDD the PLL is sensitive to noise in the 60 kHz - 200 kHz.
These pins provide the power and ground for the range. To prevent noise in this frequency range from
Twisted Pair and AUI drivers. In addition AVSS serves disrupting the VCO, it is strongly recommended that
as the ground for the logic interfaces in the 20 MHz the low-pass filter shown below be implemented on
Crystal Oscillator. Hence, these pins can be very noisy. these pins when internal ports are used.This filter is not
needed when MII is used solely.
VDD Plane
33 µF to 10 µF
VDD_PLL
(Pin 129)
0.1 µF
1 ΩΩ
2.7 to το Ω Ω
10 10
Am79C971
VSS_PLL
(Pin 119)
VSS Plane
19364D-2
Figure 2. Power and Ground Pin Connections
To determine the value for the resistor and capacitor, cept for the filter circuit already mentioned, no specific
the formula is: decoupling is necessary on these pins.
R * C ≥ 88 AVDD
where R is in Ohms and C is in microfarads. Some pos- AVDD provides power for the control and interface logic
sible combinations are given below. To minimize the in the PLL. Ground for this logic is provided by digital
voltage drop across the resistor, the R value should not ground pins. No specific decoupling is necessary on
be more than 10 Ω. this pin.
Note: The capacitor used should be tantalum not alu- Special Note for Adapter Cards: In adapter card de-
minum electrolytic.5.0 signs, it is important to utilize all available power
and ground pins available on the bus edge connec-
tor. In addition, the connection from the bus edge con-
R C nector to the power or ground plane should be made
2.7 Ω 33 µF through more than one via and with wide traces (15
4.3 Ω 22 µF mils desirable) wherever possible. Following these rec-
6.8 Ω 15 µF ommendations results in minimal inductance in the
power and ground paths. By minimizing this induc-
10 Ω 10 µF
tance, ground bounce is minimized.
VSS_PLL and VDD_PLL/AVDD
See also the PCnet™ Family Board Design and Layout
These pins provide power and ground for the AUI and Recommendations applications note (PID# 19595) for
twisted pair receive circuitry. In addition, as mentioned additional information.
earlier, VSS_PLL and VDD_PLL provide power and
ground for the phase-lock loop portion of the chip. Ex-
B-2 Am79C971
APPENDIX C
Alternative Method for Initialization*
The Am79C971 controller may be initialized by per- in the table below. These register writes are followed by
forming I/O writes only. That is, data can be written di- writing the START bit in CSR0.
rectly to the appropriate control and status registers
(CSR instead of reading from the initialization block in
memory). The registers that must be written are shown
Control and Status Register Comment

CSR2 IADR[31:16]**
CSR8 LADRF[15:0]
CSR9 LADRF[31:16]
CSR10 LADRF[47:32]
CSR11 LADRF[63:48]
CSR12 PADR[15:0]
CSR13 PADR[31:16]
CSR14 PADR[47:32]
CSR15 Mode
CSR24-25 BADR
CSR30-31 BADX
CSR47 TXPOLLINT
CSR49 RXPOLLINT
CSR76 RCVRL
CSR78 XMTRL
Notes:
*The INIT bit must not be set or the initialization block will be accessed instead.
**Needed only if SSIZE32 =0.
Am79C971 C-1
C-2 Am79C971
APPENDIX D
Look-Ahead Packet Processing (LAPP)

Concept
INTRODUCTION transmission of the next frame can be performed before

the reception of the frame actually ends at the network,
A driver for the Am79C971 controller would normally re-
and how can the CPU be instructed to perform these
quire that the CPU copy receive frame data from the
tasks during the network reception time.
controllers buffer space to the applications buffer space
after the entire frame has been received by the control- The answer depends upon exactly what is happening
ler. For applications that use a ping-pong windowing in the driver and application code, but the steps that
style, the traffic on the network will be halted until the can be performed at the same time as the receive
current frame has been completely processed by the en- data are arriving include as much as the first three
tire application stack. This means that the time between steps and part of the fourth step shown in the se-
last byte of a receive frame arriving at the client’s Ether- quence above. By performing these steps before the
net controller and the client’s transmission of the first entire frame has arrived, the frame throughput can be
byte of the next outgoing frame will be separated by: substantially increased.
1. The time that it takes the client’s CPU’s interrupt A good increase in performance can be expected when
procedure to pass software control from the current the first three steps are performed before the end of the
task to the driver, network receive operation. A much more significant
2. Plus the time that it takes the client driver to pass perfor mance increase could be realized if the
the header data to the application and request an Am79C971 controller could place the frame data di-
application buffer, rectly into the application’s buffer space; (i.e., eliminate
the need for step 4.) In order to make this work, it is
3. Plus the time that it takes the application to gener- necessary that the application buffer pointer be deter-
ate the buffer pointer and then return the buffer mined before the frame has completely arrived, then
pointer to the driver, the buffer pointer in the next descriptor for the receive
4. Plus the time that it takes the client driver to transfer frame would need to be modified in order to direct the
all of the frame data from the controller’s buffer space Am79C971 controller to write directly to the application
into the application’s buffer space and then call the buffer. More details on this operation will be given later.
application again to process the complete frame,
An alternative modification to the existing system can
5. Plus the time that it takes the application to pro- gain a smaller but still significant improvement in per-
cess the frame and generate the next outgoing formance. This alternative leaves step 4 unchanged in
frame, and that the CPU is still required to perform the copy oper-
6. Plus the time that it takes the client driver to set up ation, but is allows a large portion of the copy operation
the descriptor for the controller and then write a to be done before the frame has been completely re-
TDMD bit to CSR0. ceived by the controller, i.e., the CPU can perform the
copy operation of the receive data from the Am79C971
The sum of these times can often be about the same controller’s buffer space into the application buffer
as the time taken to actually transmit the frames on the space before the frame data has completely arrived
wire, thereby, yielding a network utilization rate of less from the network. This allows the copy operation of
than 50 percent. step 4 to be performed concurrently with the arrival of
An important thing to note is that the Am79C971 control- network data, rather than sequentially, following the
ler’s data transfers to its buffer space are such that the end of network receive activity.
system bus is needed by the Am79C971 controller for
Outline of LAPP Flow
approximately 4 percent of the time. This leaves 96 per-
cent of the system bus bandwidth for the CPU to perform This section gives a suggested outline for a driver that
some of the interframe operations in advance of the utilizes the LAPP feature of the Am79C971 controller.
completion of network receive activity, if possible. The Note: The labels in the following text are used as refer-
question then becomes: how much of the tasks that ences in the timeline diagram that follows (Figure D1).
need to be performed between reception of a frame and
Am79C971 D-1
Setup space that the controller already owns (i.e., buffer num-
The driver should set up descriptors in groups of three, ber 2). The controller does not know if buffer space in
with the OWN and STP bits of each set of three de- buffer number 2 will be sufficient or not for this frame,
scriptors to read as follows: 11b, 10b, 00b. but it has no way to tell except by trying to move the en-
tire message into that space. Only when the message
An option bit (LAPPEN) exists in CSR3, bit position 5; does not fit will it signal a buffer error condition--there is
the software should set this bit. When set, the LAPPEN no need to panic at this point that it discovers that it
bit directs the Am79C971 controller to generate an IN- does not yet own descriptor number 3.
TERRUPT when STP has been written to a receive de-
S2 The first task of the drivers interrupt service
scriptor by the Am79C971 controller.
routing is to collect the header information from
Flow the Am79C971 controller’s first buffer and pass
The Am79C971 controller polls the current receive de- it to the application.
scriptor at some point in time before a message arrives. S3 The application will return an application buffer
The Am79C971 controller determines that this receive pointer to the driver. The driver will add an offset
buffer is OWNed by the Am79C971 controller and it to the application data buffer pointer, since the
stores the descriptor information to be used when a Am79C971 controller will be placing the first
message does arrive. portion of the message into the first and second
N0 Frame preamble appears on the wire, followed buffers. (the modified application data buffer
by SFD and destination address. pointer will only be directly used by the
Am79C971 controller when it reaches the third
N1 The 64th byte of frame data arrives from the buffer.) The driver will place the modified data
wire. This causes the Am79C971 controller to buffer pointer into the final descriptor of the
begin frame data DMA operations to the first group (#3) and will grant ownership of this de-
buffer. scriptor to the Am79C971 controller.
C0 When the 64th byte of the message arrives, the C5 Interleaved with S2, S3, and S4 driver activity,
Am79C971 controller performs a lookahead the Am79C971 controller will write frame data
operation to the next receive descriptor. This to buffer number 2.
descriptor should be owned by the Am79C971
controller. S4 The driver will next proceed to copy the con-
tents of the Am79C971 controller’s first buffer
C1 The Am79C971 controller intermittently re- to the beginning of the application space. This
quests the bus to transfer frame data to the first copy will be to the exact (unmodified) buffer
buffer as it arrives on the wire. pointer that was passed by the application.
S1 The driver remains idle. S5 After copying all of the data from the first buffer
C2 When the Am79C971 controller has completely into the beginning of the application data buffer,
filled the first buffer, it writes status to the first the driver will begin to poll the ownership bit of
descriptor. the second descriptor. The driver is waiting for
the Am79C971 controller to finish filling the sec-
C3 When the first descriptor for the frame has been ond buffer.
written, changing ownership from the
Am79C971 controller to the CPU, the C6 At this point, knowing that it had not previously
Am79C971 controller will generate an SRP IN- owned the third descriptor and knowing that the
TERRUPT. (This interrupt appears as a RINT current message has not ended (there is more
interrupt in CSR0). data in the FIFO), the Am79C971 controller will
make a last ditch lookahead to the final (third)
S1 The SRP INTERRUPT causes the CPU to descriptor. This time the ownership will be
switch tasks to allow the Am79C971 controller’s TRUE (i.e., the descriptor belongs tot he con-
driver to run. troller), because the driver wrote the application
C4 During the CPU interrupt-generated task pointer into this descriptor and then changed
switching, the Am79C971 controller is perform- the ownership to give the descriptor to the
ing a lookahead operation to the third descrip- Am79C971 controller back at S3. Note that if
tor. At this point in time, the third descriptor is steps S1, S2, and S3 have not completed at
owned by the CPU. this time, a BUFF error will result.
Note: Even though the third buffer is not owned by the C7 After filling the second buffer and performing
Am79C971 controller, existing AMD Ethernet control- the last chance lookahead to the next descrip-
lers will continue to perform data DMA into the buffer tor, the Am79C971 controller will write the sta-
D-2 Am79C971
tus and change the ownership bit of descriptor S7 When the driver completes the copy of buffer
number 2. number 2 data to the application buffer space,
it begins polling descriptor number 3.
S6 After the ownership of descriptor number 2 has
been changed by the Am79C971 controller, the C9 When the Am79C971 controller has finished all
next driver poll of the second descriptor will data DMA operations, it writes status and
show ownership granted to the CPU. The driver changes ownership of descriptor number 3.
now copies the data from buffer number 2 into
S8 The driver sees that the ownership of descriptor
the middle section of the application buffer
number 3 has changed, and it calls the appli-
space. This operation is interleaved with the C7
cation to tell the application that a frame has
and C8 operations.
arrived.
C8 The Am79C971 controller will perform data
S9 The application processes the received frame
DMA to the last buffer, whose pointer is pointing
and generates the next TX frame, placing it into
to application space. Data entering the last buff-
a TX buffer.
er will not need the infamous double copy that
is required by existing drivers, since it is being S10 The driver sets up the TX descriptor for the
placed directly into the application buffer space. Am79C971 controller.
N2 The message on the wire ends.
Am79C971 D-3
Ethernet Ethernet Software
Wire Controller activity:
activity: activity:
S10: Driver sets up TX descriptor.
S9: Application processes packet, generates TX packet.

S8: Driver calls application
{
S8A: Interrupt latency.
to tell application that
packet has arrived.
C10: ERP interrupt
is generated. }
C9: Controller writes descriptor #3. S7: Driver is swapped out, allowing a non-Etherenet
application to run.
C8: Controller is performing intermittent S7A: Driver Interrupt Service
N2: EOM
bursts of DMA to fill data buffer #3.
Buffer
{ Routine executes
RETURN.
S6: Driver copies data from buffer #2 to the application buffer.
#3
C7: Controller writes descriptor #2.

S5: Driver polls descriptor #2.
C6: "Last chance" lookahead to
descriptor #3 (OWN).
C5: Controller is performing intermittent
bursts of DMA to fill data buffer #2. S3: Driver writes modified application
Buffer
#2
}{ pointer to descriptor #3.
S2: Driver call to application to
C4: Lookahead to descriptor #3 (OWN). get application buffer pointer.
S1: Interrupt latency.
C3: SRP interrupt
is generated. }
packet data arriving
Buffer S0: Driver is idle.

#1
C0: Lookahead to descriptor #2.
{N1: 64th byte of packet

data arrives.
N0: Packet preamble, SFD

and destination address
are arriving.
19364D-D1
Figure D1. LAPP Timeline
D-4 Am79C971
LAPP Software Requirements needed for the drive to copy data from buffer number 2
to the application buffer space. Note that the time
Software needs to set up a receive ring with descriptors
needed for the copies performed by the driver depends
formed into groups of three. The first descriptor of each
upon the sizes of the second and third buffers, and that
group should have OWN = 1 and STP = 1, the second
the sizes of the second and third buffers need to be set
descriptor of each group should have OWN = 1 and
according to the time needed for the data copy opera-
STP = 0. The third descriptor of each group should
tions. This means that an iterative self-adjusting mech-
have OWN = 0 and STP = 0. The size of the first buffer
anism needs to be placed into the software to
(as indicated in the first descriptor) should be at least
determine the correct buffer sizing for optimal opera-
equal to the largest expected header size; however, for
tion. Fixed values for buffer sizes may be used; in such
maximum efficiency of CPU utilization, the first buffer
a case, the LAPP method will still provide a significant
size should be larger than the header size. It should be
performance increase, but the performance increase
equal to the expected number of message bytes, minus
will not be maximized.
the time needed for interrupt latency and minus the ap-
plication call latency, minus the time needed for the Figure D-2 illustrates this setup for a receive ring size
driver to write to the third descriptor, minus the time of 9.
Descriptor OWN = 1 STP = 1

#1 SIZE = A-(S1+S2+S3+S4+S6)

A = Expected message size in bytes
#2 SIZE = S1+S2+S3+S4
S1 = Interrupt latency
Descriptor OWN = 0 STP = 0 S2 = Application call latency
#3 SIZE = S6 S3 = Time needed for driver to write
to third descriptor
Descriptor OWN = 1 STP = 1 S4 = Time needed for driver to copy
#4 SIZE = A-(S1+S2+S3+S4+S6) data from buffer #1 to
Descriptor OWN = 1 STP = 0 application buffer space
#5 SIZE = S1+S2+S3+S4 S6 = Time needed for driver to copy
data from buffer #2 to
application buffer space
#6 SIZE = S6

SIZE = A-(S1+S2+S3+S4+S6) Note that the times needed for tasks S1,
#7 S2, S3, S4, and S6 should be divided by
Descriptor OWN = 1 STP = 0 0.8 microseconds to yield an equivalent
#8 SIZE = S1+S2+S3+S4 number of network byte times before
OWN = 0 STP = 0 subtracting these quantities from the
Descriptor
SIZE = S6 expected message size A.
#9
19364D-D2
Figure D2. LAPP 3 Buffer Grouping
LAPP Rules for Parsing Descriptors ■ Software must discard all descriptors with OWN = 0
and STP = 0 and move to the next descriptor when
When using the LAPP method, software must use a
searching for the beginning of a new frame; ENP and
modified form of descriptor parsing as follows:
ERR should be ignored by software during this
■ Software will examine OWN and STP to determine search.
where an RCV frame begins. RCV frames will only ■ Software cannot change an STP value in the receive
begin in buffers that have OWN = 0 and STP = 1. descriptor ring after the initial setup of the ring is
■ Software shall assume that a frame continues until complete, even if software has ownership of the STP
it finds either ENP = 1 or ERR = 1.
Am79C971 D-5
descriptor, unless the previous STP descriptor in the for receive purposes by the controller, and the driver
ring is also OWNED by the software. must recognize this. (The driver will recognize this if it
When LAPPEN = 1, then hardware will use a modified follows the software rules.)
form of descriptor parsing as follows: The controller will ignore all descriptors with OWN = 0
■ The controller will examine OWN and STP to deter- and STP = 0 and move to the next descriptor when
mine where to begin placing an RCV frame. A new searching for a place to begin a new frame. In other
RCV frame will only begin in a buffer that has words, the controller is allowed to skip entries in the
OWN = 1 and STP =1. ring that it does not own, but only when it is looking for
a place to begin a new frame.
■ The controller will always obey the OWN bit for de-
termining whether or not it may use the next buffer Some Examples of LAPP Descriptor
for a chain. Interaction
■ The controller will always mark the end of a frame Choose an expected frame size of 1060 bytes. Choose
with either ENP = 1 or ERR = 1. buffer sizes of 800, 200, and 200 bytes.
The controller will discard all descriptors with OWN = 1 ■ Example 1: Assume that a 1060 byte frame arrives
and STP = 0 and move to the next descriptor when correctly, and that the timing of the early interrupt
searching for a place to begin a new frame. It discards and the software is smooth. The descriptors will have
these descriptors by simply changing the ownership bit changed from:
from OWN = 1 to OWN = 0. Such a descriptor is unused
Descriptor Before the Frame Arrives After the Frame Arrives Comments (After
Number OWN STP a OWN STP b Frame Arrival)
ENP ENP
1 1 1 x 0 1 0 Bytes 1-800
2 1 0 X 0 0 0 Bytes 801-1000
3 0 0 X 0 0 1 Bytes 1001-1060
4 1 1 X 1 1 X Controller’s cur-
rent location
5 1 0 X 1 0 X Not yet used
etc. 1 1 X 1 1 X Net yet used
a. & b. ENP or ERR.
■ Example 2: Assume that instead of the expected 1060 there was an error in the network, or because this is
byte frame, a 900 byte frame arrives, either because the last frame in a file transmission sequence
Number OWN STP a OWN STP b Frame Arrival)
ENP ENP
1 1 1 x 0 1 0 Bytes 1-800
2 1 0 X 0 0 0 Bytes 801-1000
3 0 0 X 0 0 ? * Discarded buffer
4 1 1 X 1 1 X Controller’s cur-
rent location
a. & b. ENP or ERR.
Note that the Am79C971 controller might write a ZERO 1. If the controller finishes the data transfers into buffer
to ENP location in the third descriptor. Here are the two number 2 after the driver writes the application mod-
possibilities: ified buffer pointer into the third descriptor, then the
controller will write a ZERO to ENP for this buffer and
will write a ZERO to OWN and STP.
D-6 Am79C971
2. If the controller finishes the data transfers into buffer the last frame in a file transmission sequence, or
number 2 before the driver writes the applications perhaps because it is an acknowledge frame.
modified buffer point into the third descriptor, then *Same as note in example 2 above, except that in this
the controller will complete the frame in buffer num- case, it is very unlikely that the driver can respond to
ber 2 and then skip the then unowned third buffer. In the interrupt and get the pointer from the application
this case, the Am79C971 controller will not have had before the Am79C971 controller has completed its poll
the opportunity to RESET the ENP bit in this descrip- of the next descriptors. This means that for almost all
tor, and it is possible that the software left this bit as occurrences of this case, the Am79C971 controller will
ENP = 1 from the last time through the ring. There- not find the OWN bit set for this descriptor and, there-
fore, the software must treat the location as a don’t fore, the ENP bit will almost always contain the old
care. The rule is, after finding ENP = 1 (or ERR = 1) value, since the Am79C971 controller will not have had
in descriptor number 2, the software must ignore an opportunity to modify it.
ENP bits until it finds the next STP = 1.
**Note that even though the Am79C971 controller will
■ Example 3: Assume that instead of the expected
write a ZERO to this ENP location, the software should
1060 byte frame, a 100 byte frame arrives, because
treat the location as a don’t care, since after finding the
there was an error in the network, or because this is
ENP = 1 in descriptor number 2, the software should ig-
nore ENP bits until it finds the next STP = 1.
Number OWN STP ENPa OWN STP ENPb Frame Arrival)
1 1 1 x 0 1 0 Bytes 1-800
2 1 0 X 0 0 0** Discarded buffer
3 0 0 X 0 0 ? Discarded buffer
Controller’s current
4 1 1 X 1 1 X
location
a. & b.ENP or ERR.
Buffer Size Tuning S2, S3, S4, S5, and S6. The result is that there will be
delay from the execution of task C9 until the execution
For maximum performance, buffer sizes should be ad-
of task S8. A perfectly timed system will have the values
justed depending upon the expected frame size and
for S5 and S7 at a minimum.
the values of the interrupt latency and application call
latency. The best driver code will minimize the CPU uti- An average increase in performance can be achieved,
lization while also minimizing the latency from frame if the general guidelines of buffer sizes in Figure 2 is fol-
end on the network to the frame sent to application lowed. However, as was noted earlier, the correct sizing
from driver (frame latency). These objectives are aimed for buffers will depend upon the expected message
at increasing throughput on the network while decreas- size. There are two problems with relating expected
ing CPU utilization. message size with the correct buffer sizing:
Note: The buffer sizes in the ring may be altered at any 1. Message sizes cannot always be accurately pre-
time that the CPU has ownership of the corresponding dicted, since a single application may expect differ-
descriptor. The best choice for buffer sizes will maxi- ent message sizes at different times. Therefore, the
mize the time that the driver is swapped out, while min- buffer sizes chosen will not always maximize
imizing the time from the last byte written by the throughput.
Am79C971 controller to the time that the data is 2. Within a single application, message sizes might be
passed from the driver to the application. In the dia- somewhat predictable, but when the same driver is
gram, this corresponds to maximizing S0, while mini- to be shared with multiple applications, there may
mizing the time between C9 and S8. (the timeline not be a common predictable message size.
happens to show a minimal time from C9 to S8.)
Additional problems occur when trying to define the
Note: By increasing the size of buffer number 1, we correct sizing because the correct size also depends
increase the value of S0. However, when we increase upon the interrupt latency, which may vary from system
the size of buffer number 1, we also increase the value to system, depending upon both the hardware and the
of S4. If the size of buffer number 1 is too large, then
software installed in each system.
the driver will not have enough time to perform tasks
Am79C971 D-7
In order to deal with the unpredictable nature of the The time from the end of frame arrival on the wire to de-
message size, the driver can implement a self-tuning livery of the frame to the application is labeled as frame
mechanism that examines the amount of time spent in latency. For the one-interrupt method, frame latency is
tasks S5 and S7. As such, while the driver is polling for minimized, while CPU utilization increases. For the
each descriptor, it could count the number of poll oper- two-interrupt method, frame latency becomes greater,
ations performed and then adjust the number 1 buffer while CPU utilization decreases. See Figure D3.
size to a larger value, by adding “t” bytes to the buffer
Note: Some of the CPU time that can be applied to
count, if the number of poll operations was greater than
non-Ethernet tasks is used for task switching in the
“x.” If fewer than “x” poll operations were needed for
CPU. One task switch is required to swap a non-Ether-
each of S5 and S7, then software should adjust the
net task into the CPU (after S7A) and a second task
buffer size to a smaller value by subtracting “y” bytes
switch is needed to swap the Ethernet driver back in
from the buffer count. Experiments with such a tuning
again (at S8A). If the time needed to perform these task
mechanism must be performed to determine the best
switches exceeds the time saved by not polling descrip-
values for “x” and “y.”
tors, then there is a net loss in performance with this
Note whenever the size of buffer number 1 is adjusted, method. Therefore, the LAPP method implemented
buffer sizes for buffer number 2 and buffer number 3 should be carefully chosen.
should also be adjusted. Figure D4 shows the buffer sizing for the two-interrupt
In some systems, the typical mix of receive frames on method. Note that the second buffer size will be about
a network for a client application consists mostly of the same for each method.
large data frames, with very few small frames. In this There is another alternative which is a marriage of the
case, for maximum efficiency of buffer sizing, when a two previous methods. This third possibility would use
frame arrives under a certain size limit, the driver the buffer sizes set by the two-interrupt method, but
should not adjust the buffer sizes in response to the would use the polling method of determining frame
short frame. end. This will give good frame latency but at the price
An Alternative LAPP Flow: Two-Interrupt Method of very high CPU utilization. And still, there are even
more compromise positions that use various fixed
An alternative to the above suggested flow is to use two
buffer sizes and, effectively, the flow of the one-inter-
interrupts, one at the start of the receive frame and the
rupt method. All of these compromises will reduce the
other at the end of the receive frame, instead of just
complexity of the one-interrupt method by removing the
looking for the SRP interrupt as described above. This
heuristic buffer sizing code, but they all become less ef-
alternative attempts to reduce the amount of time that
ficient than heuristic code would allow.
the software wastes while polling for descriptor own
bits. This time would then be available for other CPU
tasks. It also minimizes the amount of time the CPU
needs for data copying. This savings can be applied to
other CPU tasks.
D-8 Am79C971
Ethernet Ethernet
Wire Controller Software
activity: activity: activity:
S10: Driver sets up TX descriptor.
S9: Application processes packet, generates TX packet.

S8: Driver calls application

{ to tell application that
packet has arrived.
S7: Driver polls descriptor of buffer #3.
N2: EOM C8: Controller is performing intermittent Buffer

bursts of DMA to fill data buffer #3. S6: Driver copies data from buffer #2 to the application buffer.
#3

S5: Driver polls descriptor #2.
C6: "Last chance" lookahead to
descriptor #3 (OWN).
S3: Driver writes modified application
Buffer
#2
}{ pointer to descriptor #3.
S2: Driver call to application to
get application buffer pointer.
C4: Lookahead to descriptor #3 (OWN). S1: Interrupt latency.
C3: SRP interrupt
is generated. }
packet data arriving
Buffer S0: Driver is idle.

#1
C0: Lookahead to descriptor #2.
{N1: 64th byte of packet

data arrives.
N0: Packet preamble, SFD

and destination address
are arriving.
19364D-D3
Figure D3. LAPP Timeline for Two-Interrupt Method
Am79C971 D-9
#1 SIZE = HEADER_SIZE (minimum 64 bytes)
OWN = 1 STP = 0 A = Expected message size in bytes
Descriptor SIZE = S1+S2+S3+S4 S1 = Interrupt latency
#2
S2 = Application call latency
S3 = Time needed for driver to write
#3 SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
to third descriptor
#4 SIZE = HEADER_SIZE (minimum 64 bytes) data from buffer #1 to
application buffer space
#5 SIZE = S1+S2+S3+S4 data from buffer #2 to
OWN = 0 STP = 0 application buffer space
Descriptor
Descriptor OWN = 1 STP = 1 Note that the times needed for tasks S1,
#7 SIZE = HEADER_SIZE (minimum 64 bytes) S2, S3, S4, and S6 should be divided by
0.8 microseconds to yield an equivalent
Descriptor OWN = 1 STP = 0 number of network byte times before
#8 SIZE = S1+S2+S3+S4 subtracting these quantities from the
Descriptor OWN = 0 STP = 0 expected message size A.
19364D-D4
Figure D4. LAPP 3 Buffer Grouping for Two-interrupt Method

Note:
This document demonstrates a 3-buffer per packet implementation of LAPP. For PCnet-FAST application with external SRAMs
enabled, a 2-buffer per packet implementation can be used.
D-10 Am79C971
APPENDIX E
Auto-Negotiation Registers
The following registers exist in the Auto-Negotiation 13 SS NA (0) Speed Selection.

block and are written or read by using registers MII Ad- Defaults to ZERO
dress (BCR33) and MII Data Port (BCR34). These reg- after power-up and
isters are indirect read and write registers with the after hardware resets
register offset specified by the REGAD (BCR33, bits 3- (H_RESET). This is
0) portion of the MII Address Register (BCR33). The ZERO the entire time
PHYAD (BCR33, bits 3-0) portion specifies the specific the internal PHY is
PHY that you wish to communicate with. The internal active. The external
PHY on the Am79c971 controller has a PHYAD ad- PHY can be forced
dress of 1fh. The default external PHY has a PHYAD into 100Mbps or
address of 00h. The following is a table of these indirect 10Mbps mode by
registers and defaulted values for the internal registers. manipulation of this
bit. This bit is used
Register 0: MII Control Register only when the Auto-
Bit Name Default Description Negotiation Enable
bit is ZERO.
15 PRPHY Reset. Defaults to ZERO
after power-up and 12 ANE Variable* Auto-Negotiation
after hardware resets Enable. Defaults to
(H_RESET). This is ONE after power-up
normally only used to and after hardware
bring up the external resets (H_RESET).
PHY into a known This bit enables the
state. Not used for the internal or external
internal PHY. Use the PHY’s Auto-
normal Am79C971 Negotiation
reset mechanisms. capabilities. When
this bit is ZERO the
14 LB NA (0) Loop Back. Defaults internal/external
to ZERO after power- PHY’s must be forced
up and after hardware into the correct state
resets (H_RESET). through software
Loopback is intervention.
supported only in an
external PHY. See 11 PD NA (0) Power Down.
the “MII Defaults to ZERO
Configuration” after power-up and
section for more after hardware resets
details.. (H_RESET). This bit
only applies to the
external PHY. Use
the SLEEP# or other
power saving modes
in the Am79C971
Controller.
* See text on Auto Negotiation.
Am79C971 E-1
10 IS NA (0) Isolate. Defaults to Register 1: MII Status Register
ZERO after power-up
Bit Name Default Description
and after hardware
resets (H_RESET).
15 100T4 0 100Base-T4.
This bit only applies
Defaults to ZERO
to the external PHY.
after power-up and
This bit is used when
after hardware resets
multiple PHY’s can be
(H_RESET).
attached to the
Indicates that the
Am79C971 MII.
PHY is 100BASE-T4
9 RAN 0 Restart Auto capable. Not used on
Negotiation. Defaults the internal PHY.
to ZERO after power-
14 100XFD 0 100Base-X Full
up and after hardware
Duplex. Defaults to
resets ( H_RESET ).
ZERO after power-up
This bit is used when
and after hardware
the software needs to
resets (H_RESET).
reset the Auto-
Indicates that the
Negotiation process.
PHY is 100BASE-TX
For use with an
Full-Duplex capable.
external PHY without
software intervention. 13 100XHD 0 100Base-X Half
Duplex. Defaults to
8 DM 0 Duplex Mode.
ZERO after power-up
Defaults to ZERO
and after hardware
after power-up and
resets (H_RESET).
Indicates that the
(H_RESET). This bit
PHY is 100BASE-TX
sets the full-duplex
Half-Duplex capable.
feature for the internal
Not used on the
or external PHY’s.
internal PHY
Only valid when the
Auto-Negotiation 12 10FD 1 10Base Full Duplex.
Enable bit is not set. Defaults to ONE after
power-up and after
7 CT 0 Collision Test.
hardware resets
Defaults to ZERO
(H_RESET).
after power-up and
Indicates that the
PHY is 10BASE-T
(H_RESET). This bit
Full-Duplex capable.
is only useful for
testing the COL pin 11 10HD 1 10Base Half Duplex.
on the MII and is not Defaults to ONE after
supported without power-up and after
software intervention. hardware resets
(H_RESET).
0-6 RES 0 Reserved locations.
Indicates that the
Defaults to all ZEROs
PHY is 10BASE-T
after power-up and
Half-Duplex capable.
(H_RESET). 10-7 RES 0 Reserved locations.
These locations
should be read and
written as ZEROs.
E-2 Am79C971
6 MFPS 0 Management Frame 2 LS0 0 Link Status. Defaults
Preamble to ZERO after power-
Suppression. up and after hardware
Defaults to ZERO resets (H_RESET).
after power-up and This bit indicates the
after hardware resets current status of the
(H_RESET). This is network link.
used by the
Am79C971 controller 1 JD 0 Jabber Detect.
to reduce the time Defaults to ZERO
delay overhead with after power-up and
processing the MII after hardware resets
Management (H_RESET). This bit
Frames. Strips the 32 indicates that a jabber
bit preamble off of event occurred on the
each frame sent. network.
5 ANC 0 Auto-Negotiation 0 EC 1 Extended Capability.

Complete. Defaults to Defaults to ONE after
ZERO after power-up power-up and after
and after hardware hardware resets
resets (H_RESET). (H_RESET). This bit
This bit indicates that indicates that the
the Auto-Negotiation PHY has Auto-
process has Negotiation
completed and that capability. If this bit is
the contents of not set then the line
registers 4-8 are must be forced.
valid.
Register 2: PHY Identifier
4 RF 0 Remote Fault. Bit Name Default Description
Defaults to ZERO
after power-up and 15-0 OUI 0000 Organizationally
after hardware resets Unique Identifier.
(H_RESET). This is a Administered by the
indication that the IEEE.
remote node has
detected a fault with Register 3: PHY Identifier
your system.
Bit Name Default Description
3 ANA 1 Auto-Negotiation
Ability. Defaults to 15-10 OUI 68 Organizationally
ONE after power-up Unique Identifier.
and after hardware Administered by the
resets (H_RESET). IEEE.
This bit indicates that
PHY’s ability to do 9-4 MMN 01 Manufacturers Model
Auto-Negotiation. Number. The
This bit is defaulted Am79C971 Controller
ONE on the will have a default
Am79C971 model number of 1.
controller.
3-0 RN 1 Revision Number.
Initially ZERO.
Am79C971 E-3
Register 4: Auto Negotiation Register 5: Auto Negotiation Link-Partner
Advertisement Ability Register Ability Register
15 NP NA (0) Next Page. Defaults 0 These fields are identical to the previous and are valid
to ZERO after power- for the node in which we are currently engaged.
15 NP 0 Next Page. Defaults
resets (H_RESET).
to ZERO after power-
This bit indicates the
ability of the PHY to
resets (H_RESET).
send and receive
message pages after 14 ACK 0 Acknowledge.
the initial base code Defaults to ZERO
word has been sent. after power-up and
The Am79C971 after hardware resets
controller does not (H_RESET).
support Next Pages
currently. 13 RF 0 Remote Fault.
Defaults to ZERO
14 RES 0 Read as ZERO after power-up and
always. after hardware resets
(H_RESET)
13 RF 0 Remote Fault.
Defaults to ZERO 12-5 TAF 03 Technology Ability
after power-up and Field. Defaults to all
after hardware resets ZEROs after power-
(H_RESET). This bit up and after hardware
indicates that we resets (H_RESET)
have detected a
remote fault with the 4-0 SF 01 Selector Field.
other node. Defaults to all ZEROs
after power-up and
12-5 TAF 03 Technology Ability after hardware resets
Field. The (H_RESET)
Am79C971 controller
will only support Register 6: Auto Negotiation Expansion
10BaseT or 10BaseT
Register
full duplex with the
internal PHY device. Bit Name Description
When using the
internal PHY the TAF This is the catch all register of odds and ends that did
will be set to not fit in other registers.
00000011b always.
15-5 RES 0 Reserved. Read and
4-0 SF 01 Selector Field. The written as ZERO’s.
Am79C971 controller
will only currently 4 PDF 0 Parallel Detection
support IEEE 802.3 Fault. Defaults to
messages. When ZERO after power-up
using the internal and after hardware
PHY the SF will be resets (H_RESET).
set to 00001b always. This bit indicates that
more than one PHY
has responded to a
valid link or none
have responded to a
valid link. Either way
E-4 Am79C971
we need to restart the Register 7: Auto Negotiation Next Page
process. Transmit Register
3 LPNP 0 Link Partner Next Bit Name Description
Page Able. Defaults
to ZERO after power- This resister is only used during next pages. This is the
up and after hardware word that will be sent by the Am79C971 controller in re-
resets (H_RESET). sponse to a next page.
This bit gets set if the 15 NP 0 Next Page. Defaults
link partner can do to ZERO after power-
the Next Page up and after hardware
function. resets (H_RESET).
2 NPA 0 Next Page Able. 14 ACK 0 Acknowledge.
Defaults to ZERO Defaults to ZERO
after power-up and after power-up and
after hardware resets after hardware resets
(H_RESET). This bit (H_RESET).
indicates that the
internal/external PHY 13 MP 0 Message Page.
attached to the Defaults to ZERO
Am79C971 controller after power-up and
can do Next Pages. after hardware resets
The Am79C971 (H_RESET).
controller will not
support next pages 12 ACK2 0 Acknowledge 2.
without software Defaults to ZERO
support. after power-up and
1 PR 0 Page Received. (H_RESET).
Defaults to ZERO
after power-up and 11 TOG 0 Toggle. Defaults to
after hardware resets ZERO after power-up
(H_RESET). This bit and after hardware
indicates that a valid resets (H_RESET)
page has been seen
by the Am79C971 10-0 MUCF 0000 Message/Unformu-
controller’s PHY or lated Code Field. De-
the external PHY faults to all ZEROs
attached to the after power-up and
Am79C971 after hardware resets
controller. (H_RESET).
0 LPNA 0 Link Partner Auto-

Negotiation Able.
Defaults to ZERO
after power-up and
(H_RESET). This bit
indicates whether or
not the link partner
can auto-negotiate.
Am79C971 E-5
E-6 Am79C971
APPENDIX F
Am79C971A PCnet-FAST 10/100 Mbps PCI

Ethernet Controller REV A.6 ERRATA
REV A.6 STATUS

Revision A.6 silicon is the current full production silicon. Rev. A.6 has fixed rev. A.5 errata #13, #17 and #18. With
revision A.6, the device part number has also been revised to Am79C971A in order to distinguish it from revision
A.5 (Am79C971).
REV A.6 ERRATA SUMMARY
The device has seventeen errata to date. The system-level impact of these errata on customers is minimal. All infor-
mation below should be used in conjunction with the Am79C971 PCnet-FAST preliminary data sheet, dated March
1999 (PID #20550D). This datasheet applies to all revisions of the PCnet-FAST device. These errata do not affect
operation with PCnet software drivers.
Important Note: In 100 Mb mode, the Am79C971A requires the use of SRAM. Additionally, the SRAM clock
(EBCLK) should be driven with a 33 MHz clock, or if pulled up, the PCI clock should be 33MHz.
PCNET-FAST REV. A.6 ERRATA

The Symptom section gives an external description of the problem. The Implication section explains how the device
behaves and its impact on the system. The WORK AROUND section describes a work around for the problem. The
status section indicates when and how the problem will be fixed.
1) Symptom: The default Inter Packet Gap (IPG) value of 60H in CSR125, bits 15-8, results in an actual IPG of
100 bit-times versus the expected 96 bit-times.
Implication: There is a 4 bit-time offset between the IPG value in CSR125 and the actual IPG at the AUI,
10BASE-T, and MII ports of the PCnet-FAST device.
Workaround: Write the value 5CH into the IPG field of CSR125 to ensure an actual, minimum IPG of 96 bit-
times.
Status: No current plan to fix this erratum.
2) Symptom: The Interrupt Request pin (INTA#, pin 142), and some of the analog pins (RXD-, pin 110, RXD+,
pin 111, TXP-, pin 113, TXD-, pin 114, XTAL2, pin 120, DO-, pin 122, DI-, pin 125, DI+, pin 126, CI-, pin 127,
CI+, pin 128) are not accessible through the IEEE 1149.1 (JTAG) test interface.
Implication: Those pins are not included in the boundary-scan chain within the device.
Workaround: None.
3) Symptom: At high temperature and low Vcc (85 °C, 4.75V) with a minimum PCI clock low time of 12 ns, the
Tval timing for some PCI interface signals exceeds the PCI spec (11 ns max.) by up to 3 ns. The measured
value is less than 14 ns maximum on the production tester for this specific corner case for FRAME# de-asser-
tion, STOP# assertion, PERR# de-assertion, and DEVSEL# assertion.
Implication: Tval timing is well within the PCI spec for nominal Vcc and 50/50 PCI clock duty cycle. Typical
PCI systems should be able to tolerate Tval timings of 14 ns.
Workaround: None.
F-1
4) Symptom: Part A - On the first attempt of reading CSR30, the system will suffer a PCI Retry. A subsequent
CSR30 access will be allowed to read the correct CSR30 data. Part B - If the LAAINC (BCR29, bit 14) bit is
set, and if a CSR30 read access is in the middle of a series of continuous reads of BCR30 for SRAM/Flash
access, the CSR30 access causes the SRAM/Flash address to auto-increment.
Implication: Part A - This is a minor erratum with no impact on the system. The PCI Retry does not cause
any system errors and will automatically recover. Part B - The system-level exposure to this problem is very
minimal. There is no exposure or customers of AMD’s PCnet drivers, because AMD’s drivers do not perform
CSR30 reads. For those developing proprietary diagnostic software routines, please follow the workaround
recommended below.
Workaround: Part A - None needed and none available. Part B - Disable the LAAINC bit prior to executing
the specific register access sequence outlined in the symptom statement; LAAINC bit may be enabled subse-
quent to executing the CSR30 read access.
5) Symptom: In a high traffic network and with SRAM on and in 10Mbps mode, the babble error bit occasionally
gets set erroneously; no transmitter babbles are observed on the wire.
Implication: Some diagnostics software will report false babbles. No impact for customers who utilize the
PCnet family drivers since PCnet drivers do not report babble errors.
Workaround: Ignore the babble errors.
6) Symptom: In an excessively high collision network, the device occasionally set the LCOL bit erroneously in
10Mbps mode with external SRAM enabled.
Implication: No discernible performance impact. Problem has only been observed in lab set up. Some diag-
nostics software will report false LCOL errors.
Workaround: None.
7) Symptom: When PCnet-FAST receives a frame on the MII port with correct FCS followed by exactly one nib-
ble with RX_ER asserted, it does not report a FCS error.
Implication: None in an 802.3 compliant network. Observable in custom diagnostic tests for End of Shell De-
limiter (ESD) only.
Workaround: None.
8) Symptom: When RCVE bit (bit 2, CSR4, 5, 6, and 7) is set and the MII port is selected, the LED output does
not indicate the correct receive status. This bit functions correctly for the internal 10 BASE-T and AUI ports.
Implication: LED output will not be asserted based on the receive activities at the MII port.
Workaround: Use RCVME bit (bit 5, CSR 4, 5, 6 and 7) in place of the RCVE bit for proper LED receive status
indication. The RCVME bit enables the indication of all received packets which pass the address match func-
tion for this node, whereas the RCVE bit enables the indication of all packets received.
9) Symptom: During reception of a packet, if the CRS input to the device is de-asserted two RX_CLK times be-
fore the end of RX_DV, message byte counter (MCNT) will indicates one less byte and the last byte of the CRC
will be corrupt. If the CRS is de-asserted three or more RX_CLK times before the end of RX_DV, the CRC
error bit will be set and the packet will be lost.
Implication: Network performance might vary from normal to sluggish to no connection depending on the se-
verity and the rate of occurrence.
Workaround: The workaround for this problem is to OR the RX_DV and CSR signals from external PHY and
feed the output to the CRS input of the PCnet-FAST.
F-2
10) Symptom: When the device is connected to certain repeaters and hubs, there have been reports of receiving
corrupted data and bad packets. The hubs and repeaters that are used when these problems occur do not
comply with the IEEE 802.3 specification. Specifically they do not comply with the following tolerance: +/- 100
PPM. The problem is aggravated due to the fact that the device does not flag any error message as a result
of this. In addition the transfers corrupted packets and continues the network activity. The received packets
are corrupted but the CRC error bit does not get set.
Implications: a) In situations where there is no upper-layer protocol to detect the error, there is a possibility
that data may be corrupted when the device is used in conjunction with a non-IEEE 802.3 compliant hub or
repeater. b) In situations where the upper layer protocol detects the error (which is the most common situation
there may be some degradation in network performance. There is also a possibility of failure of the link or an
inability to maintain link status.
Workaround: It is suggested to adhere to IEEE compliant hubs and repeaters. This will avoid the circum-
stances that may compromise data integrity and or contribute to degradation of network performance
Status: There are no planned modifications for the device. However, modifications have been implemented
in later devices in the PCnet family, such that they can tolerate non-compliant IEEE 803.2 repeaters and hub.
11) Symptom: When the RCVME bit in the LED registers (BCR4-7) is set, the LED output drives for one clock
cycle, or longer if the pulse stretcher is on, due to reception of any packet. The expected behavior is that this
LED should be on only when there is an address match
Implications: LED output will drive every time there is an incoming packet on the wire, even when there is no
address match.
Workaround: None
12) Symptom: Setting the DRCVBC bit (CSR15, bit 14) does not prevent the reception of broadcast packets when
the LADRF[47 (CSR10, bit 15) is set.
Implications: Broadcast packets will be received when the user wants them excluded as a Logical packet.
Extra packet processing will be required.
Workaround: None
13) Symptom: Configuration Space Vendor ID (VID) Register can not a have a value other than 0x1022.
Implications: The Configuration Space VID is programmed indirectly through the BCR35. If any value other
than 0x1022 is programmed in BCR35 either through software or thorough the EEPROM, the BCR35 will have
the correct data but the VID register will have a corrupted value.
Workaround: Use only a value of 0x1022
14) Symptom: When using the advance parity mode, the occurrence of parity error in the last transfer of descrip-
tor DMA write does not stop the chip as indicated in the data sheet.
Implication: If customized or proprietary software relies on the chip to stop due to parity error in the advanced
parity mode, then it is possible (though highly unlikely in a typical system) to get corrupted data in descriptors.
PCnet software drivers do rely on the chip to stop the device upon parity error.
Workaround: Use the interrupt generated by the SINT as an indicator for parity error.
15) Symptom: When using buffer (descriptor) chaining for transmit packets, BUFF errors are reported under cer-
tain conditions.
Implication: Transmit packets associated with this condition are truncated.
F-3
Workaround: Do not allow a chain of TX descriptors to include a descriptor which previously was an end of
chain (EOP) and which is the last TX EOP descriptor for which the status has been returned. Here is a sug-
gested method for the workaround:
The device driver’s TX Write pointer (TX_W) points to first TX descriptor with OWN = 0
The device driver’s TX Read pointer (TX_R) points to the last TX descriptor with OWN=0
As the TX_R pointer is advancing in the chain, if the EOP bit is set then set a device driver TX_Last
EOP pointer (TX_L) = Current TX_R pointer
Then when a new frame is to be transmitted:
1) If a single descriptor is needed
if TX_R >TX_W, then a descriptor is available
2) If buffer chaining
if TX_L =TX_W, then TX_R -TX_W descriptors are available
else only TX_L - TX_W descriptors are available
16) Symptom: Collision LED does not show the collision status of the MII bus.
Implication: Very minor, collision LED will not show the status.
Workaround: None.
17) Symptom: During the automatic read of the EEPROM, such as after hardware reset or when the PREAD bit
is set in the BCR19, the device drives the EECS and EESK signal pins simultaneously. The EECS is driven
high at the same time when the EESK is driving low. This violates the EEPROM clock low to chip select setup
time (tSKS) parameter, which should be 100ns.
Implication: None. Even though the tSKS parameter is technically violated, the relationship between EESK
(clock), EECS (chip select), and EEDI (data in) signals is such that the device will not detect a false opcode.
This is how these signals relate to each other. EESK starts toggling from a high level. It clocks twice before
the EECS is asserted and continues toggling. The EEDI input is driven low at the same time that the EESK
starts toggling and stay low for four clocks after the assertion of the EECS. Since the EEDI is low when the
EECS is asserted, no false opcode is detected by the EEPROM.
Workaround: None needed. An external circuit may be used to delay the EECS signal by 100ns from the fall-
ing edge of the EESK signal
AM79C971A SYSTEM DESIGN HINTS

1) In 100 Mb/s mode, if the device reports excessive Transmit Underflows, set the NOUFLO bit (BCR18, bit 11) to
1. BCR18 contents are programmable either through the EEPROM or software driver.
2) In a system which does not use the reset pulse (RST#) for a warm boot reset (also known as Ctrl-Alt-Del reset),
the PCI-SIG recommends that the BIOS should disable bus mastering capability of the PCI bus mastering de-
vices early in the reboot cycle. The disabling of the bus mastering capability can be accomplished by resetting
the BMEN bit in the PCI Command Register (bit 2, Offset 04h) of the device’s PCI configuration space. This
recommendation should be followed to avoid possible system hang.
3) In the 100Mb/s Full Duplex mode, the expansion bus clock (which is typically connected to the PCI bus clock)
speed needs to be at 33MHz. Any slower speed may cause under/over flow condition.
4) When in auto-polling mode and no receive descriptors are available, the transmitter will not transmit until either a
receive descriptor is available or the transmit demand bit (TDMD, CSR0, bit 3) is set. If there are no receive
descriptors available, only one packet will be transmitted for every TDMD.
F-4
5) When using Auto-polling (BCR32, bit11), the ASEL bit (BCR2, bit1) should be reset to one, in order for the MII
Auto-poll logic (this is not the same as the descriptor Auto-polling) to correctly detect the link status change
on the MII PHY.
6) During the assertion of RST#, the EECS output becomes tri-stated. It is possible that the EECS may float to a
logic high state during this time. In order to prevent a hazardous condition due to this inadvertent selection of
the EEPROM, connect a 10K pull-down resistor from EECS to ground.
7) It is recommended that each poll to the SPND bit be performed with a software implemented delay of approxi-
mately 2-3 ms intervals. When the SPND bit (CSR5, bit0) is set in the device, the time that it takes to enter the
suspend mode is dependant on several factors. Some of these factors are; the number of packets queued for
transmission in the internal memory, the received packets still in the internal memory, the PCI bus grant time,
and the transmit channel availability in the half-duplex mode. To minimize unnecessary PCI Bus activity and
allow access to the PCI bus, it is recommended that each poll to the SPND bit be performed with a software
implemented delay of approximately 2-3 ms intervals. Successive polling or polling implemented with a hard-
ware delay will inhibit the device from completing its RX/TX DMA, causing longer delays before the device to
enter suspend mode.
F-5
F-6
Numerics
INDEX
A BCR16
I/O Base Address Lower 163
Absolute Maximum Ratings 200 BCR17
Advanced Parity Error Handling 46 I/O Base Address Upper 164
Am79C971 device, compatible with BCR18
AUI Isolation Transformers A-2 Burst and Bus Control Register 164
DC/DC Converters A-2 BCR19
Media Interface Modules A-1 EEPROM Control and Status 167
AMD Flash Programming 89 BCR2
Am79C971 Compatible Media Interface ModulesA-1 Miscellaneous Configuration 150
Recommendation for Power and Ground Decoupling BCR20
B-1 Software Style 170
Alternative Method for Initialization C-1 BCR21
Look-Ahead Packet Processing (LAPP) ConceptD-1 Interrupt Control 171
Attachment Unit Interface 25, 72 BCR22
Automatic EEPROM Read Operation 94 PCI Latency Register 171
Automatic Network Port Selection 79 BCR23
Automatic Network Selection PCI Subsystem
Exceptions 79 Vendor ID Register 172
External PHY Not Present 80 BCR24
External PHY Present and Auto-Negotiable 80 PCI Subsystem ID Register 172
External PHY Present BCR25
but Not Auto-Negotiable 80 SRAM Size Register 172
Force External Reset 81 BCR26
Working with the Micro Linear 6692 81 SRAM Boundary Register 173
Automatic Pad Generation 64 BCR27
Automatic Pad Stripping 67 SRAM Interface Control Register 173
Auto-Negotiation 79 BCR28
Expansion Bus Port Address Lower
B (Used for Flash/EPROM and SRAM
Accesses) 175
Basic Burst Read Transfer 37 BCR29
Basic Burst Write Transfer 39 Expansion Port Address Upper
Basic Functions 29 (Used for Flash/EPROM Accesses)
Network Interfaces 29 175
Software Interface 29 BCR30
System Bus Interface 29 Expansion Bus Data Port Register 176
Basic Non-Burst Read Transfer 37 BCR31
Basic Non-Burst Write Transfer 39 Software Timer Register 176
Block Diagram 5 BCR32
Buffer Management MII Control and Status Register 177
Transmit Descriptor Table Entry 57 BCR33
Buffer Management Unit 53 MII Address Register 179
Burst FIFO DMA Transfers 52 BCR34
Burst Transfer Disconnect 34 MII Management Data Register 180
Bus Acquisition 36 BCR35
Bus Configuration Registers 148–180 PCI Vendor ID Register 180
BCR0 BCR5
Master Mode Read Active 149 LED1 Status 155
I-1
BCR6 Initialization Block Address 1 118
LED2 Status 157 CSR20
BCR7 Current Transmit Buffer Address Lower 133
LED3 Status 160 CSR21
BCR9 Current Transmit Buffer Address Upper 133
Full-Duplex Control 163 CSR22
Bus Master DMA Transfers 37 Next Receive Buffer Address Lower 134
CSR23
C Next Receive Buffer Address Upper 134
CSR24
Carrier Tracking and End of Message 71 Base Address of Receive Ring Lower 134
Clock Acquisition 71 CSR25
Collision Detection 72 Base Address of Receive Ring Upper 134
Collision Handling 63 CSR26
Compatible (with Am79C971 device) Next Receive Descriptor Address Lower134
10BASE-T Filters and Transformers A-1 CSR27
AUI Isolation Transformers A-2
Next Receive Descriptor Address Upper134
DC/DC Converters A-2
CSR28
Media Interface Modules A-1
Current Receive Descriptor Address
Control and Status Registers 115–148
Lower 134
CSR0
CSR29
Am79C971 Controller Status and
Current Receive Descriptor Address
Control Register 115
Upper 135
CSR1
CSR3
Initialization Block Address 0 118
Interrupt Masks and Deferral Control 118
CSR10
CSR30
Logical Address Filter 2 129
Base Address of Transmit Ring Lower 135
CSR100
CSR31
Bus Timeout 146
Base Address of Transmit Ring Upper 135
CSR11
CSR32
Logical Address Filter 3 129
Next Transmit Descriptor Address Lower135
CSR112
CSR33
Missed Frame Count 147
Next Transmit Descriptor Address Upper135
CSR114
CSR34
Receive Collision Count 147
Current Transmit Descriptor Address Lower
CSR12
135
Physical Address Register 0 129
CSR35
CSR122
Current Transmit Descriptor Address
Advanced Feature Control 147
135
CSR124
CSR36
Test Register 1 147
Next Next Receive Descriptor Address
CSR125
136
MAC Enhanced Configuration Control 147
CSR37
CSR13
Next Next Receive Descriptor Address
Upper 136
CSR14
CSR38
Next Next Transmit Descriptor Address Lower
CSR15
136
Mode 130
CSR39
CSR16
Next Next Transmit Descriptor Address Upper
Initialization Block Address Lower 133
136
CSR17
CSR4
Initialization Block Address Upper 133
Test and Features Control 121
CSR18
CSR40
Current Receive Buffer Address Lower 133
Current Receive Byte Count 136
CSR19
CSR41
Current Receive Buffer Address Upper 133
Current Receive Status 136
CSR2
CSR42
I-2
Current Transmit Byte Count 137 DMA Address Register Lower 145
CSR43 CSR86
Current Transmit Status 137 Buffer Byte Counter 145
CSR44 CSR88
Next Receive Byte Count 137 Chip ID Register Lower 145
CSR45 CSR89
Next Receive Status 137 Chip ID Register Upper 146
CSR46 CSR9
Transmit Poll Time Counter 137 Logical Address Filter 1 129
CSR47 CSR92
Transmit Polling Interval 137 Ring Length Conversion 146
CSR48
Receive Poll Time Counter 138 D
CSR49
Receive Polling Interval 138 Data Decoding 72
CSR5 Data Registers, Other 100
DC Characteristics, Over Commercial
Extended Control and Interrupt 1 123
Operating Ranges Unless Otherwise
CSR58
Specified 200
Software Style 139
Decoupling/Bypass Capacitors B-1
CSR6
Descriptor
RX/TX Descriptor Table Length 125
DMA Transfers 47
CSR60
Rings 54
Previous Transmit Descriptor Address
Detailed Functions 30
Lower 140
Differential Input Termination 72
CSR61
Direct Access to the Interface 95
Previous Transmit Descriptor Address
Direct Flash Access 86
Upper 140
Direct SRAM Access 92
CSR62
Disconnect
Previous Transmit Byte Count 141
Of Burst Transfer 34
CSR63
Without Data Transfer 41
Previous Transmit Status 141
Distinctive Characteristics 1
CSR64
DMA Transfers
Next Transmit Buffer Address Lower 141
FIFO 50
CSR65
Next Transmit Buffer Address Upper 141
CSR66 E
Next Transmit Byte Count 141 EEPROM Interface 22, 94
CSR67 EEPROM MAP 95
Next Transmit Status 141 EEPROM-Programmable Registers 95
CSR7 Expansion Bus Interface 22, 84
Extended Control and Interrupt 2 126 AMD Flash Programming 89
CSR72 Direct Flash Access 86
Receive Ring Counter 142 Direct SRAM Access 92
CSR74 Expansion ROM - Boot Device Access 84
Transmit Ring Counter 142 External SRAM Configuration 90
CSR76 Frequency Demands for Network Operation 94
Receive Ring Length 142 Low Latency Receive Configuration 92
CSR78 No SRAM Configuration 92
Transmit Ring Length 142 SRAM Accesses 93
CSR8 SRAM Interface Bandwidth Requirements
Logical Address Filter 0 129 94
CSR80 Expansion ROM - Boot Device Access 84
DMA Transfer Counter and FIFO Threshold Expansion ROM Transfers 33
Control 142 External Address Detection Interface 81
CSR82 Internal PHY 81
Transmit Descriptor Address Pointer Lower Receive Frame Tagging 83
144 External Address Detection Interface,
CSR84 EEPROM Interface 26
I-3
External SRAM Configuration 90 Media Independent Interface 69
Miscellaneous 69
F Loss of Carrier 65
Low Latency Receive Configuration 92
FIFO DMA Transfers 50
Framing
Transmit and Receive Message Data M
Encapsulation 60 MAC 60, 61, 62
Frequency Demands for Network Operation Magic Packet Mode, Power Saving 97, 98
Expansion Bus Interface 94 Manchester Encoder/Decoder 70
Full-Duplex Carrier Tracking and End of Message 71
Link Status LED Support 76 Clock Acquisition 71
Operation 75 Data Decoding 72
Functions External Clock Drive Characteristics 70
Basic 29 External Crystal Characteristics 70
Detailed 30 Input Signal Conditioning 71
Jitter Tolerance Definition 72
G MENDEC Transmit Path 70
PLL Tracking 71
General Description 2
Receiver Path 71
General Purpose Serial Interface 75
Transmitter Timing and Operation 70
Manufacturer Contact Information A-2
I Master Abort 43
I/O Resources 103 Master Bus Interface Unit 36
IEEE 1149.1 (1990) Test Access Port Bus Acquisition 36
Interface Bus Master DMA Transfers 37
Boundary Scan Register 99 Basic Burst Read Transfer 37
Instruction Register and Decoding Logic Basic Burst Write Transfer 39
99 Basic Non-Burst Write Transfer 39
Other Data Registers 100 Burst FIFO DMA Transfers 52
Supported Instructions 99 Descriptor DMA Transfers 47
TAP Finite State Machine 99 Disconnect With Data Transfer 40
Initialization Disconnect Without Data Transfer 41
Buffer Management Unit 53 FIFO DMA Transfers 50
Initialization Block Initialization Block DMA Transfers 47
Description 180 Master Abort 43
DMA Transfers 47 Master Initiated Termination 42
LADRF 182 Non-Burst FIFO DMA Transfers 50
Mode 183 Parity Error Response 43
PADR 182 Preemption During Burst Transaction 42
RDRA and TDRA 181 Preemption During Non-Burst
RLEN and TLEN 181 Transaction 42
Input Signal Conditioning, MENDEC 71 Master Initiated Termination 42
Instruction Register and Decoding Logic 99 Media Access Control 60
Collision Handling 63
Destination Address Handling 61
J Error Detection 61
Jabber Function, Twisted Pair Transceiver 74 Framing 60
Management 61
L Medium Allocation 62
LADRF 182 Transmit and Receive Message Data
LAPP Flow, Outline of D-1 Encapsulation 60
LAPP Setup D-1 Media Independent Interface
Late Collision 65 Auto-Poll External PHY Status Polling 78
LED Support 97 Described 76
Link Test Function, Twisted Pair Transceiver 73 Loopback Features 69
Look-Ahead Packet Processing (LAPP) Concept D-1 Medium Allocation 62
Loopback Features MII Management Frames 78
I-4
MII Network Port Manager 79 Pin Designations
MII Network Status Interface 77 Listed By Driver Type 17
MII Receive Interface 76 Listed by Group 15
MII Transmit Interface 76 Listed by Pin Number 13
Transmit and Receive Message Data PLL Tracking 71
Encapsulation 60 Polarity Detection and Reversal 73
MENDEC Transmit Path 70 Power Savings Modes 97
MII 60 Magic Packet 98
MII, See Media Independent Interface Sleep 97
Miscellaneous Loopback Features 69 Power Supply Pins 28
Mode 183 Preemption
Modes During Non-Burst Transaction 42
AUI 72
GPSI 75 R
T-MAU 69
Receive
Descriptor Table Entry 58
N Exception Conditions 68
Network Interfaces, Basic Functions 29 FCS Checking 68
No SRAM Configuration, AMD Flash Operation
Programming 92 Address Matching 66
Non-Burst FIFO DMA Transfers 50 Automatic Pad Stripping 67
Exception Conditions 68
O FCS Checking 68
Function Programming 66
Operating Ranges 200
Receive Descriptors 183
Operating Ranges, DC Characteristics 200
RMD0 183
Operation
RMD1 183
Automatic Pad Generation 64
RMD2 185
Transmit Exception Conditions 65
RMD3 186
Transmit FCS Generation 64
Receiver Path, Manchester Encoder/Decoder
Transmit Function Programming 63
71
Ordering Information 4
Recommendation for Power and Ground
Outline, LAPP Flow D-1
Decoupling B-1
Register Programming Summary 196
P Am79C971 Bus Configuration Registers 198
PADR 182 Am79C971 Control and Status Registers 196
Parity Error Response 35, 43 Am79C971Programmable Registers 196
PCI (Peripheral Component Interconnect) Related AMD Products 10
Command Register 108 Reset 102
Expansion ROM Base Address Register H_Reset 102
113 RLEN and TLEN 181
Header Type Register 111 STOP 102
Interrupt Line Register 114 RMD0 183
Interrupt Pin Register 114 RMD1 183
Latency Timer Register 111 RMD2 185
MAX_LAT Register 114 RMD3 186
Memory Mapped I/O Base Address
Register 112 S
MIN_GNT Register 114 Signal Quality Error Test Function 74
PCI I/O Base Address Register 111 Slave
Programming Interface Register 111 Bus Interface Unit 30
Revision ID Register 111 Configuration Transfers 30
Status Register 109 Slave I/O Transfers 30
Sub-Class Register 111 Slave Cycle Termination
Subsystem ID Register 113 Disconnect of Burst Transfer 34
Subsystem Vendor ID Register 113 Parity Error Response 35
Physical Dimensions 229 Sleep Mode 97
I-5
Software Access 102 Collision Detection 72
I/O Resources 103 Jabber Function 74
Address PROM Space 103 Link Test Function 73
Double Word I/O Mode 104 Polarity Detection and Reversal 73
I/O Registers 103 Signal Quality Error Test Function 74
Reset Register 104 Twisted Pair Interface Status 74
Word I/O Mode 104 Twisted Pair Receive Function 73
PCI Configuration Registers 108 Twisted Pair Transmit Function 72
Software Interface, Basic Functions 29 Transmit
Software Interrupt Timer 59 Exception Conditions 65
SQE Test Error 65 FCS Generation 64
SRAM Function Programming 63
Accesses 93 Transmit and Receive Message Data
Configuration 90 Encapsulation 60
SRAM Interface Bandwidth Requirements 94 Transmit Descriptor
STOP 102 Table Entry, Buffer Unit Management 57
Supported Instructions, IEEE 1149.1 Test Transmit Descriptors
Access Port Interface 99 Described 186
Switching TMD0 186
Key to Switching Waveforms 211 TMD1 187
Test Circuits 211 TMD2 188
Switching Characteristics TMD3 189
10Base-T Interface 206 Transmit Exception Conditions
Attachment Unit Interface 207 Late Collision 65
Bus Interface 203 Loss of Carrier 65
External Address Detection Interface 210 SQE Test Error 65
General-Purpose Serial Interface 209 Transmitter Timing and Operation 70
Media Independent Interface 208 Twisted-Pair Transceiver 72
Switching Waveforms 214
10BASE-T Interface 219 U
Attachment Unit Interface 221
User Accessible Registers 106
Expansion Bus Interface 217
Interrupt Line Register 114
External Address Detection Interface 227
PCI Command Register 108
General-Purpose Serial Interface 226
PCI Configuration Registers 108
Media Independent Interface 224
PCI Expansion ROM Base Address Register113
Receive Frame Tag 228
PCI Header Type Register 111
System Bus Interface 213
PCI I/O Base Address Register 111
System Bus Interface, Basic Functions 29
PCI Interrupt Pin Register 114
PCI Latency Timer Register 111
T PCI MAX_LAT Register 114
10BASE-T Interface Connection 74 PCI Memory Mapped I/O Base Address Register
10Base-T Interface Connection 74 112
TAP Finite State Machine 99 PCI MIN_GNT Register 114
T-MAU Loopback Modes 69 PCI Programming Interface Register 111
TMD0 186 PCI Revision ID Register 111
TMD1 187 PCI Status Register 109
TMD2 188 PCI Sub-Class Register 111
TMD3 189 PCI Subsystem ID Register 113
Transceiver PCI Subsystem Vendor ID Register 113
10Base-T Interface Connection 74
I-6
The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with
respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci-fications and product descriptions at any
time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any in-tellectual property rights is granted by this publication. Except as
set forth in AM’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products
including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other appli-
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Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo and combinations thereof, HIMIB, IMR+, Magic Packet, PCnet, and PCnet-FAST, are trademarks of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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Am79C971

— IEEE 802.3-compliant MII — Supports full programmability of half-/full-

Publication# 20550 Rev: E Amendment: /0

ALTERNATE PACKAGING OPTION

Valid Combinations Valid Combinations

Part No. Description

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)

Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver

Am79C98 Twisted Pair Ethernet Transceiver (TPEX)

Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

Am79865 100 Mbps Physical Data Transmitter (PDT)

An79866A 100 Mbps Physical Data Receiver (PDR)

Am79C870 Quad 100BASE-X Transceiver

Am79C871 Quad 100BASE-X Repeater Transceiver

Am79C940 Media Access Controller for Ethernet (MACE™)

Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)

Am79C981 Integrated Multiport Repeater Plus™ (IMR+™)

Am79C987 Hardware Implemented Management Information Base™ (HIMIB™)

Pin 1 is marked for orientation.

Pin Pin Pin Pin Pin Pin Pin

Pin Pin Pin Pin Pin Pin Pin

Pin Name Pin Function Type1 Driver No. of Pins

Pin Name Pin Function Type1 Driver No. of Pins

Name Type IOL (mA) IOH (mA) Load (pF)

PAR PAR PAR

The Am79C971 controller will not assert DEVSEL if it

PAR PAR PAR

Figure 3. Slave Read Using I/O Command

PAR PAR PAR

Figure 4. Slave Write Using Memory Command

PAR PAR PAR

DEVSEL is sampled 20550D-8

Figure 5. Expansion ROM Read

Slave Cycle Termination

Disconnect When Busy

AD ADDR 1st DATA

PAR PAR PAR

PAR PAR PAR DEVSEL

TRDY Figure 9. Address Parity Error Response

PAR PAR PAR

Master Bus Interface Unit Table 3. Master Commands (Continued)

AD ADDR DATA ADDR DATA

C/BE 0110 0000 0110 0000

PAR PAR PAR PAR PAR

Figure 12. Non-Burst Read Transfer

AD ADDR DATA DATA DATA

C/BE 1110 0000

PAR PAR PAR PAR PAR

Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)

AD ADDR DATA ADDR DATA

C/BE 0111 BE 0111 BE

PAR PAR PAR PAR PAR

Figure 14. Non-Burst Write Transfer

AD ADDR DATA DATA DATA DATA

PAR PAR PAR PAR PAR PAR

Figure 15. Burst Write Transfer (EXTREQ = 1)

AD ADDRi DATA DATA ADDRi+8

C/BE 0111 0000 0111

PAR PAR PAR

Figure 16. Disconnect With Data Transfer