Exercises – Technology:

a) How many mask layers lithography steps do you need to form a simple
CMOS process (p- and n-MOS + contacts)?
b) What are these steps – draw a set of pictures with each pattern
generation step!

1
Exercises – Technology:

a) How many mask layers lithography steps do you need to form a simple
CMOS process (p- and n-MOS + contacts)?
6 up to contact – 12 with 2 metal layers and pad opening/passivation
(minimal full back-end of line)
b) What are these steps – draw a set of pictures with each pattern
generation step!
FEOL: Nwell, oxide, trench, poly (Gate), psd (p-MOS S/D), nsd (n-MOS
S/D),
BEOL: contact, metal1, via1, metal 2, pad opening, polymide

2
Exercises – Resistors

a) You need an accurate 500Ohm resistor – which technology option (see

script of lecture) do you choose?
b) Calculate the thermal noise voltage of a resistor in the band between
1Hz and 1kHz for a 1kOhm resistor
c) How much does flicker noise affect this result and how can you minimize
it‘s effect (see script of lecture)?
d) What affects the matching of resistors and how can you minimize effects
of matching?

3
Exercises – Resistors
a) You need an accurate 500Ohm resistor – which technology option (see
script of lecture) do you choose?
Poly-Si blocked best suited, or Metal film if available
b) Calculate the thermal noise voltage of a resistor in the band between
1Hz and 1kHz for a 1kOhm resistor
V²n= 4kT * 1KOhm * 999Hz = 1.6E-14, Vn= 130nV
c) How much does flicker noise affect this result and how can you minimize
it‘s effect (see script of lecture)?
If voltage drop across resistor is high – if too high increase resistor area
d) What affects the matching of resistors and how can you minimize effects
of matching? See script
4
Exercises – Transistor

Transistor analysis of a 0.25um long and 10um wide n-MOSFET:

a) Draw the transconductance gm as a function of Vds for a Vgs >Vth!
b) Give an indication for the values for gm and Vds at the turn-over point
between linear mode and saturation at the scale of both x- and y-axis (see
process parameters below)!
Process parameters: K= 25uA/V², Vth=0.4V
c) Same for p-MOS (-K=10uA/V², Vth=-0.4V)!

5
Exercises – Transistor

For p-MOS:
Mirror at y-axis -
Note, that since Vds is
negative here, also K
has to be negative to
get positive gm

6
Resistance or ideality of a transfer gate
Calculate the on-resistance Rout at different Vin
(0.5,1,1.5V) for VDD of 1.8V for a 10um wide
and minimal length switch
Vin Vout • What would be the best sizing for a full input
swing (0 to VDD ) between n- and p-MOS
• What width do you need to have an on-
resistance smaller than 10Ohm?
(Process parameters: n-MOS K= 25uA/V²,
Vth=0.4V, p-MOS K=-10uA/V², Vth=-0.4V)

7
 Resistance or ideality of a transfer gate
• Calculate the On-resistance
1/Rout = gmn + gmp + gdsn + gdsp ≈ gdsn + gdsp
(for Vds<Vgs) = (Kn*Wn*Vgsn,eff/L) + (Kp*Wp*Vgsp,eff/L)
• What would be the best sizing for a full input swing
(0 to VDD ) between n- and p-MOS
Wp= 2.5 * Wn
Vin Vout • What width do you need to have an on-resistance
smaller than 10Ohm?
1/10Ohm = 2 * 25uA/V² * 500mV * 1/0.25um * Wn
Wn = 1000um, Wp=2500um
(Process parameters: n-MOS K= 25uA/V², Vth=0.4V, p-
MOS K=-10uA/V², Vth=-0.4V, Lmin=0.25um)
8
 Analog circuit exercise on DC biasing
• Look at the first MOSFET and determine
its current / voltage characteristics?
• What does this mean for the current
flowing through the second transistor?
• Can we calculate Vgs of M1 – and what
is the resulting value for process
parameter K= 25uA/V², Vth=0.4V and
R=1kOhm?
• What is the min voltage allowed at M2 to
guarantee proper functionality?

9
Analog circuit exercise on DC biasing
• Look at the first MOSFET and
determine its current / voltage
characteristics?
Diode config -> 1 Vth at least (may
increas with more current to come into)
• What does this mean for the current
flowing through the second transistor?
Current mirror with W-ratio to M1

10
Analog circuit exercise on DC biasing
Can we calculate Vgs of M1 – and what is the
resulting value for process parameter K= 25uA/V²,
Vth=0.4V and R=1kOhm?
Sqrt(Iin)=-1/sqrt(2KR*(W/L))
+/-sqrt(1/(2KR*(W/L))-(Vth-Vdd)/R)
Iin1= (second possible operating point – not desired
here …)
Iin2=1/(2KR*(W/L))+2/sqrt(2KR*(W/L))*
sqrt(1/(2KR*(W/L))-(Vth-Vdd)/R)+
(1/(2KR*(W/L))-(Vth-Vdd)/R)
• What is the min voltage allowed at M2 to
guarantee proper functionality?
vsat 11
Circuit sizing exercise
0.25um long and 10um wide n-MOSFET in a common source
circuit: the circuit needs to be biased in saturation for an input
voltage range of 0.5-1V and a supply voltage of 2.5V:

a) Check if this condition is met under all circumstances and name

the maximum resistance R allowed at the input for the given
process parameters of the n-MOS.
b) What is the small signal gain (dVout/dVin) of this circuit
assuming Rds is much larger than R and R=2kOhm at the max. and
min input voltage values?
c) What changes with process variability Vth=0.3V or 0.5?
d) What changes with gain if W and L double?

Process parameters: K= 25uA/V², Vth=0.4V

12
Circuit sizing exercise

c) Rmax gets smaller / larger

d) First order the same

13
Parasitic capacitance
What is the capacitance you can expect for a NMOS transistor with source and bulk as well as drain
and gate tied together - at different voltage drops between the source/bulk terminal and the
drain/gate terminal for a device at different voltage drops between the gate and the source/drain/bulk
terminal
a) Draw a technology cross section and indicate all area capacitances!
b) Draw a top view of the device and indicate all sidewall capacitances!
c) Calculate Ctotal of the capacitance of this configuration for a gate-to-source voltage larger than
threshold voltage!
d) What changes for the dominant capacitance contributor when the device is biased in weak instead
of strong inversion?
Process parameters: width 10um and length 0.5um,
Cjunct_sidewall = CGD_sidewall = CGS_sidewall = 0.1 fF/um,
Cjunct_area = CSB_area == CDB_area 1fF/um², (assume a 1um long source region)
CovGS = CovDG = 0.3fF/um,
Cox = 5fF/um², Cinv = 2fF/um² for a gate-source voltage ~<Vth

14
Parasitic capacitance

15
Exercise towards digital challenges
(the hidden analog domain in digital)

• What is the impact of the digital design methodology

having a variable clock duty cycle?
(considering normal operating conditions)
• What is the impact of this method to technology transfer
(other fab, other process)?
• What is the impact of this method to the next technology
generation‘s cost of development?

16
Exercise towards digital challenges
(the hidden analog domain in digital)
• What is the impact of the digital design methodology
having a variable clock duty cycle?
A timing margin
• What is the impact of this method to technology transfer
(other fab, other process)?
New timing margin which needs to be recharacterized for worst case
conditions (but only once!)
• What is the impact of this method to the next technology
generation‘s cost of development?
Low 17