TPIC6C596

POWER LOGIC 8-BIT SHIFT REGISTER

SLIS093 – MARCH 2000

D Low rDS(on) . . . 7 Ω Typ D OR N PACKAGE

D Avalanche Energy . . . 30 mJ (TOP VIEW)

D Eight Power DMOS Transistor Outputs of VCC 1 16 GND

100-mA Continuous Current SER IN 2 15 SRCK
D 250-mA Current Limit Capability DRAIN0 3 14 DRAIN7
D ESD Protection . . . 2500 V DRAIN1 4 13 DRAIN6
D Output Clamp Voltage . . . 33 V DRAIN2 5 12 DRAIN5
DRAIN3 DRAIN4
D
6 11
Enhanced Cascading for Multiple Stages CLR 7 10 RCK
D All Registers Cleared With Single Input G 8 9 SER OUT
D Low Power Consumption

description logic symbol†

8
The TPIC6C596 is a monolithic, medium-voltage, G EN3
low-current power 8-bit shift register designed for 10
RCK C2
use in systems that require relatively moderate 7 SRG8
load power such as LEDs. The device contains a CLR R
15
built-in voltage clamp on the outputs for inductive SRCK C1
transient protection. Power driver applications 2 3
SER IN 1D 2 DRAIN0
include relays, solenoids, and other low-current or 4
medium-voltage loads. DRAIN1
5
DRAIN2
This device contains an 8-bit serial-in, parallel-out 6
DRAIN3
shift register that feeds an 8-bit D-type storage 11
register. Data transfers through both the shift and DRAIN4
12
storage registers on the rising edge of the shift DRAIN5
13
register clock (SRCK) and the register clock DRAIN6
(RCK), respectively. The storage register trans- 14
2 DRAIN7
fers data to the output buffer when shift register 9
SER OUT
clear (CLR) is high. When CLR is low, all registers
in the device are cleared. When output enable (G) † This symbol is in accordance with ANSI/IEEE Std 91-1984
is held high, all data in the output buffers is held and IEC Publication 617-12.
low and all drain outputs are off. When G is held
low, data from the storage register is transparent to the output buffers. When data in the output buffers is low,
the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current
capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide
additional hold time for cascaded applications. This will provide improved performance for applications where
clock signals may be skewed, devices are not located near one another, or the system must tolerate
electromagnetic interference.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  2000, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

description (continued)
Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous
sink-current capability. Each output provides a 250-mA maximum current limit at TC = 25°C. The current limit
decreases as the junction temperature increases for additional device protection. The device also provides up
to 2500 V of ESD protection when tested using the human-body model and 200 V machine model.
The TPIC6C596 is characterized for operation over the operating case temperature range of – 40°C to 125°C.
logic diagram (positive logic)

G 8
10
RCK
3
7 DRAIN0
CLR

D D
15
SRCK C1 C2
CLR CLR 4
2 DRAIN1
SER IN

D D
C1 C2
CLR CLR 5
DRAIN2

D D
C1 C2
CLR CLR 6
DRAIN3

D D
C1 C2
CLR CLR 11
DRAIN4

D D
C1 C2
CLR CLR 12
DRAIN5

D D
C1 C2
CLR CLR 13
DRAIN6

D D
C1 C2
CLR CLR 14
DRAIN7

D D
C1 C2
CLR CLR 16
GND

D
C1
9
CLR SER OUT

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 TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

schematic of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS

VCC
DRAIN

33 V

Input

25 V

12 V 20 V

GND
GND

absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)†
Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 250 mA
Continuous drain current, each output, all outputs on, ID, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Peak drain current single output, IDM,TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ
Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 4).

DISSIPATION RATING TABLE

TC ≤ 25°C DERATING FACTOR TC = 125°C
PACKAGE
POWER RATING ABOVE TC = 25°C POWER RATING
D 1087 mW 8.7 mW/°C 217 mW
N 1470 mW 11.7 mW/°C 294 mW

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TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

recommended operating conditions

MIN MAX UNIT
Logic supply voltage, VCC 4.5 5.5 V
High-level input voltage, VIH 0.85 VCC V
Low-level input voltage, VIL 0.15 VCC V
Pulsed drain output current, TC = 25°C, VCC = 5 V, all outputs on (see Notes 3 and 5 and Figure 11) 250 mA
Setup time, SER IN high before SRCK↑, tsu (see Figure 2) 15 ns
Hold time, SER IN high after SRCK↑, th (see Figure 2) 15 ns
Pulse duration, tw (see Figure 2) 40 ns
Operating case temperature, TC – 40 125 °C
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit TJ – TC to 10°C maximum.

electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA 33 37 V
VSD Source-to-drain diode forward voltage IF = 100 mA 0.85 1.2 V
IOH = – 20 µA, VCC = 4.5 V 4.4 4.49
VOH High level output voltage,
High-level voltage SER OUT V
IOH = – 4 mA, VCC = 4.5 V 4 4.2
IOL = 20 µA, VCC = 4.5 V 0.005 0.1
VOL Low level output voltage,
Low-level voltage SER OUT V
IOL = 4 mA, VCC = 4.5 V 0.3 0.5
IIH High-level input current VCC = 5.5 V, VI = VCC 1 µA
IIL Low-level input current VCC = 5.5 V, VI = 0 –1 µA
All outputs off 20 200
ICC Logic supply current VCC = 5
5.5
5V µA
All outputs on 150 500
fSRCK = 5 MHz, CL = 30 pF,
ICC(FRQ) Logic supply current at frequency 1.2 5 mA
All outputs off, See Figures 2 and 6
VDS(on) = 0.5 V, IN = ID,
IN Nominal current 90 mA
TC = 85°C, See Notes 5, 6 and 7
VDS = 30 V, VCC = 5.5 V 0.1 5
IDSX Off-state drain current VDS = 30 V, VCC = 5.5 V, µA
0.15 8
TC = 125°C
ID = 50 mA,
6.5 9
VCC = 4.5 V
ID = 50 mA,
See Notes 5 and 6
rDS(on) Static drain-source on-state resistance TC = 125°C, 9.9 12 Ω
and Figures 7 and 8
VCC = 4.5 V
ID = 100 mA,
6.8 10
VCC = 4.5 V
NOTES: 5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.

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 TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

switching characteristics, VCC = 5 V, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output from G 80 ns
tPHL Propagation delay time, high-to-low-level output from G CL = 30 pF,, ID = 75 mA,, 50 ns
tr Rise time, drain output See Figures 1, 2, and 9 100 ns
tf Fall time, drain output 80 ns
CL = 30 pF, ID = 75 mA,
tpd Propagation delay time, SRCK↓ to SEROUT 15 ns
See Figure 2
CL = 30 pF, ID = 75 mA,
f(SRCK) Serial clock frequency 10 MHz
See Note 8
ta Reverse-recovery-current rise time IF = 100 mA,, µ ,
di/dt = 10 A/µs, 100
ns
trr Reverse-recovery time See Notes 5 and 6 and Figure 3 120
NOTES: 5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin.

thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
D package 115
RθJA Thermal resistance,
resistance junction-to-ambient
junction to ambient All 8 outputs with equal power °C/W
N package 85

PARAMETER MEASUREMENT INFORMATION

5V 15 V 7 6 5 4 3 2 1 0
5V
SRCK
1
ID 0V
7 VCC
CLR 5V
G
15 RL = 200 Ω
0V
SRCK 3 – 6,
DUT Output 5V
Word 11 –14 SER IN
2 0V
SER IN DRAIN
Generator
5V
(see Note A) 10 RCK
RCK CL = 30 pF 0V
8 (see Note B)
5V
G
CLR
GND 0V

16 15 V
DRAIN1
0.5 V
TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 1. Resistive-Load Test Circuit and Voltage Waveforms

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TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

PARAMETER MEASUREMENT INFORMATION

5V
G 50% 50%
0V
5V 15 V tPLH tPHL
1 24 V
90% 90%
7 VCC Output
CLR 10% 10%
ID 0.5 V
15 RL = 200 Ω
SRCK 3 – 6, tr tf
Word DUT Output
2 11 –14 SWITCHING TIMES
Generator SER IN DRAIN
(see Note A) 5V
10 CL = 30 pF 50%
RCK SRCK
8 (see Note B) 0V
G GND tsu
th
16 5V
SER IN 50% 50%
TEST CIRCUIT 0V
tw

INPUT SETUP AND HOLD WAVEFORMS

SRCK 50% 50%

tpd tpd

SER OUT
50% 50%

SER OUT PROPAGATION DELAY WAVEFORM

NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 2. Test Circuit, Switching Times, and Voltage Waveforms

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 TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

PARAMETER MEASUREMENT INFORMATION

TP K
DRAIN
0.1 A
Circuit 2500 µF
Under 250 V di/dt = 10 A/µs
Test + IF
L = 0.85 mH 15 V
IF –
(see Note A) 0
TP A
25% of IRM
t2
t1 t3 Driver
IRM
RG

VGG ta
50 Ω
(see Note B) trr

TEST CIRCUIT CURRENT WAVEFORM

NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The VGG amplitude and RG are adjusted for di/dt = 10 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.

Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode

5V 15 V

tw
1 tav
7 VCC 30 Ω 5V
CLR Input
15 SRCK ID See Note B 0V
DUT IAS = 200 mA
2 1.5 H
Word SER IN
Generator 3 – 6, ID
(see Note A) 10 11 –14
RCK DRAIN VDS
8 V(BR)DSX = 33 V
G GND
VDS MIN
16

SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT VOLTAGE AND CURRENT WAVEFORMS

NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 200 mA.
Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ.

Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms

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TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

TYPICAL CHARACTERISTICS

PEAK AVALANCHE CURRENT SUPPLY CURRENT

vs vs
TIME DURATION OF AVALANCHE FREQUENCY
1 6
VCC = 5 V
TC = 25°C
TC = – 40°C to 125°C
IAS – Peak Avalanche Current – A

5
0.4

I CC – Supply Current – mA
4
0.2

0.1 3

2
0.04

0.02 1

0.01 0
0.1 0.2 0.4 1 2 4 10 0.1 1 10 100
tav – Time Duration of Avalanche – ms f – Frequency – MHz
Figure 5 Figure 6

DRAIN-TO-SOURCE ON-STATE RESISTANCE STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE

vs vs
DRAIN CURRENT LOGIC SUPPLY VOLTAGE
r DS(on) – Static Drain-to-Source On-State Resistance – Ω

30 12
r DS(on) – Drain-to-Source On-State Resistance – Ω

VCC = 5 V ID = 50 mA
See Note A TC = 125°C See Note A
25 10

TC = 125°C
20 8

TC = 25°C
15 6

10 TC = 25°C 4 TC = – 40°C

5 2
TC = – 40°C

0 0
50 70 90 110 130 150 170 190 250 4 4.5 5 5.5 6 6.5 7

ID – Drain Current – mA VCC – Logic Supply Voltage – V

Figure 7 Figure 8

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 TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

TYPICAL CHARACTERISTICS
SWITCHING TIME
vs
CASE TEMPERATURE
140
ID = 75 mA
See Note A tr
120

100 tr
Switching Time – ns
80 tPLH

60
tPHL

40

20

0
–50 –25 0 25 50 75 100 125
TC – Case Temperature – °C

Figure 9
NOTE A: Technique should limit TJ – TC to 10°C maximum.

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TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

THERMAL INFORMATION

MAXIMUM CONTINUOUS MAXIMUM PEAK DRAIN CURRENT

DRAIN CURRENT OF EACH OUTPUT OF EACH OUTPUT
vs vs
NUMBER OF OUTPUTS CONDUCTING NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY SIMULTANEOUSLY

I D – Maximum Peak Drain Current of Each Output – A

0.25 0.3
I D – Maximum Continuous Drain Current

VCC = 5 V d = 10%
0.25
0.2
d = 20%
0.2
of Each Output – A

0.15 d = 50%
TC = 25°C
0.15
d = 80%
0.1 TC = 100°C
0.1

VCC = 5 V
0.05 TC = 125°C
0.05 TC = 25°C
d = tw/tperiod
= 1 ms/tperiod
0 0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

N – Number of Outputs Conducting Simultaneously N – Number of Outputs Conducting Simultaneously

Figure 10 Figure 11

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 TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000

THERMAL INFORMATION

D PACKAGE†
NORMALIZED JUNCTION - TO -AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
10
R θJA – Normalized Junction-to-Ambient Thermal Resistance – °C/W

DC Conditions
1
d = 0.5

d = 0.2

d = 0.1
0.1
d = 0.05

d = 0.02

d = 0.01

0.01

Single Pulse

0.001
tc
tw
ID
0

0.0001
0.0001 0.001 0.01 0.1 1 10
tw – Pulse Duration – s

† Device mounted on FR4 printed-circuit board with no heat sink

NOTES: ZθA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc

Figure 12

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Copyright  2000, Texas Instruments Incorporated